1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2014 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg */ 23fb4d8502Sjsg 24fb4d8502Sjsg #ifndef __MXGPU_AI_H__ 25fb4d8502Sjsg #define __MXGPU_AI_H__ 26fb4d8502Sjsg 27fb4d8502Sjsg #define AI_MAILBOX_POLL_ACK_TIMEDOUT 500 285ca02815Sjsg #define AI_MAILBOX_POLL_MSG_TIMEDOUT 6000 291bb76ff1Sjsg #define AI_MAILBOX_POLL_FLR_TIMEDOUT 10000 305ca02815Sjsg #define AI_MAILBOX_POLL_MSG_REP_MAX 11 31fb4d8502Sjsg 32fb4d8502Sjsg enum idh_request { 33fb4d8502Sjsg IDH_REQ_GPU_INIT_ACCESS = 1, 34fb4d8502Sjsg IDH_REL_GPU_INIT_ACCESS, 35fb4d8502Sjsg IDH_REQ_GPU_FINI_ACCESS, 36fb4d8502Sjsg IDH_REL_GPU_FINI_ACCESS, 37fb4d8502Sjsg IDH_REQ_GPU_RESET_ACCESS, 381bb76ff1Sjsg IDH_REQ_GPU_INIT_DATA, 39fb4d8502Sjsg 40fb4d8502Sjsg IDH_LOG_VF_ERROR = 200, 415ca02815Sjsg IDH_READY_TO_RESET = 201, 42*f005ef32Sjsg IDH_RAS_POISON = 202, 43fb4d8502Sjsg }; 44fb4d8502Sjsg 45fb4d8502Sjsg enum idh_event { 46fb4d8502Sjsg IDH_CLR_MSG_BUF = 0, 47fb4d8502Sjsg IDH_READY_TO_ACCESS_GPU, 48fb4d8502Sjsg IDH_FLR_NOTIFICATION, 49fb4d8502Sjsg IDH_FLR_NOTIFICATION_CMPL, 50c349dbc7Sjsg IDH_SUCCESS, 51c349dbc7Sjsg IDH_FAIL, 52c349dbc7Sjsg IDH_QUERY_ALIVE, 531bb76ff1Sjsg IDH_REQ_GPU_INIT_DATA_READY, 54ad8b1aafSjsg 55ad8b1aafSjsg IDH_TEXT_MESSAGE = 255, 56fb4d8502Sjsg }; 57fb4d8502Sjsg 58fb4d8502Sjsg extern const struct amdgpu_virt_ops xgpu_ai_virt_ops; 59fb4d8502Sjsg 60fb4d8502Sjsg void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev); 61fb4d8502Sjsg int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev); 62fb4d8502Sjsg int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev); 63fb4d8502Sjsg void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev); 64fb4d8502Sjsg 65fb4d8502Sjsg #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 66fb4d8502Sjsg #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1 67fb4d8502Sjsg 68fb4d8502Sjsg #endif 69