1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "amdgpu_pm.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_common.h" 32 33 #include "vcn/vcn_1_0_offset.h" 34 #include "vcn/vcn_1_0_sh_mask.h" 35 #include "hdp/hdp_4_0_offset.h" 36 #include "mmhub/mmhub_9_1_offset.h" 37 #include "mmhub/mmhub_9_1_sh_mask.h" 38 39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 40 #include "jpeg_v1_0.h" 41 42 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab 43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1 44 #define mmUVD_REG_XX_MASK_1_0 0x05ac 45 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 46 47 static int vcn_v1_0_stop(struct amdgpu_device *adev); 48 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 53 int inst_idx, struct dpg_pause_state *new_state); 54 55 static void vcn_v1_0_idle_work_handler(struct work_struct *work); 56 57 /** 58 * vcn_v1_0_early_init - set function pointers 59 * 60 * @handle: amdgpu_device pointer 61 * 62 * Set ring and irq function pointers 63 */ 64 static int vcn_v1_0_early_init(void *handle) 65 { 66 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 67 68 adev->vcn.num_vcn_inst = 1; 69 adev->vcn.num_enc_rings = 2; 70 71 vcn_v1_0_set_dec_ring_funcs(adev); 72 vcn_v1_0_set_enc_ring_funcs(adev); 73 vcn_v1_0_set_irq_funcs(adev); 74 75 jpeg_v1_0_early_init(handle); 76 77 return 0; 78 } 79 80 /** 81 * vcn_v1_0_sw_init - sw init for VCN block 82 * 83 * @handle: amdgpu_device pointer 84 * 85 * Load firmware and sw initialization 86 */ 87 static int vcn_v1_0_sw_init(void *handle) 88 { 89 struct amdgpu_ring *ring; 90 int i, r; 91 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 92 93 /* VCN DEC TRAP */ 94 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 95 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 96 if (r) 97 return r; 98 99 /* VCN ENC TRAP */ 100 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 101 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 102 &adev->vcn.inst->irq); 103 if (r) 104 return r; 105 } 106 107 r = amdgpu_vcn_sw_init(adev); 108 if (r) 109 return r; 110 111 /* Override the work func */ 112 #ifdef __linux__ 113 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; 114 #else 115 task_set(&adev->vcn.idle_work.work.task, 116 (void (*)(void *))vcn_v1_0_idle_work_handler, 117 &adev->vcn.idle_work.work); 118 #endif 119 120 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 121 const struct common_firmware_header *hdr; 122 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 123 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 124 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 125 adev->firmware.fw_size += 126 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 127 DRM_INFO("PSP loading VCN firmware\n"); 128 } 129 130 r = amdgpu_vcn_resume(adev); 131 if (r) 132 return r; 133 134 ring = &adev->vcn.inst->ring_dec; 135 snprintf(ring->name, sizeof(ring->name), "vcn_dec"); 136 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 137 if (r) 138 return r; 139 140 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 141 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 142 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 143 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 144 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 145 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 146 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 147 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 148 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 149 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 150 151 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 152 ring = &adev->vcn.inst->ring_enc[i]; 153 snprintf(ring->name, sizeof(ring->name), "vcn_enc%d", i); 154 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 155 if (r) 156 return r; 157 } 158 159 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 160 161 r = jpeg_v1_0_sw_init(handle); 162 163 return r; 164 } 165 166 /** 167 * vcn_v1_0_sw_fini - sw fini for VCN block 168 * 169 * @handle: amdgpu_device pointer 170 * 171 * VCN suspend and free up sw allocation 172 */ 173 static int vcn_v1_0_sw_fini(void *handle) 174 { 175 int r; 176 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 177 178 r = amdgpu_vcn_suspend(adev); 179 if (r) 180 return r; 181 182 jpeg_v1_0_sw_fini(handle); 183 184 r = amdgpu_vcn_sw_fini(adev); 185 186 return r; 187 } 188 189 /** 190 * vcn_v1_0_hw_init - start and test VCN block 191 * 192 * @handle: amdgpu_device pointer 193 * 194 * Initialize the hardware, boot up the VCPU and do some testing 195 */ 196 static int vcn_v1_0_hw_init(void *handle) 197 { 198 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 199 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 200 int i, r; 201 202 r = amdgpu_ring_test_helper(ring); 203 if (r) 204 goto done; 205 206 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 207 ring = &adev->vcn.inst->ring_enc[i]; 208 r = amdgpu_ring_test_helper(ring); 209 if (r) 210 goto done; 211 } 212 213 ring = &adev->jpeg.inst->ring_dec; 214 r = amdgpu_ring_test_helper(ring); 215 if (r) 216 goto done; 217 218 done: 219 if (!r) 220 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 221 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 222 223 return r; 224 } 225 226 /** 227 * vcn_v1_0_hw_fini - stop the hardware block 228 * 229 * @handle: amdgpu_device pointer 230 * 231 * Stop the VCN block, mark ring as not ready any more 232 */ 233 static int vcn_v1_0_hw_fini(void *handle) 234 { 235 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 236 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 237 238 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 239 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) 240 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 241 242 ring->sched.ready = false; 243 244 return 0; 245 } 246 247 /** 248 * vcn_v1_0_suspend - suspend VCN block 249 * 250 * @handle: amdgpu_device pointer 251 * 252 * HW fini and suspend VCN block 253 */ 254 static int vcn_v1_0_suspend(void *handle) 255 { 256 int r; 257 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 258 259 r = vcn_v1_0_hw_fini(adev); 260 if (r) 261 return r; 262 263 r = amdgpu_vcn_suspend(adev); 264 265 return r; 266 } 267 268 /** 269 * vcn_v1_0_resume - resume VCN block 270 * 271 * @handle: amdgpu_device pointer 272 * 273 * Resume firmware and hw init VCN block 274 */ 275 static int vcn_v1_0_resume(void *handle) 276 { 277 int r; 278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 279 280 r = amdgpu_vcn_resume(adev); 281 if (r) 282 return r; 283 284 r = vcn_v1_0_hw_init(adev); 285 286 return r; 287 } 288 289 /** 290 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 291 * 292 * @adev: amdgpu_device pointer 293 * 294 * Let the VCN memory controller know it's offsets 295 */ 296 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 297 { 298 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 299 uint32_t offset; 300 301 /* cache window 0: fw */ 302 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 303 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 304 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 305 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 306 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 307 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 308 offset = 0; 309 } else { 310 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 311 lower_32_bits(adev->vcn.inst->gpu_addr)); 312 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 313 upper_32_bits(adev->vcn.inst->gpu_addr)); 314 offset = size; 315 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 316 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 317 } 318 319 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 320 321 /* cache window 1: stack */ 322 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 323 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 324 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 325 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 326 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 327 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 328 329 /* cache window 2: context */ 330 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 331 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 332 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 333 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 334 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 335 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 336 337 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 338 adev->gfx.config.gb_addr_config); 339 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 340 adev->gfx.config.gb_addr_config); 341 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 342 adev->gfx.config.gb_addr_config); 343 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 344 adev->gfx.config.gb_addr_config); 345 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 346 adev->gfx.config.gb_addr_config); 347 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 348 adev->gfx.config.gb_addr_config); 349 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 350 adev->gfx.config.gb_addr_config); 351 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 352 adev->gfx.config.gb_addr_config); 353 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 354 adev->gfx.config.gb_addr_config); 355 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 356 adev->gfx.config.gb_addr_config); 357 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 358 adev->gfx.config.gb_addr_config); 359 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 360 adev->gfx.config.gb_addr_config); 361 } 362 363 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 364 { 365 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 366 uint32_t offset; 367 368 /* cache window 0: fw */ 369 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 370 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 371 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 372 0xFFFFFFFF, 0); 373 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 374 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 375 0xFFFFFFFF, 0); 376 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 377 0xFFFFFFFF, 0); 378 offset = 0; 379 } else { 380 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 381 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 382 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 383 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 384 offset = size; 385 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 386 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 387 } 388 389 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 390 391 /* cache window 1: stack */ 392 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 393 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 394 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 395 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 396 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 397 0xFFFFFFFF, 0); 398 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 399 0xFFFFFFFF, 0); 400 401 /* cache window 2: context */ 402 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 403 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 404 0xFFFFFFFF, 0); 405 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 406 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 407 0xFFFFFFFF, 0); 408 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 409 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 410 0xFFFFFFFF, 0); 411 412 /* VCN global tiling registers */ 413 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 414 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 415 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 416 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 417 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 418 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 419 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 420 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 421 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 422 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 423 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 424 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 425 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 426 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 427 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 428 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 429 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 430 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 431 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 432 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 433 } 434 435 /** 436 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 437 * 438 * @adev: amdgpu_device pointer 439 * @sw: enable SW clock gating 440 * 441 * Disable clock gating for VCN block 442 */ 443 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 444 { 445 uint32_t data; 446 447 /* JPEG disable CGC */ 448 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 449 450 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 451 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 452 else 453 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 454 455 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 456 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 457 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 458 459 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 460 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 461 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 462 463 /* UVD disable CGC */ 464 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 465 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 466 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 467 else 468 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 469 470 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 471 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 472 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 473 474 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 475 data &= ~(UVD_CGC_GATE__SYS_MASK 476 | UVD_CGC_GATE__UDEC_MASK 477 | UVD_CGC_GATE__MPEG2_MASK 478 | UVD_CGC_GATE__REGS_MASK 479 | UVD_CGC_GATE__RBC_MASK 480 | UVD_CGC_GATE__LMI_MC_MASK 481 | UVD_CGC_GATE__LMI_UMC_MASK 482 | UVD_CGC_GATE__IDCT_MASK 483 | UVD_CGC_GATE__MPRD_MASK 484 | UVD_CGC_GATE__MPC_MASK 485 | UVD_CGC_GATE__LBSI_MASK 486 | UVD_CGC_GATE__LRBBM_MASK 487 | UVD_CGC_GATE__UDEC_RE_MASK 488 | UVD_CGC_GATE__UDEC_CM_MASK 489 | UVD_CGC_GATE__UDEC_IT_MASK 490 | UVD_CGC_GATE__UDEC_DB_MASK 491 | UVD_CGC_GATE__UDEC_MP_MASK 492 | UVD_CGC_GATE__WCB_MASK 493 | UVD_CGC_GATE__VCPU_MASK 494 | UVD_CGC_GATE__SCPU_MASK); 495 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 496 497 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 498 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 499 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 500 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 501 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 502 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 503 | UVD_CGC_CTRL__SYS_MODE_MASK 504 | UVD_CGC_CTRL__UDEC_MODE_MASK 505 | UVD_CGC_CTRL__MPEG2_MODE_MASK 506 | UVD_CGC_CTRL__REGS_MODE_MASK 507 | UVD_CGC_CTRL__RBC_MODE_MASK 508 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 509 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 510 | UVD_CGC_CTRL__IDCT_MODE_MASK 511 | UVD_CGC_CTRL__MPRD_MODE_MASK 512 | UVD_CGC_CTRL__MPC_MODE_MASK 513 | UVD_CGC_CTRL__LBSI_MODE_MASK 514 | UVD_CGC_CTRL__LRBBM_MODE_MASK 515 | UVD_CGC_CTRL__WCB_MODE_MASK 516 | UVD_CGC_CTRL__VCPU_MODE_MASK 517 | UVD_CGC_CTRL__SCPU_MODE_MASK); 518 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 519 520 /* turn on */ 521 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 522 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 523 | UVD_SUVD_CGC_GATE__SIT_MASK 524 | UVD_SUVD_CGC_GATE__SMP_MASK 525 | UVD_SUVD_CGC_GATE__SCM_MASK 526 | UVD_SUVD_CGC_GATE__SDB_MASK 527 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 528 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 529 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 530 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 531 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 532 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 533 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 534 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 535 | UVD_SUVD_CGC_GATE__SCLR_MASK 536 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 537 | UVD_SUVD_CGC_GATE__ENT_MASK 538 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 539 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 540 | UVD_SUVD_CGC_GATE__SITE_MASK 541 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 542 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 543 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 544 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 545 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 546 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 547 548 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 549 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 550 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 551 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 552 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 553 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 554 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 555 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 556 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 557 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 558 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 559 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 560 } 561 562 /** 563 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 564 * 565 * @adev: amdgpu_device pointer 566 * @sw: enable SW clock gating 567 * 568 * Enable clock gating for VCN block 569 */ 570 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 571 { 572 uint32_t data = 0; 573 574 /* enable JPEG CGC */ 575 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 576 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 577 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 578 else 579 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 580 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 581 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 582 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 583 584 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 585 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 586 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 587 588 /* enable UVD CGC */ 589 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 590 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 591 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 592 else 593 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 594 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 595 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 596 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 597 598 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 599 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 600 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 601 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 602 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 603 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 604 | UVD_CGC_CTRL__SYS_MODE_MASK 605 | UVD_CGC_CTRL__UDEC_MODE_MASK 606 | UVD_CGC_CTRL__MPEG2_MODE_MASK 607 | UVD_CGC_CTRL__REGS_MODE_MASK 608 | UVD_CGC_CTRL__RBC_MODE_MASK 609 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 610 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 611 | UVD_CGC_CTRL__IDCT_MODE_MASK 612 | UVD_CGC_CTRL__MPRD_MODE_MASK 613 | UVD_CGC_CTRL__MPC_MODE_MASK 614 | UVD_CGC_CTRL__LBSI_MODE_MASK 615 | UVD_CGC_CTRL__LRBBM_MODE_MASK 616 | UVD_CGC_CTRL__WCB_MODE_MASK 617 | UVD_CGC_CTRL__VCPU_MODE_MASK 618 | UVD_CGC_CTRL__SCPU_MODE_MASK); 619 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 620 621 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 622 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 623 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 624 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 625 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 626 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 627 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 628 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 629 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 630 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 631 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 632 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 633 } 634 635 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 636 { 637 uint32_t reg_data = 0; 638 639 /* disable JPEG CGC */ 640 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 641 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 642 else 643 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 644 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 645 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 646 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 647 648 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 649 650 /* enable sw clock gating control */ 651 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 652 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 653 else 654 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 655 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 656 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 657 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 658 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 659 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 660 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 661 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 662 UVD_CGC_CTRL__SYS_MODE_MASK | 663 UVD_CGC_CTRL__UDEC_MODE_MASK | 664 UVD_CGC_CTRL__MPEG2_MODE_MASK | 665 UVD_CGC_CTRL__REGS_MODE_MASK | 666 UVD_CGC_CTRL__RBC_MODE_MASK | 667 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 668 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 669 UVD_CGC_CTRL__IDCT_MODE_MASK | 670 UVD_CGC_CTRL__MPRD_MODE_MASK | 671 UVD_CGC_CTRL__MPC_MODE_MASK | 672 UVD_CGC_CTRL__LBSI_MODE_MASK | 673 UVD_CGC_CTRL__LRBBM_MODE_MASK | 674 UVD_CGC_CTRL__WCB_MODE_MASK | 675 UVD_CGC_CTRL__VCPU_MODE_MASK | 676 UVD_CGC_CTRL__SCPU_MODE_MASK); 677 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 678 679 /* turn off clock gating */ 680 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 681 682 /* turn on SUVD clock gating */ 683 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 684 685 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 686 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 687 } 688 689 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 690 { 691 uint32_t data = 0; 692 int ret; 693 694 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 695 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 696 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 697 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 698 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 699 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 700 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 701 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 702 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 703 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 704 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 705 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 706 707 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 708 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); 709 } else { 710 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 711 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 712 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 713 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 714 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 715 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 716 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 717 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 718 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 719 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 720 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 721 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 722 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); 723 } 724 725 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 726 727 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 728 data &= ~0x103; 729 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 730 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 731 732 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 733 } 734 735 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 736 { 737 uint32_t data = 0; 738 int ret; 739 740 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 741 /* Before power off, this indicator has to be turned on */ 742 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 743 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 744 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 745 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 746 747 748 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 749 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 750 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 751 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 752 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 753 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 754 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 755 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 756 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 757 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 758 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 759 760 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 761 762 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 763 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 764 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 765 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 766 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 767 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 768 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 769 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 770 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 771 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 772 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 773 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); 774 } 775 } 776 777 /** 778 * vcn_v1_0_start - start VCN block 779 * 780 * @adev: amdgpu_device pointer 781 * 782 * Setup and start the VCN block 783 */ 784 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 785 { 786 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 787 uint32_t rb_bufsz, tmp; 788 uint32_t lmi_swap_cntl; 789 int i, j, r; 790 791 /* disable byte swapping */ 792 lmi_swap_cntl = 0; 793 794 vcn_1_0_disable_static_power_gating(adev); 795 796 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 797 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 798 799 /* disable clock gating */ 800 vcn_v1_0_disable_clock_gating(adev); 801 802 /* disable interupt */ 803 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 804 ~UVD_MASTINT_EN__VCPU_EN_MASK); 805 806 /* initialize VCN memory controller */ 807 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 808 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 809 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 810 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 811 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 812 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 813 814 #ifdef __BIG_ENDIAN 815 /* swap (8 in 32) RB and IB */ 816 lmi_swap_cntl = 0xa; 817 #endif 818 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 819 820 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 821 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 822 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 823 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 824 825 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 826 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 827 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 828 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 829 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 830 831 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 832 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 833 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 834 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 835 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 836 837 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 838 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 839 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 840 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 841 842 vcn_v1_0_mc_resume_spg_mode(adev); 843 844 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10); 845 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0, 846 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3); 847 848 /* enable VCPU clock */ 849 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 850 851 /* boot up the VCPU */ 852 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 853 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 854 855 /* enable UMC */ 856 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 857 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 858 859 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 860 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 861 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 862 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 863 864 for (i = 0; i < 10; ++i) { 865 uint32_t status; 866 867 for (j = 0; j < 100; ++j) { 868 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 869 if (status & UVD_STATUS__IDLE) 870 break; 871 mdelay(10); 872 } 873 r = 0; 874 if (status & UVD_STATUS__IDLE) 875 break; 876 877 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 878 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 879 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 880 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 881 mdelay(10); 882 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 883 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 884 mdelay(10); 885 r = -1; 886 } 887 888 if (r) { 889 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 890 return r; 891 } 892 /* enable master interrupt */ 893 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 894 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 895 896 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 897 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 898 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 899 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 900 901 /* clear the busy bit of UVD_STATUS */ 902 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 903 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 904 905 /* force RBC into idle state */ 906 rb_bufsz = order_base_2(ring->ring_size); 907 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 908 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 909 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 910 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 911 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 912 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 913 914 /* set the write pointer delay */ 915 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 916 917 /* set the wb address */ 918 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 919 (upper_32_bits(ring->gpu_addr) >> 2)); 920 921 /* programm the RB_BASE for ring buffer */ 922 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 923 lower_32_bits(ring->gpu_addr)); 924 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 925 upper_32_bits(ring->gpu_addr)); 926 927 /* Initialize the ring buffer's read and write pointers */ 928 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 929 930 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 931 932 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 933 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 934 lower_32_bits(ring->wptr)); 935 936 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 937 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 938 939 ring = &adev->vcn.inst->ring_enc[0]; 940 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 941 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 942 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 943 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 944 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 945 946 ring = &adev->vcn.inst->ring_enc[1]; 947 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 948 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 949 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 950 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 951 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 952 953 jpeg_v1_0_start(adev, 0); 954 955 return 0; 956 } 957 958 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 959 { 960 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 961 uint32_t rb_bufsz, tmp; 962 uint32_t lmi_swap_cntl; 963 964 /* disable byte swapping */ 965 lmi_swap_cntl = 0; 966 967 vcn_1_0_enable_static_power_gating(adev); 968 969 /* enable dynamic power gating mode */ 970 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 971 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 972 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 973 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 974 975 /* enable clock gating */ 976 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 977 978 /* enable VCPU clock */ 979 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 980 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 981 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 982 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 983 984 /* disable interupt */ 985 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 986 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 987 988 /* initialize VCN memory controller */ 989 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 990 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 991 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 992 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 993 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 994 UVD_LMI_CTRL__REQ_MODE_MASK | 995 UVD_LMI_CTRL__CRC_RESET_MASK | 996 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 997 0x00100000L, 0xFFFFFFFF, 0); 998 999 #ifdef __BIG_ENDIAN 1000 /* swap (8 in 32) RB and IB */ 1001 lmi_swap_cntl = 0xa; 1002 #endif 1003 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1004 1005 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, 1006 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1007 1008 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 1009 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1010 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1011 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1012 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1013 1014 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 1015 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1016 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1017 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1018 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1019 1020 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 1021 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1022 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1023 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1024 1025 vcn_v1_0_mc_resume_dpg_mode(adev); 1026 1027 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1028 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1029 1030 /* boot up the VCPU */ 1031 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1032 1033 /* enable UMC */ 1034 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 1035 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1036 0xFFFFFFFF, 0); 1037 1038 /* enable master interrupt */ 1039 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 1040 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1041 1042 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1043 /* setup mmUVD_LMI_CTRL */ 1044 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 1045 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1046 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1047 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1048 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1049 UVD_LMI_CTRL__REQ_MODE_MASK | 1050 UVD_LMI_CTRL__CRC_RESET_MASK | 1051 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1052 0x00100000L, 0xFFFFFFFF, 1); 1053 1054 tmp = adev->gfx.config.gb_addr_config; 1055 /* setup VCN global tiling registers */ 1056 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1057 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1058 1059 /* enable System Interrupt for JRBC */ 1060 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN, 1061 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1062 1063 /* force RBC into idle state */ 1064 rb_bufsz = order_base_2(ring->ring_size); 1065 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1066 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1068 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1069 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1070 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1071 1072 /* set the write pointer delay */ 1073 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1074 1075 /* set the wb address */ 1076 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1077 (upper_32_bits(ring->gpu_addr) >> 2)); 1078 1079 /* programm the RB_BASE for ring buffer */ 1080 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1081 lower_32_bits(ring->gpu_addr)); 1082 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1083 upper_32_bits(ring->gpu_addr)); 1084 1085 /* Initialize the ring buffer's read and write pointers */ 1086 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1087 1088 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1089 1090 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1091 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1092 lower_32_bits(ring->wptr)); 1093 1094 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1095 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1096 1097 jpeg_v1_0_start(adev, 1); 1098 1099 return 0; 1100 } 1101 1102 static int vcn_v1_0_start(struct amdgpu_device *adev) 1103 { 1104 int r; 1105 1106 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1107 r = vcn_v1_0_start_dpg_mode(adev); 1108 else 1109 r = vcn_v1_0_start_spg_mode(adev); 1110 return r; 1111 } 1112 1113 /** 1114 * vcn_v1_0_stop - stop VCN block 1115 * 1116 * @adev: amdgpu_device pointer 1117 * 1118 * stop the VCN block 1119 */ 1120 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1121 { 1122 int ret_code, tmp; 1123 1124 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); 1125 1126 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1127 UVD_LMI_STATUS__READ_CLEAN_MASK | 1128 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1129 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1130 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1131 1132 /* put VCPU into reset */ 1133 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1134 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1135 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1136 1137 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1138 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1139 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1140 1141 /* disable VCPU clock */ 1142 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1143 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1144 1145 /* reset LMI UMC/LMI */ 1146 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1147 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1148 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1149 1150 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1151 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1152 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1153 1154 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1155 1156 vcn_v1_0_enable_clock_gating(adev); 1157 vcn_1_0_enable_static_power_gating(adev); 1158 return 0; 1159 } 1160 1161 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1162 { 1163 int ret_code = 0; 1164 uint32_t tmp; 1165 1166 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1167 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1168 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1169 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1170 1171 /* wait for read ptr to be equal to write ptr */ 1172 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1173 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1174 1175 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1176 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); 1177 1178 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1179 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1180 1181 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1182 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1183 1184 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1185 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1186 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1187 1188 /* disable dynamic power gating mode */ 1189 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1190 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1191 1192 return 0; 1193 } 1194 1195 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1196 { 1197 int r; 1198 1199 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1200 r = vcn_v1_0_stop_dpg_mode(adev); 1201 else 1202 r = vcn_v1_0_stop_spg_mode(adev); 1203 1204 return r; 1205 } 1206 1207 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1208 int inst_idx, struct dpg_pause_state *new_state) 1209 { 1210 int ret_code; 1211 uint32_t reg_data = 0; 1212 uint32_t reg_data2 = 0; 1213 struct amdgpu_ring *ring; 1214 1215 /* pause/unpause if state is changed */ 1216 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1217 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1218 adev->vcn.inst[inst_idx].pause_state.fw_based, 1219 adev->vcn.inst[inst_idx].pause_state.jpeg, 1220 new_state->fw_based, new_state->jpeg); 1221 1222 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1223 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1224 1225 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1226 ret_code = 0; 1227 1228 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1229 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1230 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1231 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1232 1233 if (!ret_code) { 1234 /* pause DPG non-jpeg */ 1235 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1236 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1237 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1238 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1239 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); 1240 1241 /* Restore */ 1242 ring = &adev->vcn.inst->ring_enc[0]; 1243 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1245 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1247 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1248 1249 ring = &adev->vcn.inst->ring_enc[1]; 1250 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1251 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1252 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1253 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1254 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1255 1256 ring = &adev->vcn.inst->ring_dec; 1257 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1258 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1259 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1260 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1261 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1262 } 1263 } else { 1264 /* unpause dpg non-jpeg, no need to wait */ 1265 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1266 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1267 } 1268 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1269 } 1270 1271 /* pause/unpause if state is changed */ 1272 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { 1273 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1274 adev->vcn.inst[inst_idx].pause_state.fw_based, 1275 adev->vcn.inst[inst_idx].pause_state.jpeg, 1276 new_state->fw_based, new_state->jpeg); 1277 1278 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1279 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1280 1281 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1282 ret_code = 0; 1283 1284 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1285 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1286 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1287 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1288 1289 if (!ret_code) { 1290 /* Make sure JPRG Snoop is disabled before sending the pause */ 1291 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1292 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1293 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1294 1295 /* pause DPG jpeg */ 1296 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1297 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1298 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1299 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1300 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); 1301 1302 /* Restore */ 1303 ring = &adev->jpeg.inst->ring_dec; 1304 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1305 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1306 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1307 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1308 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1309 lower_32_bits(ring->gpu_addr)); 1310 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1311 upper_32_bits(ring->gpu_addr)); 1312 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1313 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1314 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1315 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1316 1317 ring = &adev->vcn.inst->ring_dec; 1318 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1319 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1320 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1321 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1322 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1323 } 1324 } else { 1325 /* unpause dpg jpeg, no need to wait */ 1326 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1327 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1328 } 1329 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; 1330 } 1331 1332 return 0; 1333 } 1334 1335 static bool vcn_v1_0_is_idle(void *handle) 1336 { 1337 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1338 1339 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1340 } 1341 1342 static int vcn_v1_0_wait_for_idle(void *handle) 1343 { 1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1345 int ret = 0; 1346 1347 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1348 UVD_STATUS__IDLE, ret); 1349 1350 return ret; 1351 } 1352 1353 static int vcn_v1_0_set_clockgating_state(void *handle, 1354 enum amd_clockgating_state state) 1355 { 1356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1357 bool enable = (state == AMD_CG_STATE_GATE); 1358 1359 if (enable) { 1360 /* wait for STATUS to clear */ 1361 if (!vcn_v1_0_is_idle(handle)) 1362 return -EBUSY; 1363 vcn_v1_0_enable_clock_gating(adev); 1364 } else { 1365 /* disable HW gating and enable Sw gating */ 1366 vcn_v1_0_disable_clock_gating(adev); 1367 } 1368 return 0; 1369 } 1370 1371 /** 1372 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1373 * 1374 * @ring: amdgpu_ring pointer 1375 * 1376 * Returns the current hardware read pointer 1377 */ 1378 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1379 { 1380 struct amdgpu_device *adev = ring->adev; 1381 1382 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1383 } 1384 1385 /** 1386 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1387 * 1388 * @ring: amdgpu_ring pointer 1389 * 1390 * Returns the current hardware write pointer 1391 */ 1392 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1393 { 1394 struct amdgpu_device *adev = ring->adev; 1395 1396 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1397 } 1398 1399 /** 1400 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1401 * 1402 * @ring: amdgpu_ring pointer 1403 * 1404 * Commits the write pointer to the hardware 1405 */ 1406 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1407 { 1408 struct amdgpu_device *adev = ring->adev; 1409 1410 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1411 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1412 lower_32_bits(ring->wptr) | 0x80000000); 1413 1414 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1415 } 1416 1417 /** 1418 * vcn_v1_0_dec_ring_insert_start - insert a start command 1419 * 1420 * @ring: amdgpu_ring pointer 1421 * 1422 * Write a start command to the ring. 1423 */ 1424 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1425 { 1426 struct amdgpu_device *adev = ring->adev; 1427 1428 amdgpu_ring_write(ring, 1429 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1430 amdgpu_ring_write(ring, 0); 1431 amdgpu_ring_write(ring, 1432 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1433 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1434 } 1435 1436 /** 1437 * vcn_v1_0_dec_ring_insert_end - insert a end command 1438 * 1439 * @ring: amdgpu_ring pointer 1440 * 1441 * Write a end command to the ring. 1442 */ 1443 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1444 { 1445 struct amdgpu_device *adev = ring->adev; 1446 1447 amdgpu_ring_write(ring, 1448 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1449 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1450 } 1451 1452 /** 1453 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1454 * 1455 * @ring: amdgpu_ring pointer 1456 * @fence: fence to emit 1457 * 1458 * Write a fence and a trap command to the ring. 1459 */ 1460 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1461 unsigned flags) 1462 { 1463 struct amdgpu_device *adev = ring->adev; 1464 1465 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1466 1467 amdgpu_ring_write(ring, 1468 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1469 amdgpu_ring_write(ring, seq); 1470 amdgpu_ring_write(ring, 1471 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1472 amdgpu_ring_write(ring, addr & 0xffffffff); 1473 amdgpu_ring_write(ring, 1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1475 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1476 amdgpu_ring_write(ring, 1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1478 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1479 1480 amdgpu_ring_write(ring, 1481 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1482 amdgpu_ring_write(ring, 0); 1483 amdgpu_ring_write(ring, 1484 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1485 amdgpu_ring_write(ring, 0); 1486 amdgpu_ring_write(ring, 1487 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1488 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1489 } 1490 1491 /** 1492 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1493 * 1494 * @ring: amdgpu_ring pointer 1495 * @ib: indirect buffer to execute 1496 * 1497 * Write ring commands to execute the indirect buffer 1498 */ 1499 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1500 struct amdgpu_job *job, 1501 struct amdgpu_ib *ib, 1502 uint32_t flags) 1503 { 1504 struct amdgpu_device *adev = ring->adev; 1505 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1506 1507 amdgpu_ring_write(ring, 1508 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1509 amdgpu_ring_write(ring, vmid); 1510 1511 amdgpu_ring_write(ring, 1512 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1513 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1514 amdgpu_ring_write(ring, 1515 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1516 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1517 amdgpu_ring_write(ring, 1518 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1519 amdgpu_ring_write(ring, ib->length_dw); 1520 } 1521 1522 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1523 uint32_t reg, uint32_t val, 1524 uint32_t mask) 1525 { 1526 struct amdgpu_device *adev = ring->adev; 1527 1528 amdgpu_ring_write(ring, 1529 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1530 amdgpu_ring_write(ring, reg << 2); 1531 amdgpu_ring_write(ring, 1532 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1533 amdgpu_ring_write(ring, val); 1534 amdgpu_ring_write(ring, 1535 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1536 amdgpu_ring_write(ring, mask); 1537 amdgpu_ring_write(ring, 1538 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1539 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1540 } 1541 1542 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1543 unsigned vmid, uint64_t pd_addr) 1544 { 1545 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1546 uint32_t data0, data1, mask; 1547 1548 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1549 1550 /* wait for register write */ 1551 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1552 data1 = lower_32_bits(pd_addr); 1553 mask = 0xffffffff; 1554 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1555 } 1556 1557 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1558 uint32_t reg, uint32_t val) 1559 { 1560 struct amdgpu_device *adev = ring->adev; 1561 1562 amdgpu_ring_write(ring, 1563 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1564 amdgpu_ring_write(ring, reg << 2); 1565 amdgpu_ring_write(ring, 1566 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1567 amdgpu_ring_write(ring, val); 1568 amdgpu_ring_write(ring, 1569 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1570 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1571 } 1572 1573 /** 1574 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1575 * 1576 * @ring: amdgpu_ring pointer 1577 * 1578 * Returns the current hardware enc read pointer 1579 */ 1580 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1581 { 1582 struct amdgpu_device *adev = ring->adev; 1583 1584 if (ring == &adev->vcn.inst->ring_enc[0]) 1585 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1586 else 1587 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1588 } 1589 1590 /** 1591 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1592 * 1593 * @ring: amdgpu_ring pointer 1594 * 1595 * Returns the current hardware enc write pointer 1596 */ 1597 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1598 { 1599 struct amdgpu_device *adev = ring->adev; 1600 1601 if (ring == &adev->vcn.inst->ring_enc[0]) 1602 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1603 else 1604 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1605 } 1606 1607 /** 1608 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1609 * 1610 * @ring: amdgpu_ring pointer 1611 * 1612 * Commits the enc write pointer to the hardware 1613 */ 1614 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1615 { 1616 struct amdgpu_device *adev = ring->adev; 1617 1618 if (ring == &adev->vcn.inst->ring_enc[0]) 1619 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1620 lower_32_bits(ring->wptr)); 1621 else 1622 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1623 lower_32_bits(ring->wptr)); 1624 } 1625 1626 /** 1627 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1628 * 1629 * @ring: amdgpu_ring pointer 1630 * @fence: fence to emit 1631 * 1632 * Write enc a fence and a trap command to the ring. 1633 */ 1634 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1635 u64 seq, unsigned flags) 1636 { 1637 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1638 1639 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1640 amdgpu_ring_write(ring, addr); 1641 amdgpu_ring_write(ring, upper_32_bits(addr)); 1642 amdgpu_ring_write(ring, seq); 1643 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1644 } 1645 1646 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1647 { 1648 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1649 } 1650 1651 /** 1652 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1653 * 1654 * @ring: amdgpu_ring pointer 1655 * @ib: indirect buffer to execute 1656 * 1657 * Write enc ring commands to execute the indirect buffer 1658 */ 1659 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1660 struct amdgpu_job *job, 1661 struct amdgpu_ib *ib, 1662 uint32_t flags) 1663 { 1664 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1665 1666 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1667 amdgpu_ring_write(ring, vmid); 1668 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1669 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1670 amdgpu_ring_write(ring, ib->length_dw); 1671 } 1672 1673 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1674 uint32_t reg, uint32_t val, 1675 uint32_t mask) 1676 { 1677 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1678 amdgpu_ring_write(ring, reg << 2); 1679 amdgpu_ring_write(ring, mask); 1680 amdgpu_ring_write(ring, val); 1681 } 1682 1683 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1684 unsigned int vmid, uint64_t pd_addr) 1685 { 1686 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1687 1688 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1689 1690 /* wait for reg writes */ 1691 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1692 lower_32_bits(pd_addr), 0xffffffff); 1693 } 1694 1695 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1696 uint32_t reg, uint32_t val) 1697 { 1698 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1699 amdgpu_ring_write(ring, reg << 2); 1700 amdgpu_ring_write(ring, val); 1701 } 1702 1703 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1704 struct amdgpu_irq_src *source, 1705 unsigned type, 1706 enum amdgpu_interrupt_state state) 1707 { 1708 return 0; 1709 } 1710 1711 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1712 struct amdgpu_irq_src *source, 1713 struct amdgpu_iv_entry *entry) 1714 { 1715 DRM_DEBUG("IH: VCN TRAP\n"); 1716 1717 switch (entry->src_id) { 1718 case 124: 1719 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1720 break; 1721 case 119: 1722 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1723 break; 1724 case 120: 1725 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1726 break; 1727 default: 1728 DRM_ERROR("Unhandled interrupt: %d %d\n", 1729 entry->src_id, entry->src_data[0]); 1730 break; 1731 } 1732 1733 return 0; 1734 } 1735 1736 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1737 { 1738 struct amdgpu_device *adev = ring->adev; 1739 int i; 1740 1741 WARN_ON(ring->wptr % 2 || count % 2); 1742 1743 for (i = 0; i < count / 2; i++) { 1744 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1745 amdgpu_ring_write(ring, 0); 1746 } 1747 } 1748 1749 static int vcn_v1_0_set_powergating_state(void *handle, 1750 enum amd_powergating_state state) 1751 { 1752 /* This doesn't actually powergate the VCN block. 1753 * That's done in the dpm code via the SMC. This 1754 * just re-inits the block as necessary. The actual 1755 * gating still happens in the dpm code. We should 1756 * revisit this when there is a cleaner line between 1757 * the smc and the hw blocks 1758 */ 1759 int ret; 1760 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1761 1762 if(state == adev->vcn.cur_state) 1763 return 0; 1764 1765 if (state == AMD_PG_STATE_GATE) 1766 ret = vcn_v1_0_stop(adev); 1767 else 1768 ret = vcn_v1_0_start(adev); 1769 1770 if(!ret) 1771 adev->vcn.cur_state = state; 1772 return ret; 1773 } 1774 1775 static void vcn_v1_0_idle_work_handler(struct work_struct *work) 1776 { 1777 struct amdgpu_device *adev = 1778 container_of(work, struct amdgpu_device, vcn.idle_work.work); 1779 unsigned int fences = 0, i; 1780 1781 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1782 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1783 1784 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1785 struct dpg_pause_state new_state; 1786 1787 if (fences) 1788 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1789 else 1790 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1791 1792 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1793 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1794 else 1795 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1796 1797 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1798 } 1799 1800 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec); 1801 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec); 1802 1803 if (fences == 0) { 1804 amdgpu_gfx_off_ctrl(adev, true); 1805 if (adev->pm.dpm_enabled) 1806 amdgpu_dpm_enable_uvd(adev, false); 1807 else 1808 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1809 AMD_PG_STATE_GATE); 1810 } else { 1811 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1812 } 1813 } 1814 1815 void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) 1816 { 1817 struct amdgpu_device *adev = ring->adev; 1818 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 1819 1820 if (set_clocks) { 1821 amdgpu_gfx_off_ctrl(adev, false); 1822 if (adev->pm.dpm_enabled) 1823 amdgpu_dpm_enable_uvd(adev, true); 1824 else 1825 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1826 AMD_PG_STATE_UNGATE); 1827 } 1828 1829 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1830 struct dpg_pause_state new_state; 1831 unsigned int fences = 0, i; 1832 1833 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1834 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1835 1836 if (fences) 1837 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1838 else 1839 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1840 1841 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1842 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1843 else 1844 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1845 1846 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 1847 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1848 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 1849 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1850 1851 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1852 } 1853 } 1854 1855 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1856 .name = "vcn_v1_0", 1857 .early_init = vcn_v1_0_early_init, 1858 .late_init = NULL, 1859 .sw_init = vcn_v1_0_sw_init, 1860 .sw_fini = vcn_v1_0_sw_fini, 1861 .hw_init = vcn_v1_0_hw_init, 1862 .hw_fini = vcn_v1_0_hw_fini, 1863 .suspend = vcn_v1_0_suspend, 1864 .resume = vcn_v1_0_resume, 1865 .is_idle = vcn_v1_0_is_idle, 1866 .wait_for_idle = vcn_v1_0_wait_for_idle, 1867 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1868 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1869 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1870 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1871 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1872 .set_powergating_state = vcn_v1_0_set_powergating_state, 1873 }; 1874 1875 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1876 .type = AMDGPU_RING_TYPE_VCN_DEC, 1877 .align_mask = 0xf, 1878 .support_64bit_ptrs = false, 1879 .no_user_fence = true, 1880 .vmhub = AMDGPU_MMHUB_0, 1881 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1882 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1883 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1884 .emit_frame_size = 1885 6 + 6 + /* hdp invalidate / flush */ 1886 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1887 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1888 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1889 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1890 6, 1891 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1892 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1893 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1894 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1895 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1896 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1897 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 1898 .insert_start = vcn_v1_0_dec_ring_insert_start, 1899 .insert_end = vcn_v1_0_dec_ring_insert_end, 1900 .pad_ib = amdgpu_ring_generic_pad_ib, 1901 .begin_use = vcn_v1_0_ring_begin_use, 1902 .end_use = amdgpu_vcn_ring_end_use, 1903 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 1904 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 1905 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1906 }; 1907 1908 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1909 .type = AMDGPU_RING_TYPE_VCN_ENC, 1910 .align_mask = 0x3f, 1911 .nop = VCN_ENC_CMD_NO_OP, 1912 .support_64bit_ptrs = false, 1913 .no_user_fence = true, 1914 .vmhub = AMDGPU_MMHUB_0, 1915 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1916 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1917 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1918 .emit_frame_size = 1919 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1920 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1921 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1922 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1923 1, /* vcn_v1_0_enc_ring_insert_end */ 1924 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1925 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1926 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1927 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1928 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1929 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1930 .insert_nop = amdgpu_ring_insert_nop, 1931 .insert_end = vcn_v1_0_enc_ring_insert_end, 1932 .pad_ib = amdgpu_ring_generic_pad_ib, 1933 .begin_use = vcn_v1_0_ring_begin_use, 1934 .end_use = amdgpu_vcn_ring_end_use, 1935 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 1936 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 1937 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1938 }; 1939 1940 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1941 { 1942 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1943 DRM_INFO("VCN decode is enabled in VM mode\n"); 1944 } 1945 1946 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1947 { 1948 int i; 1949 1950 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1951 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1952 1953 DRM_INFO("VCN encode is enabled in VM mode\n"); 1954 } 1955 1956 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1957 .set = vcn_v1_0_set_interrupt_state, 1958 .process = vcn_v1_0_process_interrupt, 1959 }; 1960 1961 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 1962 { 1963 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 1964 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 1965 } 1966 1967 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 1968 { 1969 .type = AMD_IP_BLOCK_TYPE_VCN, 1970 .major = 1, 1971 .minor = 0, 1972 .rev = 0, 1973 .funcs = &vcn_v1_0_ip_funcs, 1974 }; 1975