1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright (C) 2018 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included 12fb4d8502Sjsg * in all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15fb4d8502Sjsg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18fb4d8502Sjsg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19fb4d8502Sjsg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20fb4d8502Sjsg */ 21fb4d8502Sjsg #ifndef _soc15_hw_ip_HEADER 22fb4d8502Sjsg #define _soc15_hw_ip_HEADER 23fb4d8502Sjsg 24fb4d8502Sjsg // HW ID 25fb4d8502Sjsg #define MP1_HWID 1 26fb4d8502Sjsg #define MP2_HWID 2 27fb4d8502Sjsg #define THM_HWID 3 28fb4d8502Sjsg #define SMUIO_HWID 4 29fb4d8502Sjsg #define FUSE_HWID 5 30fb4d8502Sjsg #define CLKA_HWID 6 31fb4d8502Sjsg #define PWR_HWID 10 32fb4d8502Sjsg #define GC_HWID 11 33fb4d8502Sjsg #define UVD_HWID 12 34fb4d8502Sjsg #define VCN_HWID UVD_HWID 35fb4d8502Sjsg #define AUDIO_AZ_HWID 13 36fb4d8502Sjsg #define ACP_HWID 14 37fb4d8502Sjsg #define DCI_HWID 15 38fb4d8502Sjsg #define DMU_HWID 271 39fb4d8502Sjsg #define DCO_HWID 16 40fb4d8502Sjsg #define DIO_HWID 272 41fb4d8502Sjsg #define XDMA_HWID 17 42fb4d8502Sjsg #define DCEAZ_HWID 18 43fb4d8502Sjsg #define DAZ_HWID 274 44fb4d8502Sjsg #define SDPMUX_HWID 19 45fb4d8502Sjsg #define NTB_HWID 20 46fb4d8502Sjsg #define IOHC_HWID 24 47fb4d8502Sjsg #define L2IMU_HWID 28 48fb4d8502Sjsg #define VCE_HWID 32 49fb4d8502Sjsg #define MMHUB_HWID 34 50fb4d8502Sjsg #define ATHUB_HWID 35 51fb4d8502Sjsg #define DBGU_NBIO_HWID 36 52fb4d8502Sjsg #define DFX_HWID 37 53fb4d8502Sjsg #define DBGU0_HWID 38 54fb4d8502Sjsg #define DBGU1_HWID 39 55fb4d8502Sjsg #define OSSSYS_HWID 40 56fb4d8502Sjsg #define HDP_HWID 41 57fb4d8502Sjsg #define SDMA0_HWID 42 58fb4d8502Sjsg #define SDMA1_HWID 43 59fb4d8502Sjsg #define ISP_HWID 44 60fb4d8502Sjsg #define DBGU_IO_HWID 45 61fb4d8502Sjsg #define DF_HWID 46 62fb4d8502Sjsg #define CLKB_HWID 47 63fb4d8502Sjsg #define FCH_HWID 48 64fb4d8502Sjsg #define DFX_DAP_HWID 49 65fb4d8502Sjsg #define L1IMU_PCIE_HWID 50 66fb4d8502Sjsg #define L1IMU_NBIF_HWID 51 67fb4d8502Sjsg #define L1IMU_IOAGR_HWID 52 68fb4d8502Sjsg #define L1IMU3_HWID 53 69fb4d8502Sjsg #define L1IMU4_HWID 54 70fb4d8502Sjsg #define L1IMU5_HWID 55 71fb4d8502Sjsg #define L1IMU6_HWID 56 72fb4d8502Sjsg #define L1IMU7_HWID 57 73fb4d8502Sjsg #define L1IMU8_HWID 58 74fb4d8502Sjsg #define L1IMU9_HWID 59 75fb4d8502Sjsg #define L1IMU10_HWID 60 76fb4d8502Sjsg #define L1IMU11_HWID 61 77fb4d8502Sjsg #define L1IMU12_HWID 62 78fb4d8502Sjsg #define L1IMU13_HWID 63 79fb4d8502Sjsg #define L1IMU14_HWID 64 80fb4d8502Sjsg #define L1IMU15_HWID 65 81fb4d8502Sjsg #define WAFLC_HWID 66 82fb4d8502Sjsg #define FCH_USB_PD_HWID 67 83*1bb76ff1Sjsg #define SDMA2_HWID 68 84*1bb76ff1Sjsg #define SDMA3_HWID 69 85fb4d8502Sjsg #define PCIE_HWID 70 86fb4d8502Sjsg #define PCS_HWID 80 87fb4d8502Sjsg #define DDCL_HWID 89 88fb4d8502Sjsg #define SST_HWID 90 89*1bb76ff1Sjsg #define LSDMA_HWID 91 90fb4d8502Sjsg #define IOAGR_HWID 100 91fb4d8502Sjsg #define NBIF_HWID 108 92fb4d8502Sjsg #define IOAPIC_HWID 124 93fb4d8502Sjsg #define SYSTEMHUB_HWID 128 94fb4d8502Sjsg #define NTBCCP_HWID 144 95fb4d8502Sjsg #define UMC_HWID 150 96fb4d8502Sjsg #define SATA_HWID 168 97fb4d8502Sjsg #define USB_HWID 170 98fb4d8502Sjsg #define CCXSEC_HWID 176 99c349dbc7Sjsg #define XGMI_HWID 200 100fb4d8502Sjsg #define XGBE_HWID 216 101c349dbc7Sjsg #define MP0_HWID 255 102c349dbc7Sjsg 103fb4d8502Sjsg #endif 104