1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright (C) 2018 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included 12fb4d8502Sjsg * in all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15fb4d8502Sjsg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18fb4d8502Sjsg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19fb4d8502Sjsg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20fb4d8502Sjsg */ 21fb4d8502Sjsg #ifndef _vega20_ip_offset_HEADER 22fb4d8502Sjsg #define _vega20_ip_offset_HEADER 23fb4d8502Sjsg 24fb4d8502Sjsg #define MAX_INSTANCE 6 25fb4d8502Sjsg #define MAX_SEGMENT 6 26fb4d8502Sjsg 27fb4d8502Sjsg 28fb4d8502Sjsg struct IP_BASE_INSTANCE 29fb4d8502Sjsg { 30fb4d8502Sjsg unsigned int segment[MAX_SEGMENT]; 31fb4d8502Sjsg }; 32fb4d8502Sjsg 33fb4d8502Sjsg struct IP_BASE 34fb4d8502Sjsg { 35fb4d8502Sjsg struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 36*5ca02815Sjsg } __maybe_unused; 37fb4d8502Sjsg 38fb4d8502Sjsg 39fb4d8502Sjsg static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0, 0, 0, 0, 0 } }, 40fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 41fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 42fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 43fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 44fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 45fb4d8502Sjsg static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } }, 46fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 47fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 48fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 49fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 50fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 51fb4d8502Sjsg static const struct IP_BASE DCE_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } }, 52fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 53fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 54fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 55fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 56fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 57fb4d8502Sjsg static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } }, 58fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 59fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 60fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 61fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 62fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 63fb4d8502Sjsg static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } }, 64fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 65fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 66fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 67fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 68fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 69fb4d8502Sjsg static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } }, 70fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 71fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 72fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 73fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 74fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 75fb4d8502Sjsg static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } }, 76fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 77fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 78fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 79fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 80fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 81fb4d8502Sjsg static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, 82fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 83fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 84fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 85fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 86fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 87fb4d8502Sjsg static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, 88fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 89fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 90fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 91fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 92fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 93fb4d8502Sjsg static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, 94fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 95fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 96fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 97fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 98fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 99fb4d8502Sjsg static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, 100fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 101fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 102fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 103fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 104fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 105fb4d8502Sjsg static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } }, 106fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 107fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 108fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 109fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 110fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 111fb4d8502Sjsg static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0, 0, 0, 0, 0 } }, 112fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 113fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 114fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 115fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 116fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 117fb4d8502Sjsg static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0, 0, 0, 0, 0 } }, 118fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 119fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 120fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 121fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 122fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 123fb4d8502Sjsg static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, 124fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 125fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 126fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 127fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 128fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 129fb4d8502Sjsg static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, 130fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 131fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 132fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 133fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 134fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 135fb4d8502Sjsg static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } }, 136fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 137fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 138fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 139fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 140fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 141fb4d8502Sjsg static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } }, 142fb4d8502Sjsg { { 0, 0x00009000, 0, 0, 0, 0 } }, 143fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 144fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 145fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 146fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 147fb4d8502Sjsg /* Adjust VCE_BASE to make vce_4_1 use vce_4_0 offset header files*/ 148fb4d8502Sjsg static const struct IP_BASE VCE_BASE ={ { { { 0x00007E00/* 0x00008800 */, 0, 0, 0, 0, 0 } }, 149fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 150fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 151fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 152fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 153fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 154fb4d8502Sjsg static const struct IP_BASE XDMA_BASE ={ { { { 0x00003400, 0, 0, 0, 0, 0 } }, 155fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 156fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 157fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 158fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 159fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 160fb4d8502Sjsg static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } }, 161fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 162fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 163fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 164fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } }, 165fb4d8502Sjsg { { 0, 0, 0, 0, 0, 0 } } } }; 166fb4d8502Sjsg 167fb4d8502Sjsg 168fb4d8502Sjsg #define ATHUB_BASE__INST0_SEG0 0x00000C20 169fb4d8502Sjsg #define ATHUB_BASE__INST0_SEG1 0 170fb4d8502Sjsg #define ATHUB_BASE__INST0_SEG2 0 171fb4d8502Sjsg #define ATHUB_BASE__INST0_SEG3 0 172fb4d8502Sjsg #define ATHUB_BASE__INST0_SEG4 0 173fb4d8502Sjsg #define ATHUB_BASE__INST0_SEG5 0 174fb4d8502Sjsg 175fb4d8502Sjsg #define ATHUB_BASE__INST1_SEG0 0 176fb4d8502Sjsg #define ATHUB_BASE__INST1_SEG1 0 177fb4d8502Sjsg #define ATHUB_BASE__INST1_SEG2 0 178fb4d8502Sjsg #define ATHUB_BASE__INST1_SEG3 0 179fb4d8502Sjsg #define ATHUB_BASE__INST1_SEG4 0 180fb4d8502Sjsg #define ATHUB_BASE__INST1_SEG5 0 181fb4d8502Sjsg 182fb4d8502Sjsg #define ATHUB_BASE__INST2_SEG0 0 183fb4d8502Sjsg #define ATHUB_BASE__INST2_SEG1 0 184fb4d8502Sjsg #define ATHUB_BASE__INST2_SEG2 0 185fb4d8502Sjsg #define ATHUB_BASE__INST2_SEG3 0 186fb4d8502Sjsg #define ATHUB_BASE__INST2_SEG4 0 187fb4d8502Sjsg #define ATHUB_BASE__INST2_SEG5 0 188fb4d8502Sjsg 189fb4d8502Sjsg #define ATHUB_BASE__INST3_SEG0 0 190fb4d8502Sjsg #define ATHUB_BASE__INST3_SEG1 0 191fb4d8502Sjsg #define ATHUB_BASE__INST3_SEG2 0 192fb4d8502Sjsg #define ATHUB_BASE__INST3_SEG3 0 193fb4d8502Sjsg #define ATHUB_BASE__INST3_SEG4 0 194fb4d8502Sjsg #define ATHUB_BASE__INST3_SEG5 0 195fb4d8502Sjsg 196fb4d8502Sjsg #define ATHUB_BASE__INST4_SEG0 0 197fb4d8502Sjsg #define ATHUB_BASE__INST4_SEG1 0 198fb4d8502Sjsg #define ATHUB_BASE__INST4_SEG2 0 199fb4d8502Sjsg #define ATHUB_BASE__INST4_SEG3 0 200fb4d8502Sjsg #define ATHUB_BASE__INST4_SEG4 0 201fb4d8502Sjsg #define ATHUB_BASE__INST4_SEG5 0 202fb4d8502Sjsg 203fb4d8502Sjsg #define ATHUB_BASE__INST5_SEG0 0 204fb4d8502Sjsg #define ATHUB_BASE__INST5_SEG1 0 205fb4d8502Sjsg #define ATHUB_BASE__INST5_SEG2 0 206fb4d8502Sjsg #define ATHUB_BASE__INST5_SEG3 0 207fb4d8502Sjsg #define ATHUB_BASE__INST5_SEG4 0 208fb4d8502Sjsg #define ATHUB_BASE__INST5_SEG5 0 209fb4d8502Sjsg 210fb4d8502Sjsg #define CLK_BASE__INST0_SEG0 0x00016C00 211fb4d8502Sjsg #define CLK_BASE__INST0_SEG1 0x00016E00 212fb4d8502Sjsg #define CLK_BASE__INST0_SEG2 0x00017000 213fb4d8502Sjsg #define CLK_BASE__INST0_SEG3 0x00017200 214fb4d8502Sjsg #define CLK_BASE__INST0_SEG4 0x0001B000 215fb4d8502Sjsg #define CLK_BASE__INST0_SEG5 0x0001B200 216fb4d8502Sjsg 217fb4d8502Sjsg #define CLK_BASE__INST1_SEG0 0 218fb4d8502Sjsg #define CLK_BASE__INST1_SEG1 0 219fb4d8502Sjsg #define CLK_BASE__INST1_SEG2 0 220fb4d8502Sjsg #define CLK_BASE__INST1_SEG3 0 221fb4d8502Sjsg #define CLK_BASE__INST1_SEG4 0 222fb4d8502Sjsg #define CLK_BASE__INST1_SEG5 0 223fb4d8502Sjsg 224fb4d8502Sjsg #define CLK_BASE__INST2_SEG0 0 225fb4d8502Sjsg #define CLK_BASE__INST2_SEG1 0 226fb4d8502Sjsg #define CLK_BASE__INST2_SEG2 0 227fb4d8502Sjsg #define CLK_BASE__INST2_SEG3 0 228fb4d8502Sjsg #define CLK_BASE__INST2_SEG4 0 229fb4d8502Sjsg #define CLK_BASE__INST2_SEG5 0 230fb4d8502Sjsg 231fb4d8502Sjsg #define CLK_BASE__INST3_SEG0 0 232fb4d8502Sjsg #define CLK_BASE__INST3_SEG1 0 233fb4d8502Sjsg #define CLK_BASE__INST3_SEG2 0 234fb4d8502Sjsg #define CLK_BASE__INST3_SEG3 0 235fb4d8502Sjsg #define CLK_BASE__INST3_SEG4 0 236fb4d8502Sjsg #define CLK_BASE__INST3_SEG5 0 237fb4d8502Sjsg 238fb4d8502Sjsg #define CLK_BASE__INST4_SEG0 0 239fb4d8502Sjsg #define CLK_BASE__INST4_SEG1 0 240fb4d8502Sjsg #define CLK_BASE__INST4_SEG2 0 241fb4d8502Sjsg #define CLK_BASE__INST4_SEG3 0 242fb4d8502Sjsg #define CLK_BASE__INST4_SEG4 0 243fb4d8502Sjsg #define CLK_BASE__INST4_SEG5 0 244fb4d8502Sjsg 245fb4d8502Sjsg #define CLK_BASE__INST5_SEG0 0 246fb4d8502Sjsg #define CLK_BASE__INST5_SEG1 0 247fb4d8502Sjsg #define CLK_BASE__INST5_SEG2 0 248fb4d8502Sjsg #define CLK_BASE__INST5_SEG3 0 249fb4d8502Sjsg #define CLK_BASE__INST5_SEG4 0 250fb4d8502Sjsg #define CLK_BASE__INST5_SEG5 0 251fb4d8502Sjsg 252fb4d8502Sjsg #define DCE_BASE__INST0_SEG0 0x00000012 253fb4d8502Sjsg #define DCE_BASE__INST0_SEG1 0x000000C0 254fb4d8502Sjsg #define DCE_BASE__INST0_SEG2 0x000034C0 255fb4d8502Sjsg #define DCE_BASE__INST0_SEG3 0 256fb4d8502Sjsg #define DCE_BASE__INST0_SEG4 0 257fb4d8502Sjsg #define DCE_BASE__INST0_SEG5 0 258fb4d8502Sjsg 259fb4d8502Sjsg #define DCE_BASE__INST1_SEG0 0 260fb4d8502Sjsg #define DCE_BASE__INST1_SEG1 0 261fb4d8502Sjsg #define DCE_BASE__INST1_SEG2 0 262fb4d8502Sjsg #define DCE_BASE__INST1_SEG3 0 263fb4d8502Sjsg #define DCE_BASE__INST1_SEG4 0 264fb4d8502Sjsg #define DCE_BASE__INST1_SEG5 0 265fb4d8502Sjsg 266fb4d8502Sjsg #define DCE_BASE__INST2_SEG0 0 267fb4d8502Sjsg #define DCE_BASE__INST2_SEG1 0 268fb4d8502Sjsg #define DCE_BASE__INST2_SEG2 0 269fb4d8502Sjsg #define DCE_BASE__INST2_SEG3 0 270fb4d8502Sjsg #define DCE_BASE__INST2_SEG4 0 271fb4d8502Sjsg #define DCE_BASE__INST2_SEG5 0 272fb4d8502Sjsg 273fb4d8502Sjsg #define DCE_BASE__INST3_SEG0 0 274fb4d8502Sjsg #define DCE_BASE__INST3_SEG1 0 275fb4d8502Sjsg #define DCE_BASE__INST3_SEG2 0 276fb4d8502Sjsg #define DCE_BASE__INST3_SEG3 0 277fb4d8502Sjsg #define DCE_BASE__INST3_SEG4 0 278fb4d8502Sjsg #define DCE_BASE__INST3_SEG5 0 279fb4d8502Sjsg 280fb4d8502Sjsg #define DCE_BASE__INST4_SEG0 0 281fb4d8502Sjsg #define DCE_BASE__INST4_SEG1 0 282fb4d8502Sjsg #define DCE_BASE__INST4_SEG2 0 283fb4d8502Sjsg #define DCE_BASE__INST4_SEG3 0 284fb4d8502Sjsg #define DCE_BASE__INST4_SEG4 0 285fb4d8502Sjsg #define DCE_BASE__INST4_SEG5 0 286fb4d8502Sjsg 287fb4d8502Sjsg #define DCE_BASE__INST5_SEG0 0 288fb4d8502Sjsg #define DCE_BASE__INST5_SEG1 0 289fb4d8502Sjsg #define DCE_BASE__INST5_SEG2 0 290fb4d8502Sjsg #define DCE_BASE__INST5_SEG3 0 291fb4d8502Sjsg #define DCE_BASE__INST5_SEG4 0 292fb4d8502Sjsg #define DCE_BASE__INST5_SEG5 0 293fb4d8502Sjsg 294fb4d8502Sjsg #define DF_BASE__INST0_SEG0 0x00007000 295fb4d8502Sjsg #define DF_BASE__INST0_SEG1 0 296fb4d8502Sjsg #define DF_BASE__INST0_SEG2 0 297fb4d8502Sjsg #define DF_BASE__INST0_SEG3 0 298fb4d8502Sjsg #define DF_BASE__INST0_SEG4 0 299fb4d8502Sjsg #define DF_BASE__INST0_SEG5 0 300fb4d8502Sjsg 301fb4d8502Sjsg #define DF_BASE__INST1_SEG0 0 302fb4d8502Sjsg #define DF_BASE__INST1_SEG1 0 303fb4d8502Sjsg #define DF_BASE__INST1_SEG2 0 304fb4d8502Sjsg #define DF_BASE__INST1_SEG3 0 305fb4d8502Sjsg #define DF_BASE__INST1_SEG4 0 306fb4d8502Sjsg #define DF_BASE__INST1_SEG5 0 307fb4d8502Sjsg 308fb4d8502Sjsg #define DF_BASE__INST2_SEG0 0 309fb4d8502Sjsg #define DF_BASE__INST2_SEG1 0 310fb4d8502Sjsg #define DF_BASE__INST2_SEG2 0 311fb4d8502Sjsg #define DF_BASE__INST2_SEG3 0 312fb4d8502Sjsg #define DF_BASE__INST2_SEG4 0 313fb4d8502Sjsg #define DF_BASE__INST2_SEG5 0 314fb4d8502Sjsg 315fb4d8502Sjsg #define DF_BASE__INST3_SEG0 0 316fb4d8502Sjsg #define DF_BASE__INST3_SEG1 0 317fb4d8502Sjsg #define DF_BASE__INST3_SEG2 0 318fb4d8502Sjsg #define DF_BASE__INST3_SEG3 0 319fb4d8502Sjsg #define DF_BASE__INST3_SEG4 0 320fb4d8502Sjsg #define DF_BASE__INST3_SEG5 0 321fb4d8502Sjsg 322fb4d8502Sjsg #define DF_BASE__INST4_SEG0 0 323fb4d8502Sjsg #define DF_BASE__INST4_SEG1 0 324fb4d8502Sjsg #define DF_BASE__INST4_SEG2 0 325fb4d8502Sjsg #define DF_BASE__INST4_SEG3 0 326fb4d8502Sjsg #define DF_BASE__INST4_SEG4 0 327fb4d8502Sjsg #define DF_BASE__INST4_SEG5 0 328fb4d8502Sjsg 329fb4d8502Sjsg #define DF_BASE__INST5_SEG0 0 330fb4d8502Sjsg #define DF_BASE__INST5_SEG1 0 331fb4d8502Sjsg #define DF_BASE__INST5_SEG2 0 332fb4d8502Sjsg #define DF_BASE__INST5_SEG3 0 333fb4d8502Sjsg #define DF_BASE__INST5_SEG4 0 334fb4d8502Sjsg #define DF_BASE__INST5_SEG5 0 335fb4d8502Sjsg 336fb4d8502Sjsg #define FUSE_BASE__INST0_SEG0 0x00017400 337fb4d8502Sjsg #define FUSE_BASE__INST0_SEG1 0 338fb4d8502Sjsg #define FUSE_BASE__INST0_SEG2 0 339fb4d8502Sjsg #define FUSE_BASE__INST0_SEG3 0 340fb4d8502Sjsg #define FUSE_BASE__INST0_SEG4 0 341fb4d8502Sjsg #define FUSE_BASE__INST0_SEG5 0 342fb4d8502Sjsg 343fb4d8502Sjsg #define FUSE_BASE__INST1_SEG0 0 344fb4d8502Sjsg #define FUSE_BASE__INST1_SEG1 0 345fb4d8502Sjsg #define FUSE_BASE__INST1_SEG2 0 346fb4d8502Sjsg #define FUSE_BASE__INST1_SEG3 0 347fb4d8502Sjsg #define FUSE_BASE__INST1_SEG4 0 348fb4d8502Sjsg #define FUSE_BASE__INST1_SEG5 0 349fb4d8502Sjsg 350fb4d8502Sjsg #define FUSE_BASE__INST2_SEG0 0 351fb4d8502Sjsg #define FUSE_BASE__INST2_SEG1 0 352fb4d8502Sjsg #define FUSE_BASE__INST2_SEG2 0 353fb4d8502Sjsg #define FUSE_BASE__INST2_SEG3 0 354fb4d8502Sjsg #define FUSE_BASE__INST2_SEG4 0 355fb4d8502Sjsg #define FUSE_BASE__INST2_SEG5 0 356fb4d8502Sjsg 357fb4d8502Sjsg #define FUSE_BASE__INST3_SEG0 0 358fb4d8502Sjsg #define FUSE_BASE__INST3_SEG1 0 359fb4d8502Sjsg #define FUSE_BASE__INST3_SEG2 0 360fb4d8502Sjsg #define FUSE_BASE__INST3_SEG3 0 361fb4d8502Sjsg #define FUSE_BASE__INST3_SEG4 0 362fb4d8502Sjsg #define FUSE_BASE__INST3_SEG5 0 363fb4d8502Sjsg 364fb4d8502Sjsg #define FUSE_BASE__INST4_SEG0 0 365fb4d8502Sjsg #define FUSE_BASE__INST4_SEG1 0 366fb4d8502Sjsg #define FUSE_BASE__INST4_SEG2 0 367fb4d8502Sjsg #define FUSE_BASE__INST4_SEG3 0 368fb4d8502Sjsg #define FUSE_BASE__INST4_SEG4 0 369fb4d8502Sjsg #define FUSE_BASE__INST4_SEG5 0 370fb4d8502Sjsg 371fb4d8502Sjsg #define FUSE_BASE__INST5_SEG0 0 372fb4d8502Sjsg #define FUSE_BASE__INST5_SEG1 0 373fb4d8502Sjsg #define FUSE_BASE__INST5_SEG2 0 374fb4d8502Sjsg #define FUSE_BASE__INST5_SEG3 0 375fb4d8502Sjsg #define FUSE_BASE__INST5_SEG4 0 376fb4d8502Sjsg #define FUSE_BASE__INST5_SEG5 0 377fb4d8502Sjsg 378fb4d8502Sjsg #define GC_BASE__INST0_SEG0 0x00002000 379fb4d8502Sjsg #define GC_BASE__INST0_SEG1 0x0000A000 380fb4d8502Sjsg #define GC_BASE__INST0_SEG2 0 381fb4d8502Sjsg #define GC_BASE__INST0_SEG3 0 382fb4d8502Sjsg #define GC_BASE__INST0_SEG4 0 383fb4d8502Sjsg #define GC_BASE__INST0_SEG5 0 384fb4d8502Sjsg 385fb4d8502Sjsg #define GC_BASE__INST1_SEG0 0 386fb4d8502Sjsg #define GC_BASE__INST1_SEG1 0 387fb4d8502Sjsg #define GC_BASE__INST1_SEG2 0 388fb4d8502Sjsg #define GC_BASE__INST1_SEG3 0 389fb4d8502Sjsg #define GC_BASE__INST1_SEG4 0 390fb4d8502Sjsg #define GC_BASE__INST1_SEG5 0 391fb4d8502Sjsg 392fb4d8502Sjsg #define GC_BASE__INST2_SEG0 0 393fb4d8502Sjsg #define GC_BASE__INST2_SEG1 0 394fb4d8502Sjsg #define GC_BASE__INST2_SEG2 0 395fb4d8502Sjsg #define GC_BASE__INST2_SEG3 0 396fb4d8502Sjsg #define GC_BASE__INST2_SEG4 0 397fb4d8502Sjsg #define GC_BASE__INST2_SEG5 0 398fb4d8502Sjsg 399fb4d8502Sjsg #define GC_BASE__INST3_SEG0 0 400fb4d8502Sjsg #define GC_BASE__INST3_SEG1 0 401fb4d8502Sjsg #define GC_BASE__INST3_SEG2 0 402fb4d8502Sjsg #define GC_BASE__INST3_SEG3 0 403fb4d8502Sjsg #define GC_BASE__INST3_SEG4 0 404fb4d8502Sjsg #define GC_BASE__INST3_SEG5 0 405fb4d8502Sjsg 406fb4d8502Sjsg #define GC_BASE__INST4_SEG0 0 407fb4d8502Sjsg #define GC_BASE__INST4_SEG1 0 408fb4d8502Sjsg #define GC_BASE__INST4_SEG2 0 409fb4d8502Sjsg #define GC_BASE__INST4_SEG3 0 410fb4d8502Sjsg #define GC_BASE__INST4_SEG4 0 411fb4d8502Sjsg #define GC_BASE__INST4_SEG5 0 412fb4d8502Sjsg 413fb4d8502Sjsg #define GC_BASE__INST5_SEG0 0 414fb4d8502Sjsg #define GC_BASE__INST5_SEG1 0 415fb4d8502Sjsg #define GC_BASE__INST5_SEG2 0 416fb4d8502Sjsg #define GC_BASE__INST5_SEG3 0 417fb4d8502Sjsg #define GC_BASE__INST5_SEG4 0 418fb4d8502Sjsg #define GC_BASE__INST5_SEG5 0 419fb4d8502Sjsg 420fb4d8502Sjsg #define HDP_BASE__INST0_SEG0 0x00000F20 421fb4d8502Sjsg #define HDP_BASE__INST0_SEG1 0 422fb4d8502Sjsg #define HDP_BASE__INST0_SEG2 0 423fb4d8502Sjsg #define HDP_BASE__INST0_SEG3 0 424fb4d8502Sjsg #define HDP_BASE__INST0_SEG4 0 425fb4d8502Sjsg #define HDP_BASE__INST0_SEG5 0 426fb4d8502Sjsg 427fb4d8502Sjsg #define HDP_BASE__INST1_SEG0 0 428fb4d8502Sjsg #define HDP_BASE__INST1_SEG1 0 429fb4d8502Sjsg #define HDP_BASE__INST1_SEG2 0 430fb4d8502Sjsg #define HDP_BASE__INST1_SEG3 0 431fb4d8502Sjsg #define HDP_BASE__INST1_SEG4 0 432fb4d8502Sjsg #define HDP_BASE__INST1_SEG5 0 433fb4d8502Sjsg 434fb4d8502Sjsg #define HDP_BASE__INST2_SEG0 0 435fb4d8502Sjsg #define HDP_BASE__INST2_SEG1 0 436fb4d8502Sjsg #define HDP_BASE__INST2_SEG2 0 437fb4d8502Sjsg #define HDP_BASE__INST2_SEG3 0 438fb4d8502Sjsg #define HDP_BASE__INST2_SEG4 0 439fb4d8502Sjsg #define HDP_BASE__INST2_SEG5 0 440fb4d8502Sjsg 441fb4d8502Sjsg #define HDP_BASE__INST3_SEG0 0 442fb4d8502Sjsg #define HDP_BASE__INST3_SEG1 0 443fb4d8502Sjsg #define HDP_BASE__INST3_SEG2 0 444fb4d8502Sjsg #define HDP_BASE__INST3_SEG3 0 445fb4d8502Sjsg #define HDP_BASE__INST3_SEG4 0 446fb4d8502Sjsg #define HDP_BASE__INST3_SEG5 0 447fb4d8502Sjsg 448fb4d8502Sjsg #define HDP_BASE__INST4_SEG0 0 449fb4d8502Sjsg #define HDP_BASE__INST4_SEG1 0 450fb4d8502Sjsg #define HDP_BASE__INST4_SEG2 0 451fb4d8502Sjsg #define HDP_BASE__INST4_SEG3 0 452fb4d8502Sjsg #define HDP_BASE__INST4_SEG4 0 453fb4d8502Sjsg #define HDP_BASE__INST4_SEG5 0 454fb4d8502Sjsg 455fb4d8502Sjsg #define HDP_BASE__INST5_SEG0 0 456fb4d8502Sjsg #define HDP_BASE__INST5_SEG1 0 457fb4d8502Sjsg #define HDP_BASE__INST5_SEG2 0 458fb4d8502Sjsg #define HDP_BASE__INST5_SEG3 0 459fb4d8502Sjsg #define HDP_BASE__INST5_SEG4 0 460fb4d8502Sjsg #define HDP_BASE__INST5_SEG5 0 461fb4d8502Sjsg 462fb4d8502Sjsg #define MMHUB_BASE__INST0_SEG0 0x0001A000 463fb4d8502Sjsg #define MMHUB_BASE__INST0_SEG1 0 464fb4d8502Sjsg #define MMHUB_BASE__INST0_SEG2 0 465fb4d8502Sjsg #define MMHUB_BASE__INST0_SEG3 0 466fb4d8502Sjsg #define MMHUB_BASE__INST0_SEG4 0 467fb4d8502Sjsg #define MMHUB_BASE__INST0_SEG5 0 468fb4d8502Sjsg 469fb4d8502Sjsg #define MMHUB_BASE__INST1_SEG0 0 470fb4d8502Sjsg #define MMHUB_BASE__INST1_SEG1 0 471fb4d8502Sjsg #define MMHUB_BASE__INST1_SEG2 0 472fb4d8502Sjsg #define MMHUB_BASE__INST1_SEG3 0 473fb4d8502Sjsg #define MMHUB_BASE__INST1_SEG4 0 474fb4d8502Sjsg #define MMHUB_BASE__INST1_SEG5 0 475fb4d8502Sjsg 476fb4d8502Sjsg #define MMHUB_BASE__INST2_SEG0 0 477fb4d8502Sjsg #define MMHUB_BASE__INST2_SEG1 0 478fb4d8502Sjsg #define MMHUB_BASE__INST2_SEG2 0 479fb4d8502Sjsg #define MMHUB_BASE__INST2_SEG3 0 480fb4d8502Sjsg #define MMHUB_BASE__INST2_SEG4 0 481fb4d8502Sjsg #define MMHUB_BASE__INST2_SEG5 0 482fb4d8502Sjsg 483fb4d8502Sjsg #define MMHUB_BASE__INST3_SEG0 0 484fb4d8502Sjsg #define MMHUB_BASE__INST3_SEG1 0 485fb4d8502Sjsg #define MMHUB_BASE__INST3_SEG2 0 486fb4d8502Sjsg #define MMHUB_BASE__INST3_SEG3 0 487fb4d8502Sjsg #define MMHUB_BASE__INST3_SEG4 0 488fb4d8502Sjsg #define MMHUB_BASE__INST3_SEG5 0 489fb4d8502Sjsg 490fb4d8502Sjsg #define MMHUB_BASE__INST4_SEG0 0 491fb4d8502Sjsg #define MMHUB_BASE__INST4_SEG1 0 492fb4d8502Sjsg #define MMHUB_BASE__INST4_SEG2 0 493fb4d8502Sjsg #define MMHUB_BASE__INST4_SEG3 0 494fb4d8502Sjsg #define MMHUB_BASE__INST4_SEG4 0 495fb4d8502Sjsg #define MMHUB_BASE__INST4_SEG5 0 496fb4d8502Sjsg 497fb4d8502Sjsg #define MMHUB_BASE__INST5_SEG0 0 498fb4d8502Sjsg #define MMHUB_BASE__INST5_SEG1 0 499fb4d8502Sjsg #define MMHUB_BASE__INST5_SEG2 0 500fb4d8502Sjsg #define MMHUB_BASE__INST5_SEG3 0 501fb4d8502Sjsg #define MMHUB_BASE__INST5_SEG4 0 502fb4d8502Sjsg #define MMHUB_BASE__INST5_SEG5 0 503fb4d8502Sjsg 504fb4d8502Sjsg #define MP0_BASE__INST0_SEG0 0x00016000 505fb4d8502Sjsg #define MP0_BASE__INST0_SEG1 0 506fb4d8502Sjsg #define MP0_BASE__INST0_SEG2 0 507fb4d8502Sjsg #define MP0_BASE__INST0_SEG3 0 508fb4d8502Sjsg #define MP0_BASE__INST0_SEG4 0 509fb4d8502Sjsg #define MP0_BASE__INST0_SEG5 0 510fb4d8502Sjsg 511fb4d8502Sjsg #define MP0_BASE__INST1_SEG0 0 512fb4d8502Sjsg #define MP0_BASE__INST1_SEG1 0 513fb4d8502Sjsg #define MP0_BASE__INST1_SEG2 0 514fb4d8502Sjsg #define MP0_BASE__INST1_SEG3 0 515fb4d8502Sjsg #define MP0_BASE__INST1_SEG4 0 516fb4d8502Sjsg #define MP0_BASE__INST1_SEG5 0 517fb4d8502Sjsg 518fb4d8502Sjsg #define MP0_BASE__INST2_SEG0 0 519fb4d8502Sjsg #define MP0_BASE__INST2_SEG1 0 520fb4d8502Sjsg #define MP0_BASE__INST2_SEG2 0 521fb4d8502Sjsg #define MP0_BASE__INST2_SEG3 0 522fb4d8502Sjsg #define MP0_BASE__INST2_SEG4 0 523fb4d8502Sjsg #define MP0_BASE__INST2_SEG5 0 524fb4d8502Sjsg 525fb4d8502Sjsg #define MP0_BASE__INST3_SEG0 0 526fb4d8502Sjsg #define MP0_BASE__INST3_SEG1 0 527fb4d8502Sjsg #define MP0_BASE__INST3_SEG2 0 528fb4d8502Sjsg #define MP0_BASE__INST3_SEG3 0 529fb4d8502Sjsg #define MP0_BASE__INST3_SEG4 0 530fb4d8502Sjsg #define MP0_BASE__INST3_SEG5 0 531fb4d8502Sjsg 532fb4d8502Sjsg #define MP0_BASE__INST4_SEG0 0 533fb4d8502Sjsg #define MP0_BASE__INST4_SEG1 0 534fb4d8502Sjsg #define MP0_BASE__INST4_SEG2 0 535fb4d8502Sjsg #define MP0_BASE__INST4_SEG3 0 536fb4d8502Sjsg #define MP0_BASE__INST4_SEG4 0 537fb4d8502Sjsg #define MP0_BASE__INST4_SEG5 0 538fb4d8502Sjsg 539fb4d8502Sjsg #define MP0_BASE__INST5_SEG0 0 540fb4d8502Sjsg #define MP0_BASE__INST5_SEG1 0 541fb4d8502Sjsg #define MP0_BASE__INST5_SEG2 0 542fb4d8502Sjsg #define MP0_BASE__INST5_SEG3 0 543fb4d8502Sjsg #define MP0_BASE__INST5_SEG4 0 544fb4d8502Sjsg #define MP0_BASE__INST5_SEG5 0 545fb4d8502Sjsg 546fb4d8502Sjsg #define MP1_BASE__INST0_SEG0 0x00016000 547fb4d8502Sjsg #define MP1_BASE__INST0_SEG1 0 548fb4d8502Sjsg #define MP1_BASE__INST0_SEG2 0 549fb4d8502Sjsg #define MP1_BASE__INST0_SEG3 0 550fb4d8502Sjsg #define MP1_BASE__INST0_SEG4 0 551fb4d8502Sjsg #define MP1_BASE__INST0_SEG5 0 552fb4d8502Sjsg 553fb4d8502Sjsg #define MP1_BASE__INST1_SEG0 0 554fb4d8502Sjsg #define MP1_BASE__INST1_SEG1 0 555fb4d8502Sjsg #define MP1_BASE__INST1_SEG2 0 556fb4d8502Sjsg #define MP1_BASE__INST1_SEG3 0 557fb4d8502Sjsg #define MP1_BASE__INST1_SEG4 0 558fb4d8502Sjsg #define MP1_BASE__INST1_SEG5 0 559fb4d8502Sjsg 560fb4d8502Sjsg #define MP1_BASE__INST2_SEG0 0 561fb4d8502Sjsg #define MP1_BASE__INST2_SEG1 0 562fb4d8502Sjsg #define MP1_BASE__INST2_SEG2 0 563fb4d8502Sjsg #define MP1_BASE__INST2_SEG3 0 564fb4d8502Sjsg #define MP1_BASE__INST2_SEG4 0 565fb4d8502Sjsg #define MP1_BASE__INST2_SEG5 0 566fb4d8502Sjsg 567fb4d8502Sjsg #define MP1_BASE__INST3_SEG0 0 568fb4d8502Sjsg #define MP1_BASE__INST3_SEG1 0 569fb4d8502Sjsg #define MP1_BASE__INST3_SEG2 0 570fb4d8502Sjsg #define MP1_BASE__INST3_SEG3 0 571fb4d8502Sjsg #define MP1_BASE__INST3_SEG4 0 572fb4d8502Sjsg #define MP1_BASE__INST3_SEG5 0 573fb4d8502Sjsg 574fb4d8502Sjsg #define MP1_BASE__INST4_SEG0 0 575fb4d8502Sjsg #define MP1_BASE__INST4_SEG1 0 576fb4d8502Sjsg #define MP1_BASE__INST4_SEG2 0 577fb4d8502Sjsg #define MP1_BASE__INST4_SEG3 0 578fb4d8502Sjsg #define MP1_BASE__INST4_SEG4 0 579fb4d8502Sjsg #define MP1_BASE__INST4_SEG5 0 580fb4d8502Sjsg 581fb4d8502Sjsg #define MP1_BASE__INST5_SEG0 0 582fb4d8502Sjsg #define MP1_BASE__INST5_SEG1 0 583fb4d8502Sjsg #define MP1_BASE__INST5_SEG2 0 584fb4d8502Sjsg #define MP1_BASE__INST5_SEG3 0 585fb4d8502Sjsg #define MP1_BASE__INST5_SEG4 0 586fb4d8502Sjsg #define MP1_BASE__INST5_SEG5 0 587fb4d8502Sjsg 588fb4d8502Sjsg #define NBIO_BASE__INST0_SEG0 0x00000000 589fb4d8502Sjsg #define NBIO_BASE__INST0_SEG1 0x00000014 590fb4d8502Sjsg #define NBIO_BASE__INST0_SEG2 0x00000D20 591fb4d8502Sjsg #define NBIO_BASE__INST0_SEG3 0x00010400 592fb4d8502Sjsg #define NBIO_BASE__INST0_SEG4 0 593fb4d8502Sjsg #define NBIO_BASE__INST0_SEG5 0 594fb4d8502Sjsg 595fb4d8502Sjsg #define NBIO_BASE__INST1_SEG0 0 596fb4d8502Sjsg #define NBIO_BASE__INST1_SEG1 0 597fb4d8502Sjsg #define NBIO_BASE__INST1_SEG2 0 598fb4d8502Sjsg #define NBIO_BASE__INST1_SEG3 0 599fb4d8502Sjsg #define NBIO_BASE__INST1_SEG4 0 600fb4d8502Sjsg #define NBIO_BASE__INST1_SEG5 0 601fb4d8502Sjsg 602fb4d8502Sjsg #define NBIO_BASE__INST2_SEG0 0 603fb4d8502Sjsg #define NBIO_BASE__INST2_SEG1 0 604fb4d8502Sjsg #define NBIO_BASE__INST2_SEG2 0 605fb4d8502Sjsg #define NBIO_BASE__INST2_SEG3 0 606fb4d8502Sjsg #define NBIO_BASE__INST2_SEG4 0 607fb4d8502Sjsg #define NBIO_BASE__INST2_SEG5 0 608fb4d8502Sjsg 609fb4d8502Sjsg #define NBIO_BASE__INST3_SEG0 0 610fb4d8502Sjsg #define NBIO_BASE__INST3_SEG1 0 611fb4d8502Sjsg #define NBIO_BASE__INST3_SEG2 0 612fb4d8502Sjsg #define NBIO_BASE__INST3_SEG3 0 613fb4d8502Sjsg #define NBIO_BASE__INST3_SEG4 0 614fb4d8502Sjsg #define NBIO_BASE__INST3_SEG5 0 615fb4d8502Sjsg 616fb4d8502Sjsg #define NBIO_BASE__INST4_SEG0 0 617fb4d8502Sjsg #define NBIO_BASE__INST4_SEG1 0 618fb4d8502Sjsg #define NBIO_BASE__INST4_SEG2 0 619fb4d8502Sjsg #define NBIO_BASE__INST4_SEG3 0 620fb4d8502Sjsg #define NBIO_BASE__INST4_SEG4 0 621fb4d8502Sjsg #define NBIO_BASE__INST4_SEG5 0 622fb4d8502Sjsg 623fb4d8502Sjsg #define NBIO_BASE__INST5_SEG0 0 624fb4d8502Sjsg #define NBIO_BASE__INST5_SEG1 0 625fb4d8502Sjsg #define NBIO_BASE__INST5_SEG2 0 626fb4d8502Sjsg #define NBIO_BASE__INST5_SEG3 0 627fb4d8502Sjsg #define NBIO_BASE__INST5_SEG4 0 628fb4d8502Sjsg #define NBIO_BASE__INST5_SEG5 0 629fb4d8502Sjsg 630fb4d8502Sjsg #define OSSSYS_BASE__INST0_SEG0 0x000010A0 631fb4d8502Sjsg #define OSSSYS_BASE__INST0_SEG1 0 632fb4d8502Sjsg #define OSSSYS_BASE__INST0_SEG2 0 633fb4d8502Sjsg #define OSSSYS_BASE__INST0_SEG3 0 634fb4d8502Sjsg #define OSSSYS_BASE__INST0_SEG4 0 635fb4d8502Sjsg #define OSSSYS_BASE__INST0_SEG5 0 636fb4d8502Sjsg 637fb4d8502Sjsg #define OSSSYS_BASE__INST1_SEG0 0 638fb4d8502Sjsg #define OSSSYS_BASE__INST1_SEG1 0 639fb4d8502Sjsg #define OSSSYS_BASE__INST1_SEG2 0 640fb4d8502Sjsg #define OSSSYS_BASE__INST1_SEG3 0 641fb4d8502Sjsg #define OSSSYS_BASE__INST1_SEG4 0 642fb4d8502Sjsg #define OSSSYS_BASE__INST1_SEG5 0 643fb4d8502Sjsg 644fb4d8502Sjsg #define OSSSYS_BASE__INST2_SEG0 0 645fb4d8502Sjsg #define OSSSYS_BASE__INST2_SEG1 0 646fb4d8502Sjsg #define OSSSYS_BASE__INST2_SEG2 0 647fb4d8502Sjsg #define OSSSYS_BASE__INST2_SEG3 0 648fb4d8502Sjsg #define OSSSYS_BASE__INST2_SEG4 0 649fb4d8502Sjsg #define OSSSYS_BASE__INST2_SEG5 0 650fb4d8502Sjsg 651fb4d8502Sjsg #define OSSSYS_BASE__INST3_SEG0 0 652fb4d8502Sjsg #define OSSSYS_BASE__INST3_SEG1 0 653fb4d8502Sjsg #define OSSSYS_BASE__INST3_SEG2 0 654fb4d8502Sjsg #define OSSSYS_BASE__INST3_SEG3 0 655fb4d8502Sjsg #define OSSSYS_BASE__INST3_SEG4 0 656fb4d8502Sjsg #define OSSSYS_BASE__INST3_SEG5 0 657fb4d8502Sjsg 658fb4d8502Sjsg #define OSSSYS_BASE__INST4_SEG0 0 659fb4d8502Sjsg #define OSSSYS_BASE__INST4_SEG1 0 660fb4d8502Sjsg #define OSSSYS_BASE__INST4_SEG2 0 661fb4d8502Sjsg #define OSSSYS_BASE__INST4_SEG3 0 662fb4d8502Sjsg #define OSSSYS_BASE__INST4_SEG4 0 663fb4d8502Sjsg #define OSSSYS_BASE__INST4_SEG5 0 664fb4d8502Sjsg 665fb4d8502Sjsg #define OSSSYS_BASE__INST5_SEG0 0 666fb4d8502Sjsg #define OSSSYS_BASE__INST5_SEG1 0 667fb4d8502Sjsg #define OSSSYS_BASE__INST5_SEG2 0 668fb4d8502Sjsg #define OSSSYS_BASE__INST5_SEG3 0 669fb4d8502Sjsg #define OSSSYS_BASE__INST5_SEG4 0 670fb4d8502Sjsg #define OSSSYS_BASE__INST5_SEG5 0 671fb4d8502Sjsg 672fb4d8502Sjsg #define SDMA0_BASE__INST0_SEG0 0x00001260 673fb4d8502Sjsg #define SDMA0_BASE__INST0_SEG1 0 674fb4d8502Sjsg #define SDMA0_BASE__INST0_SEG2 0 675fb4d8502Sjsg #define SDMA0_BASE__INST0_SEG3 0 676fb4d8502Sjsg #define SDMA0_BASE__INST0_SEG4 0 677fb4d8502Sjsg #define SDMA0_BASE__INST0_SEG5 0 678fb4d8502Sjsg 679fb4d8502Sjsg #define SDMA0_BASE__INST1_SEG0 0 680fb4d8502Sjsg #define SDMA0_BASE__INST1_SEG1 0 681fb4d8502Sjsg #define SDMA0_BASE__INST1_SEG2 0 682fb4d8502Sjsg #define SDMA0_BASE__INST1_SEG3 0 683fb4d8502Sjsg #define SDMA0_BASE__INST1_SEG4 0 684fb4d8502Sjsg #define SDMA0_BASE__INST1_SEG5 0 685fb4d8502Sjsg 686fb4d8502Sjsg #define SDMA0_BASE__INST2_SEG0 0 687fb4d8502Sjsg #define SDMA0_BASE__INST2_SEG1 0 688fb4d8502Sjsg #define SDMA0_BASE__INST2_SEG2 0 689fb4d8502Sjsg #define SDMA0_BASE__INST2_SEG3 0 690fb4d8502Sjsg #define SDMA0_BASE__INST2_SEG4 0 691fb4d8502Sjsg #define SDMA0_BASE__INST2_SEG5 0 692fb4d8502Sjsg 693fb4d8502Sjsg #define SDMA0_BASE__INST3_SEG0 0 694fb4d8502Sjsg #define SDMA0_BASE__INST3_SEG1 0 695fb4d8502Sjsg #define SDMA0_BASE__INST3_SEG2 0 696fb4d8502Sjsg #define SDMA0_BASE__INST3_SEG3 0 697fb4d8502Sjsg #define SDMA0_BASE__INST3_SEG4 0 698fb4d8502Sjsg #define SDMA0_BASE__INST3_SEG5 0 699fb4d8502Sjsg 700fb4d8502Sjsg #define SDMA0_BASE__INST4_SEG0 0 701fb4d8502Sjsg #define SDMA0_BASE__INST4_SEG1 0 702fb4d8502Sjsg #define SDMA0_BASE__INST4_SEG2 0 703fb4d8502Sjsg #define SDMA0_BASE__INST4_SEG3 0 704fb4d8502Sjsg #define SDMA0_BASE__INST4_SEG4 0 705fb4d8502Sjsg #define SDMA0_BASE__INST4_SEG5 0 706fb4d8502Sjsg 707fb4d8502Sjsg #define SDMA0_BASE__INST5_SEG0 0 708fb4d8502Sjsg #define SDMA0_BASE__INST5_SEG1 0 709fb4d8502Sjsg #define SDMA0_BASE__INST5_SEG2 0 710fb4d8502Sjsg #define SDMA0_BASE__INST5_SEG3 0 711fb4d8502Sjsg #define SDMA0_BASE__INST5_SEG4 0 712fb4d8502Sjsg #define SDMA0_BASE__INST5_SEG5 0 713fb4d8502Sjsg 714fb4d8502Sjsg #define SDMA1_BASE__INST0_SEG0 0x00001860 715fb4d8502Sjsg #define SDMA1_BASE__INST0_SEG1 0 716fb4d8502Sjsg #define SDMA1_BASE__INST0_SEG2 0 717fb4d8502Sjsg #define SDMA1_BASE__INST0_SEG3 0 718fb4d8502Sjsg #define SDMA1_BASE__INST0_SEG4 0 719fb4d8502Sjsg #define SDMA1_BASE__INST0_SEG5 0 720fb4d8502Sjsg 721fb4d8502Sjsg #define SDMA1_BASE__INST1_SEG0 0 722fb4d8502Sjsg #define SDMA1_BASE__INST1_SEG1 0 723fb4d8502Sjsg #define SDMA1_BASE__INST1_SEG2 0 724fb4d8502Sjsg #define SDMA1_BASE__INST1_SEG3 0 725fb4d8502Sjsg #define SDMA1_BASE__INST1_SEG4 0 726fb4d8502Sjsg #define SDMA1_BASE__INST1_SEG5 0 727fb4d8502Sjsg 728fb4d8502Sjsg #define SDMA1_BASE__INST2_SEG0 0 729fb4d8502Sjsg #define SDMA1_BASE__INST2_SEG1 0 730fb4d8502Sjsg #define SDMA1_BASE__INST2_SEG2 0 731fb4d8502Sjsg #define SDMA1_BASE__INST2_SEG3 0 732fb4d8502Sjsg #define SDMA1_BASE__INST2_SEG4 0 733fb4d8502Sjsg #define SDMA1_BASE__INST2_SEG5 0 734fb4d8502Sjsg 735fb4d8502Sjsg #define SDMA1_BASE__INST3_SEG0 0 736fb4d8502Sjsg #define SDMA1_BASE__INST3_SEG1 0 737fb4d8502Sjsg #define SDMA1_BASE__INST3_SEG2 0 738fb4d8502Sjsg #define SDMA1_BASE__INST3_SEG3 0 739fb4d8502Sjsg #define SDMA1_BASE__INST3_SEG4 0 740fb4d8502Sjsg #define SDMA1_BASE__INST3_SEG5 0 741fb4d8502Sjsg 742fb4d8502Sjsg #define SDMA1_BASE__INST4_SEG0 0 743fb4d8502Sjsg #define SDMA1_BASE__INST4_SEG1 0 744fb4d8502Sjsg #define SDMA1_BASE__INST4_SEG2 0 745fb4d8502Sjsg #define SDMA1_BASE__INST4_SEG3 0 746fb4d8502Sjsg #define SDMA1_BASE__INST4_SEG4 0 747fb4d8502Sjsg #define SDMA1_BASE__INST4_SEG5 0 748fb4d8502Sjsg 749fb4d8502Sjsg #define SDMA1_BASE__INST5_SEG0 0 750fb4d8502Sjsg #define SDMA1_BASE__INST5_SEG1 0 751fb4d8502Sjsg #define SDMA1_BASE__INST5_SEG2 0 752fb4d8502Sjsg #define SDMA1_BASE__INST5_SEG3 0 753fb4d8502Sjsg #define SDMA1_BASE__INST5_SEG4 0 754fb4d8502Sjsg #define SDMA1_BASE__INST5_SEG5 0 755fb4d8502Sjsg 756fb4d8502Sjsg #define SMUIO_BASE__INST0_SEG0 0x00016800 757fb4d8502Sjsg #define SMUIO_BASE__INST0_SEG1 0x00016A00 758fb4d8502Sjsg #define SMUIO_BASE__INST0_SEG2 0 759fb4d8502Sjsg #define SMUIO_BASE__INST0_SEG3 0 760fb4d8502Sjsg #define SMUIO_BASE__INST0_SEG4 0 761fb4d8502Sjsg #define SMUIO_BASE__INST0_SEG5 0 762fb4d8502Sjsg 763fb4d8502Sjsg #define SMUIO_BASE__INST1_SEG0 0 764fb4d8502Sjsg #define SMUIO_BASE__INST1_SEG1 0 765fb4d8502Sjsg #define SMUIO_BASE__INST1_SEG2 0 766fb4d8502Sjsg #define SMUIO_BASE__INST1_SEG3 0 767fb4d8502Sjsg #define SMUIO_BASE__INST1_SEG4 0 768fb4d8502Sjsg #define SMUIO_BASE__INST1_SEG5 0 769fb4d8502Sjsg 770fb4d8502Sjsg #define SMUIO_BASE__INST2_SEG0 0 771fb4d8502Sjsg #define SMUIO_BASE__INST2_SEG1 0 772fb4d8502Sjsg #define SMUIO_BASE__INST2_SEG2 0 773fb4d8502Sjsg #define SMUIO_BASE__INST2_SEG3 0 774fb4d8502Sjsg #define SMUIO_BASE__INST2_SEG4 0 775fb4d8502Sjsg #define SMUIO_BASE__INST2_SEG5 0 776fb4d8502Sjsg 777fb4d8502Sjsg #define SMUIO_BASE__INST3_SEG0 0 778fb4d8502Sjsg #define SMUIO_BASE__INST3_SEG1 0 779fb4d8502Sjsg #define SMUIO_BASE__INST3_SEG2 0 780fb4d8502Sjsg #define SMUIO_BASE__INST3_SEG3 0 781fb4d8502Sjsg #define SMUIO_BASE__INST3_SEG4 0 782fb4d8502Sjsg #define SMUIO_BASE__INST3_SEG5 0 783fb4d8502Sjsg 784fb4d8502Sjsg #define SMUIO_BASE__INST4_SEG0 0 785fb4d8502Sjsg #define SMUIO_BASE__INST4_SEG1 0 786fb4d8502Sjsg #define SMUIO_BASE__INST4_SEG2 0 787fb4d8502Sjsg #define SMUIO_BASE__INST4_SEG3 0 788fb4d8502Sjsg #define SMUIO_BASE__INST4_SEG4 0 789fb4d8502Sjsg #define SMUIO_BASE__INST4_SEG5 0 790fb4d8502Sjsg 791fb4d8502Sjsg #define SMUIO_BASE__INST5_SEG0 0 792fb4d8502Sjsg #define SMUIO_BASE__INST5_SEG1 0 793fb4d8502Sjsg #define SMUIO_BASE__INST5_SEG2 0 794fb4d8502Sjsg #define SMUIO_BASE__INST5_SEG3 0 795fb4d8502Sjsg #define SMUIO_BASE__INST5_SEG4 0 796fb4d8502Sjsg #define SMUIO_BASE__INST5_SEG5 0 797fb4d8502Sjsg 798fb4d8502Sjsg #define THM_BASE__INST0_SEG0 0x00016600 799fb4d8502Sjsg #define THM_BASE__INST0_SEG1 0 800fb4d8502Sjsg #define THM_BASE__INST0_SEG2 0 801fb4d8502Sjsg #define THM_BASE__INST0_SEG3 0 802fb4d8502Sjsg #define THM_BASE__INST0_SEG4 0 803fb4d8502Sjsg #define THM_BASE__INST0_SEG5 0 804fb4d8502Sjsg 805fb4d8502Sjsg #define THM_BASE__INST1_SEG0 0 806fb4d8502Sjsg #define THM_BASE__INST1_SEG1 0 807fb4d8502Sjsg #define THM_BASE__INST1_SEG2 0 808fb4d8502Sjsg #define THM_BASE__INST1_SEG3 0 809fb4d8502Sjsg #define THM_BASE__INST1_SEG4 0 810fb4d8502Sjsg #define THM_BASE__INST1_SEG5 0 811fb4d8502Sjsg 812fb4d8502Sjsg #define THM_BASE__INST2_SEG0 0 813fb4d8502Sjsg #define THM_BASE__INST2_SEG1 0 814fb4d8502Sjsg #define THM_BASE__INST2_SEG2 0 815fb4d8502Sjsg #define THM_BASE__INST2_SEG3 0 816fb4d8502Sjsg #define THM_BASE__INST2_SEG4 0 817fb4d8502Sjsg #define THM_BASE__INST2_SEG5 0 818fb4d8502Sjsg 819fb4d8502Sjsg #define THM_BASE__INST3_SEG0 0 820fb4d8502Sjsg #define THM_BASE__INST3_SEG1 0 821fb4d8502Sjsg #define THM_BASE__INST3_SEG2 0 822fb4d8502Sjsg #define THM_BASE__INST3_SEG3 0 823fb4d8502Sjsg #define THM_BASE__INST3_SEG4 0 824fb4d8502Sjsg #define THM_BASE__INST3_SEG5 0 825fb4d8502Sjsg 826fb4d8502Sjsg #define THM_BASE__INST4_SEG0 0 827fb4d8502Sjsg #define THM_BASE__INST4_SEG1 0 828fb4d8502Sjsg #define THM_BASE__INST4_SEG2 0 829fb4d8502Sjsg #define THM_BASE__INST4_SEG3 0 830fb4d8502Sjsg #define THM_BASE__INST4_SEG4 0 831fb4d8502Sjsg #define THM_BASE__INST4_SEG5 0 832fb4d8502Sjsg 833fb4d8502Sjsg #define THM_BASE__INST5_SEG0 0 834fb4d8502Sjsg #define THM_BASE__INST5_SEG1 0 835fb4d8502Sjsg #define THM_BASE__INST5_SEG2 0 836fb4d8502Sjsg #define THM_BASE__INST5_SEG3 0 837fb4d8502Sjsg #define THM_BASE__INST5_SEG4 0 838fb4d8502Sjsg #define THM_BASE__INST5_SEG5 0 839fb4d8502Sjsg 840fb4d8502Sjsg #define UMC_BASE__INST0_SEG0 0x00014000 841fb4d8502Sjsg #define UMC_BASE__INST0_SEG1 0 842fb4d8502Sjsg #define UMC_BASE__INST0_SEG2 0 843fb4d8502Sjsg #define UMC_BASE__INST0_SEG3 0 844fb4d8502Sjsg #define UMC_BASE__INST0_SEG4 0 845fb4d8502Sjsg #define UMC_BASE__INST0_SEG5 0 846fb4d8502Sjsg 847fb4d8502Sjsg #define UMC_BASE__INST1_SEG0 0 848fb4d8502Sjsg #define UMC_BASE__INST1_SEG1 0 849fb4d8502Sjsg #define UMC_BASE__INST1_SEG2 0 850fb4d8502Sjsg #define UMC_BASE__INST1_SEG3 0 851fb4d8502Sjsg #define UMC_BASE__INST1_SEG4 0 852fb4d8502Sjsg #define UMC_BASE__INST1_SEG5 0 853fb4d8502Sjsg 854fb4d8502Sjsg #define UMC_BASE__INST2_SEG0 0 855fb4d8502Sjsg #define UMC_BASE__INST2_SEG1 0 856fb4d8502Sjsg #define UMC_BASE__INST2_SEG2 0 857fb4d8502Sjsg #define UMC_BASE__INST2_SEG3 0 858fb4d8502Sjsg #define UMC_BASE__INST2_SEG4 0 859fb4d8502Sjsg #define UMC_BASE__INST2_SEG5 0 860fb4d8502Sjsg 861fb4d8502Sjsg #define UMC_BASE__INST3_SEG0 0 862fb4d8502Sjsg #define UMC_BASE__INST3_SEG1 0 863fb4d8502Sjsg #define UMC_BASE__INST3_SEG2 0 864fb4d8502Sjsg #define UMC_BASE__INST3_SEG3 0 865fb4d8502Sjsg #define UMC_BASE__INST3_SEG4 0 866fb4d8502Sjsg #define UMC_BASE__INST3_SEG5 0 867fb4d8502Sjsg 868fb4d8502Sjsg #define UMC_BASE__INST4_SEG0 0 869fb4d8502Sjsg #define UMC_BASE__INST4_SEG1 0 870fb4d8502Sjsg #define UMC_BASE__INST4_SEG2 0 871fb4d8502Sjsg #define UMC_BASE__INST4_SEG3 0 872fb4d8502Sjsg #define UMC_BASE__INST4_SEG4 0 873fb4d8502Sjsg #define UMC_BASE__INST4_SEG5 0 874fb4d8502Sjsg 875fb4d8502Sjsg #define UMC_BASE__INST5_SEG0 0 876fb4d8502Sjsg #define UMC_BASE__INST5_SEG1 0 877fb4d8502Sjsg #define UMC_BASE__INST5_SEG2 0 878fb4d8502Sjsg #define UMC_BASE__INST5_SEG3 0 879fb4d8502Sjsg #define UMC_BASE__INST5_SEG4 0 880fb4d8502Sjsg #define UMC_BASE__INST5_SEG5 0 881fb4d8502Sjsg 882fb4d8502Sjsg #define UVD_BASE__INST0_SEG0 0x00007800 883fb4d8502Sjsg #define UVD_BASE__INST0_SEG1 0x00007E00 884fb4d8502Sjsg #define UVD_BASE__INST0_SEG2 0 885fb4d8502Sjsg #define UVD_BASE__INST0_SEG3 0 886fb4d8502Sjsg #define UVD_BASE__INST0_SEG4 0 887fb4d8502Sjsg #define UVD_BASE__INST0_SEG5 0 888fb4d8502Sjsg 889fb4d8502Sjsg #define UVD_BASE__INST1_SEG0 0 890fb4d8502Sjsg #define UVD_BASE__INST1_SEG1 0x00009000 891fb4d8502Sjsg #define UVD_BASE__INST1_SEG2 0 892fb4d8502Sjsg #define UVD_BASE__INST1_SEG3 0 893fb4d8502Sjsg #define UVD_BASE__INST1_SEG4 0 894fb4d8502Sjsg #define UVD_BASE__INST1_SEG5 0 895fb4d8502Sjsg 896fb4d8502Sjsg #define UVD_BASE__INST2_SEG0 0 897fb4d8502Sjsg #define UVD_BASE__INST2_SEG1 0 898fb4d8502Sjsg #define UVD_BASE__INST2_SEG2 0 899fb4d8502Sjsg #define UVD_BASE__INST2_SEG3 0 900fb4d8502Sjsg #define UVD_BASE__INST2_SEG4 0 901fb4d8502Sjsg #define UVD_BASE__INST2_SEG5 0 902fb4d8502Sjsg 903fb4d8502Sjsg #define UVD_BASE__INST3_SEG0 0 904fb4d8502Sjsg #define UVD_BASE__INST3_SEG1 0 905fb4d8502Sjsg #define UVD_BASE__INST3_SEG2 0 906fb4d8502Sjsg #define UVD_BASE__INST3_SEG3 0 907fb4d8502Sjsg #define UVD_BASE__INST3_SEG4 0 908fb4d8502Sjsg #define UVD_BASE__INST3_SEG5 0 909fb4d8502Sjsg 910fb4d8502Sjsg #define UVD_BASE__INST4_SEG0 0 911fb4d8502Sjsg #define UVD_BASE__INST4_SEG1 0 912fb4d8502Sjsg #define UVD_BASE__INST4_SEG2 0 913fb4d8502Sjsg #define UVD_BASE__INST4_SEG3 0 914fb4d8502Sjsg #define UVD_BASE__INST4_SEG4 0 915fb4d8502Sjsg #define UVD_BASE__INST4_SEG5 0 916fb4d8502Sjsg 917fb4d8502Sjsg #define UVD_BASE__INST5_SEG0 0 918fb4d8502Sjsg #define UVD_BASE__INST5_SEG1 0 919fb4d8502Sjsg #define UVD_BASE__INST5_SEG2 0 920fb4d8502Sjsg #define UVD_BASE__INST5_SEG3 0 921fb4d8502Sjsg #define UVD_BASE__INST5_SEG4 0 922fb4d8502Sjsg #define UVD_BASE__INST5_SEG5 0 923fb4d8502Sjsg 924fb4d8502Sjsg #define VCE_BASE__INST0_SEG0 0x00008800 925fb4d8502Sjsg #define VCE_BASE__INST0_SEG1 0 926fb4d8502Sjsg #define VCE_BASE__INST0_SEG2 0 927fb4d8502Sjsg #define VCE_BASE__INST0_SEG3 0 928fb4d8502Sjsg #define VCE_BASE__INST0_SEG4 0 929fb4d8502Sjsg #define VCE_BASE__INST0_SEG5 0 930fb4d8502Sjsg 931fb4d8502Sjsg #define VCE_BASE__INST1_SEG0 0 932fb4d8502Sjsg #define VCE_BASE__INST1_SEG1 0 933fb4d8502Sjsg #define VCE_BASE__INST1_SEG2 0 934fb4d8502Sjsg #define VCE_BASE__INST1_SEG3 0 935fb4d8502Sjsg #define VCE_BASE__INST1_SEG4 0 936fb4d8502Sjsg #define VCE_BASE__INST1_SEG5 0 937fb4d8502Sjsg 938fb4d8502Sjsg #define VCE_BASE__INST2_SEG0 0 939fb4d8502Sjsg #define VCE_BASE__INST2_SEG1 0 940fb4d8502Sjsg #define VCE_BASE__INST2_SEG2 0 941fb4d8502Sjsg #define VCE_BASE__INST2_SEG3 0 942fb4d8502Sjsg #define VCE_BASE__INST2_SEG4 0 943fb4d8502Sjsg #define VCE_BASE__INST2_SEG5 0 944fb4d8502Sjsg 945fb4d8502Sjsg #define VCE_BASE__INST3_SEG0 0 946fb4d8502Sjsg #define VCE_BASE__INST3_SEG1 0 947fb4d8502Sjsg #define VCE_BASE__INST3_SEG2 0 948fb4d8502Sjsg #define VCE_BASE__INST3_SEG3 0 949fb4d8502Sjsg #define VCE_BASE__INST3_SEG4 0 950fb4d8502Sjsg #define VCE_BASE__INST3_SEG5 0 951fb4d8502Sjsg 952fb4d8502Sjsg #define VCE_BASE__INST4_SEG0 0 953fb4d8502Sjsg #define VCE_BASE__INST4_SEG1 0 954fb4d8502Sjsg #define VCE_BASE__INST4_SEG2 0 955fb4d8502Sjsg #define VCE_BASE__INST4_SEG3 0 956fb4d8502Sjsg #define VCE_BASE__INST4_SEG4 0 957fb4d8502Sjsg #define VCE_BASE__INST4_SEG5 0 958fb4d8502Sjsg 959fb4d8502Sjsg #define VCE_BASE__INST5_SEG0 0 960fb4d8502Sjsg #define VCE_BASE__INST5_SEG1 0 961fb4d8502Sjsg #define VCE_BASE__INST5_SEG2 0 962fb4d8502Sjsg #define VCE_BASE__INST5_SEG3 0 963fb4d8502Sjsg #define VCE_BASE__INST5_SEG4 0 964fb4d8502Sjsg #define VCE_BASE__INST5_SEG5 0 965fb4d8502Sjsg 966fb4d8502Sjsg #define XDMA_BASE__INST0_SEG0 0x00003400 967fb4d8502Sjsg #define XDMA_BASE__INST0_SEG1 0 968fb4d8502Sjsg #define XDMA_BASE__INST0_SEG2 0 969fb4d8502Sjsg #define XDMA_BASE__INST0_SEG3 0 970fb4d8502Sjsg #define XDMA_BASE__INST0_SEG4 0 971fb4d8502Sjsg #define XDMA_BASE__INST0_SEG5 0 972fb4d8502Sjsg 973fb4d8502Sjsg #define XDMA_BASE__INST1_SEG0 0 974fb4d8502Sjsg #define XDMA_BASE__INST1_SEG1 0 975fb4d8502Sjsg #define XDMA_BASE__INST1_SEG2 0 976fb4d8502Sjsg #define XDMA_BASE__INST1_SEG3 0 977fb4d8502Sjsg #define XDMA_BASE__INST1_SEG4 0 978fb4d8502Sjsg #define XDMA_BASE__INST1_SEG5 0 979fb4d8502Sjsg 980fb4d8502Sjsg #define XDMA_BASE__INST2_SEG0 0 981fb4d8502Sjsg #define XDMA_BASE__INST2_SEG1 0 982fb4d8502Sjsg #define XDMA_BASE__INST2_SEG2 0 983fb4d8502Sjsg #define XDMA_BASE__INST2_SEG3 0 984fb4d8502Sjsg #define XDMA_BASE__INST2_SEG4 0 985fb4d8502Sjsg #define XDMA_BASE__INST2_SEG5 0 986fb4d8502Sjsg 987fb4d8502Sjsg #define XDMA_BASE__INST3_SEG0 0 988fb4d8502Sjsg #define XDMA_BASE__INST3_SEG1 0 989fb4d8502Sjsg #define XDMA_BASE__INST3_SEG2 0 990fb4d8502Sjsg #define XDMA_BASE__INST3_SEG3 0 991fb4d8502Sjsg #define XDMA_BASE__INST3_SEG4 0 992fb4d8502Sjsg #define XDMA_BASE__INST3_SEG5 0 993fb4d8502Sjsg 994fb4d8502Sjsg #define XDMA_BASE__INST4_SEG0 0 995fb4d8502Sjsg #define XDMA_BASE__INST4_SEG1 0 996fb4d8502Sjsg #define XDMA_BASE__INST4_SEG2 0 997fb4d8502Sjsg #define XDMA_BASE__INST4_SEG3 0 998fb4d8502Sjsg #define XDMA_BASE__INST4_SEG4 0 999fb4d8502Sjsg #define XDMA_BASE__INST4_SEG5 0 1000fb4d8502Sjsg 1001fb4d8502Sjsg #define XDMA_BASE__INST5_SEG0 0 1002fb4d8502Sjsg #define XDMA_BASE__INST5_SEG1 0 1003fb4d8502Sjsg #define XDMA_BASE__INST5_SEG2 0 1004fb4d8502Sjsg #define XDMA_BASE__INST5_SEG3 0 1005fb4d8502Sjsg #define XDMA_BASE__INST5_SEG4 0 1006fb4d8502Sjsg #define XDMA_BASE__INST5_SEG5 0 1007fb4d8502Sjsg 1008fb4d8502Sjsg #define RSMU_BASE__INST0_SEG0 0x00012000 1009fb4d8502Sjsg #define RSMU_BASE__INST0_SEG1 0 1010fb4d8502Sjsg #define RSMU_BASE__INST0_SEG2 0 1011fb4d8502Sjsg #define RSMU_BASE__INST0_SEG3 0 1012fb4d8502Sjsg #define RSMU_BASE__INST0_SEG4 0 1013fb4d8502Sjsg #define RSMU_BASE__INST0_SEG5 0 1014fb4d8502Sjsg 1015fb4d8502Sjsg #define RSMU_BASE__INST1_SEG0 0 1016fb4d8502Sjsg #define RSMU_BASE__INST1_SEG1 0 1017fb4d8502Sjsg #define RSMU_BASE__INST1_SEG2 0 1018fb4d8502Sjsg #define RSMU_BASE__INST1_SEG3 0 1019fb4d8502Sjsg #define RSMU_BASE__INST1_SEG4 0 1020fb4d8502Sjsg #define RSMU_BASE__INST1_SEG5 0 1021fb4d8502Sjsg 1022fb4d8502Sjsg #define RSMU_BASE__INST2_SEG0 0 1023fb4d8502Sjsg #define RSMU_BASE__INST2_SEG1 0 1024fb4d8502Sjsg #define RSMU_BASE__INST2_SEG2 0 1025fb4d8502Sjsg #define RSMU_BASE__INST2_SEG3 0 1026fb4d8502Sjsg #define RSMU_BASE__INST2_SEG4 0 1027fb4d8502Sjsg #define RSMU_BASE__INST2_SEG5 0 1028fb4d8502Sjsg 1029fb4d8502Sjsg #define RSMU_BASE__INST3_SEG0 0 1030fb4d8502Sjsg #define RSMU_BASE__INST3_SEG1 0 1031fb4d8502Sjsg #define RSMU_BASE__INST3_SEG2 0 1032fb4d8502Sjsg #define RSMU_BASE__INST3_SEG3 0 1033fb4d8502Sjsg #define RSMU_BASE__INST3_SEG4 0 1034fb4d8502Sjsg #define RSMU_BASE__INST3_SEG5 0 1035fb4d8502Sjsg 1036fb4d8502Sjsg #define RSMU_BASE__INST4_SEG0 0 1037fb4d8502Sjsg #define RSMU_BASE__INST4_SEG1 0 1038fb4d8502Sjsg #define RSMU_BASE__INST4_SEG2 0 1039fb4d8502Sjsg #define RSMU_BASE__INST4_SEG3 0 1040fb4d8502Sjsg #define RSMU_BASE__INST4_SEG4 0 1041fb4d8502Sjsg #define RSMU_BASE__INST4_SEG5 0 1042fb4d8502Sjsg 1043fb4d8502Sjsg #define RSMU_BASE__INST5_SEG0 0 1044fb4d8502Sjsg #define RSMU_BASE__INST5_SEG1 0 1045fb4d8502Sjsg #define RSMU_BASE__INST5_SEG2 0 1046fb4d8502Sjsg #define RSMU_BASE__INST5_SEG3 0 1047fb4d8502Sjsg #define RSMU_BASE__INST5_SEG4 0 1048fb4d8502Sjsg #define RSMU_BASE__INST5_SEG5 0 1049fb4d8502Sjsg 1050fb4d8502Sjsg #endif 1051fb4d8502Sjsg 1052