1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/kernel.h> 35 #include <linux/module.h> 36 #include <linux/pci.h> 37 #include <linux/slab.h> 38 #include <linux/vga_switcheroo.h> 39 40 #include <drm/drm_displayid.h> 41 #include <drm/drm_drv.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_print.h> 45 46 #include "drm_crtc_internal.h" 47 48 static int oui(u8 first, u8 second, u8 third) 49 { 50 return (first << 16) | (second << 8) | third; 51 } 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* use +hsync +vsync for detailed mode */ 77 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 78 /* Force reduced-blanking timings for detailed modes */ 79 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 80 /* Force 8bpc */ 81 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 82 /* Force 12bpc */ 83 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 84 /* Force 6bpc */ 85 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 86 /* Force 10bpc */ 87 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 88 /* Non desktop display (i.e. HMD) */ 89 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 90 /* Cap the DSC target bitrate to 15bpp */ 91 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 92 93 #define MICROSOFT_IEEE_OUI 0xca125c 94 95 struct detailed_mode_closure { 96 struct drm_connector *connector; 97 const struct drm_edid *drm_edid; 98 bool preferred; 99 int modes; 100 }; 101 102 #define LEVEL_DMT 0 103 #define LEVEL_GTF 1 104 #define LEVEL_GTF2 2 105 #define LEVEL_CVT 3 106 107 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 108 { \ 109 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \ 110 product_id), \ 111 .quirks = _quirks \ 112 } 113 114 static const struct edid_quirk { 115 u32 panel_id; 116 u32 quirks; 117 } edid_quirk_list[] = { 118 /* Acer AL1706 */ 119 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 120 /* Acer F51 */ 121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 122 123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 125 126 /* BenQ GW2765 */ 127 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC), 128 129 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 131 132 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 134 135 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 137 138 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 139 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 140 141 /* Belinea 10 15 55 */ 142 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 143 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 144 145 /* Envision Peripherals, Inc. EN-7100e */ 146 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 147 /* Envision EN2028 */ 148 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 149 150 /* Funai Electronics PM36B */ 151 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 152 EDID_QUIRK_DETAILED_IN_CM), 153 154 /* LG 27GP950 */ 155 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 156 157 /* LG 27GN950 */ 158 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 159 160 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 161 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 162 163 /* LG Philips LCD LP154W01-A5 */ 164 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 165 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 166 167 /* Samsung SyncMaster 205BW. Note: irony */ 168 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 169 /* Samsung SyncMaster 22[5-6]BW */ 170 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 171 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 172 173 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 174 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 175 176 /* ViewSonic VA2026w */ 177 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 178 179 /* Medion MD 30217 PG */ 180 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 181 182 /* Lenovo G50 */ 183 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 184 185 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 186 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 187 188 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 189 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 190 191 /* Valve Index Headset */ 192 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 193 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 194 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 195 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 196 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 197 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 198 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 199 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 200 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 201 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 202 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 203 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 204 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 209 210 /* HTC Vive and Vive Pro VR Headsets */ 211 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 213 214 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 215 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 217 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 218 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 219 220 /* Windows Mixed Reality Headsets */ 221 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 222 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 223 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 224 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 225 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 226 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 227 228 /* Sony PlayStation VR Headset */ 229 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 230 231 /* Sensics VR Headsets */ 232 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 233 234 /* OSVR HDK and HDK2 VR Headsets */ 235 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 236 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), 237 }; 238 239 /* 240 * Autogenerated from the DMT spec. 241 * This table is copied from xfree86/modes/xf86EdidModes.c. 242 */ 243 static const struct drm_display_mode drm_dmt_modes[] = { 244 /* 0x01 - 640x350@85Hz */ 245 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 246 736, 832, 0, 350, 382, 385, 445, 0, 247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x02 - 640x400@85Hz */ 249 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 250 736, 832, 0, 400, 401, 404, 445, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x03 - 720x400@85Hz */ 253 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 254 828, 936, 0, 400, 401, 404, 446, 0, 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 256 /* 0x04 - 640x480@60Hz */ 257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 258 752, 800, 0, 480, 490, 492, 525, 0, 259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x05 - 640x480@72Hz */ 261 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 262 704, 832, 0, 480, 489, 492, 520, 0, 263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 264 /* 0x06 - 640x480@75Hz */ 265 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 266 720, 840, 0, 480, 481, 484, 500, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 268 /* 0x07 - 640x480@85Hz */ 269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 270 752, 832, 0, 480, 481, 484, 509, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 272 /* 0x08 - 800x600@56Hz */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 274 896, 1024, 0, 600, 601, 603, 625, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x09 - 800x600@60Hz */ 277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 278 968, 1056, 0, 600, 601, 605, 628, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0a - 800x600@72Hz */ 281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 282 976, 1040, 0, 600, 637, 643, 666, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 284 /* 0x0b - 800x600@75Hz */ 285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 286 896, 1056, 0, 600, 601, 604, 625, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x0c - 800x600@85Hz */ 289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 290 896, 1048, 0, 600, 601, 604, 631, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x0d - 800x600@120Hz RB */ 293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 294 880, 960, 0, 600, 603, 607, 636, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 296 /* 0x0e - 848x480@60Hz */ 297 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 298 976, 1088, 0, 480, 486, 494, 517, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x0f - 1024x768@43Hz, interlace */ 301 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 302 1208, 1264, 0, 768, 768, 776, 817, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 304 DRM_MODE_FLAG_INTERLACE) }, 305 /* 0x10 - 1024x768@60Hz */ 306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 307 1184, 1344, 0, 768, 771, 777, 806, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x11 - 1024x768@70Hz */ 310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 311 1184, 1328, 0, 768, 771, 777, 806, 0, 312 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 313 /* 0x12 - 1024x768@75Hz */ 314 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 315 1136, 1312, 0, 768, 769, 772, 800, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 317 /* 0x13 - 1024x768@85Hz */ 318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 319 1168, 1376, 0, 768, 769, 772, 808, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x14 - 1024x768@120Hz RB */ 322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 323 1104, 1184, 0, 768, 771, 775, 813, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 325 /* 0x15 - 1152x864@75Hz */ 326 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 327 1344, 1600, 0, 864, 865, 868, 900, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x55 - 1280x720@60Hz */ 330 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 331 1430, 1650, 0, 720, 725, 730, 750, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x16 - 1280x768@60Hz RB */ 334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 335 1360, 1440, 0, 768, 771, 778, 790, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x17 - 1280x768@60Hz */ 338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 339 1472, 1664, 0, 768, 771, 778, 798, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x18 - 1280x768@75Hz */ 342 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 343 1488, 1696, 0, 768, 771, 778, 805, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x19 - 1280x768@85Hz */ 346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 347 1496, 1712, 0, 768, 771, 778, 809, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1a - 1280x768@120Hz RB */ 350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 351 1360, 1440, 0, 768, 771, 778, 813, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x1b - 1280x800@60Hz RB */ 354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 355 1360, 1440, 0, 800, 803, 809, 823, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 357 /* 0x1c - 1280x800@60Hz */ 358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 359 1480, 1680, 0, 800, 803, 809, 831, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x1d - 1280x800@75Hz */ 362 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 363 1488, 1696, 0, 800, 803, 809, 838, 0, 364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 0x1e - 1280x800@85Hz */ 366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 367 1496, 1712, 0, 800, 803, 809, 843, 0, 368 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x1f - 1280x800@120Hz RB */ 370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 371 1360, 1440, 0, 800, 803, 809, 847, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 373 /* 0x20 - 1280x960@60Hz */ 374 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 375 1488, 1800, 0, 960, 961, 964, 1000, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x21 - 1280x960@85Hz */ 378 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 379 1504, 1728, 0, 960, 961, 964, 1011, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x22 - 1280x960@120Hz RB */ 382 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 383 1360, 1440, 0, 960, 963, 967, 1017, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 385 /* 0x23 - 1280x1024@60Hz */ 386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 387 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x24 - 1280x1024@75Hz */ 390 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 391 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x25 - 1280x1024@85Hz */ 394 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 395 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x26 - 1280x1024@120Hz RB */ 398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 399 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 401 /* 0x27 - 1360x768@60Hz */ 402 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 403 1536, 1792, 0, 768, 771, 777, 795, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x28 - 1360x768@120Hz RB */ 406 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 407 1440, 1520, 0, 768, 771, 776, 813, 0, 408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 409 /* 0x51 - 1366x768@60Hz */ 410 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 411 1579, 1792, 0, 768, 771, 774, 798, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x56 - 1366x768@60Hz */ 414 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 415 1436, 1500, 0, 768, 769, 772, 800, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x29 - 1400x1050@60Hz RB */ 418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 419 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x2a - 1400x1050@60Hz */ 422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 423 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x2b - 1400x1050@75Hz */ 426 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 427 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x2c - 1400x1050@85Hz */ 430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 431 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x2d - 1400x1050@120Hz RB */ 434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 435 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x2e - 1440x900@60Hz RB */ 438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 439 1520, 1600, 0, 900, 903, 909, 926, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 441 /* 0x2f - 1440x900@60Hz */ 442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 443 1672, 1904, 0, 900, 903, 909, 934, 0, 444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x30 - 1440x900@75Hz */ 446 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 447 1688, 1936, 0, 900, 903, 909, 942, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x31 - 1440x900@85Hz */ 450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 451 1696, 1952, 0, 900, 903, 909, 948, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x32 - 1440x900@120Hz RB */ 454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 455 1520, 1600, 0, 900, 903, 909, 953, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 457 /* 0x53 - 1600x900@60Hz */ 458 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 459 1704, 1800, 0, 900, 901, 904, 1000, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x33 - 1600x1200@60Hz */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x34 - 1600x1200@65Hz */ 466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x35 - 1600x1200@70Hz */ 470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 471 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x36 - 1600x1200@75Hz */ 474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x37 - 1600x1200@85Hz */ 478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x38 - 1600x1200@120Hz RB */ 482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 483 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 485 /* 0x39 - 1680x1050@60Hz RB */ 486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 487 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 489 /* 0x3a - 1680x1050@60Hz */ 490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 491 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x3b - 1680x1050@75Hz */ 494 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 495 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 497 /* 0x3c - 1680x1050@85Hz */ 498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 499 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x3d - 1680x1050@120Hz RB */ 502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 503 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 505 /* 0x3e - 1792x1344@60Hz */ 506 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 507 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 509 /* 0x3f - 1792x1344@75Hz */ 510 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 511 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 513 /* 0x40 - 1792x1344@120Hz RB */ 514 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 515 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x41 - 1856x1392@60Hz */ 518 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 519 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x42 - 1856x1392@75Hz */ 522 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 523 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x43 - 1856x1392@120Hz RB */ 526 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 527 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 529 /* 0x52 - 1920x1080@60Hz */ 530 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 531 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 533 /* 0x44 - 1920x1200@60Hz RB */ 534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 535 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 537 /* 0x45 - 1920x1200@60Hz */ 538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 539 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 541 /* 0x46 - 1920x1200@75Hz */ 542 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 543 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 545 /* 0x47 - 1920x1200@85Hz */ 546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 547 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 549 /* 0x48 - 1920x1200@120Hz RB */ 550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 551 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 553 /* 0x49 - 1920x1440@60Hz */ 554 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 555 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4a - 1920x1440@75Hz */ 558 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 559 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x4b - 1920x1440@120Hz RB */ 562 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 563 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 565 /* 0x54 - 2048x1152@60Hz */ 566 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 567 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 569 /* 0x4c - 2560x1600@60Hz RB */ 570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 571 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 573 /* 0x4d - 2560x1600@60Hz */ 574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 575 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 576 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 577 /* 0x4e - 2560x1600@75Hz */ 578 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 579 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 581 /* 0x4f - 2560x1600@85Hz */ 582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 583 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 584 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 585 /* 0x50 - 2560x1600@120Hz RB */ 586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 587 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 589 /* 0x57 - 4096x2160@60Hz RB */ 590 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 591 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 593 /* 0x58 - 4096x2160@59.94Hz RB */ 594 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 595 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 597 }; 598 599 /* 600 * These more or less come from the DMT spec. The 720x400 modes are 601 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 602 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 603 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 604 * mode. 605 * 606 * The DMT modes have been fact-checked; the rest are mild guesses. 607 */ 608 static const struct drm_display_mode edid_est_modes[] = { 609 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 610 968, 1056, 0, 600, 601, 605, 628, 0, 611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 613 896, 1024, 0, 600, 601, 603, 625, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 615 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 616 720, 840, 0, 480, 481, 484, 500, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 619 704, 832, 0, 480, 489, 492, 520, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 622 768, 864, 0, 480, 483, 486, 525, 0, 623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 625 752, 800, 0, 480, 490, 492, 525, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 627 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 628 846, 900, 0, 400, 421, 423, 449, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 631 846, 900, 0, 400, 412, 414, 449, 0, 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 633 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 634 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 636 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 637 1136, 1312, 0, 768, 769, 772, 800, 0, 638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 640 1184, 1328, 0, 768, 771, 777, 806, 0, 641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 643 1184, 1344, 0, 768, 771, 777, 806, 0, 644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 645 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 646 1208, 1264, 0, 768, 768, 776, 817, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 648 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 649 928, 1152, 0, 624, 625, 628, 667, 0, 650 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 651 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 652 896, 1056, 0, 600, 601, 604, 625, 0, 653 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 655 976, 1040, 0, 600, 637, 643, 666, 0, 656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 657 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 658 1344, 1600, 0, 864, 865, 868, 900, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 660 }; 661 662 struct minimode { 663 short w; 664 short h; 665 short r; 666 short rb; 667 }; 668 669 static const struct minimode est3_modes[] = { 670 /* byte 6 */ 671 { 640, 350, 85, 0 }, 672 { 640, 400, 85, 0 }, 673 { 720, 400, 85, 0 }, 674 { 640, 480, 85, 0 }, 675 { 848, 480, 60, 0 }, 676 { 800, 600, 85, 0 }, 677 { 1024, 768, 85, 0 }, 678 { 1152, 864, 75, 0 }, 679 /* byte 7 */ 680 { 1280, 768, 60, 1 }, 681 { 1280, 768, 60, 0 }, 682 { 1280, 768, 75, 0 }, 683 { 1280, 768, 85, 0 }, 684 { 1280, 960, 60, 0 }, 685 { 1280, 960, 85, 0 }, 686 { 1280, 1024, 60, 0 }, 687 { 1280, 1024, 85, 0 }, 688 /* byte 8 */ 689 { 1360, 768, 60, 0 }, 690 { 1440, 900, 60, 1 }, 691 { 1440, 900, 60, 0 }, 692 { 1440, 900, 75, 0 }, 693 { 1440, 900, 85, 0 }, 694 { 1400, 1050, 60, 1 }, 695 { 1400, 1050, 60, 0 }, 696 { 1400, 1050, 75, 0 }, 697 /* byte 9 */ 698 { 1400, 1050, 85, 0 }, 699 { 1680, 1050, 60, 1 }, 700 { 1680, 1050, 60, 0 }, 701 { 1680, 1050, 75, 0 }, 702 { 1680, 1050, 85, 0 }, 703 { 1600, 1200, 60, 0 }, 704 { 1600, 1200, 65, 0 }, 705 { 1600, 1200, 70, 0 }, 706 /* byte 10 */ 707 { 1600, 1200, 75, 0 }, 708 { 1600, 1200, 85, 0 }, 709 { 1792, 1344, 60, 0 }, 710 { 1792, 1344, 75, 0 }, 711 { 1856, 1392, 60, 0 }, 712 { 1856, 1392, 75, 0 }, 713 { 1920, 1200, 60, 1 }, 714 { 1920, 1200, 60, 0 }, 715 /* byte 11 */ 716 { 1920, 1200, 75, 0 }, 717 { 1920, 1200, 85, 0 }, 718 { 1920, 1440, 60, 0 }, 719 { 1920, 1440, 75, 0 }, 720 }; 721 722 static const struct minimode extra_modes[] = { 723 { 1024, 576, 60, 0 }, 724 { 1366, 768, 60, 0 }, 725 { 1600, 900, 60, 0 }, 726 { 1680, 945, 60, 0 }, 727 { 1920, 1080, 60, 0 }, 728 { 2048, 1152, 60, 0 }, 729 { 2048, 1536, 60, 0 }, 730 }; 731 732 /* 733 * From CEA/CTA-861 spec. 734 * 735 * Do not access directly, instead always use cea_mode_for_vic(). 736 */ 737 static const struct drm_display_mode edid_cea_modes_1[] = { 738 /* 1 - 640x480@60Hz 4:3 */ 739 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 740 752, 800, 0, 480, 490, 492, 525, 0, 741 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 742 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 743 /* 2 - 720x480@60Hz 4:3 */ 744 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 745 798, 858, 0, 480, 489, 495, 525, 0, 746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 747 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 748 /* 3 - 720x480@60Hz 16:9 */ 749 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 750 798, 858, 0, 480, 489, 495, 525, 0, 751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 752 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 4 - 1280x720@60Hz 16:9 */ 754 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 755 1430, 1650, 0, 720, 725, 730, 750, 0, 756 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 757 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 758 /* 5 - 1920x1080i@60Hz 16:9 */ 759 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 760 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 761 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 762 DRM_MODE_FLAG_INTERLACE), 763 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 764 /* 6 - 720(1440)x480i@60Hz 4:3 */ 765 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 766 801, 858, 0, 480, 488, 494, 525, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 768 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 770 /* 7 - 720(1440)x480i@60Hz 16:9 */ 771 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 772 801, 858, 0, 480, 488, 494, 525, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 774 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 8 - 720(1440)x240@60Hz 4:3 */ 777 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 778 801, 858, 0, 240, 244, 247, 262, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 780 DRM_MODE_FLAG_DBLCLK), 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 782 /* 9 - 720(1440)x240@60Hz 16:9 */ 783 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 784 801, 858, 0, 240, 244, 247, 262, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 786 DRM_MODE_FLAG_DBLCLK), 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 788 /* 10 - 2880x480i@60Hz 4:3 */ 789 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 790 3204, 3432, 0, 480, 488, 494, 525, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 792 DRM_MODE_FLAG_INTERLACE), 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 11 - 2880x480i@60Hz 16:9 */ 795 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 796 3204, 3432, 0, 480, 488, 494, 525, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 798 DRM_MODE_FLAG_INTERLACE), 799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 12 - 2880x240@60Hz 4:3 */ 801 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 802 3204, 3432, 0, 240, 244, 247, 262, 0, 803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 804 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 805 /* 13 - 2880x240@60Hz 16:9 */ 806 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 807 3204, 3432, 0, 240, 244, 247, 262, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 810 /* 14 - 1440x480@60Hz 4:3 */ 811 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 812 1596, 1716, 0, 480, 489, 495, 525, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 814 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 815 /* 15 - 1440x480@60Hz 16:9 */ 816 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 817 1596, 1716, 0, 480, 489, 495, 525, 0, 818 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 819 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 820 /* 16 - 1920x1080@60Hz 16:9 */ 821 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 822 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 824 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 825 /* 17 - 720x576@50Hz 4:3 */ 826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 827 796, 864, 0, 576, 581, 586, 625, 0, 828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 829 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 830 /* 18 - 720x576@50Hz 16:9 */ 831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 832 796, 864, 0, 576, 581, 586, 625, 0, 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 834 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 835 /* 19 - 1280x720@50Hz 16:9 */ 836 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 837 1760, 1980, 0, 720, 725, 730, 750, 0, 838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 839 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 840 /* 20 - 1920x1080i@50Hz 16:9 */ 841 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 842 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 844 DRM_MODE_FLAG_INTERLACE), 845 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 21 - 720(1440)x576i@50Hz 4:3 */ 847 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 848 795, 864, 0, 576, 580, 586, 625, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 850 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 852 /* 22 - 720(1440)x576i@50Hz 16:9 */ 853 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 854 795, 864, 0, 576, 580, 586, 625, 0, 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 856 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 23 - 720(1440)x288@50Hz 4:3 */ 859 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 860 795, 864, 0, 288, 290, 293, 312, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_DBLCLK), 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 864 /* 24 - 720(1440)x288@50Hz 16:9 */ 865 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 866 795, 864, 0, 288, 290, 293, 312, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 868 DRM_MODE_FLAG_DBLCLK), 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 25 - 2880x576i@50Hz 4:3 */ 871 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 872 3180, 3456, 0, 576, 580, 586, 625, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 874 DRM_MODE_FLAG_INTERLACE), 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 876 /* 26 - 2880x576i@50Hz 16:9 */ 877 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 878 3180, 3456, 0, 576, 580, 586, 625, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 880 DRM_MODE_FLAG_INTERLACE), 881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 27 - 2880x288@50Hz 4:3 */ 883 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 884 3180, 3456, 0, 288, 290, 293, 312, 0, 885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 886 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 887 /* 28 - 2880x288@50Hz 16:9 */ 888 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 889 3180, 3456, 0, 288, 290, 293, 312, 0, 890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 891 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 29 - 1440x576@50Hz 4:3 */ 893 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 894 1592, 1728, 0, 576, 581, 586, 625, 0, 895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 896 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 897 /* 30 - 1440x576@50Hz 16:9 */ 898 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 899 1592, 1728, 0, 576, 581, 586, 625, 0, 900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 901 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 902 /* 31 - 1920x1080@50Hz 16:9 */ 903 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 904 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 906 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 907 /* 32 - 1920x1080@24Hz 16:9 */ 908 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 909 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 911 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 912 /* 33 - 1920x1080@25Hz 16:9 */ 913 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 914 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 915 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 916 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 917 /* 34 - 1920x1080@30Hz 16:9 */ 918 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 919 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 920 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 921 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 922 /* 35 - 2880x480@60Hz 4:3 */ 923 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 924 3192, 3432, 0, 480, 489, 495, 525, 0, 925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 926 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 927 /* 36 - 2880x480@60Hz 16:9 */ 928 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 929 3192, 3432, 0, 480, 489, 495, 525, 0, 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 931 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 932 /* 37 - 2880x576@50Hz 4:3 */ 933 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 934 3184, 3456, 0, 576, 581, 586, 625, 0, 935 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 936 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 937 /* 38 - 2880x576@50Hz 16:9 */ 938 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 939 3184, 3456, 0, 576, 581, 586, 625, 0, 940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 941 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 942 /* 39 - 1920x1080i@50Hz 16:9 */ 943 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 944 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 946 DRM_MODE_FLAG_INTERLACE), 947 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 40 - 1920x1080i@100Hz 16:9 */ 949 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 950 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 952 DRM_MODE_FLAG_INTERLACE), 953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 954 /* 41 - 1280x720@100Hz 16:9 */ 955 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 956 1760, 1980, 0, 720, 725, 730, 750, 0, 957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 958 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 959 /* 42 - 720x576@100Hz 4:3 */ 960 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 961 796, 864, 0, 576, 581, 586, 625, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 963 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 964 /* 43 - 720x576@100Hz 16:9 */ 965 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 966 796, 864, 0, 576, 581, 586, 625, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 968 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 969 /* 44 - 720(1440)x576i@100Hz 4:3 */ 970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 971 795, 864, 0, 576, 580, 586, 625, 0, 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 974 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 975 /* 45 - 720(1440)x576i@100Hz 16:9 */ 976 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 977 795, 864, 0, 576, 580, 586, 625, 0, 978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 979 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 46 - 1920x1080i@120Hz 16:9 */ 982 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 983 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 985 DRM_MODE_FLAG_INTERLACE), 986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 987 /* 47 - 1280x720@120Hz 16:9 */ 988 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 989 1430, 1650, 0, 720, 725, 730, 750, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 991 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 48 - 720x480@120Hz 4:3 */ 993 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 994 798, 858, 0, 480, 489, 495, 525, 0, 995 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 996 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 997 /* 49 - 720x480@120Hz 16:9 */ 998 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 999 798, 858, 0, 480, 489, 495, 525, 0, 1000 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1001 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1002 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1003 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1004 801, 858, 0, 480, 488, 494, 525, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1006 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1007 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1008 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1009 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1010 801, 858, 0, 480, 488, 494, 525, 0, 1011 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1012 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1014 /* 52 - 720x576@200Hz 4:3 */ 1015 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1016 796, 864, 0, 576, 581, 586, 625, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1018 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1019 /* 53 - 720x576@200Hz 16:9 */ 1020 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1021 796, 864, 0, 576, 581, 586, 625, 0, 1022 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1023 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1024 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1025 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1026 795, 864, 0, 576, 580, 586, 625, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1028 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1029 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1030 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1031 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1032 795, 864, 0, 576, 580, 586, 625, 0, 1033 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1034 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1036 /* 56 - 720x480@240Hz 4:3 */ 1037 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1038 798, 858, 0, 480, 489, 495, 525, 0, 1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1040 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1041 /* 57 - 720x480@240Hz 16:9 */ 1042 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1043 798, 858, 0, 480, 489, 495, 525, 0, 1044 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1045 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1046 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1047 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1048 801, 858, 0, 480, 488, 494, 525, 0, 1049 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1050 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1051 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1052 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1053 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1054 801, 858, 0, 480, 488, 494, 525, 0, 1055 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1056 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 60 - 1280x720@24Hz 16:9 */ 1059 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1060 3080, 3300, 0, 720, 725, 730, 750, 0, 1061 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1062 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1063 /* 61 - 1280x720@25Hz 16:9 */ 1064 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1065 3740, 3960, 0, 720, 725, 730, 750, 0, 1066 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1067 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1068 /* 62 - 1280x720@30Hz 16:9 */ 1069 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1070 3080, 3300, 0, 720, 725, 730, 750, 0, 1071 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1072 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1073 /* 63 - 1920x1080@120Hz 16:9 */ 1074 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1075 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1076 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1077 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1078 /* 64 - 1920x1080@100Hz 16:9 */ 1079 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1080 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1081 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1082 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1083 /* 65 - 1280x720@24Hz 64:27 */ 1084 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1085 3080, 3300, 0, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1087 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1088 /* 66 - 1280x720@25Hz 64:27 */ 1089 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1090 3740, 3960, 0, 720, 725, 730, 750, 0, 1091 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1092 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1093 /* 67 - 1280x720@30Hz 64:27 */ 1094 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1095 3080, 3300, 0, 720, 725, 730, 750, 0, 1096 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1097 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1098 /* 68 - 1280x720@50Hz 64:27 */ 1099 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1100 1760, 1980, 0, 720, 725, 730, 750, 0, 1101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1102 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1103 /* 69 - 1280x720@60Hz 64:27 */ 1104 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1105 1430, 1650, 0, 720, 725, 730, 750, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1107 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1108 /* 70 - 1280x720@100Hz 64:27 */ 1109 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1110 1760, 1980, 0, 720, 725, 730, 750, 0, 1111 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1112 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1113 /* 71 - 1280x720@120Hz 64:27 */ 1114 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1115 1430, 1650, 0, 720, 725, 730, 750, 0, 1116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1117 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1118 /* 72 - 1920x1080@24Hz 64:27 */ 1119 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1120 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1121 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1122 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1123 /* 73 - 1920x1080@25Hz 64:27 */ 1124 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1125 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1127 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1128 /* 74 - 1920x1080@30Hz 64:27 */ 1129 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1130 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1132 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1133 /* 75 - 1920x1080@50Hz 64:27 */ 1134 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1135 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1136 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1137 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1138 /* 76 - 1920x1080@60Hz 64:27 */ 1139 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1140 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1141 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1142 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1143 /* 77 - 1920x1080@100Hz 64:27 */ 1144 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1145 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1147 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1148 /* 78 - 1920x1080@120Hz 64:27 */ 1149 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1150 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1151 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1152 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1153 /* 79 - 1680x720@24Hz 64:27 */ 1154 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1155 3080, 3300, 0, 720, 725, 730, 750, 0, 1156 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1157 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1158 /* 80 - 1680x720@25Hz 64:27 */ 1159 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1160 2948, 3168, 0, 720, 725, 730, 750, 0, 1161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1162 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1163 /* 81 - 1680x720@30Hz 64:27 */ 1164 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1165 2420, 2640, 0, 720, 725, 730, 750, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1167 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1168 /* 82 - 1680x720@50Hz 64:27 */ 1169 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1170 1980, 2200, 0, 720, 725, 730, 750, 0, 1171 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1172 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1173 /* 83 - 1680x720@60Hz 64:27 */ 1174 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1175 1980, 2200, 0, 720, 725, 730, 750, 0, 1176 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1177 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1178 /* 84 - 1680x720@100Hz 64:27 */ 1179 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1180 1780, 2000, 0, 720, 725, 730, 825, 0, 1181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1182 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1183 /* 85 - 1680x720@120Hz 64:27 */ 1184 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1185 1780, 2000, 0, 720, 725, 730, 825, 0, 1186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1187 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1188 /* 86 - 2560x1080@24Hz 64:27 */ 1189 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1190 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1192 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1193 /* 87 - 2560x1080@25Hz 64:27 */ 1194 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1195 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1197 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1198 /* 88 - 2560x1080@30Hz 64:27 */ 1199 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1200 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1202 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1203 /* 89 - 2560x1080@50Hz 64:27 */ 1204 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1205 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1207 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1208 /* 90 - 2560x1080@60Hz 64:27 */ 1209 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1210 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1212 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1213 /* 91 - 2560x1080@100Hz 64:27 */ 1214 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1215 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1217 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1218 /* 92 - 2560x1080@120Hz 64:27 */ 1219 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1220 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1222 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1223 /* 93 - 3840x2160@24Hz 16:9 */ 1224 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1225 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1227 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1228 /* 94 - 3840x2160@25Hz 16:9 */ 1229 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1230 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1232 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1233 /* 95 - 3840x2160@30Hz 16:9 */ 1234 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1235 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1237 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1238 /* 96 - 3840x2160@50Hz 16:9 */ 1239 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1240 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1242 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1243 /* 97 - 3840x2160@60Hz 16:9 */ 1244 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1245 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1247 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1248 /* 98 - 4096x2160@24Hz 256:135 */ 1249 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1250 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1252 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1253 /* 99 - 4096x2160@25Hz 256:135 */ 1254 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1255 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1257 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1258 /* 100 - 4096x2160@30Hz 256:135 */ 1259 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1260 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1262 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1263 /* 101 - 4096x2160@50Hz 256:135 */ 1264 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1265 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1267 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1268 /* 102 - 4096x2160@60Hz 256:135 */ 1269 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1270 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1272 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1273 /* 103 - 3840x2160@24Hz 64:27 */ 1274 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1275 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1277 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1278 /* 104 - 3840x2160@25Hz 64:27 */ 1279 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1280 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1281 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1282 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1283 /* 105 - 3840x2160@30Hz 64:27 */ 1284 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1285 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1287 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1288 /* 106 - 3840x2160@50Hz 64:27 */ 1289 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1290 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1292 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1293 /* 107 - 3840x2160@60Hz 64:27 */ 1294 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1295 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1297 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1298 /* 108 - 1280x720@48Hz 16:9 */ 1299 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1300 2280, 2500, 0, 720, 725, 730, 750, 0, 1301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1302 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1303 /* 109 - 1280x720@48Hz 64:27 */ 1304 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1305 2280, 2500, 0, 720, 725, 730, 750, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1307 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1308 /* 110 - 1680x720@48Hz 64:27 */ 1309 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1310 2530, 2750, 0, 720, 725, 730, 750, 0, 1311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1312 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1313 /* 111 - 1920x1080@48Hz 16:9 */ 1314 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1315 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1317 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1318 /* 112 - 1920x1080@48Hz 64:27 */ 1319 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1320 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1322 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1323 /* 113 - 2560x1080@48Hz 64:27 */ 1324 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1325 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1327 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1328 /* 114 - 3840x2160@48Hz 16:9 */ 1329 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1330 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1332 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1333 /* 115 - 4096x2160@48Hz 256:135 */ 1334 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1335 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1337 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1338 /* 116 - 3840x2160@48Hz 64:27 */ 1339 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1340 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1342 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1343 /* 117 - 3840x2160@100Hz 16:9 */ 1344 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1345 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1347 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1348 /* 118 - 3840x2160@120Hz 16:9 */ 1349 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1350 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1352 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1353 /* 119 - 3840x2160@100Hz 64:27 */ 1354 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1355 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1357 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1358 /* 120 - 3840x2160@120Hz 64:27 */ 1359 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1360 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1362 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1363 /* 121 - 5120x2160@24Hz 64:27 */ 1364 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1365 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1367 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1368 /* 122 - 5120x2160@25Hz 64:27 */ 1369 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1370 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1372 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1373 /* 123 - 5120x2160@30Hz 64:27 */ 1374 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1375 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1377 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1378 /* 124 - 5120x2160@48Hz 64:27 */ 1379 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1380 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1382 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1383 /* 125 - 5120x2160@50Hz 64:27 */ 1384 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1385 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1387 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1388 /* 126 - 5120x2160@60Hz 64:27 */ 1389 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1390 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1392 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1393 /* 127 - 5120x2160@100Hz 64:27 */ 1394 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1395 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1397 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1398 }; 1399 1400 /* 1401 * From CEA/CTA-861 spec. 1402 * 1403 * Do not access directly, instead always use cea_mode_for_vic(). 1404 */ 1405 static const struct drm_display_mode edid_cea_modes_193[] = { 1406 /* 193 - 5120x2160@120Hz 64:27 */ 1407 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1408 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1410 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1411 /* 194 - 7680x4320@24Hz 16:9 */ 1412 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1413 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1415 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1416 /* 195 - 7680x4320@25Hz 16:9 */ 1417 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1418 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1420 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1421 /* 196 - 7680x4320@30Hz 16:9 */ 1422 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1423 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1425 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1426 /* 197 - 7680x4320@48Hz 16:9 */ 1427 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1428 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1430 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1431 /* 198 - 7680x4320@50Hz 16:9 */ 1432 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1433 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1435 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1436 /* 199 - 7680x4320@60Hz 16:9 */ 1437 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1438 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1440 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1441 /* 200 - 7680x4320@100Hz 16:9 */ 1442 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1443 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1445 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1446 /* 201 - 7680x4320@120Hz 16:9 */ 1447 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1448 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1450 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1451 /* 202 - 7680x4320@24Hz 64:27 */ 1452 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1453 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1455 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1456 /* 203 - 7680x4320@25Hz 64:27 */ 1457 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1458 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1460 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1461 /* 204 - 7680x4320@30Hz 64:27 */ 1462 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1463 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1465 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1466 /* 205 - 7680x4320@48Hz 64:27 */ 1467 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1468 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1470 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1471 /* 206 - 7680x4320@50Hz 64:27 */ 1472 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1473 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1475 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1476 /* 207 - 7680x4320@60Hz 64:27 */ 1477 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1478 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1480 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1481 /* 208 - 7680x4320@100Hz 64:27 */ 1482 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1483 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1485 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1486 /* 209 - 7680x4320@120Hz 64:27 */ 1487 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1488 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1490 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1491 /* 210 - 10240x4320@24Hz 64:27 */ 1492 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1493 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1495 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1496 /* 211 - 10240x4320@25Hz 64:27 */ 1497 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1498 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1500 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1501 /* 212 - 10240x4320@30Hz 64:27 */ 1502 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1503 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1505 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1506 /* 213 - 10240x4320@48Hz 64:27 */ 1507 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1508 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1510 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1511 /* 214 - 10240x4320@50Hz 64:27 */ 1512 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1513 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1515 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1516 /* 215 - 10240x4320@60Hz 64:27 */ 1517 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1518 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1520 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1521 /* 216 - 10240x4320@100Hz 64:27 */ 1522 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1523 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1525 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1526 /* 217 - 10240x4320@120Hz 64:27 */ 1527 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1528 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1530 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1531 /* 218 - 4096x2160@100Hz 256:135 */ 1532 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1533 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1536 /* 219 - 4096x2160@120Hz 256:135 */ 1537 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1538 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1540 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1541 }; 1542 1543 /* 1544 * HDMI 1.4 4k modes. Index using the VIC. 1545 */ 1546 static const struct drm_display_mode edid_4k_modes[] = { 1547 /* 0 - dummy, VICs start at 1 */ 1548 { }, 1549 /* 1 - 3840x2160@30Hz */ 1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1551 3840, 4016, 4104, 4400, 0, 1552 2160, 2168, 2178, 2250, 0, 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1554 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1555 /* 2 - 3840x2160@25Hz */ 1556 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1557 3840, 4896, 4984, 5280, 0, 1558 2160, 2168, 2178, 2250, 0, 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1560 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1561 /* 3 - 3840x2160@24Hz */ 1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1563 3840, 5116, 5204, 5500, 0, 1564 2160, 2168, 2178, 2250, 0, 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1567 /* 4 - 4096x2160@24Hz (SMPTE) */ 1568 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1569 4096, 5116, 5204, 5500, 0, 1570 2160, 2168, 2178, 2250, 0, 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1573 }; 1574 1575 /*** DDC fetch and block validation ***/ 1576 1577 /* 1578 * The opaque EDID type, internal to drm_edid.c. 1579 */ 1580 struct drm_edid { 1581 /* Size allocated for edid */ 1582 size_t size; 1583 const struct edid *edid; 1584 }; 1585 1586 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1587 1588 static int edid_hfeeodb_block_count(const struct edid *edid) 1589 { 1590 int eeodb = edid_hfeeodb_extension_block_count(edid); 1591 1592 return eeodb ? eeodb + 1 : 0; 1593 } 1594 1595 static int edid_extension_block_count(const struct edid *edid) 1596 { 1597 return edid->extensions; 1598 } 1599 1600 static int edid_block_count(const struct edid *edid) 1601 { 1602 return edid_extension_block_count(edid) + 1; 1603 } 1604 1605 static int edid_size_by_blocks(int num_blocks) 1606 { 1607 return num_blocks * EDID_LENGTH; 1608 } 1609 1610 static int edid_size(const struct edid *edid) 1611 { 1612 return edid_size_by_blocks(edid_block_count(edid)); 1613 } 1614 1615 static const void *edid_block_data(const struct edid *edid, int index) 1616 { 1617 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1618 1619 return edid + index; 1620 } 1621 1622 static const void *edid_extension_block_data(const struct edid *edid, int index) 1623 { 1624 return edid_block_data(edid, index + 1); 1625 } 1626 1627 /* EDID block count indicated in EDID, may exceed allocated size */ 1628 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1629 { 1630 int num_blocks; 1631 1632 /* Starting point */ 1633 num_blocks = edid_block_count(drm_edid->edid); 1634 1635 /* HF-EEODB override */ 1636 if (drm_edid->size >= edid_size_by_blocks(2)) { 1637 int eeodb; 1638 1639 /* 1640 * Note: HF-EEODB may specify a smaller extension count than the 1641 * regular one. Unlike in buffer allocation, here we can use it. 1642 */ 1643 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1644 if (eeodb) 1645 num_blocks = eeodb; 1646 } 1647 1648 return num_blocks; 1649 } 1650 1651 /* EDID block count, limited by allocated size */ 1652 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1653 { 1654 /* Limit by allocated size */ 1655 return min(__drm_edid_block_count(drm_edid), 1656 (int)drm_edid->size / EDID_LENGTH); 1657 } 1658 1659 /* EDID extension block count, limited by allocated size */ 1660 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1661 { 1662 return drm_edid_block_count(drm_edid) - 1; 1663 } 1664 1665 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1666 { 1667 return edid_block_data(drm_edid->edid, index); 1668 } 1669 1670 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1671 int index) 1672 { 1673 return edid_extension_block_data(drm_edid->edid, index); 1674 } 1675 1676 /* 1677 * Initializer helper for legacy interfaces, where we have no choice but to 1678 * trust edid size. Not for general purpose use. 1679 */ 1680 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1681 const struct edid *edid) 1682 { 1683 if (!edid) 1684 return NULL; 1685 1686 memset(drm_edid, 0, sizeof(*drm_edid)); 1687 1688 drm_edid->edid = edid; 1689 drm_edid->size = edid_size(edid); 1690 1691 return drm_edid; 1692 } 1693 1694 /* 1695 * EDID base and extension block iterator. 1696 * 1697 * struct drm_edid_iter iter; 1698 * const u8 *block; 1699 * 1700 * drm_edid_iter_begin(drm_edid, &iter); 1701 * drm_edid_iter_for_each(block, &iter) { 1702 * // do stuff with block 1703 * } 1704 * drm_edid_iter_end(&iter); 1705 */ 1706 struct drm_edid_iter { 1707 const struct drm_edid *drm_edid; 1708 1709 /* Current block index. */ 1710 int index; 1711 }; 1712 1713 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1714 struct drm_edid_iter *iter) 1715 { 1716 memset(iter, 0, sizeof(*iter)); 1717 1718 iter->drm_edid = drm_edid; 1719 } 1720 1721 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1722 { 1723 const void *block = NULL; 1724 1725 if (!iter->drm_edid) 1726 return NULL; 1727 1728 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1729 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1730 1731 return block; 1732 } 1733 1734 #define drm_edid_iter_for_each(__block, __iter) \ 1735 while (((__block) = __drm_edid_iter_next(__iter))) 1736 1737 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1738 { 1739 memset(iter, 0, sizeof(*iter)); 1740 } 1741 1742 static const u8 edid_header[] = { 1743 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1744 }; 1745 1746 static void edid_header_fix(void *edid) 1747 { 1748 memcpy(edid, edid_header, sizeof(edid_header)); 1749 } 1750 1751 /** 1752 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1753 * @_edid: pointer to raw base EDID block 1754 * 1755 * Sanity check the header of the base EDID block. 1756 * 1757 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1758 */ 1759 int drm_edid_header_is_valid(const void *_edid) 1760 { 1761 const struct edid *edid = _edid; 1762 int i, score = 0; 1763 1764 for (i = 0; i < sizeof(edid_header); i++) { 1765 if (edid->header[i] == edid_header[i]) 1766 score++; 1767 } 1768 1769 return score; 1770 } 1771 EXPORT_SYMBOL(drm_edid_header_is_valid); 1772 1773 static int edid_fixup __read_mostly = 6; 1774 module_param_named(edid_fixup, edid_fixup, int, 0400); 1775 MODULE_PARM_DESC(edid_fixup, 1776 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1777 1778 static int edid_block_compute_checksum(const void *_block) 1779 { 1780 const u8 *block = _block; 1781 int i; 1782 u8 csum = 0, crc = 0; 1783 1784 for (i = 0; i < EDID_LENGTH - 1; i++) 1785 csum += block[i]; 1786 1787 crc = 0x100 - csum; 1788 1789 return crc; 1790 } 1791 1792 static int edid_block_get_checksum(const void *_block) 1793 { 1794 const struct edid *block = _block; 1795 1796 return block->checksum; 1797 } 1798 1799 static int edid_block_tag(const void *_block) 1800 { 1801 const u8 *block = _block; 1802 1803 return block[0]; 1804 } 1805 1806 static bool edid_block_is_zero(const void *edid) 1807 { 1808 return !memchr_inv(edid, 0, EDID_LENGTH); 1809 } 1810 1811 /** 1812 * drm_edid_are_equal - compare two edid blobs. 1813 * @edid1: pointer to first blob 1814 * @edid2: pointer to second blob 1815 * This helper can be used during probing to determine if 1816 * edid had changed. 1817 */ 1818 bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) 1819 { 1820 int edid1_len, edid2_len; 1821 bool edid1_present = edid1 != NULL; 1822 bool edid2_present = edid2 != NULL; 1823 1824 if (edid1_present != edid2_present) 1825 return false; 1826 1827 if (edid1) { 1828 edid1_len = edid_size(edid1); 1829 edid2_len = edid_size(edid2); 1830 1831 if (edid1_len != edid2_len) 1832 return false; 1833 1834 if (memcmp(edid1, edid2, edid1_len)) 1835 return false; 1836 } 1837 1838 return true; 1839 } 1840 EXPORT_SYMBOL(drm_edid_are_equal); 1841 1842 enum edid_block_status { 1843 EDID_BLOCK_OK = 0, 1844 EDID_BLOCK_READ_FAIL, 1845 EDID_BLOCK_NULL, 1846 EDID_BLOCK_ZERO, 1847 EDID_BLOCK_HEADER_CORRUPT, 1848 EDID_BLOCK_HEADER_REPAIR, 1849 EDID_BLOCK_HEADER_FIXED, 1850 EDID_BLOCK_CHECKSUM, 1851 EDID_BLOCK_VERSION, 1852 }; 1853 1854 static enum edid_block_status edid_block_check(const void *_block, 1855 bool is_base_block) 1856 { 1857 const struct edid *block = _block; 1858 1859 if (!block) 1860 return EDID_BLOCK_NULL; 1861 1862 if (is_base_block) { 1863 int score = drm_edid_header_is_valid(block); 1864 1865 if (score < clamp(edid_fixup, 0, 8)) { 1866 if (edid_block_is_zero(block)) 1867 return EDID_BLOCK_ZERO; 1868 else 1869 return EDID_BLOCK_HEADER_CORRUPT; 1870 } 1871 1872 if (score < 8) 1873 return EDID_BLOCK_HEADER_REPAIR; 1874 } 1875 1876 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1877 if (edid_block_is_zero(block)) 1878 return EDID_BLOCK_ZERO; 1879 else 1880 return EDID_BLOCK_CHECKSUM; 1881 } 1882 1883 if (is_base_block) { 1884 if (block->version != 1) 1885 return EDID_BLOCK_VERSION; 1886 } 1887 1888 return EDID_BLOCK_OK; 1889 } 1890 1891 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1892 { 1893 return status == EDID_BLOCK_OK || 1894 status == EDID_BLOCK_HEADER_FIXED || 1895 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1896 } 1897 1898 static bool edid_block_valid(const void *block, bool base) 1899 { 1900 return edid_block_status_valid(edid_block_check(block, base), 1901 edid_block_tag(block)); 1902 } 1903 1904 static void edid_block_status_print(enum edid_block_status status, 1905 const struct edid *block, 1906 int block_num) 1907 { 1908 switch (status) { 1909 case EDID_BLOCK_OK: 1910 break; 1911 case EDID_BLOCK_READ_FAIL: 1912 pr_debug("EDID block %d read failed\n", block_num); 1913 break; 1914 case EDID_BLOCK_NULL: 1915 pr_debug("EDID block %d pointer is NULL\n", block_num); 1916 break; 1917 case EDID_BLOCK_ZERO: 1918 pr_notice("EDID block %d is all zeroes\n", block_num); 1919 break; 1920 case EDID_BLOCK_HEADER_CORRUPT: 1921 pr_notice("EDID has corrupt header\n"); 1922 break; 1923 case EDID_BLOCK_HEADER_REPAIR: 1924 pr_debug("EDID corrupt header needs repair\n"); 1925 break; 1926 case EDID_BLOCK_HEADER_FIXED: 1927 pr_debug("EDID corrupt header fixed\n"); 1928 break; 1929 case EDID_BLOCK_CHECKSUM: 1930 if (edid_block_status_valid(status, edid_block_tag(block))) { 1931 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1932 block_num, edid_block_tag(block), 1933 edid_block_compute_checksum(block)); 1934 } else { 1935 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1936 block_num, edid_block_tag(block), 1937 edid_block_compute_checksum(block)); 1938 } 1939 break; 1940 case EDID_BLOCK_VERSION: 1941 pr_notice("EDID has major version %d, instead of 1\n", 1942 block->version); 1943 break; 1944 default: 1945 WARN(1, "EDID block %d unknown edid block status code %d\n", 1946 block_num, status); 1947 break; 1948 } 1949 } 1950 1951 static void edid_block_dump(const char *level, const void *block, int block_num) 1952 { 1953 enum edid_block_status status; 1954 char prefix[20]; 1955 1956 status = edid_block_check(block, block_num == 0); 1957 if (status == EDID_BLOCK_ZERO) 1958 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", block_num); 1959 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1960 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", block_num); 1961 else 1962 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", block_num); 1963 1964 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1965 block, EDID_LENGTH, false); 1966 } 1967 1968 /** 1969 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1970 * @_block: pointer to raw EDID block 1971 * @block_num: type of block to validate (0 for base, extension otherwise) 1972 * @print_bad_edid: if true, dump bad EDID blocks to the console 1973 * @edid_corrupt: if true, the header or checksum is invalid 1974 * 1975 * Validate a base or extension EDID block and optionally dump bad blocks to 1976 * the console. 1977 * 1978 * Return: True if the block is valid, false otherwise. 1979 */ 1980 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1981 bool *edid_corrupt) 1982 { 1983 struct edid *block = (struct edid *)_block; 1984 enum edid_block_status status; 1985 bool is_base_block = block_num == 0; 1986 bool valid; 1987 1988 if (WARN_ON(!block)) 1989 return false; 1990 1991 status = edid_block_check(block, is_base_block); 1992 if (status == EDID_BLOCK_HEADER_REPAIR) { 1993 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1994 edid_header_fix(block); 1995 1996 /* Retry with fixed header, update status if that worked. */ 1997 status = edid_block_check(block, is_base_block); 1998 if (status == EDID_BLOCK_OK) 1999 status = EDID_BLOCK_HEADER_FIXED; 2000 } 2001 2002 if (edid_corrupt) { 2003 /* 2004 * Unknown major version isn't corrupt but we can't use it. Only 2005 * the base block can reset edid_corrupt to false. 2006 */ 2007 if (is_base_block && 2008 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2009 *edid_corrupt = false; 2010 else if (status != EDID_BLOCK_OK) 2011 *edid_corrupt = true; 2012 } 2013 2014 edid_block_status_print(status, block, block_num); 2015 2016 /* Determine whether we can use this block with this status. */ 2017 valid = edid_block_status_valid(status, edid_block_tag(block)); 2018 2019 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2020 pr_notice("Raw EDID:\n"); 2021 edid_block_dump(KERN_NOTICE, block, block_num); 2022 } 2023 2024 return valid; 2025 } 2026 EXPORT_SYMBOL(drm_edid_block_valid); 2027 2028 /** 2029 * drm_edid_is_valid - sanity check EDID data 2030 * @edid: EDID data 2031 * 2032 * Sanity-check an entire EDID record (including extensions) 2033 * 2034 * Return: True if the EDID data is valid, false otherwise. 2035 */ 2036 bool drm_edid_is_valid(struct edid *edid) 2037 { 2038 int i; 2039 2040 if (!edid) 2041 return false; 2042 2043 for (i = 0; i < edid_block_count(edid); i++) { 2044 void *block = (void *)edid_block_data(edid, i); 2045 2046 if (!drm_edid_block_valid(block, i, true, NULL)) 2047 return false; 2048 } 2049 2050 return true; 2051 } 2052 EXPORT_SYMBOL(drm_edid_is_valid); 2053 2054 /** 2055 * drm_edid_valid - sanity check EDID data 2056 * @drm_edid: EDID data 2057 * 2058 * Sanity check an EDID. Cross check block count against allocated size and 2059 * checksum the blocks. 2060 * 2061 * Return: True if the EDID data is valid, false otherwise. 2062 */ 2063 bool drm_edid_valid(const struct drm_edid *drm_edid) 2064 { 2065 int i; 2066 2067 if (!drm_edid) 2068 return false; 2069 2070 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2071 return false; 2072 2073 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2074 const void *block = drm_edid_block_data(drm_edid, i); 2075 2076 if (!edid_block_valid(block, i == 0)) 2077 return false; 2078 } 2079 2080 return true; 2081 } 2082 EXPORT_SYMBOL(drm_edid_valid); 2083 2084 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2085 size_t *alloc_size) 2086 { 2087 struct edid *new; 2088 int i, valid_blocks = 0; 2089 2090 /* 2091 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2092 * back to regular extension count here. We don't want to start 2093 * modifying the HF-EEODB extension too. 2094 */ 2095 for (i = 0; i < edid_block_count(edid); i++) { 2096 const void *src_block = edid_block_data(edid, i); 2097 2098 if (edid_block_valid(src_block, i == 0)) { 2099 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2100 2101 memmove(dst_block, src_block, EDID_LENGTH); 2102 valid_blocks++; 2103 } 2104 } 2105 2106 /* We already trusted the base block to be valid here... */ 2107 if (WARN_ON(!valid_blocks)) { 2108 kfree(edid); 2109 return NULL; 2110 } 2111 2112 edid->extensions = valid_blocks - 1; 2113 edid->checksum = edid_block_compute_checksum(edid); 2114 2115 *alloc_size = edid_size_by_blocks(valid_blocks); 2116 2117 #ifdef __linux__ 2118 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2119 if (!new) 2120 kfree(edid); 2121 #else 2122 new = kmalloc(*alloc_size, GFP_KERNEL); 2123 if (!new) 2124 kfree(edid); 2125 memcpy(new, edid, EDID_LENGTH); 2126 kfree(edid); 2127 #endif 2128 2129 return new; 2130 } 2131 2132 #define DDC_SEGMENT_ADDR 0x30 2133 /** 2134 * drm_do_probe_ddc_edid() - get EDID information via I2C 2135 * @data: I2C device adapter 2136 * @buf: EDID data buffer to be filled 2137 * @block: 128 byte EDID block to start fetching from 2138 * @len: EDID data buffer length to fetch 2139 * 2140 * Try to fetch EDID information by calling I2C driver functions. 2141 * 2142 * Return: 0 on success or -1 on failure. 2143 */ 2144 static int 2145 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2146 { 2147 struct i2c_adapter *adapter = data; 2148 unsigned char start = block * EDID_LENGTH; 2149 unsigned char segment = block >> 1; 2150 unsigned char xfers = segment ? 3 : 2; 2151 int ret, retries = 5; 2152 2153 /* 2154 * The core I2C driver will automatically retry the transfer if the 2155 * adapter reports EAGAIN. However, we find that bit-banging transfers 2156 * are susceptible to errors under a heavily loaded machine and 2157 * generate spurious NAKs and timeouts. Retrying the transfer 2158 * of the individual block a few times seems to overcome this. 2159 */ 2160 do { 2161 struct i2c_msg msgs[] = { 2162 { 2163 .addr = DDC_SEGMENT_ADDR, 2164 .flags = 0, 2165 .len = 1, 2166 .buf = &segment, 2167 }, { 2168 .addr = DDC_ADDR, 2169 .flags = 0, 2170 .len = 1, 2171 .buf = &start, 2172 }, { 2173 .addr = DDC_ADDR, 2174 .flags = I2C_M_RD, 2175 .len = len, 2176 .buf = buf, 2177 } 2178 }; 2179 2180 /* 2181 * Avoid sending the segment addr to not upset non-compliant 2182 * DDC monitors. 2183 */ 2184 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2185 2186 if (ret == -ENXIO) { 2187 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2188 adapter->name); 2189 break; 2190 } 2191 } while (ret != xfers && --retries); 2192 2193 return ret == xfers ? 0 : -1; 2194 } 2195 2196 static void connector_bad_edid(struct drm_connector *connector, 2197 const struct edid *edid, int num_blocks) 2198 { 2199 int i; 2200 u8 last_block; 2201 2202 /* 2203 * 0x7e in the EDID is the number of extension blocks. The EDID 2204 * is 1 (base block) + num_ext_blocks big. That means we can think 2205 * of 0x7e in the EDID of the _index_ of the last block in the 2206 * combined chunk of memory. 2207 */ 2208 last_block = edid->extensions; 2209 2210 /* Calculate real checksum for the last edid extension block data */ 2211 if (last_block < num_blocks) 2212 connector->real_edid_checksum = 2213 edid_block_compute_checksum(edid + last_block); 2214 2215 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2216 return; 2217 2218 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2219 connector->base.id, connector->name); 2220 for (i = 0; i < num_blocks; i++) 2221 edid_block_dump(KERN_DEBUG, edid + i, i); 2222 } 2223 2224 /* Get override or firmware EDID */ 2225 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2226 { 2227 const struct drm_edid *override = NULL; 2228 2229 mutex_lock(&connector->edid_override_mutex); 2230 2231 if (connector->edid_override) 2232 override = drm_edid_dup(connector->edid_override); 2233 2234 mutex_unlock(&connector->edid_override_mutex); 2235 2236 if (!override) 2237 override = drm_edid_load_firmware(connector); 2238 2239 return IS_ERR(override) ? NULL : override; 2240 } 2241 2242 /* For debugfs edid_override implementation */ 2243 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2244 { 2245 const struct drm_edid *drm_edid; 2246 2247 mutex_lock(&connector->edid_override_mutex); 2248 2249 drm_edid = connector->edid_override; 2250 if (drm_edid) 2251 seq_write(m, drm_edid->edid, drm_edid->size); 2252 2253 mutex_unlock(&connector->edid_override_mutex); 2254 2255 return 0; 2256 } 2257 2258 /* For debugfs edid_override implementation */ 2259 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2260 size_t size) 2261 { 2262 const struct drm_edid *drm_edid; 2263 2264 drm_edid = drm_edid_alloc(edid, size); 2265 if (!drm_edid_valid(drm_edid)) { 2266 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2267 connector->base.id, connector->name); 2268 drm_edid_free(drm_edid); 2269 return -EINVAL; 2270 } 2271 2272 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2273 connector->base.id, connector->name); 2274 2275 mutex_lock(&connector->edid_override_mutex); 2276 2277 drm_edid_free(connector->edid_override); 2278 connector->edid_override = drm_edid; 2279 2280 mutex_unlock(&connector->edid_override_mutex); 2281 2282 return 0; 2283 } 2284 2285 /* For debugfs edid_override implementation */ 2286 int drm_edid_override_reset(struct drm_connector *connector) 2287 { 2288 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2289 connector->base.id, connector->name); 2290 2291 mutex_lock(&connector->edid_override_mutex); 2292 2293 drm_edid_free(connector->edid_override); 2294 connector->edid_override = NULL; 2295 2296 mutex_unlock(&connector->edid_override_mutex); 2297 2298 return 0; 2299 } 2300 2301 /** 2302 * drm_edid_override_connector_update - add modes from override/firmware EDID 2303 * @connector: connector we're probing 2304 * 2305 * Add modes from the override/firmware EDID, if available. Only to be used from 2306 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2307 * failed during drm_get_edid() and caused the override/firmware EDID to be 2308 * skipped. 2309 * 2310 * Return: The number of modes added or 0 if we couldn't find any. 2311 */ 2312 int drm_edid_override_connector_update(struct drm_connector *connector) 2313 { 2314 const struct drm_edid *override; 2315 int num_modes = 0; 2316 2317 override = drm_edid_override_get(connector); 2318 if (override) { 2319 if (drm_edid_connector_update(connector, override) == 0) 2320 num_modes = drm_edid_connector_add_modes(connector); 2321 2322 drm_edid_free(override); 2323 2324 drm_dbg_kms(connector->dev, 2325 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2326 connector->base.id, connector->name, num_modes); 2327 } 2328 2329 return num_modes; 2330 } 2331 EXPORT_SYMBOL(drm_edid_override_connector_update); 2332 2333 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2334 2335 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2336 read_block_fn read_block, 2337 void *context) 2338 { 2339 enum edid_block_status status; 2340 bool is_base_block = block_num == 0; 2341 int try; 2342 2343 for (try = 0; try < 4; try++) { 2344 if (read_block(context, block, block_num, EDID_LENGTH)) 2345 return EDID_BLOCK_READ_FAIL; 2346 2347 status = edid_block_check(block, is_base_block); 2348 if (status == EDID_BLOCK_HEADER_REPAIR) { 2349 edid_header_fix(block); 2350 2351 /* Retry with fixed header, update status if that worked. */ 2352 status = edid_block_check(block, is_base_block); 2353 if (status == EDID_BLOCK_OK) 2354 status = EDID_BLOCK_HEADER_FIXED; 2355 } 2356 2357 if (edid_block_status_valid(status, edid_block_tag(block))) 2358 break; 2359 2360 /* Fail early for unrepairable base block all zeros. */ 2361 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2362 break; 2363 } 2364 2365 return status; 2366 } 2367 2368 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2369 read_block_fn read_block, void *context, 2370 size_t *size) 2371 { 2372 enum edid_block_status status; 2373 int i, num_blocks, invalid_blocks = 0; 2374 const struct drm_edid *override; 2375 struct edid *edid, *new; 2376 size_t alloc_size = EDID_LENGTH; 2377 2378 override = drm_edid_override_get(connector); 2379 if (override) { 2380 alloc_size = override->size; 2381 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2382 drm_edid_free(override); 2383 if (!edid) 2384 return NULL; 2385 goto ok; 2386 } 2387 2388 edid = kmalloc(alloc_size, GFP_KERNEL); 2389 if (!edid) 2390 return NULL; 2391 2392 status = edid_block_read(edid, 0, read_block, context); 2393 2394 edid_block_status_print(status, edid, 0); 2395 2396 if (status == EDID_BLOCK_READ_FAIL) 2397 goto fail; 2398 2399 /* FIXME: Clarify what a corrupt EDID actually means. */ 2400 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2401 connector->edid_corrupt = false; 2402 else 2403 connector->edid_corrupt = true; 2404 2405 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2406 if (status == EDID_BLOCK_ZERO) 2407 connector->null_edid_counter++; 2408 2409 connector_bad_edid(connector, edid, 1); 2410 goto fail; 2411 } 2412 2413 if (!edid_extension_block_count(edid)) 2414 goto ok; 2415 2416 alloc_size = edid_size(edid); 2417 #ifdef __linux__ 2418 new = krealloc(edid, alloc_size, GFP_KERNEL); 2419 if (!new) 2420 goto fail; 2421 #else 2422 new = kmalloc(alloc_size, GFP_KERNEL); 2423 if (!new) 2424 goto fail; 2425 memcpy(new, edid, EDID_LENGTH); 2426 kfree(edid); 2427 #endif 2428 edid = new; 2429 2430 num_blocks = edid_block_count(edid); 2431 for (i = 1; i < num_blocks; i++) { 2432 void *block = (void *)edid_block_data(edid, i); 2433 2434 status = edid_block_read(block, i, read_block, context); 2435 2436 edid_block_status_print(status, block, i); 2437 2438 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2439 if (status == EDID_BLOCK_READ_FAIL) 2440 goto fail; 2441 invalid_blocks++; 2442 } else if (i == 1) { 2443 /* 2444 * If the first EDID extension is a CTA extension, and 2445 * the first Data Block is HF-EEODB, override the 2446 * extension block count. 2447 * 2448 * Note: HF-EEODB could specify a smaller extension 2449 * count too, but we can't risk allocating a smaller 2450 * amount. 2451 */ 2452 int eeodb = edid_hfeeodb_block_count(edid); 2453 2454 if (eeodb > num_blocks) { 2455 num_blocks = eeodb; 2456 alloc_size = edid_size_by_blocks(num_blocks); 2457 #ifdef __linux__ 2458 new = krealloc(edid, alloc_size, GFP_KERNEL); 2459 if (!new) 2460 goto fail; 2461 #else 2462 new = kmalloc(alloc_size, GFP_KERNEL); 2463 if (!new) 2464 goto fail; 2465 memcpy(new, edid, EDID_LENGTH); 2466 kfree(edid); 2467 #endif 2468 edid = new; 2469 } 2470 } 2471 } 2472 2473 if (invalid_blocks) { 2474 connector_bad_edid(connector, edid, num_blocks); 2475 2476 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2477 } 2478 2479 ok: 2480 if (size) 2481 *size = alloc_size; 2482 2483 return edid; 2484 2485 fail: 2486 kfree(edid); 2487 return NULL; 2488 } 2489 2490 /** 2491 * drm_do_get_edid - get EDID data using a custom EDID block read function 2492 * @connector: connector we're probing 2493 * @read_block: EDID block read function 2494 * @context: private data passed to the block read function 2495 * 2496 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2497 * exposes a different interface to read EDID blocks this function can be used 2498 * to get EDID data using a custom block read function. 2499 * 2500 * As in the general case the DDC bus is accessible by the kernel at the I2C 2501 * level, drivers must make all reasonable efforts to expose it as an I2C 2502 * adapter and use drm_get_edid() instead of abusing this function. 2503 * 2504 * The EDID may be overridden using debugfs override_edid or firmware EDID 2505 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2506 * order. Having either of them bypasses actual EDID reads. 2507 * 2508 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2509 */ 2510 struct edid *drm_do_get_edid(struct drm_connector *connector, 2511 read_block_fn read_block, 2512 void *context) 2513 { 2514 return _drm_do_get_edid(connector, read_block, context, NULL); 2515 } 2516 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2517 2518 /** 2519 * drm_edid_raw - Get a pointer to the raw EDID data. 2520 * @drm_edid: drm_edid container 2521 * 2522 * Get a pointer to the raw EDID data. 2523 * 2524 * This is for transition only. Avoid using this like the plague. 2525 * 2526 * Return: Pointer to raw EDID data. 2527 */ 2528 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2529 { 2530 if (!drm_edid || !drm_edid->size) 2531 return NULL; 2532 2533 /* 2534 * Do not return pointers where relying on EDID extension count would 2535 * lead to buffer overflow. 2536 */ 2537 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2538 return NULL; 2539 2540 return drm_edid->edid; 2541 } 2542 EXPORT_SYMBOL(drm_edid_raw); 2543 2544 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2545 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2546 { 2547 struct drm_edid *drm_edid; 2548 2549 if (!edid || !size || size < EDID_LENGTH) 2550 return NULL; 2551 2552 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2553 if (drm_edid) { 2554 drm_edid->edid = edid; 2555 drm_edid->size = size; 2556 } 2557 2558 return drm_edid; 2559 } 2560 2561 /** 2562 * drm_edid_alloc - Allocate a new drm_edid container 2563 * @edid: Pointer to raw EDID data 2564 * @size: Size of memory allocated for EDID 2565 * 2566 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2567 * the actual size that has been allocated for the data. There is no validation 2568 * of the raw EDID data against the size, but at least the EDID base block must 2569 * fit in the buffer. 2570 * 2571 * The returned pointer must be freed using drm_edid_free(). 2572 * 2573 * Return: drm_edid container, or NULL on errors 2574 */ 2575 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2576 { 2577 const struct drm_edid *drm_edid; 2578 2579 if (!edid || !size || size < EDID_LENGTH) 2580 return NULL; 2581 2582 edid = kmemdup(edid, size, GFP_KERNEL); 2583 if (!edid) 2584 return NULL; 2585 2586 drm_edid = _drm_edid_alloc(edid, size); 2587 if (!drm_edid) 2588 kfree(edid); 2589 2590 return drm_edid; 2591 } 2592 EXPORT_SYMBOL(drm_edid_alloc); 2593 2594 /** 2595 * drm_edid_dup - Duplicate a drm_edid container 2596 * @drm_edid: EDID to duplicate 2597 * 2598 * The returned pointer must be freed using drm_edid_free(). 2599 * 2600 * Returns: drm_edid container copy, or NULL on errors 2601 */ 2602 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2603 { 2604 if (!drm_edid) 2605 return NULL; 2606 2607 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2608 } 2609 EXPORT_SYMBOL(drm_edid_dup); 2610 2611 /** 2612 * drm_edid_free - Free the drm_edid container 2613 * @drm_edid: EDID to free 2614 */ 2615 void drm_edid_free(const struct drm_edid *drm_edid) 2616 { 2617 if (!drm_edid) 2618 return; 2619 2620 kfree(drm_edid->edid); 2621 kfree(drm_edid); 2622 } 2623 EXPORT_SYMBOL(drm_edid_free); 2624 2625 /** 2626 * drm_probe_ddc() - probe DDC presence 2627 * @adapter: I2C adapter to probe 2628 * 2629 * Return: True on success, false on failure. 2630 */ 2631 bool 2632 drm_probe_ddc(struct i2c_adapter *adapter) 2633 { 2634 unsigned char out; 2635 2636 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2637 } 2638 EXPORT_SYMBOL(drm_probe_ddc); 2639 2640 /** 2641 * drm_get_edid - get EDID data, if available 2642 * @connector: connector we're probing 2643 * @adapter: I2C adapter to use for DDC 2644 * 2645 * Poke the given I2C channel to grab EDID data if possible. If found, 2646 * attach it to the connector. 2647 * 2648 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2649 */ 2650 struct edid *drm_get_edid(struct drm_connector *connector, 2651 struct i2c_adapter *adapter) 2652 { 2653 struct edid *edid; 2654 2655 if (connector->force == DRM_FORCE_OFF) 2656 return NULL; 2657 2658 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2659 return NULL; 2660 2661 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2662 drm_connector_update_edid_property(connector, edid); 2663 return edid; 2664 } 2665 EXPORT_SYMBOL(drm_get_edid); 2666 2667 /** 2668 * drm_edid_read_custom - Read EDID data using given EDID block read function 2669 * @connector: Connector to use 2670 * @read_block: EDID block read function 2671 * @context: Private data passed to the block read function 2672 * 2673 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2674 * exposes a different interface to read EDID blocks this function can be used 2675 * to get EDID data using a custom block read function. 2676 * 2677 * As in the general case the DDC bus is accessible by the kernel at the I2C 2678 * level, drivers must make all reasonable efforts to expose it as an I2C 2679 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2680 * this function. 2681 * 2682 * The EDID may be overridden using debugfs override_edid or firmware EDID 2683 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2684 * order. Having either of them bypasses actual EDID reads. 2685 * 2686 * The returned pointer must be freed using drm_edid_free(). 2687 * 2688 * Return: Pointer to EDID, or NULL if probe/read failed. 2689 */ 2690 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2691 read_block_fn read_block, 2692 void *context) 2693 { 2694 const struct drm_edid *drm_edid; 2695 struct edid *edid; 2696 size_t size = 0; 2697 2698 edid = _drm_do_get_edid(connector, read_block, context, &size); 2699 if (!edid) 2700 return NULL; 2701 2702 /* Sanity check for now */ 2703 drm_WARN_ON(connector->dev, !size); 2704 2705 drm_edid = _drm_edid_alloc(edid, size); 2706 if (!drm_edid) 2707 kfree(edid); 2708 2709 return drm_edid; 2710 } 2711 EXPORT_SYMBOL(drm_edid_read_custom); 2712 2713 /** 2714 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2715 * @connector: Connector to use 2716 * @adapter: I2C adapter to use for DDC 2717 * 2718 * Read EDID using the given I2C adapter. 2719 * 2720 * The EDID may be overridden using debugfs override_edid or firmware EDID 2721 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2722 * order. Having either of them bypasses actual EDID reads. 2723 * 2724 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2725 * using drm_edid_read() instead of this function. 2726 * 2727 * The returned pointer must be freed using drm_edid_free(). 2728 * 2729 * Return: Pointer to EDID, or NULL if probe/read failed. 2730 */ 2731 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2732 struct i2c_adapter *adapter) 2733 { 2734 const struct drm_edid *drm_edid; 2735 2736 if (connector->force == DRM_FORCE_OFF) 2737 return NULL; 2738 2739 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2740 return NULL; 2741 2742 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2743 2744 /* Note: Do *not* call connector updates here. */ 2745 2746 return drm_edid; 2747 } 2748 EXPORT_SYMBOL(drm_edid_read_ddc); 2749 2750 /** 2751 * drm_edid_read - Read EDID data using connector's I2C adapter 2752 * @connector: Connector to use 2753 * 2754 * Read EDID using the connector's I2C adapter. 2755 * 2756 * The EDID may be overridden using debugfs override_edid or firmware EDID 2757 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2758 * order. Having either of them bypasses actual EDID reads. 2759 * 2760 * The returned pointer must be freed using drm_edid_free(). 2761 * 2762 * Return: Pointer to EDID, or NULL if probe/read failed. 2763 */ 2764 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2765 { 2766 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2767 return NULL; 2768 2769 return drm_edid_read_ddc(connector, connector->ddc); 2770 } 2771 EXPORT_SYMBOL(drm_edid_read); 2772 2773 static u32 edid_extract_panel_id(const struct edid *edid) 2774 { 2775 /* 2776 * We represent the ID as a 32-bit number so it can easily be compared 2777 * with "==". 2778 * 2779 * NOTE that we deal with endianness differently for the top half 2780 * of this ID than for the bottom half. The bottom half (the product 2781 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2782 * that's how everyone seems to interpret it. The top half (the mfg_id) 2783 * gets stored as big endian because that makes 2784 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2785 * to write (it's easier to extract the ASCII). It doesn't really 2786 * matter, though, as long as the number here is unique. 2787 */ 2788 return (u32)edid->mfg_id[0] << 24 | 2789 (u32)edid->mfg_id[1] << 16 | 2790 (u32)EDID_PRODUCT_ID(edid); 2791 } 2792 2793 /** 2794 * drm_edid_get_panel_id - Get a panel's ID through DDC 2795 * @adapter: I2C adapter to use for DDC 2796 * 2797 * This function reads the first block of the EDID of a panel and (assuming 2798 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2799 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2800 * supposed to be different for each different modem of panel. 2801 * 2802 * This function is intended to be used during early probing on devices where 2803 * more than one panel might be present. Because of its intended use it must 2804 * assume that the EDID of the panel is correct, at least as far as the ID 2805 * is concerned (in other words, we don't process any overrides here). 2806 * 2807 * NOTE: it's expected that this function and drm_do_get_edid() will both 2808 * be read the EDID, but there is no caching between them. Since we're only 2809 * reading the first block, hopefully this extra overhead won't be too big. 2810 * 2811 * Return: A 32-bit ID that should be different for each make/model of panel. 2812 * See the functions drm_edid_encode_panel_id() and 2813 * drm_edid_decode_panel_id() for some details on the structure of this 2814 * ID. 2815 */ 2816 2817 u32 drm_edid_get_panel_id(struct i2c_adapter *adapter) 2818 { 2819 enum edid_block_status status; 2820 void *base_block; 2821 u32 panel_id = 0; 2822 2823 /* 2824 * There are no manufacturer IDs of 0, so if there is a problem reading 2825 * the EDID then we'll just return 0. 2826 */ 2827 2828 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2829 if (!base_block) 2830 return 0; 2831 2832 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2833 2834 edid_block_status_print(status, base_block, 0); 2835 2836 if (edid_block_status_valid(status, edid_block_tag(base_block))) 2837 panel_id = edid_extract_panel_id(base_block); 2838 else 2839 edid_block_dump(KERN_NOTICE, base_block, 0); 2840 2841 kfree(base_block); 2842 2843 return panel_id; 2844 } 2845 EXPORT_SYMBOL(drm_edid_get_panel_id); 2846 2847 /** 2848 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2849 * @connector: connector we're probing 2850 * @adapter: I2C adapter to use for DDC 2851 * 2852 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2853 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2854 * switch DDC to the GPU which is retrieving EDID. 2855 * 2856 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2857 */ 2858 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2859 struct i2c_adapter *adapter) 2860 { 2861 STUB(); 2862 return NULL; 2863 #ifdef notyet 2864 struct drm_device *dev = connector->dev; 2865 struct pci_dev *pdev = to_pci_dev(dev->dev); 2866 struct edid *edid; 2867 2868 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2869 return NULL; 2870 2871 vga_switcheroo_lock_ddc(pdev); 2872 edid = drm_get_edid(connector, adapter); 2873 vga_switcheroo_unlock_ddc(pdev); 2874 2875 return edid; 2876 #endif 2877 } 2878 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2879 2880 /** 2881 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2882 * @connector: connector we're probing 2883 * @adapter: I2C adapter to use for DDC 2884 * 2885 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2886 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2887 * temporarily switch DDC to the GPU which is retrieving EDID. 2888 * 2889 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2890 */ 2891 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2892 struct i2c_adapter *adapter) 2893 { 2894 STUB(); 2895 return NULL; 2896 #ifdef notyet 2897 struct drm_device *dev = connector->dev; 2898 struct pci_dev *pdev = to_pci_dev(dev->dev); 2899 const struct drm_edid *drm_edid; 2900 2901 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2902 return NULL; 2903 2904 vga_switcheroo_lock_ddc(pdev); 2905 drm_edid = drm_edid_read_ddc(connector, adapter); 2906 vga_switcheroo_unlock_ddc(pdev); 2907 2908 return drm_edid; 2909 #endif 2910 } 2911 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2912 2913 /** 2914 * drm_edid_duplicate - duplicate an EDID and the extensions 2915 * @edid: EDID to duplicate 2916 * 2917 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2918 */ 2919 struct edid *drm_edid_duplicate(const struct edid *edid) 2920 { 2921 if (!edid) 2922 return NULL; 2923 2924 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2925 } 2926 EXPORT_SYMBOL(drm_edid_duplicate); 2927 2928 /*** EDID parsing ***/ 2929 2930 /** 2931 * edid_get_quirks - return quirk flags for a given EDID 2932 * @drm_edid: EDID to process 2933 * 2934 * This tells subsequent routines what fixes they need to apply. 2935 */ 2936 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2937 { 2938 u32 panel_id = edid_extract_panel_id(drm_edid->edid); 2939 const struct edid_quirk *quirk; 2940 int i; 2941 2942 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2943 quirk = &edid_quirk_list[i]; 2944 if (quirk->panel_id == panel_id) 2945 return quirk->quirks; 2946 } 2947 2948 return 0; 2949 } 2950 2951 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2952 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2953 2954 /* 2955 * Walk the mode list for connector, clearing the preferred status on existing 2956 * modes and setting it anew for the right mode ala quirks. 2957 */ 2958 static void edid_fixup_preferred(struct drm_connector *connector) 2959 { 2960 const struct drm_display_info *info = &connector->display_info; 2961 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2962 int target_refresh = 0; 2963 int cur_vrefresh, preferred_vrefresh; 2964 2965 if (list_empty(&connector->probed_modes)) 2966 return; 2967 2968 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 2969 target_refresh = 60; 2970 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 2971 target_refresh = 75; 2972 2973 preferred_mode = list_first_entry(&connector->probed_modes, 2974 struct drm_display_mode, head); 2975 2976 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2977 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2978 2979 if (cur_mode == preferred_mode) 2980 continue; 2981 2982 /* Largest mode is preferred */ 2983 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2984 preferred_mode = cur_mode; 2985 2986 cur_vrefresh = drm_mode_vrefresh(cur_mode); 2987 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 2988 /* At a given size, try to get closest to target refresh */ 2989 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2990 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2991 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2992 preferred_mode = cur_mode; 2993 } 2994 } 2995 2996 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2997 } 2998 2999 static bool 3000 mode_is_rb(const struct drm_display_mode *mode) 3001 { 3002 return (mode->htotal - mode->hdisplay == 160) && 3003 (mode->hsync_end - mode->hdisplay == 80) && 3004 (mode->hsync_end - mode->hsync_start == 32) && 3005 (mode->vsync_start - mode->vdisplay == 3); 3006 } 3007 3008 /* 3009 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3010 * @dev: Device to duplicate against 3011 * @hsize: Mode width 3012 * @vsize: Mode height 3013 * @fresh: Mode refresh rate 3014 * @rb: Mode reduced-blanking-ness 3015 * 3016 * Walk the DMT mode list looking for a match for the given parameters. 3017 * 3018 * Return: A newly allocated copy of the mode, or NULL if not found. 3019 */ 3020 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 3021 int hsize, int vsize, int fresh, 3022 bool rb) 3023 { 3024 int i; 3025 3026 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3027 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3028 3029 if (hsize != ptr->hdisplay) 3030 continue; 3031 if (vsize != ptr->vdisplay) 3032 continue; 3033 if (fresh != drm_mode_vrefresh(ptr)) 3034 continue; 3035 if (rb != mode_is_rb(ptr)) 3036 continue; 3037 3038 return drm_mode_duplicate(dev, ptr); 3039 } 3040 3041 return NULL; 3042 } 3043 EXPORT_SYMBOL(drm_mode_find_dmt); 3044 3045 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3046 { 3047 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3048 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3049 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3050 3051 return descriptor->pixel_clock == 0 && 3052 descriptor->data.other_data.pad1 == 0 && 3053 descriptor->data.other_data.type == type; 3054 } 3055 3056 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3057 { 3058 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3059 3060 return descriptor->pixel_clock != 0; 3061 } 3062 3063 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3064 3065 static void 3066 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3067 { 3068 int i, n; 3069 u8 d = ext[0x02]; 3070 const u8 *det_base = ext + d; 3071 3072 if (d < 4 || d > 127) 3073 return; 3074 3075 n = (127 - d) / 18; 3076 for (i = 0; i < n; i++) 3077 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3078 } 3079 3080 static void 3081 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3082 { 3083 unsigned int i, n = min((int)ext[0x02], 6); 3084 const u8 *det_base = ext + 5; 3085 3086 if (ext[0x01] != 1) 3087 return; /* unknown version */ 3088 3089 for (i = 0; i < n; i++) 3090 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3091 } 3092 3093 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3094 detailed_cb *cb, void *closure) 3095 { 3096 struct drm_edid_iter edid_iter; 3097 const u8 *ext; 3098 int i; 3099 3100 if (!drm_edid) 3101 return; 3102 3103 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3104 cb(&drm_edid->edid->detailed_timings[i], closure); 3105 3106 drm_edid_iter_begin(drm_edid, &edid_iter); 3107 drm_edid_iter_for_each(ext, &edid_iter) { 3108 switch (*ext) { 3109 case CEA_EXT: 3110 cea_for_each_detailed_block(ext, cb, closure); 3111 break; 3112 case VTB_EXT: 3113 vtb_for_each_detailed_block(ext, cb, closure); 3114 break; 3115 default: 3116 break; 3117 } 3118 } 3119 drm_edid_iter_end(&edid_iter); 3120 } 3121 3122 static void 3123 is_rb(const struct detailed_timing *descriptor, void *data) 3124 { 3125 bool *res = data; 3126 3127 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3128 return; 3129 3130 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3131 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3132 3133 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3134 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3135 *res = true; 3136 } 3137 3138 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3139 static bool 3140 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3141 { 3142 if (drm_edid->edid->revision >= 4) { 3143 bool ret = false; 3144 3145 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3146 return ret; 3147 } 3148 3149 return ((drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 3150 } 3151 3152 static void 3153 find_gtf2(const struct detailed_timing *descriptor, void *data) 3154 { 3155 const struct detailed_timing **res = data; 3156 3157 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3158 return; 3159 3160 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3161 3162 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3163 *res = descriptor; 3164 } 3165 3166 /* Secondary GTF curve kicks in above some break frequency */ 3167 static int 3168 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3169 { 3170 const struct detailed_timing *descriptor = NULL; 3171 3172 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3173 3174 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3175 3176 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3177 } 3178 3179 static int 3180 drm_gtf2_2c(const struct drm_edid *drm_edid) 3181 { 3182 const struct detailed_timing *descriptor = NULL; 3183 3184 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3185 3186 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3187 3188 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3189 } 3190 3191 static int 3192 drm_gtf2_m(const struct drm_edid *drm_edid) 3193 { 3194 const struct detailed_timing *descriptor = NULL; 3195 3196 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3197 3198 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3199 3200 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3201 } 3202 3203 static int 3204 drm_gtf2_k(const struct drm_edid *drm_edid) 3205 { 3206 const struct detailed_timing *descriptor = NULL; 3207 3208 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3209 3210 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3211 3212 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3213 } 3214 3215 static int 3216 drm_gtf2_2j(const struct drm_edid *drm_edid) 3217 { 3218 const struct detailed_timing *descriptor = NULL; 3219 3220 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3221 3222 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3223 3224 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3225 } 3226 3227 static void 3228 get_timing_level(const struct detailed_timing *descriptor, void *data) 3229 { 3230 int *res = data; 3231 3232 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3233 return; 3234 3235 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3236 3237 switch (descriptor->data.other_data.data.range.flags) { 3238 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3239 *res = LEVEL_GTF; 3240 break; 3241 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3242 *res = LEVEL_GTF2; 3243 break; 3244 case DRM_EDID_CVT_SUPPORT_FLAG: 3245 *res = LEVEL_CVT; 3246 break; 3247 default: 3248 break; 3249 } 3250 } 3251 3252 /* Get standard timing level (CVT/GTF/DMT). */ 3253 static int standard_timing_level(const struct drm_edid *drm_edid) 3254 { 3255 const struct edid *edid = drm_edid->edid; 3256 3257 if (edid->revision >= 4) { 3258 /* 3259 * If the range descriptor doesn't 3260 * indicate otherwise default to CVT 3261 */ 3262 int ret = LEVEL_CVT; 3263 3264 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3265 3266 return ret; 3267 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3268 return LEVEL_GTF2; 3269 } else if (edid->revision >= 2) { 3270 return LEVEL_GTF; 3271 } else { 3272 return LEVEL_DMT; 3273 } 3274 } 3275 3276 /* 3277 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3278 * monitors fill with ascii space (0x20) instead. 3279 */ 3280 static int 3281 bad_std_timing(u8 a, u8 b) 3282 { 3283 return (a == 0x00 && b == 0x00) || 3284 (a == 0x01 && b == 0x01) || 3285 (a == 0x20 && b == 0x20); 3286 } 3287 3288 static int drm_mode_hsync(const struct drm_display_mode *mode) 3289 { 3290 if (mode->htotal <= 0) 3291 return 0; 3292 3293 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3294 } 3295 3296 static struct drm_display_mode * 3297 drm_gtf2_mode(struct drm_device *dev, 3298 const struct drm_edid *drm_edid, 3299 int hsize, int vsize, int vrefresh_rate) 3300 { 3301 struct drm_display_mode *mode; 3302 3303 /* 3304 * This is potentially wrong if there's ever a monitor with 3305 * more than one ranges section, each claiming a different 3306 * secondary GTF curve. Please don't do that. 3307 */ 3308 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3309 if (!mode) 3310 return NULL; 3311 3312 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3313 drm_mode_destroy(dev, mode); 3314 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3315 vrefresh_rate, 0, 0, 3316 drm_gtf2_m(drm_edid), 3317 drm_gtf2_2c(drm_edid), 3318 drm_gtf2_k(drm_edid), 3319 drm_gtf2_2j(drm_edid)); 3320 } 3321 3322 return mode; 3323 } 3324 3325 /* 3326 * Take the standard timing params (in this case width, aspect, and refresh) 3327 * and convert them into a real mode using CVT/GTF/DMT. 3328 */ 3329 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3330 const struct drm_edid *drm_edid, 3331 const struct std_timing *t) 3332 { 3333 struct drm_device *dev = connector->dev; 3334 struct drm_display_mode *m, *mode = NULL; 3335 int hsize, vsize; 3336 int vrefresh_rate; 3337 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3338 >> EDID_TIMING_ASPECT_SHIFT; 3339 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3340 >> EDID_TIMING_VFREQ_SHIFT; 3341 int timing_level = standard_timing_level(drm_edid); 3342 3343 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3344 return NULL; 3345 3346 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3347 hsize = t->hsize * 8 + 248; 3348 /* vrefresh_rate = vfreq + 60 */ 3349 vrefresh_rate = vfreq + 60; 3350 /* the vdisplay is calculated based on the aspect ratio */ 3351 if (aspect_ratio == 0) { 3352 if (drm_edid->edid->revision < 3) 3353 vsize = hsize; 3354 else 3355 vsize = (hsize * 10) / 16; 3356 } else if (aspect_ratio == 1) 3357 vsize = (hsize * 3) / 4; 3358 else if (aspect_ratio == 2) 3359 vsize = (hsize * 4) / 5; 3360 else 3361 vsize = (hsize * 9) / 16; 3362 3363 /* HDTV hack, part 1 */ 3364 if (vrefresh_rate == 60 && 3365 ((hsize == 1360 && vsize == 765) || 3366 (hsize == 1368 && vsize == 769))) { 3367 hsize = 1366; 3368 vsize = 768; 3369 } 3370 3371 /* 3372 * If this connector already has a mode for this size and refresh 3373 * rate (because it came from detailed or CVT info), use that 3374 * instead. This way we don't have to guess at interlace or 3375 * reduced blanking. 3376 */ 3377 list_for_each_entry(m, &connector->probed_modes, head) 3378 if (m->hdisplay == hsize && m->vdisplay == vsize && 3379 drm_mode_vrefresh(m) == vrefresh_rate) 3380 return NULL; 3381 3382 /* HDTV hack, part 2 */ 3383 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3384 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3385 false); 3386 if (!mode) 3387 return NULL; 3388 mode->hdisplay = 1366; 3389 mode->hsync_start = mode->hsync_start - 1; 3390 mode->hsync_end = mode->hsync_end - 1; 3391 return mode; 3392 } 3393 3394 /* check whether it can be found in default mode table */ 3395 if (drm_monitor_supports_rb(drm_edid)) { 3396 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3397 true); 3398 if (mode) 3399 return mode; 3400 } 3401 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3402 if (mode) 3403 return mode; 3404 3405 /* okay, generate it */ 3406 switch (timing_level) { 3407 case LEVEL_DMT: 3408 break; 3409 case LEVEL_GTF: 3410 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3411 break; 3412 case LEVEL_GTF2: 3413 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3414 break; 3415 case LEVEL_CVT: 3416 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3417 false); 3418 break; 3419 } 3420 return mode; 3421 } 3422 3423 /* 3424 * EDID is delightfully ambiguous about how interlaced modes are to be 3425 * encoded. Our internal representation is of frame height, but some 3426 * HDTV detailed timings are encoded as field height. 3427 * 3428 * The format list here is from CEA, in frame size. Technically we 3429 * should be checking refresh rate too. Whatever. 3430 */ 3431 static void 3432 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3433 const struct detailed_pixel_timing *pt) 3434 { 3435 int i; 3436 static const struct { 3437 int w, h; 3438 } cea_interlaced[] = { 3439 { 1920, 1080 }, 3440 { 720, 480 }, 3441 { 1440, 480 }, 3442 { 2880, 480 }, 3443 { 720, 576 }, 3444 { 1440, 576 }, 3445 { 2880, 576 }, 3446 }; 3447 3448 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3449 return; 3450 3451 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3452 if ((mode->hdisplay == cea_interlaced[i].w) && 3453 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3454 mode->vdisplay *= 2; 3455 mode->vsync_start *= 2; 3456 mode->vsync_end *= 2; 3457 mode->vtotal *= 2; 3458 mode->vtotal |= 1; 3459 } 3460 } 3461 3462 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3463 } 3464 3465 /* 3466 * Create a new mode from an EDID detailed timing section. An EDID detailed 3467 * timing block contains enough info for us to create and return a new struct 3468 * drm_display_mode. 3469 */ 3470 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3471 const struct drm_edid *drm_edid, 3472 const struct detailed_timing *timing) 3473 { 3474 const struct drm_display_info *info = &connector->display_info; 3475 struct drm_device *dev = connector->dev; 3476 struct drm_display_mode *mode; 3477 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3478 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3479 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3480 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3481 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3482 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3483 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3484 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3485 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3486 3487 /* ignore tiny modes */ 3488 if (hactive < 64 || vactive < 64) 3489 return NULL; 3490 3491 if (pt->misc & DRM_EDID_PT_STEREO) { 3492 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3493 connector->base.id, connector->name); 3494 return NULL; 3495 } 3496 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3497 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3498 connector->base.id, connector->name); 3499 } 3500 3501 /* it is incorrect if hsync/vsync width is zero */ 3502 if (!hsync_pulse_width || !vsync_pulse_width) { 3503 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3504 connector->base.id, connector->name); 3505 return NULL; 3506 } 3507 3508 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3509 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3510 if (!mode) 3511 return NULL; 3512 3513 goto set_size; 3514 } 3515 3516 mode = drm_mode_create(dev); 3517 if (!mode) 3518 return NULL; 3519 3520 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3521 mode->clock = 1088 * 10; 3522 else 3523 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3524 3525 mode->hdisplay = hactive; 3526 mode->hsync_start = mode->hdisplay + hsync_offset; 3527 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3528 mode->htotal = mode->hdisplay + hblank; 3529 3530 mode->vdisplay = vactive; 3531 mode->vsync_start = mode->vdisplay + vsync_offset; 3532 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3533 mode->vtotal = mode->vdisplay + vblank; 3534 3535 /* Some EDIDs have bogus h/vsync_end values */ 3536 if (mode->hsync_end > mode->htotal) { 3537 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3538 connector->base.id, connector->name, 3539 mode->hsync_end, mode->htotal); 3540 mode->hsync_end = mode->htotal; 3541 } 3542 if (mode->vsync_end > mode->vtotal) { 3543 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3544 connector->base.id, connector->name, 3545 mode->vsync_end, mode->vtotal); 3546 mode->vsync_end = mode->vtotal; 3547 } 3548 3549 drm_mode_do_interlace_quirk(mode, pt); 3550 3551 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3552 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3553 } else { 3554 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3555 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3556 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3557 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3558 } 3559 3560 set_size: 3561 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3562 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3563 3564 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3565 mode->width_mm *= 10; 3566 mode->height_mm *= 10; 3567 } 3568 3569 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3570 mode->width_mm = drm_edid->edid->width_cm * 10; 3571 mode->height_mm = drm_edid->edid->height_cm * 10; 3572 } 3573 3574 mode->type = DRM_MODE_TYPE_DRIVER; 3575 drm_mode_set_name(mode); 3576 3577 return mode; 3578 } 3579 3580 static bool 3581 mode_in_hsync_range(const struct drm_display_mode *mode, 3582 const struct edid *edid, const u8 *t) 3583 { 3584 int hsync, hmin, hmax; 3585 3586 hmin = t[7]; 3587 if (edid->revision >= 4) 3588 hmin += ((t[4] & 0x04) ? 255 : 0); 3589 hmax = t[8]; 3590 if (edid->revision >= 4) 3591 hmax += ((t[4] & 0x08) ? 255 : 0); 3592 hsync = drm_mode_hsync(mode); 3593 3594 return (hsync <= hmax && hsync >= hmin); 3595 } 3596 3597 static bool 3598 mode_in_vsync_range(const struct drm_display_mode *mode, 3599 const struct edid *edid, const u8 *t) 3600 { 3601 int vsync, vmin, vmax; 3602 3603 vmin = t[5]; 3604 if (edid->revision >= 4) 3605 vmin += ((t[4] & 0x01) ? 255 : 0); 3606 vmax = t[6]; 3607 if (edid->revision >= 4) 3608 vmax += ((t[4] & 0x02) ? 255 : 0); 3609 vsync = drm_mode_vrefresh(mode); 3610 3611 return (vsync <= vmax && vsync >= vmin); 3612 } 3613 3614 static u32 3615 range_pixel_clock(const struct edid *edid, const u8 *t) 3616 { 3617 /* unspecified */ 3618 if (t[9] == 0 || t[9] == 255) 3619 return 0; 3620 3621 /* 1.4 with CVT support gives us real precision, yay */ 3622 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3623 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3624 3625 /* 1.3 is pathetic, so fuzz up a bit */ 3626 return t[9] * 10000 + 5001; 3627 } 3628 3629 static bool mode_in_range(const struct drm_display_mode *mode, 3630 const struct drm_edid *drm_edid, 3631 const struct detailed_timing *timing) 3632 { 3633 const struct edid *edid = drm_edid->edid; 3634 u32 max_clock; 3635 const u8 *t = (const u8 *)timing; 3636 3637 if (!mode_in_hsync_range(mode, edid, t)) 3638 return false; 3639 3640 if (!mode_in_vsync_range(mode, edid, t)) 3641 return false; 3642 3643 if ((max_clock = range_pixel_clock(edid, t))) 3644 if (mode->clock > max_clock) 3645 return false; 3646 3647 /* 1.4 max horizontal check */ 3648 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3649 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3650 return false; 3651 3652 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3653 return false; 3654 3655 return true; 3656 } 3657 3658 static bool valid_inferred_mode(const struct drm_connector *connector, 3659 const struct drm_display_mode *mode) 3660 { 3661 const struct drm_display_mode *m; 3662 bool ok = false; 3663 3664 list_for_each_entry(m, &connector->probed_modes, head) { 3665 if (mode->hdisplay == m->hdisplay && 3666 mode->vdisplay == m->vdisplay && 3667 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3668 return false; /* duplicated */ 3669 if (mode->hdisplay <= m->hdisplay && 3670 mode->vdisplay <= m->vdisplay) 3671 ok = true; 3672 } 3673 return ok; 3674 } 3675 3676 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3677 const struct drm_edid *drm_edid, 3678 const struct detailed_timing *timing) 3679 { 3680 int i, modes = 0; 3681 struct drm_display_mode *newmode; 3682 struct drm_device *dev = connector->dev; 3683 3684 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3685 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3686 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3687 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3688 if (newmode) { 3689 drm_mode_probed_add(connector, newmode); 3690 modes++; 3691 } 3692 } 3693 } 3694 3695 return modes; 3696 } 3697 3698 /* fix up 1366x768 mode from 1368x768; 3699 * GFT/CVT can't express 1366 width which isn't dividable by 8 3700 */ 3701 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3702 { 3703 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3704 mode->hdisplay = 1366; 3705 mode->hsync_start--; 3706 mode->hsync_end--; 3707 drm_mode_set_name(mode); 3708 } 3709 } 3710 3711 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3712 const struct drm_edid *drm_edid, 3713 const struct detailed_timing *timing) 3714 { 3715 int i, modes = 0; 3716 struct drm_display_mode *newmode; 3717 struct drm_device *dev = connector->dev; 3718 3719 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3720 const struct minimode *m = &extra_modes[i]; 3721 3722 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3723 if (!newmode) 3724 return modes; 3725 3726 drm_mode_fixup_1366x768(newmode); 3727 if (!mode_in_range(newmode, drm_edid, timing) || 3728 !valid_inferred_mode(connector, newmode)) { 3729 drm_mode_destroy(dev, newmode); 3730 continue; 3731 } 3732 3733 drm_mode_probed_add(connector, newmode); 3734 modes++; 3735 } 3736 3737 return modes; 3738 } 3739 3740 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3741 const struct drm_edid *drm_edid, 3742 const struct detailed_timing *timing) 3743 { 3744 int i, modes = 0; 3745 struct drm_display_mode *newmode; 3746 struct drm_device *dev = connector->dev; 3747 3748 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3749 const struct minimode *m = &extra_modes[i]; 3750 3751 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3752 if (!newmode) 3753 return modes; 3754 3755 drm_mode_fixup_1366x768(newmode); 3756 if (!mode_in_range(newmode, drm_edid, timing) || 3757 !valid_inferred_mode(connector, newmode)) { 3758 drm_mode_destroy(dev, newmode); 3759 continue; 3760 } 3761 3762 drm_mode_probed_add(connector, newmode); 3763 modes++; 3764 } 3765 3766 return modes; 3767 } 3768 3769 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3770 const struct drm_edid *drm_edid, 3771 const struct detailed_timing *timing) 3772 { 3773 int i, modes = 0; 3774 struct drm_display_mode *newmode; 3775 struct drm_device *dev = connector->dev; 3776 bool rb = drm_monitor_supports_rb(drm_edid); 3777 3778 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3779 const struct minimode *m = &extra_modes[i]; 3780 3781 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3782 if (!newmode) 3783 return modes; 3784 3785 drm_mode_fixup_1366x768(newmode); 3786 if (!mode_in_range(newmode, drm_edid, timing) || 3787 !valid_inferred_mode(connector, newmode)) { 3788 drm_mode_destroy(dev, newmode); 3789 continue; 3790 } 3791 3792 drm_mode_probed_add(connector, newmode); 3793 modes++; 3794 } 3795 3796 return modes; 3797 } 3798 3799 static void 3800 do_inferred_modes(const struct detailed_timing *timing, void *c) 3801 { 3802 struct detailed_mode_closure *closure = c; 3803 const struct detailed_non_pixel *data = &timing->data.other_data; 3804 const struct detailed_data_monitor_range *range = &data->data.range; 3805 3806 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3807 return; 3808 3809 closure->modes += drm_dmt_modes_for_range(closure->connector, 3810 closure->drm_edid, 3811 timing); 3812 3813 if (closure->drm_edid->edid->revision < 2) 3814 return; /* GTF not defined yet */ 3815 3816 switch (range->flags) { 3817 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3818 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3819 closure->drm_edid, 3820 timing); 3821 break; 3822 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3823 closure->modes += drm_gtf_modes_for_range(closure->connector, 3824 closure->drm_edid, 3825 timing); 3826 break; 3827 case DRM_EDID_CVT_SUPPORT_FLAG: 3828 if (closure->drm_edid->edid->revision < 4) 3829 break; 3830 3831 closure->modes += drm_cvt_modes_for_range(closure->connector, 3832 closure->drm_edid, 3833 timing); 3834 break; 3835 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3836 default: 3837 break; 3838 } 3839 } 3840 3841 static int add_inferred_modes(struct drm_connector *connector, 3842 const struct drm_edid *drm_edid) 3843 { 3844 struct detailed_mode_closure closure = { 3845 .connector = connector, 3846 .drm_edid = drm_edid, 3847 }; 3848 3849 if (drm_edid->edid->revision >= 1) 3850 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3851 3852 return closure.modes; 3853 } 3854 3855 static int 3856 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3857 { 3858 int i, j, m, modes = 0; 3859 struct drm_display_mode *mode; 3860 const u8 *est = ((const u8 *)timing) + 6; 3861 3862 for (i = 0; i < 6; i++) { 3863 for (j = 7; j >= 0; j--) { 3864 m = (i * 8) + (7 - j); 3865 if (m >= ARRAY_SIZE(est3_modes)) 3866 break; 3867 if (est[i] & (1 << j)) { 3868 mode = drm_mode_find_dmt(connector->dev, 3869 est3_modes[m].w, 3870 est3_modes[m].h, 3871 est3_modes[m].r, 3872 est3_modes[m].rb); 3873 if (mode) { 3874 drm_mode_probed_add(connector, mode); 3875 modes++; 3876 } 3877 } 3878 } 3879 } 3880 3881 return modes; 3882 } 3883 3884 static void 3885 do_established_modes(const struct detailed_timing *timing, void *c) 3886 { 3887 struct detailed_mode_closure *closure = c; 3888 3889 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3890 return; 3891 3892 closure->modes += drm_est3_modes(closure->connector, timing); 3893 } 3894 3895 /* 3896 * Get established modes from EDID and add them. Each EDID block contains a 3897 * bitmap of the supported "established modes" list (defined above). Tease them 3898 * out and add them to the global modes list. 3899 */ 3900 static int add_established_modes(struct drm_connector *connector, 3901 const struct drm_edid *drm_edid) 3902 { 3903 struct drm_device *dev = connector->dev; 3904 const struct edid *edid = drm_edid->edid; 3905 unsigned long est_bits = edid->established_timings.t1 | 3906 (edid->established_timings.t2 << 8) | 3907 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3908 int i, modes = 0; 3909 struct detailed_mode_closure closure = { 3910 .connector = connector, 3911 .drm_edid = drm_edid, 3912 }; 3913 3914 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3915 if (est_bits & (1<<i)) { 3916 struct drm_display_mode *newmode; 3917 3918 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3919 if (newmode) { 3920 drm_mode_probed_add(connector, newmode); 3921 modes++; 3922 } 3923 } 3924 } 3925 3926 if (edid->revision >= 1) 3927 drm_for_each_detailed_block(drm_edid, do_established_modes, 3928 &closure); 3929 3930 return modes + closure.modes; 3931 } 3932 3933 static void 3934 do_standard_modes(const struct detailed_timing *timing, void *c) 3935 { 3936 struct detailed_mode_closure *closure = c; 3937 const struct detailed_non_pixel *data = &timing->data.other_data; 3938 struct drm_connector *connector = closure->connector; 3939 int i; 3940 3941 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3942 return; 3943 3944 for (i = 0; i < 6; i++) { 3945 const struct std_timing *std = &data->data.timings[i]; 3946 struct drm_display_mode *newmode; 3947 3948 newmode = drm_mode_std(connector, closure->drm_edid, std); 3949 if (newmode) { 3950 drm_mode_probed_add(connector, newmode); 3951 closure->modes++; 3952 } 3953 } 3954 } 3955 3956 /* 3957 * Get standard modes from EDID and add them. Standard modes can be calculated 3958 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 3959 * add them to the list. 3960 */ 3961 static int add_standard_modes(struct drm_connector *connector, 3962 const struct drm_edid *drm_edid) 3963 { 3964 int i, modes = 0; 3965 struct detailed_mode_closure closure = { 3966 .connector = connector, 3967 .drm_edid = drm_edid, 3968 }; 3969 3970 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3971 struct drm_display_mode *newmode; 3972 3973 newmode = drm_mode_std(connector, drm_edid, 3974 &drm_edid->edid->standard_timings[i]); 3975 if (newmode) { 3976 drm_mode_probed_add(connector, newmode); 3977 modes++; 3978 } 3979 } 3980 3981 if (drm_edid->edid->revision >= 1) 3982 drm_for_each_detailed_block(drm_edid, do_standard_modes, 3983 &closure); 3984 3985 /* XXX should also look for standard codes in VTB blocks */ 3986 3987 return modes + closure.modes; 3988 } 3989 3990 static int drm_cvt_modes(struct drm_connector *connector, 3991 const struct detailed_timing *timing) 3992 { 3993 int i, j, modes = 0; 3994 struct drm_display_mode *newmode; 3995 struct drm_device *dev = connector->dev; 3996 const struct cvt_timing *cvt; 3997 static const int rates[] = { 60, 85, 75, 60, 50 }; 3998 const u8 empty[3] = { 0, 0, 0 }; 3999 4000 for (i = 0; i < 4; i++) { 4001 int width, height; 4002 4003 cvt = &(timing->data.other_data.data.cvt[i]); 4004 4005 if (!memcmp(cvt->code, empty, 3)) 4006 continue; 4007 4008 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4009 switch (cvt->code[1] & 0x0c) { 4010 /* default - because compiler doesn't see that we've enumerated all cases */ 4011 default: 4012 case 0x00: 4013 width = height * 4 / 3; 4014 break; 4015 case 0x04: 4016 width = height * 16 / 9; 4017 break; 4018 case 0x08: 4019 width = height * 16 / 10; 4020 break; 4021 case 0x0c: 4022 width = height * 15 / 9; 4023 break; 4024 } 4025 4026 for (j = 1; j < 5; j++) { 4027 if (cvt->code[2] & (1 << j)) { 4028 newmode = drm_cvt_mode(dev, width, height, 4029 rates[j], j == 0, 4030 false, false); 4031 if (newmode) { 4032 drm_mode_probed_add(connector, newmode); 4033 modes++; 4034 } 4035 } 4036 } 4037 } 4038 4039 return modes; 4040 } 4041 4042 static void 4043 do_cvt_mode(const struct detailed_timing *timing, void *c) 4044 { 4045 struct detailed_mode_closure *closure = c; 4046 4047 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4048 return; 4049 4050 closure->modes += drm_cvt_modes(closure->connector, timing); 4051 } 4052 4053 static int 4054 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4055 { 4056 struct detailed_mode_closure closure = { 4057 .connector = connector, 4058 .drm_edid = drm_edid, 4059 }; 4060 4061 if (drm_edid->edid->revision >= 3) 4062 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4063 4064 /* XXX should also look for CVT codes in VTB blocks */ 4065 4066 return closure.modes; 4067 } 4068 4069 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4070 struct drm_display_mode *mode); 4071 4072 static void 4073 do_detailed_mode(const struct detailed_timing *timing, void *c) 4074 { 4075 struct detailed_mode_closure *closure = c; 4076 struct drm_display_mode *newmode; 4077 4078 if (!is_detailed_timing_descriptor(timing)) 4079 return; 4080 4081 newmode = drm_mode_detailed(closure->connector, 4082 closure->drm_edid, timing); 4083 if (!newmode) 4084 return; 4085 4086 if (closure->preferred) 4087 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4088 4089 /* 4090 * Detailed modes are limited to 10kHz pixel clock resolution, 4091 * so fix up anything that looks like CEA/HDMI mode, but the clock 4092 * is just slightly off. 4093 */ 4094 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4095 4096 drm_mode_probed_add(closure->connector, newmode); 4097 closure->modes++; 4098 closure->preferred = false; 4099 } 4100 4101 /* 4102 * add_detailed_modes - Add modes from detailed timings 4103 * @connector: attached connector 4104 * @drm_edid: EDID block to scan 4105 */ 4106 static int add_detailed_modes(struct drm_connector *connector, 4107 const struct drm_edid *drm_edid) 4108 { 4109 struct detailed_mode_closure closure = { 4110 .connector = connector, 4111 .drm_edid = drm_edid, 4112 }; 4113 4114 if (drm_edid->edid->revision >= 4) 4115 closure.preferred = true; /* first detailed timing is always preferred */ 4116 else 4117 closure.preferred = 4118 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4119 4120 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4121 4122 return closure.modes; 4123 } 4124 4125 /* CTA-861-H Table 60 - CTA Tag Codes */ 4126 #define CTA_DB_AUDIO 1 4127 #define CTA_DB_VIDEO 2 4128 #define CTA_DB_VENDOR 3 4129 #define CTA_DB_SPEAKER 4 4130 #define CTA_DB_EXTENDED_TAG 7 4131 4132 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4133 #define CTA_EXT_DB_VIDEO_CAP 0 4134 #define CTA_EXT_DB_VENDOR 1 4135 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4136 #define CTA_EXT_DB_420_VIDEO_DATA 14 4137 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4138 #define CTA_EXT_DB_HF_EEODB 0x78 4139 #define CTA_EXT_DB_HF_SCDB 0x79 4140 4141 #define EDID_BASIC_AUDIO (1 << 6) 4142 #define EDID_CEA_YCRCB444 (1 << 5) 4143 #define EDID_CEA_YCRCB422 (1 << 4) 4144 #define EDID_CEA_VCDB_QS (1 << 6) 4145 4146 /* 4147 * Search EDID for CEA extension block. 4148 * 4149 * FIXME: Prefer not returning pointers to raw EDID data. 4150 */ 4151 const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid, 4152 int ext_id, int *ext_index) 4153 { 4154 const u8 *edid_ext = NULL; 4155 int i; 4156 4157 /* No EDID or EDID extensions */ 4158 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4159 return NULL; 4160 4161 /* Find CEA extension */ 4162 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4163 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4164 if (edid_block_tag(edid_ext) == ext_id) 4165 break; 4166 } 4167 4168 if (i >= drm_edid_extension_block_count(drm_edid)) 4169 return NULL; 4170 4171 *ext_index = i + 1; 4172 4173 return edid_ext; 4174 } 4175 4176 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4177 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4178 { 4179 const struct displayid_block *block; 4180 struct displayid_iter iter; 4181 int ext_index = 0; 4182 bool found = false; 4183 4184 /* Look for a top level CEA extension block */ 4185 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index)) 4186 return true; 4187 4188 /* CEA blocks can also be found embedded in a DisplayID block */ 4189 displayid_iter_edid_begin(drm_edid, &iter); 4190 displayid_iter_for_each(block, &iter) { 4191 if (block->tag == DATA_BLOCK_CTA) { 4192 found = true; 4193 break; 4194 } 4195 } 4196 displayid_iter_end(&iter); 4197 4198 return found; 4199 } 4200 4201 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4202 { 4203 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4204 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4205 4206 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4207 return &edid_cea_modes_1[vic - 1]; 4208 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4209 return &edid_cea_modes_193[vic - 193]; 4210 return NULL; 4211 } 4212 4213 static u8 cea_num_vics(void) 4214 { 4215 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4216 } 4217 4218 static u8 cea_next_vic(u8 vic) 4219 { 4220 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4221 vic = 193; 4222 return vic; 4223 } 4224 4225 /* 4226 * Calculate the alternate clock for the CEA mode 4227 * (60Hz vs. 59.94Hz etc.) 4228 */ 4229 static unsigned int 4230 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4231 { 4232 unsigned int clock = cea_mode->clock; 4233 4234 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4235 return clock; 4236 4237 /* 4238 * edid_cea_modes contains the 59.94Hz 4239 * variant for 240 and 480 line modes, 4240 * and the 60Hz variant otherwise. 4241 */ 4242 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4243 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4244 else 4245 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4246 4247 return clock; 4248 } 4249 4250 static bool 4251 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4252 { 4253 /* 4254 * For certain VICs the spec allows the vertical 4255 * front porch to vary by one or two lines. 4256 * 4257 * cea_modes[] stores the variant with the shortest 4258 * vertical front porch. We can adjust the mode to 4259 * get the other variants by simply increasing the 4260 * vertical front porch length. 4261 */ 4262 #ifdef notyet 4263 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4264 cea_mode_for_vic(9)->vtotal != 262 || 4265 cea_mode_for_vic(12)->vtotal != 262 || 4266 cea_mode_for_vic(13)->vtotal != 262 || 4267 cea_mode_for_vic(23)->vtotal != 312 || 4268 cea_mode_for_vic(24)->vtotal != 312 || 4269 cea_mode_for_vic(27)->vtotal != 312 || 4270 cea_mode_for_vic(28)->vtotal != 312); 4271 #endif 4272 4273 if (((vic == 8 || vic == 9 || 4274 vic == 12 || vic == 13) && mode->vtotal < 263) || 4275 ((vic == 23 || vic == 24 || 4276 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4277 mode->vsync_start++; 4278 mode->vsync_end++; 4279 mode->vtotal++; 4280 4281 return true; 4282 } 4283 4284 return false; 4285 } 4286 4287 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4288 unsigned int clock_tolerance) 4289 { 4290 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4291 u8 vic; 4292 4293 if (!to_match->clock) 4294 return 0; 4295 4296 if (to_match->picture_aspect_ratio) 4297 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4298 4299 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4300 struct drm_display_mode cea_mode; 4301 unsigned int clock1, clock2; 4302 4303 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4304 4305 /* Check both 60Hz and 59.94Hz */ 4306 clock1 = cea_mode.clock; 4307 clock2 = cea_mode_alternate_clock(&cea_mode); 4308 4309 if (abs(to_match->clock - clock1) > clock_tolerance && 4310 abs(to_match->clock - clock2) > clock_tolerance) 4311 continue; 4312 4313 do { 4314 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4315 return vic; 4316 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4317 } 4318 4319 return 0; 4320 } 4321 4322 /** 4323 * drm_match_cea_mode - look for a CEA mode matching given mode 4324 * @to_match: display mode 4325 * 4326 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4327 * mode. 4328 */ 4329 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4330 { 4331 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4332 u8 vic; 4333 4334 if (!to_match->clock) 4335 return 0; 4336 4337 if (to_match->picture_aspect_ratio) 4338 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4339 4340 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4341 struct drm_display_mode cea_mode; 4342 unsigned int clock1, clock2; 4343 4344 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4345 4346 /* Check both 60Hz and 59.94Hz */ 4347 clock1 = cea_mode.clock; 4348 clock2 = cea_mode_alternate_clock(&cea_mode); 4349 4350 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4351 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4352 continue; 4353 4354 do { 4355 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4356 return vic; 4357 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4358 } 4359 4360 return 0; 4361 } 4362 EXPORT_SYMBOL(drm_match_cea_mode); 4363 4364 static bool drm_valid_cea_vic(u8 vic) 4365 { 4366 return cea_mode_for_vic(vic) != NULL; 4367 } 4368 4369 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4370 { 4371 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4372 4373 if (mode) 4374 return mode->picture_aspect_ratio; 4375 4376 return HDMI_PICTURE_ASPECT_NONE; 4377 } 4378 4379 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4380 { 4381 return edid_4k_modes[video_code].picture_aspect_ratio; 4382 } 4383 4384 /* 4385 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4386 * specific block). 4387 */ 4388 static unsigned int 4389 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4390 { 4391 return cea_mode_alternate_clock(hdmi_mode); 4392 } 4393 4394 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4395 unsigned int clock_tolerance) 4396 { 4397 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4398 u8 vic; 4399 4400 if (!to_match->clock) 4401 return 0; 4402 4403 if (to_match->picture_aspect_ratio) 4404 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4405 4406 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4407 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4408 unsigned int clock1, clock2; 4409 4410 /* Make sure to also match alternate clocks */ 4411 clock1 = hdmi_mode->clock; 4412 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4413 4414 if (abs(to_match->clock - clock1) > clock_tolerance && 4415 abs(to_match->clock - clock2) > clock_tolerance) 4416 continue; 4417 4418 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4419 return vic; 4420 } 4421 4422 return 0; 4423 } 4424 4425 /* 4426 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4427 * @to_match: display mode 4428 * 4429 * An HDMI mode is one defined in the HDMI vendor specific block. 4430 * 4431 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4432 */ 4433 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4434 { 4435 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4436 u8 vic; 4437 4438 if (!to_match->clock) 4439 return 0; 4440 4441 if (to_match->picture_aspect_ratio) 4442 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4443 4444 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4445 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4446 unsigned int clock1, clock2; 4447 4448 /* Make sure to also match alternate clocks */ 4449 clock1 = hdmi_mode->clock; 4450 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4451 4452 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4453 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4454 drm_mode_match(to_match, hdmi_mode, match_flags)) 4455 return vic; 4456 } 4457 return 0; 4458 } 4459 4460 static bool drm_valid_hdmi_vic(u8 vic) 4461 { 4462 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4463 } 4464 4465 static int add_alternate_cea_modes(struct drm_connector *connector, 4466 const struct drm_edid *drm_edid) 4467 { 4468 struct drm_device *dev = connector->dev; 4469 struct drm_display_mode *mode, *tmp; 4470 DRM_LIST_HEAD(list); 4471 int modes = 0; 4472 4473 /* Don't add CTA modes if the CTA extension block is missing */ 4474 if (!drm_edid_has_cta_extension(drm_edid)) 4475 return 0; 4476 4477 /* 4478 * Go through all probed modes and create a new mode 4479 * with the alternate clock for certain CEA modes. 4480 */ 4481 list_for_each_entry(mode, &connector->probed_modes, head) { 4482 const struct drm_display_mode *cea_mode = NULL; 4483 struct drm_display_mode *newmode; 4484 u8 vic = drm_match_cea_mode(mode); 4485 unsigned int clock1, clock2; 4486 4487 if (drm_valid_cea_vic(vic)) { 4488 cea_mode = cea_mode_for_vic(vic); 4489 clock2 = cea_mode_alternate_clock(cea_mode); 4490 } else { 4491 vic = drm_match_hdmi_mode(mode); 4492 if (drm_valid_hdmi_vic(vic)) { 4493 cea_mode = &edid_4k_modes[vic]; 4494 clock2 = hdmi_mode_alternate_clock(cea_mode); 4495 } 4496 } 4497 4498 if (!cea_mode) 4499 continue; 4500 4501 clock1 = cea_mode->clock; 4502 4503 if (clock1 == clock2) 4504 continue; 4505 4506 if (mode->clock != clock1 && mode->clock != clock2) 4507 continue; 4508 4509 newmode = drm_mode_duplicate(dev, cea_mode); 4510 if (!newmode) 4511 continue; 4512 4513 /* Carry over the stereo flags */ 4514 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4515 4516 /* 4517 * The current mode could be either variant. Make 4518 * sure to pick the "other" clock for the new mode. 4519 */ 4520 if (mode->clock != clock1) 4521 newmode->clock = clock1; 4522 else 4523 newmode->clock = clock2; 4524 4525 list_add_tail(&newmode->head, &list); 4526 } 4527 4528 list_for_each_entry_safe(mode, tmp, &list, head) { 4529 list_del(&mode->head); 4530 drm_mode_probed_add(connector, mode); 4531 modes++; 4532 } 4533 4534 return modes; 4535 } 4536 4537 static u8 svd_to_vic(u8 svd) 4538 { 4539 /* 0-6 bit vic, 7th bit native mode indicator */ 4540 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4541 return svd & 127; 4542 4543 return svd; 4544 } 4545 4546 /* 4547 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4548 * the EDID, or NULL on errors. 4549 */ 4550 static struct drm_display_mode * 4551 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4552 { 4553 const struct drm_display_info *info = &connector->display_info; 4554 struct drm_device *dev = connector->dev; 4555 4556 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4557 return NULL; 4558 4559 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4560 } 4561 4562 /* 4563 * do_y420vdb_modes - Parse YCBCR 420 only modes 4564 * @connector: connector corresponding to the HDMI sink 4565 * @svds: start of the data block of CEA YCBCR 420 VDB 4566 * @len: length of the CEA YCBCR 420 VDB 4567 * 4568 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4569 * which contains modes which can be supported in YCBCR 420 4570 * output format only. 4571 */ 4572 static int do_y420vdb_modes(struct drm_connector *connector, 4573 const u8 *svds, u8 svds_len) 4574 { 4575 struct drm_device *dev = connector->dev; 4576 int modes = 0, i; 4577 4578 for (i = 0; i < svds_len; i++) { 4579 u8 vic = svd_to_vic(svds[i]); 4580 struct drm_display_mode *newmode; 4581 4582 if (!drm_valid_cea_vic(vic)) 4583 continue; 4584 4585 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4586 if (!newmode) 4587 break; 4588 drm_mode_probed_add(connector, newmode); 4589 modes++; 4590 } 4591 4592 return modes; 4593 } 4594 4595 /** 4596 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4597 * @dev: DRM device 4598 * @video_code: CEA VIC of the mode 4599 * 4600 * Creates a new mode matching the specified CEA VIC. 4601 * 4602 * Returns: A new drm_display_mode on success or NULL on failure 4603 */ 4604 struct drm_display_mode * 4605 drm_display_mode_from_cea_vic(struct drm_device *dev, 4606 u8 video_code) 4607 { 4608 const struct drm_display_mode *cea_mode; 4609 struct drm_display_mode *newmode; 4610 4611 cea_mode = cea_mode_for_vic(video_code); 4612 if (!cea_mode) 4613 return NULL; 4614 4615 newmode = drm_mode_duplicate(dev, cea_mode); 4616 if (!newmode) 4617 return NULL; 4618 4619 return newmode; 4620 } 4621 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4622 4623 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4624 static int add_cta_vdb_modes(struct drm_connector *connector) 4625 { 4626 const struct drm_display_info *info = &connector->display_info; 4627 int i, modes = 0; 4628 4629 if (!info->vics) 4630 return 0; 4631 4632 for (i = 0; i < info->vics_len; i++) { 4633 struct drm_display_mode *mode; 4634 4635 mode = drm_display_mode_from_vic_index(connector, i); 4636 if (mode) { 4637 drm_mode_probed_add(connector, mode); 4638 modes++; 4639 } 4640 } 4641 4642 return modes; 4643 } 4644 4645 struct stereo_mandatory_mode { 4646 int width, height, vrefresh; 4647 unsigned int flags; 4648 }; 4649 4650 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4651 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4652 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4653 { 1920, 1080, 50, 4654 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4655 { 1920, 1080, 60, 4656 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4657 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4658 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4659 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4660 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4661 }; 4662 4663 static bool 4664 stereo_match_mandatory(const struct drm_display_mode *mode, 4665 const struct stereo_mandatory_mode *stereo_mode) 4666 { 4667 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4668 4669 return mode->hdisplay == stereo_mode->width && 4670 mode->vdisplay == stereo_mode->height && 4671 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4672 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4673 } 4674 4675 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4676 { 4677 struct drm_device *dev = connector->dev; 4678 const struct drm_display_mode *mode; 4679 struct list_head stereo_modes; 4680 int modes = 0, i; 4681 4682 INIT_LIST_HEAD(&stereo_modes); 4683 4684 list_for_each_entry(mode, &connector->probed_modes, head) { 4685 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4686 const struct stereo_mandatory_mode *mandatory; 4687 struct drm_display_mode *new_mode; 4688 4689 if (!stereo_match_mandatory(mode, 4690 &stereo_mandatory_modes[i])) 4691 continue; 4692 4693 mandatory = &stereo_mandatory_modes[i]; 4694 new_mode = drm_mode_duplicate(dev, mode); 4695 if (!new_mode) 4696 continue; 4697 4698 new_mode->flags |= mandatory->flags; 4699 list_add_tail(&new_mode->head, &stereo_modes); 4700 modes++; 4701 } 4702 } 4703 4704 list_splice_tail(&stereo_modes, &connector->probed_modes); 4705 4706 return modes; 4707 } 4708 4709 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4710 { 4711 struct drm_device *dev = connector->dev; 4712 struct drm_display_mode *newmode; 4713 4714 if (!drm_valid_hdmi_vic(vic)) { 4715 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4716 connector->base.id, connector->name, vic); 4717 return 0; 4718 } 4719 4720 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4721 if (!newmode) 4722 return 0; 4723 4724 drm_mode_probed_add(connector, newmode); 4725 4726 return 1; 4727 } 4728 4729 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4730 int vic_index) 4731 { 4732 struct drm_display_mode *newmode; 4733 int modes = 0; 4734 4735 if (structure & (1 << 0)) { 4736 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4737 if (newmode) { 4738 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4739 drm_mode_probed_add(connector, newmode); 4740 modes++; 4741 } 4742 } 4743 if (structure & (1 << 6)) { 4744 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4745 if (newmode) { 4746 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4747 drm_mode_probed_add(connector, newmode); 4748 modes++; 4749 } 4750 } 4751 if (structure & (1 << 8)) { 4752 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4753 if (newmode) { 4754 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4755 drm_mode_probed_add(connector, newmode); 4756 modes++; 4757 } 4758 } 4759 4760 return modes; 4761 } 4762 4763 static bool hdmi_vsdb_latency_present(const u8 *db) 4764 { 4765 return db[8] & BIT(7); 4766 } 4767 4768 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4769 { 4770 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4771 } 4772 4773 static int hdmi_vsdb_latency_length(const u8 *db) 4774 { 4775 if (hdmi_vsdb_i_latency_present(db)) 4776 return 4; 4777 else if (hdmi_vsdb_latency_present(db)) 4778 return 2; 4779 else 4780 return 0; 4781 } 4782 4783 /* 4784 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4785 * @connector: connector corresponding to the HDMI sink 4786 * @db: start of the CEA vendor specific block 4787 * @len: length of the CEA block payload, ie. one can access up to db[len] 4788 * 4789 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4790 * also adds the stereo 3d modes when applicable. 4791 */ 4792 static int 4793 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4794 { 4795 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4796 u8 vic_len, hdmi_3d_len = 0; 4797 u16 mask; 4798 u16 structure_all; 4799 4800 if (len < 8) 4801 goto out; 4802 4803 /* no HDMI_Video_Present */ 4804 if (!(db[8] & (1 << 5))) 4805 goto out; 4806 4807 offset += hdmi_vsdb_latency_length(db); 4808 4809 /* the declared length is not long enough for the 2 first bytes 4810 * of additional video format capabilities */ 4811 if (len < (8 + offset + 2)) 4812 goto out; 4813 4814 /* 3D_Present */ 4815 offset++; 4816 if (db[8 + offset] & (1 << 7)) { 4817 modes += add_hdmi_mandatory_stereo_modes(connector); 4818 4819 /* 3D_Multi_present */ 4820 multi_present = (db[8 + offset] & 0x60) >> 5; 4821 } 4822 4823 offset++; 4824 vic_len = db[8 + offset] >> 5; 4825 hdmi_3d_len = db[8 + offset] & 0x1f; 4826 4827 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4828 u8 vic; 4829 4830 vic = db[9 + offset + i]; 4831 modes += add_hdmi_mode(connector, vic); 4832 } 4833 offset += 1 + vic_len; 4834 4835 if (multi_present == 1) 4836 multi_len = 2; 4837 else if (multi_present == 2) 4838 multi_len = 4; 4839 else 4840 multi_len = 0; 4841 4842 if (len < (8 + offset + hdmi_3d_len - 1)) 4843 goto out; 4844 4845 if (hdmi_3d_len < multi_len) 4846 goto out; 4847 4848 if (multi_present == 1 || multi_present == 2) { 4849 /* 3D_Structure_ALL */ 4850 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4851 4852 /* check if 3D_MASK is present */ 4853 if (multi_present == 2) 4854 mask = (db[10 + offset] << 8) | db[11 + offset]; 4855 else 4856 mask = 0xffff; 4857 4858 for (i = 0; i < 16; i++) { 4859 if (mask & (1 << i)) 4860 modes += add_3d_struct_modes(connector, 4861 structure_all, i); 4862 } 4863 } 4864 4865 offset += multi_len; 4866 4867 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4868 int vic_index; 4869 struct drm_display_mode *newmode = NULL; 4870 unsigned int newflag = 0; 4871 bool detail_present; 4872 4873 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4874 4875 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4876 break; 4877 4878 /* 2D_VIC_order_X */ 4879 vic_index = db[8 + offset + i] >> 4; 4880 4881 /* 3D_Structure_X */ 4882 switch (db[8 + offset + i] & 0x0f) { 4883 case 0: 4884 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4885 break; 4886 case 6: 4887 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4888 break; 4889 case 8: 4890 /* 3D_Detail_X */ 4891 if ((db[9 + offset + i] >> 4) == 1) 4892 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4893 break; 4894 } 4895 4896 if (newflag != 0) { 4897 newmode = drm_display_mode_from_vic_index(connector, 4898 vic_index); 4899 4900 if (newmode) { 4901 newmode->flags |= newflag; 4902 drm_mode_probed_add(connector, newmode); 4903 modes++; 4904 } 4905 } 4906 4907 if (detail_present) 4908 i++; 4909 } 4910 4911 out: 4912 return modes; 4913 } 4914 4915 static int 4916 cea_revision(const u8 *cea) 4917 { 4918 /* 4919 * FIXME is this correct for the DispID variant? 4920 * The DispID spec doesn't really specify whether 4921 * this is the revision of the CEA extension or 4922 * the DispID CEA data block. And the only value 4923 * given as an example is 0. 4924 */ 4925 return cea[1]; 4926 } 4927 4928 /* 4929 * CTA Data Block iterator. 4930 * 4931 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4932 * CTA Data Blocks. 4933 * 4934 * struct cea_db *db: 4935 * struct cea_db_iter iter; 4936 * 4937 * cea_db_iter_edid_begin(edid, &iter); 4938 * cea_db_iter_for_each(db, &iter) { 4939 * // do stuff with db 4940 * } 4941 * cea_db_iter_end(&iter); 4942 */ 4943 struct cea_db_iter { 4944 struct drm_edid_iter edid_iter; 4945 struct displayid_iter displayid_iter; 4946 4947 /* Current Data Block Collection. */ 4948 const u8 *collection; 4949 4950 /* Current Data Block index in current collection. */ 4951 int index; 4952 4953 /* End index in current collection. */ 4954 int end; 4955 }; 4956 4957 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 4958 struct cea_db { 4959 u8 tag_length; 4960 u8 data[]; 4961 } __packed; 4962 4963 static int cea_db_tag(const struct cea_db *db) 4964 { 4965 return db->tag_length >> 5; 4966 } 4967 4968 static int cea_db_payload_len(const void *_db) 4969 { 4970 /* FIXME: Transition to passing struct cea_db * everywhere. */ 4971 const struct cea_db *db = _db; 4972 4973 return db->tag_length & 0x1f; 4974 } 4975 4976 static const void *cea_db_data(const struct cea_db *db) 4977 { 4978 return db->data; 4979 } 4980 4981 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 4982 { 4983 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 4984 cea_db_payload_len(db) >= 1 && 4985 db->data[0] == tag; 4986 } 4987 4988 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 4989 { 4990 const u8 *data = cea_db_data(db); 4991 4992 return cea_db_tag(db) == CTA_DB_VENDOR && 4993 cea_db_payload_len(db) >= 3 && 4994 oui(data[2], data[1], data[0]) == vendor_oui; 4995 } 4996 4997 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 4998 struct cea_db_iter *iter) 4999 { 5000 memset(iter, 0, sizeof(*iter)); 5001 5002 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 5003 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 5004 } 5005 5006 static const struct cea_db * 5007 __cea_db_iter_current_block(const struct cea_db_iter *iter) 5008 { 5009 const struct cea_db *db; 5010 5011 if (!iter->collection) 5012 return NULL; 5013 5014 db = (const struct cea_db *)&iter->collection[iter->index]; 5015 5016 if (iter->index + sizeof(*db) <= iter->end && 5017 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 5018 return db; 5019 5020 return NULL; 5021 } 5022 5023 /* 5024 * References: 5025 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5026 */ 5027 static int cea_db_collection_size(const u8 *cta) 5028 { 5029 u8 d = cta[2]; 5030 5031 if (d < 4 || d > 127) 5032 return 0; 5033 5034 return d - 4; 5035 } 5036 5037 /* 5038 * References: 5039 * - VESA E-EDID v1.4 5040 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5041 */ 5042 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5043 { 5044 const u8 *ext; 5045 5046 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5047 int size; 5048 5049 /* Only support CTA Extension revision 3+ */ 5050 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5051 continue; 5052 5053 size = cea_db_collection_size(ext); 5054 if (!size) 5055 continue; 5056 5057 iter->index = 4; 5058 iter->end = iter->index + size; 5059 5060 return ext; 5061 } 5062 5063 return NULL; 5064 } 5065 5066 /* 5067 * References: 5068 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5069 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5070 * 5071 * Note that the above do not specify any connection between DisplayID Data 5072 * Block revision and CTA Extension versions. 5073 */ 5074 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5075 { 5076 const struct displayid_block *block; 5077 5078 displayid_iter_for_each(block, &iter->displayid_iter) { 5079 if (block->tag != DATA_BLOCK_CTA) 5080 continue; 5081 5082 /* 5083 * The displayid iterator has already verified the block bounds 5084 * in displayid_iter_block(). 5085 */ 5086 iter->index = sizeof(*block); 5087 iter->end = iter->index + block->num_bytes; 5088 5089 return block; 5090 } 5091 5092 return NULL; 5093 } 5094 5095 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5096 { 5097 const struct cea_db *db; 5098 5099 if (iter->collection) { 5100 /* Current collection should always be valid. */ 5101 db = __cea_db_iter_current_block(iter); 5102 if (WARN_ON(!db)) { 5103 iter->collection = NULL; 5104 return NULL; 5105 } 5106 5107 /* Next block in CTA Data Block Collection */ 5108 iter->index += sizeof(*db) + cea_db_payload_len(db); 5109 5110 db = __cea_db_iter_current_block(iter); 5111 if (db) 5112 return db; 5113 } 5114 5115 for (;;) { 5116 /* 5117 * Find the next CTA Data Block Collection. First iterate all 5118 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5119 * 5120 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5121 * Extension, it's recommended that DisplayID extensions are 5122 * exposed after all of the CTA Extensions. 5123 */ 5124 iter->collection = __cea_db_iter_edid_next(iter); 5125 if (!iter->collection) 5126 iter->collection = __cea_db_iter_displayid_next(iter); 5127 5128 if (!iter->collection) 5129 return NULL; 5130 5131 db = __cea_db_iter_current_block(iter); 5132 if (db) 5133 return db; 5134 } 5135 } 5136 5137 #define cea_db_iter_for_each(__db, __iter) \ 5138 while (((__db) = __cea_db_iter_next(__iter))) 5139 5140 static void cea_db_iter_end(struct cea_db_iter *iter) 5141 { 5142 displayid_iter_end(&iter->displayid_iter); 5143 drm_edid_iter_end(&iter->edid_iter); 5144 5145 memset(iter, 0, sizeof(*iter)); 5146 } 5147 5148 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5149 { 5150 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5151 cea_db_payload_len(db) >= 5; 5152 } 5153 5154 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5155 { 5156 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5157 cea_db_payload_len(db) >= 7; 5158 } 5159 5160 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5161 { 5162 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5163 cea_db_payload_len(db) >= 2; 5164 } 5165 5166 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5167 { 5168 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5169 cea_db_payload_len(db) == 21; 5170 } 5171 5172 static bool cea_db_is_vcdb(const struct cea_db *db) 5173 { 5174 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5175 cea_db_payload_len(db) == 2; 5176 } 5177 5178 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5179 { 5180 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5181 cea_db_payload_len(db) >= 7; 5182 } 5183 5184 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5185 { 5186 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5187 } 5188 5189 static bool cea_db_is_y420vdb(const struct cea_db *db) 5190 { 5191 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5192 } 5193 5194 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5195 { 5196 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5197 cea_db_payload_len(db) >= 3; 5198 } 5199 5200 /* 5201 * Get the HF-EEODB override extension block count from EDID. 5202 * 5203 * The passed in EDID may be partially read, as long as it has at least two 5204 * blocks (base block and one extension block) if EDID extension count is > 0. 5205 * 5206 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5207 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5208 * iterators instead. 5209 * 5210 * References: 5211 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5212 */ 5213 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5214 { 5215 const u8 *cta; 5216 5217 /* No extensions according to base block, no HF-EEODB. */ 5218 if (!edid_extension_block_count(edid)) 5219 return 0; 5220 5221 /* HF-EEODB is always in the first EDID extension block only */ 5222 cta = edid_extension_block_data(edid, 0); 5223 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5224 return 0; 5225 5226 /* Need to have the data block collection, and at least 3 bytes. */ 5227 if (cea_db_collection_size(cta) < 3) 5228 return 0; 5229 5230 /* 5231 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5232 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5233 * through 6 of Block 1 of the E-EDID. 5234 */ 5235 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5236 return 0; 5237 5238 return cta[4 + 2]; 5239 } 5240 5241 /* 5242 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5243 * 5244 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5245 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5246 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5247 * support YCBCR420 output too. 5248 */ 5249 static void parse_cta_y420cmdb(struct drm_connector *connector, 5250 const struct cea_db *db, u64 *y420cmdb_map) 5251 { 5252 struct drm_display_info *info = &connector->display_info; 5253 int i, map_len = cea_db_payload_len(db) - 1; 5254 const u8 *data = cea_db_data(db) + 1; 5255 u64 map = 0; 5256 5257 if (map_len == 0) { 5258 /* All CEA modes support ycbcr420 sampling also.*/ 5259 map = U64_MAX; 5260 goto out; 5261 } 5262 5263 /* 5264 * This map indicates which of the existing CEA block modes 5265 * from VDB can support YCBCR420 output too. So if bit=0 is 5266 * set, first mode from VDB can support YCBCR420 output too. 5267 * We will parse and keep this map, before parsing VDB itself 5268 * to avoid going through the same block again and again. 5269 * 5270 * Spec is not clear about max possible size of this block. 5271 * Clamping max bitmap block size at 8 bytes. Every byte can 5272 * address 8 CEA modes, in this way this map can address 5273 * 8*8 = first 64 SVDs. 5274 */ 5275 if (WARN_ON_ONCE(map_len > 8)) 5276 map_len = 8; 5277 5278 for (i = 0; i < map_len; i++) 5279 map |= (u64)data[i] << (8 * i); 5280 5281 out: 5282 if (map) 5283 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5284 5285 *y420cmdb_map = map; 5286 } 5287 5288 static int add_cea_modes(struct drm_connector *connector, 5289 const struct drm_edid *drm_edid) 5290 { 5291 const struct cea_db *db; 5292 struct cea_db_iter iter; 5293 int modes; 5294 5295 /* CTA VDB block VICs parsed earlier */ 5296 modes = add_cta_vdb_modes(connector); 5297 5298 cea_db_iter_edid_begin(drm_edid, &iter); 5299 cea_db_iter_for_each(db, &iter) { 5300 if (cea_db_is_hdmi_vsdb(db)) { 5301 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5302 cea_db_payload_len(db)); 5303 } else if (cea_db_is_y420vdb(db)) { 5304 const u8 *vdb420 = cea_db_data(db) + 1; 5305 5306 /* Add 4:2:0(only) modes present in EDID */ 5307 modes += do_y420vdb_modes(connector, vdb420, 5308 cea_db_payload_len(db) - 1); 5309 } 5310 } 5311 cea_db_iter_end(&iter); 5312 5313 return modes; 5314 } 5315 5316 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5317 struct drm_display_mode *mode) 5318 { 5319 const struct drm_display_mode *cea_mode; 5320 int clock1, clock2, clock; 5321 u8 vic; 5322 const char *type; 5323 5324 /* 5325 * allow 5kHz clock difference either way to account for 5326 * the 10kHz clock resolution limit of detailed timings. 5327 */ 5328 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5329 if (drm_valid_cea_vic(vic)) { 5330 type = "CEA"; 5331 cea_mode = cea_mode_for_vic(vic); 5332 clock1 = cea_mode->clock; 5333 clock2 = cea_mode_alternate_clock(cea_mode); 5334 } else { 5335 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5336 if (drm_valid_hdmi_vic(vic)) { 5337 type = "HDMI"; 5338 cea_mode = &edid_4k_modes[vic]; 5339 clock1 = cea_mode->clock; 5340 clock2 = hdmi_mode_alternate_clock(cea_mode); 5341 } else { 5342 return; 5343 } 5344 } 5345 5346 /* pick whichever is closest */ 5347 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5348 clock = clock1; 5349 else 5350 clock = clock2; 5351 5352 if (mode->clock == clock) 5353 return; 5354 5355 drm_dbg_kms(connector->dev, 5356 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5357 connector->base.id, connector->name, 5358 type, vic, mode->clock, clock); 5359 mode->clock = clock; 5360 } 5361 5362 static void drm_calculate_luminance_range(struct drm_connector *connector) 5363 { 5364 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5365 struct drm_luminance_range_info *luminance_range = 5366 &connector->display_info.luminance_range; 5367 static const u8 pre_computed_values[] = { 5368 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5369 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5370 }; 5371 u32 max_avg, min_cll, max, min, q, r; 5372 5373 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5374 return; 5375 5376 max_avg = hdr_metadata->max_fall; 5377 min_cll = hdr_metadata->min_cll; 5378 5379 /* 5380 * From the specification (CTA-861-G), for calculating the maximum 5381 * luminance we need to use: 5382 * Luminance = 50*2**(CV/32) 5383 * Where CV is a one-byte value. 5384 * For calculating this expression we may need float point precision; 5385 * to avoid this complexity level, we take advantage that CV is divided 5386 * by a constant. From the Euclids division algorithm, we know that CV 5387 * can be written as: CV = 32*q + r. Next, we replace CV in the 5388 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5389 * need to pre-compute the value of r/32. For pre-computing the values 5390 * We just used the following Ruby line: 5391 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5392 * The results of the above expressions can be verified at 5393 * pre_computed_values. 5394 */ 5395 q = max_avg >> 5; 5396 r = max_avg % 32; 5397 max = (1 << q) * pre_computed_values[r]; 5398 5399 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5400 q = DIV_ROUND_CLOSEST(min_cll, 255); 5401 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5402 5403 luminance_range->min_luminance = min; 5404 luminance_range->max_luminance = max; 5405 } 5406 5407 static uint8_t eotf_supported(const u8 *edid_ext) 5408 { 5409 return edid_ext[2] & 5410 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5411 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5412 BIT(HDMI_EOTF_SMPTE_ST2084) | 5413 BIT(HDMI_EOTF_BT_2100_HLG)); 5414 } 5415 5416 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5417 { 5418 return edid_ext[3] & 5419 BIT(HDMI_STATIC_METADATA_TYPE1); 5420 } 5421 5422 static void 5423 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5424 { 5425 u16 len; 5426 5427 len = cea_db_payload_len(db); 5428 5429 connector->hdr_sink_metadata.hdmi_type1.eotf = 5430 eotf_supported(db); 5431 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5432 hdr_metadata_type(db); 5433 5434 if (len >= 4) 5435 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5436 if (len >= 5) 5437 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5438 if (len >= 6) { 5439 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5440 5441 /* Calculate only when all values are available */ 5442 drm_calculate_luminance_range(connector); 5443 } 5444 } 5445 5446 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5447 static void 5448 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5449 { 5450 u8 len = cea_db_payload_len(db); 5451 5452 if (len >= 6 && (db[6] & (1 << 7))) 5453 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5454 5455 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5456 connector->latency_present[0] = true; 5457 connector->video_latency[0] = db[9]; 5458 connector->audio_latency[0] = db[10]; 5459 } 5460 5461 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5462 connector->latency_present[1] = true; 5463 connector->video_latency[1] = db[11]; 5464 connector->audio_latency[1] = db[12]; 5465 } 5466 5467 drm_dbg_kms(connector->dev, 5468 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5469 connector->base.id, connector->name, 5470 connector->latency_present[0], connector->latency_present[1], 5471 connector->video_latency[0], connector->video_latency[1], 5472 connector->audio_latency[0], connector->audio_latency[1]); 5473 } 5474 5475 static void 5476 monitor_name(const struct detailed_timing *timing, void *data) 5477 { 5478 const char **res = data; 5479 5480 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5481 return; 5482 5483 *res = timing->data.other_data.data.str.str; 5484 } 5485 5486 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5487 { 5488 const char *edid_name = NULL; 5489 int mnl; 5490 5491 if (!drm_edid || !name) 5492 return 0; 5493 5494 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5495 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5496 if (edid_name[mnl] == 0x0a) 5497 break; 5498 5499 name[mnl] = edid_name[mnl]; 5500 } 5501 5502 return mnl; 5503 } 5504 5505 /** 5506 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5507 * @edid: monitor EDID information 5508 * @name: pointer to a character array to hold the name of the monitor 5509 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5510 * 5511 */ 5512 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5513 { 5514 int name_length = 0; 5515 5516 if (bufsize <= 0) 5517 return; 5518 5519 if (edid) { 5520 char buf[13]; 5521 struct drm_edid drm_edid = { 5522 .edid = edid, 5523 .size = edid_size(edid), 5524 }; 5525 5526 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5527 memcpy(name, buf, name_length); 5528 } 5529 5530 name[name_length] = '\0'; 5531 } 5532 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5533 5534 static void clear_eld(struct drm_connector *connector) 5535 { 5536 memset(connector->eld, 0, sizeof(connector->eld)); 5537 5538 connector->latency_present[0] = false; 5539 connector->latency_present[1] = false; 5540 connector->video_latency[0] = 0; 5541 connector->audio_latency[0] = 0; 5542 connector->video_latency[1] = 0; 5543 connector->audio_latency[1] = 0; 5544 } 5545 5546 /* 5547 * drm_edid_to_eld - build ELD from EDID 5548 * @connector: connector corresponding to the HDMI/DP sink 5549 * @drm_edid: EDID to parse 5550 * 5551 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5552 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5553 */ 5554 static void drm_edid_to_eld(struct drm_connector *connector, 5555 const struct drm_edid *drm_edid) 5556 { 5557 const struct drm_display_info *info = &connector->display_info; 5558 const struct cea_db *db; 5559 struct cea_db_iter iter; 5560 uint8_t *eld = connector->eld; 5561 int total_sad_count = 0; 5562 int mnl; 5563 5564 if (!drm_edid) 5565 return; 5566 5567 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5568 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5569 connector->base.id, connector->name, 5570 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5571 5572 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5573 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5574 5575 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5576 5577 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5578 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5579 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5580 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5581 5582 cea_db_iter_edid_begin(drm_edid, &iter); 5583 cea_db_iter_for_each(db, &iter) { 5584 const u8 *data = cea_db_data(db); 5585 int len = cea_db_payload_len(db); 5586 int sad_count; 5587 5588 switch (cea_db_tag(db)) { 5589 case CTA_DB_AUDIO: 5590 /* Audio Data Block, contains SADs */ 5591 sad_count = min(len / 3, 15 - total_sad_count); 5592 if (sad_count >= 1) 5593 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5594 data, sad_count * 3); 5595 total_sad_count += sad_count; 5596 break; 5597 case CTA_DB_SPEAKER: 5598 /* Speaker Allocation Data Block */ 5599 if (len >= 1) 5600 eld[DRM_ELD_SPEAKER] = data[0]; 5601 break; 5602 case CTA_DB_VENDOR: 5603 /* HDMI Vendor-Specific Data Block */ 5604 if (cea_db_is_hdmi_vsdb(db)) 5605 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5606 break; 5607 default: 5608 break; 5609 } 5610 } 5611 cea_db_iter_end(&iter); 5612 5613 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5614 5615 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5616 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5617 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5618 else 5619 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5620 5621 eld[DRM_ELD_BASELINE_ELD_LEN] = 5622 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5623 5624 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5625 connector->base.id, connector->name, 5626 drm_eld_size(eld), total_sad_count); 5627 } 5628 5629 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5630 struct cea_sad **sads) 5631 { 5632 const struct cea_db *db; 5633 struct cea_db_iter iter; 5634 int count = 0; 5635 5636 cea_db_iter_edid_begin(drm_edid, &iter); 5637 cea_db_iter_for_each(db, &iter) { 5638 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5639 int j; 5640 5641 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5642 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 5643 if (!*sads) 5644 return -ENOMEM; 5645 for (j = 0; j < count; j++) { 5646 const u8 *sad = &db->data[j * 3]; 5647 5648 (*sads)[j].format = (sad[0] & 0x78) >> 3; 5649 (*sads)[j].channels = sad[0] & 0x7; 5650 (*sads)[j].freq = sad[1] & 0x7F; 5651 (*sads)[j].byte2 = sad[2]; 5652 } 5653 break; 5654 } 5655 } 5656 cea_db_iter_end(&iter); 5657 5658 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5659 5660 return count; 5661 } 5662 5663 /** 5664 * drm_edid_to_sad - extracts SADs from EDID 5665 * @edid: EDID to parse 5666 * @sads: pointer that will be set to the extracted SADs 5667 * 5668 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5669 * 5670 * Note: The returned pointer needs to be freed using kfree(). 5671 * 5672 * Return: The number of found SADs or negative number on error. 5673 */ 5674 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5675 { 5676 struct drm_edid drm_edid; 5677 5678 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5679 } 5680 EXPORT_SYMBOL(drm_edid_to_sad); 5681 5682 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5683 u8 **sadb) 5684 { 5685 const struct cea_db *db; 5686 struct cea_db_iter iter; 5687 int count = 0; 5688 5689 cea_db_iter_edid_begin(drm_edid, &iter); 5690 cea_db_iter_for_each(db, &iter) { 5691 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5692 cea_db_payload_len(db) == 3) { 5693 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5694 GFP_KERNEL); 5695 if (!*sadb) 5696 return -ENOMEM; 5697 count = cea_db_payload_len(db); 5698 break; 5699 } 5700 } 5701 cea_db_iter_end(&iter); 5702 5703 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5704 5705 return count; 5706 } 5707 5708 /** 5709 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5710 * @edid: EDID to parse 5711 * @sadb: pointer to the speaker block 5712 * 5713 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5714 * 5715 * Note: The returned pointer needs to be freed using kfree(). 5716 * 5717 * Return: The number of found Speaker Allocation Blocks or negative number on 5718 * error. 5719 */ 5720 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5721 { 5722 struct drm_edid drm_edid; 5723 5724 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5725 sadb); 5726 } 5727 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5728 5729 /** 5730 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5731 * @connector: connector associated with the HDMI/DP sink 5732 * @mode: the display mode 5733 * 5734 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5735 * the sink doesn't support audio or video. 5736 */ 5737 int drm_av_sync_delay(struct drm_connector *connector, 5738 const struct drm_display_mode *mode) 5739 { 5740 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5741 int a, v; 5742 5743 if (!connector->latency_present[0]) 5744 return 0; 5745 if (!connector->latency_present[1]) 5746 i = 0; 5747 5748 a = connector->audio_latency[i]; 5749 v = connector->video_latency[i]; 5750 5751 /* 5752 * HDMI/DP sink doesn't support audio or video? 5753 */ 5754 if (a == 255 || v == 255) 5755 return 0; 5756 5757 /* 5758 * Convert raw EDID values to millisecond. 5759 * Treat unknown latency as 0ms. 5760 */ 5761 if (a) 5762 a = min(2 * (a - 1), 500); 5763 if (v) 5764 v = min(2 * (v - 1), 500); 5765 5766 return max(v - a, 0); 5767 } 5768 EXPORT_SYMBOL(drm_av_sync_delay); 5769 5770 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5771 { 5772 const struct cea_db *db; 5773 struct cea_db_iter iter; 5774 bool hdmi = false; 5775 5776 /* 5777 * Because HDMI identifier is in Vendor Specific Block, 5778 * search it from all data blocks of CEA extension. 5779 */ 5780 cea_db_iter_edid_begin(drm_edid, &iter); 5781 cea_db_iter_for_each(db, &iter) { 5782 if (cea_db_is_hdmi_vsdb(db)) { 5783 hdmi = true; 5784 break; 5785 } 5786 } 5787 cea_db_iter_end(&iter); 5788 5789 return hdmi; 5790 } 5791 5792 /** 5793 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5794 * @edid: monitor EDID information 5795 * 5796 * Parse the CEA extension according to CEA-861-B. 5797 * 5798 * Drivers that have added the modes parsed from EDID to drm_display_info 5799 * should use &drm_display_info.is_hdmi instead of calling this function. 5800 * 5801 * Return: True if the monitor is HDMI, false if not or unknown. 5802 */ 5803 bool drm_detect_hdmi_monitor(const struct edid *edid) 5804 { 5805 struct drm_edid drm_edid; 5806 5807 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5808 } 5809 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5810 5811 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5812 { 5813 struct drm_edid_iter edid_iter; 5814 const struct cea_db *db; 5815 struct cea_db_iter iter; 5816 const u8 *edid_ext; 5817 bool has_audio = false; 5818 5819 drm_edid_iter_begin(drm_edid, &edid_iter); 5820 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5821 if (edid_ext[0] == CEA_EXT) { 5822 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5823 if (has_audio) 5824 break; 5825 } 5826 } 5827 drm_edid_iter_end(&edid_iter); 5828 5829 if (has_audio) { 5830 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5831 goto end; 5832 } 5833 5834 cea_db_iter_edid_begin(drm_edid, &iter); 5835 cea_db_iter_for_each(db, &iter) { 5836 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5837 const u8 *data = cea_db_data(db); 5838 int i; 5839 5840 for (i = 0; i < cea_db_payload_len(db); i += 3) 5841 DRM_DEBUG_KMS("CEA audio format %d\n", 5842 (data[i] >> 3) & 0xf); 5843 has_audio = true; 5844 break; 5845 } 5846 } 5847 cea_db_iter_end(&iter); 5848 5849 end: 5850 return has_audio; 5851 } 5852 5853 /** 5854 * drm_detect_monitor_audio - check monitor audio capability 5855 * @edid: EDID block to scan 5856 * 5857 * Monitor should have CEA extension block. 5858 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5859 * audio' only. If there is any audio extension block and supported 5860 * audio format, assume at least 'basic audio' support, even if 'basic 5861 * audio' is not defined in EDID. 5862 * 5863 * Return: True if the monitor supports audio, false otherwise. 5864 */ 5865 bool drm_detect_monitor_audio(const struct edid *edid) 5866 { 5867 struct drm_edid drm_edid; 5868 5869 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5870 } 5871 EXPORT_SYMBOL(drm_detect_monitor_audio); 5872 5873 5874 /** 5875 * drm_default_rgb_quant_range - default RGB quantization range 5876 * @mode: display mode 5877 * 5878 * Determine the default RGB quantization range for the mode, 5879 * as specified in CEA-861. 5880 * 5881 * Return: The default RGB quantization range for the mode 5882 */ 5883 enum hdmi_quantization_range 5884 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 5885 { 5886 /* All CEA modes other than VIC 1 use limited quantization range. */ 5887 return drm_match_cea_mode(mode) > 1 ? 5888 HDMI_QUANTIZATION_RANGE_LIMITED : 5889 HDMI_QUANTIZATION_RANGE_FULL; 5890 } 5891 EXPORT_SYMBOL(drm_default_rgb_quant_range); 5892 5893 /* CTA-861 Video Data Block (CTA VDB) */ 5894 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 5895 { 5896 struct drm_display_info *info = &connector->display_info; 5897 int i, vic_index, len = cea_db_payload_len(db); 5898 const u8 *svds = cea_db_data(db); 5899 u8 *vics; 5900 5901 if (!len) 5902 return; 5903 5904 /* Gracefully handle multiple VDBs, however unlikely that is */ 5905 #ifdef __linux__ 5906 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 5907 if (!vics) 5908 return; 5909 #else 5910 vics = kmalloc(info->vics_len + len, GFP_KERNEL); 5911 if (!vics) 5912 return; 5913 memcpy(vics, info->vics, info->vics_len); 5914 kfree(info->vics); 5915 #endif 5916 5917 vic_index = info->vics_len; 5918 info->vics_len += len; 5919 info->vics = vics; 5920 5921 for (i = 0; i < len; i++) { 5922 u8 vic = svd_to_vic(svds[i]); 5923 5924 if (!drm_valid_cea_vic(vic)) 5925 vic = 0; 5926 5927 info->vics[vic_index++] = vic; 5928 } 5929 } 5930 5931 /* 5932 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 5933 * 5934 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 5935 * using the VICs themselves. 5936 */ 5937 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 5938 { 5939 struct drm_display_info *info = &connector->display_info; 5940 struct drm_hdmi_info *hdmi = &info->hdmi; 5941 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 5942 5943 for (i = 0; i < len; i++) { 5944 u8 vic = info->vics[i]; 5945 5946 if (vic && y420cmdb_map & BIT_ULL(i)) 5947 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 5948 } 5949 } 5950 5951 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 5952 { 5953 const struct drm_display_info *info = &connector->display_info; 5954 int i; 5955 5956 if (!vic || !info->vics) 5957 return false; 5958 5959 for (i = 0; i < info->vics_len; i++) { 5960 if (info->vics[i] == vic) 5961 return true; 5962 } 5963 5964 return false; 5965 } 5966 5967 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 5968 static void parse_cta_y420vdb(struct drm_connector *connector, 5969 const struct cea_db *db) 5970 { 5971 struct drm_display_info *info = &connector->display_info; 5972 struct drm_hdmi_info *hdmi = &info->hdmi; 5973 const u8 *svds = cea_db_data(db) + 1; 5974 int i; 5975 5976 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 5977 u8 vic = svd_to_vic(svds[i]); 5978 5979 if (!drm_valid_cea_vic(vic)) 5980 continue; 5981 5982 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 5983 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5984 } 5985 } 5986 5987 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 5988 { 5989 struct drm_display_info *info = &connector->display_info; 5990 5991 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 5992 connector->base.id, connector->name, db[2]); 5993 5994 if (db[2] & EDID_CEA_VCDB_QS) 5995 info->rgb_quant_range_selectable = true; 5996 } 5997 5998 static 5999 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 6000 { 6001 switch (max_frl_rate) { 6002 case 1: 6003 *max_lanes = 3; 6004 *max_rate_per_lane = 3; 6005 break; 6006 case 2: 6007 *max_lanes = 3; 6008 *max_rate_per_lane = 6; 6009 break; 6010 case 3: 6011 *max_lanes = 4; 6012 *max_rate_per_lane = 6; 6013 break; 6014 case 4: 6015 *max_lanes = 4; 6016 *max_rate_per_lane = 8; 6017 break; 6018 case 5: 6019 *max_lanes = 4; 6020 *max_rate_per_lane = 10; 6021 break; 6022 case 6: 6023 *max_lanes = 4; 6024 *max_rate_per_lane = 12; 6025 break; 6026 case 0: 6027 default: 6028 *max_lanes = 0; 6029 *max_rate_per_lane = 0; 6030 } 6031 } 6032 6033 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 6034 const u8 *db) 6035 { 6036 u8 dc_mask; 6037 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 6038 6039 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 6040 hdmi->y420_dc_modes = dc_mask; 6041 } 6042 6043 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6044 const u8 *hf_scds) 6045 { 6046 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6047 6048 if (!hdmi_dsc->v_1p2) 6049 return; 6050 6051 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6052 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6053 6054 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6055 hdmi_dsc->bpc_supported = 16; 6056 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6057 hdmi_dsc->bpc_supported = 12; 6058 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6059 hdmi_dsc->bpc_supported = 10; 6060 else 6061 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6062 hdmi_dsc->bpc_supported = 8; 6063 6064 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6065 u8 dsc_max_slices; 6066 u8 dsc_max_frl_rate; 6067 6068 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6069 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6070 &hdmi_dsc->max_frl_rate_per_lane); 6071 6072 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6073 6074 switch (dsc_max_slices) { 6075 case 1: 6076 hdmi_dsc->max_slices = 1; 6077 hdmi_dsc->clk_per_slice = 340; 6078 break; 6079 case 2: 6080 hdmi_dsc->max_slices = 2; 6081 hdmi_dsc->clk_per_slice = 340; 6082 break; 6083 case 3: 6084 hdmi_dsc->max_slices = 4; 6085 hdmi_dsc->clk_per_slice = 340; 6086 break; 6087 case 4: 6088 hdmi_dsc->max_slices = 8; 6089 hdmi_dsc->clk_per_slice = 340; 6090 break; 6091 case 5: 6092 hdmi_dsc->max_slices = 8; 6093 hdmi_dsc->clk_per_slice = 400; 6094 break; 6095 case 6: 6096 hdmi_dsc->max_slices = 12; 6097 hdmi_dsc->clk_per_slice = 400; 6098 break; 6099 case 7: 6100 hdmi_dsc->max_slices = 16; 6101 hdmi_dsc->clk_per_slice = 400; 6102 break; 6103 case 0: 6104 default: 6105 hdmi_dsc->max_slices = 0; 6106 hdmi_dsc->clk_per_slice = 0; 6107 } 6108 } 6109 6110 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6111 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6112 } 6113 6114 /* Sink Capability Data Structure */ 6115 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6116 const u8 *hf_scds) 6117 { 6118 struct drm_display_info *info = &connector->display_info; 6119 struct drm_hdmi_info *hdmi = &info->hdmi; 6120 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6121 int max_tmds_clock = 0; 6122 u8 max_frl_rate = 0; 6123 bool dsc_support = false; 6124 6125 info->has_hdmi_infoframe = true; 6126 6127 if (hf_scds[6] & 0x80) { 6128 hdmi->scdc.supported = true; 6129 if (hf_scds[6] & 0x40) 6130 hdmi->scdc.read_request = true; 6131 } 6132 6133 /* 6134 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6135 * And as per the spec, three factors confirm this: 6136 * * Availability of a HF-VSDB block in EDID (check) 6137 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6138 * * SCDC support available (let's check) 6139 * Lets check it out. 6140 */ 6141 6142 if (hf_scds[5]) { 6143 struct drm_scdc *scdc = &hdmi->scdc; 6144 6145 /* max clock is 5000 KHz times block value */ 6146 max_tmds_clock = hf_scds[5] * 5000; 6147 6148 if (max_tmds_clock > 340000) { 6149 info->max_tmds_clock = max_tmds_clock; 6150 } 6151 6152 if (scdc->supported) { 6153 scdc->scrambling.supported = true; 6154 6155 /* Few sinks support scrambling for clocks < 340M */ 6156 if ((hf_scds[6] & 0x8)) 6157 scdc->scrambling.low_rates = true; 6158 } 6159 } 6160 6161 if (hf_scds[7]) { 6162 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6163 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6164 &hdmi->max_frl_rate_per_lane); 6165 } 6166 6167 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6168 6169 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6170 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6171 dsc_support = true; 6172 } 6173 6174 drm_dbg_kms(connector->dev, 6175 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6176 connector->base.id, connector->name, 6177 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6178 } 6179 6180 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6181 const u8 *hdmi) 6182 { 6183 struct drm_display_info *info = &connector->display_info; 6184 unsigned int dc_bpc = 0; 6185 6186 /* HDMI supports at least 8 bpc */ 6187 info->bpc = 8; 6188 6189 if (cea_db_payload_len(hdmi) < 6) 6190 return; 6191 6192 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6193 dc_bpc = 10; 6194 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6195 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6196 connector->base.id, connector->name); 6197 } 6198 6199 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6200 dc_bpc = 12; 6201 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6202 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6203 connector->base.id, connector->name); 6204 } 6205 6206 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6207 dc_bpc = 16; 6208 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6209 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6210 connector->base.id, connector->name); 6211 } 6212 6213 if (dc_bpc == 0) { 6214 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6215 connector->base.id, connector->name); 6216 return; 6217 } 6218 6219 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6220 connector->base.id, connector->name, dc_bpc); 6221 info->bpc = dc_bpc; 6222 6223 /* YCRCB444 is optional according to spec. */ 6224 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6225 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6226 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6227 connector->base.id, connector->name); 6228 } 6229 6230 /* 6231 * Spec says that if any deep color mode is supported at all, 6232 * then deep color 36 bit must be supported. 6233 */ 6234 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6235 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6236 connector->base.id, connector->name); 6237 } 6238 } 6239 6240 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6241 static void 6242 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6243 { 6244 struct drm_display_info *info = &connector->display_info; 6245 u8 len = cea_db_payload_len(db); 6246 6247 info->is_hdmi = true; 6248 6249 if (len >= 6) 6250 info->dvi_dual = db[6] & 1; 6251 if (len >= 7) 6252 info->max_tmds_clock = db[7] * 5000; 6253 6254 /* 6255 * Try to infer whether the sink supports HDMI infoframes. 6256 * 6257 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6258 * supports infoframes if HDMI_Video_present is set. 6259 */ 6260 if (len >= 8 && db[8] & BIT(5)) 6261 info->has_hdmi_infoframe = true; 6262 6263 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6264 connector->base.id, connector->name, 6265 info->dvi_dual, info->max_tmds_clock); 6266 6267 drm_parse_hdmi_deep_color_info(connector, db); 6268 } 6269 6270 /* 6271 * See EDID extension for head-mounted and specialized monitors, specified at: 6272 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6273 */ 6274 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6275 const u8 *db) 6276 { 6277 struct drm_display_info *info = &connector->display_info; 6278 u8 version = db[4]; 6279 bool desktop_usage = db[5] & BIT(6); 6280 6281 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6282 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6283 info->non_desktop = true; 6284 6285 drm_dbg_kms(connector->dev, 6286 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6287 connector->base.id, connector->name, version, db[5]); 6288 } 6289 6290 static void drm_parse_cea_ext(struct drm_connector *connector, 6291 const struct drm_edid *drm_edid) 6292 { 6293 struct drm_display_info *info = &connector->display_info; 6294 struct drm_edid_iter edid_iter; 6295 const struct cea_db *db; 6296 struct cea_db_iter iter; 6297 const u8 *edid_ext; 6298 u64 y420cmdb_map = 0; 6299 6300 drm_edid_iter_begin(drm_edid, &edid_iter); 6301 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6302 if (edid_ext[0] != CEA_EXT) 6303 continue; 6304 6305 if (!info->cea_rev) 6306 info->cea_rev = edid_ext[1]; 6307 6308 if (info->cea_rev != edid_ext[1]) 6309 drm_dbg_kms(connector->dev, 6310 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6311 connector->base.id, connector->name, 6312 info->cea_rev, edid_ext[1]); 6313 6314 /* The existence of a CTA extension should imply RGB support */ 6315 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6316 if (edid_ext[3] & EDID_CEA_YCRCB444) 6317 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6318 if (edid_ext[3] & EDID_CEA_YCRCB422) 6319 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6320 if (edid_ext[3] & EDID_BASIC_AUDIO) 6321 info->has_audio = true; 6322 6323 } 6324 drm_edid_iter_end(&edid_iter); 6325 6326 cea_db_iter_edid_begin(drm_edid, &iter); 6327 cea_db_iter_for_each(db, &iter) { 6328 /* FIXME: convert parsers to use struct cea_db */ 6329 const u8 *data = (const u8 *)db; 6330 6331 if (cea_db_is_hdmi_vsdb(db)) 6332 drm_parse_hdmi_vsdb_video(connector, data); 6333 else if (cea_db_is_hdmi_forum_vsdb(db) || 6334 cea_db_is_hdmi_forum_scdb(db)) 6335 drm_parse_hdmi_forum_scds(connector, data); 6336 else if (cea_db_is_microsoft_vsdb(db)) 6337 drm_parse_microsoft_vsdb(connector, data); 6338 else if (cea_db_is_y420cmdb(db)) 6339 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6340 else if (cea_db_is_y420vdb(db)) 6341 parse_cta_y420vdb(connector, db); 6342 else if (cea_db_is_vcdb(db)) 6343 drm_parse_vcdb(connector, data); 6344 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6345 drm_parse_hdr_metadata_block(connector, data); 6346 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6347 parse_cta_vdb(connector, db); 6348 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6349 info->has_audio = true; 6350 } 6351 cea_db_iter_end(&iter); 6352 6353 if (y420cmdb_map) 6354 update_cta_y420cmdb(connector, y420cmdb_map); 6355 } 6356 6357 static 6358 void get_monitor_range(const struct detailed_timing *timing, void *c) 6359 { 6360 struct detailed_mode_closure *closure = c; 6361 struct drm_display_info *info = &closure->connector->display_info; 6362 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6363 const struct detailed_non_pixel *data = &timing->data.other_data; 6364 const struct detailed_data_monitor_range *range = &data->data.range; 6365 const struct edid *edid = closure->drm_edid->edid; 6366 6367 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6368 return; 6369 6370 /* 6371 * These limits are used to determine the VRR refresh 6372 * rate range. Only the "range limits only" variant 6373 * of the range descriptor seems to guarantee that 6374 * any and all timings are accepted by the sink, as 6375 * opposed to just timings conforming to the indicated 6376 * formula (GTF/GTF2/CVT). Thus other variants of the 6377 * range descriptor are not accepted here. 6378 */ 6379 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6380 return; 6381 6382 monitor_range->min_vfreq = range->min_vfreq; 6383 monitor_range->max_vfreq = range->max_vfreq; 6384 6385 if (edid->revision >= 4) { 6386 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6387 monitor_range->min_vfreq += 255; 6388 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6389 monitor_range->max_vfreq += 255; 6390 } 6391 } 6392 6393 static void drm_get_monitor_range(struct drm_connector *connector, 6394 const struct drm_edid *drm_edid) 6395 { 6396 const struct drm_display_info *info = &connector->display_info; 6397 struct detailed_mode_closure closure = { 6398 .connector = connector, 6399 .drm_edid = drm_edid, 6400 }; 6401 6402 if (drm_edid->edid->revision < 4) 6403 return; 6404 6405 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6406 return; 6407 6408 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6409 6410 drm_dbg_kms(connector->dev, 6411 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6412 connector->base.id, connector->name, 6413 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6414 } 6415 6416 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6417 const struct displayid_block *block) 6418 { 6419 struct displayid_vesa_vendor_specific_block *vesa = 6420 (struct displayid_vesa_vendor_specific_block *)block; 6421 struct drm_display_info *info = &connector->display_info; 6422 6423 if (block->num_bytes < 3) { 6424 drm_dbg_kms(connector->dev, 6425 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6426 connector->base.id, connector->name, block->num_bytes); 6427 return; 6428 } 6429 6430 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6431 return; 6432 6433 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6434 drm_dbg_kms(connector->dev, 6435 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6436 connector->base.id, connector->name); 6437 return; 6438 } 6439 6440 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6441 default: 6442 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6443 connector->base.id, connector->name); 6444 fallthrough; 6445 case 0: 6446 info->mso_stream_count = 0; 6447 break; 6448 case 1: 6449 info->mso_stream_count = 2; /* 2 or 4 links */ 6450 break; 6451 case 2: 6452 info->mso_stream_count = 4; /* 4 links */ 6453 break; 6454 } 6455 6456 if (!info->mso_stream_count) { 6457 info->mso_pixel_overlap = 0; 6458 return; 6459 } 6460 6461 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6462 if (info->mso_pixel_overlap > 8) { 6463 drm_dbg_kms(connector->dev, 6464 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6465 connector->base.id, connector->name, 6466 info->mso_pixel_overlap); 6467 info->mso_pixel_overlap = 8; 6468 } 6469 6470 drm_dbg_kms(connector->dev, 6471 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6472 connector->base.id, connector->name, 6473 info->mso_stream_count, info->mso_pixel_overlap); 6474 } 6475 6476 static void drm_update_mso(struct drm_connector *connector, 6477 const struct drm_edid *drm_edid) 6478 { 6479 const struct displayid_block *block; 6480 struct displayid_iter iter; 6481 6482 displayid_iter_edid_begin(drm_edid, &iter); 6483 displayid_iter_for_each(block, &iter) { 6484 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6485 drm_parse_vesa_mso_data(connector, block); 6486 } 6487 displayid_iter_end(&iter); 6488 } 6489 6490 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6491 * all of the values which would have been set from EDID 6492 */ 6493 static void drm_reset_display_info(struct drm_connector *connector) 6494 { 6495 struct drm_display_info *info = &connector->display_info; 6496 6497 info->width_mm = 0; 6498 info->height_mm = 0; 6499 6500 info->bpc = 0; 6501 info->color_formats = 0; 6502 info->cea_rev = 0; 6503 info->max_tmds_clock = 0; 6504 info->dvi_dual = false; 6505 info->is_hdmi = false; 6506 info->has_audio = false; 6507 info->has_hdmi_infoframe = false; 6508 info->rgb_quant_range_selectable = false; 6509 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6510 6511 info->edid_hdmi_rgb444_dc_modes = 0; 6512 info->edid_hdmi_ycbcr444_dc_modes = 0; 6513 6514 info->non_desktop = 0; 6515 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6516 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6517 6518 info->mso_stream_count = 0; 6519 info->mso_pixel_overlap = 0; 6520 info->max_dsc_bpp = 0; 6521 6522 kfree(info->vics); 6523 info->vics = NULL; 6524 info->vics_len = 0; 6525 6526 info->quirks = 0; 6527 } 6528 6529 static void update_displayid_info(struct drm_connector *connector, 6530 const struct drm_edid *drm_edid) 6531 { 6532 struct drm_display_info *info = &connector->display_info; 6533 const struct displayid_block *block; 6534 struct displayid_iter iter; 6535 6536 displayid_iter_edid_begin(drm_edid, &iter); 6537 displayid_iter_for_each(block, &iter) { 6538 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6539 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6540 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6541 info->non_desktop = true; 6542 6543 /* 6544 * We're only interested in the base section here, no need to 6545 * iterate further. 6546 */ 6547 break; 6548 } 6549 displayid_iter_end(&iter); 6550 } 6551 6552 static void update_display_info(struct drm_connector *connector, 6553 const struct drm_edid *drm_edid) 6554 { 6555 struct drm_display_info *info = &connector->display_info; 6556 const struct edid *edid; 6557 6558 drm_reset_display_info(connector); 6559 clear_eld(connector); 6560 6561 if (!drm_edid) 6562 return; 6563 6564 edid = drm_edid->edid; 6565 6566 info->quirks = edid_get_quirks(drm_edid); 6567 6568 info->width_mm = edid->width_cm * 10; 6569 info->height_mm = edid->height_cm * 10; 6570 6571 drm_get_monitor_range(connector, drm_edid); 6572 6573 if (edid->revision < 3) 6574 goto out; 6575 6576 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 6577 goto out; 6578 6579 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6580 drm_parse_cea_ext(connector, drm_edid); 6581 6582 update_displayid_info(connector, drm_edid); 6583 6584 /* 6585 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6586 * 6587 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6588 * tells us to assume 8 bpc color depth if the EDID doesn't have 6589 * extensions which tell otherwise. 6590 */ 6591 if (info->bpc == 0 && edid->revision == 3 && 6592 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6593 info->bpc = 8; 6594 drm_dbg_kms(connector->dev, 6595 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6596 connector->base.id, connector->name, info->bpc); 6597 } 6598 6599 /* Only defined for 1.4 with digital displays */ 6600 if (edid->revision < 4) 6601 goto out; 6602 6603 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6604 case DRM_EDID_DIGITAL_DEPTH_6: 6605 info->bpc = 6; 6606 break; 6607 case DRM_EDID_DIGITAL_DEPTH_8: 6608 info->bpc = 8; 6609 break; 6610 case DRM_EDID_DIGITAL_DEPTH_10: 6611 info->bpc = 10; 6612 break; 6613 case DRM_EDID_DIGITAL_DEPTH_12: 6614 info->bpc = 12; 6615 break; 6616 case DRM_EDID_DIGITAL_DEPTH_14: 6617 info->bpc = 14; 6618 break; 6619 case DRM_EDID_DIGITAL_DEPTH_16: 6620 info->bpc = 16; 6621 break; 6622 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6623 default: 6624 info->bpc = 0; 6625 break; 6626 } 6627 6628 drm_dbg_kms(connector->dev, 6629 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6630 connector->base.id, connector->name, info->bpc); 6631 6632 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6633 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6634 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6635 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6636 6637 drm_update_mso(connector, drm_edid); 6638 6639 out: 6640 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6641 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6642 connector->base.id, connector->name, 6643 info->non_desktop ? " (redundant quirk)" : ""); 6644 info->non_desktop = true; 6645 } 6646 6647 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6648 info->max_dsc_bpp = 15; 6649 6650 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6651 info->bpc = 6; 6652 6653 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6654 info->bpc = 8; 6655 6656 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6657 info->bpc = 10; 6658 6659 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6660 info->bpc = 12; 6661 6662 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6663 drm_edid_to_eld(connector, drm_edid); 6664 } 6665 6666 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6667 struct displayid_detailed_timings_1 *timings, 6668 bool type_7) 6669 { 6670 struct drm_display_mode *mode; 6671 unsigned pixel_clock = (timings->pixel_clock[0] | 6672 (timings->pixel_clock[1] << 8) | 6673 (timings->pixel_clock[2] << 16)) + 1; 6674 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6675 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6676 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6677 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6678 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6679 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6680 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6681 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6682 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6683 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6684 6685 mode = drm_mode_create(dev); 6686 if (!mode) 6687 return NULL; 6688 6689 /* resolution is kHz for type VII, and 10 kHz for type I */ 6690 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6691 mode->hdisplay = hactive; 6692 mode->hsync_start = mode->hdisplay + hsync; 6693 mode->hsync_end = mode->hsync_start + hsync_width; 6694 mode->htotal = mode->hdisplay + hblank; 6695 6696 mode->vdisplay = vactive; 6697 mode->vsync_start = mode->vdisplay + vsync; 6698 mode->vsync_end = mode->vsync_start + vsync_width; 6699 mode->vtotal = mode->vdisplay + vblank; 6700 6701 mode->flags = 0; 6702 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6703 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6704 mode->type = DRM_MODE_TYPE_DRIVER; 6705 6706 if (timings->flags & 0x80) 6707 mode->type |= DRM_MODE_TYPE_PREFERRED; 6708 drm_mode_set_name(mode); 6709 6710 return mode; 6711 } 6712 6713 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6714 const struct displayid_block *block) 6715 { 6716 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6717 int i; 6718 int num_timings; 6719 struct drm_display_mode *newmode; 6720 int num_modes = 0; 6721 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6722 /* blocks must be multiple of 20 bytes length */ 6723 if (block->num_bytes % 20) 6724 return 0; 6725 6726 num_timings = block->num_bytes / 20; 6727 for (i = 0; i < num_timings; i++) { 6728 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6729 6730 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6731 if (!newmode) 6732 continue; 6733 6734 drm_mode_probed_add(connector, newmode); 6735 num_modes++; 6736 } 6737 return num_modes; 6738 } 6739 6740 static int add_displayid_detailed_modes(struct drm_connector *connector, 6741 const struct drm_edid *drm_edid) 6742 { 6743 const struct displayid_block *block; 6744 struct displayid_iter iter; 6745 int num_modes = 0; 6746 6747 displayid_iter_edid_begin(drm_edid, &iter); 6748 displayid_iter_for_each(block, &iter) { 6749 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6750 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6751 num_modes += add_displayid_detailed_1_modes(connector, block); 6752 } 6753 displayid_iter_end(&iter); 6754 6755 return num_modes; 6756 } 6757 6758 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6759 const struct drm_edid *drm_edid) 6760 { 6761 const struct drm_display_info *info = &connector->display_info; 6762 int num_modes = 0; 6763 6764 if (!drm_edid) 6765 return 0; 6766 6767 /* 6768 * EDID spec says modes should be preferred in this order: 6769 * - preferred detailed mode 6770 * - other detailed modes from base block 6771 * - detailed modes from extension blocks 6772 * - CVT 3-byte code modes 6773 * - standard timing codes 6774 * - established timing codes 6775 * - modes inferred from GTF or CVT range information 6776 * 6777 * We get this pretty much right. 6778 * 6779 * XXX order for additional mode types in extension blocks? 6780 */ 6781 num_modes += add_detailed_modes(connector, drm_edid); 6782 num_modes += add_cvt_modes(connector, drm_edid); 6783 num_modes += add_standard_modes(connector, drm_edid); 6784 num_modes += add_established_modes(connector, drm_edid); 6785 num_modes += add_cea_modes(connector, drm_edid); 6786 num_modes += add_alternate_cea_modes(connector, drm_edid); 6787 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6788 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6789 num_modes += add_inferred_modes(connector, drm_edid); 6790 6791 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6792 edid_fixup_preferred(connector); 6793 6794 return num_modes; 6795 } 6796 6797 static void _drm_update_tile_info(struct drm_connector *connector, 6798 const struct drm_edid *drm_edid); 6799 6800 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6801 const struct drm_edid *drm_edid) 6802 { 6803 struct drm_device *dev = connector->dev; 6804 int ret; 6805 6806 if (connector->edid_blob_ptr) { 6807 const struct edid *old_edid = connector->edid_blob_ptr->data; 6808 6809 if (old_edid) { 6810 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) { 6811 connector->epoch_counter++; 6812 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6813 connector->base.id, connector->name, 6814 connector->epoch_counter); 6815 } 6816 } 6817 } 6818 6819 ret = drm_property_replace_global_blob(dev, 6820 &connector->edid_blob_ptr, 6821 drm_edid ? drm_edid->size : 0, 6822 drm_edid ? drm_edid->edid : NULL, 6823 &connector->base, 6824 dev->mode_config.edid_property); 6825 if (ret) { 6826 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6827 connector->base.id, connector->name, ret); 6828 goto out; 6829 } 6830 6831 ret = drm_object_property_set_value(&connector->base, 6832 dev->mode_config.non_desktop_property, 6833 connector->display_info.non_desktop); 6834 if (ret) { 6835 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6836 connector->base.id, connector->name, ret); 6837 goto out; 6838 } 6839 6840 ret = drm_connector_set_tile_property(connector); 6841 if (ret) { 6842 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6843 connector->base.id, connector->name, ret); 6844 goto out; 6845 } 6846 6847 out: 6848 return ret; 6849 } 6850 6851 /** 6852 * drm_edid_connector_update - Update connector information from EDID 6853 * @connector: Connector 6854 * @drm_edid: EDID 6855 * 6856 * Update the connector display info, ELD, HDR metadata, relevant properties, 6857 * etc. from the passed in EDID. 6858 * 6859 * If EDID is NULL, reset the information. 6860 * 6861 * Must be called before calling drm_edid_connector_add_modes(). 6862 * 6863 * Return: 0 on success, negative error on errors. 6864 */ 6865 int drm_edid_connector_update(struct drm_connector *connector, 6866 const struct drm_edid *drm_edid) 6867 { 6868 update_display_info(connector, drm_edid); 6869 6870 _drm_update_tile_info(connector, drm_edid); 6871 6872 return _drm_edid_connector_property_update(connector, drm_edid); 6873 } 6874 EXPORT_SYMBOL(drm_edid_connector_update); 6875 6876 /** 6877 * drm_edid_connector_add_modes - Update probed modes from the EDID property 6878 * @connector: Connector 6879 * 6880 * Add the modes from the previously updated EDID property to the connector 6881 * probed modes list. 6882 * 6883 * drm_edid_connector_update() must have been called before this to update the 6884 * EDID property. 6885 * 6886 * Return: The number of modes added, or 0 if we couldn't find any. 6887 */ 6888 int drm_edid_connector_add_modes(struct drm_connector *connector) 6889 { 6890 const struct drm_edid *drm_edid = NULL; 6891 int count; 6892 6893 if (connector->edid_blob_ptr) 6894 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 6895 connector->edid_blob_ptr->length); 6896 6897 count = _drm_edid_connector_add_modes(connector, drm_edid); 6898 6899 drm_edid_free(drm_edid); 6900 6901 return count; 6902 } 6903 EXPORT_SYMBOL(drm_edid_connector_add_modes); 6904 6905 /** 6906 * drm_connector_update_edid_property - update the edid property of a connector 6907 * @connector: drm connector 6908 * @edid: new value of the edid property 6909 * 6910 * This function creates a new blob modeset object and assigns its id to the 6911 * connector's edid property. 6912 * Since we also parse tile information from EDID's displayID block, we also 6913 * set the connector's tile property here. See drm_connector_set_tile_property() 6914 * for more details. 6915 * 6916 * This function is deprecated. Use drm_edid_connector_update() instead. 6917 * 6918 * Returns: 6919 * Zero on success, negative errno on failure. 6920 */ 6921 int drm_connector_update_edid_property(struct drm_connector *connector, 6922 const struct edid *edid) 6923 { 6924 struct drm_edid drm_edid; 6925 6926 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 6927 } 6928 EXPORT_SYMBOL(drm_connector_update_edid_property); 6929 6930 /** 6931 * drm_add_edid_modes - add modes from EDID data, if available 6932 * @connector: connector we're probing 6933 * @edid: EDID data 6934 * 6935 * Add the specified modes to the connector's mode list. Also fills out the 6936 * &drm_display_info structure and ELD in @connector with any information which 6937 * can be derived from the edid. 6938 * 6939 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 6940 * 6941 * Return: The number of modes added or 0 if we couldn't find any. 6942 */ 6943 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 6944 { 6945 struct drm_edid _drm_edid; 6946 const struct drm_edid *drm_edid; 6947 6948 if (edid && !drm_edid_is_valid(edid)) { 6949 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 6950 connector->base.id, connector->name); 6951 edid = NULL; 6952 } 6953 6954 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 6955 6956 update_display_info(connector, drm_edid); 6957 6958 return _drm_edid_connector_add_modes(connector, drm_edid); 6959 } 6960 EXPORT_SYMBOL(drm_add_edid_modes); 6961 6962 /** 6963 * drm_add_modes_noedid - add modes for the connectors without EDID 6964 * @connector: connector we're probing 6965 * @hdisplay: the horizontal display limit 6966 * @vdisplay: the vertical display limit 6967 * 6968 * Add the specified modes to the connector's mode list. Only when the 6969 * hdisplay/vdisplay is not beyond the given limit, it will be added. 6970 * 6971 * Return: The number of modes added or 0 if we couldn't find any. 6972 */ 6973 int drm_add_modes_noedid(struct drm_connector *connector, 6974 int hdisplay, int vdisplay) 6975 { 6976 int i, count, num_modes = 0; 6977 struct drm_display_mode *mode; 6978 struct drm_device *dev = connector->dev; 6979 6980 count = ARRAY_SIZE(drm_dmt_modes); 6981 if (hdisplay < 0) 6982 hdisplay = 0; 6983 if (vdisplay < 0) 6984 vdisplay = 0; 6985 6986 for (i = 0; i < count; i++) { 6987 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 6988 6989 if (hdisplay && vdisplay) { 6990 /* 6991 * Only when two are valid, they will be used to check 6992 * whether the mode should be added to the mode list of 6993 * the connector. 6994 */ 6995 if (ptr->hdisplay > hdisplay || 6996 ptr->vdisplay > vdisplay) 6997 continue; 6998 } 6999 if (drm_mode_vrefresh(ptr) > 61) 7000 continue; 7001 mode = drm_mode_duplicate(dev, ptr); 7002 if (mode) { 7003 drm_mode_probed_add(connector, mode); 7004 num_modes++; 7005 } 7006 } 7007 return num_modes; 7008 } 7009 EXPORT_SYMBOL(drm_add_modes_noedid); 7010 7011 /** 7012 * drm_set_preferred_mode - Sets the preferred mode of a connector 7013 * @connector: connector whose mode list should be processed 7014 * @hpref: horizontal resolution of preferred mode 7015 * @vpref: vertical resolution of preferred mode 7016 * 7017 * Marks a mode as preferred if it matches the resolution specified by @hpref 7018 * and @vpref. 7019 */ 7020 void drm_set_preferred_mode(struct drm_connector *connector, 7021 int hpref, int vpref) 7022 { 7023 struct drm_display_mode *mode; 7024 7025 list_for_each_entry(mode, &connector->probed_modes, head) { 7026 if (mode->hdisplay == hpref && 7027 mode->vdisplay == vpref) 7028 mode->type |= DRM_MODE_TYPE_PREFERRED; 7029 } 7030 } 7031 EXPORT_SYMBOL(drm_set_preferred_mode); 7032 7033 static bool is_hdmi2_sink(const struct drm_connector *connector) 7034 { 7035 /* 7036 * FIXME: sil-sii8620 doesn't have a connector around when 7037 * we need one, so we have to be prepared for a NULL connector. 7038 */ 7039 if (!connector) 7040 return true; 7041 7042 return connector->display_info.hdmi.scdc.supported || 7043 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7044 } 7045 7046 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7047 const struct drm_display_mode *mode) 7048 { 7049 bool has_hdmi_infoframe = connector ? 7050 connector->display_info.has_hdmi_infoframe : false; 7051 7052 if (!has_hdmi_infoframe) 7053 return 0; 7054 7055 /* No HDMI VIC when signalling 3D video format */ 7056 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7057 return 0; 7058 7059 return drm_match_hdmi_mode(mode); 7060 } 7061 7062 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7063 const struct drm_display_mode *mode) 7064 { 7065 /* 7066 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7067 * we should send its VIC in vendor infoframes, else send the 7068 * VIC in AVI infoframes. Lets check if this mode is present in 7069 * HDMI 1.4b 4K modes 7070 */ 7071 if (drm_mode_hdmi_vic(connector, mode)) 7072 return 0; 7073 7074 return drm_match_cea_mode(mode); 7075 } 7076 7077 /* 7078 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7079 * conform to HDMI 1.4. 7080 * 7081 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7082 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7083 * 7084 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7085 * version. 7086 */ 7087 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7088 { 7089 if (!is_hdmi2_sink(connector) && vic > 64 && 7090 !cta_vdb_has_vic(connector, vic)) 7091 return 0; 7092 7093 return vic; 7094 } 7095 7096 /** 7097 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7098 * data from a DRM display mode 7099 * @frame: HDMI AVI infoframe 7100 * @connector: the connector 7101 * @mode: DRM display mode 7102 * 7103 * Return: 0 on success or a negative error code on failure. 7104 */ 7105 int 7106 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7107 const struct drm_connector *connector, 7108 const struct drm_display_mode *mode) 7109 { 7110 enum hdmi_picture_aspect picture_aspect; 7111 u8 vic, hdmi_vic; 7112 7113 if (!frame || !mode) 7114 return -EINVAL; 7115 7116 hdmi_avi_infoframe_init(frame); 7117 7118 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7119 frame->pixel_repeat = 1; 7120 7121 vic = drm_mode_cea_vic(connector, mode); 7122 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7123 7124 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7125 7126 /* 7127 * As some drivers don't support atomic, we can't use connector state. 7128 * So just initialize the frame with default values, just the same way 7129 * as it's done with other properties here. 7130 */ 7131 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7132 frame->itc = 0; 7133 7134 /* 7135 * Populate picture aspect ratio from either 7136 * user input (if specified) or from the CEA/HDMI mode lists. 7137 */ 7138 picture_aspect = mode->picture_aspect_ratio; 7139 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7140 if (vic) 7141 picture_aspect = drm_get_cea_aspect_ratio(vic); 7142 else if (hdmi_vic) 7143 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7144 } 7145 7146 /* 7147 * The infoframe can't convey anything but none, 4:3 7148 * and 16:9, so if the user has asked for anything else 7149 * we can only satisfy it by specifying the right VIC. 7150 */ 7151 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7152 if (vic) { 7153 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7154 return -EINVAL; 7155 } else if (hdmi_vic) { 7156 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7157 return -EINVAL; 7158 } else { 7159 return -EINVAL; 7160 } 7161 7162 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7163 } 7164 7165 frame->video_code = vic_for_avi_infoframe(connector, vic); 7166 frame->picture_aspect = picture_aspect; 7167 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7168 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7169 7170 return 0; 7171 } 7172 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7173 7174 /** 7175 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7176 * quantization range information 7177 * @frame: HDMI AVI infoframe 7178 * @connector: the connector 7179 * @mode: DRM display mode 7180 * @rgb_quant_range: RGB quantization range (Q) 7181 */ 7182 void 7183 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7184 const struct drm_connector *connector, 7185 const struct drm_display_mode *mode, 7186 enum hdmi_quantization_range rgb_quant_range) 7187 { 7188 const struct drm_display_info *info = &connector->display_info; 7189 7190 /* 7191 * CEA-861: 7192 * "A Source shall not send a non-zero Q value that does not correspond 7193 * to the default RGB Quantization Range for the transmitted Picture 7194 * unless the Sink indicates support for the Q bit in a Video 7195 * Capabilities Data Block." 7196 * 7197 * HDMI 2.0 recommends sending non-zero Q when it does match the 7198 * default RGB quantization range for the mode, even when QS=0. 7199 */ 7200 if (info->rgb_quant_range_selectable || 7201 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7202 frame->quantization_range = rgb_quant_range; 7203 else 7204 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7205 7206 /* 7207 * CEA-861-F: 7208 * "When transmitting any RGB colorimetry, the Source should set the 7209 * YQ-field to match the RGB Quantization Range being transmitted 7210 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7211 * set YQ=1) and the Sink shall ignore the YQ-field." 7212 * 7213 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7214 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7215 * good way to tell which version of CEA-861 the sink supports, so 7216 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7217 * on CEA-861-F. 7218 */ 7219 if (!is_hdmi2_sink(connector) || 7220 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7221 frame->ycc_quantization_range = 7222 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7223 else 7224 frame->ycc_quantization_range = 7225 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7226 } 7227 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7228 7229 static enum hdmi_3d_structure 7230 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7231 { 7232 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7233 7234 switch (layout) { 7235 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7236 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7237 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7238 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7239 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7240 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7241 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7242 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7243 case DRM_MODE_FLAG_3D_L_DEPTH: 7244 return HDMI_3D_STRUCTURE_L_DEPTH; 7245 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7246 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7247 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7248 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7249 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7250 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7251 default: 7252 return HDMI_3D_STRUCTURE_INVALID; 7253 } 7254 } 7255 7256 /** 7257 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7258 * data from a DRM display mode 7259 * @frame: HDMI vendor infoframe 7260 * @connector: the connector 7261 * @mode: DRM display mode 7262 * 7263 * Note that there's is a need to send HDMI vendor infoframes only when using a 7264 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7265 * function will return -EINVAL, error that can be safely ignored. 7266 * 7267 * Return: 0 on success or a negative error code on failure. 7268 */ 7269 int 7270 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7271 const struct drm_connector *connector, 7272 const struct drm_display_mode *mode) 7273 { 7274 /* 7275 * FIXME: sil-sii8620 doesn't have a connector around when 7276 * we need one, so we have to be prepared for a NULL connector. 7277 */ 7278 bool has_hdmi_infoframe = connector ? 7279 connector->display_info.has_hdmi_infoframe : false; 7280 int err; 7281 7282 if (!frame || !mode) 7283 return -EINVAL; 7284 7285 if (!has_hdmi_infoframe) 7286 return -EINVAL; 7287 7288 err = hdmi_vendor_infoframe_init(frame); 7289 if (err < 0) 7290 return err; 7291 7292 /* 7293 * Even if it's not absolutely necessary to send the infoframe 7294 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7295 * know that the sink can handle it. This is based on a 7296 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7297 * have trouble realizing that they should switch from 3D to 2D 7298 * mode if the source simply stops sending the infoframe when 7299 * it wants to switch from 3D to 2D. 7300 */ 7301 frame->vic = drm_mode_hdmi_vic(connector, mode); 7302 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7303 7304 return 0; 7305 } 7306 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7307 7308 static void drm_parse_tiled_block(struct drm_connector *connector, 7309 const struct displayid_block *block) 7310 { 7311 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7312 u16 w, h; 7313 u8 tile_v_loc, tile_h_loc; 7314 u8 num_v_tile, num_h_tile; 7315 struct drm_tile_group *tg; 7316 7317 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7318 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7319 7320 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7321 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7322 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7323 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7324 7325 connector->has_tile = true; 7326 if (tile->tile_cap & 0x80) 7327 connector->tile_is_single_monitor = true; 7328 7329 connector->num_h_tile = num_h_tile + 1; 7330 connector->num_v_tile = num_v_tile + 1; 7331 connector->tile_h_loc = tile_h_loc; 7332 connector->tile_v_loc = tile_v_loc; 7333 connector->tile_h_size = w + 1; 7334 connector->tile_v_size = h + 1; 7335 7336 drm_dbg_kms(connector->dev, 7337 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7338 connector->base.id, connector->name, 7339 tile->tile_cap, 7340 connector->tile_h_size, connector->tile_v_size, 7341 connector->num_h_tile, connector->num_v_tile, 7342 connector->tile_h_loc, connector->tile_v_loc, 7343 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7344 7345 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7346 if (!tg) 7347 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7348 if (!tg) 7349 return; 7350 7351 if (connector->tile_group != tg) { 7352 /* if we haven't got a pointer, 7353 take the reference, drop ref to old tile group */ 7354 if (connector->tile_group) 7355 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7356 connector->tile_group = tg; 7357 } else { 7358 /* if same tile group, then release the ref we just took. */ 7359 drm_mode_put_tile_group(connector->dev, tg); 7360 } 7361 } 7362 7363 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7364 const struct displayid_block *block) 7365 { 7366 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 && 7367 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7368 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7369 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7370 } 7371 7372 static void _drm_update_tile_info(struct drm_connector *connector, 7373 const struct drm_edid *drm_edid) 7374 { 7375 const struct displayid_block *block; 7376 struct displayid_iter iter; 7377 7378 connector->has_tile = false; 7379 7380 displayid_iter_edid_begin(drm_edid, &iter); 7381 displayid_iter_for_each(block, &iter) { 7382 if (displayid_is_tiled_block(&iter, block)) 7383 drm_parse_tiled_block(connector, block); 7384 } 7385 displayid_iter_end(&iter); 7386 7387 if (!connector->has_tile && connector->tile_group) { 7388 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7389 connector->tile_group = NULL; 7390 } 7391 } 7392