1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/kernel.h> 34 #include <linux/module.h> 35 #include <linux/slab.h> 36 #include <linux/vga_switcheroo.h> 37 38 #include <drm/drm_displayid.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_encoder.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_scdc_helper.h> 44 45 #include "drm_crtc_internal.h" 46 47 #define version_greater(edid, maj, min) \ 48 (((edid)->version > (maj)) || \ 49 ((edid)->version == (maj) && (edid)->revision > (min))) 50 51 #define EDID_EST_TIMINGS 16 52 #define EDID_STD_TIMINGS 8 53 #define EDID_DETAILED_TIMINGS 4 54 55 /* 56 * EDID blocks out in the wild have a variety of bugs, try to collect 57 * them here (note that userspace may work around broken monitors first, 58 * but fixes should make their way here so that the kernel "just works" 59 * on as many displays as possible). 60 */ 61 62 /* First detailed mode wrong, use largest 60Hz mode */ 63 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 64 /* Reported 135MHz pixel clock is too high, needs adjustment */ 65 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 66 /* Prefer the largest mode at 75 Hz */ 67 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 68 /* Detail timing is in cm not mm */ 69 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 70 /* Detailed timing descriptors have bogus size values, so just take the 71 * maximum size and use that. 72 */ 73 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 /* Force 10bpc */ 85 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 86 /* Non desktop display (i.e. HMD) */ 87 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 88 89 struct detailed_mode_closure { 90 struct drm_connector *connector; 91 struct edid *edid; 92 bool preferred; 93 u32 quirks; 94 int modes; 95 }; 96 97 #define LEVEL_DMT 0 98 #define LEVEL_GTF 1 99 #define LEVEL_GTF2 2 100 #define LEVEL_CVT 3 101 102 static const struct edid_quirk { 103 char vendor[4]; 104 int product_id; 105 u32 quirks; 106 } edid_quirk_list[] = { 107 /* Acer AL1706 */ 108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 109 /* Acer F51 */ 110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 111 112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 114 115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 117 118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 120 121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 123 124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 126 127 /* Belinea 10 15 55 */ 128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 130 131 /* Envision Peripherals, Inc. EN-7100e */ 132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 133 /* Envision EN2028 */ 134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 135 136 /* Funai Electronics PM36B */ 137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 138 EDID_QUIRK_DETAILED_IN_CM }, 139 140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 142 143 /* LG Philips LCD LP154W01-A5 */ 144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 146 147 /* Samsung SyncMaster 205BW. Note: irony */ 148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 149 /* Samsung SyncMaster 22[5-6]BW */ 150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 152 153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 155 156 /* ViewSonic VA2026w */ 157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 158 159 /* Medion MD 30217 PG */ 160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 161 162 /* Lenovo G50 */ 163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 171 /* Valve Index Headset */ 172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 189 190 /* HTC Vive and Vive Pro VR Headsets */ 191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 193 194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP }, 199 200 /* Windows Mixed Reality Headsets */ 201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 209 210 /* Sony PlayStation VR Headset */ 211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 212 213 /* Sensics VR Headsets */ 214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 215 216 /* OSVR HDK and HDK2 VR Headsets */ 217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 218 }; 219 220 /* 221 * Autogenerated from the DMT spec. 222 * This table is copied from xfree86/modes/xf86EdidModes.c. 223 */ 224 static const struct drm_display_mode drm_dmt_modes[] = { 225 /* 0x01 - 640x350@85Hz */ 226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 227 736, 832, 0, 350, 382, 385, 445, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x02 - 640x400@85Hz */ 230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 231 736, 832, 0, 400, 401, 404, 445, 0, 232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x03 - 720x400@85Hz */ 234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 235 828, 936, 0, 400, 401, 404, 446, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x04 - 640x480@60Hz */ 238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 239 752, 800, 0, 480, 490, 492, 525, 0, 240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x05 - 640x480@72Hz */ 242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 243 704, 832, 0, 480, 489, 492, 520, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x06 - 640x480@75Hz */ 246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 247 720, 840, 0, 480, 481, 484, 500, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 0x07 - 640x480@85Hz */ 250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 251 752, 832, 0, 480, 481, 484, 509, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x08 - 800x600@56Hz */ 254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 255 896, 1024, 0, 600, 601, 603, 625, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x09 - 800x600@60Hz */ 258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 259 968, 1056, 0, 600, 601, 605, 628, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x0a - 800x600@72Hz */ 262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 263 976, 1040, 0, 600, 637, 643, 666, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x0b - 800x600@75Hz */ 266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 267 896, 1056, 0, 600, 601, 604, 625, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x0c - 800x600@85Hz */ 270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 271 896, 1048, 0, 600, 601, 604, 631, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x0d - 800x600@120Hz RB */ 274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 275 880, 960, 0, 600, 603, 607, 636, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 0x0e - 848x480@60Hz */ 278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 279 976, 1088, 0, 480, 486, 494, 517, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x0f - 1024x768@43Hz, interlace */ 282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 283 1208, 1264, 0, 768, 768, 776, 817, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 285 DRM_MODE_FLAG_INTERLACE) }, 286 /* 0x10 - 1024x768@60Hz */ 287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 288 1184, 1344, 0, 768, 771, 777, 806, 0, 289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x11 - 1024x768@70Hz */ 291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 292 1184, 1328, 0, 768, 771, 777, 806, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 294 /* 0x12 - 1024x768@75Hz */ 295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 296 1136, 1312, 0, 768, 769, 772, 800, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x13 - 1024x768@85Hz */ 299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 300 1168, 1376, 0, 768, 769, 772, 808, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x14 - 1024x768@120Hz RB */ 303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 304 1104, 1184, 0, 768, 771, 775, 813, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x15 - 1152x864@75Hz */ 307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 308 1344, 1600, 0, 864, 865, 868, 900, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x55 - 1280x720@60Hz */ 311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 312 1430, 1650, 0, 720, 725, 730, 750, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x16 - 1280x768@60Hz RB */ 315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 316 1360, 1440, 0, 768, 771, 778, 790, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x17 - 1280x768@60Hz */ 319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 320 1472, 1664, 0, 768, 771, 778, 798, 0, 321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x18 - 1280x768@75Hz */ 323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 324 1488, 1696, 0, 768, 771, 778, 805, 0, 325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x19 - 1280x768@85Hz */ 327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 328 1496, 1712, 0, 768, 771, 778, 809, 0, 329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x1a - 1280x768@120Hz RB */ 331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 332 1360, 1440, 0, 768, 771, 778, 813, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x1b - 1280x800@60Hz RB */ 335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 336 1360, 1440, 0, 800, 803, 809, 823, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 338 /* 0x1c - 1280x800@60Hz */ 339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 340 1480, 1680, 0, 800, 803, 809, 831, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x1d - 1280x800@75Hz */ 343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 344 1488, 1696, 0, 800, 803, 809, 838, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x1e - 1280x800@85Hz */ 347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 348 1496, 1712, 0, 800, 803, 809, 843, 0, 349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x1f - 1280x800@120Hz RB */ 351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 352 1360, 1440, 0, 800, 803, 809, 847, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x20 - 1280x960@60Hz */ 355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 356 1488, 1800, 0, 960, 961, 964, 1000, 0, 357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x21 - 1280x960@85Hz */ 359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 360 1504, 1728, 0, 960, 961, 964, 1011, 0, 361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x22 - 1280x960@120Hz RB */ 363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 364 1360, 1440, 0, 960, 963, 967, 1017, 0, 365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 366 /* 0x23 - 1280x1024@60Hz */ 367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 370 /* 0x24 - 1280x1024@75Hz */ 371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x25 - 1280x1024@85Hz */ 375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x26 - 1280x1024@120Hz RB */ 379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 382 /* 0x27 - 1360x768@60Hz */ 383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 384 1536, 1792, 0, 768, 771, 777, 795, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x28 - 1360x768@120Hz RB */ 387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 388 1440, 1520, 0, 768, 771, 776, 813, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x51 - 1366x768@60Hz */ 391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 392 1579, 1792, 0, 768, 771, 774, 798, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x56 - 1366x768@60Hz */ 395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 396 1436, 1500, 0, 768, 769, 772, 800, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x29 - 1400x1050@60Hz RB */ 399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x2a - 1400x1050@60Hz */ 403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x2b - 1400x1050@75Hz */ 407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x2c - 1400x1050@85Hz */ 411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x2d - 1400x1050@120Hz RB */ 415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x2e - 1440x900@60Hz RB */ 419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 420 1520, 1600, 0, 900, 903, 909, 926, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x2f - 1440x900@60Hz */ 423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 424 1672, 1904, 0, 900, 903, 909, 934, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x30 - 1440x900@75Hz */ 427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 428 1688, 1936, 0, 900, 903, 909, 942, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x31 - 1440x900@85Hz */ 431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 432 1696, 1952, 0, 900, 903, 909, 948, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x32 - 1440x900@120Hz RB */ 435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 436 1520, 1600, 0, 900, 903, 909, 953, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x53 - 1600x900@60Hz */ 439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 440 1704, 1800, 0, 900, 901, 904, 1000, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x33 - 1600x1200@60Hz */ 443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x34 - 1600x1200@65Hz */ 447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 450 /* 0x35 - 1600x1200@70Hz */ 451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x36 - 1600x1200@75Hz */ 455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x37 - 1600x1200@85Hz */ 459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x38 - 1600x1200@120Hz RB */ 463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x39 - 1680x1050@60Hz RB */ 467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x3a - 1680x1050@60Hz */ 471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x3b - 1680x1050@75Hz */ 475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x3c - 1680x1050@85Hz */ 479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x3d - 1680x1050@120Hz RB */ 483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x3e - 1792x1344@60Hz */ 487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x3f - 1792x1344@75Hz */ 491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x40 - 1792x1344@120Hz RB */ 495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x41 - 1856x1392@60Hz */ 499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x42 - 1856x1392@75Hz */ 503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 506 /* 0x43 - 1856x1392@120Hz RB */ 507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 /* 0x52 - 1920x1080@60Hz */ 511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 514 /* 0x44 - 1920x1200@60Hz RB */ 515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 518 /* 0x45 - 1920x1200@60Hz */ 519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 522 /* 0x46 - 1920x1200@75Hz */ 523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 526 /* 0x47 - 1920x1200@85Hz */ 527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 530 /* 0x48 - 1920x1200@120Hz RB */ 531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 534 /* 0x49 - 1920x1440@60Hz */ 535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 538 /* 0x4a - 1920x1440@75Hz */ 539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 542 /* 0x4b - 1920x1440@120Hz RB */ 543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 546 /* 0x54 - 2048x1152@60Hz */ 547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 550 /* 0x4c - 2560x1600@60Hz RB */ 551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 554 /* 0x4d - 2560x1600@60Hz */ 555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 558 /* 0x4e - 2560x1600@75Hz */ 559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 562 /* 0x4f - 2560x1600@85Hz */ 563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 566 /* 0x50 - 2560x1600@120Hz RB */ 567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 570 /* 0x57 - 4096x2160@60Hz RB */ 571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 574 /* 0x58 - 4096x2160@59.94Hz RB */ 575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 578 }; 579 580 /* 581 * These more or less come from the DMT spec. The 720x400 modes are 582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 585 * mode. 586 * 587 * The DMT modes have been fact-checked; the rest are mild guesses. 588 */ 589 static const struct drm_display_mode edid_est_modes[] = { 590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 591 968, 1056, 0, 600, 601, 605, 628, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 594 896, 1024, 0, 600, 601, 603, 625, 0, 595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 597 720, 840, 0, 480, 481, 484, 500, 0, 598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 600 704, 832, 0, 480, 489, 492, 520, 0, 601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 603 768, 864, 0, 480, 483, 486, 525, 0, 604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 606 752, 800, 0, 480, 490, 492, 525, 0, 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 609 846, 900, 0, 400, 421, 423, 449, 0, 610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 612 846, 900, 0, 400, 412, 414, 449, 0, 613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 618 1136, 1312, 0, 768, 769, 772, 800, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 621 1184, 1328, 0, 768, 771, 777, 806, 0, 622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 624 1184, 1344, 0, 768, 771, 777, 806, 0, 625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 627 1208, 1264, 0, 768, 768, 776, 817, 0, 628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 630 928, 1152, 0, 624, 625, 628, 667, 0, 631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 633 896, 1056, 0, 600, 601, 604, 625, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 636 976, 1040, 0, 600, 637, 643, 666, 0, 637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 639 1344, 1600, 0, 864, 865, 868, 900, 0, 640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 641 }; 642 643 struct minimode { 644 short w; 645 short h; 646 short r; 647 short rb; 648 }; 649 650 static const struct minimode est3_modes[] = { 651 /* byte 6 */ 652 { 640, 350, 85, 0 }, 653 { 640, 400, 85, 0 }, 654 { 720, 400, 85, 0 }, 655 { 640, 480, 85, 0 }, 656 { 848, 480, 60, 0 }, 657 { 800, 600, 85, 0 }, 658 { 1024, 768, 85, 0 }, 659 { 1152, 864, 75, 0 }, 660 /* byte 7 */ 661 { 1280, 768, 60, 1 }, 662 { 1280, 768, 60, 0 }, 663 { 1280, 768, 75, 0 }, 664 { 1280, 768, 85, 0 }, 665 { 1280, 960, 60, 0 }, 666 { 1280, 960, 85, 0 }, 667 { 1280, 1024, 60, 0 }, 668 { 1280, 1024, 85, 0 }, 669 /* byte 8 */ 670 { 1360, 768, 60, 0 }, 671 { 1440, 900, 60, 1 }, 672 { 1440, 900, 60, 0 }, 673 { 1440, 900, 75, 0 }, 674 { 1440, 900, 85, 0 }, 675 { 1400, 1050, 60, 1 }, 676 { 1400, 1050, 60, 0 }, 677 { 1400, 1050, 75, 0 }, 678 /* byte 9 */ 679 { 1400, 1050, 85, 0 }, 680 { 1680, 1050, 60, 1 }, 681 { 1680, 1050, 60, 0 }, 682 { 1680, 1050, 75, 0 }, 683 { 1680, 1050, 85, 0 }, 684 { 1600, 1200, 60, 0 }, 685 { 1600, 1200, 65, 0 }, 686 { 1600, 1200, 70, 0 }, 687 /* byte 10 */ 688 { 1600, 1200, 75, 0 }, 689 { 1600, 1200, 85, 0 }, 690 { 1792, 1344, 60, 0 }, 691 { 1792, 1344, 75, 0 }, 692 { 1856, 1392, 60, 0 }, 693 { 1856, 1392, 75, 0 }, 694 { 1920, 1200, 60, 1 }, 695 { 1920, 1200, 60, 0 }, 696 /* byte 11 */ 697 { 1920, 1200, 75, 0 }, 698 { 1920, 1200, 85, 0 }, 699 { 1920, 1440, 60, 0 }, 700 { 1920, 1440, 75, 0 }, 701 }; 702 703 static const struct minimode extra_modes[] = { 704 { 1024, 576, 60, 0 }, 705 { 1366, 768, 60, 0 }, 706 { 1600, 900, 60, 0 }, 707 { 1680, 945, 60, 0 }, 708 { 1920, 1080, 60, 0 }, 709 { 2048, 1152, 60, 0 }, 710 { 2048, 1536, 60, 0 }, 711 }; 712 713 /* 714 * From CEA/CTA-861 spec. 715 * 716 * Do not access directly, instead always use cea_mode_for_vic(). 717 */ 718 static const struct drm_display_mode edid_cea_modes_1[] = { 719 /* 1 - 640x480@60Hz 4:3 */ 720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 721 752, 800, 0, 480, 490, 492, 525, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 724 /* 2 - 720x480@60Hz 4:3 */ 725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 726 798, 858, 0, 480, 489, 495, 525, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 729 /* 3 - 720x480@60Hz 16:9 */ 730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 731 798, 858, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 4 - 1280x720@60Hz 16:9 */ 735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 736 1430, 1650, 0, 720, 725, 730, 750, 0, 737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 5 - 1920x1080i@60Hz 16:9 */ 740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 743 DRM_MODE_FLAG_INTERLACE), 744 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 6 - 720(1440)x480i@60Hz 4:3 */ 746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 747 801, 858, 0, 480, 488, 494, 525, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 7 - 720(1440)x480i@60Hz 16:9 */ 752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 753 801, 858, 0, 480, 488, 494, 525, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 756 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 8 - 720(1440)x240@60Hz 4:3 */ 758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 759 801, 858, 0, 240, 244, 247, 262, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_DBLCLK), 762 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 9 - 720(1440)x240@60Hz 16:9 */ 764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 765 801, 858, 0, 240, 244, 247, 262, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_DBLCLK), 768 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 10 - 2880x480i@60Hz 4:3 */ 770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 771 3204, 3432, 0, 480, 488, 494, 525, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_INTERLACE), 774 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 11 - 2880x480i@60Hz 16:9 */ 776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 777 3204, 3432, 0, 480, 488, 494, 525, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_INTERLACE), 780 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 12 - 2880x240@60Hz 4:3 */ 782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 783 3204, 3432, 0, 240, 244, 247, 262, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 785 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 13 - 2880x240@60Hz 16:9 */ 787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 788 3204, 3432, 0, 240, 244, 247, 262, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 790 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 791 /* 14 - 1440x480@60Hz 4:3 */ 792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 793 1596, 1716, 0, 480, 489, 495, 525, 0, 794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 795 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 15 - 1440x480@60Hz 16:9 */ 797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 798 1596, 1716, 0, 480, 489, 495, 525, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 800 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 16 - 1920x1080@60Hz 16:9 */ 802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 806 /* 17 - 720x576@50Hz 4:3 */ 807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 808 796, 864, 0, 576, 581, 586, 625, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 811 /* 18 - 720x576@50Hz 16:9 */ 812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 813 796, 864, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 19 - 1280x720@50Hz 16:9 */ 817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 818 1760, 1980, 0, 720, 725, 730, 750, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 20 - 1920x1080i@50Hz 16:9 */ 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 825 DRM_MODE_FLAG_INTERLACE), 826 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 21 - 720(1440)x576i@50Hz 4:3 */ 828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 829 795, 864, 0, 576, 580, 586, 625, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 833 /* 22 - 720(1440)x576i@50Hz 16:9 */ 834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 835 795, 864, 0, 576, 580, 586, 625, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 838 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 23 - 720(1440)x288@50Hz 4:3 */ 840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 841 795, 864, 0, 288, 290, 293, 312, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 843 DRM_MODE_FLAG_DBLCLK), 844 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 845 /* 24 - 720(1440)x288@50Hz 16:9 */ 846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 847 795, 864, 0, 288, 290, 293, 312, 0, 848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 849 DRM_MODE_FLAG_DBLCLK), 850 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 25 - 2880x576i@50Hz 4:3 */ 852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 853 3180, 3456, 0, 576, 580, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 855 DRM_MODE_FLAG_INTERLACE), 856 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 857 /* 26 - 2880x576i@50Hz 16:9 */ 858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 859 3180, 3456, 0, 576, 580, 586, 625, 0, 860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 861 DRM_MODE_FLAG_INTERLACE), 862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 863 /* 27 - 2880x288@50Hz 4:3 */ 864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 865 3180, 3456, 0, 288, 290, 293, 312, 0, 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 868 /* 28 - 2880x288@50Hz 16:9 */ 869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 870 3180, 3456, 0, 288, 290, 293, 312, 0, 871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 872 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 29 - 1440x576@50Hz 4:3 */ 874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 875 1592, 1728, 0, 576, 581, 586, 625, 0, 876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 877 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 878 /* 30 - 1440x576@50Hz 16:9 */ 879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 880 1592, 1728, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 883 /* 31 - 1920x1080@50Hz 16:9 */ 884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 887 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 32 - 1920x1080@24Hz 16:9 */ 889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 33 - 1920x1080@25Hz 16:9 */ 894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 897 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 34 - 1920x1080@30Hz 16:9 */ 899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 35 - 2880x480@60Hz 4:3 */ 904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 905 3192, 3432, 0, 480, 489, 495, 525, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 907 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 908 /* 36 - 2880x480@60Hz 16:9 */ 909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 910 3192, 3432, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 37 - 2880x576@50Hz 4:3 */ 914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 915 3184, 3456, 0, 576, 581, 586, 625, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 918 /* 38 - 2880x576@50Hz 16:9 */ 919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 920 3184, 3456, 0, 576, 581, 586, 625, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 922 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 923 /* 39 - 1920x1080i@50Hz 16:9 */ 924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 927 DRM_MODE_FLAG_INTERLACE), 928 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 40 - 1920x1080i@100Hz 16:9 */ 930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 933 DRM_MODE_FLAG_INTERLACE), 934 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 41 - 1280x720@100Hz 16:9 */ 936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 937 1760, 1980, 0, 720, 725, 730, 750, 0, 938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 939 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 42 - 720x576@100Hz 4:3 */ 941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 796, 864, 0, 576, 581, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 944 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 945 /* 43 - 720x576@100Hz 16:9 */ 946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 947 796, 864, 0, 576, 581, 586, 625, 0, 948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 949 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 950 /* 44 - 720(1440)x576i@100Hz 4:3 */ 951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 952 795, 864, 0, 576, 580, 586, 625, 0, 953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 955 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 956 /* 45 - 720(1440)x576i@100Hz 16:9 */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 46 - 1920x1080i@120Hz 16:9 */ 963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 966 DRM_MODE_FLAG_INTERLACE), 967 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 47 - 1280x720@120Hz 16:9 */ 969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 970 1430, 1650, 0, 720, 725, 730, 750, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 48 - 720x480@120Hz 4:3 */ 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 975 798, 858, 0, 480, 489, 495, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 977 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 978 /* 49 - 720x480@120Hz 16:9 */ 979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 980 798, 858, 0, 480, 489, 495, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 982 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 983 /* 50 - 720(1440)x480i@120Hz 4:3 */ 984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 985 801, 858, 0, 480, 488, 494, 525, 0, 986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 988 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 989 /* 51 - 720(1440)x480i@120Hz 16:9 */ 990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 991 801, 858, 0, 480, 488, 494, 525, 0, 992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 994 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 52 - 720x576@200Hz 4:3 */ 996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 997 796, 864, 0, 576, 581, 586, 625, 0, 998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 999 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1000 /* 53 - 720x576@200Hz 16:9 */ 1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1002 796, 864, 0, 576, 581, 586, 625, 0, 1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1004 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1007 795, 864, 0, 576, 580, 586, 625, 0, 1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1010 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1011 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1013 795, 864, 0, 576, 580, 586, 625, 0, 1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1016 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 /* 56 - 720x480@240Hz 4:3 */ 1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1019 798, 858, 0, 480, 489, 495, 525, 0, 1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1021 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1022 /* 57 - 720x480@240Hz 16:9 */ 1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1024 798, 858, 0, 480, 489, 495, 525, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1026 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1027 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1029 801, 858, 0, 480, 488, 494, 525, 0, 1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1032 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1033 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1035 801, 858, 0, 480, 488, 494, 525, 0, 1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1038 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1039 /* 60 - 1280x720@24Hz 16:9 */ 1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1041 3080, 3300, 0, 720, 725, 730, 750, 0, 1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1043 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1044 /* 61 - 1280x720@25Hz 16:9 */ 1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1046 3740, 3960, 0, 720, 725, 730, 750, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1049 /* 62 - 1280x720@30Hz 16:9 */ 1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1051 3080, 3300, 0, 720, 725, 730, 750, 0, 1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1053 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1054 /* 63 - 1920x1080@120Hz 16:9 */ 1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1058 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1059 /* 64 - 1920x1080@100Hz 16:9 */ 1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1063 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1064 /* 65 - 1280x720@24Hz 64:27 */ 1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1066 3080, 3300, 0, 720, 725, 730, 750, 0, 1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1068 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1069 /* 66 - 1280x720@25Hz 64:27 */ 1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1071 3740, 3960, 0, 720, 725, 730, 750, 0, 1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1073 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1074 /* 67 - 1280x720@30Hz 64:27 */ 1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1076 3080, 3300, 0, 720, 725, 730, 750, 0, 1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1078 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1079 /* 68 - 1280x720@50Hz 64:27 */ 1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1081 1760, 1980, 0, 720, 725, 730, 750, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1083 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1084 /* 69 - 1280x720@60Hz 64:27 */ 1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1086 1430, 1650, 0, 720, 725, 730, 750, 0, 1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1088 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1089 /* 70 - 1280x720@100Hz 64:27 */ 1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1091 1760, 1980, 0, 720, 725, 730, 750, 0, 1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1093 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1094 /* 71 - 1280x720@120Hz 64:27 */ 1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1096 1430, 1650, 0, 720, 725, 730, 750, 0, 1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1098 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1099 /* 72 - 1920x1080@24Hz 64:27 */ 1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1103 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1104 /* 73 - 1920x1080@25Hz 64:27 */ 1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1108 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1109 /* 74 - 1920x1080@30Hz 64:27 */ 1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1113 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1114 /* 75 - 1920x1080@50Hz 64:27 */ 1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1118 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1119 /* 76 - 1920x1080@60Hz 64:27 */ 1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1123 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1124 /* 77 - 1920x1080@100Hz 64:27 */ 1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1128 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1129 /* 78 - 1920x1080@120Hz 64:27 */ 1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1133 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1134 /* 79 - 1680x720@24Hz 64:27 */ 1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1136 3080, 3300, 0, 720, 725, 730, 750, 0, 1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1138 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1139 /* 80 - 1680x720@25Hz 64:27 */ 1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1141 2948, 3168, 0, 720, 725, 730, 750, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1143 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1144 /* 81 - 1680x720@30Hz 64:27 */ 1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1146 2420, 2640, 0, 720, 725, 730, 750, 0, 1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1148 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1149 /* 82 - 1680x720@50Hz 64:27 */ 1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1151 1980, 2200, 0, 720, 725, 730, 750, 0, 1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1153 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1154 /* 83 - 1680x720@60Hz 64:27 */ 1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1156 1980, 2200, 0, 720, 725, 730, 750, 0, 1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1158 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1159 /* 84 - 1680x720@100Hz 64:27 */ 1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1161 1780, 2000, 0, 720, 725, 730, 825, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1163 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1164 /* 85 - 1680x720@120Hz 64:27 */ 1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1166 1780, 2000, 0, 720, 725, 730, 825, 0, 1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1168 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1169 /* 86 - 2560x1080@24Hz 64:27 */ 1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1173 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1174 /* 87 - 2560x1080@25Hz 64:27 */ 1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1178 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1179 /* 88 - 2560x1080@30Hz 64:27 */ 1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1183 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1184 /* 89 - 2560x1080@50Hz 64:27 */ 1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1188 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1189 /* 90 - 2560x1080@60Hz 64:27 */ 1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1193 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1194 /* 91 - 2560x1080@100Hz 64:27 */ 1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1198 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1199 /* 92 - 2560x1080@120Hz 64:27 */ 1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1203 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1204 /* 93 - 3840x2160@24Hz 16:9 */ 1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1208 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1209 /* 94 - 3840x2160@25Hz 16:9 */ 1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1213 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1214 /* 95 - 3840x2160@30Hz 16:9 */ 1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1218 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1219 /* 96 - 3840x2160@50Hz 16:9 */ 1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1223 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1224 /* 97 - 3840x2160@60Hz 16:9 */ 1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1228 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1229 /* 98 - 4096x2160@24Hz 256:135 */ 1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1233 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1234 /* 99 - 4096x2160@25Hz 256:135 */ 1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1238 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1239 /* 100 - 4096x2160@30Hz 256:135 */ 1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1243 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1244 /* 101 - 4096x2160@50Hz 256:135 */ 1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1248 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1249 /* 102 - 4096x2160@60Hz 256:135 */ 1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1253 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1254 /* 103 - 3840x2160@24Hz 64:27 */ 1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1258 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1259 /* 104 - 3840x2160@25Hz 64:27 */ 1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1263 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1264 /* 105 - 3840x2160@30Hz 64:27 */ 1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1268 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1269 /* 106 - 3840x2160@50Hz 64:27 */ 1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1273 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1274 /* 107 - 3840x2160@60Hz 64:27 */ 1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1278 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1279 /* 108 - 1280x720@48Hz 16:9 */ 1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1281 2280, 2500, 0, 720, 725, 730, 750, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1283 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1284 /* 109 - 1280x720@48Hz 64:27 */ 1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1286 2280, 2500, 0, 720, 725, 730, 750, 0, 1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1288 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1289 /* 110 - 1680x720@48Hz 64:27 */ 1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1291 2530, 2750, 0, 720, 725, 730, 750, 0, 1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1293 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1294 /* 111 - 1920x1080@48Hz 16:9 */ 1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1298 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1299 /* 112 - 1920x1080@48Hz 64:27 */ 1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1303 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1304 /* 113 - 2560x1080@48Hz 64:27 */ 1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1308 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1309 /* 114 - 3840x2160@48Hz 16:9 */ 1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1313 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1314 /* 115 - 4096x2160@48Hz 256:135 */ 1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1318 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1319 /* 116 - 3840x2160@48Hz 64:27 */ 1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1323 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1324 /* 117 - 3840x2160@100Hz 16:9 */ 1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1328 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1329 /* 118 - 3840x2160@120Hz 16:9 */ 1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1333 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1334 /* 119 - 3840x2160@100Hz 64:27 */ 1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1338 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1339 /* 120 - 3840x2160@120Hz 64:27 */ 1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1343 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1344 /* 121 - 5120x2160@24Hz 64:27 */ 1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1348 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1349 /* 122 - 5120x2160@25Hz 64:27 */ 1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1353 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1354 /* 123 - 5120x2160@30Hz 64:27 */ 1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1358 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1359 /* 124 - 5120x2160@48Hz 64:27 */ 1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1363 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1364 /* 125 - 5120x2160@50Hz 64:27 */ 1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1368 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1369 /* 126 - 5120x2160@60Hz 64:27 */ 1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1373 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1374 /* 127 - 5120x2160@100Hz 64:27 */ 1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1378 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1379 }; 1380 1381 /* 1382 * From CEA/CTA-861 spec. 1383 * 1384 * Do not access directly, instead always use cea_mode_for_vic(). 1385 */ 1386 static const struct drm_display_mode edid_cea_modes_193[] = { 1387 /* 193 - 5120x2160@120Hz 64:27 */ 1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1391 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1392 /* 194 - 7680x4320@24Hz 16:9 */ 1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1396 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1397 /* 195 - 7680x4320@25Hz 16:9 */ 1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1401 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1402 /* 196 - 7680x4320@30Hz 16:9 */ 1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1406 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1407 /* 197 - 7680x4320@48Hz 16:9 */ 1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1411 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1412 /* 198 - 7680x4320@50Hz 16:9 */ 1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1416 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1417 /* 199 - 7680x4320@60Hz 16:9 */ 1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1421 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1422 /* 200 - 7680x4320@100Hz 16:9 */ 1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1426 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1427 /* 201 - 7680x4320@120Hz 16:9 */ 1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1431 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1432 /* 202 - 7680x4320@24Hz 64:27 */ 1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1436 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1437 /* 203 - 7680x4320@25Hz 64:27 */ 1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1441 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1442 /* 204 - 7680x4320@30Hz 64:27 */ 1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1446 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1447 /* 205 - 7680x4320@48Hz 64:27 */ 1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1451 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1452 /* 206 - 7680x4320@50Hz 64:27 */ 1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1456 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1457 /* 207 - 7680x4320@60Hz 64:27 */ 1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1461 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1462 /* 208 - 7680x4320@100Hz 64:27 */ 1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1466 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1467 /* 209 - 7680x4320@120Hz 64:27 */ 1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1471 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1472 /* 210 - 10240x4320@24Hz 64:27 */ 1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1476 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1477 /* 211 - 10240x4320@25Hz 64:27 */ 1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1481 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1482 /* 212 - 10240x4320@30Hz 64:27 */ 1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1486 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1487 /* 213 - 10240x4320@48Hz 64:27 */ 1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1491 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1492 /* 214 - 10240x4320@50Hz 64:27 */ 1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1496 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1497 /* 215 - 10240x4320@60Hz 64:27 */ 1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1501 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1502 /* 216 - 10240x4320@100Hz 64:27 */ 1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1506 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1507 /* 217 - 10240x4320@120Hz 64:27 */ 1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1511 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1512 /* 218 - 4096x2160@100Hz 256:135 */ 1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1516 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1517 /* 219 - 4096x2160@120Hz 256:135 */ 1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1521 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1522 }; 1523 1524 /* 1525 * HDMI 1.4 4k modes. Index using the VIC. 1526 */ 1527 static const struct drm_display_mode edid_4k_modes[] = { 1528 /* 0 - dummy, VICs start at 1 */ 1529 { }, 1530 /* 1 - 3840x2160@30Hz */ 1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1532 3840, 4016, 4104, 4400, 0, 1533 2160, 2168, 2178, 2250, 0, 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1535 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1536 /* 2 - 3840x2160@25Hz */ 1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1538 3840, 4896, 4984, 5280, 0, 1539 2160, 2168, 2178, 2250, 0, 1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1541 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1542 /* 3 - 3840x2160@24Hz */ 1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1544 3840, 5116, 5204, 5500, 0, 1545 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1548 /* 4 - 4096x2160@24Hz (SMPTE) */ 1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1550 4096, 5116, 5204, 5500, 0, 1551 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1554 }; 1555 1556 /*** DDC fetch and block validation ***/ 1557 1558 static const u8 edid_header[] = { 1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1560 }; 1561 1562 /** 1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1564 * @raw_edid: pointer to raw base EDID block 1565 * 1566 * Sanity check the header of the base EDID block. 1567 * 1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1569 */ 1570 int drm_edid_header_is_valid(const u8 *raw_edid) 1571 { 1572 int i, score = 0; 1573 1574 for (i = 0; i < sizeof(edid_header); i++) 1575 if (raw_edid[i] == edid_header[i]) 1576 score++; 1577 1578 return score; 1579 } 1580 EXPORT_SYMBOL(drm_edid_header_is_valid); 1581 1582 static int edid_fixup __read_mostly = 6; 1583 module_param_named(edid_fixup, edid_fixup, int, 0400); 1584 MODULE_PARM_DESC(edid_fixup, 1585 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1586 1587 static void drm_get_displayid(struct drm_connector *connector, 1588 struct edid *edid); 1589 static int validate_displayid(u8 *displayid, int length, int idx); 1590 1591 static int drm_edid_block_checksum(const u8 *raw_edid) 1592 { 1593 int i; 1594 u8 csum = 0, crc = 0; 1595 1596 for (i = 0; i < EDID_LENGTH - 1; i++) 1597 csum += raw_edid[i]; 1598 1599 crc = 0x100 - csum; 1600 1601 return crc; 1602 } 1603 1604 static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) 1605 { 1606 if (raw_edid[EDID_LENGTH - 1] != real_checksum) 1607 return true; 1608 else 1609 return false; 1610 } 1611 1612 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1613 { 1614 if (memchr_inv(in_edid, 0, length)) 1615 return false; 1616 1617 return true; 1618 } 1619 1620 /** 1621 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1622 * @raw_edid: pointer to raw EDID block 1623 * @block: type of block to validate (0 for base, extension otherwise) 1624 * @print_bad_edid: if true, dump bad EDID blocks to the console 1625 * @edid_corrupt: if true, the header or checksum is invalid 1626 * 1627 * Validate a base or extension EDID block and optionally dump bad blocks to 1628 * the console. 1629 * 1630 * Return: True if the block is valid, false otherwise. 1631 */ 1632 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1633 bool *edid_corrupt) 1634 { 1635 u8 csum; 1636 struct edid *edid = (struct edid *)raw_edid; 1637 1638 if (WARN_ON(!raw_edid)) 1639 return false; 1640 1641 if (edid_fixup > 8 || edid_fixup < 0) 1642 edid_fixup = 6; 1643 1644 if (block == 0) { 1645 int score = drm_edid_header_is_valid(raw_edid); 1646 if (score == 8) { 1647 if (edid_corrupt) 1648 *edid_corrupt = false; 1649 } else if (score >= edid_fixup) { 1650 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1651 * The corrupt flag needs to be set here otherwise, the 1652 * fix-up code here will correct the problem, the 1653 * checksum is correct and the test fails 1654 */ 1655 if (edid_corrupt) 1656 *edid_corrupt = true; 1657 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1658 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1659 } else { 1660 if (edid_corrupt) 1661 *edid_corrupt = true; 1662 goto bad; 1663 } 1664 } 1665 1666 csum = drm_edid_block_checksum(raw_edid); 1667 if (drm_edid_block_checksum_diff(raw_edid, csum)) { 1668 if (edid_corrupt) 1669 *edid_corrupt = true; 1670 1671 /* allow CEA to slide through, switches mangle this */ 1672 if (raw_edid[0] == CEA_EXT) { 1673 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1674 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1675 } else { 1676 if (print_bad_edid) 1677 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1678 1679 goto bad; 1680 } 1681 } 1682 1683 /* per-block-type checks */ 1684 switch (raw_edid[0]) { 1685 case 0: /* base */ 1686 if (edid->version != 1) { 1687 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1688 goto bad; 1689 } 1690 1691 if (edid->revision > 4) 1692 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1693 break; 1694 1695 default: 1696 break; 1697 } 1698 1699 return true; 1700 1701 bad: 1702 if (print_bad_edid) { 1703 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1704 pr_notice("EDID block is all zeroes\n"); 1705 } else { 1706 pr_notice("Raw EDID:\n"); 1707 print_hex_dump(KERN_NOTICE, 1708 " \t", DUMP_PREFIX_NONE, 16, 1, 1709 raw_edid, EDID_LENGTH, false); 1710 } 1711 } 1712 return false; 1713 } 1714 EXPORT_SYMBOL(drm_edid_block_valid); 1715 1716 /** 1717 * drm_edid_is_valid - sanity check EDID data 1718 * @edid: EDID data 1719 * 1720 * Sanity-check an entire EDID record (including extensions) 1721 * 1722 * Return: True if the EDID data is valid, false otherwise. 1723 */ 1724 bool drm_edid_is_valid(struct edid *edid) 1725 { 1726 int i; 1727 u8 *raw = (u8 *)edid; 1728 1729 if (!edid) 1730 return false; 1731 1732 for (i = 0; i <= edid->extensions; i++) 1733 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1734 return false; 1735 1736 return true; 1737 } 1738 EXPORT_SYMBOL(drm_edid_is_valid); 1739 1740 #define DDC_SEGMENT_ADDR 0x30 1741 /** 1742 * drm_do_probe_ddc_edid() - get EDID information via I2C 1743 * @data: I2C device adapter 1744 * @buf: EDID data buffer to be filled 1745 * @block: 128 byte EDID block to start fetching from 1746 * @len: EDID data buffer length to fetch 1747 * 1748 * Try to fetch EDID information by calling I2C driver functions. 1749 * 1750 * Return: 0 on success or -1 on failure. 1751 */ 1752 static int 1753 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1754 { 1755 struct i2c_adapter *adapter = data; 1756 unsigned char start = block * EDID_LENGTH; 1757 unsigned char segment = block >> 1; 1758 unsigned char xfers = segment ? 3 : 2; 1759 int ret, retries = 5; 1760 1761 /* 1762 * The core I2C driver will automatically retry the transfer if the 1763 * adapter reports EAGAIN. However, we find that bit-banging transfers 1764 * are susceptible to errors under a heavily loaded machine and 1765 * generate spurious NAKs and timeouts. Retrying the transfer 1766 * of the individual block a few times seems to overcome this. 1767 */ 1768 do { 1769 struct i2c_msg msgs[] = { 1770 { 1771 .addr = DDC_SEGMENT_ADDR, 1772 .flags = 0, 1773 .len = 1, 1774 .buf = &segment, 1775 }, { 1776 .addr = DDC_ADDR, 1777 .flags = 0, 1778 .len = 1, 1779 .buf = &start, 1780 }, { 1781 .addr = DDC_ADDR, 1782 .flags = I2C_M_RD, 1783 .len = len, 1784 .buf = buf, 1785 } 1786 }; 1787 1788 /* 1789 * Avoid sending the segment addr to not upset non-compliant 1790 * DDC monitors. 1791 */ 1792 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1793 1794 if (ret == -ENXIO) { 1795 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1796 adapter->name); 1797 break; 1798 } 1799 } while (ret != xfers && --retries); 1800 1801 return ret == xfers ? 0 : -1; 1802 } 1803 1804 static void connector_bad_edid(struct drm_connector *connector, 1805 u8 *edid, int num_blocks) 1806 { 1807 int i; 1808 u8 num_of_ext = edid[0x7e]; 1809 1810 if (num_of_ext > num_blocks) 1811 num_of_ext = num_blocks; 1812 1813 /* Calculate real checksum for the last edid extension block data */ 1814 connector->real_edid_checksum = 1815 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH); 1816 1817 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1818 return; 1819 1820 dev_warn(connector->dev->dev, 1821 "%s: EDID is invalid:\n", 1822 connector->name); 1823 for (i = 0; i < num_blocks; i++) { 1824 u8 *block = edid + i * EDID_LENGTH; 1825 char prefix[20]; 1826 1827 if (drm_edid_is_zero(block, EDID_LENGTH)) 1828 snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", i); 1829 else if (!drm_edid_block_valid(block, i, false, NULL)) 1830 snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", i); 1831 else 1832 snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", i); 1833 1834 print_hex_dump(KERN_WARNING, 1835 prefix, DUMP_PREFIX_NONE, 16, 1, 1836 block, EDID_LENGTH, false); 1837 } 1838 } 1839 1840 /* Get override or firmware EDID */ 1841 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1842 { 1843 struct edid *override = NULL; 1844 1845 if (connector->override_edid) 1846 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1847 1848 if (!override) 1849 override = drm_load_edid_firmware(connector); 1850 1851 return IS_ERR(override) ? NULL : override; 1852 } 1853 1854 /** 1855 * drm_add_override_edid_modes - add modes from override/firmware EDID 1856 * @connector: connector we're probing 1857 * 1858 * Add modes from the override/firmware EDID, if available. Only to be used from 1859 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1860 * failed during drm_get_edid() and caused the override/firmware EDID to be 1861 * skipped. 1862 * 1863 * Return: The number of modes added or 0 if we couldn't find any. 1864 */ 1865 int drm_add_override_edid_modes(struct drm_connector *connector) 1866 { 1867 struct edid *override; 1868 int num_modes = 0; 1869 1870 override = drm_get_override_edid(connector); 1871 if (override) { 1872 drm_connector_update_edid_property(connector, override); 1873 num_modes = drm_add_edid_modes(connector, override); 1874 kfree(override); 1875 1876 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1877 connector->base.id, connector->name, num_modes); 1878 } 1879 1880 return num_modes; 1881 } 1882 EXPORT_SYMBOL(drm_add_override_edid_modes); 1883 1884 /** 1885 * drm_do_get_edid - get EDID data using a custom EDID block read function 1886 * @connector: connector we're probing 1887 * @get_edid_block: EDID block read function 1888 * @data: private data passed to the block read function 1889 * 1890 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1891 * exposes a different interface to read EDID blocks this function can be used 1892 * to get EDID data using a custom block read function. 1893 * 1894 * As in the general case the DDC bus is accessible by the kernel at the I2C 1895 * level, drivers must make all reasonable efforts to expose it as an I2C 1896 * adapter and use drm_get_edid() instead of abusing this function. 1897 * 1898 * The EDID may be overridden using debugfs override_edid or firmare EDID 1899 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1900 * order. Having either of them bypasses actual EDID reads. 1901 * 1902 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1903 */ 1904 struct edid *drm_do_get_edid(struct drm_connector *connector, 1905 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1906 size_t len), 1907 void *data) 1908 { 1909 int i, j = 0, valid_extensions = 0; 1910 u8 *edid, *new; 1911 struct edid *override; 1912 1913 override = drm_get_override_edid(connector); 1914 if (override) 1915 return override; 1916 1917 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1918 return NULL; 1919 1920 /* base block fetch */ 1921 for (i = 0; i < 4; i++) { 1922 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1923 goto out; 1924 if (drm_edid_block_valid(edid, 0, false, 1925 &connector->edid_corrupt)) 1926 break; 1927 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1928 connector->null_edid_counter++; 1929 goto carp; 1930 } 1931 } 1932 if (i == 4) 1933 goto carp; 1934 1935 /* if there's no extensions, we're done */ 1936 valid_extensions = edid[0x7e]; 1937 if (valid_extensions == 0) 1938 return (struct edid *)edid; 1939 1940 #ifdef __linux__ 1941 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1942 if (!new) 1943 goto out; 1944 #else 1945 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1946 if (!new) 1947 goto out; 1948 memcpy(new, edid, EDID_LENGTH); 1949 kfree(edid); 1950 #endif 1951 edid = new; 1952 1953 for (j = 1; j <= edid[0x7e]; j++) { 1954 u8 *block = edid + j * EDID_LENGTH; 1955 1956 for (i = 0; i < 4; i++) { 1957 if (get_edid_block(data, block, j, EDID_LENGTH)) 1958 goto out; 1959 if (drm_edid_block_valid(block, j, false, NULL)) 1960 break; 1961 } 1962 1963 if (i == 4) 1964 valid_extensions--; 1965 } 1966 1967 if (valid_extensions != edid[0x7e]) { 1968 u8 *base; 1969 1970 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1971 1972 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1973 edid[0x7e] = valid_extensions; 1974 1975 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1976 GFP_KERNEL); 1977 if (!new) 1978 goto out; 1979 1980 base = new; 1981 for (i = 0; i <= edid[0x7e]; i++) { 1982 u8 *block = edid + i * EDID_LENGTH; 1983 1984 if (!drm_edid_block_valid(block, i, false, NULL)) 1985 continue; 1986 1987 memcpy(base, block, EDID_LENGTH); 1988 base += EDID_LENGTH; 1989 } 1990 1991 kfree(edid); 1992 edid = new; 1993 } 1994 1995 return (struct edid *)edid; 1996 1997 carp: 1998 connector_bad_edid(connector, edid, 1); 1999 out: 2000 kfree(edid); 2001 return NULL; 2002 } 2003 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2004 2005 /** 2006 * drm_probe_ddc() - probe DDC presence 2007 * @adapter: I2C adapter to probe 2008 * 2009 * Return: True on success, false on failure. 2010 */ 2011 bool 2012 drm_probe_ddc(struct i2c_adapter *adapter) 2013 { 2014 unsigned char out; 2015 2016 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2017 } 2018 EXPORT_SYMBOL(drm_probe_ddc); 2019 2020 /** 2021 * drm_get_edid - get EDID data, if available 2022 * @connector: connector we're probing 2023 * @adapter: I2C adapter to use for DDC 2024 * 2025 * Poke the given I2C channel to grab EDID data if possible. If found, 2026 * attach it to the connector. 2027 * 2028 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2029 */ 2030 struct edid *drm_get_edid(struct drm_connector *connector, 2031 struct i2c_adapter *adapter) 2032 { 2033 struct edid *edid; 2034 2035 if (connector->force == DRM_FORCE_OFF) 2036 return NULL; 2037 2038 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2039 return NULL; 2040 2041 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2042 if (edid) 2043 drm_get_displayid(connector, edid); 2044 return edid; 2045 } 2046 EXPORT_SYMBOL(drm_get_edid); 2047 2048 /** 2049 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2050 * @connector: connector we're probing 2051 * @adapter: I2C adapter to use for DDC 2052 * 2053 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2054 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2055 * switch DDC to the GPU which is retrieving EDID. 2056 * 2057 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2058 */ 2059 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2060 struct i2c_adapter *adapter) 2061 { 2062 struct pci_dev *pdev = connector->dev->pdev; 2063 struct edid *edid; 2064 2065 vga_switcheroo_lock_ddc(pdev); 2066 edid = drm_get_edid(connector, adapter); 2067 vga_switcheroo_unlock_ddc(pdev); 2068 2069 return edid; 2070 } 2071 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2072 2073 /** 2074 * drm_edid_duplicate - duplicate an EDID and the extensions 2075 * @edid: EDID to duplicate 2076 * 2077 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2078 */ 2079 struct edid *drm_edid_duplicate(const struct edid *edid) 2080 { 2081 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2082 } 2083 EXPORT_SYMBOL(drm_edid_duplicate); 2084 2085 /*** EDID parsing ***/ 2086 2087 /** 2088 * edid_vendor - match a string against EDID's obfuscated vendor field 2089 * @edid: EDID to match 2090 * @vendor: vendor string 2091 * 2092 * Returns true if @vendor is in @edid, false otherwise 2093 */ 2094 static bool edid_vendor(const struct edid *edid, const char *vendor) 2095 { 2096 char edid_vendor[3]; 2097 2098 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2099 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2100 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2101 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2102 2103 return !strncmp(edid_vendor, vendor, 3); 2104 } 2105 2106 /** 2107 * edid_get_quirks - return quirk flags for a given EDID 2108 * @edid: EDID to process 2109 * 2110 * This tells subsequent routines what fixes they need to apply. 2111 */ 2112 static u32 edid_get_quirks(const struct edid *edid) 2113 { 2114 const struct edid_quirk *quirk; 2115 int i; 2116 2117 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2118 quirk = &edid_quirk_list[i]; 2119 2120 if (edid_vendor(edid, quirk->vendor) && 2121 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2122 return quirk->quirks; 2123 } 2124 2125 return 0; 2126 } 2127 2128 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2129 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2130 2131 /** 2132 * edid_fixup_preferred - set preferred modes based on quirk list 2133 * @connector: has mode list to fix up 2134 * @quirks: quirks list 2135 * 2136 * Walk the mode list for @connector, clearing the preferred status 2137 * on existing modes and setting it anew for the right mode ala @quirks. 2138 */ 2139 static void edid_fixup_preferred(struct drm_connector *connector, 2140 u32 quirks) 2141 { 2142 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2143 int target_refresh = 0; 2144 int cur_vrefresh, preferred_vrefresh; 2145 2146 if (list_empty(&connector->probed_modes)) 2147 return; 2148 2149 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2150 target_refresh = 60; 2151 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2152 target_refresh = 75; 2153 2154 preferred_mode = list_first_entry(&connector->probed_modes, 2155 struct drm_display_mode, head); 2156 2157 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2158 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2159 2160 if (cur_mode == preferred_mode) 2161 continue; 2162 2163 /* Largest mode is preferred */ 2164 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2165 preferred_mode = cur_mode; 2166 2167 cur_vrefresh = cur_mode->vrefresh ? 2168 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 2169 preferred_vrefresh = preferred_mode->vrefresh ? 2170 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 2171 /* At a given size, try to get closest to target refresh */ 2172 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2173 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2174 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2175 preferred_mode = cur_mode; 2176 } 2177 } 2178 2179 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2180 } 2181 2182 static bool 2183 mode_is_rb(const struct drm_display_mode *mode) 2184 { 2185 return (mode->htotal - mode->hdisplay == 160) && 2186 (mode->hsync_end - mode->hdisplay == 80) && 2187 (mode->hsync_end - mode->hsync_start == 32) && 2188 (mode->vsync_start - mode->vdisplay == 3); 2189 } 2190 2191 /* 2192 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2193 * @dev: Device to duplicate against 2194 * @hsize: Mode width 2195 * @vsize: Mode height 2196 * @fresh: Mode refresh rate 2197 * @rb: Mode reduced-blanking-ness 2198 * 2199 * Walk the DMT mode list looking for a match for the given parameters. 2200 * 2201 * Return: A newly allocated copy of the mode, or NULL if not found. 2202 */ 2203 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2204 int hsize, int vsize, int fresh, 2205 bool rb) 2206 { 2207 int i; 2208 2209 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2210 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2211 if (hsize != ptr->hdisplay) 2212 continue; 2213 if (vsize != ptr->vdisplay) 2214 continue; 2215 if (fresh != drm_mode_vrefresh(ptr)) 2216 continue; 2217 if (rb != mode_is_rb(ptr)) 2218 continue; 2219 2220 return drm_mode_duplicate(dev, ptr); 2221 } 2222 2223 return NULL; 2224 } 2225 EXPORT_SYMBOL(drm_mode_find_dmt); 2226 2227 static bool is_display_descriptor(const u8 d[18], u8 tag) 2228 { 2229 return d[0] == 0x00 && d[1] == 0x00 && 2230 d[2] == 0x00 && d[3] == tag; 2231 } 2232 2233 static bool is_detailed_timing_descriptor(const u8 d[18]) 2234 { 2235 return d[0] != 0x00 || d[1] != 0x00; 2236 } 2237 2238 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2239 2240 static void 2241 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2242 { 2243 int i, n; 2244 u8 d = ext[0x02]; 2245 u8 *det_base = ext + d; 2246 2247 if (d < 4 || d > 127) 2248 return; 2249 2250 n = (127 - d) / 18; 2251 for (i = 0; i < n; i++) 2252 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2253 } 2254 2255 static void 2256 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2257 { 2258 unsigned int i, n = min((int)ext[0x02], 6); 2259 u8 *det_base = ext + 5; 2260 2261 if (ext[0x01] != 1) 2262 return; /* unknown version */ 2263 2264 for (i = 0; i < n; i++) 2265 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2266 } 2267 2268 static void 2269 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2270 { 2271 int i; 2272 struct edid *edid = (struct edid *)raw_edid; 2273 2274 if (edid == NULL) 2275 return; 2276 2277 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2278 cb(&(edid->detailed_timings[i]), closure); 2279 2280 for (i = 1; i <= raw_edid[0x7e]; i++) { 2281 u8 *ext = raw_edid + (i * EDID_LENGTH); 2282 switch (*ext) { 2283 case CEA_EXT: 2284 cea_for_each_detailed_block(ext, cb, closure); 2285 break; 2286 case VTB_EXT: 2287 vtb_for_each_detailed_block(ext, cb, closure); 2288 break; 2289 default: 2290 break; 2291 } 2292 } 2293 } 2294 2295 static void 2296 is_rb(struct detailed_timing *t, void *data) 2297 { 2298 u8 *r = (u8 *)t; 2299 2300 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2301 return; 2302 2303 if (r[15] & 0x10) 2304 *(bool *)data = true; 2305 } 2306 2307 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2308 static bool 2309 drm_monitor_supports_rb(struct edid *edid) 2310 { 2311 if (edid->revision >= 4) { 2312 bool ret = false; 2313 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2314 return ret; 2315 } 2316 2317 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2318 } 2319 2320 static void 2321 find_gtf2(struct detailed_timing *t, void *data) 2322 { 2323 u8 *r = (u8 *)t; 2324 2325 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE)) 2326 return; 2327 2328 if (r[10] == 0x02) 2329 *(u8 **)data = r; 2330 } 2331 2332 /* Secondary GTF curve kicks in above some break frequency */ 2333 static int 2334 drm_gtf2_hbreak(struct edid *edid) 2335 { 2336 u8 *r = NULL; 2337 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2338 return r ? (r[12] * 2) : 0; 2339 } 2340 2341 static int 2342 drm_gtf2_2c(struct edid *edid) 2343 { 2344 u8 *r = NULL; 2345 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2346 return r ? r[13] : 0; 2347 } 2348 2349 static int 2350 drm_gtf2_m(struct edid *edid) 2351 { 2352 u8 *r = NULL; 2353 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2354 return r ? (r[15] << 8) + r[14] : 0; 2355 } 2356 2357 static int 2358 drm_gtf2_k(struct edid *edid) 2359 { 2360 u8 *r = NULL; 2361 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2362 return r ? r[16] : 0; 2363 } 2364 2365 static int 2366 drm_gtf2_2j(struct edid *edid) 2367 { 2368 u8 *r = NULL; 2369 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2370 return r ? r[17] : 0; 2371 } 2372 2373 /** 2374 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2375 * @edid: EDID block to scan 2376 */ 2377 static int standard_timing_level(struct edid *edid) 2378 { 2379 if (edid->revision >= 2) { 2380 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2381 return LEVEL_CVT; 2382 if (drm_gtf2_hbreak(edid)) 2383 return LEVEL_GTF2; 2384 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2385 return LEVEL_GTF; 2386 } 2387 return LEVEL_DMT; 2388 } 2389 2390 /* 2391 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2392 * monitors fill with ascii space (0x20) instead. 2393 */ 2394 static int 2395 bad_std_timing(u8 a, u8 b) 2396 { 2397 return (a == 0x00 && b == 0x00) || 2398 (a == 0x01 && b == 0x01) || 2399 (a == 0x20 && b == 0x20); 2400 } 2401 2402 /** 2403 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2404 * @connector: connector of for the EDID block 2405 * @edid: EDID block to scan 2406 * @t: standard timing params 2407 * 2408 * Take the standard timing params (in this case width, aspect, and refresh) 2409 * and convert them into a real mode using CVT/GTF/DMT. 2410 */ 2411 static struct drm_display_mode * 2412 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2413 struct std_timing *t) 2414 { 2415 struct drm_device *dev = connector->dev; 2416 struct drm_display_mode *m, *mode = NULL; 2417 int hsize, vsize; 2418 int vrefresh_rate; 2419 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2420 >> EDID_TIMING_ASPECT_SHIFT; 2421 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2422 >> EDID_TIMING_VFREQ_SHIFT; 2423 int timing_level = standard_timing_level(edid); 2424 2425 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2426 return NULL; 2427 2428 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2429 hsize = t->hsize * 8 + 248; 2430 /* vrefresh_rate = vfreq + 60 */ 2431 vrefresh_rate = vfreq + 60; 2432 /* the vdisplay is calculated based on the aspect ratio */ 2433 if (aspect_ratio == 0) { 2434 if (edid->revision < 3) 2435 vsize = hsize; 2436 else 2437 vsize = (hsize * 10) / 16; 2438 } else if (aspect_ratio == 1) 2439 vsize = (hsize * 3) / 4; 2440 else if (aspect_ratio == 2) 2441 vsize = (hsize * 4) / 5; 2442 else 2443 vsize = (hsize * 9) / 16; 2444 2445 /* HDTV hack, part 1 */ 2446 if (vrefresh_rate == 60 && 2447 ((hsize == 1360 && vsize == 765) || 2448 (hsize == 1368 && vsize == 769))) { 2449 hsize = 1366; 2450 vsize = 768; 2451 } 2452 2453 /* 2454 * If this connector already has a mode for this size and refresh 2455 * rate (because it came from detailed or CVT info), use that 2456 * instead. This way we don't have to guess at interlace or 2457 * reduced blanking. 2458 */ 2459 list_for_each_entry(m, &connector->probed_modes, head) 2460 if (m->hdisplay == hsize && m->vdisplay == vsize && 2461 drm_mode_vrefresh(m) == vrefresh_rate) 2462 return NULL; 2463 2464 /* HDTV hack, part 2 */ 2465 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2466 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2467 false); 2468 if (!mode) 2469 return NULL; 2470 mode->hdisplay = 1366; 2471 mode->hsync_start = mode->hsync_start - 1; 2472 mode->hsync_end = mode->hsync_end - 1; 2473 return mode; 2474 } 2475 2476 /* check whether it can be found in default mode table */ 2477 if (drm_monitor_supports_rb(edid)) { 2478 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2479 true); 2480 if (mode) 2481 return mode; 2482 } 2483 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2484 if (mode) 2485 return mode; 2486 2487 /* okay, generate it */ 2488 switch (timing_level) { 2489 case LEVEL_DMT: 2490 break; 2491 case LEVEL_GTF: 2492 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2493 break; 2494 case LEVEL_GTF2: 2495 /* 2496 * This is potentially wrong if there's ever a monitor with 2497 * more than one ranges section, each claiming a different 2498 * secondary GTF curve. Please don't do that. 2499 */ 2500 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2501 if (!mode) 2502 return NULL; 2503 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2504 drm_mode_destroy(dev, mode); 2505 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2506 vrefresh_rate, 0, 0, 2507 drm_gtf2_m(edid), 2508 drm_gtf2_2c(edid), 2509 drm_gtf2_k(edid), 2510 drm_gtf2_2j(edid)); 2511 } 2512 break; 2513 case LEVEL_CVT: 2514 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2515 false); 2516 break; 2517 } 2518 return mode; 2519 } 2520 2521 /* 2522 * EDID is delightfully ambiguous about how interlaced modes are to be 2523 * encoded. Our internal representation is of frame height, but some 2524 * HDTV detailed timings are encoded as field height. 2525 * 2526 * The format list here is from CEA, in frame size. Technically we 2527 * should be checking refresh rate too. Whatever. 2528 */ 2529 static void 2530 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2531 struct detailed_pixel_timing *pt) 2532 { 2533 int i; 2534 static const struct { 2535 int w, h; 2536 } cea_interlaced[] = { 2537 { 1920, 1080 }, 2538 { 720, 480 }, 2539 { 1440, 480 }, 2540 { 2880, 480 }, 2541 { 720, 576 }, 2542 { 1440, 576 }, 2543 { 2880, 576 }, 2544 }; 2545 2546 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2547 return; 2548 2549 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2550 if ((mode->hdisplay == cea_interlaced[i].w) && 2551 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2552 mode->vdisplay *= 2; 2553 mode->vsync_start *= 2; 2554 mode->vsync_end *= 2; 2555 mode->vtotal *= 2; 2556 mode->vtotal |= 1; 2557 } 2558 } 2559 2560 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2561 } 2562 2563 /** 2564 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2565 * @dev: DRM device (needed to create new mode) 2566 * @edid: EDID block 2567 * @timing: EDID detailed timing info 2568 * @quirks: quirks to apply 2569 * 2570 * An EDID detailed timing block contains enough info for us to create and 2571 * return a new struct drm_display_mode. 2572 */ 2573 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2574 struct edid *edid, 2575 struct detailed_timing *timing, 2576 u32 quirks) 2577 { 2578 struct drm_display_mode *mode; 2579 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2580 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2581 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2582 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2583 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2584 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2585 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2586 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2587 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2588 2589 /* ignore tiny modes */ 2590 if (hactive < 64 || vactive < 64) 2591 return NULL; 2592 2593 if (pt->misc & DRM_EDID_PT_STEREO) { 2594 DRM_DEBUG_KMS("stereo mode not supported\n"); 2595 return NULL; 2596 } 2597 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2598 DRM_DEBUG_KMS("composite sync not supported\n"); 2599 } 2600 2601 /* it is incorrect if hsync/vsync width is zero */ 2602 if (!hsync_pulse_width || !vsync_pulse_width) { 2603 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2604 "Wrong Hsync/Vsync pulse width\n"); 2605 return NULL; 2606 } 2607 2608 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2609 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2610 if (!mode) 2611 return NULL; 2612 2613 goto set_size; 2614 } 2615 2616 mode = drm_mode_create(dev); 2617 if (!mode) 2618 return NULL; 2619 2620 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2621 timing->pixel_clock = cpu_to_le16(1088); 2622 2623 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2624 2625 mode->hdisplay = hactive; 2626 mode->hsync_start = mode->hdisplay + hsync_offset; 2627 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2628 mode->htotal = mode->hdisplay + hblank; 2629 2630 mode->vdisplay = vactive; 2631 mode->vsync_start = mode->vdisplay + vsync_offset; 2632 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2633 mode->vtotal = mode->vdisplay + vblank; 2634 2635 /* Some EDIDs have bogus h/vtotal values */ 2636 if (mode->hsync_end > mode->htotal) 2637 mode->htotal = mode->hsync_end + 1; 2638 if (mode->vsync_end > mode->vtotal) 2639 mode->vtotal = mode->vsync_end + 1; 2640 2641 drm_mode_do_interlace_quirk(mode, pt); 2642 2643 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2644 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2645 } 2646 2647 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2648 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2649 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2650 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2651 2652 set_size: 2653 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2654 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2655 2656 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2657 mode->width_mm *= 10; 2658 mode->height_mm *= 10; 2659 } 2660 2661 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2662 mode->width_mm = edid->width_cm * 10; 2663 mode->height_mm = edid->height_cm * 10; 2664 } 2665 2666 mode->type = DRM_MODE_TYPE_DRIVER; 2667 mode->vrefresh = drm_mode_vrefresh(mode); 2668 drm_mode_set_name(mode); 2669 2670 return mode; 2671 } 2672 2673 static bool 2674 mode_in_hsync_range(const struct drm_display_mode *mode, 2675 struct edid *edid, u8 *t) 2676 { 2677 int hsync, hmin, hmax; 2678 2679 hmin = t[7]; 2680 if (edid->revision >= 4) 2681 hmin += ((t[4] & 0x04) ? 255 : 0); 2682 hmax = t[8]; 2683 if (edid->revision >= 4) 2684 hmax += ((t[4] & 0x08) ? 255 : 0); 2685 hsync = drm_mode_hsync(mode); 2686 2687 return (hsync <= hmax && hsync >= hmin); 2688 } 2689 2690 static bool 2691 mode_in_vsync_range(const struct drm_display_mode *mode, 2692 struct edid *edid, u8 *t) 2693 { 2694 int vsync, vmin, vmax; 2695 2696 vmin = t[5]; 2697 if (edid->revision >= 4) 2698 vmin += ((t[4] & 0x01) ? 255 : 0); 2699 vmax = t[6]; 2700 if (edid->revision >= 4) 2701 vmax += ((t[4] & 0x02) ? 255 : 0); 2702 vsync = drm_mode_vrefresh(mode); 2703 2704 return (vsync <= vmax && vsync >= vmin); 2705 } 2706 2707 static u32 2708 range_pixel_clock(struct edid *edid, u8 *t) 2709 { 2710 /* unspecified */ 2711 if (t[9] == 0 || t[9] == 255) 2712 return 0; 2713 2714 /* 1.4 with CVT support gives us real precision, yay */ 2715 if (edid->revision >= 4 && t[10] == 0x04) 2716 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2717 2718 /* 1.3 is pathetic, so fuzz up a bit */ 2719 return t[9] * 10000 + 5001; 2720 } 2721 2722 static bool 2723 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2724 struct detailed_timing *timing) 2725 { 2726 u32 max_clock; 2727 u8 *t = (u8 *)timing; 2728 2729 if (!mode_in_hsync_range(mode, edid, t)) 2730 return false; 2731 2732 if (!mode_in_vsync_range(mode, edid, t)) 2733 return false; 2734 2735 if ((max_clock = range_pixel_clock(edid, t))) 2736 if (mode->clock > max_clock) 2737 return false; 2738 2739 /* 1.4 max horizontal check */ 2740 if (edid->revision >= 4 && t[10] == 0x04) 2741 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2742 return false; 2743 2744 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2745 return false; 2746 2747 return true; 2748 } 2749 2750 static bool valid_inferred_mode(const struct drm_connector *connector, 2751 const struct drm_display_mode *mode) 2752 { 2753 const struct drm_display_mode *m; 2754 bool ok = false; 2755 2756 list_for_each_entry(m, &connector->probed_modes, head) { 2757 if (mode->hdisplay == m->hdisplay && 2758 mode->vdisplay == m->vdisplay && 2759 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2760 return false; /* duplicated */ 2761 if (mode->hdisplay <= m->hdisplay && 2762 mode->vdisplay <= m->vdisplay) 2763 ok = true; 2764 } 2765 return ok; 2766 } 2767 2768 static int 2769 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2770 struct detailed_timing *timing) 2771 { 2772 int i, modes = 0; 2773 struct drm_display_mode *newmode; 2774 struct drm_device *dev = connector->dev; 2775 2776 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2777 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2778 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2779 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2780 if (newmode) { 2781 drm_mode_probed_add(connector, newmode); 2782 modes++; 2783 } 2784 } 2785 } 2786 2787 return modes; 2788 } 2789 2790 /* fix up 1366x768 mode from 1368x768; 2791 * GFT/CVT can't express 1366 width which isn't dividable by 8 2792 */ 2793 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2794 { 2795 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2796 mode->hdisplay = 1366; 2797 mode->hsync_start--; 2798 mode->hsync_end--; 2799 drm_mode_set_name(mode); 2800 } 2801 } 2802 2803 static int 2804 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2805 struct detailed_timing *timing) 2806 { 2807 int i, modes = 0; 2808 struct drm_display_mode *newmode; 2809 struct drm_device *dev = connector->dev; 2810 2811 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2812 const struct minimode *m = &extra_modes[i]; 2813 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2814 if (!newmode) 2815 return modes; 2816 2817 drm_mode_fixup_1366x768(newmode); 2818 if (!mode_in_range(newmode, edid, timing) || 2819 !valid_inferred_mode(connector, newmode)) { 2820 drm_mode_destroy(dev, newmode); 2821 continue; 2822 } 2823 2824 drm_mode_probed_add(connector, newmode); 2825 modes++; 2826 } 2827 2828 return modes; 2829 } 2830 2831 static int 2832 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2833 struct detailed_timing *timing) 2834 { 2835 int i, modes = 0; 2836 struct drm_display_mode *newmode; 2837 struct drm_device *dev = connector->dev; 2838 bool rb = drm_monitor_supports_rb(edid); 2839 2840 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2841 const struct minimode *m = &extra_modes[i]; 2842 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2843 if (!newmode) 2844 return modes; 2845 2846 drm_mode_fixup_1366x768(newmode); 2847 if (!mode_in_range(newmode, edid, timing) || 2848 !valid_inferred_mode(connector, newmode)) { 2849 drm_mode_destroy(dev, newmode); 2850 continue; 2851 } 2852 2853 drm_mode_probed_add(connector, newmode); 2854 modes++; 2855 } 2856 2857 return modes; 2858 } 2859 2860 static void 2861 do_inferred_modes(struct detailed_timing *timing, void *c) 2862 { 2863 struct detailed_mode_closure *closure = c; 2864 struct detailed_non_pixel *data = &timing->data.other_data; 2865 struct detailed_data_monitor_range *range = &data->data.range; 2866 2867 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 2868 return; 2869 2870 closure->modes += drm_dmt_modes_for_range(closure->connector, 2871 closure->edid, 2872 timing); 2873 2874 if (!version_greater(closure->edid, 1, 1)) 2875 return; /* GTF not defined yet */ 2876 2877 switch (range->flags) { 2878 case 0x02: /* secondary gtf, XXX could do more */ 2879 case 0x00: /* default gtf */ 2880 closure->modes += drm_gtf_modes_for_range(closure->connector, 2881 closure->edid, 2882 timing); 2883 break; 2884 case 0x04: /* cvt, only in 1.4+ */ 2885 if (!version_greater(closure->edid, 1, 3)) 2886 break; 2887 2888 closure->modes += drm_cvt_modes_for_range(closure->connector, 2889 closure->edid, 2890 timing); 2891 break; 2892 case 0x01: /* just the ranges, no formula */ 2893 default: 2894 break; 2895 } 2896 } 2897 2898 static int 2899 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2900 { 2901 struct detailed_mode_closure closure = { 2902 .connector = connector, 2903 .edid = edid, 2904 }; 2905 2906 if (version_greater(edid, 1, 0)) 2907 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2908 &closure); 2909 2910 return closure.modes; 2911 } 2912 2913 static int 2914 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2915 { 2916 int i, j, m, modes = 0; 2917 struct drm_display_mode *mode; 2918 u8 *est = ((u8 *)timing) + 6; 2919 2920 for (i = 0; i < 6; i++) { 2921 for (j = 7; j >= 0; j--) { 2922 m = (i * 8) + (7 - j); 2923 if (m >= ARRAY_SIZE(est3_modes)) 2924 break; 2925 if (est[i] & (1 << j)) { 2926 mode = drm_mode_find_dmt(connector->dev, 2927 est3_modes[m].w, 2928 est3_modes[m].h, 2929 est3_modes[m].r, 2930 est3_modes[m].rb); 2931 if (mode) { 2932 drm_mode_probed_add(connector, mode); 2933 modes++; 2934 } 2935 } 2936 } 2937 } 2938 2939 return modes; 2940 } 2941 2942 static void 2943 do_established_modes(struct detailed_timing *timing, void *c) 2944 { 2945 struct detailed_mode_closure *closure = c; 2946 2947 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS)) 2948 return; 2949 2950 closure->modes += drm_est3_modes(closure->connector, timing); 2951 } 2952 2953 /** 2954 * add_established_modes - get est. modes from EDID and add them 2955 * @connector: connector to add mode(s) to 2956 * @edid: EDID block to scan 2957 * 2958 * Each EDID block contains a bitmap of the supported "established modes" list 2959 * (defined above). Tease them out and add them to the global modes list. 2960 */ 2961 static int 2962 add_established_modes(struct drm_connector *connector, struct edid *edid) 2963 { 2964 struct drm_device *dev = connector->dev; 2965 unsigned long est_bits = edid->established_timings.t1 | 2966 (edid->established_timings.t2 << 8) | 2967 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2968 int i, modes = 0; 2969 struct detailed_mode_closure closure = { 2970 .connector = connector, 2971 .edid = edid, 2972 }; 2973 2974 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2975 if (est_bits & (1<<i)) { 2976 struct drm_display_mode *newmode; 2977 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2978 if (newmode) { 2979 drm_mode_probed_add(connector, newmode); 2980 modes++; 2981 } 2982 } 2983 } 2984 2985 if (version_greater(edid, 1, 0)) 2986 drm_for_each_detailed_block((u8 *)edid, 2987 do_established_modes, &closure); 2988 2989 return modes + closure.modes; 2990 } 2991 2992 static void 2993 do_standard_modes(struct detailed_timing *timing, void *c) 2994 { 2995 struct detailed_mode_closure *closure = c; 2996 struct detailed_non_pixel *data = &timing->data.other_data; 2997 struct drm_connector *connector = closure->connector; 2998 struct edid *edid = closure->edid; 2999 int i; 3000 3001 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES)) 3002 return; 3003 3004 for (i = 0; i < 6; i++) { 3005 struct std_timing *std = &data->data.timings[i]; 3006 struct drm_display_mode *newmode; 3007 3008 newmode = drm_mode_std(connector, edid, std); 3009 if (newmode) { 3010 drm_mode_probed_add(connector, newmode); 3011 closure->modes++; 3012 } 3013 } 3014 } 3015 3016 /** 3017 * add_standard_modes - get std. modes from EDID and add them 3018 * @connector: connector to add mode(s) to 3019 * @edid: EDID block to scan 3020 * 3021 * Standard modes can be calculated using the appropriate standard (DMT, 3022 * GTF or CVT. Grab them from @edid and add them to the list. 3023 */ 3024 static int 3025 add_standard_modes(struct drm_connector *connector, struct edid *edid) 3026 { 3027 int i, modes = 0; 3028 struct detailed_mode_closure closure = { 3029 .connector = connector, 3030 .edid = edid, 3031 }; 3032 3033 for (i = 0; i < EDID_STD_TIMINGS; i++) { 3034 struct drm_display_mode *newmode; 3035 3036 newmode = drm_mode_std(connector, edid, 3037 &edid->standard_timings[i]); 3038 if (newmode) { 3039 drm_mode_probed_add(connector, newmode); 3040 modes++; 3041 } 3042 } 3043 3044 if (version_greater(edid, 1, 0)) 3045 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3046 &closure); 3047 3048 /* XXX should also look for standard codes in VTB blocks */ 3049 3050 return modes + closure.modes; 3051 } 3052 3053 static int drm_cvt_modes(struct drm_connector *connector, 3054 struct detailed_timing *timing) 3055 { 3056 int i, j, modes = 0; 3057 struct drm_display_mode *newmode; 3058 struct drm_device *dev = connector->dev; 3059 struct cvt_timing *cvt; 3060 const int rates[] = { 60, 85, 75, 60, 50 }; 3061 const u8 empty[3] = { 0, 0, 0 }; 3062 3063 for (i = 0; i < 4; i++) { 3064 int uninitialized_var(width), height; 3065 cvt = &(timing->data.other_data.data.cvt[i]); 3066 3067 if (!memcmp(cvt->code, empty, 3)) 3068 continue; 3069 3070 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3071 switch (cvt->code[1] & 0x0c) { 3072 case 0x00: 3073 width = height * 4 / 3; 3074 break; 3075 case 0x04: 3076 width = height * 16 / 9; 3077 break; 3078 case 0x08: 3079 width = height * 16 / 10; 3080 break; 3081 case 0x0c: 3082 width = height * 15 / 9; 3083 break; 3084 } 3085 3086 for (j = 1; j < 5; j++) { 3087 if (cvt->code[2] & (1 << j)) { 3088 newmode = drm_cvt_mode(dev, width, height, 3089 rates[j], j == 0, 3090 false, false); 3091 if (newmode) { 3092 drm_mode_probed_add(connector, newmode); 3093 modes++; 3094 } 3095 } 3096 } 3097 } 3098 3099 return modes; 3100 } 3101 3102 static void 3103 do_cvt_mode(struct detailed_timing *timing, void *c) 3104 { 3105 struct detailed_mode_closure *closure = c; 3106 3107 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE)) 3108 return; 3109 3110 closure->modes += drm_cvt_modes(closure->connector, timing); 3111 } 3112 3113 static int 3114 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3115 { 3116 struct detailed_mode_closure closure = { 3117 .connector = connector, 3118 .edid = edid, 3119 }; 3120 3121 if (version_greater(edid, 1, 2)) 3122 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3123 3124 /* XXX should also look for CVT codes in VTB blocks */ 3125 3126 return closure.modes; 3127 } 3128 3129 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3130 3131 static void 3132 do_detailed_mode(struct detailed_timing *timing, void *c) 3133 { 3134 struct detailed_mode_closure *closure = c; 3135 struct drm_display_mode *newmode; 3136 3137 if (!is_detailed_timing_descriptor((const u8 *)timing)) 3138 return; 3139 3140 newmode = drm_mode_detailed(closure->connector->dev, 3141 closure->edid, timing, 3142 closure->quirks); 3143 if (!newmode) 3144 return; 3145 3146 if (closure->preferred) 3147 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3148 3149 /* 3150 * Detailed modes are limited to 10kHz pixel clock resolution, 3151 * so fix up anything that looks like CEA/HDMI mode, but the clock 3152 * is just slightly off. 3153 */ 3154 fixup_detailed_cea_mode_clock(newmode); 3155 3156 drm_mode_probed_add(closure->connector, newmode); 3157 closure->modes++; 3158 closure->preferred = false; 3159 } 3160 3161 /* 3162 * add_detailed_modes - Add modes from detailed timings 3163 * @connector: attached connector 3164 * @edid: EDID block to scan 3165 * @quirks: quirks to apply 3166 */ 3167 static int 3168 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3169 u32 quirks) 3170 { 3171 struct detailed_mode_closure closure = { 3172 .connector = connector, 3173 .edid = edid, 3174 .preferred = true, 3175 .quirks = quirks, 3176 }; 3177 3178 if (closure.preferred && !version_greater(edid, 1, 3)) 3179 closure.preferred = 3180 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3181 3182 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3183 3184 return closure.modes; 3185 } 3186 3187 #define AUDIO_BLOCK 0x01 3188 #define VIDEO_BLOCK 0x02 3189 #define VENDOR_BLOCK 0x03 3190 #define SPEAKER_BLOCK 0x04 3191 #define HDR_STATIC_METADATA_BLOCK 0x6 3192 #define USE_EXTENDED_TAG 0x07 3193 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3194 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3195 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3196 #define EDID_BASIC_AUDIO (1 << 6) 3197 #define EDID_CEA_YCRCB444 (1 << 5) 3198 #define EDID_CEA_YCRCB422 (1 << 4) 3199 #define EDID_CEA_VCDB_QS (1 << 6) 3200 3201 /* 3202 * Search EDID for CEA extension block. 3203 */ 3204 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 3205 { 3206 u8 *edid_ext = NULL; 3207 int i; 3208 3209 /* No EDID or EDID extensions */ 3210 if (edid == NULL || edid->extensions == 0) 3211 return NULL; 3212 3213 /* Find CEA extension */ 3214 for (i = 0; i < edid->extensions; i++) { 3215 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 3216 if (edid_ext[0] == ext_id) 3217 break; 3218 } 3219 3220 if (i == edid->extensions) 3221 return NULL; 3222 3223 return edid_ext; 3224 } 3225 3226 3227 static u8 *drm_find_displayid_extension(const struct edid *edid) 3228 { 3229 return drm_find_edid_extension(edid, DISPLAYID_EXT); 3230 } 3231 3232 static u8 *drm_find_cea_extension(const struct edid *edid) 3233 { 3234 int ret; 3235 int idx = 1; 3236 int length = EDID_LENGTH; 3237 struct displayid_block *block; 3238 u8 *cea; 3239 u8 *displayid; 3240 3241 /* Look for a top level CEA extension block */ 3242 cea = drm_find_edid_extension(edid, CEA_EXT); 3243 if (cea) 3244 return cea; 3245 3246 /* CEA blocks can also be found embedded in a DisplayID block */ 3247 displayid = drm_find_displayid_extension(edid); 3248 if (!displayid) 3249 return NULL; 3250 3251 ret = validate_displayid(displayid, length, idx); 3252 if (ret) 3253 return NULL; 3254 3255 idx += sizeof(struct displayid_hdr); 3256 for_each_displayid_db(displayid, block, idx, length) { 3257 if (block->tag == DATA_BLOCK_CTA) { 3258 cea = (u8 *)block; 3259 break; 3260 } 3261 } 3262 3263 return cea; 3264 } 3265 3266 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3267 { 3268 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3269 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3270 3271 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3272 return &edid_cea_modes_1[vic - 1]; 3273 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3274 return &edid_cea_modes_193[vic - 193]; 3275 return NULL; 3276 } 3277 3278 static u8 cea_num_vics(void) 3279 { 3280 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3281 } 3282 3283 static u8 cea_next_vic(u8 vic) 3284 { 3285 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3286 vic = 193; 3287 return vic; 3288 } 3289 3290 /* 3291 * Calculate the alternate clock for the CEA mode 3292 * (60Hz vs. 59.94Hz etc.) 3293 */ 3294 static unsigned int 3295 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3296 { 3297 unsigned int clock = cea_mode->clock; 3298 3299 if (cea_mode->vrefresh % 6 != 0) 3300 return clock; 3301 3302 /* 3303 * edid_cea_modes contains the 59.94Hz 3304 * variant for 240 and 480 line modes, 3305 * and the 60Hz variant otherwise. 3306 */ 3307 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3308 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3309 else 3310 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3311 3312 return clock; 3313 } 3314 3315 static bool 3316 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3317 { 3318 /* 3319 * For certain VICs the spec allows the vertical 3320 * front porch to vary by one or two lines. 3321 * 3322 * cea_modes[] stores the variant with the shortest 3323 * vertical front porch. We can adjust the mode to 3324 * get the other variants by simply increasing the 3325 * vertical front porch length. 3326 */ 3327 #ifdef notyet 3328 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3329 cea_mode_for_vic(9)->vtotal != 262 || 3330 cea_mode_for_vic(12)->vtotal != 262 || 3331 cea_mode_for_vic(13)->vtotal != 262 || 3332 cea_mode_for_vic(23)->vtotal != 312 || 3333 cea_mode_for_vic(24)->vtotal != 312 || 3334 cea_mode_for_vic(27)->vtotal != 312 || 3335 cea_mode_for_vic(28)->vtotal != 312); 3336 #endif 3337 3338 if (((vic == 8 || vic == 9 || 3339 vic == 12 || vic == 13) && mode->vtotal < 263) || 3340 ((vic == 23 || vic == 24 || 3341 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3342 mode->vsync_start++; 3343 mode->vsync_end++; 3344 mode->vtotal++; 3345 3346 return true; 3347 } 3348 3349 return false; 3350 } 3351 3352 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3353 unsigned int clock_tolerance) 3354 { 3355 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3356 u8 vic; 3357 3358 if (!to_match->clock) 3359 return 0; 3360 3361 if (to_match->picture_aspect_ratio) 3362 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3363 3364 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3365 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3366 unsigned int clock1, clock2; 3367 3368 /* Check both 60Hz and 59.94Hz */ 3369 clock1 = cea_mode.clock; 3370 clock2 = cea_mode_alternate_clock(&cea_mode); 3371 3372 if (abs(to_match->clock - clock1) > clock_tolerance && 3373 abs(to_match->clock - clock2) > clock_tolerance) 3374 continue; 3375 3376 do { 3377 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3378 return vic; 3379 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3380 } 3381 3382 return 0; 3383 } 3384 3385 /** 3386 * drm_match_cea_mode - look for a CEA mode matching given mode 3387 * @to_match: display mode 3388 * 3389 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3390 * mode. 3391 */ 3392 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3393 { 3394 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3395 u8 vic; 3396 3397 if (!to_match->clock) 3398 return 0; 3399 3400 if (to_match->picture_aspect_ratio) 3401 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3402 3403 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3404 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3405 unsigned int clock1, clock2; 3406 3407 /* Check both 60Hz and 59.94Hz */ 3408 clock1 = cea_mode.clock; 3409 clock2 = cea_mode_alternate_clock(&cea_mode); 3410 3411 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3412 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3413 continue; 3414 3415 do { 3416 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3417 return vic; 3418 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3419 } 3420 3421 return 0; 3422 } 3423 EXPORT_SYMBOL(drm_match_cea_mode); 3424 3425 static bool drm_valid_cea_vic(u8 vic) 3426 { 3427 return cea_mode_for_vic(vic) != NULL; 3428 } 3429 3430 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3431 { 3432 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3433 3434 if (mode) 3435 return mode->picture_aspect_ratio; 3436 3437 return HDMI_PICTURE_ASPECT_NONE; 3438 } 3439 3440 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3441 { 3442 return edid_4k_modes[video_code].picture_aspect_ratio; 3443 } 3444 3445 /* 3446 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3447 * specific block). 3448 */ 3449 static unsigned int 3450 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3451 { 3452 return cea_mode_alternate_clock(hdmi_mode); 3453 } 3454 3455 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3456 unsigned int clock_tolerance) 3457 { 3458 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3459 u8 vic; 3460 3461 if (!to_match->clock) 3462 return 0; 3463 3464 if (to_match->picture_aspect_ratio) 3465 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3466 3467 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3468 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3469 unsigned int clock1, clock2; 3470 3471 /* Make sure to also match alternate clocks */ 3472 clock1 = hdmi_mode->clock; 3473 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3474 3475 if (abs(to_match->clock - clock1) > clock_tolerance && 3476 abs(to_match->clock - clock2) > clock_tolerance) 3477 continue; 3478 3479 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3480 return vic; 3481 } 3482 3483 return 0; 3484 } 3485 3486 /* 3487 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3488 * @to_match: display mode 3489 * 3490 * An HDMI mode is one defined in the HDMI vendor specific block. 3491 * 3492 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3493 */ 3494 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3495 { 3496 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3497 u8 vic; 3498 3499 if (!to_match->clock) 3500 return 0; 3501 3502 if (to_match->picture_aspect_ratio) 3503 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3504 3505 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3506 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3507 unsigned int clock1, clock2; 3508 3509 /* Make sure to also match alternate clocks */ 3510 clock1 = hdmi_mode->clock; 3511 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3512 3513 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3514 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3515 drm_mode_match(to_match, hdmi_mode, match_flags)) 3516 return vic; 3517 } 3518 return 0; 3519 } 3520 3521 static bool drm_valid_hdmi_vic(u8 vic) 3522 { 3523 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3524 } 3525 3526 static int 3527 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3528 { 3529 struct drm_device *dev = connector->dev; 3530 struct drm_display_mode *mode, *tmp; 3531 DRM_LIST_HEAD(list); 3532 int modes = 0; 3533 3534 /* Don't add CEA modes if the CEA extension block is missing */ 3535 if (!drm_find_cea_extension(edid)) 3536 return 0; 3537 3538 /* 3539 * Go through all probed modes and create a new mode 3540 * with the alternate clock for certain CEA modes. 3541 */ 3542 list_for_each_entry(mode, &connector->probed_modes, head) { 3543 const struct drm_display_mode *cea_mode = NULL; 3544 struct drm_display_mode *newmode; 3545 u8 vic = drm_match_cea_mode(mode); 3546 unsigned int clock1, clock2; 3547 3548 if (drm_valid_cea_vic(vic)) { 3549 cea_mode = cea_mode_for_vic(vic); 3550 clock2 = cea_mode_alternate_clock(cea_mode); 3551 } else { 3552 vic = drm_match_hdmi_mode(mode); 3553 if (drm_valid_hdmi_vic(vic)) { 3554 cea_mode = &edid_4k_modes[vic]; 3555 clock2 = hdmi_mode_alternate_clock(cea_mode); 3556 } 3557 } 3558 3559 if (!cea_mode) 3560 continue; 3561 3562 clock1 = cea_mode->clock; 3563 3564 if (clock1 == clock2) 3565 continue; 3566 3567 if (mode->clock != clock1 && mode->clock != clock2) 3568 continue; 3569 3570 newmode = drm_mode_duplicate(dev, cea_mode); 3571 if (!newmode) 3572 continue; 3573 3574 /* Carry over the stereo flags */ 3575 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3576 3577 /* 3578 * The current mode could be either variant. Make 3579 * sure to pick the "other" clock for the new mode. 3580 */ 3581 if (mode->clock != clock1) 3582 newmode->clock = clock1; 3583 else 3584 newmode->clock = clock2; 3585 3586 list_add_tail(&newmode->head, &list); 3587 } 3588 3589 list_for_each_entry_safe(mode, tmp, &list, head) { 3590 list_del(&mode->head); 3591 drm_mode_probed_add(connector, mode); 3592 modes++; 3593 } 3594 3595 return modes; 3596 } 3597 3598 static u8 svd_to_vic(u8 svd) 3599 { 3600 /* 0-6 bit vic, 7th bit native mode indicator */ 3601 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3602 return svd & 127; 3603 3604 return svd; 3605 } 3606 3607 static struct drm_display_mode * 3608 drm_display_mode_from_vic_index(struct drm_connector *connector, 3609 const u8 *video_db, u8 video_len, 3610 u8 video_index) 3611 { 3612 struct drm_device *dev = connector->dev; 3613 struct drm_display_mode *newmode; 3614 u8 vic; 3615 3616 if (video_db == NULL || video_index >= video_len) 3617 return NULL; 3618 3619 /* CEA modes are numbered 1..127 */ 3620 vic = svd_to_vic(video_db[video_index]); 3621 if (!drm_valid_cea_vic(vic)) 3622 return NULL; 3623 3624 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3625 if (!newmode) 3626 return NULL; 3627 3628 newmode->vrefresh = 0; 3629 3630 return newmode; 3631 } 3632 3633 /* 3634 * do_y420vdb_modes - Parse YCBCR 420 only modes 3635 * @connector: connector corresponding to the HDMI sink 3636 * @svds: start of the data block of CEA YCBCR 420 VDB 3637 * @len: length of the CEA YCBCR 420 VDB 3638 * 3639 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3640 * which contains modes which can be supported in YCBCR 420 3641 * output format only. 3642 */ 3643 static int do_y420vdb_modes(struct drm_connector *connector, 3644 const u8 *svds, u8 svds_len) 3645 { 3646 int modes = 0, i; 3647 struct drm_device *dev = connector->dev; 3648 struct drm_display_info *info = &connector->display_info; 3649 struct drm_hdmi_info *hdmi = &info->hdmi; 3650 3651 for (i = 0; i < svds_len; i++) { 3652 u8 vic = svd_to_vic(svds[i]); 3653 struct drm_display_mode *newmode; 3654 3655 if (!drm_valid_cea_vic(vic)) 3656 continue; 3657 3658 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3659 if (!newmode) 3660 break; 3661 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3662 drm_mode_probed_add(connector, newmode); 3663 modes++; 3664 } 3665 3666 if (modes > 0) 3667 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3668 return modes; 3669 } 3670 3671 /* 3672 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3673 * @connector: connector corresponding to the HDMI sink 3674 * @vic: CEA vic for the video mode to be added in the map 3675 * 3676 * Makes an entry for a videomode in the YCBCR 420 bitmap 3677 */ 3678 static void 3679 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3680 { 3681 u8 vic = svd_to_vic(svd); 3682 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3683 3684 if (!drm_valid_cea_vic(vic)) 3685 return; 3686 3687 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3688 } 3689 3690 static int 3691 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3692 { 3693 int i, modes = 0; 3694 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3695 3696 for (i = 0; i < len; i++) { 3697 struct drm_display_mode *mode; 3698 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3699 if (mode) { 3700 /* 3701 * YCBCR420 capability block contains a bitmap which 3702 * gives the index of CEA modes from CEA VDB, which 3703 * can support YCBCR 420 sampling output also (apart 3704 * from RGB/YCBCR444 etc). 3705 * For example, if the bit 0 in bitmap is set, 3706 * first mode in VDB can support YCBCR420 output too. 3707 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3708 */ 3709 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3710 drm_add_cmdb_modes(connector, db[i]); 3711 3712 drm_mode_probed_add(connector, mode); 3713 modes++; 3714 } 3715 } 3716 3717 return modes; 3718 } 3719 3720 struct stereo_mandatory_mode { 3721 int width, height, vrefresh; 3722 unsigned int flags; 3723 }; 3724 3725 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3726 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3727 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3728 { 1920, 1080, 50, 3729 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3730 { 1920, 1080, 60, 3731 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3732 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3733 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3734 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3735 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3736 }; 3737 3738 static bool 3739 stereo_match_mandatory(const struct drm_display_mode *mode, 3740 const struct stereo_mandatory_mode *stereo_mode) 3741 { 3742 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3743 3744 return mode->hdisplay == stereo_mode->width && 3745 mode->vdisplay == stereo_mode->height && 3746 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3747 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3748 } 3749 3750 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3751 { 3752 struct drm_device *dev = connector->dev; 3753 const struct drm_display_mode *mode; 3754 struct list_head stereo_modes; 3755 int modes = 0, i; 3756 3757 INIT_LIST_HEAD(&stereo_modes); 3758 3759 list_for_each_entry(mode, &connector->probed_modes, head) { 3760 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3761 const struct stereo_mandatory_mode *mandatory; 3762 struct drm_display_mode *new_mode; 3763 3764 if (!stereo_match_mandatory(mode, 3765 &stereo_mandatory_modes[i])) 3766 continue; 3767 3768 mandatory = &stereo_mandatory_modes[i]; 3769 new_mode = drm_mode_duplicate(dev, mode); 3770 if (!new_mode) 3771 continue; 3772 3773 new_mode->flags |= mandatory->flags; 3774 list_add_tail(&new_mode->head, &stereo_modes); 3775 modes++; 3776 } 3777 } 3778 3779 list_splice_tail(&stereo_modes, &connector->probed_modes); 3780 3781 return modes; 3782 } 3783 3784 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3785 { 3786 struct drm_device *dev = connector->dev; 3787 struct drm_display_mode *newmode; 3788 3789 if (!drm_valid_hdmi_vic(vic)) { 3790 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3791 return 0; 3792 } 3793 3794 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3795 if (!newmode) 3796 return 0; 3797 3798 drm_mode_probed_add(connector, newmode); 3799 3800 return 1; 3801 } 3802 3803 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3804 const u8 *video_db, u8 video_len, u8 video_index) 3805 { 3806 struct drm_display_mode *newmode; 3807 int modes = 0; 3808 3809 if (structure & (1 << 0)) { 3810 newmode = drm_display_mode_from_vic_index(connector, video_db, 3811 video_len, 3812 video_index); 3813 if (newmode) { 3814 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3815 drm_mode_probed_add(connector, newmode); 3816 modes++; 3817 } 3818 } 3819 if (structure & (1 << 6)) { 3820 newmode = drm_display_mode_from_vic_index(connector, video_db, 3821 video_len, 3822 video_index); 3823 if (newmode) { 3824 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3825 drm_mode_probed_add(connector, newmode); 3826 modes++; 3827 } 3828 } 3829 if (structure & (1 << 8)) { 3830 newmode = drm_display_mode_from_vic_index(connector, video_db, 3831 video_len, 3832 video_index); 3833 if (newmode) { 3834 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3835 drm_mode_probed_add(connector, newmode); 3836 modes++; 3837 } 3838 } 3839 3840 return modes; 3841 } 3842 3843 /* 3844 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3845 * @connector: connector corresponding to the HDMI sink 3846 * @db: start of the CEA vendor specific block 3847 * @len: length of the CEA block payload, ie. one can access up to db[len] 3848 * 3849 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3850 * also adds the stereo 3d modes when applicable. 3851 */ 3852 static int 3853 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3854 const u8 *video_db, u8 video_len) 3855 { 3856 struct drm_display_info *info = &connector->display_info; 3857 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3858 u8 vic_len, hdmi_3d_len = 0; 3859 u16 mask; 3860 u16 structure_all; 3861 3862 if (len < 8) 3863 goto out; 3864 3865 /* no HDMI_Video_Present */ 3866 if (!(db[8] & (1 << 5))) 3867 goto out; 3868 3869 /* Latency_Fields_Present */ 3870 if (db[8] & (1 << 7)) 3871 offset += 2; 3872 3873 /* I_Latency_Fields_Present */ 3874 if (db[8] & (1 << 6)) 3875 offset += 2; 3876 3877 /* the declared length is not long enough for the 2 first bytes 3878 * of additional video format capabilities */ 3879 if (len < (8 + offset + 2)) 3880 goto out; 3881 3882 /* 3D_Present */ 3883 offset++; 3884 if (db[8 + offset] & (1 << 7)) { 3885 modes += add_hdmi_mandatory_stereo_modes(connector); 3886 3887 /* 3D_Multi_present */ 3888 multi_present = (db[8 + offset] & 0x60) >> 5; 3889 } 3890 3891 offset++; 3892 vic_len = db[8 + offset] >> 5; 3893 hdmi_3d_len = db[8 + offset] & 0x1f; 3894 3895 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3896 u8 vic; 3897 3898 vic = db[9 + offset + i]; 3899 modes += add_hdmi_mode(connector, vic); 3900 } 3901 offset += 1 + vic_len; 3902 3903 if (multi_present == 1) 3904 multi_len = 2; 3905 else if (multi_present == 2) 3906 multi_len = 4; 3907 else 3908 multi_len = 0; 3909 3910 if (len < (8 + offset + hdmi_3d_len - 1)) 3911 goto out; 3912 3913 if (hdmi_3d_len < multi_len) 3914 goto out; 3915 3916 if (multi_present == 1 || multi_present == 2) { 3917 /* 3D_Structure_ALL */ 3918 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3919 3920 /* check if 3D_MASK is present */ 3921 if (multi_present == 2) 3922 mask = (db[10 + offset] << 8) | db[11 + offset]; 3923 else 3924 mask = 0xffff; 3925 3926 for (i = 0; i < 16; i++) { 3927 if (mask & (1 << i)) 3928 modes += add_3d_struct_modes(connector, 3929 structure_all, 3930 video_db, 3931 video_len, i); 3932 } 3933 } 3934 3935 offset += multi_len; 3936 3937 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3938 int vic_index; 3939 struct drm_display_mode *newmode = NULL; 3940 unsigned int newflag = 0; 3941 bool detail_present; 3942 3943 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3944 3945 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3946 break; 3947 3948 /* 2D_VIC_order_X */ 3949 vic_index = db[8 + offset + i] >> 4; 3950 3951 /* 3D_Structure_X */ 3952 switch (db[8 + offset + i] & 0x0f) { 3953 case 0: 3954 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3955 break; 3956 case 6: 3957 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3958 break; 3959 case 8: 3960 /* 3D_Detail_X */ 3961 if ((db[9 + offset + i] >> 4) == 1) 3962 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3963 break; 3964 } 3965 3966 if (newflag != 0) { 3967 newmode = drm_display_mode_from_vic_index(connector, 3968 video_db, 3969 video_len, 3970 vic_index); 3971 3972 if (newmode) { 3973 newmode->flags |= newflag; 3974 drm_mode_probed_add(connector, newmode); 3975 modes++; 3976 } 3977 } 3978 3979 if (detail_present) 3980 i++; 3981 } 3982 3983 out: 3984 if (modes > 0) 3985 info->has_hdmi_infoframe = true; 3986 return modes; 3987 } 3988 3989 static int 3990 cea_db_payload_len(const u8 *db) 3991 { 3992 return db[0] & 0x1f; 3993 } 3994 3995 static int 3996 cea_db_extended_tag(const u8 *db) 3997 { 3998 return db[1]; 3999 } 4000 4001 static int 4002 cea_db_tag(const u8 *db) 4003 { 4004 return db[0] >> 5; 4005 } 4006 4007 static int 4008 cea_revision(const u8 *cea) 4009 { 4010 /* 4011 * FIXME is this correct for the DispID variant? 4012 * The DispID spec doesn't really specify whether 4013 * this is the revision of the CEA extension or 4014 * the DispID CEA data block. And the only value 4015 * given as an example is 0. 4016 */ 4017 return cea[1]; 4018 } 4019 4020 static int 4021 cea_db_offsets(const u8 *cea, int *start, int *end) 4022 { 4023 /* DisplayID CTA extension blocks and top-level CEA EDID 4024 * block header definitions differ in the following bytes: 4025 * 1) Byte 2 of the header specifies length differently, 4026 * 2) Byte 3 is only present in the CEA top level block. 4027 * 4028 * The different definitions for byte 2 follow. 4029 * 4030 * DisplayID CTA extension block defines byte 2 as: 4031 * Number of payload bytes 4032 * 4033 * CEA EDID block defines byte 2 as: 4034 * Byte number (decimal) within this block where the 18-byte 4035 * DTDs begin. If no non-DTD data is present in this extension 4036 * block, the value should be set to 04h (the byte after next). 4037 * If set to 00h, there are no DTDs present in this block and 4038 * no non-DTD data. 4039 */ 4040 if (cea[0] == DATA_BLOCK_CTA) { 4041 /* 4042 * for_each_displayid_db() has already verified 4043 * that these stay within expected bounds. 4044 */ 4045 *start = 3; 4046 *end = *start + cea[2]; 4047 } else if (cea[0] == CEA_EXT) { 4048 /* Data block offset in CEA extension block */ 4049 *start = 4; 4050 *end = cea[2]; 4051 if (*end == 0) 4052 *end = 127; 4053 if (*end < 4 || *end > 127) 4054 return -ERANGE; 4055 } else { 4056 return -EOPNOTSUPP; 4057 } 4058 4059 return 0; 4060 } 4061 4062 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4063 { 4064 int hdmi_id; 4065 4066 if (cea_db_tag(db) != VENDOR_BLOCK) 4067 return false; 4068 4069 if (cea_db_payload_len(db) < 5) 4070 return false; 4071 4072 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4073 4074 return hdmi_id == HDMI_IEEE_OUI; 4075 } 4076 4077 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4078 { 4079 unsigned int oui; 4080 4081 if (cea_db_tag(db) != VENDOR_BLOCK) 4082 return false; 4083 4084 if (cea_db_payload_len(db) < 7) 4085 return false; 4086 4087 oui = db[3] << 16 | db[2] << 8 | db[1]; 4088 4089 return oui == HDMI_FORUM_IEEE_OUI; 4090 } 4091 4092 static bool cea_db_is_vcdb(const u8 *db) 4093 { 4094 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4095 return false; 4096 4097 if (cea_db_payload_len(db) != 2) 4098 return false; 4099 4100 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4101 return false; 4102 4103 return true; 4104 } 4105 4106 static bool cea_db_is_y420cmdb(const u8 *db) 4107 { 4108 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4109 return false; 4110 4111 if (!cea_db_payload_len(db)) 4112 return false; 4113 4114 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4115 return false; 4116 4117 return true; 4118 } 4119 4120 static bool cea_db_is_y420vdb(const u8 *db) 4121 { 4122 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4123 return false; 4124 4125 if (!cea_db_payload_len(db)) 4126 return false; 4127 4128 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4129 return false; 4130 4131 return true; 4132 } 4133 4134 #define for_each_cea_db(cea, i, start, end) \ 4135 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4136 4137 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4138 const u8 *db) 4139 { 4140 struct drm_display_info *info = &connector->display_info; 4141 struct drm_hdmi_info *hdmi = &info->hdmi; 4142 u8 map_len = cea_db_payload_len(db) - 1; 4143 u8 count; 4144 u64 map = 0; 4145 4146 if (map_len == 0) { 4147 /* All CEA modes support ycbcr420 sampling also.*/ 4148 hdmi->y420_cmdb_map = U64_MAX; 4149 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4150 return; 4151 } 4152 4153 /* 4154 * This map indicates which of the existing CEA block modes 4155 * from VDB can support YCBCR420 output too. So if bit=0 is 4156 * set, first mode from VDB can support YCBCR420 output too. 4157 * We will parse and keep this map, before parsing VDB itself 4158 * to avoid going through the same block again and again. 4159 * 4160 * Spec is not clear about max possible size of this block. 4161 * Clamping max bitmap block size at 8 bytes. Every byte can 4162 * address 8 CEA modes, in this way this map can address 4163 * 8*8 = first 64 SVDs. 4164 */ 4165 if (WARN_ON_ONCE(map_len > 8)) 4166 map_len = 8; 4167 4168 for (count = 0; count < map_len; count++) 4169 map |= (u64)db[2 + count] << (8 * count); 4170 4171 if (map) 4172 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4173 4174 hdmi->y420_cmdb_map = map; 4175 } 4176 4177 static int 4178 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4179 { 4180 const u8 *cea = drm_find_cea_extension(edid); 4181 const u8 *db, *hdmi = NULL, *video = NULL; 4182 u8 dbl, hdmi_len, video_len = 0; 4183 int modes = 0; 4184 4185 if (cea && cea_revision(cea) >= 3) { 4186 int i, start, end; 4187 4188 if (cea_db_offsets(cea, &start, &end)) 4189 return 0; 4190 4191 for_each_cea_db(cea, i, start, end) { 4192 db = &cea[i]; 4193 dbl = cea_db_payload_len(db); 4194 4195 if (cea_db_tag(db) == VIDEO_BLOCK) { 4196 video = db + 1; 4197 video_len = dbl; 4198 modes += do_cea_modes(connector, video, dbl); 4199 } else if (cea_db_is_hdmi_vsdb(db)) { 4200 hdmi = db; 4201 hdmi_len = dbl; 4202 } else if (cea_db_is_y420vdb(db)) { 4203 const u8 *vdb420 = &db[2]; 4204 4205 /* Add 4:2:0(only) modes present in EDID */ 4206 modes += do_y420vdb_modes(connector, 4207 vdb420, 4208 dbl - 1); 4209 } 4210 } 4211 } 4212 4213 /* 4214 * We parse the HDMI VSDB after having added the cea modes as we will 4215 * be patching their flags when the sink supports stereo 3D. 4216 */ 4217 if (hdmi) 4218 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4219 video_len); 4220 4221 return modes; 4222 } 4223 4224 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4225 { 4226 const struct drm_display_mode *cea_mode; 4227 int clock1, clock2, clock; 4228 u8 vic; 4229 const char *type; 4230 4231 /* 4232 * allow 5kHz clock difference either way to account for 4233 * the 10kHz clock resolution limit of detailed timings. 4234 */ 4235 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4236 if (drm_valid_cea_vic(vic)) { 4237 type = "CEA"; 4238 cea_mode = cea_mode_for_vic(vic); 4239 clock1 = cea_mode->clock; 4240 clock2 = cea_mode_alternate_clock(cea_mode); 4241 } else { 4242 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4243 if (drm_valid_hdmi_vic(vic)) { 4244 type = "HDMI"; 4245 cea_mode = &edid_4k_modes[vic]; 4246 clock1 = cea_mode->clock; 4247 clock2 = hdmi_mode_alternate_clock(cea_mode); 4248 } else { 4249 return; 4250 } 4251 } 4252 4253 /* pick whichever is closest */ 4254 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4255 clock = clock1; 4256 else 4257 clock = clock2; 4258 4259 if (mode->clock == clock) 4260 return; 4261 4262 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4263 type, vic, mode->clock, clock); 4264 mode->clock = clock; 4265 } 4266 4267 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4268 { 4269 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4270 return false; 4271 4272 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4273 return false; 4274 4275 if (cea_db_payload_len(db) < 3) 4276 return false; 4277 4278 return true; 4279 } 4280 4281 static uint8_t eotf_supported(const u8 *edid_ext) 4282 { 4283 return edid_ext[2] & 4284 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4285 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4286 BIT(HDMI_EOTF_SMPTE_ST2084) | 4287 BIT(HDMI_EOTF_BT_2100_HLG)); 4288 } 4289 4290 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4291 { 4292 return edid_ext[3] & 4293 BIT(HDMI_STATIC_METADATA_TYPE1); 4294 } 4295 4296 static void 4297 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4298 { 4299 u16 len; 4300 4301 len = cea_db_payload_len(db); 4302 4303 connector->hdr_sink_metadata.hdmi_type1.eotf = 4304 eotf_supported(db); 4305 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4306 hdr_metadata_type(db); 4307 4308 if (len >= 4) 4309 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4310 if (len >= 5) 4311 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4312 if (len >= 6) 4313 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4314 } 4315 4316 static void 4317 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4318 { 4319 u8 len = cea_db_payload_len(db); 4320 4321 if (len >= 6 && (db[6] & (1 << 7))) 4322 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4323 if (len >= 8) { 4324 connector->latency_present[0] = db[8] >> 7; 4325 connector->latency_present[1] = (db[8] >> 6) & 1; 4326 } 4327 if (len >= 9) 4328 connector->video_latency[0] = db[9]; 4329 if (len >= 10) 4330 connector->audio_latency[0] = db[10]; 4331 if (len >= 11) 4332 connector->video_latency[1] = db[11]; 4333 if (len >= 12) 4334 connector->audio_latency[1] = db[12]; 4335 4336 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4337 "video latency %d %d, " 4338 "audio latency %d %d\n", 4339 connector->latency_present[0], 4340 connector->latency_present[1], 4341 connector->video_latency[0], 4342 connector->video_latency[1], 4343 connector->audio_latency[0], 4344 connector->audio_latency[1]); 4345 } 4346 4347 static void 4348 monitor_name(struct detailed_timing *t, void *data) 4349 { 4350 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME)) 4351 return; 4352 4353 *(u8 **)data = t->data.other_data.data.str.str; 4354 } 4355 4356 static int get_monitor_name(struct edid *edid, char name[13]) 4357 { 4358 char *edid_name = NULL; 4359 int mnl; 4360 4361 if (!edid || !name) 4362 return 0; 4363 4364 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4365 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4366 if (edid_name[mnl] == 0x0a) 4367 break; 4368 4369 name[mnl] = edid_name[mnl]; 4370 } 4371 4372 return mnl; 4373 } 4374 4375 /** 4376 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4377 * @edid: monitor EDID information 4378 * @name: pointer to a character array to hold the name of the monitor 4379 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4380 * 4381 */ 4382 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4383 { 4384 int name_length; 4385 char buf[13]; 4386 4387 if (bufsize <= 0) 4388 return; 4389 4390 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4391 memcpy(name, buf, name_length); 4392 name[name_length] = '\0'; 4393 } 4394 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4395 4396 static void clear_eld(struct drm_connector *connector) 4397 { 4398 memset(connector->eld, 0, sizeof(connector->eld)); 4399 4400 connector->latency_present[0] = false; 4401 connector->latency_present[1] = false; 4402 connector->video_latency[0] = 0; 4403 connector->audio_latency[0] = 0; 4404 connector->video_latency[1] = 0; 4405 connector->audio_latency[1] = 0; 4406 } 4407 4408 /* 4409 * drm_edid_to_eld - build ELD from EDID 4410 * @connector: connector corresponding to the HDMI/DP sink 4411 * @edid: EDID to parse 4412 * 4413 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4414 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4415 */ 4416 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4417 { 4418 uint8_t *eld = connector->eld; 4419 u8 *cea; 4420 u8 *db; 4421 int total_sad_count = 0; 4422 int mnl; 4423 int dbl; 4424 4425 clear_eld(connector); 4426 4427 if (!edid) 4428 return; 4429 4430 cea = drm_find_cea_extension(edid); 4431 if (!cea) { 4432 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4433 return; 4434 } 4435 4436 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4437 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4438 4439 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4440 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4441 4442 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4443 4444 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4445 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4446 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4447 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4448 4449 if (cea_revision(cea) >= 3) { 4450 int i, start, end; 4451 int sad_count; 4452 4453 if (cea_db_offsets(cea, &start, &end)) { 4454 start = 0; 4455 end = 0; 4456 } 4457 4458 for_each_cea_db(cea, i, start, end) { 4459 db = &cea[i]; 4460 dbl = cea_db_payload_len(db); 4461 4462 switch (cea_db_tag(db)) { 4463 case AUDIO_BLOCK: 4464 /* Audio Data Block, contains SADs */ 4465 sad_count = min(dbl / 3, 15 - total_sad_count); 4466 if (sad_count >= 1) 4467 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4468 &db[1], sad_count * 3); 4469 total_sad_count += sad_count; 4470 break; 4471 case SPEAKER_BLOCK: 4472 /* Speaker Allocation Data Block */ 4473 if (dbl >= 1) 4474 eld[DRM_ELD_SPEAKER] = db[1]; 4475 break; 4476 case VENDOR_BLOCK: 4477 /* HDMI Vendor-Specific Data Block */ 4478 if (cea_db_is_hdmi_vsdb(db)) 4479 drm_parse_hdmi_vsdb_audio(connector, db); 4480 break; 4481 default: 4482 break; 4483 } 4484 } 4485 } 4486 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4487 4488 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4489 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4490 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4491 else 4492 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4493 4494 eld[DRM_ELD_BASELINE_ELD_LEN] = 4495 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4496 4497 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4498 drm_eld_size(eld), total_sad_count); 4499 } 4500 4501 /** 4502 * drm_edid_to_sad - extracts SADs from EDID 4503 * @edid: EDID to parse 4504 * @sads: pointer that will be set to the extracted SADs 4505 * 4506 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4507 * 4508 * Note: The returned pointer needs to be freed using kfree(). 4509 * 4510 * Return: The number of found SADs or negative number on error. 4511 */ 4512 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4513 { 4514 int count = 0; 4515 int i, start, end, dbl; 4516 u8 *cea; 4517 4518 cea = drm_find_cea_extension(edid); 4519 if (!cea) { 4520 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4521 return 0; 4522 } 4523 4524 if (cea_revision(cea) < 3) { 4525 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4526 return 0; 4527 } 4528 4529 if (cea_db_offsets(cea, &start, &end)) { 4530 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4531 return -EPROTO; 4532 } 4533 4534 for_each_cea_db(cea, i, start, end) { 4535 u8 *db = &cea[i]; 4536 4537 if (cea_db_tag(db) == AUDIO_BLOCK) { 4538 int j; 4539 dbl = cea_db_payload_len(db); 4540 4541 count = dbl / 3; /* SAD is 3B */ 4542 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4543 if (!*sads) 4544 return -ENOMEM; 4545 for (j = 0; j < count; j++) { 4546 u8 *sad = &db[1 + j * 3]; 4547 4548 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4549 (*sads)[j].channels = sad[0] & 0x7; 4550 (*sads)[j].freq = sad[1] & 0x7F; 4551 (*sads)[j].byte2 = sad[2]; 4552 } 4553 break; 4554 } 4555 } 4556 4557 return count; 4558 } 4559 EXPORT_SYMBOL(drm_edid_to_sad); 4560 4561 /** 4562 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4563 * @edid: EDID to parse 4564 * @sadb: pointer to the speaker block 4565 * 4566 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4567 * 4568 * Note: The returned pointer needs to be freed using kfree(). 4569 * 4570 * Return: The number of found Speaker Allocation Blocks or negative number on 4571 * error. 4572 */ 4573 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4574 { 4575 int count = 0; 4576 int i, start, end, dbl; 4577 const u8 *cea; 4578 4579 cea = drm_find_cea_extension(edid); 4580 if (!cea) { 4581 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4582 return 0; 4583 } 4584 4585 if (cea_revision(cea) < 3) { 4586 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4587 return 0; 4588 } 4589 4590 if (cea_db_offsets(cea, &start, &end)) { 4591 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4592 return -EPROTO; 4593 } 4594 4595 for_each_cea_db(cea, i, start, end) { 4596 const u8 *db = &cea[i]; 4597 4598 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4599 dbl = cea_db_payload_len(db); 4600 4601 /* Speaker Allocation Data Block */ 4602 if (dbl == 3) { 4603 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4604 if (!*sadb) 4605 return -ENOMEM; 4606 count = dbl; 4607 break; 4608 } 4609 } 4610 } 4611 4612 return count; 4613 } 4614 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4615 4616 /** 4617 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4618 * @connector: connector associated with the HDMI/DP sink 4619 * @mode: the display mode 4620 * 4621 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4622 * the sink doesn't support audio or video. 4623 */ 4624 int drm_av_sync_delay(struct drm_connector *connector, 4625 const struct drm_display_mode *mode) 4626 { 4627 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4628 int a, v; 4629 4630 if (!connector->latency_present[0]) 4631 return 0; 4632 if (!connector->latency_present[1]) 4633 i = 0; 4634 4635 a = connector->audio_latency[i]; 4636 v = connector->video_latency[i]; 4637 4638 /* 4639 * HDMI/DP sink doesn't support audio or video? 4640 */ 4641 if (a == 255 || v == 255) 4642 return 0; 4643 4644 /* 4645 * Convert raw EDID values to millisecond. 4646 * Treat unknown latency as 0ms. 4647 */ 4648 if (a) 4649 a = min(2 * (a - 1), 500); 4650 if (v) 4651 v = min(2 * (v - 1), 500); 4652 4653 return max(v - a, 0); 4654 } 4655 EXPORT_SYMBOL(drm_av_sync_delay); 4656 4657 /** 4658 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4659 * @edid: monitor EDID information 4660 * 4661 * Parse the CEA extension according to CEA-861-B. 4662 * 4663 * Drivers that have added the modes parsed from EDID to drm_display_info 4664 * should use &drm_display_info.is_hdmi instead of calling this function. 4665 * 4666 * Return: True if the monitor is HDMI, false if not or unknown. 4667 */ 4668 bool drm_detect_hdmi_monitor(struct edid *edid) 4669 { 4670 u8 *edid_ext; 4671 int i; 4672 int start_offset, end_offset; 4673 4674 edid_ext = drm_find_cea_extension(edid); 4675 if (!edid_ext) 4676 return false; 4677 4678 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4679 return false; 4680 4681 /* 4682 * Because HDMI identifier is in Vendor Specific Block, 4683 * search it from all data blocks of CEA extension. 4684 */ 4685 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4686 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4687 return true; 4688 } 4689 4690 return false; 4691 } 4692 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4693 4694 /** 4695 * drm_detect_monitor_audio - check monitor audio capability 4696 * @edid: EDID block to scan 4697 * 4698 * Monitor should have CEA extension block. 4699 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4700 * audio' only. If there is any audio extension block and supported 4701 * audio format, assume at least 'basic audio' support, even if 'basic 4702 * audio' is not defined in EDID. 4703 * 4704 * Return: True if the monitor supports audio, false otherwise. 4705 */ 4706 bool drm_detect_monitor_audio(struct edid *edid) 4707 { 4708 u8 *edid_ext; 4709 int i, j; 4710 bool has_audio = false; 4711 int start_offset, end_offset; 4712 4713 edid_ext = drm_find_cea_extension(edid); 4714 if (!edid_ext) 4715 goto end; 4716 4717 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4718 4719 if (has_audio) { 4720 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4721 goto end; 4722 } 4723 4724 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4725 goto end; 4726 4727 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4728 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4729 has_audio = true; 4730 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4731 DRM_DEBUG_KMS("CEA audio format %d\n", 4732 (edid_ext[i + j] >> 3) & 0xf); 4733 goto end; 4734 } 4735 } 4736 end: 4737 return has_audio; 4738 } 4739 EXPORT_SYMBOL(drm_detect_monitor_audio); 4740 4741 4742 /** 4743 * drm_default_rgb_quant_range - default RGB quantization range 4744 * @mode: display mode 4745 * 4746 * Determine the default RGB quantization range for the mode, 4747 * as specified in CEA-861. 4748 * 4749 * Return: The default RGB quantization range for the mode 4750 */ 4751 enum hdmi_quantization_range 4752 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4753 { 4754 /* All CEA modes other than VIC 1 use limited quantization range. */ 4755 return drm_match_cea_mode(mode) > 1 ? 4756 HDMI_QUANTIZATION_RANGE_LIMITED : 4757 HDMI_QUANTIZATION_RANGE_FULL; 4758 } 4759 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4760 4761 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4762 { 4763 struct drm_display_info *info = &connector->display_info; 4764 4765 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4766 4767 if (db[2] & EDID_CEA_VCDB_QS) 4768 info->rgb_quant_range_selectable = true; 4769 } 4770 4771 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4772 const u8 *db) 4773 { 4774 u8 dc_mask; 4775 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4776 4777 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4778 hdmi->y420_dc_modes = dc_mask; 4779 } 4780 4781 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4782 const u8 *hf_vsdb) 4783 { 4784 struct drm_display_info *display = &connector->display_info; 4785 struct drm_hdmi_info *hdmi = &display->hdmi; 4786 4787 display->has_hdmi_infoframe = true; 4788 4789 if (hf_vsdb[6] & 0x80) { 4790 hdmi->scdc.supported = true; 4791 if (hf_vsdb[6] & 0x40) 4792 hdmi->scdc.read_request = true; 4793 } 4794 4795 /* 4796 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4797 * And as per the spec, three factors confirm this: 4798 * * Availability of a HF-VSDB block in EDID (check) 4799 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4800 * * SCDC support available (let's check) 4801 * Lets check it out. 4802 */ 4803 4804 if (hf_vsdb[5]) { 4805 /* max clock is 5000 KHz times block value */ 4806 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4807 struct drm_scdc *scdc = &hdmi->scdc; 4808 4809 if (max_tmds_clock > 340000) { 4810 display->max_tmds_clock = max_tmds_clock; 4811 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4812 display->max_tmds_clock); 4813 } 4814 4815 if (scdc->supported) { 4816 scdc->scrambling.supported = true; 4817 4818 /* Few sinks support scrambling for clocks < 340M */ 4819 if ((hf_vsdb[6] & 0x8)) 4820 scdc->scrambling.low_rates = true; 4821 } 4822 } 4823 4824 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4825 } 4826 4827 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4828 const u8 *hdmi) 4829 { 4830 struct drm_display_info *info = &connector->display_info; 4831 unsigned int dc_bpc = 0; 4832 4833 /* HDMI supports at least 8 bpc */ 4834 info->bpc = 8; 4835 4836 if (cea_db_payload_len(hdmi) < 6) 4837 return; 4838 4839 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4840 dc_bpc = 10; 4841 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4842 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4843 connector->name); 4844 } 4845 4846 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4847 dc_bpc = 12; 4848 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4849 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4850 connector->name); 4851 } 4852 4853 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4854 dc_bpc = 16; 4855 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4856 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4857 connector->name); 4858 } 4859 4860 if (dc_bpc == 0) { 4861 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4862 connector->name); 4863 return; 4864 } 4865 4866 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4867 connector->name, dc_bpc); 4868 info->bpc = dc_bpc; 4869 4870 /* 4871 * Deep color support mandates RGB444 support for all video 4872 * modes and forbids YCRCB422 support for all video modes per 4873 * HDMI 1.3 spec. 4874 */ 4875 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4876 4877 /* YCRCB444 is optional according to spec. */ 4878 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4879 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4880 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4881 connector->name); 4882 } 4883 4884 /* 4885 * Spec says that if any deep color mode is supported at all, 4886 * then deep color 36 bit must be supported. 4887 */ 4888 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4889 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4890 connector->name); 4891 } 4892 } 4893 4894 static void 4895 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4896 { 4897 struct drm_display_info *info = &connector->display_info; 4898 u8 len = cea_db_payload_len(db); 4899 4900 info->is_hdmi = true; 4901 4902 if (len >= 6) 4903 info->dvi_dual = db[6] & 1; 4904 if (len >= 7) 4905 info->max_tmds_clock = db[7] * 5000; 4906 4907 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4908 "max TMDS clock %d kHz\n", 4909 info->dvi_dual, 4910 info->max_tmds_clock); 4911 4912 drm_parse_hdmi_deep_color_info(connector, db); 4913 } 4914 4915 static void drm_parse_cea_ext(struct drm_connector *connector, 4916 const struct edid *edid) 4917 { 4918 struct drm_display_info *info = &connector->display_info; 4919 const u8 *edid_ext; 4920 int i, start, end; 4921 4922 edid_ext = drm_find_cea_extension(edid); 4923 if (!edid_ext) 4924 return; 4925 4926 info->cea_rev = edid_ext[1]; 4927 4928 /* The existence of a CEA block should imply RGB support */ 4929 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4930 if (edid_ext[3] & EDID_CEA_YCRCB444) 4931 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4932 if (edid_ext[3] & EDID_CEA_YCRCB422) 4933 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4934 4935 if (cea_db_offsets(edid_ext, &start, &end)) 4936 return; 4937 4938 for_each_cea_db(edid_ext, i, start, end) { 4939 const u8 *db = &edid_ext[i]; 4940 4941 if (cea_db_is_hdmi_vsdb(db)) 4942 drm_parse_hdmi_vsdb_video(connector, db); 4943 if (cea_db_is_hdmi_forum_vsdb(db)) 4944 drm_parse_hdmi_forum_vsdb(connector, db); 4945 if (cea_db_is_y420cmdb(db)) 4946 drm_parse_y420cmdb_bitmap(connector, db); 4947 if (cea_db_is_vcdb(db)) 4948 drm_parse_vcdb(connector, db); 4949 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4950 drm_parse_hdr_metadata_block(connector, db); 4951 } 4952 } 4953 4954 static 4955 void get_monitor_range(struct detailed_timing *timing, 4956 void *info_monitor_range) 4957 { 4958 struct drm_monitor_range_info *monitor_range = info_monitor_range; 4959 const struct detailed_non_pixel *data = &timing->data.other_data; 4960 const struct detailed_data_monitor_range *range = &data->data.range; 4961 4962 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE)) 4963 return; 4964 4965 /* 4966 * Check for flag range limits only. If flag == 1 then 4967 * no additional timing information provided. 4968 * Default GTF, GTF Secondary curve and CVT are not 4969 * supported 4970 */ 4971 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 4972 return; 4973 4974 monitor_range->min_vfreq = range->min_vfreq; 4975 monitor_range->max_vfreq = range->max_vfreq; 4976 } 4977 4978 static 4979 void drm_get_monitor_range(struct drm_connector *connector, 4980 const struct edid *edid) 4981 { 4982 struct drm_display_info *info = &connector->display_info; 4983 4984 if (!version_greater(edid, 1, 1)) 4985 return; 4986 4987 drm_for_each_detailed_block((u8 *)edid, get_monitor_range, 4988 &info->monitor_range); 4989 4990 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 4991 info->monitor_range.min_vfreq, 4992 info->monitor_range.max_vfreq); 4993 } 4994 4995 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4996 * all of the values which would have been set from EDID 4997 */ 4998 void 4999 drm_reset_display_info(struct drm_connector *connector) 5000 { 5001 struct drm_display_info *info = &connector->display_info; 5002 5003 info->width_mm = 0; 5004 info->height_mm = 0; 5005 5006 info->bpc = 0; 5007 info->color_formats = 0; 5008 info->cea_rev = 0; 5009 info->max_tmds_clock = 0; 5010 info->dvi_dual = false; 5011 info->is_hdmi = false; 5012 info->has_hdmi_infoframe = false; 5013 info->rgb_quant_range_selectable = false; 5014 memset(&info->hdmi, 0, sizeof(info->hdmi)); 5015 5016 info->non_desktop = 0; 5017 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 5018 } 5019 5020 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 5021 { 5022 struct drm_display_info *info = &connector->display_info; 5023 5024 u32 quirks = edid_get_quirks(edid); 5025 5026 drm_reset_display_info(connector); 5027 5028 info->width_mm = edid->width_cm * 10; 5029 info->height_mm = edid->height_cm * 10; 5030 5031 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 5032 5033 drm_get_monitor_range(connector, edid); 5034 5035 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 5036 5037 if (edid->revision < 3) 5038 return quirks; 5039 5040 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 5041 return quirks; 5042 5043 drm_parse_cea_ext(connector, edid); 5044 5045 /* 5046 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 5047 * 5048 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 5049 * tells us to assume 8 bpc color depth if the EDID doesn't have 5050 * extensions which tell otherwise. 5051 */ 5052 if (info->bpc == 0 && edid->revision == 3 && 5053 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 5054 info->bpc = 8; 5055 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 5056 connector->name, info->bpc); 5057 } 5058 5059 /* Only defined for 1.4 with digital displays */ 5060 if (edid->revision < 4) 5061 return quirks; 5062 5063 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 5064 case DRM_EDID_DIGITAL_DEPTH_6: 5065 info->bpc = 6; 5066 break; 5067 case DRM_EDID_DIGITAL_DEPTH_8: 5068 info->bpc = 8; 5069 break; 5070 case DRM_EDID_DIGITAL_DEPTH_10: 5071 info->bpc = 10; 5072 break; 5073 case DRM_EDID_DIGITAL_DEPTH_12: 5074 info->bpc = 12; 5075 break; 5076 case DRM_EDID_DIGITAL_DEPTH_14: 5077 info->bpc = 14; 5078 break; 5079 case DRM_EDID_DIGITAL_DEPTH_16: 5080 info->bpc = 16; 5081 break; 5082 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 5083 default: 5084 info->bpc = 0; 5085 break; 5086 } 5087 5088 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 5089 connector->name, info->bpc); 5090 5091 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 5092 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 5093 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 5094 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 5095 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 5096 return quirks; 5097 } 5098 5099 static int validate_displayid(u8 *displayid, int length, int idx) 5100 { 5101 int i; 5102 u8 csum = 0; 5103 struct displayid_hdr *base; 5104 5105 base = (struct displayid_hdr *)&displayid[idx]; 5106 5107 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5108 base->rev, base->bytes, base->prod_id, base->ext_count); 5109 5110 if (base->bytes + 5 > length - idx) 5111 return -EINVAL; 5112 for (i = idx; i <= base->bytes + 5; i++) { 5113 csum += displayid[i]; 5114 } 5115 if (csum) { 5116 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5117 return -EINVAL; 5118 } 5119 return 0; 5120 } 5121 5122 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5123 struct displayid_detailed_timings_1 *timings) 5124 { 5125 struct drm_display_mode *mode; 5126 unsigned pixel_clock = (timings->pixel_clock[0] | 5127 (timings->pixel_clock[1] << 8) | 5128 (timings->pixel_clock[2] << 16)) + 1; 5129 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5130 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5131 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5132 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5133 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5134 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5135 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5136 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5137 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5138 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5139 mode = drm_mode_create(dev); 5140 if (!mode) 5141 return NULL; 5142 5143 mode->clock = pixel_clock * 10; 5144 mode->hdisplay = hactive; 5145 mode->hsync_start = mode->hdisplay + hsync; 5146 mode->hsync_end = mode->hsync_start + hsync_width; 5147 mode->htotal = mode->hdisplay + hblank; 5148 5149 mode->vdisplay = vactive; 5150 mode->vsync_start = mode->vdisplay + vsync; 5151 mode->vsync_end = mode->vsync_start + vsync_width; 5152 mode->vtotal = mode->vdisplay + vblank; 5153 5154 mode->flags = 0; 5155 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5156 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5157 mode->type = DRM_MODE_TYPE_DRIVER; 5158 5159 if (timings->flags & 0x80) 5160 mode->type |= DRM_MODE_TYPE_PREFERRED; 5161 mode->vrefresh = drm_mode_vrefresh(mode); 5162 drm_mode_set_name(mode); 5163 5164 return mode; 5165 } 5166 5167 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5168 struct displayid_block *block) 5169 { 5170 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 5171 int i; 5172 int num_timings; 5173 struct drm_display_mode *newmode; 5174 int num_modes = 0; 5175 /* blocks must be multiple of 20 bytes length */ 5176 if (block->num_bytes % 20) 5177 return 0; 5178 5179 num_timings = block->num_bytes / 20; 5180 for (i = 0; i < num_timings; i++) { 5181 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5182 5183 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5184 if (!newmode) 5185 continue; 5186 5187 drm_mode_probed_add(connector, newmode); 5188 num_modes++; 5189 } 5190 return num_modes; 5191 } 5192 5193 static int add_displayid_detailed_modes(struct drm_connector *connector, 5194 struct edid *edid) 5195 { 5196 u8 *displayid; 5197 int ret; 5198 int idx = 1; 5199 int length = EDID_LENGTH; 5200 struct displayid_block *block; 5201 int num_modes = 0; 5202 5203 displayid = drm_find_displayid_extension(edid); 5204 if (!displayid) 5205 return 0; 5206 5207 ret = validate_displayid(displayid, length, idx); 5208 if (ret) 5209 return 0; 5210 5211 idx += sizeof(struct displayid_hdr); 5212 for_each_displayid_db(displayid, block, idx, length) { 5213 switch (block->tag) { 5214 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5215 num_modes += add_displayid_detailed_1_modes(connector, block); 5216 break; 5217 } 5218 } 5219 return num_modes; 5220 } 5221 5222 /** 5223 * drm_add_edid_modes - add modes from EDID data, if available 5224 * @connector: connector we're probing 5225 * @edid: EDID data 5226 * 5227 * Add the specified modes to the connector's mode list. Also fills out the 5228 * &drm_display_info structure and ELD in @connector with any information which 5229 * can be derived from the edid. 5230 * 5231 * Return: The number of modes added or 0 if we couldn't find any. 5232 */ 5233 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5234 { 5235 int num_modes = 0; 5236 u32 quirks; 5237 5238 if (edid == NULL) { 5239 clear_eld(connector); 5240 return 0; 5241 } 5242 if (!drm_edid_is_valid(edid)) { 5243 clear_eld(connector); 5244 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 5245 connector->name); 5246 return 0; 5247 } 5248 5249 drm_edid_to_eld(connector, edid); 5250 5251 /* 5252 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5253 * To avoid multiple parsing of same block, lets parse that map 5254 * from sink info, before parsing CEA modes. 5255 */ 5256 quirks = drm_add_display_info(connector, edid); 5257 5258 /* 5259 * EDID spec says modes should be preferred in this order: 5260 * - preferred detailed mode 5261 * - other detailed modes from base block 5262 * - detailed modes from extension blocks 5263 * - CVT 3-byte code modes 5264 * - standard timing codes 5265 * - established timing codes 5266 * - modes inferred from GTF or CVT range information 5267 * 5268 * We get this pretty much right. 5269 * 5270 * XXX order for additional mode types in extension blocks? 5271 */ 5272 num_modes += add_detailed_modes(connector, edid, quirks); 5273 num_modes += add_cvt_modes(connector, edid); 5274 num_modes += add_standard_modes(connector, edid); 5275 num_modes += add_established_modes(connector, edid); 5276 num_modes += add_cea_modes(connector, edid); 5277 num_modes += add_alternate_cea_modes(connector, edid); 5278 num_modes += add_displayid_detailed_modes(connector, edid); 5279 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5280 num_modes += add_inferred_modes(connector, edid); 5281 5282 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5283 edid_fixup_preferred(connector, quirks); 5284 5285 if (quirks & EDID_QUIRK_FORCE_6BPC) 5286 connector->display_info.bpc = 6; 5287 5288 if (quirks & EDID_QUIRK_FORCE_8BPC) 5289 connector->display_info.bpc = 8; 5290 5291 if (quirks & EDID_QUIRK_FORCE_10BPC) 5292 connector->display_info.bpc = 10; 5293 5294 if (quirks & EDID_QUIRK_FORCE_12BPC) 5295 connector->display_info.bpc = 12; 5296 5297 return num_modes; 5298 } 5299 EXPORT_SYMBOL(drm_add_edid_modes); 5300 5301 /** 5302 * drm_add_modes_noedid - add modes for the connectors without EDID 5303 * @connector: connector we're probing 5304 * @hdisplay: the horizontal display limit 5305 * @vdisplay: the vertical display limit 5306 * 5307 * Add the specified modes to the connector's mode list. Only when the 5308 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5309 * 5310 * Return: The number of modes added or 0 if we couldn't find any. 5311 */ 5312 int drm_add_modes_noedid(struct drm_connector *connector, 5313 int hdisplay, int vdisplay) 5314 { 5315 int i, count, num_modes = 0; 5316 struct drm_display_mode *mode; 5317 struct drm_device *dev = connector->dev; 5318 5319 count = ARRAY_SIZE(drm_dmt_modes); 5320 if (hdisplay < 0) 5321 hdisplay = 0; 5322 if (vdisplay < 0) 5323 vdisplay = 0; 5324 5325 for (i = 0; i < count; i++) { 5326 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5327 if (hdisplay && vdisplay) { 5328 /* 5329 * Only when two are valid, they will be used to check 5330 * whether the mode should be added to the mode list of 5331 * the connector. 5332 */ 5333 if (ptr->hdisplay > hdisplay || 5334 ptr->vdisplay > vdisplay) 5335 continue; 5336 } 5337 if (drm_mode_vrefresh(ptr) > 61) 5338 continue; 5339 mode = drm_mode_duplicate(dev, ptr); 5340 if (mode) { 5341 drm_mode_probed_add(connector, mode); 5342 num_modes++; 5343 } 5344 } 5345 return num_modes; 5346 } 5347 EXPORT_SYMBOL(drm_add_modes_noedid); 5348 5349 /** 5350 * drm_set_preferred_mode - Sets the preferred mode of a connector 5351 * @connector: connector whose mode list should be processed 5352 * @hpref: horizontal resolution of preferred mode 5353 * @vpref: vertical resolution of preferred mode 5354 * 5355 * Marks a mode as preferred if it matches the resolution specified by @hpref 5356 * and @vpref. 5357 */ 5358 void drm_set_preferred_mode(struct drm_connector *connector, 5359 int hpref, int vpref) 5360 { 5361 struct drm_display_mode *mode; 5362 5363 list_for_each_entry(mode, &connector->probed_modes, head) { 5364 if (mode->hdisplay == hpref && 5365 mode->vdisplay == vpref) 5366 mode->type |= DRM_MODE_TYPE_PREFERRED; 5367 } 5368 } 5369 EXPORT_SYMBOL(drm_set_preferred_mode); 5370 5371 static bool is_hdmi2_sink(struct drm_connector *connector) 5372 { 5373 /* 5374 * FIXME: sil-sii8620 doesn't have a connector around when 5375 * we need one, so we have to be prepared for a NULL connector. 5376 */ 5377 if (!connector) 5378 return true; 5379 5380 return connector->display_info.hdmi.scdc.supported || 5381 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5382 } 5383 5384 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5385 { 5386 return sink_eotf & BIT(output_eotf); 5387 } 5388 5389 /** 5390 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5391 * HDR metadata from userspace 5392 * @frame: HDMI DRM infoframe 5393 * @conn_state: Connector state containing HDR metadata 5394 * 5395 * Return: 0 on success or a negative error code on failure. 5396 */ 5397 int 5398 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5399 const struct drm_connector_state *conn_state) 5400 { 5401 struct drm_connector *connector; 5402 struct hdr_output_metadata *hdr_metadata; 5403 int err; 5404 5405 if (!frame || !conn_state) 5406 return -EINVAL; 5407 5408 connector = conn_state->connector; 5409 5410 if (!conn_state->hdr_output_metadata) 5411 return -EINVAL; 5412 5413 hdr_metadata = conn_state->hdr_output_metadata->data; 5414 5415 if (!hdr_metadata || !connector) 5416 return -EINVAL; 5417 5418 /* Sink EOTF is Bit map while infoframe is absolute values */ 5419 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5420 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5421 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5422 return -EINVAL; 5423 } 5424 5425 err = hdmi_drm_infoframe_init(frame); 5426 if (err < 0) 5427 return err; 5428 5429 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5430 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5431 5432 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5433 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5434 BUILD_BUG_ON(sizeof(frame->white_point) != 5435 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5436 5437 memcpy(&frame->display_primaries, 5438 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5439 sizeof(frame->display_primaries)); 5440 5441 memcpy(&frame->white_point, 5442 &hdr_metadata->hdmi_metadata_type1.white_point, 5443 sizeof(frame->white_point)); 5444 5445 frame->max_display_mastering_luminance = 5446 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5447 frame->min_display_mastering_luminance = 5448 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5449 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5450 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5451 5452 return 0; 5453 } 5454 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5455 5456 static u8 drm_mode_hdmi_vic(struct drm_connector *connector, 5457 const struct drm_display_mode *mode) 5458 { 5459 bool has_hdmi_infoframe = connector ? 5460 connector->display_info.has_hdmi_infoframe : false; 5461 5462 if (!has_hdmi_infoframe) 5463 return 0; 5464 5465 /* No HDMI VIC when signalling 3D video format */ 5466 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5467 return 0; 5468 5469 return drm_match_hdmi_mode(mode); 5470 } 5471 5472 static u8 drm_mode_cea_vic(struct drm_connector *connector, 5473 const struct drm_display_mode *mode) 5474 { 5475 u8 vic; 5476 5477 /* 5478 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5479 * we should send its VIC in vendor infoframes, else send the 5480 * VIC in AVI infoframes. Lets check if this mode is present in 5481 * HDMI 1.4b 4K modes 5482 */ 5483 if (drm_mode_hdmi_vic(connector, mode)) 5484 return 0; 5485 5486 vic = drm_match_cea_mode(mode); 5487 5488 /* 5489 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5490 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5491 * have to make sure we dont break HDMI 1.4 sinks. 5492 */ 5493 if (!is_hdmi2_sink(connector) && vic > 64) 5494 return 0; 5495 5496 return vic; 5497 } 5498 5499 /** 5500 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5501 * data from a DRM display mode 5502 * @frame: HDMI AVI infoframe 5503 * @connector: the connector 5504 * @mode: DRM display mode 5505 * 5506 * Return: 0 on success or a negative error code on failure. 5507 */ 5508 int 5509 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5510 struct drm_connector *connector, 5511 const struct drm_display_mode *mode) 5512 { 5513 enum hdmi_picture_aspect picture_aspect; 5514 u8 vic, hdmi_vic; 5515 5516 if (!frame || !mode) 5517 return -EINVAL; 5518 5519 hdmi_avi_infoframe_init(frame); 5520 5521 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5522 frame->pixel_repeat = 1; 5523 5524 vic = drm_mode_cea_vic(connector, mode); 5525 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5526 5527 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5528 5529 /* 5530 * As some drivers don't support atomic, we can't use connector state. 5531 * So just initialize the frame with default values, just the same way 5532 * as it's done with other properties here. 5533 */ 5534 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5535 frame->itc = 0; 5536 5537 /* 5538 * Populate picture aspect ratio from either 5539 * user input (if specified) or from the CEA/HDMI mode lists. 5540 */ 5541 picture_aspect = mode->picture_aspect_ratio; 5542 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5543 if (vic) 5544 picture_aspect = drm_get_cea_aspect_ratio(vic); 5545 else if (hdmi_vic) 5546 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5547 } 5548 5549 /* 5550 * The infoframe can't convey anything but none, 4:3 5551 * and 16:9, so if the user has asked for anything else 5552 * we can only satisfy it by specifying the right VIC. 5553 */ 5554 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5555 if (vic) { 5556 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5557 return -EINVAL; 5558 } else if (hdmi_vic) { 5559 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5560 return -EINVAL; 5561 } else { 5562 return -EINVAL; 5563 } 5564 5565 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5566 } 5567 5568 frame->video_code = vic; 5569 frame->picture_aspect = picture_aspect; 5570 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5571 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5572 5573 return 0; 5574 } 5575 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5576 5577 /* HDMI Colorspace Spec Definitions */ 5578 #define FULL_COLORIMETRY_MASK 0x1FF 5579 #define NORMAL_COLORIMETRY_MASK 0x3 5580 #define EXTENDED_COLORIMETRY_MASK 0x7 5581 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5582 5583 #define C(x) ((x) << 0) 5584 #define EC(x) ((x) << 2) 5585 #define ACE(x) ((x) << 5) 5586 5587 #define HDMI_COLORIMETRY_NO_DATA 0x0 5588 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5589 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5590 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5591 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5592 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5593 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5594 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5595 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5596 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5597 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5598 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5599 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5600 5601 static const u32 hdmi_colorimetry_val[] = { 5602 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5603 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5604 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5605 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5606 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5607 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5608 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5609 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5610 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5611 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5612 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5613 }; 5614 5615 #undef C 5616 #undef EC 5617 #undef ACE 5618 5619 /** 5620 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5621 * colorspace information 5622 * @frame: HDMI AVI infoframe 5623 * @conn_state: connector state 5624 */ 5625 void 5626 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5627 const struct drm_connector_state *conn_state) 5628 { 5629 u32 colorimetry_val; 5630 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5631 5632 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5633 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5634 else 5635 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5636 5637 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5638 /* 5639 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5640 * structure and extend it in drivers/video/hdmi 5641 */ 5642 frame->extended_colorimetry = (colorimetry_val >> 2) & 5643 EXTENDED_COLORIMETRY_MASK; 5644 } 5645 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5646 5647 /** 5648 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5649 * quantization range information 5650 * @frame: HDMI AVI infoframe 5651 * @connector: the connector 5652 * @mode: DRM display mode 5653 * @rgb_quant_range: RGB quantization range (Q) 5654 */ 5655 void 5656 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5657 struct drm_connector *connector, 5658 const struct drm_display_mode *mode, 5659 enum hdmi_quantization_range rgb_quant_range) 5660 { 5661 const struct drm_display_info *info = &connector->display_info; 5662 5663 /* 5664 * CEA-861: 5665 * "A Source shall not send a non-zero Q value that does not correspond 5666 * to the default RGB Quantization Range for the transmitted Picture 5667 * unless the Sink indicates support for the Q bit in a Video 5668 * Capabilities Data Block." 5669 * 5670 * HDMI 2.0 recommends sending non-zero Q when it does match the 5671 * default RGB quantization range for the mode, even when QS=0. 5672 */ 5673 if (info->rgb_quant_range_selectable || 5674 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5675 frame->quantization_range = rgb_quant_range; 5676 else 5677 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5678 5679 /* 5680 * CEA-861-F: 5681 * "When transmitting any RGB colorimetry, the Source should set the 5682 * YQ-field to match the RGB Quantization Range being transmitted 5683 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5684 * set YQ=1) and the Sink shall ignore the YQ-field." 5685 * 5686 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5687 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5688 * good way to tell which version of CEA-861 the sink supports, so 5689 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5690 * on on CEA-861-F. 5691 */ 5692 if (!is_hdmi2_sink(connector) || 5693 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5694 frame->ycc_quantization_range = 5695 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5696 else 5697 frame->ycc_quantization_range = 5698 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5699 } 5700 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5701 5702 /** 5703 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5704 * bar information 5705 * @frame: HDMI AVI infoframe 5706 * @conn_state: connector state 5707 */ 5708 void 5709 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5710 const struct drm_connector_state *conn_state) 5711 { 5712 frame->right_bar = conn_state->tv.margins.right; 5713 frame->left_bar = conn_state->tv.margins.left; 5714 frame->top_bar = conn_state->tv.margins.top; 5715 frame->bottom_bar = conn_state->tv.margins.bottom; 5716 } 5717 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5718 5719 static enum hdmi_3d_structure 5720 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5721 { 5722 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5723 5724 switch (layout) { 5725 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5726 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5727 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5728 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5729 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5730 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5731 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5732 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5733 case DRM_MODE_FLAG_3D_L_DEPTH: 5734 return HDMI_3D_STRUCTURE_L_DEPTH; 5735 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5736 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5737 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5738 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5739 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5740 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5741 default: 5742 return HDMI_3D_STRUCTURE_INVALID; 5743 } 5744 } 5745 5746 /** 5747 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5748 * data from a DRM display mode 5749 * @frame: HDMI vendor infoframe 5750 * @connector: the connector 5751 * @mode: DRM display mode 5752 * 5753 * Note that there's is a need to send HDMI vendor infoframes only when using a 5754 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5755 * function will return -EINVAL, error that can be safely ignored. 5756 * 5757 * Return: 0 on success or a negative error code on failure. 5758 */ 5759 int 5760 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5761 struct drm_connector *connector, 5762 const struct drm_display_mode *mode) 5763 { 5764 /* 5765 * FIXME: sil-sii8620 doesn't have a connector around when 5766 * we need one, so we have to be prepared for a NULL connector. 5767 */ 5768 bool has_hdmi_infoframe = connector ? 5769 connector->display_info.has_hdmi_infoframe : false; 5770 int err; 5771 5772 if (!frame || !mode) 5773 return -EINVAL; 5774 5775 if (!has_hdmi_infoframe) 5776 return -EINVAL; 5777 5778 err = hdmi_vendor_infoframe_init(frame); 5779 if (err < 0) 5780 return err; 5781 5782 /* 5783 * Even if it's not absolutely necessary to send the infoframe 5784 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5785 * know that the sink can handle it. This is based on a 5786 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5787 * have trouble realizing that they shuld switch from 3D to 2D 5788 * mode if the source simply stops sending the infoframe when 5789 * it wants to switch from 3D to 2D. 5790 */ 5791 frame->vic = drm_mode_hdmi_vic(connector, mode); 5792 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5793 5794 return 0; 5795 } 5796 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5797 5798 static int drm_parse_tiled_block(struct drm_connector *connector, 5799 struct displayid_block *block) 5800 { 5801 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 5802 u16 w, h; 5803 u8 tile_v_loc, tile_h_loc; 5804 u8 num_v_tile, num_h_tile; 5805 struct drm_tile_group *tg; 5806 5807 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5808 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5809 5810 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5811 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5812 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5813 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5814 5815 connector->has_tile = true; 5816 if (tile->tile_cap & 0x80) 5817 connector->tile_is_single_monitor = true; 5818 5819 connector->num_h_tile = num_h_tile + 1; 5820 connector->num_v_tile = num_v_tile + 1; 5821 connector->tile_h_loc = tile_h_loc; 5822 connector->tile_v_loc = tile_v_loc; 5823 connector->tile_h_size = w + 1; 5824 connector->tile_v_size = h + 1; 5825 5826 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5827 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5828 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5829 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5830 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5831 5832 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5833 if (!tg) { 5834 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5835 } 5836 if (!tg) 5837 return -ENOMEM; 5838 5839 if (connector->tile_group != tg) { 5840 /* if we haven't got a pointer, 5841 take the reference, drop ref to old tile group */ 5842 if (connector->tile_group) { 5843 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5844 } 5845 connector->tile_group = tg; 5846 } else 5847 /* if same tile group, then release the ref we just took. */ 5848 drm_mode_put_tile_group(connector->dev, tg); 5849 return 0; 5850 } 5851 5852 static int drm_parse_display_id(struct drm_connector *connector, 5853 u8 *displayid, int length, 5854 bool is_edid_extension) 5855 { 5856 /* if this is an EDID extension the first byte will be 0x70 */ 5857 int idx = 0; 5858 struct displayid_block *block; 5859 int ret; 5860 5861 if (is_edid_extension) 5862 idx = 1; 5863 5864 ret = validate_displayid(displayid, length, idx); 5865 if (ret) 5866 return ret; 5867 5868 idx += sizeof(struct displayid_hdr); 5869 for_each_displayid_db(displayid, block, idx, length) { 5870 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5871 block->tag, block->rev, block->num_bytes); 5872 5873 switch (block->tag) { 5874 case DATA_BLOCK_TILED_DISPLAY: 5875 ret = drm_parse_tiled_block(connector, block); 5876 if (ret) 5877 return ret; 5878 break; 5879 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5880 /* handled in mode gathering code. */ 5881 break; 5882 case DATA_BLOCK_CTA: 5883 /* handled in the cea parser code. */ 5884 break; 5885 default: 5886 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5887 break; 5888 } 5889 } 5890 return 0; 5891 } 5892 5893 static void drm_get_displayid(struct drm_connector *connector, 5894 struct edid *edid) 5895 { 5896 void *displayid = NULL; 5897 int ret; 5898 connector->has_tile = false; 5899 displayid = drm_find_displayid_extension(edid); 5900 if (!displayid) { 5901 /* drop reference to any tile group we had */ 5902 goto out_drop_ref; 5903 } 5904 5905 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5906 if (ret < 0) 5907 goto out_drop_ref; 5908 if (!connector->has_tile) 5909 goto out_drop_ref; 5910 return; 5911 out_drop_ref: 5912 if (connector->tile_group) { 5913 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5914 connector->tile_group = NULL; 5915 } 5916 return; 5917 } 5918