11bb76ff1Sjsg /* SPDX-License-Identifier: MIT */ 21bb76ff1Sjsg /* 31bb76ff1Sjsg * Copyright © 2022 Intel Corporation 41bb76ff1Sjsg */ 51bb76ff1Sjsg 61bb76ff1Sjsg #ifndef __HSW_IPS_H__ 71bb76ff1Sjsg #define __HSW_IPS_H__ 81bb76ff1Sjsg 91bb76ff1Sjsg #include <linux/types.h> 101bb76ff1Sjsg 111bb76ff1Sjsg struct intel_atomic_state; 121bb76ff1Sjsg struct intel_crtc; 131bb76ff1Sjsg struct intel_crtc_state; 141bb76ff1Sjsg 151bb76ff1Sjsg bool hsw_ips_disable(const struct intel_crtc_state *crtc_state); 161bb76ff1Sjsg bool hsw_ips_pre_update(struct intel_atomic_state *state, 171bb76ff1Sjsg struct intel_crtc *crtc); 181bb76ff1Sjsg void hsw_ips_post_update(struct intel_atomic_state *state, 191bb76ff1Sjsg struct intel_crtc *crtc); 201bb76ff1Sjsg bool hsw_crtc_supports_ips(struct intel_crtc *crtc); 211bb76ff1Sjsg bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 221bb76ff1Sjsg int hsw_ips_compute_config(struct intel_atomic_state *state, 231bb76ff1Sjsg struct intel_crtc *crtc); 241bb76ff1Sjsg void hsw_ips_get_config(struct intel_crtc_state *crtc_state); 25*f005ef32Sjsg void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc); 261bb76ff1Sjsg 271bb76ff1Sjsg #endif /* __HSW_IPS_H__ */ 28