11bb76ff1Sjsg /* SPDX-License-Identifier: MIT */ 21bb76ff1Sjsg /* 31bb76ff1Sjsg * Copyright © 2022 Intel Corporation 41bb76ff1Sjsg */ 51bb76ff1Sjsg 61bb76ff1Sjsg #ifndef __SKL_WATERMARK_H__ 71bb76ff1Sjsg #define __SKL_WATERMARK_H__ 81bb76ff1Sjsg 91bb76ff1Sjsg #include <linux/types.h> 101bb76ff1Sjsg 11*f005ef32Sjsg #include "intel_display_limits.h" 121bb76ff1Sjsg #include "intel_global_state.h" 13*f005ef32Sjsg #include "intel_wm_types.h" 141bb76ff1Sjsg 151bb76ff1Sjsg struct drm_i915_private; 161bb76ff1Sjsg struct intel_atomic_state; 171bb76ff1Sjsg struct intel_bw_state; 181bb76ff1Sjsg struct intel_crtc; 191bb76ff1Sjsg struct intel_crtc_state; 201bb76ff1Sjsg struct intel_plane; 211bb76ff1Sjsg 221bb76ff1Sjsg u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); 231bb76ff1Sjsg 241bb76ff1Sjsg void intel_sagv_pre_plane_update(struct intel_atomic_state *state); 251bb76ff1Sjsg void intel_sagv_post_plane_update(struct intel_atomic_state *state); 261bb76ff1Sjsg bool intel_can_enable_sagv(struct drm_i915_private *i915, 271bb76ff1Sjsg const struct intel_bw_state *bw_state); 281bb76ff1Sjsg 291bb76ff1Sjsg u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, 301bb76ff1Sjsg const struct skl_ddb_entry *entry); 311bb76ff1Sjsg 321bb76ff1Sjsg void skl_write_plane_wm(struct intel_plane *plane, 331bb76ff1Sjsg const struct intel_crtc_state *crtc_state); 341bb76ff1Sjsg void skl_write_cursor_wm(struct intel_plane *plane, 351bb76ff1Sjsg const struct intel_crtc_state *crtc_state); 361bb76ff1Sjsg 371bb76ff1Sjsg bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, 381bb76ff1Sjsg const struct skl_ddb_entry *entries, 391bb76ff1Sjsg int num_entries, int ignore_idx); 401bb76ff1Sjsg 411bb76ff1Sjsg void intel_wm_state_verify(struct intel_crtc *crtc, 421bb76ff1Sjsg struct intel_crtc_state *new_crtc_state); 431bb76ff1Sjsg 441bb76ff1Sjsg void skl_watermark_ipc_init(struct drm_i915_private *i915); 451bb76ff1Sjsg void skl_watermark_ipc_update(struct drm_i915_private *i915); 461bb76ff1Sjsg bool skl_watermark_ipc_enabled(struct drm_i915_private *i915); 47*f005ef32Sjsg void skl_watermark_debugfs_register(struct drm_i915_private *i915); 481bb76ff1Sjsg 491bb76ff1Sjsg void skl_wm_init(struct drm_i915_private *i915); 501bb76ff1Sjsg 511bb76ff1Sjsg struct intel_dbuf_state { 521bb76ff1Sjsg struct intel_global_state base; 531bb76ff1Sjsg 541bb76ff1Sjsg struct skl_ddb_entry ddb[I915_MAX_PIPES]; 551bb76ff1Sjsg unsigned int weight[I915_MAX_PIPES]; 561bb76ff1Sjsg u8 slices[I915_MAX_PIPES]; 571bb76ff1Sjsg u8 enabled_slices; 581bb76ff1Sjsg u8 active_pipes; 591bb76ff1Sjsg bool joined_mbus; 601bb76ff1Sjsg }; 611bb76ff1Sjsg 621bb76ff1Sjsg struct intel_dbuf_state * 631bb76ff1Sjsg intel_atomic_get_dbuf_state(struct intel_atomic_state *state); 641bb76ff1Sjsg 651bb76ff1Sjsg #define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base) 661bb76ff1Sjsg #define intel_atomic_get_old_dbuf_state(state) \ 671bb76ff1Sjsg to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) 681bb76ff1Sjsg #define intel_atomic_get_new_dbuf_state(state) \ 691bb76ff1Sjsg to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj)) 701bb76ff1Sjsg 711bb76ff1Sjsg int intel_dbuf_init(struct drm_i915_private *i915); 721bb76ff1Sjsg void intel_dbuf_pre_plane_update(struct intel_atomic_state *state); 731bb76ff1Sjsg void intel_dbuf_post_plane_update(struct intel_atomic_state *state); 741bb76ff1Sjsg void intel_mbus_dbox_update(struct intel_atomic_state *state); 751bb76ff1Sjsg 761bb76ff1Sjsg #endif /* __SKL_WATERMARK_H__ */ 771bb76ff1Sjsg 78