1*ad8b1aafSjsg /* SPDX-License-Identifier: MIT */ 2*ad8b1aafSjsg /* 3*ad8b1aafSjsg * Copyright © 2020 Intel Corporation 4*ad8b1aafSjsg */ 5*ad8b1aafSjsg 6*ad8b1aafSjsg #ifndef __GEN2_ENGINE_CS_H__ 7*ad8b1aafSjsg #define __GEN2_ENGINE_CS_H__ 8*ad8b1aafSjsg 9*ad8b1aafSjsg #include <linux/types.h> 10*ad8b1aafSjsg 11*ad8b1aafSjsg struct i915_request; 12*ad8b1aafSjsg struct intel_engine_cs; 13*ad8b1aafSjsg 14*ad8b1aafSjsg int gen2_emit_flush(struct i915_request *rq, u32 mode); 15*ad8b1aafSjsg int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode); 16*ad8b1aafSjsg int gen4_emit_flush_vcs(struct i915_request *rq, u32 mode); 17*ad8b1aafSjsg 18*ad8b1aafSjsg u32 *gen3_emit_breadcrumb(struct i915_request *rq, u32 *cs); 19*ad8b1aafSjsg u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs); 20*ad8b1aafSjsg 21*ad8b1aafSjsg int i830_emit_bb_start(struct i915_request *rq, 22*ad8b1aafSjsg u64 offset, u32 len, 23*ad8b1aafSjsg unsigned int dispatch_flags); 24*ad8b1aafSjsg int gen3_emit_bb_start(struct i915_request *rq, 25*ad8b1aafSjsg u64 offset, u32 len, 26*ad8b1aafSjsg unsigned int dispatch_flags); 27*ad8b1aafSjsg int gen4_emit_bb_start(struct i915_request *rq, 28*ad8b1aafSjsg u64 offset, u32 length, 29*ad8b1aafSjsg unsigned int dispatch_flags); 30*ad8b1aafSjsg 31*ad8b1aafSjsg void gen2_irq_enable(struct intel_engine_cs *engine); 32*ad8b1aafSjsg void gen2_irq_disable(struct intel_engine_cs *engine); 33*ad8b1aafSjsg void gen3_irq_enable(struct intel_engine_cs *engine); 34*ad8b1aafSjsg void gen3_irq_disable(struct intel_engine_cs *engine); 35*ad8b1aafSjsg void gen5_irq_enable(struct intel_engine_cs *engine); 36*ad8b1aafSjsg void gen5_irq_disable(struct intel_engine_cs *engine); 37*ad8b1aafSjsg 38*ad8b1aafSjsg #endif /* __GEN2_ENGINE_CS_H__ */ 39