1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include "i915_drv.h" 9 #include "i915_perf_types.h" 10 #include "intel_engine_regs.h" 11 #include "intel_gt_regs.h" 12 #include "intel_sseu.h" 13 14 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, 15 u8 max_subslices, u8 max_eus_per_subslice) 16 { 17 sseu->max_slices = max_slices; 18 sseu->max_subslices = max_subslices; 19 sseu->max_eus_per_subslice = max_eus_per_subslice; 20 } 21 22 unsigned int 23 intel_sseu_subslice_total(const struct sseu_dev_info *sseu) 24 { 25 unsigned int i, total = 0; 26 27 if (sseu->has_xehp_dss) 28 return bitmap_weight(sseu->subslice_mask.xehp, 29 XEHP_BITMAP_BITS(sseu->subslice_mask)); 30 31 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++) 32 total += hweight8(sseu->subslice_mask.hsw[i]); 33 34 return total; 35 } 36 37 unsigned int 38 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice) 39 { 40 WARN_ON(sseu->has_xehp_dss); 41 if (WARN_ON(slice >= sseu->max_slices)) 42 return 0; 43 44 return sseu->subslice_mask.hsw[slice]; 45 } 46 47 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, 48 int subslice) 49 { 50 if (sseu->has_xehp_dss) { 51 WARN_ON(slice > 0); 52 return sseu->eu_mask.xehp[subslice]; 53 } else { 54 return sseu->eu_mask.hsw[slice][subslice]; 55 } 56 } 57 58 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, 59 u16 eu_mask) 60 { 61 GEM_WARN_ON(eu_mask && __fls(eu_mask) >= sseu->max_eus_per_subslice); 62 if (sseu->has_xehp_dss) { 63 GEM_WARN_ON(slice > 0); 64 sseu->eu_mask.xehp[subslice] = eu_mask; 65 } else { 66 sseu->eu_mask.hsw[slice][subslice] = eu_mask; 67 } 68 } 69 70 static u16 compute_eu_total(const struct sseu_dev_info *sseu) 71 { 72 int s, ss, total = 0; 73 74 for (s = 0; s < sseu->max_slices; s++) 75 for (ss = 0; ss < sseu->max_subslices; ss++) 76 if (sseu->has_xehp_dss) 77 total += hweight16(sseu->eu_mask.xehp[ss]); 78 else 79 total += hweight16(sseu->eu_mask.hsw[s][ss]); 80 81 return total; 82 } 83 84 /** 85 * intel_sseu_copy_eumask_to_user - Copy EU mask into a userspace buffer 86 * @to: Pointer to userspace buffer to copy to 87 * @sseu: SSEU structure containing EU mask to copy 88 * 89 * Copies the EU mask to a userspace buffer in the format expected by 90 * the query ioctl's topology queries. 91 * 92 * Returns the result of the copy_to_user() operation. 93 */ 94 int intel_sseu_copy_eumask_to_user(void __user *to, 95 const struct sseu_dev_info *sseu) 96 { 97 u8 eu_mask[GEN_SS_MASK_SIZE * GEN_MAX_EU_STRIDE] = {}; 98 int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); 99 int len = sseu->max_slices * sseu->max_subslices * eu_stride; 100 int s, ss, i; 101 102 for (s = 0; s < sseu->max_slices; s++) { 103 for (ss = 0; ss < sseu->max_subslices; ss++) { 104 int uapi_offset = 105 s * sseu->max_subslices * eu_stride + 106 ss * eu_stride; 107 u16 mask = sseu_get_eus(sseu, s, ss); 108 109 for (i = 0; i < eu_stride; i++) 110 eu_mask[uapi_offset + i] = 111 (mask >> (BITS_PER_BYTE * i)) & 0xff; 112 } 113 } 114 115 return copy_to_user(to, eu_mask, len); 116 } 117 118 /** 119 * intel_sseu_copy_ssmask_to_user - Copy subslice mask into a userspace buffer 120 * @to: Pointer to userspace buffer to copy to 121 * @sseu: SSEU structure containing subslice mask to copy 122 * 123 * Copies the subslice mask to a userspace buffer in the format expected by 124 * the query ioctl's topology queries. 125 * 126 * Returns the result of the copy_to_user() operation. 127 */ 128 int intel_sseu_copy_ssmask_to_user(void __user *to, 129 const struct sseu_dev_info *sseu) 130 { 131 u8 ss_mask[GEN_SS_MASK_SIZE] = {}; 132 int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); 133 int len = sseu->max_slices * ss_stride; 134 int s, ss, i; 135 136 for (s = 0; s < sseu->max_slices; s++) { 137 for (ss = 0; ss < sseu->max_subslices; ss++) { 138 i = s * ss_stride * BITS_PER_BYTE + ss; 139 140 if (!intel_sseu_has_subslice(sseu, s, ss)) 141 continue; 142 143 ss_mask[i / BITS_PER_BYTE] |= BIT(i % BITS_PER_BYTE); 144 } 145 } 146 147 return copy_to_user(to, ss_mask, len); 148 } 149 150 static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, 151 u32 ss_en, u16 eu_en) 152 { 153 u32 valid_ss_mask = GENMASK(sseu->max_subslices - 1, 0); 154 int ss; 155 156 sseu->slice_mask |= BIT(0); 157 sseu->subslice_mask.hsw[0] = ss_en & valid_ss_mask; 158 159 for (ss = 0; ss < sseu->max_subslices; ss++) 160 if (intel_sseu_has_subslice(sseu, 0, ss)) 161 sseu_set_eus(sseu, 0, ss, eu_en); 162 163 sseu->eu_per_subslice = hweight16(eu_en); 164 sseu->eu_total = compute_eu_total(sseu); 165 } 166 167 static void xehp_compute_sseu_info(struct sseu_dev_info *sseu, 168 u16 eu_en) 169 { 170 int ss; 171 172 sseu->slice_mask |= BIT(0); 173 174 bitmap_or(sseu->subslice_mask.xehp, 175 sseu->compute_subslice_mask.xehp, 176 sseu->geometry_subslice_mask.xehp, 177 XEHP_BITMAP_BITS(sseu->subslice_mask)); 178 179 for (ss = 0; ss < sseu->max_subslices; ss++) 180 if (intel_sseu_has_subslice(sseu, 0, ss)) 181 sseu_set_eus(sseu, 0, ss, eu_en); 182 183 sseu->eu_per_subslice = hweight16(eu_en); 184 sseu->eu_total = compute_eu_total(sseu); 185 } 186 187 static void 188 xehp_load_dss_mask(struct intel_uncore *uncore, 189 intel_sseu_ss_mask_t *ssmask, 190 int numregs, 191 ...) 192 { 193 STUB(); 194 #ifdef notyet 195 va_list argp; 196 u32 fuse_val[I915_MAX_SS_FUSE_REGS] = {}; 197 int i; 198 199 if (WARN_ON(numregs > I915_MAX_SS_FUSE_REGS)) 200 numregs = I915_MAX_SS_FUSE_REGS; 201 202 va_start(argp, numregs); 203 for (i = 0; i < numregs; i++) 204 fuse_val[i] = intel_uncore_read(uncore, va_arg(argp, i915_reg_t)); 205 va_end(argp); 206 207 bitmap_from_arr32(ssmask->xehp, fuse_val, numregs * 32); 208 #endif 209 } 210 211 static void xehp_sseu_info_init(struct intel_gt *gt) 212 { 213 struct sseu_dev_info *sseu = >->info.sseu; 214 struct intel_uncore *uncore = gt->uncore; 215 u16 eu_en = 0; 216 u8 eu_en_fuse; 217 int num_compute_regs, num_geometry_regs; 218 int eu; 219 220 if (IS_PONTEVECCHIO(gt->i915)) { 221 num_geometry_regs = 0; 222 num_compute_regs = 2; 223 } else { 224 num_geometry_regs = 1; 225 num_compute_regs = 1; 226 } 227 228 /* 229 * The concept of slice has been removed in Xe_HP. To be compatible 230 * with prior generations, assume a single slice across the entire 231 * device. Then calculate out the DSS for each workload type within 232 * that software slice. 233 */ 234 intel_sseu_set_info(sseu, 1, 235 32 * max(num_geometry_regs, num_compute_regs), 236 HAS_ONE_EU_PER_FUSE_BIT(gt->i915) ? 8 : 16); 237 sseu->has_xehp_dss = 1; 238 239 xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask, 240 num_geometry_regs, 241 GEN12_GT_GEOMETRY_DSS_ENABLE); 242 xehp_load_dss_mask(uncore, &sseu->compute_subslice_mask, 243 num_compute_regs, 244 GEN12_GT_COMPUTE_DSS_ENABLE, 245 XEHPC_GT_COMPUTE_DSS_ENABLE_EXT); 246 247 eu_en_fuse = intel_uncore_read(uncore, XEHP_EU_ENABLE) & XEHP_EU_ENA_MASK; 248 249 if (HAS_ONE_EU_PER_FUSE_BIT(gt->i915)) 250 eu_en = eu_en_fuse; 251 else 252 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 253 if (eu_en_fuse & BIT(eu)) 254 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); 255 256 xehp_compute_sseu_info(sseu, eu_en); 257 } 258 259 static void gen12_sseu_info_init(struct intel_gt *gt) 260 { 261 struct sseu_dev_info *sseu = >->info.sseu; 262 struct intel_uncore *uncore = gt->uncore; 263 u32 g_dss_en; 264 u16 eu_en = 0; 265 u8 eu_en_fuse; 266 u8 s_en; 267 int eu; 268 269 /* 270 * Gen12 has Dual-Subslices, which behave similarly to 2 gen11 SS. 271 * Instead of splitting these, provide userspace with an array 272 * of DSS to more closely represent the hardware resource. 273 */ 274 intel_sseu_set_info(sseu, 1, 6, 16); 275 276 /* 277 * Although gen12 architecture supported multiple slices, TGL, RKL, 278 * DG1, and ADL only had a single slice. 279 */ 280 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & 281 GEN11_GT_S_ENA_MASK; 282 drm_WARN_ON(>->i915->drm, s_en != 0x1); 283 284 g_dss_en = intel_uncore_read(uncore, GEN12_GT_GEOMETRY_DSS_ENABLE); 285 286 /* one bit per pair of EUs */ 287 eu_en_fuse = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & 288 GEN11_EU_DIS_MASK); 289 290 for (eu = 0; eu < sseu->max_eus_per_subslice / 2; eu++) 291 if (eu_en_fuse & BIT(eu)) 292 eu_en |= BIT(eu * 2) | BIT(eu * 2 + 1); 293 294 gen11_compute_sseu_info(sseu, g_dss_en, eu_en); 295 296 /* TGL only supports slice-level power gating */ 297 sseu->has_slice_pg = 1; 298 } 299 300 static void gen11_sseu_info_init(struct intel_gt *gt) 301 { 302 struct sseu_dev_info *sseu = >->info.sseu; 303 struct intel_uncore *uncore = gt->uncore; 304 u32 ss_en; 305 u8 eu_en; 306 u8 s_en; 307 308 if (IS_JASPERLAKE(gt->i915) || IS_ELKHARTLAKE(gt->i915)) 309 intel_sseu_set_info(sseu, 1, 4, 8); 310 else 311 intel_sseu_set_info(sseu, 1, 8, 8); 312 313 /* 314 * Although gen11 architecture supported multiple slices, ICL and 315 * EHL/JSL only had a single slice in practice. 316 */ 317 s_en = intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE) & 318 GEN11_GT_S_ENA_MASK; 319 drm_WARN_ON(>->i915->drm, s_en != 0x1); 320 321 ss_en = ~intel_uncore_read(uncore, GEN11_GT_SUBSLICE_DISABLE); 322 323 eu_en = ~(intel_uncore_read(uncore, GEN11_EU_DISABLE) & 324 GEN11_EU_DIS_MASK); 325 326 gen11_compute_sseu_info(sseu, ss_en, eu_en); 327 328 /* ICL has no power gating restrictions. */ 329 sseu->has_slice_pg = 1; 330 sseu->has_subslice_pg = 1; 331 sseu->has_eu_pg = 1; 332 } 333 334 static void cherryview_sseu_info_init(struct intel_gt *gt) 335 { 336 struct sseu_dev_info *sseu = >->info.sseu; 337 u32 fuse; 338 339 fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT); 340 341 sseu->slice_mask = BIT(0); 342 intel_sseu_set_info(sseu, 1, 2, 8); 343 344 if (!(fuse & CHV_FGT_DISABLE_SS0)) { 345 u8 disabled_mask = 346 ((fuse & CHV_FGT_EU_DIS_SS0_R0_MASK) >> 347 CHV_FGT_EU_DIS_SS0_R0_SHIFT) | 348 (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >> 349 CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4); 350 351 sseu->subslice_mask.hsw[0] |= BIT(0); 352 sseu_set_eus(sseu, 0, 0, ~disabled_mask & 0xFF); 353 } 354 355 if (!(fuse & CHV_FGT_DISABLE_SS1)) { 356 u8 disabled_mask = 357 ((fuse & CHV_FGT_EU_DIS_SS1_R0_MASK) >> 358 CHV_FGT_EU_DIS_SS1_R0_SHIFT) | 359 (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >> 360 CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4); 361 362 sseu->subslice_mask.hsw[0] |= BIT(1); 363 sseu_set_eus(sseu, 0, 1, ~disabled_mask & 0xFF); 364 } 365 366 sseu->eu_total = compute_eu_total(sseu); 367 368 /* 369 * CHV expected to always have a uniform distribution of EU 370 * across subslices. 371 */ 372 sseu->eu_per_subslice = intel_sseu_subslice_total(sseu) ? 373 sseu->eu_total / 374 intel_sseu_subslice_total(sseu) : 375 0; 376 /* 377 * CHV supports subslice power gating on devices with more than 378 * one subslice, and supports EU power gating on devices with 379 * more than one EU pair per subslice. 380 */ 381 sseu->has_slice_pg = 0; 382 sseu->has_subslice_pg = intel_sseu_subslice_total(sseu) > 1; 383 sseu->has_eu_pg = (sseu->eu_per_subslice > 2); 384 } 385 386 static void gen9_sseu_info_init(struct intel_gt *gt) 387 { 388 struct drm_i915_private *i915 = gt->i915; 389 struct sseu_dev_info *sseu = >->info.sseu; 390 struct intel_uncore *uncore = gt->uncore; 391 u32 fuse2, eu_disable, subslice_mask; 392 const u8 eu_mask = 0xff; 393 int s, ss; 394 395 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); 396 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 397 398 /* BXT has a single slice and at most 3 subslices. */ 399 intel_sseu_set_info(sseu, IS_GEN9_LP(i915) ? 1 : 3, 400 IS_GEN9_LP(i915) ? 3 : 4, 8); 401 402 /* 403 * The subslice disable field is global, i.e. it applies 404 * to each of the enabled slices. 405 */ 406 subslice_mask = (1 << sseu->max_subslices) - 1; 407 subslice_mask &= ~((fuse2 & GEN9_F2_SS_DIS_MASK) >> 408 GEN9_F2_SS_DIS_SHIFT); 409 410 /* 411 * Iterate through enabled slices and subslices to 412 * count the total enabled EU. 413 */ 414 for (s = 0; s < sseu->max_slices; s++) { 415 if (!(sseu->slice_mask & BIT(s))) 416 /* skip disabled slice */ 417 continue; 418 419 sseu->subslice_mask.hsw[s] = subslice_mask; 420 421 eu_disable = intel_uncore_read(uncore, GEN9_EU_DISABLE(s)); 422 for (ss = 0; ss < sseu->max_subslices; ss++) { 423 int eu_per_ss; 424 u8 eu_disabled_mask; 425 426 if (!intel_sseu_has_subslice(sseu, s, ss)) 427 /* skip disabled subslice */ 428 continue; 429 430 eu_disabled_mask = (eu_disable >> (ss * 8)) & eu_mask; 431 432 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & eu_mask); 433 434 eu_per_ss = sseu->max_eus_per_subslice - 435 hweight8(eu_disabled_mask); 436 437 /* 438 * Record which subslice(s) has(have) 7 EUs. we 439 * can tune the hash used to spread work among 440 * subslices if they are unbalanced. 441 */ 442 if (eu_per_ss == 7) 443 sseu->subslice_7eu[s] |= BIT(ss); 444 } 445 } 446 447 sseu->eu_total = compute_eu_total(sseu); 448 449 /* 450 * SKL is expected to always have a uniform distribution 451 * of EU across subslices with the exception that any one 452 * EU in any one subslice may be fused off for die 453 * recovery. BXT is expected to be perfectly uniform in EU 454 * distribution. 455 */ 456 sseu->eu_per_subslice = 457 intel_sseu_subslice_total(sseu) ? 458 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) : 459 0; 460 461 /* 462 * SKL+ supports slice power gating on devices with more than 463 * one slice, and supports EU power gating on devices with 464 * more than one EU pair per subslice. BXT+ supports subslice 465 * power gating on devices with more than one subslice, and 466 * supports EU power gating on devices with more than one EU 467 * pair per subslice. 468 */ 469 sseu->has_slice_pg = 470 !IS_GEN9_LP(i915) && hweight8(sseu->slice_mask) > 1; 471 sseu->has_subslice_pg = 472 IS_GEN9_LP(i915) && intel_sseu_subslice_total(sseu) > 1; 473 sseu->has_eu_pg = sseu->eu_per_subslice > 2; 474 475 if (IS_GEN9_LP(i915)) { 476 #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask.hsw[0] & BIT(ss))) 477 RUNTIME_INFO(i915)->has_pooled_eu = hweight8(sseu->subslice_mask.hsw[0]) == 3; 478 479 sseu->min_eu_in_pool = 0; 480 if (HAS_POOLED_EU(i915)) { 481 if (IS_SS_DISABLED(2) || IS_SS_DISABLED(0)) 482 sseu->min_eu_in_pool = 3; 483 else if (IS_SS_DISABLED(1)) 484 sseu->min_eu_in_pool = 6; 485 else 486 sseu->min_eu_in_pool = 9; 487 } 488 #undef IS_SS_DISABLED 489 } 490 } 491 492 static void bdw_sseu_info_init(struct intel_gt *gt) 493 { 494 struct sseu_dev_info *sseu = >->info.sseu; 495 struct intel_uncore *uncore = gt->uncore; 496 int s, ss; 497 u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ 498 u32 eu_disable0, eu_disable1, eu_disable2; 499 500 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); 501 sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; 502 intel_sseu_set_info(sseu, 3, 3, 8); 503 504 /* 505 * The subslice disable field is global, i.e. it applies 506 * to each of the enabled slices. 507 */ 508 subslice_mask = GENMASK(sseu->max_subslices - 1, 0); 509 subslice_mask &= ~((fuse2 & GEN8_F2_SS_DIS_MASK) >> 510 GEN8_F2_SS_DIS_SHIFT); 511 eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); 512 eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); 513 eu_disable2 = intel_uncore_read(uncore, GEN8_EU_DISABLE2); 514 eu_disable[0] = eu_disable0 & GEN8_EU_DIS0_S0_MASK; 515 eu_disable[1] = (eu_disable0 >> GEN8_EU_DIS0_S1_SHIFT) | 516 ((eu_disable1 & GEN8_EU_DIS1_S1_MASK) << 517 (32 - GEN8_EU_DIS0_S1_SHIFT)); 518 eu_disable[2] = (eu_disable1 >> GEN8_EU_DIS1_S2_SHIFT) | 519 ((eu_disable2 & GEN8_EU_DIS2_S2_MASK) << 520 (32 - GEN8_EU_DIS1_S2_SHIFT)); 521 522 /* 523 * Iterate through enabled slices and subslices to 524 * count the total enabled EU. 525 */ 526 for (s = 0; s < sseu->max_slices; s++) { 527 if (!(sseu->slice_mask & BIT(s))) 528 /* skip disabled slice */ 529 continue; 530 531 sseu->subslice_mask.hsw[s] = subslice_mask; 532 533 for (ss = 0; ss < sseu->max_subslices; ss++) { 534 u8 eu_disabled_mask; 535 u32 n_disabled; 536 537 if (!intel_sseu_has_subslice(sseu, s, ss)) 538 /* skip disabled subslice */ 539 continue; 540 541 eu_disabled_mask = 542 eu_disable[s] >> (ss * sseu->max_eus_per_subslice); 543 544 sseu_set_eus(sseu, s, ss, ~eu_disabled_mask & 0xFF); 545 546 n_disabled = hweight8(eu_disabled_mask); 547 548 /* 549 * Record which subslices have 7 EUs. 550 */ 551 if (sseu->max_eus_per_subslice - n_disabled == 7) 552 sseu->subslice_7eu[s] |= 1 << ss; 553 } 554 } 555 556 sseu->eu_total = compute_eu_total(sseu); 557 558 /* 559 * BDW is expected to always have a uniform distribution of EU across 560 * subslices with the exception that any one EU in any one subslice may 561 * be fused off for die recovery. 562 */ 563 sseu->eu_per_subslice = 564 intel_sseu_subslice_total(sseu) ? 565 DIV_ROUND_UP(sseu->eu_total, intel_sseu_subslice_total(sseu)) : 566 0; 567 568 /* 569 * BDW supports slice power gating on devices with more than 570 * one slice. 571 */ 572 sseu->has_slice_pg = hweight8(sseu->slice_mask) > 1; 573 sseu->has_subslice_pg = 0; 574 sseu->has_eu_pg = 0; 575 } 576 577 static void hsw_sseu_info_init(struct intel_gt *gt) 578 { 579 struct drm_i915_private *i915 = gt->i915; 580 struct sseu_dev_info *sseu = >->info.sseu; 581 u32 fuse1; 582 u8 subslice_mask = 0; 583 int s, ss; 584 585 /* 586 * There isn't a register to tell us how many slices/subslices. We 587 * work off the PCI-ids here. 588 */ 589 switch (INTEL_INFO(i915)->gt) { 590 default: 591 MISSING_CASE(INTEL_INFO(i915)->gt); 592 fallthrough; 593 case 1: 594 sseu->slice_mask = BIT(0); 595 subslice_mask = BIT(0); 596 break; 597 case 2: 598 sseu->slice_mask = BIT(0); 599 subslice_mask = BIT(0) | BIT(1); 600 break; 601 case 3: 602 sseu->slice_mask = BIT(0) | BIT(1); 603 subslice_mask = BIT(0) | BIT(1); 604 break; 605 } 606 607 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1); 608 switch (REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)) { 609 default: 610 MISSING_CASE(REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)); 611 fallthrough; 612 case HSW_F1_EU_DIS_10EUS: 613 sseu->eu_per_subslice = 10; 614 break; 615 case HSW_F1_EU_DIS_8EUS: 616 sseu->eu_per_subslice = 8; 617 break; 618 case HSW_F1_EU_DIS_6EUS: 619 sseu->eu_per_subslice = 6; 620 break; 621 } 622 623 intel_sseu_set_info(sseu, hweight8(sseu->slice_mask), 624 hweight8(subslice_mask), 625 sseu->eu_per_subslice); 626 627 for (s = 0; s < sseu->max_slices; s++) { 628 sseu->subslice_mask.hsw[s] = subslice_mask; 629 630 for (ss = 0; ss < sseu->max_subslices; ss++) { 631 sseu_set_eus(sseu, s, ss, 632 (1UL << sseu->eu_per_subslice) - 1); 633 } 634 } 635 636 sseu->eu_total = compute_eu_total(sseu); 637 638 /* No powergating for you. */ 639 sseu->has_slice_pg = 0; 640 sseu->has_subslice_pg = 0; 641 sseu->has_eu_pg = 0; 642 } 643 644 void intel_sseu_info_init(struct intel_gt *gt) 645 { 646 struct drm_i915_private *i915 = gt->i915; 647 648 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 649 xehp_sseu_info_init(gt); 650 else if (GRAPHICS_VER(i915) >= 12) 651 gen12_sseu_info_init(gt); 652 else if (GRAPHICS_VER(i915) >= 11) 653 gen11_sseu_info_init(gt); 654 else if (GRAPHICS_VER(i915) >= 9) 655 gen9_sseu_info_init(gt); 656 else if (IS_BROADWELL(i915)) 657 bdw_sseu_info_init(gt); 658 else if (IS_CHERRYVIEW(i915)) 659 cherryview_sseu_info_init(gt); 660 else if (IS_HASWELL(i915)) 661 hsw_sseu_info_init(gt); 662 } 663 664 u32 intel_sseu_make_rpcs(struct intel_gt *gt, 665 const struct intel_sseu *req_sseu) 666 { 667 struct drm_i915_private *i915 = gt->i915; 668 const struct sseu_dev_info *sseu = >->info.sseu; 669 bool subslice_pg = sseu->has_subslice_pg; 670 u8 slices, subslices; 671 u32 rpcs = 0; 672 673 /* 674 * No explicit RPCS request is needed to ensure full 675 * slice/subslice/EU enablement prior to Gen9. 676 */ 677 if (GRAPHICS_VER(i915) < 9) 678 return 0; 679 680 /* 681 * If i915/perf is active, we want a stable powergating configuration 682 * on the system. Use the configuration pinned by i915/perf. 683 */ 684 if (gt->perf.group && gt->perf.group[PERF_GROUP_OAG].exclusive_stream) 685 req_sseu = >->perf.sseu; 686 687 slices = hweight8(req_sseu->slice_mask); 688 subslices = hweight8(req_sseu->subslice_mask); 689 690 /* 691 * Since the SScount bitfield in GEN8_R_PWR_CLK_STATE is only three bits 692 * wide and Icelake has up to eight subslices, specfial programming is 693 * needed in order to correctly enable all subslices. 694 * 695 * According to documentation software must consider the configuration 696 * as 2x4x8 and hardware will translate this to 1x8x8. 697 * 698 * Furthemore, even though SScount is three bits, maximum documented 699 * value for it is four. From this some rules/restrictions follow: 700 * 701 * 1. 702 * If enabled subslice count is greater than four, two whole slices must 703 * be enabled instead. 704 * 705 * 2. 706 * When more than one slice is enabled, hardware ignores the subslice 707 * count altogether. 708 * 709 * From these restrictions it follows that it is not possible to enable 710 * a count of subslices between the SScount maximum of four restriction, 711 * and the maximum available number on a particular SKU. Either all 712 * subslices are enabled, or a count between one and four on the first 713 * slice. 714 */ 715 if (GRAPHICS_VER(i915) == 11 && 716 slices == 1 && 717 subslices > min_t(u8, 4, hweight8(sseu->subslice_mask.hsw[0]) / 2)) { 718 GEM_BUG_ON(subslices & 1); 719 720 subslice_pg = false; 721 slices *= 2; 722 } 723 724 /* 725 * Starting in Gen9, render power gating can leave 726 * slice/subslice/EU in a partially enabled state. We 727 * must make an explicit request through RPCS for full 728 * enablement. 729 */ 730 if (sseu->has_slice_pg) { 731 u32 mask, val = slices; 732 733 if (GRAPHICS_VER(i915) >= 11) { 734 mask = GEN11_RPCS_S_CNT_MASK; 735 val <<= GEN11_RPCS_S_CNT_SHIFT; 736 } else { 737 mask = GEN8_RPCS_S_CNT_MASK; 738 val <<= GEN8_RPCS_S_CNT_SHIFT; 739 } 740 741 GEM_BUG_ON(val & ~mask); 742 val &= mask; 743 744 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_S_CNT_ENABLE | val; 745 } 746 747 if (subslice_pg) { 748 u32 val = subslices; 749 750 val <<= GEN8_RPCS_SS_CNT_SHIFT; 751 752 GEM_BUG_ON(val & ~GEN8_RPCS_SS_CNT_MASK); 753 val &= GEN8_RPCS_SS_CNT_MASK; 754 755 rpcs |= GEN8_RPCS_ENABLE | GEN8_RPCS_SS_CNT_ENABLE | val; 756 } 757 758 if (sseu->has_eu_pg) { 759 u32 val; 760 761 val = req_sseu->min_eus_per_subslice << GEN8_RPCS_EU_MIN_SHIFT; 762 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MIN_MASK); 763 val &= GEN8_RPCS_EU_MIN_MASK; 764 765 rpcs |= val; 766 767 val = req_sseu->max_eus_per_subslice << GEN8_RPCS_EU_MAX_SHIFT; 768 GEM_BUG_ON(val & ~GEN8_RPCS_EU_MAX_MASK); 769 val &= GEN8_RPCS_EU_MAX_MASK; 770 771 rpcs |= val; 772 773 rpcs |= GEN8_RPCS_ENABLE; 774 } 775 776 return rpcs; 777 } 778 779 void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p) 780 { 781 int s; 782 783 if (sseu->has_xehp_dss) { 784 drm_printf(p, "subslice total: %u\n", 785 intel_sseu_subslice_total(sseu)); 786 drm_printf(p, "geometry dss mask=%*pb\n", 787 XEHP_BITMAP_BITS(sseu->geometry_subslice_mask), 788 sseu->geometry_subslice_mask.xehp); 789 drm_printf(p, "compute dss mask=%*pb\n", 790 XEHP_BITMAP_BITS(sseu->compute_subslice_mask), 791 sseu->compute_subslice_mask.xehp); 792 } else { 793 drm_printf(p, "slice total: %u, mask=%04x\n", 794 hweight8(sseu->slice_mask), sseu->slice_mask); 795 drm_printf(p, "subslice total: %u\n", 796 intel_sseu_subslice_total(sseu)); 797 798 for (s = 0; s < sseu->max_slices; s++) { 799 u8 ss_mask = sseu->subslice_mask.hsw[s]; 800 801 drm_printf(p, "slice%d: %u subslices, mask=%08x\n", 802 s, hweight8(ss_mask), ss_mask); 803 } 804 } 805 806 drm_printf(p, "EU total: %u\n", sseu->eu_total); 807 drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice); 808 drm_printf(p, "has slice power gating: %s\n", 809 str_yes_no(sseu->has_slice_pg)); 810 drm_printf(p, "has subslice power gating: %s\n", 811 str_yes_no(sseu->has_subslice_pg)); 812 drm_printf(p, "has EU power gating: %s\n", 813 str_yes_no(sseu->has_eu_pg)); 814 } 815 816 static void sseu_print_hsw_topology(const struct sseu_dev_info *sseu, 817 struct drm_printer *p) 818 { 819 int s, ss; 820 821 for (s = 0; s < sseu->max_slices; s++) { 822 u8 ss_mask = sseu->subslice_mask.hsw[s]; 823 824 drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n", 825 s, hweight8(ss_mask), ss_mask); 826 827 for (ss = 0; ss < sseu->max_subslices; ss++) { 828 u16 enabled_eus = sseu_get_eus(sseu, s, ss); 829 830 drm_printf(p, "\tsubslice%d: %u EUs (0x%hx)\n", 831 ss, hweight16(enabled_eus), enabled_eus); 832 } 833 } 834 } 835 836 static void sseu_print_xehp_topology(const struct sseu_dev_info *sseu, 837 struct drm_printer *p) 838 { 839 int dss; 840 841 for (dss = 0; dss < sseu->max_subslices; dss++) { 842 u16 enabled_eus = sseu_get_eus(sseu, 0, dss); 843 844 drm_printf(p, "DSS_%02d: G:%3s C:%3s, %2u EUs (0x%04hx)\n", dss, 845 str_yes_no(test_bit(dss, sseu->geometry_subslice_mask.xehp)), 846 str_yes_no(test_bit(dss, sseu->compute_subslice_mask.xehp)), 847 hweight16(enabled_eus), enabled_eus); 848 } 849 } 850 851 void intel_sseu_print_topology(struct drm_i915_private *i915, 852 const struct sseu_dev_info *sseu, 853 struct drm_printer *p) 854 { 855 if (sseu->max_slices == 0) { 856 drm_printf(p, "Unavailable\n"); 857 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 858 sseu_print_xehp_topology(sseu, p); 859 } else { 860 sseu_print_hsw_topology(sseu, p); 861 } 862 } 863 864 void intel_sseu_print_ss_info(const char *type, 865 const struct sseu_dev_info *sseu, 866 struct seq_file *m) 867 { 868 int s; 869 870 if (sseu->has_xehp_dss) { 871 seq_printf(m, " %s Geometry DSS: %u\n", type, 872 bitmap_weight(sseu->geometry_subslice_mask.xehp, 873 XEHP_BITMAP_BITS(sseu->geometry_subslice_mask))); 874 seq_printf(m, " %s Compute DSS: %u\n", type, 875 bitmap_weight(sseu->compute_subslice_mask.xehp, 876 XEHP_BITMAP_BITS(sseu->compute_subslice_mask))); 877 } else { 878 for (s = 0; s < fls(sseu->slice_mask); s++) 879 seq_printf(m, " %s Slice%i subslices: %u\n", type, 880 s, hweight8(sseu->subslice_mask.hsw[s])); 881 } 882 } 883 884 u16 intel_slicemask_from_xehp_dssmask(intel_sseu_ss_mask_t dss_mask, 885 int dss_per_slice) 886 { 887 STUB(); 888 return 0; 889 #ifdef notyet 890 intel_sseu_ss_mask_t per_slice_mask = {}; 891 unsigned long slice_mask = 0; 892 int i; 893 894 WARN_ON(DIV_ROUND_UP(XEHP_BITMAP_BITS(dss_mask), dss_per_slice) > 895 8 * sizeof(slice_mask)); 896 897 bitmap_fill(per_slice_mask.xehp, dss_per_slice); 898 for (i = 0; !bitmap_empty(dss_mask.xehp, XEHP_BITMAP_BITS(dss_mask)); i++) { 899 if (bitmap_intersects(dss_mask.xehp, per_slice_mask.xehp, dss_per_slice)) 900 slice_mask |= BIT(i); 901 902 bitmap_shift_right(dss_mask.xehp, dss_mask.xehp, dss_per_slice, 903 XEHP_BITMAP_BITS(dss_mask)); 904 } 905 906 return slice_mask; 907 #endif 908 } 909