1*c349dbc7Sjsg /* 2*c349dbc7Sjsg * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3*c349dbc7Sjsg * 4*c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5*c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6*c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7*c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9*c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10*c349dbc7Sjsg * 11*c349dbc7Sjsg * The above copyright notice and this permission notice (including the next 12*c349dbc7Sjsg * paragraph) shall be included in all copies or substantial portions of the 13*c349dbc7Sjsg * Software. 14*c349dbc7Sjsg * 15*c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16*c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*c349dbc7Sjsg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19*c349dbc7Sjsg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20*c349dbc7Sjsg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21*c349dbc7Sjsg * SOFTWARE. 22*c349dbc7Sjsg * 23*c349dbc7Sjsg * Authors: 24*c349dbc7Sjsg * Anhua Xu 25*c349dbc7Sjsg * Kevin Tian <kevin.tian@intel.com> 26*c349dbc7Sjsg * 27*c349dbc7Sjsg * Contributors: 28*c349dbc7Sjsg * Min He <min.he@intel.com> 29*c349dbc7Sjsg * Bing Niu <bing.niu@intel.com> 30*c349dbc7Sjsg * Zhi Wang <zhi.a.wang@intel.com> 31*c349dbc7Sjsg * 32*c349dbc7Sjsg */ 33*c349dbc7Sjsg 34*c349dbc7Sjsg #ifndef __GVT_SCHED_POLICY__ 35*c349dbc7Sjsg #define __GVT_SCHED_POLICY__ 36*c349dbc7Sjsg 37*c349dbc7Sjsg struct intel_gvt; 38*c349dbc7Sjsg struct intel_vgpu; 39*c349dbc7Sjsg 40*c349dbc7Sjsg struct intel_gvt_sched_policy_ops { 41*c349dbc7Sjsg int (*init)(struct intel_gvt *gvt); 42*c349dbc7Sjsg void (*clean)(struct intel_gvt *gvt); 43*c349dbc7Sjsg int (*init_vgpu)(struct intel_vgpu *vgpu); 44*c349dbc7Sjsg void (*clean_vgpu)(struct intel_vgpu *vgpu); 45*c349dbc7Sjsg void (*start_schedule)(struct intel_vgpu *vgpu); 46*c349dbc7Sjsg void (*stop_schedule)(struct intel_vgpu *vgpu); 47*c349dbc7Sjsg }; 48*c349dbc7Sjsg 49*c349dbc7Sjsg void intel_gvt_schedule(struct intel_gvt *gvt); 50*c349dbc7Sjsg 51*c349dbc7Sjsg int intel_gvt_init_sched_policy(struct intel_gvt *gvt); 52*c349dbc7Sjsg 53*c349dbc7Sjsg void intel_gvt_clean_sched_policy(struct intel_gvt *gvt); 54*c349dbc7Sjsg 55*c349dbc7Sjsg int intel_vgpu_init_sched_policy(struct intel_vgpu *vgpu); 56*c349dbc7Sjsg 57*c349dbc7Sjsg void intel_vgpu_clean_sched_policy(struct intel_vgpu *vgpu); 58*c349dbc7Sjsg 59*c349dbc7Sjsg void intel_vgpu_start_schedule(struct intel_vgpu *vgpu); 60*c349dbc7Sjsg 61*c349dbc7Sjsg void intel_vgpu_stop_schedule(struct intel_vgpu *vgpu); 62*c349dbc7Sjsg 63*c349dbc7Sjsg void intel_gvt_kick_schedule(struct intel_gvt *gvt); 64*c349dbc7Sjsg 65*c349dbc7Sjsg #endif 66