1*1bb76ff1Sjsg /* SPDX-License-Identifier: MIT */ 2*1bb76ff1Sjsg /* 3*1bb76ff1Sjsg * Copyright © 2013-2021 Intel Corporation 4*1bb76ff1Sjsg */ 5*1bb76ff1Sjsg 6*1bb76ff1Sjsg #ifndef _INTEL_SBI_H_ 7*1bb76ff1Sjsg #define _INTEL_SBI_H_ 8*1bb76ff1Sjsg 9*1bb76ff1Sjsg #include <linux/types.h> 10*1bb76ff1Sjsg 11*1bb76ff1Sjsg struct drm_i915_private; 12*1bb76ff1Sjsg 13*1bb76ff1Sjsg enum intel_sbi_destination { 14*1bb76ff1Sjsg SBI_ICLK, 15*1bb76ff1Sjsg SBI_MPHY, 16*1bb76ff1Sjsg }; 17*1bb76ff1Sjsg 18*1bb76ff1Sjsg u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg, 19*1bb76ff1Sjsg enum intel_sbi_destination destination); 20*1bb76ff1Sjsg void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value, 21*1bb76ff1Sjsg enum intel_sbi_destination destination); 22*1bb76ff1Sjsg 23*1bb76ff1Sjsg #endif /* _INTEL_SBI_H_ */ 24