1 /* $OpenBSD: evergreen.c,v 1.19 2015/04/18 14:47:35 jsg Exp $ */ 2 /* 3 * Copyright 2010 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Alex Deucher 24 */ 25 #include <dev/pci/drm/drmP.h> 26 #include "radeon.h" 27 #include "radeon_asic.h" 28 #include <dev/pci/drm/radeon_drm.h> 29 #include "evergreend.h" 30 #include "atom.h" 31 #include "avivod.h" 32 #include "evergreen_reg.h" 33 #include "evergreen_blit_shaders.h" 34 35 #define EVERGREEN_PFP_UCODE_SIZE 1120 36 #define EVERGREEN_PM4_UCODE_SIZE 1376 37 38 static const u32 crtc_offsets[6] = 39 { 40 EVERGREEN_CRTC0_REGISTER_OFFSET, 41 EVERGREEN_CRTC1_REGISTER_OFFSET, 42 EVERGREEN_CRTC2_REGISTER_OFFSET, 43 EVERGREEN_CRTC3_REGISTER_OFFSET, 44 EVERGREEN_CRTC4_REGISTER_OFFSET, 45 EVERGREEN_CRTC5_REGISTER_OFFSET 46 }; 47 48 static void evergreen_gpu_init(struct radeon_device *rdev); 49 void evergreen_fini(struct radeon_device *rdev); 50 void evergreen_pcie_gen2_enable(struct radeon_device *rdev); 51 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 52 int ring, u32 cp_int_cntl); 53 54 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 55 unsigned *bankh, unsigned *mtaspect, 56 unsigned *tile_split) 57 { 58 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 59 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 60 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 61 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 62 switch (*bankw) { 63 default: 64 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break; 65 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break; 66 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break; 67 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break; 68 } 69 switch (*bankh) { 70 default: 71 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break; 72 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break; 73 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break; 74 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break; 75 } 76 switch (*mtaspect) { 77 default: 78 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break; 79 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break; 80 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break; 81 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break; 82 } 83 } 84 85 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) 86 { 87 pcireg_t ctl, v; 88 int off; 89 90 if (pci_get_capability(rdev->pc, rdev->pa_tag, PCI_CAP_PCIEXPRESS, 91 &off, &ctl) == 0) 92 return; 93 94 ctl = pci_conf_read(rdev->pc, rdev->pa_tag, off + PCI_PCIE_DCSR); 95 96 v = (ctl & PCI_PCIE_DCSR_MPS) >> 12; 97 98 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it 99 * to avoid hangs or perfomance issues 100 */ 101 if ((v == 0) || (v == 6) || (v == 7)) { 102 ctl &= ~PCI_PCIE_DCSR_MPS; 103 ctl |= (2 << 12); 104 pci_conf_write(rdev->pc, rdev->pa_tag, off + PCI_PCIE_DCSR, ctl); 105 } 106 } 107 108 static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc) 109 { 110 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) 111 return true; 112 else 113 return false; 114 } 115 116 static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc) 117 { 118 u32 pos1, pos2; 119 120 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); 121 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); 122 123 if (pos1 != pos2) 124 return true; 125 else 126 return false; 127 } 128 129 /** 130 * dce4_wait_for_vblank - vblank wait asic callback. 131 * 132 * @rdev: radeon_device pointer 133 * @crtc: crtc to wait for vblank on 134 * 135 * Wait for vblank on the requested crtc (evergreen+). 136 */ 137 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) 138 { 139 unsigned i = 0; 140 141 if (crtc >= rdev->num_crtc) 142 return; 143 144 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) 145 return; 146 147 /* depending on when we hit vblank, we may be close to active; if so, 148 * wait for another frame. 149 */ 150 while (dce4_is_in_vblank(rdev, crtc)) { 151 if (i++ % 100 == 0) { 152 if (!dce4_is_counter_moving(rdev, crtc)) 153 break; 154 } 155 } 156 157 while (!dce4_is_in_vblank(rdev, crtc)) { 158 if (i++ % 100 == 0) { 159 if (!dce4_is_counter_moving(rdev, crtc)) 160 break; 161 } 162 } 163 } 164 165 /** 166 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback. 167 * 168 * @rdev: radeon_device pointer 169 * @crtc: crtc to prepare for pageflip on 170 * 171 * Pre-pageflip callback (evergreen+). 172 * Enables the pageflip irq (vblank irq). 173 */ 174 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc) 175 { 176 /* enable the pflip int */ 177 radeon_irq_kms_pflip_irq_get(rdev, crtc); 178 } 179 180 /** 181 * evergreen_post_page_flip - pos-pageflip callback. 182 * 183 * @rdev: radeon_device pointer 184 * @crtc: crtc to cleanup pageflip on 185 * 186 * Post-pageflip callback (evergreen+). 187 * Disables the pageflip irq (vblank irq). 188 */ 189 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc) 190 { 191 /* disable the pflip int */ 192 radeon_irq_kms_pflip_irq_put(rdev, crtc); 193 } 194 195 /** 196 * evergreen_page_flip - pageflip callback. 197 * 198 * @rdev: radeon_device pointer 199 * @crtc_id: crtc to cleanup pageflip on 200 * @crtc_base: new address of the crtc (GPU MC address) 201 * 202 * Does the actual pageflip (evergreen+). 203 * During vblank we take the crtc lock and wait for the update_pending 204 * bit to go high, when it does, we release the lock, and allow the 205 * double buffered update to take place. 206 * Returns the current update pending status. 207 */ 208 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 209 { 210 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 211 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); 212 int i; 213 214 /* Lock the graphics update lock */ 215 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; 216 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 217 218 /* update the scanout addresses */ 219 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 220 upper_32_bits(crtc_base)); 221 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 222 (u32)crtc_base); 223 224 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 225 upper_32_bits(crtc_base)); 226 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 227 (u32)crtc_base); 228 229 /* Wait for update_pending to go high. */ 230 for (i = 0; i < rdev->usec_timeout; i++) { 231 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) 232 break; 233 udelay(1); 234 } 235 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 236 237 /* Unlock the lock, so double-buffering can take place inside vblank */ 238 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; 239 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 240 241 /* Return current update_pending status: */ 242 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING; 243 } 244 245 /* get temperature in millidegrees */ 246 int evergreen_get_temp(struct radeon_device *rdev) 247 { 248 u32 temp, toffset; 249 int actual_temp = 0; 250 251 if (rdev->family == CHIP_JUNIPER) { 252 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> 253 TOFFSET_SHIFT; 254 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> 255 TS0_ADC_DOUT_SHIFT; 256 257 if (toffset & 0x100) 258 actual_temp = temp / 2 - (0x200 - toffset); 259 else 260 actual_temp = temp / 2 + toffset; 261 262 actual_temp = actual_temp * 1000; 263 264 } else { 265 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 266 ASIC_T_SHIFT; 267 268 if (temp & 0x400) 269 actual_temp = -256; 270 else if (temp & 0x200) 271 actual_temp = 255; 272 else if (temp & 0x100) { 273 actual_temp = temp & 0x1ff; 274 actual_temp |= ~0x1ff; 275 } else 276 actual_temp = temp & 0xff; 277 278 actual_temp = (actual_temp * 1000) / 2; 279 } 280 281 return actual_temp; 282 } 283 284 int sumo_get_temp(struct radeon_device *rdev) 285 { 286 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; 287 int actual_temp = temp - 49; 288 289 return actual_temp * 1000; 290 } 291 292 /** 293 * sumo_pm_init_profile - Initialize power profiles callback. 294 * 295 * @rdev: radeon_device pointer 296 * 297 * Initialize the power states used in profile mode 298 * (sumo, trinity, SI). 299 * Used for profile mode only. 300 */ 301 void sumo_pm_init_profile(struct radeon_device *rdev) 302 { 303 int idx; 304 305 /* default */ 306 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 307 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 308 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 309 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 310 311 /* low,mid sh/mh */ 312 if (rdev->flags & RADEON_IS_MOBILITY) 313 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 314 else 315 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 316 317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 321 322 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 323 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 324 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 326 327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 331 332 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 333 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 334 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 336 337 /* high sh/mh */ 338 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 339 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 340 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 341 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 342 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 343 rdev->pm.power_state[idx].num_clock_modes - 1; 344 345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 346 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 349 rdev->pm.power_state[idx].num_clock_modes - 1; 350 } 351 352 /** 353 * btc_pm_init_profile - Initialize power profiles callback. 354 * 355 * @rdev: radeon_device pointer 356 * 357 * Initialize the power states used in profile mode 358 * (BTC, cayman). 359 * Used for profile mode only. 360 */ 361 void btc_pm_init_profile(struct radeon_device *rdev) 362 { 363 int idx; 364 365 /* default */ 366 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 367 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 370 /* starting with BTC, there is one state that is used for both 371 * MH and SH. Difference is that we always use the high clock index for 372 * mclk. 373 */ 374 if (rdev->flags & RADEON_IS_MOBILITY) 375 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 376 else 377 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 378 /* low sh */ 379 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 380 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 381 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 382 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 383 /* mid sh */ 384 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 385 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 386 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 387 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 388 /* high sh */ 389 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 390 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 391 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 392 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 393 /* low mh */ 394 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 395 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 396 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 397 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 398 /* mid mh */ 399 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 400 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 401 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 402 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 403 /* high mh */ 404 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 405 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 406 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 407 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 408 } 409 410 /** 411 * evergreen_pm_misc - set additional pm hw parameters callback. 412 * 413 * @rdev: radeon_device pointer 414 * 415 * Set non-clock parameters associated with a power state 416 * (voltage, etc.) (evergreen+). 417 */ 418 void evergreen_pm_misc(struct radeon_device *rdev) 419 { 420 int req_ps_idx = rdev->pm.requested_power_state_index; 421 int req_cm_idx = rdev->pm.requested_clock_mode_index; 422 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 423 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 424 425 if (voltage->type == VOLTAGE_SW) { 426 /* 0xff01 is a flag rather then an actual voltage */ 427 if (voltage->voltage == 0xff01) 428 return; 429 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { 430 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 431 rdev->pm.current_vddc = voltage->voltage; 432 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage); 433 } 434 435 /* starting with BTC, there is one state that is used for both 436 * MH and SH. Difference is that we always use the high clock index for 437 * mclk and vddci. 438 */ 439 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 440 (rdev->family >= CHIP_BARTS) && 441 rdev->pm.active_crtc_count && 442 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 443 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 444 voltage = &rdev->pm.power_state[req_ps_idx]. 445 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage; 446 447 /* 0xff01 is a flag rather then an actual voltage */ 448 if (voltage->vddci == 0xff01) 449 return; 450 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { 451 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); 452 rdev->pm.current_vddci = voltage->vddci; 453 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci); 454 } 455 } 456 } 457 458 /** 459 * evergreen_pm_prepare - pre-power state change callback. 460 * 461 * @rdev: radeon_device pointer 462 * 463 * Prepare for a power state change (evergreen+). 464 */ 465 void evergreen_pm_prepare(struct radeon_device *rdev) 466 { 467 struct drm_device *ddev = rdev->ddev; 468 struct drm_crtc *crtc; 469 struct radeon_crtc *radeon_crtc; 470 u32 tmp; 471 472 /* disable any active CRTCs */ 473 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 474 radeon_crtc = to_radeon_crtc(crtc); 475 if (radeon_crtc->enabled) { 476 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); 477 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 478 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 479 } 480 } 481 } 482 483 /** 484 * evergreen_pm_finish - post-power state change callback. 485 * 486 * @rdev: radeon_device pointer 487 * 488 * Clean up after a power state change (evergreen+). 489 */ 490 void evergreen_pm_finish(struct radeon_device *rdev) 491 { 492 struct drm_device *ddev = rdev->ddev; 493 struct drm_crtc *crtc; 494 struct radeon_crtc *radeon_crtc; 495 u32 tmp; 496 497 /* enable any active CRTCs */ 498 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 499 radeon_crtc = to_radeon_crtc(crtc); 500 if (radeon_crtc->enabled) { 501 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); 502 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 503 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 504 } 505 } 506 } 507 508 /** 509 * evergreen_hpd_sense - hpd sense callback. 510 * 511 * @rdev: radeon_device pointer 512 * @hpd: hpd (hotplug detect) pin 513 * 514 * Checks if a digital monitor is connected (evergreen+). 515 * Returns true if connected, false if not connected. 516 */ 517 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 518 { 519 bool connected = false; 520 521 switch (hpd) { 522 case RADEON_HPD_1: 523 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 524 connected = true; 525 break; 526 case RADEON_HPD_2: 527 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 528 connected = true; 529 break; 530 case RADEON_HPD_3: 531 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 532 connected = true; 533 break; 534 case RADEON_HPD_4: 535 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 536 connected = true; 537 break; 538 case RADEON_HPD_5: 539 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 540 connected = true; 541 break; 542 case RADEON_HPD_6: 543 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 544 connected = true; 545 break; 546 default: 547 break; 548 } 549 550 return connected; 551 } 552 553 /** 554 * evergreen_hpd_set_polarity - hpd set polarity callback. 555 * 556 * @rdev: radeon_device pointer 557 * @hpd: hpd (hotplug detect) pin 558 * 559 * Set the polarity of the hpd pin (evergreen+). 560 */ 561 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 562 enum radeon_hpd_id hpd) 563 { 564 u32 tmp; 565 bool connected = evergreen_hpd_sense(rdev, hpd); 566 567 switch (hpd) { 568 case RADEON_HPD_1: 569 tmp = RREG32(DC_HPD1_INT_CONTROL); 570 if (connected) 571 tmp &= ~DC_HPDx_INT_POLARITY; 572 else 573 tmp |= DC_HPDx_INT_POLARITY; 574 WREG32(DC_HPD1_INT_CONTROL, tmp); 575 break; 576 case RADEON_HPD_2: 577 tmp = RREG32(DC_HPD2_INT_CONTROL); 578 if (connected) 579 tmp &= ~DC_HPDx_INT_POLARITY; 580 else 581 tmp |= DC_HPDx_INT_POLARITY; 582 WREG32(DC_HPD2_INT_CONTROL, tmp); 583 break; 584 case RADEON_HPD_3: 585 tmp = RREG32(DC_HPD3_INT_CONTROL); 586 if (connected) 587 tmp &= ~DC_HPDx_INT_POLARITY; 588 else 589 tmp |= DC_HPDx_INT_POLARITY; 590 WREG32(DC_HPD3_INT_CONTROL, tmp); 591 break; 592 case RADEON_HPD_4: 593 tmp = RREG32(DC_HPD4_INT_CONTROL); 594 if (connected) 595 tmp &= ~DC_HPDx_INT_POLARITY; 596 else 597 tmp |= DC_HPDx_INT_POLARITY; 598 WREG32(DC_HPD4_INT_CONTROL, tmp); 599 break; 600 case RADEON_HPD_5: 601 tmp = RREG32(DC_HPD5_INT_CONTROL); 602 if (connected) 603 tmp &= ~DC_HPDx_INT_POLARITY; 604 else 605 tmp |= DC_HPDx_INT_POLARITY; 606 WREG32(DC_HPD5_INT_CONTROL, tmp); 607 break; 608 case RADEON_HPD_6: 609 tmp = RREG32(DC_HPD6_INT_CONTROL); 610 if (connected) 611 tmp &= ~DC_HPDx_INT_POLARITY; 612 else 613 tmp |= DC_HPDx_INT_POLARITY; 614 WREG32(DC_HPD6_INT_CONTROL, tmp); 615 break; 616 default: 617 break; 618 } 619 } 620 621 /** 622 * evergreen_hpd_init - hpd setup callback. 623 * 624 * @rdev: radeon_device pointer 625 * 626 * Setup the hpd pins used by the card (evergreen+). 627 * Enable the pin, set the polarity, and enable the hpd interrupts. 628 */ 629 void evergreen_hpd_init(struct radeon_device *rdev) 630 { 631 struct drm_device *dev = rdev->ddev; 632 struct drm_connector *connector; 633 unsigned enabled = 0; 634 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | 635 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; 636 637 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 638 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 639 640 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 641 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 642 /* don't try to enable hpd on eDP or LVDS avoid breaking the 643 * aux dp channel on imac and help (but not completely fix) 644 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 645 * also avoid interrupt storms during dpms. 646 */ 647 continue; 648 } 649 switch (radeon_connector->hpd.hpd) { 650 case RADEON_HPD_1: 651 WREG32(DC_HPD1_CONTROL, tmp); 652 break; 653 case RADEON_HPD_2: 654 WREG32(DC_HPD2_CONTROL, tmp); 655 break; 656 case RADEON_HPD_3: 657 WREG32(DC_HPD3_CONTROL, tmp); 658 break; 659 case RADEON_HPD_4: 660 WREG32(DC_HPD4_CONTROL, tmp); 661 break; 662 case RADEON_HPD_5: 663 WREG32(DC_HPD5_CONTROL, tmp); 664 break; 665 case RADEON_HPD_6: 666 WREG32(DC_HPD6_CONTROL, tmp); 667 break; 668 default: 669 break; 670 } 671 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 672 enabled |= 1 << radeon_connector->hpd.hpd; 673 } 674 radeon_irq_kms_enable_hpd(rdev, enabled); 675 } 676 677 /** 678 * evergreen_hpd_fini - hpd tear down callback. 679 * 680 * @rdev: radeon_device pointer 681 * 682 * Tear down the hpd pins used by the card (evergreen+). 683 * Disable the hpd interrupts. 684 */ 685 void evergreen_hpd_fini(struct radeon_device *rdev) 686 { 687 struct drm_device *dev = rdev->ddev; 688 struct drm_connector *connector; 689 unsigned disabled = 0; 690 691 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 692 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 693 switch (radeon_connector->hpd.hpd) { 694 case RADEON_HPD_1: 695 WREG32(DC_HPD1_CONTROL, 0); 696 break; 697 case RADEON_HPD_2: 698 WREG32(DC_HPD2_CONTROL, 0); 699 break; 700 case RADEON_HPD_3: 701 WREG32(DC_HPD3_CONTROL, 0); 702 break; 703 case RADEON_HPD_4: 704 WREG32(DC_HPD4_CONTROL, 0); 705 break; 706 case RADEON_HPD_5: 707 WREG32(DC_HPD5_CONTROL, 0); 708 break; 709 case RADEON_HPD_6: 710 WREG32(DC_HPD6_CONTROL, 0); 711 break; 712 default: 713 break; 714 } 715 disabled |= 1 << radeon_connector->hpd.hpd; 716 } 717 radeon_irq_kms_disable_hpd(rdev, disabled); 718 } 719 720 /* watermark setup */ 721 722 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, 723 struct radeon_crtc *radeon_crtc, 724 struct drm_display_mode *mode, 725 struct drm_display_mode *other_mode) 726 { 727 u32 tmp, buffer_alloc, i; 728 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; 729 /* 730 * Line Buffer Setup 731 * There are 3 line buffers, each one shared by 2 display controllers. 732 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 733 * the display controllers. The paritioning is done via one of four 734 * preset allocations specified in bits 2:0: 735 * first display controller 736 * 0 - first half of lb (3840 * 2) 737 * 1 - first 3/4 of lb (5760 * 2) 738 * 2 - whole lb (7680 * 2), other crtc must be disabled 739 * 3 - first 1/4 of lb (1920 * 2) 740 * second display controller 741 * 4 - second half of lb (3840 * 2) 742 * 5 - second 3/4 of lb (5760 * 2) 743 * 6 - whole lb (7680 * 2), other crtc must be disabled 744 * 7 - last 1/4 of lb (1920 * 2) 745 */ 746 /* this can get tricky if we have two large displays on a paired group 747 * of crtcs. Ideally for multiple large displays we'd assign them to 748 * non-linked crtcs for maximum line buffer allocation. 749 */ 750 if (radeon_crtc->base.enabled && mode) { 751 if (other_mode) { 752 tmp = 0; /* 1/2 */ 753 buffer_alloc = 1; 754 } else { 755 tmp = 2; /* whole */ 756 buffer_alloc = 2; 757 } 758 } else { 759 tmp = 0; 760 buffer_alloc = 0; 761 } 762 763 /* second controller of the pair uses second half of the lb */ 764 if (radeon_crtc->crtc_id % 2) 765 tmp += 4; 766 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); 767 768 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 769 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 770 DMIF_BUFFERS_ALLOCATED(buffer_alloc)); 771 for (i = 0; i < rdev->usec_timeout; i++) { 772 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 773 DMIF_BUFFERS_ALLOCATED_COMPLETED) 774 break; 775 udelay(1); 776 } 777 } 778 779 if (radeon_crtc->base.enabled && mode) { 780 switch (tmp) { 781 case 0: 782 case 4: 783 default: 784 if (ASIC_IS_DCE5(rdev)) 785 return 4096 * 2; 786 else 787 return 3840 * 2; 788 case 1: 789 case 5: 790 if (ASIC_IS_DCE5(rdev)) 791 return 6144 * 2; 792 else 793 return 5760 * 2; 794 case 2: 795 case 6: 796 if (ASIC_IS_DCE5(rdev)) 797 return 8192 * 2; 798 else 799 return 7680 * 2; 800 case 3: 801 case 7: 802 if (ASIC_IS_DCE5(rdev)) 803 return 2048 * 2; 804 else 805 return 1920 * 2; 806 } 807 } 808 809 /* controller not enabled, so no lb used */ 810 return 0; 811 } 812 813 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) 814 { 815 u32 tmp = RREG32(MC_SHARED_CHMAP); 816 817 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 818 case 0: 819 default: 820 return 1; 821 case 1: 822 return 2; 823 case 2: 824 return 4; 825 case 3: 826 return 8; 827 } 828 } 829 830 struct evergreen_wm_params { 831 u32 dram_channels; /* number of dram channels */ 832 u32 yclk; /* bandwidth per dram data pin in kHz */ 833 u32 sclk; /* engine clock in kHz */ 834 u32 disp_clk; /* display clock in kHz */ 835 u32 src_width; /* viewport width */ 836 u32 active_time; /* active display time in ns */ 837 u32 blank_time; /* blank time in ns */ 838 bool interlaced; /* mode is interlaced */ 839 fixed20_12 vsc; /* vertical scale ratio */ 840 u32 num_heads; /* number of active crtcs */ 841 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 842 u32 lb_size; /* line buffer allocated to pipe */ 843 u32 vtaps; /* vertical scaler taps */ 844 }; 845 846 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) 847 { 848 /* Calculate DRAM Bandwidth and the part allocated to display. */ 849 fixed20_12 dram_efficiency; /* 0.7 */ 850 fixed20_12 yclk, dram_channels, bandwidth; 851 fixed20_12 a; 852 853 a.full = dfixed_const(1000); 854 yclk.full = dfixed_const(wm->yclk); 855 yclk.full = dfixed_div(yclk, a); 856 dram_channels.full = dfixed_const(wm->dram_channels * 4); 857 a.full = dfixed_const(10); 858 dram_efficiency.full = dfixed_const(7); 859 dram_efficiency.full = dfixed_div(dram_efficiency, a); 860 bandwidth.full = dfixed_mul(dram_channels, yclk); 861 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 862 863 return dfixed_trunc(bandwidth); 864 } 865 866 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) 867 { 868 /* Calculate DRAM Bandwidth and the part allocated to display. */ 869 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 870 fixed20_12 yclk, dram_channels, bandwidth; 871 fixed20_12 a; 872 873 a.full = dfixed_const(1000); 874 yclk.full = dfixed_const(wm->yclk); 875 yclk.full = dfixed_div(yclk, a); 876 dram_channels.full = dfixed_const(wm->dram_channels * 4); 877 a.full = dfixed_const(10); 878 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 879 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 880 bandwidth.full = dfixed_mul(dram_channels, yclk); 881 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 882 883 return dfixed_trunc(bandwidth); 884 } 885 886 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) 887 { 888 /* Calculate the display Data return Bandwidth */ 889 fixed20_12 return_efficiency; /* 0.8 */ 890 fixed20_12 sclk, bandwidth; 891 fixed20_12 a; 892 893 a.full = dfixed_const(1000); 894 sclk.full = dfixed_const(wm->sclk); 895 sclk.full = dfixed_div(sclk, a); 896 a.full = dfixed_const(10); 897 return_efficiency.full = dfixed_const(8); 898 return_efficiency.full = dfixed_div(return_efficiency, a); 899 a.full = dfixed_const(32); 900 bandwidth.full = dfixed_mul(a, sclk); 901 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 902 903 return dfixed_trunc(bandwidth); 904 } 905 906 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) 907 { 908 /* Calculate the DMIF Request Bandwidth */ 909 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 910 fixed20_12 disp_clk, bandwidth; 911 fixed20_12 a; 912 913 a.full = dfixed_const(1000); 914 disp_clk.full = dfixed_const(wm->disp_clk); 915 disp_clk.full = dfixed_div(disp_clk, a); 916 a.full = dfixed_const(10); 917 disp_clk_request_efficiency.full = dfixed_const(8); 918 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 919 a.full = dfixed_const(32); 920 bandwidth.full = dfixed_mul(a, disp_clk); 921 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency); 922 923 return dfixed_trunc(bandwidth); 924 } 925 926 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm) 927 { 928 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 929 u32 dram_bandwidth = evergreen_dram_bandwidth(wm); 930 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm); 931 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm); 932 933 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 934 } 935 936 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm) 937 { 938 /* Calculate the display mode Average Bandwidth 939 * DisplayMode should contain the source and destination dimensions, 940 * timing, etc. 941 */ 942 fixed20_12 bpp; 943 fixed20_12 line_time; 944 fixed20_12 src_width; 945 fixed20_12 bandwidth; 946 fixed20_12 a; 947 948 a.full = dfixed_const(1000); 949 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 950 line_time.full = dfixed_div(line_time, a); 951 bpp.full = dfixed_const(wm->bytes_per_pixel); 952 src_width.full = dfixed_const(wm->src_width); 953 bandwidth.full = dfixed_mul(src_width, bpp); 954 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 955 bandwidth.full = dfixed_div(bandwidth, line_time); 956 957 return dfixed_trunc(bandwidth); 958 } 959 960 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm) 961 { 962 /* First calcualte the latency in ns */ 963 u32 mc_latency = 2000; /* 2000 ns. */ 964 u32 available_bandwidth = evergreen_available_bandwidth(wm); 965 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 966 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 967 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 968 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 969 (wm->num_heads * cursor_line_pair_return_time); 970 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 971 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 972 fixed20_12 a, b, c; 973 974 if (wm->num_heads == 0) 975 return 0; 976 977 a.full = dfixed_const(2); 978 b.full = dfixed_const(1); 979 if ((wm->vsc.full > a.full) || 980 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 981 (wm->vtaps >= 5) || 982 ((wm->vsc.full >= a.full) && wm->interlaced)) 983 max_src_lines_per_dst_line = 4; 984 else 985 max_src_lines_per_dst_line = 2; 986 987 a.full = dfixed_const(available_bandwidth); 988 b.full = dfixed_const(wm->num_heads); 989 a.full = dfixed_div(a, b); 990 991 b.full = dfixed_const(1000); 992 c.full = dfixed_const(wm->disp_clk); 993 b.full = dfixed_div(c, b); 994 c.full = dfixed_const(wm->bytes_per_pixel); 995 b.full = dfixed_mul(b, c); 996 997 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b)); 998 999 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1000 b.full = dfixed_const(1000); 1001 c.full = dfixed_const(lb_fill_bw); 1002 b.full = dfixed_div(c, b); 1003 a.full = dfixed_div(a, b); 1004 line_fill_time = dfixed_trunc(a); 1005 1006 if (line_fill_time < wm->active_time) 1007 return latency; 1008 else 1009 return latency + (line_fill_time - wm->active_time); 1010 1011 } 1012 1013 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm) 1014 { 1015 if (evergreen_average_bandwidth(wm) <= 1016 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) 1017 return true; 1018 else 1019 return false; 1020 }; 1021 1022 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm) 1023 { 1024 if (evergreen_average_bandwidth(wm) <= 1025 (evergreen_available_bandwidth(wm) / wm->num_heads)) 1026 return true; 1027 else 1028 return false; 1029 }; 1030 1031 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm) 1032 { 1033 u32 lb_partitions = wm->lb_size / wm->src_width; 1034 u32 line_time = wm->active_time + wm->blank_time; 1035 u32 latency_tolerant_lines; 1036 u32 latency_hiding; 1037 fixed20_12 a; 1038 1039 a.full = dfixed_const(1); 1040 if (wm->vsc.full > a.full) 1041 latency_tolerant_lines = 1; 1042 else { 1043 if (lb_partitions <= (wm->vtaps + 1)) 1044 latency_tolerant_lines = 1; 1045 else 1046 latency_tolerant_lines = 2; 1047 } 1048 1049 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1050 1051 if (evergreen_latency_watermark(wm) <= latency_hiding) 1052 return true; 1053 else 1054 return false; 1055 } 1056 1057 static void evergreen_program_watermarks(struct radeon_device *rdev, 1058 struct radeon_crtc *radeon_crtc, 1059 u32 lb_size, u32 num_heads) 1060 { 1061 struct drm_display_mode *mode = &radeon_crtc->base.mode; 1062 struct evergreen_wm_params wm; 1063 u32 pixel_period; 1064 u32 line_time = 0; 1065 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1066 u32 priority_a_mark = 0, priority_b_mark = 0; 1067 u32 priority_a_cnt = PRIORITY_OFF; 1068 u32 priority_b_cnt = PRIORITY_OFF; 1069 u32 pipe_offset = radeon_crtc->crtc_id * 16; 1070 u32 tmp, arb_control3; 1071 fixed20_12 a, b, c; 1072 1073 if (radeon_crtc->base.enabled && num_heads && mode) { 1074 pixel_period = 1000000 / (u32)mode->clock; 1075 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1076 priority_a_cnt = 0; 1077 priority_b_cnt = 0; 1078 1079 wm.yclk = rdev->pm.current_mclk * 10; 1080 wm.sclk = rdev->pm.current_sclk * 10; 1081 wm.disp_clk = mode->clock; 1082 wm.src_width = mode->crtc_hdisplay; 1083 wm.active_time = mode->crtc_hdisplay * pixel_period; 1084 wm.blank_time = line_time - wm.active_time; 1085 wm.interlaced = false; 1086 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1087 wm.interlaced = true; 1088 wm.vsc = radeon_crtc->vsc; 1089 wm.vtaps = 1; 1090 if (radeon_crtc->rmx_type != RMX_OFF) 1091 wm.vtaps = 2; 1092 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1093 wm.lb_size = lb_size; 1094 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); 1095 wm.num_heads = num_heads; 1096 1097 /* set for high clocks */ 1098 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535); 1099 /* set for low clocks */ 1100 /* wm.yclk = low clk; wm.sclk = low clk */ 1101 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535); 1102 1103 /* possibly force display priority to high */ 1104 /* should really do this at mode validation time... */ 1105 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || 1106 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) || 1107 !evergreen_check_latency_hiding(&wm) || 1108 (rdev->disp_priority == 2)) { 1109 DRM_DEBUG_KMS("force priority to high\n"); 1110 priority_a_cnt |= PRIORITY_ALWAYS_ON; 1111 priority_b_cnt |= PRIORITY_ALWAYS_ON; 1112 } 1113 1114 a.full = dfixed_const(1000); 1115 b.full = dfixed_const(mode->clock); 1116 b.full = dfixed_div(b, a); 1117 c.full = dfixed_const(latency_watermark_a); 1118 c.full = dfixed_mul(c, b); 1119 c.full = dfixed_mul(c, radeon_crtc->hsc); 1120 c.full = dfixed_div(c, a); 1121 a.full = dfixed_const(16); 1122 c.full = dfixed_div(c, a); 1123 priority_a_mark = dfixed_trunc(c); 1124 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 1125 1126 a.full = dfixed_const(1000); 1127 b.full = dfixed_const(mode->clock); 1128 b.full = dfixed_div(b, a); 1129 c.full = dfixed_const(latency_watermark_b); 1130 c.full = dfixed_mul(c, b); 1131 c.full = dfixed_mul(c, radeon_crtc->hsc); 1132 c.full = dfixed_div(c, a); 1133 a.full = dfixed_const(16); 1134 c.full = dfixed_div(c, a); 1135 priority_b_mark = dfixed_trunc(c); 1136 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 1137 } 1138 1139 /* select wm A */ 1140 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); 1141 tmp = arb_control3; 1142 tmp &= ~LATENCY_WATERMARK_MASK(3); 1143 tmp |= LATENCY_WATERMARK_MASK(1); 1144 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); 1145 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 1146 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 1147 LATENCY_HIGH_WATERMARK(line_time))); 1148 /* select wm B */ 1149 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); 1150 tmp &= ~LATENCY_WATERMARK_MASK(3); 1151 tmp |= LATENCY_WATERMARK_MASK(2); 1152 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); 1153 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, 1154 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 1155 LATENCY_HIGH_WATERMARK(line_time))); 1156 /* restore original selection */ 1157 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); 1158 1159 /* write the priority marks */ 1160 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 1161 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 1162 1163 } 1164 1165 /** 1166 * evergreen_bandwidth_update - update display watermarks callback. 1167 * 1168 * @rdev: radeon_device pointer 1169 * 1170 * Update the display watermarks based on the requested mode(s) 1171 * (evergreen+). 1172 */ 1173 void evergreen_bandwidth_update(struct radeon_device *rdev) 1174 { 1175 struct drm_display_mode *mode0 = NULL; 1176 struct drm_display_mode *mode1 = NULL; 1177 u32 num_heads = 0, lb_size; 1178 int i; 1179 1180 radeon_update_display_priority(rdev); 1181 1182 for (i = 0; i < rdev->num_crtc; i++) { 1183 if (rdev->mode_info.crtcs[i]->base.enabled) 1184 num_heads++; 1185 } 1186 for (i = 0; i < rdev->num_crtc; i += 2) { 1187 mode0 = &rdev->mode_info.crtcs[i]->base.mode; 1188 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; 1189 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); 1190 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); 1191 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); 1192 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); 1193 } 1194 } 1195 1196 /** 1197 * evergreen_mc_wait_for_idle - wait for MC idle callback. 1198 * 1199 * @rdev: radeon_device pointer 1200 * 1201 * Wait for the MC (memory controller) to be idle. 1202 * (evergreen+). 1203 * Returns 0 if the MC is idle, -1 if not. 1204 */ 1205 int evergreen_mc_wait_for_idle(struct radeon_device *rdev) 1206 { 1207 unsigned i; 1208 u32 tmp; 1209 1210 for (i = 0; i < rdev->usec_timeout; i++) { 1211 /* read MC_STATUS */ 1212 tmp = RREG32(SRBM_STATUS) & 0x1F00; 1213 if (!tmp) 1214 return 0; 1215 udelay(1); 1216 } 1217 return -1; 1218 } 1219 1220 /* 1221 * GART 1222 */ 1223 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) 1224 { 1225 unsigned i; 1226 u32 tmp; 1227 1228 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 1229 1230 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 1231 for (i = 0; i < rdev->usec_timeout; i++) { 1232 /* read MC_STATUS */ 1233 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 1234 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 1235 if (tmp == 2) { 1236 printk(KERN_WARNING "[drm] r600 flush TLB failed\n"); 1237 return; 1238 } 1239 if (tmp) { 1240 return; 1241 } 1242 udelay(1); 1243 } 1244 } 1245 1246 static int evergreen_pcie_gart_enable(struct radeon_device *rdev) 1247 { 1248 u32 tmp; 1249 int r; 1250 1251 if (rdev->gart.robj == NULL) { 1252 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 1253 return -EINVAL; 1254 } 1255 r = radeon_gart_table_vram_pin(rdev); 1256 if (r) 1257 return r; 1258 radeon_gart_restore(rdev); 1259 /* Setup L2 cache */ 1260 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1261 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1262 EFFECTIVE_L2_QUEUE_SIZE(7)); 1263 WREG32(VM_L2_CNTL2, 0); 1264 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 1265 /* Setup TLB control */ 1266 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1267 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1268 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 1269 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1270 if (rdev->flags & RADEON_IS_IGP) { 1271 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); 1272 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); 1273 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); 1274 } else { 1275 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1276 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1277 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1278 if ((rdev->family == CHIP_JUNIPER) || 1279 (rdev->family == CHIP_CYPRESS) || 1280 (rdev->family == CHIP_HEMLOCK) || 1281 (rdev->family == CHIP_BARTS)) 1282 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); 1283 } 1284 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1285 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1286 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1287 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1288 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 1289 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 1290 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 1291 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 1292 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 1293 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 1294 (u32)(rdev->dummy_page.addr >> 12)); 1295 WREG32(VM_CONTEXT1_CNTL, 0); 1296 1297 evergreen_pcie_gart_tlb_flush(rdev); 1298 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1299 (unsigned)(rdev->mc.gtt_size >> 20), 1300 (unsigned long long)rdev->gart.table_addr); 1301 rdev->gart.ready = true; 1302 return 0; 1303 } 1304 1305 static void evergreen_pcie_gart_disable(struct radeon_device *rdev) 1306 { 1307 u32 tmp; 1308 1309 /* Disable all tables */ 1310 WREG32(VM_CONTEXT0_CNTL, 0); 1311 WREG32(VM_CONTEXT1_CNTL, 0); 1312 1313 /* Setup L2 cache */ 1314 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 1315 EFFECTIVE_L2_QUEUE_SIZE(7)); 1316 WREG32(VM_L2_CNTL2, 0); 1317 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 1318 /* Setup TLB control */ 1319 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1320 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1321 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1322 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1323 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1324 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1325 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1326 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1327 radeon_gart_table_vram_unpin(rdev); 1328 } 1329 1330 static void evergreen_pcie_gart_fini(struct radeon_device *rdev) 1331 { 1332 evergreen_pcie_gart_disable(rdev); 1333 radeon_gart_table_vram_free(rdev); 1334 radeon_gart_fini(rdev); 1335 } 1336 1337 1338 static void evergreen_agp_enable(struct radeon_device *rdev) 1339 { 1340 u32 tmp; 1341 1342 /* Setup L2 cache */ 1343 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 1344 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 1345 EFFECTIVE_L2_QUEUE_SIZE(7)); 1346 WREG32(VM_L2_CNTL2, 0); 1347 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); 1348 /* Setup TLB control */ 1349 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 1350 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 1351 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 1352 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 1353 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 1354 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 1355 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 1356 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 1357 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 1358 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 1359 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 1360 WREG32(VM_CONTEXT0_CNTL, 0); 1361 WREG32(VM_CONTEXT1_CNTL, 0); 1362 } 1363 1364 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) 1365 { 1366 u32 crtc_enabled, tmp, frame_count, blackout; 1367 int i, j; 1368 1369 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 1370 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 1371 1372 /* disable VGA render */ 1373 WREG32(VGA_RENDER_CONTROL, 0); 1374 /* blank the display controllers */ 1375 for (i = 0; i < rdev->num_crtc; i++) { 1376 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; 1377 if (crtc_enabled) { 1378 save->crtc_enabled[i] = true; 1379 if (ASIC_IS_DCE6(rdev)) { 1380 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); 1381 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { 1382 radeon_wait_for_vblank(rdev, i); 1383 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 1384 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; 1385 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 1386 } 1387 } else { 1388 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 1389 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) { 1390 radeon_wait_for_vblank(rdev, i); 1391 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 1392 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 1393 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 1394 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 1395 } 1396 } 1397 /* wait for the next frame */ 1398 frame_count = radeon_get_vblank_counter(rdev, i); 1399 for (j = 0; j < rdev->usec_timeout; j++) { 1400 if (radeon_get_vblank_counter(rdev, i) != frame_count) 1401 break; 1402 udelay(1); 1403 } 1404 1405 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 1406 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 1407 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 1408 tmp &= ~EVERGREEN_CRTC_MASTER_EN; 1409 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 1410 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 1411 save->crtc_enabled[i] = false; 1412 /* ***** */ 1413 } else { 1414 save->crtc_enabled[i] = false; 1415 } 1416 } 1417 1418 radeon_mc_wait_for_idle(rdev); 1419 1420 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 1421 if ((blackout & BLACKOUT_MODE_MASK) != 1) { 1422 /* Block CPU access */ 1423 WREG32(BIF_FB_EN, 0); 1424 /* blackout the MC */ 1425 blackout &= ~BLACKOUT_MODE_MASK; 1426 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); 1427 } 1428 /* wait for the MC to settle */ 1429 udelay(100); 1430 1431 /* lock double buffered regs */ 1432 for (i = 0; i < rdev->num_crtc; i++) { 1433 if (save->crtc_enabled[i]) { 1434 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); 1435 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) { 1436 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; 1437 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); 1438 } 1439 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); 1440 if (!(tmp & 1)) { 1441 tmp |= 1; 1442 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 1443 } 1444 } 1445 } 1446 } 1447 1448 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 1449 { 1450 u32 tmp, frame_count; 1451 int i, j; 1452 1453 /* update crtc base addresses */ 1454 for (i = 0; i < rdev->num_crtc; i++) { 1455 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 1456 upper_32_bits(rdev->mc.vram_start)); 1457 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 1458 upper_32_bits(rdev->mc.vram_start)); 1459 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 1460 (u32)rdev->mc.vram_start); 1461 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 1462 (u32)rdev->mc.vram_start); 1463 } 1464 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 1465 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 1466 1467 /* unlock regs and wait for update */ 1468 for (i = 0; i < rdev->num_crtc; i++) { 1469 if (save->crtc_enabled[i]) { 1470 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); 1471 if ((tmp & 0x3) != 0) { 1472 tmp &= ~0x3; 1473 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 1474 } 1475 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); 1476 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) { 1477 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; 1478 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); 1479 } 1480 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); 1481 if (tmp & 1) { 1482 tmp &= ~1; 1483 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 1484 } 1485 for (j = 0; j < rdev->usec_timeout; j++) { 1486 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); 1487 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) 1488 break; 1489 udelay(1); 1490 } 1491 } 1492 } 1493 1494 /* unblackout the MC */ 1495 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); 1496 tmp &= ~BLACKOUT_MODE_MASK; 1497 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); 1498 /* allow CPU access */ 1499 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 1500 1501 for (i = 0; i < rdev->num_crtc; i++) { 1502 if (save->crtc_enabled[i]) { 1503 if (ASIC_IS_DCE6(rdev)) { 1504 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); 1505 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; 1506 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 1507 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 1508 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 1509 } else { 1510 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 1511 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; 1512 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 1513 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 1514 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 1515 } 1516 /* wait for the next frame */ 1517 frame_count = radeon_get_vblank_counter(rdev, i); 1518 for (j = 0; j < rdev->usec_timeout; j++) { 1519 if (radeon_get_vblank_counter(rdev, i) != frame_count) 1520 break; 1521 udelay(1); 1522 } 1523 } 1524 } 1525 /* Unlock vga access */ 1526 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 1527 mdelay(1); 1528 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1529 } 1530 1531 void evergreen_mc_program(struct radeon_device *rdev) 1532 { 1533 struct evergreen_mc_save save; 1534 u32 tmp; 1535 int i, j; 1536 1537 /* Initialize HDP */ 1538 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1539 WREG32((0x2c14 + j), 0x00000000); 1540 WREG32((0x2c18 + j), 0x00000000); 1541 WREG32((0x2c1c + j), 0x00000000); 1542 WREG32((0x2c20 + j), 0x00000000); 1543 WREG32((0x2c24 + j), 0x00000000); 1544 } 1545 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1546 1547 evergreen_mc_stop(rdev, &save); 1548 if (evergreen_mc_wait_for_idle(rdev)) { 1549 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1550 } 1551 /* Lockout access through VGA aperture*/ 1552 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1553 /* Update configuration */ 1554 if (rdev->flags & RADEON_IS_AGP) { 1555 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1556 /* VRAM before AGP */ 1557 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1558 rdev->mc.vram_start >> 12); 1559 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1560 rdev->mc.gtt_end >> 12); 1561 } else { 1562 /* VRAM after AGP */ 1563 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1564 rdev->mc.gtt_start >> 12); 1565 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1566 rdev->mc.vram_end >> 12); 1567 } 1568 } else { 1569 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1570 rdev->mc.vram_start >> 12); 1571 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1572 rdev->mc.vram_end >> 12); 1573 } 1574 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1575 /* llano/ontario only */ 1576 if ((rdev->family == CHIP_PALM) || 1577 (rdev->family == CHIP_SUMO) || 1578 (rdev->family == CHIP_SUMO2)) { 1579 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; 1580 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; 1581 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; 1582 WREG32(MC_FUS_VM_FB_OFFSET, tmp); 1583 } 1584 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1585 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1586 WREG32(MC_VM_FB_LOCATION, tmp); 1587 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1588 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 1589 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1590 if (rdev->flags & RADEON_IS_AGP) { 1591 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1592 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 1593 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1594 } else { 1595 WREG32(MC_VM_AGP_BASE, 0); 1596 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1597 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1598 } 1599 if (evergreen_mc_wait_for_idle(rdev)) { 1600 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1601 } 1602 evergreen_mc_resume(rdev, &save); 1603 /* we need to own VRAM, so turn off the VGA renderer here 1604 * to stop it overwriting our objects */ 1605 rv515_vga_render_disable(rdev); 1606 } 1607 1608 /* 1609 * CP. 1610 */ 1611 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1612 { 1613 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1614 u32 next_rptr; 1615 1616 /* set to DX10/11 mode */ 1617 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); 1618 radeon_ring_write(ring, 1); 1619 1620 if (ring->rptr_save_reg) { 1621 next_rptr = ring->wptr + 3 + 4; 1622 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1623 radeon_ring_write(ring, ((ring->rptr_save_reg - 1624 PACKET3_SET_CONFIG_REG_START) >> 2)); 1625 radeon_ring_write(ring, next_rptr); 1626 } else if (rdev->wb.enabled) { 1627 next_rptr = ring->wptr + 5 + 4; 1628 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 1629 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 1630 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 1631 radeon_ring_write(ring, next_rptr); 1632 radeon_ring_write(ring, 0); 1633 } 1634 1635 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1636 radeon_ring_write(ring, 1637 #ifdef __BIG_ENDIAN 1638 (2 << 0) | 1639 #endif 1640 (ib->gpu_addr & 0xFFFFFFFC)); 1641 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 1642 radeon_ring_write(ring, ib->length_dw); 1643 } 1644 1645 1646 static int evergreen_cp_load_microcode(struct radeon_device *rdev) 1647 { 1648 const __be32 *fw_data; 1649 int i; 1650 1651 if (!rdev->me_fw || !rdev->pfp_fw) 1652 return -EINVAL; 1653 1654 r700_cp_stop(rdev); 1655 WREG32(CP_RB_CNTL, 1656 #ifdef __BIG_ENDIAN 1657 BUF_SWAP_32BIT | 1658 #endif 1659 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 1660 1661 fw_data = (const __be32 *)rdev->pfp_fw; 1662 WREG32(CP_PFP_UCODE_ADDR, 0); 1663 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++) 1664 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1665 WREG32(CP_PFP_UCODE_ADDR, 0); 1666 1667 fw_data = (const __be32 *)rdev->me_fw; 1668 WREG32(CP_ME_RAM_WADDR, 0); 1669 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++) 1670 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1671 1672 WREG32(CP_PFP_UCODE_ADDR, 0); 1673 WREG32(CP_ME_RAM_WADDR, 0); 1674 WREG32(CP_ME_RAM_RADDR, 0); 1675 return 0; 1676 } 1677 1678 static int evergreen_cp_start(struct radeon_device *rdev) 1679 { 1680 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1681 int r, i; 1682 uint32_t cp_me; 1683 1684 r = radeon_ring_lock(rdev, ring, 7); 1685 if (r) { 1686 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1687 return r; 1688 } 1689 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1690 radeon_ring_write(ring, 0x1); 1691 radeon_ring_write(ring, 0x0); 1692 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); 1693 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1694 radeon_ring_write(ring, 0); 1695 radeon_ring_write(ring, 0); 1696 radeon_ring_unlock_commit(rdev, ring); 1697 1698 cp_me = 0xff; 1699 WREG32(CP_ME_CNTL, cp_me); 1700 1701 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19); 1702 if (r) { 1703 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1704 return r; 1705 } 1706 1707 /* setup clear context state */ 1708 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1709 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1710 1711 for (i = 0; i < evergreen_default_size; i++) 1712 radeon_ring_write(ring, evergreen_default_state[i]); 1713 1714 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1715 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1716 1717 /* set clear context state */ 1718 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1719 radeon_ring_write(ring, 0); 1720 1721 /* SQ_VTX_BASE_VTX_LOC */ 1722 radeon_ring_write(ring, 0xc0026f00); 1723 radeon_ring_write(ring, 0x00000000); 1724 radeon_ring_write(ring, 0x00000000); 1725 radeon_ring_write(ring, 0x00000000); 1726 1727 /* Clear consts */ 1728 radeon_ring_write(ring, 0xc0036f00); 1729 radeon_ring_write(ring, 0x00000bc4); 1730 radeon_ring_write(ring, 0xffffffff); 1731 radeon_ring_write(ring, 0xffffffff); 1732 radeon_ring_write(ring, 0xffffffff); 1733 1734 radeon_ring_write(ring, 0xc0026900); 1735 radeon_ring_write(ring, 0x00000316); 1736 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1737 radeon_ring_write(ring, 0x00000010); /* */ 1738 1739 radeon_ring_unlock_commit(rdev, ring); 1740 1741 return 0; 1742 } 1743 1744 static int evergreen_cp_resume(struct radeon_device *rdev) 1745 { 1746 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1747 u32 tmp; 1748 u32 rb_bufsz; 1749 int r; 1750 1751 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1752 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1753 SOFT_RESET_PA | 1754 SOFT_RESET_SH | 1755 SOFT_RESET_VGT | 1756 SOFT_RESET_SPI | 1757 SOFT_RESET_SX)); 1758 RREG32(GRBM_SOFT_RESET); 1759 mdelay(15); 1760 WREG32(GRBM_SOFT_RESET, 0); 1761 RREG32(GRBM_SOFT_RESET); 1762 1763 /* Set ring buffer size */ 1764 rb_bufsz = drm_order(ring->ring_size / 8); 1765 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1766 #ifdef __BIG_ENDIAN 1767 tmp |= BUF_SWAP_32BIT; 1768 #endif 1769 WREG32(CP_RB_CNTL, tmp); 1770 WREG32(CP_SEM_WAIT_TIMER, 0x0); 1771 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 1772 1773 /* Set the write pointer delay */ 1774 WREG32(CP_RB_WPTR_DELAY, 0); 1775 1776 /* Initialize the ring buffer's read and write pointers */ 1777 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1778 WREG32(CP_RB_RPTR_WR, 0); 1779 ring->wptr = 0; 1780 WREG32(CP_RB_WPTR, ring->wptr); 1781 1782 /* set the wb address whether it's enabled or not */ 1783 WREG32(CP_RB_RPTR_ADDR, 1784 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 1785 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 1786 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1787 1788 if (rdev->wb.enabled) 1789 WREG32(SCRATCH_UMSK, 0xff); 1790 else { 1791 tmp |= RB_NO_UPDATE; 1792 WREG32(SCRATCH_UMSK, 0); 1793 } 1794 1795 mdelay(1); 1796 WREG32(CP_RB_CNTL, tmp); 1797 1798 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 1799 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 1800 1801 ring->rptr = RREG32(CP_RB_RPTR); 1802 1803 evergreen_cp_start(rdev); 1804 ring->ready = true; 1805 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1806 if (r) { 1807 ring->ready = false; 1808 return r; 1809 } 1810 return 0; 1811 } 1812 1813 /* 1814 * Core functions 1815 */ 1816 static void evergreen_gpu_init(struct radeon_device *rdev) 1817 { 1818 u32 gb_addr_config; 1819 u32 mc_shared_chmap, mc_arb_ramcfg; 1820 u32 sx_debug_1; 1821 u32 smx_dc_ctl0; 1822 u32 sq_config; 1823 u32 sq_lds_resource_mgmt; 1824 u32 sq_gpr_resource_mgmt_1; 1825 u32 sq_gpr_resource_mgmt_2; 1826 u32 sq_gpr_resource_mgmt_3; 1827 u32 sq_thread_resource_mgmt; 1828 u32 sq_thread_resource_mgmt_2; 1829 u32 sq_stack_resource_mgmt_1; 1830 u32 sq_stack_resource_mgmt_2; 1831 u32 sq_stack_resource_mgmt_3; 1832 u32 vgt_cache_invalidation; 1833 u32 hdp_host_path_cntl, tmp; 1834 u32 disabled_rb_mask; 1835 int i, j, num_shader_engines, ps_thread_count; 1836 1837 switch (rdev->family) { 1838 case CHIP_CYPRESS: 1839 case CHIP_HEMLOCK: 1840 rdev->config.evergreen.num_ses = 2; 1841 rdev->config.evergreen.max_pipes = 4; 1842 rdev->config.evergreen.max_tile_pipes = 8; 1843 rdev->config.evergreen.max_simds = 10; 1844 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1845 rdev->config.evergreen.max_gprs = 256; 1846 rdev->config.evergreen.max_threads = 248; 1847 rdev->config.evergreen.max_gs_threads = 32; 1848 rdev->config.evergreen.max_stack_entries = 512; 1849 rdev->config.evergreen.sx_num_of_sets = 4; 1850 rdev->config.evergreen.sx_max_export_size = 256; 1851 rdev->config.evergreen.sx_max_export_pos_size = 64; 1852 rdev->config.evergreen.sx_max_export_smx_size = 192; 1853 rdev->config.evergreen.max_hw_contexts = 8; 1854 rdev->config.evergreen.sq_num_cf_insts = 2; 1855 1856 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1857 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1858 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1859 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN; 1860 break; 1861 case CHIP_JUNIPER: 1862 rdev->config.evergreen.num_ses = 1; 1863 rdev->config.evergreen.max_pipes = 4; 1864 rdev->config.evergreen.max_tile_pipes = 4; 1865 rdev->config.evergreen.max_simds = 10; 1866 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 1867 rdev->config.evergreen.max_gprs = 256; 1868 rdev->config.evergreen.max_threads = 248; 1869 rdev->config.evergreen.max_gs_threads = 32; 1870 rdev->config.evergreen.max_stack_entries = 512; 1871 rdev->config.evergreen.sx_num_of_sets = 4; 1872 rdev->config.evergreen.sx_max_export_size = 256; 1873 rdev->config.evergreen.sx_max_export_pos_size = 64; 1874 rdev->config.evergreen.sx_max_export_smx_size = 192; 1875 rdev->config.evergreen.max_hw_contexts = 8; 1876 rdev->config.evergreen.sq_num_cf_insts = 2; 1877 1878 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1879 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1880 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1881 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN; 1882 break; 1883 case CHIP_REDWOOD: 1884 rdev->config.evergreen.num_ses = 1; 1885 rdev->config.evergreen.max_pipes = 4; 1886 rdev->config.evergreen.max_tile_pipes = 4; 1887 rdev->config.evergreen.max_simds = 5; 1888 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1889 rdev->config.evergreen.max_gprs = 256; 1890 rdev->config.evergreen.max_threads = 248; 1891 rdev->config.evergreen.max_gs_threads = 32; 1892 rdev->config.evergreen.max_stack_entries = 256; 1893 rdev->config.evergreen.sx_num_of_sets = 4; 1894 rdev->config.evergreen.sx_max_export_size = 256; 1895 rdev->config.evergreen.sx_max_export_pos_size = 64; 1896 rdev->config.evergreen.sx_max_export_smx_size = 192; 1897 rdev->config.evergreen.max_hw_contexts = 8; 1898 rdev->config.evergreen.sq_num_cf_insts = 2; 1899 1900 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 1901 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1902 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1903 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN; 1904 break; 1905 case CHIP_CEDAR: 1906 default: 1907 rdev->config.evergreen.num_ses = 1; 1908 rdev->config.evergreen.max_pipes = 2; 1909 rdev->config.evergreen.max_tile_pipes = 2; 1910 rdev->config.evergreen.max_simds = 2; 1911 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1912 rdev->config.evergreen.max_gprs = 256; 1913 rdev->config.evergreen.max_threads = 192; 1914 rdev->config.evergreen.max_gs_threads = 16; 1915 rdev->config.evergreen.max_stack_entries = 256; 1916 rdev->config.evergreen.sx_num_of_sets = 4; 1917 rdev->config.evergreen.sx_max_export_size = 128; 1918 rdev->config.evergreen.sx_max_export_pos_size = 32; 1919 rdev->config.evergreen.sx_max_export_smx_size = 96; 1920 rdev->config.evergreen.max_hw_contexts = 4; 1921 rdev->config.evergreen.sq_num_cf_insts = 1; 1922 1923 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1924 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1925 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1926 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; 1927 break; 1928 case CHIP_PALM: 1929 rdev->config.evergreen.num_ses = 1; 1930 rdev->config.evergreen.max_pipes = 2; 1931 rdev->config.evergreen.max_tile_pipes = 2; 1932 rdev->config.evergreen.max_simds = 2; 1933 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1934 rdev->config.evergreen.max_gprs = 256; 1935 rdev->config.evergreen.max_threads = 192; 1936 rdev->config.evergreen.max_gs_threads = 16; 1937 rdev->config.evergreen.max_stack_entries = 256; 1938 rdev->config.evergreen.sx_num_of_sets = 4; 1939 rdev->config.evergreen.sx_max_export_size = 128; 1940 rdev->config.evergreen.sx_max_export_pos_size = 32; 1941 rdev->config.evergreen.sx_max_export_smx_size = 96; 1942 rdev->config.evergreen.max_hw_contexts = 4; 1943 rdev->config.evergreen.sq_num_cf_insts = 1; 1944 1945 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1946 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1947 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1948 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN; 1949 break; 1950 case CHIP_SUMO: 1951 rdev->config.evergreen.num_ses = 1; 1952 rdev->config.evergreen.max_pipes = 4; 1953 rdev->config.evergreen.max_tile_pipes = 4; 1954 if (rdev->pdev->device == 0x9648) 1955 rdev->config.evergreen.max_simds = 3; 1956 else if ((rdev->pdev->device == 0x9647) || 1957 (rdev->pdev->device == 0x964a)) 1958 rdev->config.evergreen.max_simds = 4; 1959 else 1960 rdev->config.evergreen.max_simds = 5; 1961 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 1962 rdev->config.evergreen.max_gprs = 256; 1963 rdev->config.evergreen.max_threads = 248; 1964 rdev->config.evergreen.max_gs_threads = 32; 1965 rdev->config.evergreen.max_stack_entries = 256; 1966 rdev->config.evergreen.sx_num_of_sets = 4; 1967 rdev->config.evergreen.sx_max_export_size = 256; 1968 rdev->config.evergreen.sx_max_export_pos_size = 64; 1969 rdev->config.evergreen.sx_max_export_smx_size = 192; 1970 rdev->config.evergreen.max_hw_contexts = 8; 1971 rdev->config.evergreen.sq_num_cf_insts = 2; 1972 1973 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1974 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1975 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1976 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN; 1977 break; 1978 case CHIP_SUMO2: 1979 rdev->config.evergreen.num_ses = 1; 1980 rdev->config.evergreen.max_pipes = 4; 1981 rdev->config.evergreen.max_tile_pipes = 4; 1982 rdev->config.evergreen.max_simds = 2; 1983 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 1984 rdev->config.evergreen.max_gprs = 256; 1985 rdev->config.evergreen.max_threads = 248; 1986 rdev->config.evergreen.max_gs_threads = 32; 1987 rdev->config.evergreen.max_stack_entries = 512; 1988 rdev->config.evergreen.sx_num_of_sets = 4; 1989 rdev->config.evergreen.sx_max_export_size = 256; 1990 rdev->config.evergreen.sx_max_export_pos_size = 64; 1991 rdev->config.evergreen.sx_max_export_smx_size = 192; 1992 rdev->config.evergreen.max_hw_contexts = 4; 1993 rdev->config.evergreen.sq_num_cf_insts = 2; 1994 1995 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 1996 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1997 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1998 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN; 1999 break; 2000 case CHIP_BARTS: 2001 rdev->config.evergreen.num_ses = 2; 2002 rdev->config.evergreen.max_pipes = 4; 2003 rdev->config.evergreen.max_tile_pipes = 8; 2004 rdev->config.evergreen.max_simds = 7; 2005 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; 2006 rdev->config.evergreen.max_gprs = 256; 2007 rdev->config.evergreen.max_threads = 248; 2008 rdev->config.evergreen.max_gs_threads = 32; 2009 rdev->config.evergreen.max_stack_entries = 512; 2010 rdev->config.evergreen.sx_num_of_sets = 4; 2011 rdev->config.evergreen.sx_max_export_size = 256; 2012 rdev->config.evergreen.sx_max_export_pos_size = 64; 2013 rdev->config.evergreen.sx_max_export_smx_size = 192; 2014 rdev->config.evergreen.max_hw_contexts = 8; 2015 rdev->config.evergreen.sq_num_cf_insts = 2; 2016 2017 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 2018 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 2019 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 2020 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN; 2021 break; 2022 case CHIP_TURKS: 2023 rdev->config.evergreen.num_ses = 1; 2024 rdev->config.evergreen.max_pipes = 4; 2025 rdev->config.evergreen.max_tile_pipes = 4; 2026 rdev->config.evergreen.max_simds = 6; 2027 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; 2028 rdev->config.evergreen.max_gprs = 256; 2029 rdev->config.evergreen.max_threads = 248; 2030 rdev->config.evergreen.max_gs_threads = 32; 2031 rdev->config.evergreen.max_stack_entries = 256; 2032 rdev->config.evergreen.sx_num_of_sets = 4; 2033 rdev->config.evergreen.sx_max_export_size = 256; 2034 rdev->config.evergreen.sx_max_export_pos_size = 64; 2035 rdev->config.evergreen.sx_max_export_smx_size = 192; 2036 rdev->config.evergreen.max_hw_contexts = 8; 2037 rdev->config.evergreen.sq_num_cf_insts = 2; 2038 2039 rdev->config.evergreen.sc_prim_fifo_size = 0x100; 2040 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 2041 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 2042 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN; 2043 break; 2044 case CHIP_CAICOS: 2045 rdev->config.evergreen.num_ses = 1; 2046 rdev->config.evergreen.max_pipes = 2; 2047 rdev->config.evergreen.max_tile_pipes = 2; 2048 rdev->config.evergreen.max_simds = 2; 2049 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; 2050 rdev->config.evergreen.max_gprs = 256; 2051 rdev->config.evergreen.max_threads = 192; 2052 rdev->config.evergreen.max_gs_threads = 16; 2053 rdev->config.evergreen.max_stack_entries = 256; 2054 rdev->config.evergreen.sx_num_of_sets = 4; 2055 rdev->config.evergreen.sx_max_export_size = 128; 2056 rdev->config.evergreen.sx_max_export_pos_size = 32; 2057 rdev->config.evergreen.sx_max_export_smx_size = 96; 2058 rdev->config.evergreen.max_hw_contexts = 4; 2059 rdev->config.evergreen.sq_num_cf_insts = 1; 2060 2061 rdev->config.evergreen.sc_prim_fifo_size = 0x40; 2062 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 2063 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 2064 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN; 2065 break; 2066 } 2067 2068 /* Initialize HDP */ 2069 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2070 WREG32((0x2c14 + j), 0x00000000); 2071 WREG32((0x2c18 + j), 0x00000000); 2072 WREG32((0x2c1c + j), 0x00000000); 2073 WREG32((0x2c20 + j), 0x00000000); 2074 WREG32((0x2c24 + j), 0x00000000); 2075 } 2076 2077 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 2078 2079 evergreen_fix_pci_max_read_req_size(rdev); 2080 2081 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 2082 if ((rdev->family == CHIP_PALM) || 2083 (rdev->family == CHIP_SUMO) || 2084 (rdev->family == CHIP_SUMO2)) 2085 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); 2086 else 2087 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 2088 2089 /* setup tiling info dword. gb_addr_config is not adequate since it does 2090 * not have bank info, so create a custom tiling dword. 2091 * bits 3:0 num_pipes 2092 * bits 7:4 num_banks 2093 * bits 11:8 group_size 2094 * bits 15:12 row_size 2095 */ 2096 rdev->config.evergreen.tile_config = 0; 2097 switch (rdev->config.evergreen.max_tile_pipes) { 2098 case 1: 2099 default: 2100 rdev->config.evergreen.tile_config |= (0 << 0); 2101 break; 2102 case 2: 2103 rdev->config.evergreen.tile_config |= (1 << 0); 2104 break; 2105 case 4: 2106 rdev->config.evergreen.tile_config |= (2 << 0); 2107 break; 2108 case 8: 2109 rdev->config.evergreen.tile_config |= (3 << 0); 2110 break; 2111 } 2112 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ 2113 if (rdev->flags & RADEON_IS_IGP) 2114 rdev->config.evergreen.tile_config |= 1 << 4; 2115 else { 2116 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 2117 case 0: /* four banks */ 2118 rdev->config.evergreen.tile_config |= 0 << 4; 2119 break; 2120 case 1: /* eight banks */ 2121 rdev->config.evergreen.tile_config |= 1 << 4; 2122 break; 2123 case 2: /* sixteen banks */ 2124 default: 2125 rdev->config.evergreen.tile_config |= 2 << 4; 2126 break; 2127 } 2128 } 2129 rdev->config.evergreen.tile_config |= 0 << 8; 2130 rdev->config.evergreen.tile_config |= 2131 ((gb_addr_config & 0x30000000) >> 28) << 12; 2132 2133 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1; 2134 2135 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { 2136 u32 efuse_straps_4; 2137 u32 efuse_straps_3; 2138 2139 WREG32(RCU_IND_INDEX, 0x204); 2140 efuse_straps_4 = RREG32(RCU_IND_DATA); 2141 WREG32(RCU_IND_INDEX, 0x203); 2142 efuse_straps_3 = RREG32(RCU_IND_DATA); 2143 tmp = (((efuse_straps_4 & 0xf) << 4) | 2144 ((efuse_straps_3 & 0xf0000000) >> 28)); 2145 } else { 2146 tmp = 0; 2147 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) { 2148 u32 rb_disable_bitmap; 2149 2150 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 2151 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); 2152 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; 2153 tmp <<= 4; 2154 tmp |= rb_disable_bitmap; 2155 } 2156 } 2157 /* enabled rb are just the one not disabled :) */ 2158 disabled_rb_mask = tmp; 2159 2160 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 2161 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); 2162 2163 WREG32(GB_ADDR_CONFIG, gb_addr_config); 2164 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2165 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2166 WREG32(DMA_TILING_CONFIG, gb_addr_config); 2167 2168 if ((rdev->config.evergreen.max_backends == 1) && 2169 (rdev->flags & RADEON_IS_IGP)) { 2170 if ((disabled_rb_mask & 3) == 1) { 2171 /* RB0 disabled, RB1 enabled */ 2172 tmp = 0x11111111; 2173 } else { 2174 /* RB1 disabled, RB0 enabled */ 2175 tmp = 0x00000000; 2176 } 2177 } else { 2178 tmp = gb_addr_config & NUM_PIPES_MASK; 2179 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, 2180 EVERGREEN_MAX_BACKENDS, disabled_rb_mask); 2181 } 2182 WREG32(GB_BACKEND_MAP, tmp); 2183 2184 WREG32(CGTS_SYS_TCC_DISABLE, 0); 2185 WREG32(CGTS_TCC_DISABLE, 0); 2186 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); 2187 WREG32(CGTS_USER_TCC_DISABLE, 0); 2188 2189 /* set HW defaults for 3D engine */ 2190 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 2191 ROQ_IB2_START(0x2b))); 2192 2193 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 2194 2195 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | 2196 SYNC_GRADIENT | 2197 SYNC_WALKER | 2198 SYNC_ALIGNER)); 2199 2200 sx_debug_1 = RREG32(SX_DEBUG_1); 2201 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 2202 WREG32(SX_DEBUG_1, sx_debug_1); 2203 2204 2205 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); 2206 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff); 2207 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); 2208 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 2209 2210 if (rdev->family <= CHIP_SUMO2) 2211 WREG32(SMX_SAR_CTL0, 0x00010000); 2212 2213 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | 2214 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | 2215 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); 2216 2217 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | 2218 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | 2219 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); 2220 2221 WREG32(VGT_NUM_INSTANCES, 1); 2222 WREG32(SPI_CONFIG_CNTL, 0); 2223 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 2224 WREG32(CP_PERFMON_CNTL, 0); 2225 2226 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | 2227 FETCH_FIFO_HIWATER(0x4) | 2228 DONE_FIFO_HIWATER(0xe0) | 2229 ALU_UPDATE_FIFO_HIWATER(0x8))); 2230 2231 sq_config = RREG32(SQ_CONFIG); 2232 sq_config &= ~(PS_PRIO(3) | 2233 VS_PRIO(3) | 2234 GS_PRIO(3) | 2235 ES_PRIO(3)); 2236 sq_config |= (VC_ENABLE | 2237 EXPORT_SRC_C | 2238 PS_PRIO(0) | 2239 VS_PRIO(1) | 2240 GS_PRIO(2) | 2241 ES_PRIO(3)); 2242 2243 switch (rdev->family) { 2244 case CHIP_CEDAR: 2245 case CHIP_PALM: 2246 case CHIP_SUMO: 2247 case CHIP_SUMO2: 2248 case CHIP_CAICOS: 2249 /* no vertex cache */ 2250 sq_config &= ~VC_ENABLE; 2251 break; 2252 default: 2253 break; 2254 } 2255 2256 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); 2257 2258 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); 2259 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); 2260 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4); 2261 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); 2262 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); 2263 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 2264 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 2265 2266 switch (rdev->family) { 2267 case CHIP_CEDAR: 2268 case CHIP_PALM: 2269 case CHIP_SUMO: 2270 case CHIP_SUMO2: 2271 ps_thread_count = 96; 2272 break; 2273 default: 2274 ps_thread_count = 128; 2275 break; 2276 } 2277 2278 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); 2279 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2280 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2281 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2282 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2283 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2284 2285 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2286 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2287 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2288 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2289 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2290 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 2291 2292 WREG32(SQ_CONFIG, sq_config); 2293 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 2294 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 2295 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3); 2296 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 2297 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2); 2298 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 2299 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 2300 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3); 2301 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2302 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt); 2303 2304 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 2305 FORCE_EOV_MAX_REZ_CNT(255))); 2306 2307 switch (rdev->family) { 2308 case CHIP_CEDAR: 2309 case CHIP_PALM: 2310 case CHIP_SUMO: 2311 case CHIP_SUMO2: 2312 case CHIP_CAICOS: 2313 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); 2314 break; 2315 default: 2316 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); 2317 break; 2318 } 2319 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); 2320 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); 2321 2322 WREG32(VGT_GS_VERTEX_REUSE, 16); 2323 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0); 2324 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 2325 2326 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14); 2327 WREG32(VGT_OUT_DEALLOC_CNTL, 16); 2328 2329 WREG32(CB_PERF_CTR0_SEL_0, 0); 2330 WREG32(CB_PERF_CTR0_SEL_1, 0); 2331 WREG32(CB_PERF_CTR1_SEL_0, 0); 2332 WREG32(CB_PERF_CTR1_SEL_1, 0); 2333 WREG32(CB_PERF_CTR2_SEL_0, 0); 2334 WREG32(CB_PERF_CTR2_SEL_1, 0); 2335 WREG32(CB_PERF_CTR3_SEL_0, 0); 2336 WREG32(CB_PERF_CTR3_SEL_1, 0); 2337 2338 /* clear render buffer base addresses */ 2339 WREG32(CB_COLOR0_BASE, 0); 2340 WREG32(CB_COLOR1_BASE, 0); 2341 WREG32(CB_COLOR2_BASE, 0); 2342 WREG32(CB_COLOR3_BASE, 0); 2343 WREG32(CB_COLOR4_BASE, 0); 2344 WREG32(CB_COLOR5_BASE, 0); 2345 WREG32(CB_COLOR6_BASE, 0); 2346 WREG32(CB_COLOR7_BASE, 0); 2347 WREG32(CB_COLOR8_BASE, 0); 2348 WREG32(CB_COLOR9_BASE, 0); 2349 WREG32(CB_COLOR10_BASE, 0); 2350 WREG32(CB_COLOR11_BASE, 0); 2351 2352 /* set the shader const cache sizes to 0 */ 2353 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4) 2354 WREG32(i, 0); 2355 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4) 2356 WREG32(i, 0); 2357 2358 tmp = RREG32(HDP_MISC_CNTL); 2359 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 2360 WREG32(HDP_MISC_CNTL, tmp); 2361 2362 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 2363 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 2364 2365 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 2366 2367 udelay(50); 2368 2369 } 2370 2371 int evergreen_mc_init(struct radeon_device *rdev) 2372 { 2373 u32 tmp; 2374 int chansize, numchan; 2375 2376 /* Get VRAM informations */ 2377 rdev->mc.vram_is_ddr = true; 2378 if ((rdev->family == CHIP_PALM) || 2379 (rdev->family == CHIP_SUMO) || 2380 (rdev->family == CHIP_SUMO2)) 2381 tmp = RREG32(FUS_MC_ARB_RAMCFG); 2382 else 2383 tmp = RREG32(MC_ARB_RAMCFG); 2384 if (tmp & CHANSIZE_OVERRIDE) { 2385 chansize = 16; 2386 } else if (tmp & CHANSIZE_MASK) { 2387 chansize = 64; 2388 } else { 2389 chansize = 32; 2390 } 2391 tmp = RREG32(MC_SHARED_CHMAP); 2392 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 2393 case 0: 2394 default: 2395 numchan = 1; 2396 break; 2397 case 1: 2398 numchan = 2; 2399 break; 2400 case 2: 2401 numchan = 4; 2402 break; 2403 case 3: 2404 numchan = 8; 2405 break; 2406 } 2407 rdev->mc.vram_width = numchan * chansize; 2408 /* Could aper size report 0 ? */ 2409 rdev->mc.aper_base = rdev->fb_aper_offset; 2410 rdev->mc.aper_size = rdev->fb_aper_size; 2411 /* Setup GPU memory space */ 2412 if ((rdev->family == CHIP_PALM) || 2413 (rdev->family == CHIP_SUMO) || 2414 (rdev->family == CHIP_SUMO2)) { 2415 /* size in bytes on fusion */ 2416 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 2417 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 2418 } else { 2419 /* size in MB on evergreen/cayman/tn */ 2420 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; 2421 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; 2422 } 2423 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2424 r700_vram_gtt_location(rdev, &rdev->mc); 2425 radeon_update_bandwidth_info(rdev); 2426 2427 return 0; 2428 } 2429 2430 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2431 { 2432 u32 srbm_status; 2433 u32 grbm_status; 2434 u32 grbm_status_se0, grbm_status_se1; 2435 2436 srbm_status = RREG32(SRBM_STATUS); 2437 grbm_status = RREG32(GRBM_STATUS); 2438 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 2439 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 2440 if (!(grbm_status & GUI_ACTIVE)) { 2441 radeon_ring_lockup_update(ring); 2442 return false; 2443 } 2444 /* force CP activities */ 2445 radeon_ring_force_activity(rdev, ring); 2446 return radeon_ring_test_lockup(rdev, ring); 2447 } 2448 2449 static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev) 2450 { 2451 u32 grbm_reset = 0; 2452 2453 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2454 return; 2455 2456 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", 2457 RREG32(GRBM_STATUS)); 2458 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", 2459 RREG32(GRBM_STATUS_SE0)); 2460 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", 2461 RREG32(GRBM_STATUS_SE1)); 2462 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", 2463 RREG32(SRBM_STATUS)); 2464 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 2465 RREG32(CP_STALLED_STAT1)); 2466 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 2467 RREG32(CP_STALLED_STAT2)); 2468 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 2469 RREG32(CP_BUSY_STAT)); 2470 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 2471 RREG32(CP_STAT)); 2472 2473 /* Disable CP parsing/prefetching */ 2474 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 2475 2476 /* reset all the gfx blocks */ 2477 grbm_reset = (SOFT_RESET_CP | 2478 SOFT_RESET_CB | 2479 SOFT_RESET_DB | 2480 SOFT_RESET_PA | 2481 SOFT_RESET_SC | 2482 SOFT_RESET_SPI | 2483 SOFT_RESET_SH | 2484 SOFT_RESET_SX | 2485 SOFT_RESET_TC | 2486 SOFT_RESET_TA | 2487 SOFT_RESET_VC | 2488 SOFT_RESET_VGT); 2489 2490 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); 2491 WREG32(GRBM_SOFT_RESET, grbm_reset); 2492 (void)RREG32(GRBM_SOFT_RESET); 2493 udelay(50); 2494 WREG32(GRBM_SOFT_RESET, 0); 2495 (void)RREG32(GRBM_SOFT_RESET); 2496 2497 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", 2498 RREG32(GRBM_STATUS)); 2499 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", 2500 RREG32(GRBM_STATUS_SE0)); 2501 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", 2502 RREG32(GRBM_STATUS_SE1)); 2503 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", 2504 RREG32(SRBM_STATUS)); 2505 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 2506 RREG32(CP_STALLED_STAT1)); 2507 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 2508 RREG32(CP_STALLED_STAT2)); 2509 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 2510 RREG32(CP_BUSY_STAT)); 2511 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 2512 RREG32(CP_STAT)); 2513 } 2514 2515 static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev) 2516 { 2517 u32 tmp; 2518 2519 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2520 return; 2521 2522 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 2523 RREG32(DMA_STATUS_REG)); 2524 2525 /* Disable DMA */ 2526 tmp = RREG32(DMA_RB_CNTL); 2527 tmp &= ~DMA_RB_ENABLE; 2528 WREG32(DMA_RB_CNTL, tmp); 2529 2530 /* Reset dma */ 2531 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2532 RREG32(SRBM_SOFT_RESET); 2533 udelay(50); 2534 WREG32(SRBM_SOFT_RESET, 0); 2535 2536 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 2537 RREG32(DMA_STATUS_REG)); 2538 } 2539 2540 static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 2541 { 2542 struct evergreen_mc_save save; 2543 2544 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2545 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE); 2546 2547 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2548 reset_mask &= ~RADEON_RESET_DMA; 2549 2550 if (reset_mask == 0) 2551 return 0; 2552 2553 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 2554 2555 evergreen_mc_stop(rdev, &save); 2556 if (evergreen_mc_wait_for_idle(rdev)) { 2557 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2558 } 2559 2560 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 2561 evergreen_gpu_soft_reset_gfx(rdev); 2562 2563 if (reset_mask & RADEON_RESET_DMA) 2564 evergreen_gpu_soft_reset_dma(rdev); 2565 2566 /* Wait a little for things to settle down */ 2567 udelay(50); 2568 2569 evergreen_mc_resume(rdev, &save); 2570 return 0; 2571 } 2572 2573 int evergreen_asic_reset(struct radeon_device *rdev) 2574 { 2575 return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 2576 RADEON_RESET_COMPUTE | 2577 RADEON_RESET_DMA)); 2578 } 2579 2580 /* Interrupts */ 2581 2582 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) 2583 { 2584 if (crtc >= rdev->num_crtc) 2585 return 0; 2586 else 2587 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 2588 } 2589 2590 void evergreen_disable_interrupt_state(struct radeon_device *rdev) 2591 { 2592 u32 tmp; 2593 2594 if (rdev->family >= CHIP_CAYMAN) { 2595 cayman_cp_int_cntl_setup(rdev, 0, 2596 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2597 cayman_cp_int_cntl_setup(rdev, 1, 0); 2598 cayman_cp_int_cntl_setup(rdev, 2, 0); 2599 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; 2600 WREG32(CAYMAN_DMA1_CNTL, tmp); 2601 } else 2602 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 2603 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 2604 WREG32(DMA_CNTL, tmp); 2605 WREG32(GRBM_INT_CNTL, 0); 2606 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2607 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2608 if (rdev->num_crtc >= 4) { 2609 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2610 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2611 } 2612 if (rdev->num_crtc >= 6) { 2613 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2614 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2615 } 2616 2617 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2618 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2619 if (rdev->num_crtc >= 4) { 2620 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2621 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2622 } 2623 if (rdev->num_crtc >= 6) { 2624 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2625 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2626 } 2627 2628 /* only one DAC on DCE6 */ 2629 if (!ASIC_IS_DCE6(rdev)) 2630 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2631 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 2632 2633 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2634 WREG32(DC_HPD1_INT_CONTROL, tmp); 2635 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2636 WREG32(DC_HPD2_INT_CONTROL, tmp); 2637 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2638 WREG32(DC_HPD3_INT_CONTROL, tmp); 2639 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2640 WREG32(DC_HPD4_INT_CONTROL, tmp); 2641 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2642 WREG32(DC_HPD5_INT_CONTROL, tmp); 2643 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 2644 WREG32(DC_HPD6_INT_CONTROL, tmp); 2645 2646 } 2647 2648 int evergreen_irq_set(struct radeon_device *rdev) 2649 { 2650 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 2651 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; 2652 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 2653 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 2654 u32 grbm_int_cntl = 0; 2655 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 2656 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; 2657 u32 dma_cntl, dma_cntl1 = 0; 2658 2659 if (!rdev->irq.installed) { 2660 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 2661 return -EINVAL; 2662 } 2663 /* don't enable anything if the ih is disabled */ 2664 if (!rdev->ih.enabled) { 2665 r600_disable_interrupts(rdev); 2666 /* force the active interrupt state to all disabled */ 2667 evergreen_disable_interrupt_state(rdev); 2668 return 0; 2669 } 2670 2671 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2672 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 2673 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 2674 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 2675 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 2676 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 2677 2678 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2679 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2680 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2681 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2682 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2683 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 2684 2685 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 2686 2687 if (rdev->family >= CHIP_CAYMAN) { 2688 /* enable CP interrupts on all rings */ 2689 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 2690 DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); 2691 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 2692 } 2693 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { 2694 DRM_DEBUG("evergreen_irq_set: sw int cp1\n"); 2695 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; 2696 } 2697 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { 2698 DRM_DEBUG("evergreen_irq_set: sw int cp2\n"); 2699 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; 2700 } 2701 } else { 2702 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 2703 DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); 2704 cp_int_cntl |= RB_INT_ENABLE; 2705 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 2706 } 2707 } 2708 2709 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 2710 DRM_DEBUG("r600_irq_set: sw int dma\n"); 2711 dma_cntl |= TRAP_ENABLE; 2712 } 2713 2714 if (rdev->family >= CHIP_CAYMAN) { 2715 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; 2716 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { 2717 DRM_DEBUG("r600_irq_set: sw int dma1\n"); 2718 dma_cntl1 |= TRAP_ENABLE; 2719 } 2720 } 2721 2722 if (rdev->irq.crtc_vblank_int[0] || 2723 atomic_read(&rdev->irq.pflip[0])) { 2724 DRM_DEBUG("evergreen_irq_set: vblank 0\n"); 2725 crtc1 |= VBLANK_INT_MASK; 2726 } 2727 if (rdev->irq.crtc_vblank_int[1] || 2728 atomic_read(&rdev->irq.pflip[1])) { 2729 DRM_DEBUG("evergreen_irq_set: vblank 1\n"); 2730 crtc2 |= VBLANK_INT_MASK; 2731 } 2732 if (rdev->irq.crtc_vblank_int[2] || 2733 atomic_read(&rdev->irq.pflip[2])) { 2734 DRM_DEBUG("evergreen_irq_set: vblank 2\n"); 2735 crtc3 |= VBLANK_INT_MASK; 2736 } 2737 if (rdev->irq.crtc_vblank_int[3] || 2738 atomic_read(&rdev->irq.pflip[3])) { 2739 DRM_DEBUG("evergreen_irq_set: vblank 3\n"); 2740 crtc4 |= VBLANK_INT_MASK; 2741 } 2742 if (rdev->irq.crtc_vblank_int[4] || 2743 atomic_read(&rdev->irq.pflip[4])) { 2744 DRM_DEBUG("evergreen_irq_set: vblank 4\n"); 2745 crtc5 |= VBLANK_INT_MASK; 2746 } 2747 if (rdev->irq.crtc_vblank_int[5] || 2748 atomic_read(&rdev->irq.pflip[5])) { 2749 DRM_DEBUG("evergreen_irq_set: vblank 5\n"); 2750 crtc6 |= VBLANK_INT_MASK; 2751 } 2752 if (rdev->irq.hpd[0]) { 2753 DRM_DEBUG("evergreen_irq_set: hpd 1\n"); 2754 hpd1 |= DC_HPDx_INT_EN; 2755 } 2756 if (rdev->irq.hpd[1]) { 2757 DRM_DEBUG("evergreen_irq_set: hpd 2\n"); 2758 hpd2 |= DC_HPDx_INT_EN; 2759 } 2760 if (rdev->irq.hpd[2]) { 2761 DRM_DEBUG("evergreen_irq_set: hpd 3\n"); 2762 hpd3 |= DC_HPDx_INT_EN; 2763 } 2764 if (rdev->irq.hpd[3]) { 2765 DRM_DEBUG("evergreen_irq_set: hpd 4\n"); 2766 hpd4 |= DC_HPDx_INT_EN; 2767 } 2768 if (rdev->irq.hpd[4]) { 2769 DRM_DEBUG("evergreen_irq_set: hpd 5\n"); 2770 hpd5 |= DC_HPDx_INT_EN; 2771 } 2772 if (rdev->irq.hpd[5]) { 2773 DRM_DEBUG("evergreen_irq_set: hpd 6\n"); 2774 hpd6 |= DC_HPDx_INT_EN; 2775 } 2776 if (rdev->irq.afmt[0]) { 2777 DRM_DEBUG("evergreen_irq_set: hdmi 0\n"); 2778 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2779 } 2780 if (rdev->irq.afmt[1]) { 2781 DRM_DEBUG("evergreen_irq_set: hdmi 1\n"); 2782 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2783 } 2784 if (rdev->irq.afmt[2]) { 2785 DRM_DEBUG("evergreen_irq_set: hdmi 2\n"); 2786 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2787 } 2788 if (rdev->irq.afmt[3]) { 2789 DRM_DEBUG("evergreen_irq_set: hdmi 3\n"); 2790 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2791 } 2792 if (rdev->irq.afmt[4]) { 2793 DRM_DEBUG("evergreen_irq_set: hdmi 4\n"); 2794 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2795 } 2796 if (rdev->irq.afmt[5]) { 2797 DRM_DEBUG("evergreen_irq_set: hdmi 5\n"); 2798 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK; 2799 } 2800 2801 if (rdev->family >= CHIP_CAYMAN) { 2802 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); 2803 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); 2804 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2); 2805 } else 2806 WREG32(CP_INT_CNTL, cp_int_cntl); 2807 2808 WREG32(DMA_CNTL, dma_cntl); 2809 2810 if (rdev->family >= CHIP_CAYMAN) 2811 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1); 2812 2813 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 2814 2815 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2816 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2817 if (rdev->num_crtc >= 4) { 2818 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2819 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2820 } 2821 if (rdev->num_crtc >= 6) { 2822 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2823 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2824 } 2825 2826 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 2827 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 2828 if (rdev->num_crtc >= 4) { 2829 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 2830 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 2831 } 2832 if (rdev->num_crtc >= 6) { 2833 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 2834 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 2835 } 2836 2837 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2838 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2839 WREG32(DC_HPD3_INT_CONTROL, hpd3); 2840 WREG32(DC_HPD4_INT_CONTROL, hpd4); 2841 WREG32(DC_HPD5_INT_CONTROL, hpd5); 2842 WREG32(DC_HPD6_INT_CONTROL, hpd6); 2843 2844 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); 2845 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); 2846 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); 2847 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); 2848 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); 2849 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); 2850 2851 return 0; 2852 } 2853 2854 static void evergreen_irq_ack(struct radeon_device *rdev) 2855 { 2856 u32 tmp; 2857 2858 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 2859 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 2860 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 2861 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 2862 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 2863 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2864 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2865 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2866 if (rdev->num_crtc >= 4) { 2867 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2868 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2869 } 2870 if (rdev->num_crtc >= 6) { 2871 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2872 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2873 } 2874 2875 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 2876 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 2877 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 2878 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 2879 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 2880 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 2881 2882 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 2883 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2884 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 2885 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2886 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 2887 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2888 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 2889 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2890 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2891 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2892 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 2893 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2894 2895 if (rdev->num_crtc >= 4) { 2896 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 2897 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2898 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 2899 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2900 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2901 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2902 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2903 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2904 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2905 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2906 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2907 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2908 } 2909 2910 if (rdev->num_crtc >= 6) { 2911 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 2912 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2913 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 2914 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 2915 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2916 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2917 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2918 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2919 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2920 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2921 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2922 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2923 } 2924 2925 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 2926 tmp = RREG32(DC_HPD1_INT_CONTROL); 2927 tmp |= DC_HPDx_INT_ACK; 2928 WREG32(DC_HPD1_INT_CONTROL, tmp); 2929 } 2930 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 2931 tmp = RREG32(DC_HPD2_INT_CONTROL); 2932 tmp |= DC_HPDx_INT_ACK; 2933 WREG32(DC_HPD2_INT_CONTROL, tmp); 2934 } 2935 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 2936 tmp = RREG32(DC_HPD3_INT_CONTROL); 2937 tmp |= DC_HPDx_INT_ACK; 2938 WREG32(DC_HPD3_INT_CONTROL, tmp); 2939 } 2940 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 2941 tmp = RREG32(DC_HPD4_INT_CONTROL); 2942 tmp |= DC_HPDx_INT_ACK; 2943 WREG32(DC_HPD4_INT_CONTROL, tmp); 2944 } 2945 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 2946 tmp = RREG32(DC_HPD5_INT_CONTROL); 2947 tmp |= DC_HPDx_INT_ACK; 2948 WREG32(DC_HPD5_INT_CONTROL, tmp); 2949 } 2950 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 2951 tmp = RREG32(DC_HPD5_INT_CONTROL); 2952 tmp |= DC_HPDx_INT_ACK; 2953 WREG32(DC_HPD6_INT_CONTROL, tmp); 2954 } 2955 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { 2956 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 2957 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2958 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); 2959 } 2960 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { 2961 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 2962 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2963 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); 2964 } 2965 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { 2966 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 2967 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2968 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); 2969 } 2970 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { 2971 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 2972 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2973 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); 2974 } 2975 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { 2976 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 2977 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2978 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); 2979 } 2980 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { 2981 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 2982 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 2983 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); 2984 } 2985 } 2986 2987 static void evergreen_irq_disable(struct radeon_device *rdev) 2988 { 2989 r600_disable_interrupts(rdev); 2990 /* Wait and acknowledge irq */ 2991 mdelay(1); 2992 evergreen_irq_ack(rdev); 2993 evergreen_disable_interrupt_state(rdev); 2994 } 2995 2996 void evergreen_irq_suspend(struct radeon_device *rdev) 2997 { 2998 evergreen_irq_disable(rdev); 2999 r600_rlc_stop(rdev); 3000 } 3001 3002 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev) 3003 { 3004 u32 wptr, tmp; 3005 3006 if (rdev->wb.enabled) 3007 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3008 else 3009 wptr = RREG32(IH_RB_WPTR); 3010 3011 if (wptr & RB_OVERFLOW) { 3012 /* When a ring buffer overflow happen start parsing interrupt 3013 * from the last not overwritten vector (wptr + 16). Hopefully 3014 * this should allow us to catchup. 3015 */ 3016 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3017 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3018 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3019 tmp = RREG32(IH_RB_CNTL); 3020 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3021 WREG32(IH_RB_CNTL, tmp); 3022 } 3023 return (wptr & rdev->ih.ptr_mask); 3024 } 3025 3026 int evergreen_irq_process(struct radeon_device *rdev) 3027 { 3028 u32 wptr; 3029 u32 rptr; 3030 u32 src_id, src_data; 3031 u32 ring_index; 3032 bool queue_hotplug = false; 3033 bool queue_hdmi = false; 3034 3035 if (!rdev->ih.enabled || rdev->shutdown) 3036 return IRQ_NONE; 3037 3038 wptr = evergreen_get_ih_wptr(rdev); 3039 3040 if (wptr == rdev->ih.rptr) 3041 return IRQ_NONE; 3042 restart_ih: 3043 /* is somebody else already processing irqs? */ 3044 if (atomic_xchg(&rdev->ih.lock, 1)) 3045 return IRQ_NONE; 3046 3047 rptr = rdev->ih.rptr; 3048 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3049 3050 /* Order reading of wptr vs. reading of IH ring data */ 3051 rmb(); 3052 3053 /* display interrupts */ 3054 evergreen_irq_ack(rdev); 3055 3056 while (rptr != wptr) { 3057 /* wptr/rptr are in bytes! */ 3058 ring_index = rptr / 4; 3059 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3060 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3061 3062 switch (src_id) { 3063 case 1: /* D1 vblank/vline */ 3064 switch (src_data) { 3065 case 0: /* D1 vblank */ 3066 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 3067 if (rdev->irq.crtc_vblank_int[0]) { 3068 drm_handle_vblank(rdev->ddev, 0); 3069 rdev->pm.vblank_sync = true; 3070 wake_up(&rdev->irq.vblank_queue); 3071 } 3072 if (atomic_read(&rdev->irq.pflip[0])) 3073 radeon_crtc_handle_flip(rdev, 0); 3074 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3075 DRM_DEBUG("IH: D1 vblank\n"); 3076 } 3077 break; 3078 case 1: /* D1 vline */ 3079 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 3080 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3081 DRM_DEBUG("IH: D1 vline\n"); 3082 } 3083 break; 3084 default: 3085 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3086 break; 3087 } 3088 break; 3089 case 2: /* D2 vblank/vline */ 3090 switch (src_data) { 3091 case 0: /* D2 vblank */ 3092 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 3093 if (rdev->irq.crtc_vblank_int[1]) { 3094 drm_handle_vblank(rdev->ddev, 1); 3095 rdev->pm.vblank_sync = true; 3096 wake_up(&rdev->irq.vblank_queue); 3097 } 3098 if (atomic_read(&rdev->irq.pflip[1])) 3099 radeon_crtc_handle_flip(rdev, 1); 3100 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 3101 DRM_DEBUG("IH: D2 vblank\n"); 3102 } 3103 break; 3104 case 1: /* D2 vline */ 3105 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 3106 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 3107 DRM_DEBUG("IH: D2 vline\n"); 3108 } 3109 break; 3110 default: 3111 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3112 break; 3113 } 3114 break; 3115 case 3: /* D3 vblank/vline */ 3116 switch (src_data) { 3117 case 0: /* D3 vblank */ 3118 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 3119 if (rdev->irq.crtc_vblank_int[2]) { 3120 drm_handle_vblank(rdev->ddev, 2); 3121 rdev->pm.vblank_sync = true; 3122 wake_up(&rdev->irq.vblank_queue); 3123 } 3124 if (atomic_read(&rdev->irq.pflip[2])) 3125 radeon_crtc_handle_flip(rdev, 2); 3126 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 3127 DRM_DEBUG("IH: D3 vblank\n"); 3128 } 3129 break; 3130 case 1: /* D3 vline */ 3131 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 3132 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 3133 DRM_DEBUG("IH: D3 vline\n"); 3134 } 3135 break; 3136 default: 3137 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3138 break; 3139 } 3140 break; 3141 case 4: /* D4 vblank/vline */ 3142 switch (src_data) { 3143 case 0: /* D4 vblank */ 3144 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 3145 if (rdev->irq.crtc_vblank_int[3]) { 3146 drm_handle_vblank(rdev->ddev, 3); 3147 rdev->pm.vblank_sync = true; 3148 wake_up(&rdev->irq.vblank_queue); 3149 } 3150 if (atomic_read(&rdev->irq.pflip[3])) 3151 radeon_crtc_handle_flip(rdev, 3); 3152 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 3153 DRM_DEBUG("IH: D4 vblank\n"); 3154 } 3155 break; 3156 case 1: /* D4 vline */ 3157 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 3158 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 3159 DRM_DEBUG("IH: D4 vline\n"); 3160 } 3161 break; 3162 default: 3163 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3164 break; 3165 } 3166 break; 3167 case 5: /* D5 vblank/vline */ 3168 switch (src_data) { 3169 case 0: /* D5 vblank */ 3170 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 3171 if (rdev->irq.crtc_vblank_int[4]) { 3172 drm_handle_vblank(rdev->ddev, 4); 3173 rdev->pm.vblank_sync = true; 3174 wake_up(&rdev->irq.vblank_queue); 3175 } 3176 if (atomic_read(&rdev->irq.pflip[4])) 3177 radeon_crtc_handle_flip(rdev, 4); 3178 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 3179 DRM_DEBUG("IH: D5 vblank\n"); 3180 } 3181 break; 3182 case 1: /* D5 vline */ 3183 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 3184 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 3185 DRM_DEBUG("IH: D5 vline\n"); 3186 } 3187 break; 3188 default: 3189 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3190 break; 3191 } 3192 break; 3193 case 6: /* D6 vblank/vline */ 3194 switch (src_data) { 3195 case 0: /* D6 vblank */ 3196 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 3197 if (rdev->irq.crtc_vblank_int[5]) { 3198 drm_handle_vblank(rdev->ddev, 5); 3199 rdev->pm.vblank_sync = true; 3200 wake_up(&rdev->irq.vblank_queue); 3201 } 3202 if (atomic_read(&rdev->irq.pflip[5])) 3203 radeon_crtc_handle_flip(rdev, 5); 3204 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 3205 DRM_DEBUG("IH: D6 vblank\n"); 3206 } 3207 break; 3208 case 1: /* D6 vline */ 3209 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 3210 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 3211 DRM_DEBUG("IH: D6 vline\n"); 3212 } 3213 break; 3214 default: 3215 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3216 break; 3217 } 3218 break; 3219 case 42: /* HPD hotplug */ 3220 switch (src_data) { 3221 case 0: 3222 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 3223 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 3224 queue_hotplug = true; 3225 DRM_DEBUG("IH: HPD1\n"); 3226 } 3227 break; 3228 case 1: 3229 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 3230 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 3231 queue_hotplug = true; 3232 DRM_DEBUG("IH: HPD2\n"); 3233 } 3234 break; 3235 case 2: 3236 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 3237 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 3238 queue_hotplug = true; 3239 DRM_DEBUG("IH: HPD3\n"); 3240 } 3241 break; 3242 case 3: 3243 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 3244 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 3245 queue_hotplug = true; 3246 DRM_DEBUG("IH: HPD4\n"); 3247 } 3248 break; 3249 case 4: 3250 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 3251 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 3252 queue_hotplug = true; 3253 DRM_DEBUG("IH: HPD5\n"); 3254 } 3255 break; 3256 case 5: 3257 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 3258 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 3259 queue_hotplug = true; 3260 DRM_DEBUG("IH: HPD6\n"); 3261 } 3262 break; 3263 default: 3264 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3265 break; 3266 } 3267 break; 3268 case 44: /* hdmi */ 3269 switch (src_data) { 3270 case 0: 3271 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { 3272 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; 3273 queue_hdmi = true; 3274 DRM_DEBUG("IH: HDMI0\n"); 3275 } 3276 break; 3277 case 1: 3278 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { 3279 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; 3280 queue_hdmi = true; 3281 DRM_DEBUG("IH: HDMI1\n"); 3282 } 3283 break; 3284 case 2: 3285 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { 3286 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; 3287 queue_hdmi = true; 3288 DRM_DEBUG("IH: HDMI2\n"); 3289 } 3290 break; 3291 case 3: 3292 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { 3293 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; 3294 queue_hdmi = true; 3295 DRM_DEBUG("IH: HDMI3\n"); 3296 } 3297 break; 3298 case 4: 3299 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { 3300 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; 3301 queue_hdmi = true; 3302 DRM_DEBUG("IH: HDMI4\n"); 3303 } 3304 break; 3305 case 5: 3306 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { 3307 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; 3308 queue_hdmi = true; 3309 DRM_DEBUG("IH: HDMI5\n"); 3310 } 3311 break; 3312 default: 3313 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 3314 break; 3315 } 3316 break; 3317 case 146: 3318 case 147: 3319 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); 3320 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 3321 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 3322 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 3323 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 3324 /* reset addr and status */ 3325 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); 3326 break; 3327 case 176: /* CP_INT in ring buffer */ 3328 case 177: /* CP_INT in IB1 */ 3329 case 178: /* CP_INT in IB2 */ 3330 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 3331 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3332 break; 3333 case 181: /* CP EOP event */ 3334 DRM_DEBUG("IH: CP EOP\n"); 3335 if (rdev->family >= CHIP_CAYMAN) { 3336 switch (src_data) { 3337 case 0: 3338 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3339 break; 3340 case 1: 3341 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 3342 break; 3343 case 2: 3344 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 3345 break; 3346 } 3347 } else 3348 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3349 break; 3350 case 224: /* DMA trap event */ 3351 DRM_DEBUG("IH: DMA trap\n"); 3352 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 3353 break; 3354 case 233: /* GUI IDLE */ 3355 DRM_DEBUG("IH: GUI idle\n"); 3356 break; 3357 case 244: /* DMA trap event */ 3358 if (rdev->family >= CHIP_CAYMAN) { 3359 DRM_DEBUG("IH: DMA1 trap\n"); 3360 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 3361 } 3362 break; 3363 default: 3364 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3365 break; 3366 } 3367 3368 /* wptr/rptr are in bytes! */ 3369 rptr += 16; 3370 rptr &= rdev->ih.ptr_mask; 3371 } 3372 if (queue_hotplug) 3373 task_add(systq, &rdev->hotplug_task); 3374 if (queue_hdmi) 3375 task_add(systq, &rdev->audio_task); 3376 rdev->ih.rptr = rptr; 3377 WREG32(IH_RB_RPTR, rdev->ih.rptr); 3378 atomic_set(&rdev->ih.lock, 0); 3379 3380 /* make sure wptr hasn't changed while processing */ 3381 wptr = evergreen_get_ih_wptr(rdev); 3382 if (wptr != rptr) 3383 goto restart_ih; 3384 3385 return IRQ_HANDLED; 3386 } 3387 3388 /** 3389 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring 3390 * 3391 * @rdev: radeon_device pointer 3392 * @fence: radeon fence object 3393 * 3394 * Add a DMA fence packet to the ring to write 3395 * the fence seq number and DMA trap packet to generate 3396 * an interrupt if needed (evergreen-SI). 3397 */ 3398 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 3399 struct radeon_fence *fence) 3400 { 3401 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3402 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 3403 /* write the fence */ 3404 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 3405 radeon_ring_write(ring, addr & 0xfffffffc); 3406 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 3407 radeon_ring_write(ring, fence->seq); 3408 /* generate an interrupt */ 3409 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 3410 /* flush HDP */ 3411 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); 3412 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); 3413 radeon_ring_write(ring, 1); 3414 } 3415 3416 /** 3417 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine 3418 * 3419 * @rdev: radeon_device pointer 3420 * @ib: IB object to schedule 3421 * 3422 * Schedule an IB in the DMA ring (evergreen). 3423 */ 3424 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 3425 struct radeon_ib *ib) 3426 { 3427 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3428 3429 if (rdev->wb.enabled) { 3430 u32 next_rptr = ring->wptr + 4; 3431 while ((next_rptr & 7) != 5) 3432 next_rptr++; 3433 next_rptr += 3; 3434 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3435 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3436 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3437 radeon_ring_write(ring, next_rptr); 3438 } 3439 3440 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3441 * Pad as necessary with NOPs. 3442 */ 3443 while ((ring->wptr & 7) != 5) 3444 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3445 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3446 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3447 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3448 3449 } 3450 3451 /** 3452 * evergreen_copy_dma - copy pages using the DMA engine 3453 * 3454 * @rdev: radeon_device pointer 3455 * @src_offset: src GPU address 3456 * @dst_offset: dst GPU address 3457 * @num_gpu_pages: number of GPU pages to xfer 3458 * @fence: radeon fence object 3459 * 3460 * Copy GPU paging using the DMA engine (evergreen-cayman). 3461 * Used by the radeon ttm implementation to move pages if 3462 * registered as the asic copy callback. 3463 */ 3464 int evergreen_copy_dma(struct radeon_device *rdev, 3465 uint64_t src_offset, uint64_t dst_offset, 3466 unsigned num_gpu_pages, 3467 struct radeon_fence **fence) 3468 { 3469 struct radeon_semaphore *sem = NULL; 3470 int ring_index = rdev->asic->copy.dma_ring_index; 3471 struct radeon_ring *ring = &rdev->ring[ring_index]; 3472 u32 size_in_dw, cur_size_in_dw; 3473 int i, num_loops; 3474 int r = 0; 3475 3476 r = radeon_semaphore_create(rdev, &sem); 3477 if (r) { 3478 DRM_ERROR("radeon: moving bo (%d).\n", r); 3479 return r; 3480 } 3481 3482 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 3483 num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff); 3484 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); 3485 if (r) { 3486 DRM_ERROR("radeon: moving bo (%d).\n", r); 3487 radeon_semaphore_free(rdev, &sem, NULL); 3488 return r; 3489 } 3490 3491 if (radeon_fence_need_sync(*fence, ring->idx)) { 3492 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 3493 ring->idx); 3494 radeon_fence_note_sync(*fence, ring->idx); 3495 } else { 3496 radeon_semaphore_free(rdev, &sem, NULL); 3497 } 3498 3499 for (i = 0; i < num_loops; i++) { 3500 cur_size_in_dw = size_in_dw; 3501 if (cur_size_in_dw > 0xFFFFF) 3502 cur_size_in_dw = 0xFFFFF; 3503 size_in_dw -= cur_size_in_dw; 3504 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 3505 radeon_ring_write(ring, dst_offset & 0xfffffffc); 3506 radeon_ring_write(ring, src_offset & 0xfffffffc); 3507 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3508 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); 3509 src_offset += cur_size_in_dw * 4; 3510 dst_offset += cur_size_in_dw * 4; 3511 } 3512 3513 r = radeon_fence_emit(rdev, fence, ring->idx); 3514 if (r) { 3515 radeon_ring_unlock_undo(rdev, ring); 3516 return r; 3517 } 3518 3519 radeon_ring_unlock_commit(rdev, ring); 3520 radeon_semaphore_free(rdev, &sem, *fence); 3521 3522 return r; 3523 } 3524 3525 static int evergreen_startup(struct radeon_device *rdev) 3526 { 3527 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3528 int r; 3529 3530 /* enable pcie gen2 link */ 3531 evergreen_pcie_gen2_enable(rdev); 3532 3533 evergreen_mc_program(rdev); 3534 3535 if (ASIC_IS_DCE5(rdev)) { 3536 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { 3537 r = ni_init_microcode(rdev); 3538 if (r) { 3539 DRM_ERROR("Failed to load firmware!\n"); 3540 return r; 3541 } 3542 } 3543 r = ni_mc_load_microcode(rdev); 3544 if (r) { 3545 DRM_ERROR("Failed to load MC firmware!\n"); 3546 return r; 3547 } 3548 } else { 3549 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 3550 r = r600_init_microcode(rdev); 3551 if (r) { 3552 DRM_ERROR("Failed to load firmware!\n"); 3553 return r; 3554 } 3555 } 3556 } 3557 3558 r = r600_vram_scratch_init(rdev); 3559 if (r) 3560 return r; 3561 3562 if (rdev->flags & RADEON_IS_AGP) { 3563 evergreen_agp_enable(rdev); 3564 } else { 3565 r = evergreen_pcie_gart_enable(rdev); 3566 if (r) 3567 return r; 3568 } 3569 evergreen_gpu_init(rdev); 3570 3571 r = evergreen_blit_init(rdev); 3572 if (r) { 3573 r600_blit_fini(rdev); 3574 rdev->asic->copy.copy = NULL; 3575 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 3576 } 3577 3578 /* allocate wb buffer */ 3579 r = radeon_wb_init(rdev); 3580 if (r) 3581 return r; 3582 3583 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3584 if (r) { 3585 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3586 return r; 3587 } 3588 3589 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 3590 if (r) { 3591 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 3592 return r; 3593 } 3594 3595 /* Enable IRQ */ 3596 if (!rdev->irq.installed) { 3597 r = radeon_irq_kms_init(rdev); 3598 if (r) 3599 return r; 3600 } 3601 3602 r = r600_irq_init(rdev); 3603 if (r) { 3604 DRM_ERROR("radeon: IH init failed (%d).\n", r); 3605 radeon_irq_kms_fini(rdev); 3606 return r; 3607 } 3608 evergreen_irq_set(rdev); 3609 3610 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3611 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 3612 0, 0xfffff, RADEON_CP_PACKET2); 3613 if (r) 3614 return r; 3615 3616 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3617 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 3618 DMA_RB_RPTR, DMA_RB_WPTR, 3619 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3620 if (r) 3621 return r; 3622 3623 r = evergreen_cp_load_microcode(rdev); 3624 if (r) 3625 return r; 3626 r = evergreen_cp_resume(rdev); 3627 if (r) 3628 return r; 3629 r = r600_dma_resume(rdev); 3630 if (r) 3631 return r; 3632 3633 r = radeon_ib_pool_init(rdev); 3634 if (r) { 3635 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3636 return r; 3637 } 3638 3639 r = r600_audio_init(rdev); 3640 if (r) { 3641 DRM_ERROR("radeon: audio init failed\n"); 3642 return r; 3643 } 3644 3645 return 0; 3646 } 3647 3648 int evergreen_resume(struct radeon_device *rdev) 3649 { 3650 int r; 3651 3652 /* reset the asic, the gfx blocks are often in a bad state 3653 * after the driver is unloaded or after a resume 3654 */ 3655 if (radeon_asic_reset(rdev)) 3656 dev_warn(rdev->dev, "GPU reset failed !\n"); 3657 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 3658 * posting will perform necessary task to bring back GPU into good 3659 * shape. 3660 */ 3661 /* post card */ 3662 atom_asic_init(rdev->mode_info.atom_context); 3663 3664 rdev->accel_working = true; 3665 r = evergreen_startup(rdev); 3666 if (r) { 3667 DRM_ERROR("evergreen startup failed on resume\n"); 3668 rdev->accel_working = false; 3669 return r; 3670 } 3671 3672 return r; 3673 3674 } 3675 3676 int evergreen_suspend(struct radeon_device *rdev) 3677 { 3678 r600_audio_fini(rdev); 3679 r700_cp_stop(rdev); 3680 r600_dma_stop(rdev); 3681 evergreen_irq_suspend(rdev); 3682 radeon_wb_disable(rdev); 3683 evergreen_pcie_gart_disable(rdev); 3684 3685 return 0; 3686 } 3687 3688 /* Plan is to move initialization in that function and use 3689 * helper function so that radeon_device_init pretty much 3690 * do nothing more than calling asic specific function. This 3691 * should also allow to remove a bunch of callback function 3692 * like vram_info. 3693 */ 3694 int evergreen_init(struct radeon_device *rdev) 3695 { 3696 int r; 3697 3698 /* Read BIOS */ 3699 if (!radeon_get_bios(rdev)) { 3700 if (ASIC_IS_AVIVO(rdev)) 3701 return -EINVAL; 3702 } 3703 /* Must be an ATOMBIOS */ 3704 if (!rdev->is_atom_bios) { 3705 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); 3706 return -EINVAL; 3707 } 3708 r = radeon_atombios_init(rdev); 3709 if (r) 3710 return r; 3711 /* reset the asic, the gfx blocks are often in a bad state 3712 * after the driver is unloaded or after a resume 3713 */ 3714 if (radeon_asic_reset(rdev)) 3715 dev_warn(rdev->dev, "GPU reset failed !\n"); 3716 /* Post card if necessary */ 3717 if (!radeon_card_posted(rdev)) { 3718 if (!rdev->bios) { 3719 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 3720 return -EINVAL; 3721 } 3722 DRM_INFO("GPU not posted. posting now...\n"); 3723 atom_asic_init(rdev->mode_info.atom_context); 3724 } 3725 /* Initialize scratch registers */ 3726 r600_scratch_init(rdev); 3727 /* Initialize surface registers */ 3728 radeon_surface_init(rdev); 3729 /* Initialize clocks */ 3730 radeon_get_clock_info(rdev->ddev); 3731 /* Fence driver */ 3732 r = radeon_fence_driver_init(rdev); 3733 if (r) 3734 return r; 3735 /* initialize AGP */ 3736 if (rdev->flags & RADEON_IS_AGP) { 3737 r = radeon_agp_init(rdev); 3738 if (r) 3739 radeon_agp_disable(rdev); 3740 } 3741 /* initialize memory controller */ 3742 r = evergreen_mc_init(rdev); 3743 if (r) 3744 return r; 3745 /* Memory manager */ 3746 r = radeon_bo_init(rdev); 3747 if (r) 3748 return r; 3749 3750 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 3751 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 3752 3753 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 3754 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 3755 3756 rdev->ih.ring_obj = NULL; 3757 r600_ih_ring_init(rdev, 64 * 1024); 3758 3759 r = r600_pcie_gart_init(rdev); 3760 if (r) 3761 return r; 3762 3763 rdev->accel_working = true; 3764 r = evergreen_startup(rdev); 3765 if (r) { 3766 dev_err(rdev->dev, "disabling GPU acceleration\n"); 3767 r700_cp_fini(rdev); 3768 r600_dma_fini(rdev); 3769 r600_irq_fini(rdev); 3770 radeon_wb_fini(rdev); 3771 radeon_ib_pool_fini(rdev); 3772 radeon_irq_kms_fini(rdev); 3773 evergreen_pcie_gart_fini(rdev); 3774 rdev->accel_working = false; 3775 } 3776 3777 /* Don't start up if the MC ucode is missing on BTC parts. 3778 * The default clocks and voltages before the MC ucode 3779 * is loaded are not suffient for advanced operations. 3780 */ 3781 if (ASIC_IS_DCE5(rdev)) { 3782 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { 3783 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 3784 return -EINVAL; 3785 } 3786 } 3787 3788 return 0; 3789 } 3790 3791 void evergreen_fini(struct radeon_device *rdev) 3792 { 3793 r600_audio_fini(rdev); 3794 r600_blit_fini(rdev); 3795 r700_cp_fini(rdev); 3796 r600_dma_fini(rdev); 3797 r600_irq_fini(rdev); 3798 radeon_wb_fini(rdev); 3799 radeon_ib_pool_fini(rdev); 3800 radeon_irq_kms_fini(rdev); 3801 evergreen_pcie_gart_fini(rdev); 3802 r600_vram_scratch_fini(rdev); 3803 radeon_gem_fini(rdev); 3804 radeon_fence_driver_fini(rdev); 3805 radeon_agp_fini(rdev); 3806 radeon_bo_fini(rdev); 3807 radeon_atombios_fini(rdev); 3808 kfree(rdev->bios); 3809 rdev->bios = NULL; 3810 } 3811 3812 void evergreen_pcie_gen2_enable(struct radeon_device *rdev) 3813 { 3814 u32 link_width_cntl, speed_cntl, mask; 3815 int ret; 3816 3817 if (radeon_pcie_gen2 == 0) 3818 return; 3819 3820 if (rdev->flags & RADEON_IS_IGP) 3821 return; 3822 3823 if (!(rdev->flags & RADEON_IS_PCIE)) 3824 return; 3825 3826 /* x2 cards have a special sequence */ 3827 if (ASIC_IS_X2(rdev)) 3828 return; 3829 3830 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 3831 if (ret != 0) 3832 return; 3833 3834 if (!(mask & DRM_PCIE_SPEED_50)) 3835 return; 3836 3837 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3838 if (speed_cntl & LC_CURRENT_DATA_RATE) { 3839 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 3840 return; 3841 } 3842 3843 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 3844 3845 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) || 3846 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 3847 3848 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3849 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3850 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3851 3852 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3853 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 3854 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3855 3856 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3857 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; 3858 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3859 3860 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3861 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; 3862 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3863 3864 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 3865 speed_cntl |= LC_GEN2_EN_STRAP; 3866 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 3867 3868 } else { 3869 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 3870 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 3871 if (1) 3872 link_width_cntl |= LC_UPCONFIGURE_DIS; 3873 else 3874 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 3875 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 3876 } 3877 } 3878