1 /* $OpenBSD: r300.c,v 1.7 2015/04/06 03:49:47 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include <dev/pci/drm/drm.h> 31 #include <dev/pci/drm/drm_crtc_helper.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include <dev/pci/drm/radeon_drm.h> 36 #include "r100_track.h" 37 #include "r300d.h" 38 #include "rv350d.h" 39 #include "r300_reg_safe.h" 40 41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 42 * 43 * GPU Errata: 44 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 45 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 46 * However, scheduling such write to the ring seems harmless, i suspect 47 * the CP read collide with the flush somehow, or maybe the MC, hard to 48 * tell. (Jerome Glisse) 49 */ 50 51 /* 52 * rv370,rv380 PCIE GART 53 */ 54 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 55 56 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 57 { 58 uint32_t tmp; 59 int i; 60 61 /* Workaround HW bug do flush 2 times */ 62 for (i = 0; i < 2; i++) { 63 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 65 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 66 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 67 } 68 mb(); 69 } 70 71 #define R300_PTE_WRITEABLE (1 << 2) 72 #define R300_PTE_READABLE (1 << 3) 73 74 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 75 { 76 volatile uint32_t *ptr = rdev->gart.ptr; 77 78 if (i < 0 || i > rdev->gart.num_gpu_pages) { 79 return -EINVAL; 80 } 81 addr = (lower_32_bits(addr) >> 8) | 82 ((upper_32_bits(addr) & 0xff) << 24) | 83 R300_PTE_WRITEABLE | R300_PTE_READABLE; 84 /* on x86 we want this to be CPU endian, on powerpc 85 * on powerpc without HW swappers, it'll get swapped on way 86 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 87 ptr += i; 88 *ptr = (uint32_t)addr; 89 return 0; 90 } 91 92 int rv370_pcie_gart_init(struct radeon_device *rdev) 93 { 94 int r; 95 96 if (rdev->gart.robj) { 97 WARN(1, "RV370 PCIE GART already initialized\n"); 98 return 0; 99 } 100 /* Initialize common gart structure */ 101 r = radeon_gart_init(rdev); 102 if (r) 103 return r; 104 r = rv370_debugfs_pcie_gart_info_init(rdev); 105 if (r) 106 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 108 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 109 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 110 return radeon_gart_table_vram_alloc(rdev); 111 } 112 113 int rv370_pcie_gart_enable(struct radeon_device *rdev) 114 { 115 uint32_t table_addr; 116 uint32_t tmp; 117 int r; 118 119 if (rdev->gart.robj == NULL) { 120 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 121 return -EINVAL; 122 } 123 r = radeon_gart_table_vram_pin(rdev); 124 if (r) 125 return r; 126 radeon_gart_restore(rdev); 127 /* discard memory request outside of configured range */ 128 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 129 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 131 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 132 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 133 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 134 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 135 table_addr = rdev->gart.table_addr; 136 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 137 /* FIXME: setup default page */ 138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 139 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 140 /* Clear error */ 141 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 142 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 143 tmp |= RADEON_PCIE_TX_GART_EN; 144 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 146 rv370_pcie_gart_tlb_flush(rdev); 147 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 148 (unsigned)(rdev->mc.gtt_size >> 20), 149 (unsigned long long)table_addr); 150 rdev->gart.ready = true; 151 return 0; 152 } 153 154 void rv370_pcie_gart_disable(struct radeon_device *rdev) 155 { 156 u32 tmp; 157 158 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 159 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 160 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 162 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 163 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 164 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 165 radeon_gart_table_vram_unpin(rdev); 166 } 167 168 void rv370_pcie_gart_fini(struct radeon_device *rdev) 169 { 170 radeon_gart_fini(rdev); 171 rv370_pcie_gart_disable(rdev); 172 radeon_gart_table_vram_free(rdev); 173 } 174 175 void r300_fence_ring_emit(struct radeon_device *rdev, 176 struct radeon_fence *fence) 177 { 178 struct radeon_ring *ring = &rdev->ring[fence->ring]; 179 180 /* Who ever call radeon_fence_emit should call ring_lock and ask 181 * for enough space (today caller are ib schedule and buffer move) */ 182 /* Write SC register so SC & US assert idle */ 183 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 184 radeon_ring_write(ring, 0); 185 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 186 radeon_ring_write(ring, 0); 187 /* Flush 3D cache */ 188 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 189 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 190 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 191 radeon_ring_write(ring, R300_ZC_FLUSH); 192 /* Wait until IDLE & CLEAN */ 193 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 194 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 195 RADEON_WAIT_2D_IDLECLEAN | 196 RADEON_WAIT_DMA_GUI_IDLE)); 197 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 198 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 199 RADEON_HDP_READ_BUFFER_INVALIDATE); 200 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 201 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 202 /* Emit fence sequence & fire IRQ */ 203 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 204 radeon_ring_write(ring, fence->seq); 205 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 206 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 207 } 208 209 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 210 { 211 unsigned gb_tile_config; 212 int r; 213 214 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 215 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 216 switch(rdev->num_gb_pipes) { 217 case 2: 218 gb_tile_config |= R300_PIPE_COUNT_R300; 219 break; 220 case 3: 221 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 222 break; 223 case 4: 224 gb_tile_config |= R300_PIPE_COUNT_R420; 225 break; 226 case 1: 227 default: 228 gb_tile_config |= R300_PIPE_COUNT_RV350; 229 break; 230 } 231 232 r = radeon_ring_lock(rdev, ring, 64); 233 if (r) { 234 return; 235 } 236 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 237 radeon_ring_write(ring, 238 RADEON_ISYNC_ANY2D_IDLE3D | 239 RADEON_ISYNC_ANY3D_IDLE2D | 240 RADEON_ISYNC_WAIT_IDLEGUI | 241 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 242 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 243 radeon_ring_write(ring, gb_tile_config); 244 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 245 radeon_ring_write(ring, 246 RADEON_WAIT_2D_IDLECLEAN | 247 RADEON_WAIT_3D_IDLECLEAN); 248 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 249 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 250 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 251 radeon_ring_write(ring, 0); 252 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 253 radeon_ring_write(ring, 0); 254 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 255 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 256 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 257 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 258 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 259 radeon_ring_write(ring, 260 RADEON_WAIT_2D_IDLECLEAN | 261 RADEON_WAIT_3D_IDLECLEAN); 262 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 263 radeon_ring_write(ring, 0); 264 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 265 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 266 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 267 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 268 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 269 radeon_ring_write(ring, 270 ((6 << R300_MS_X0_SHIFT) | 271 (6 << R300_MS_Y0_SHIFT) | 272 (6 << R300_MS_X1_SHIFT) | 273 (6 << R300_MS_Y1_SHIFT) | 274 (6 << R300_MS_X2_SHIFT) | 275 (6 << R300_MS_Y2_SHIFT) | 276 (6 << R300_MSBD0_Y_SHIFT) | 277 (6 << R300_MSBD0_X_SHIFT))); 278 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 279 radeon_ring_write(ring, 280 ((6 << R300_MS_X3_SHIFT) | 281 (6 << R300_MS_Y3_SHIFT) | 282 (6 << R300_MS_X4_SHIFT) | 283 (6 << R300_MS_Y4_SHIFT) | 284 (6 << R300_MS_X5_SHIFT) | 285 (6 << R300_MS_Y5_SHIFT) | 286 (6 << R300_MSBD1_SHIFT))); 287 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 288 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 289 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 290 radeon_ring_write(ring, 291 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 292 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 293 radeon_ring_write(ring, 294 R300_GEOMETRY_ROUND_NEAREST | 295 R300_COLOR_ROUND_NEAREST); 296 radeon_ring_unlock_commit(rdev, ring); 297 } 298 299 static void r300_errata(struct radeon_device *rdev) 300 { 301 rdev->pll_errata = 0; 302 303 if (rdev->family == CHIP_R300 && 304 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 305 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 306 } 307 } 308 309 int r300_mc_wait_for_idle(struct radeon_device *rdev) 310 { 311 unsigned i; 312 uint32_t tmp; 313 314 for (i = 0; i < rdev->usec_timeout; i++) { 315 /* read MC_STATUS */ 316 tmp = RREG32(RADEON_MC_STATUS); 317 if (tmp & R300_MC_IDLE) { 318 return 0; 319 } 320 DRM_UDELAY(1); 321 } 322 return -1; 323 } 324 325 static void r300_gpu_init(struct radeon_device *rdev) 326 { 327 uint32_t gb_tile_config, tmp; 328 329 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 330 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 331 /* r300,r350 */ 332 rdev->num_gb_pipes = 2; 333 } else { 334 /* rv350,rv370,rv380,r300 AD, r350 AH */ 335 rdev->num_gb_pipes = 1; 336 } 337 rdev->num_z_pipes = 1; 338 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 339 switch (rdev->num_gb_pipes) { 340 case 2: 341 gb_tile_config |= R300_PIPE_COUNT_R300; 342 break; 343 case 3: 344 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 345 break; 346 case 4: 347 gb_tile_config |= R300_PIPE_COUNT_R420; 348 break; 349 default: 350 case 1: 351 gb_tile_config |= R300_PIPE_COUNT_RV350; 352 break; 353 } 354 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 355 356 if (r100_gui_wait_for_idle(rdev)) { 357 printk(KERN_WARNING "Failed to wait GUI idle while " 358 "programming pipes. Bad things might happen.\n"); 359 } 360 361 tmp = RREG32(R300_DST_PIPE_CONFIG); 362 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 363 364 WREG32(R300_RB2D_DSTCACHE_MODE, 365 R300_DC_AUTOFLUSH_ENABLE | 366 R300_DC_DC_DISABLE_IGNORE_PE); 367 368 if (r100_gui_wait_for_idle(rdev)) { 369 printk(KERN_WARNING "Failed to wait GUI idle while " 370 "programming pipes. Bad things might happen.\n"); 371 } 372 if (r300_mc_wait_for_idle(rdev)) { 373 printk(KERN_WARNING "Failed to wait MC idle while " 374 "programming pipes. Bad things might happen.\n"); 375 } 376 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 377 rdev->num_gb_pipes, rdev->num_z_pipes); 378 } 379 380 int r300_asic_reset(struct radeon_device *rdev) 381 { 382 struct r100_mc_save save; 383 u32 status, tmp; 384 int ret = 0; 385 386 status = RREG32(R_000E40_RBBM_STATUS); 387 if (!G_000E40_GUI_ACTIVE(status)) { 388 return 0; 389 } 390 r100_mc_stop(rdev, &save); 391 status = RREG32(R_000E40_RBBM_STATUS); 392 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 393 /* stop CP */ 394 WREG32(RADEON_CP_CSQ_CNTL, 0); 395 tmp = RREG32(RADEON_CP_RB_CNTL); 396 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 397 WREG32(RADEON_CP_RB_RPTR_WR, 0); 398 WREG32(RADEON_CP_RB_WPTR, 0); 399 WREG32(RADEON_CP_RB_CNTL, tmp); 400 /* save PCI state */ 401 #ifdef notyet 402 pci_save_state(rdev->pdev); 403 #endif 404 /* disable bus mastering */ 405 r100_bm_disable(rdev); 406 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 407 S_0000F0_SOFT_RESET_GA(1)); 408 RREG32(R_0000F0_RBBM_SOFT_RESET); 409 mdelay(500); 410 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 411 mdelay(1); 412 status = RREG32(R_000E40_RBBM_STATUS); 413 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 414 /* resetting the CP seems to be problematic sometimes it end up 415 * hard locking the computer, but it's necessary for successful 416 * reset more test & playing is needed on R3XX/R4XX to find a 417 * reliable (if any solution) 418 */ 419 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 420 RREG32(R_0000F0_RBBM_SOFT_RESET); 421 mdelay(500); 422 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 423 mdelay(1); 424 status = RREG32(R_000E40_RBBM_STATUS); 425 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 426 /* restore PCI & busmastering */ 427 #ifdef notyet 428 pci_restore_state(rdev->pdev); 429 #endif 430 r100_enable_bm(rdev); 431 /* Check if GPU is idle */ 432 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 433 dev_err(rdev->dev, "failed to reset GPU\n"); 434 ret = -1; 435 } else 436 dev_info(rdev->dev, "GPU reset succeed\n"); 437 r100_mc_resume(rdev, &save); 438 return ret; 439 } 440 441 /* 442 * r300,r350,rv350,rv380 VRAM info 443 */ 444 void r300_mc_init(struct radeon_device *rdev) 445 { 446 u64 base; 447 u32 tmp; 448 449 /* DDR for all card after R300 & IGP */ 450 rdev->mc.vram_is_ddr = true; 451 tmp = RREG32(RADEON_MEM_CNTL); 452 tmp &= R300_MEM_NUM_CHANNELS_MASK; 453 switch (tmp) { 454 case 0: rdev->mc.vram_width = 64; break; 455 case 1: rdev->mc.vram_width = 128; break; 456 case 2: rdev->mc.vram_width = 256; break; 457 default: rdev->mc.vram_width = 128; break; 458 } 459 r100_vram_init_sizes(rdev); 460 base = rdev->mc.aper_base; 461 if (rdev->flags & RADEON_IS_IGP) 462 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 463 radeon_vram_location(rdev, &rdev->mc, base); 464 rdev->mc.gtt_base_align = 0; 465 if (!(rdev->flags & RADEON_IS_AGP)) 466 radeon_gtt_location(rdev, &rdev->mc); 467 radeon_update_bandwidth_info(rdev); 468 } 469 470 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 471 { 472 uint32_t link_width_cntl, mask; 473 474 if (rdev->flags & RADEON_IS_IGP) 475 return; 476 477 if (!(rdev->flags & RADEON_IS_PCIE)) 478 return; 479 480 /* FIXME wait for idle */ 481 482 switch (lanes) { 483 case 0: 484 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 485 break; 486 case 1: 487 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 488 break; 489 case 2: 490 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 491 break; 492 case 4: 493 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 494 break; 495 case 8: 496 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 497 break; 498 case 12: 499 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 500 break; 501 case 16: 502 default: 503 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 504 break; 505 } 506 507 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 508 509 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 510 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 511 return; 512 513 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 514 RADEON_PCIE_LC_RECONFIG_NOW | 515 RADEON_PCIE_LC_RECONFIG_LATER | 516 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 517 link_width_cntl |= mask; 518 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 519 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 520 RADEON_PCIE_LC_RECONFIG_NOW)); 521 522 /* wait for lane set to complete */ 523 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 524 while (link_width_cntl == 0xffffffff) 525 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 526 527 } 528 529 int rv370_get_pcie_lanes(struct radeon_device *rdev) 530 { 531 u32 link_width_cntl; 532 533 if (rdev->flags & RADEON_IS_IGP) 534 return 0; 535 536 if (!(rdev->flags & RADEON_IS_PCIE)) 537 return 0; 538 539 /* FIXME wait for idle */ 540 541 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 542 543 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 544 case RADEON_PCIE_LC_LINK_WIDTH_X0: 545 return 0; 546 case RADEON_PCIE_LC_LINK_WIDTH_X1: 547 return 1; 548 case RADEON_PCIE_LC_LINK_WIDTH_X2: 549 return 2; 550 case RADEON_PCIE_LC_LINK_WIDTH_X4: 551 return 4; 552 case RADEON_PCIE_LC_LINK_WIDTH_X8: 553 return 8; 554 case RADEON_PCIE_LC_LINK_WIDTH_X16: 555 default: 556 return 16; 557 } 558 } 559 560 #if defined(CONFIG_DEBUG_FS) 561 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 562 { 563 struct drm_info_node *node = (struct drm_info_node *) m->private; 564 struct drm_device *dev = node->minor->dev; 565 struct radeon_device *rdev = dev->dev_private; 566 uint32_t tmp; 567 568 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 569 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 570 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 571 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 572 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 573 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 574 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 575 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 576 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 577 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 578 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 579 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 580 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 581 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 582 return 0; 583 } 584 585 static struct drm_info_list rv370_pcie_gart_info_list[] = { 586 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 587 }; 588 #endif 589 590 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 591 { 592 #if defined(CONFIG_DEBUG_FS) 593 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 594 #else 595 return 0; 596 #endif 597 } 598 599 static int r300_packet0_check(struct radeon_cs_parser *p, 600 struct radeon_cs_packet *pkt, 601 unsigned idx, unsigned reg) 602 { 603 struct radeon_cs_reloc *reloc; 604 struct r100_cs_track *track; 605 volatile uint32_t *ib; 606 uint32_t tmp, tile_flags = 0; 607 unsigned i; 608 int r; 609 u32 idx_value; 610 611 ib = p->ib.ptr; 612 track = (struct r100_cs_track *)p->track; 613 idx_value = radeon_get_ib_value(p, idx); 614 615 switch(reg) { 616 case AVIVO_D1MODE_VLINE_START_END: 617 case RADEON_CRTC_GUI_TRIG_VLINE: 618 r = r100_cs_packet_parse_vline(p); 619 if (r) { 620 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 621 idx, reg); 622 r100_cs_dump_packet(p, pkt); 623 return r; 624 } 625 break; 626 case RADEON_DST_PITCH_OFFSET: 627 case RADEON_SRC_PITCH_OFFSET: 628 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 629 if (r) 630 return r; 631 break; 632 case R300_RB3D_COLOROFFSET0: 633 case R300_RB3D_COLOROFFSET1: 634 case R300_RB3D_COLOROFFSET2: 635 case R300_RB3D_COLOROFFSET3: 636 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 637 r = r100_cs_packet_next_reloc(p, &reloc); 638 if (r) { 639 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 640 idx, reg); 641 r100_cs_dump_packet(p, pkt); 642 return r; 643 } 644 track->cb[i].robj = reloc->robj; 645 track->cb[i].offset = idx_value; 646 track->cb_dirty = true; 647 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 648 break; 649 case R300_ZB_DEPTHOFFSET: 650 r = r100_cs_packet_next_reloc(p, &reloc); 651 if (r) { 652 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 653 idx, reg); 654 r100_cs_dump_packet(p, pkt); 655 return r; 656 } 657 track->zb.robj = reloc->robj; 658 track->zb.offset = idx_value; 659 track->zb_dirty = true; 660 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 661 break; 662 case R300_TX_OFFSET_0: 663 case R300_TX_OFFSET_0+4: 664 case R300_TX_OFFSET_0+8: 665 case R300_TX_OFFSET_0+12: 666 case R300_TX_OFFSET_0+16: 667 case R300_TX_OFFSET_0+20: 668 case R300_TX_OFFSET_0+24: 669 case R300_TX_OFFSET_0+28: 670 case R300_TX_OFFSET_0+32: 671 case R300_TX_OFFSET_0+36: 672 case R300_TX_OFFSET_0+40: 673 case R300_TX_OFFSET_0+44: 674 case R300_TX_OFFSET_0+48: 675 case R300_TX_OFFSET_0+52: 676 case R300_TX_OFFSET_0+56: 677 case R300_TX_OFFSET_0+60: 678 i = (reg - R300_TX_OFFSET_0) >> 2; 679 r = r100_cs_packet_next_reloc(p, &reloc); 680 if (r) { 681 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 682 idx, reg); 683 r100_cs_dump_packet(p, pkt); 684 return r; 685 } 686 687 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 688 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 689 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); 690 } else { 691 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 692 tile_flags |= R300_TXO_MACRO_TILE; 693 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 694 tile_flags |= R300_TXO_MICRO_TILE; 695 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 696 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 697 698 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); 699 tmp |= tile_flags; 700 ib[idx] = tmp; 701 } 702 track->textures[i].robj = reloc->robj; 703 track->tex_dirty = true; 704 break; 705 /* Tracked registers */ 706 case 0x2084: 707 /* VAP_VF_CNTL */ 708 track->vap_vf_cntl = idx_value; 709 break; 710 case 0x20B4: 711 /* VAP_VTX_SIZE */ 712 track->vtx_size = idx_value & 0x7F; 713 break; 714 case 0x2134: 715 /* VAP_VF_MAX_VTX_INDX */ 716 track->max_indx = idx_value & 0x00FFFFFFUL; 717 break; 718 case 0x2088: 719 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 720 if (p->rdev->family < CHIP_RV515) 721 goto fail; 722 track->vap_alt_nverts = idx_value & 0xFFFFFF; 723 break; 724 case 0x43E4: 725 /* SC_SCISSOR1 */ 726 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 727 if (p->rdev->family < CHIP_RV515) { 728 track->maxy -= 1440; 729 } 730 track->cb_dirty = true; 731 track->zb_dirty = true; 732 break; 733 case 0x4E00: 734 /* RB3D_CCTL */ 735 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 736 p->rdev->cmask_filp != p->filp) { 737 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 738 return -EINVAL; 739 } 740 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 741 track->cb_dirty = true; 742 break; 743 case 0x4E38: 744 case 0x4E3C: 745 case 0x4E40: 746 case 0x4E44: 747 /* RB3D_COLORPITCH0 */ 748 /* RB3D_COLORPITCH1 */ 749 /* RB3D_COLORPITCH2 */ 750 /* RB3D_COLORPITCH3 */ 751 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 752 r = r100_cs_packet_next_reloc(p, &reloc); 753 if (r) { 754 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 755 idx, reg); 756 r100_cs_dump_packet(p, pkt); 757 return r; 758 } 759 760 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 761 tile_flags |= R300_COLOR_TILE_ENABLE; 762 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 763 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 764 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 765 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 766 767 tmp = idx_value & ~(0x7 << 16); 768 tmp |= tile_flags; 769 ib[idx] = tmp; 770 } 771 i = (reg - 0x4E38) >> 2; 772 track->cb[i].pitch = idx_value & 0x3FFE; 773 switch (((idx_value >> 21) & 0xF)) { 774 case 9: 775 case 11: 776 case 12: 777 track->cb[i].cpp = 1; 778 break; 779 case 3: 780 case 4: 781 case 13: 782 case 15: 783 track->cb[i].cpp = 2; 784 break; 785 case 5: 786 if (p->rdev->family < CHIP_RV515) { 787 DRM_ERROR("Invalid color buffer format (%d)!\n", 788 ((idx_value >> 21) & 0xF)); 789 return -EINVAL; 790 } 791 /* Pass through. */ 792 case 6: 793 track->cb[i].cpp = 4; 794 break; 795 case 10: 796 track->cb[i].cpp = 8; 797 break; 798 case 7: 799 track->cb[i].cpp = 16; 800 break; 801 default: 802 DRM_ERROR("Invalid color buffer format (%d) !\n", 803 ((idx_value >> 21) & 0xF)); 804 return -EINVAL; 805 } 806 track->cb_dirty = true; 807 break; 808 case 0x4F00: 809 /* ZB_CNTL */ 810 if (idx_value & 2) { 811 track->z_enabled = true; 812 } else { 813 track->z_enabled = false; 814 } 815 track->zb_dirty = true; 816 break; 817 case 0x4F10: 818 /* ZB_FORMAT */ 819 switch ((idx_value & 0xF)) { 820 case 0: 821 case 1: 822 track->zb.cpp = 2; 823 break; 824 case 2: 825 track->zb.cpp = 4; 826 break; 827 default: 828 DRM_ERROR("Invalid z buffer format (%d) !\n", 829 (idx_value & 0xF)); 830 return -EINVAL; 831 } 832 track->zb_dirty = true; 833 break; 834 case 0x4F24: 835 /* ZB_DEPTHPITCH */ 836 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 837 r = r100_cs_packet_next_reloc(p, &reloc); 838 if (r) { 839 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 840 idx, reg); 841 r100_cs_dump_packet(p, pkt); 842 return r; 843 } 844 845 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 846 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 847 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 848 tile_flags |= R300_DEPTHMICROTILE_TILED; 849 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 850 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 851 852 tmp = idx_value & ~(0x7 << 16); 853 tmp |= tile_flags; 854 ib[idx] = tmp; 855 } 856 track->zb.pitch = idx_value & 0x3FFC; 857 track->zb_dirty = true; 858 break; 859 case 0x4104: 860 /* TX_ENABLE */ 861 for (i = 0; i < 16; i++) { 862 bool enabled; 863 864 enabled = !!(idx_value & (1 << i)); 865 track->textures[i].enabled = enabled; 866 } 867 track->tex_dirty = true; 868 break; 869 case 0x44C0: 870 case 0x44C4: 871 case 0x44C8: 872 case 0x44CC: 873 case 0x44D0: 874 case 0x44D4: 875 case 0x44D8: 876 case 0x44DC: 877 case 0x44E0: 878 case 0x44E4: 879 case 0x44E8: 880 case 0x44EC: 881 case 0x44F0: 882 case 0x44F4: 883 case 0x44F8: 884 case 0x44FC: 885 /* TX_FORMAT1_[0-15] */ 886 i = (reg - 0x44C0) >> 2; 887 tmp = (idx_value >> 25) & 0x3; 888 track->textures[i].tex_coord_type = tmp; 889 switch ((idx_value & 0x1F)) { 890 case R300_TX_FORMAT_X8: 891 case R300_TX_FORMAT_Y4X4: 892 case R300_TX_FORMAT_Z3Y3X2: 893 track->textures[i].cpp = 1; 894 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 895 break; 896 case R300_TX_FORMAT_X16: 897 case R300_TX_FORMAT_FL_I16: 898 case R300_TX_FORMAT_Y8X8: 899 case R300_TX_FORMAT_Z5Y6X5: 900 case R300_TX_FORMAT_Z6Y5X5: 901 case R300_TX_FORMAT_W4Z4Y4X4: 902 case R300_TX_FORMAT_W1Z5Y5X5: 903 case R300_TX_FORMAT_D3DMFT_CxV8U8: 904 case R300_TX_FORMAT_B8G8_B8G8: 905 case R300_TX_FORMAT_G8R8_G8B8: 906 track->textures[i].cpp = 2; 907 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 908 break; 909 case R300_TX_FORMAT_Y16X16: 910 case R300_TX_FORMAT_FL_I16A16: 911 case R300_TX_FORMAT_Z11Y11X10: 912 case R300_TX_FORMAT_Z10Y11X11: 913 case R300_TX_FORMAT_W8Z8Y8X8: 914 case R300_TX_FORMAT_W2Z10Y10X10: 915 case 0x17: 916 case R300_TX_FORMAT_FL_I32: 917 case 0x1e: 918 track->textures[i].cpp = 4; 919 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 920 break; 921 case R300_TX_FORMAT_W16Z16Y16X16: 922 case R300_TX_FORMAT_FL_R16G16B16A16: 923 case R300_TX_FORMAT_FL_I32A32: 924 track->textures[i].cpp = 8; 925 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 926 break; 927 case R300_TX_FORMAT_FL_R32G32B32A32: 928 track->textures[i].cpp = 16; 929 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 930 break; 931 case R300_TX_FORMAT_DXT1: 932 track->textures[i].cpp = 1; 933 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 934 break; 935 case R300_TX_FORMAT_ATI2N: 936 if (p->rdev->family < CHIP_R420) { 937 DRM_ERROR("Invalid texture format %u\n", 938 (idx_value & 0x1F)); 939 return -EINVAL; 940 } 941 /* The same rules apply as for DXT3/5. */ 942 /* Pass through. */ 943 case R300_TX_FORMAT_DXT3: 944 case R300_TX_FORMAT_DXT5: 945 track->textures[i].cpp = 1; 946 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 947 break; 948 default: 949 DRM_ERROR("Invalid texture format %u\n", 950 (idx_value & 0x1F)); 951 return -EINVAL; 952 } 953 track->tex_dirty = true; 954 break; 955 case 0x4400: 956 case 0x4404: 957 case 0x4408: 958 case 0x440C: 959 case 0x4410: 960 case 0x4414: 961 case 0x4418: 962 case 0x441C: 963 case 0x4420: 964 case 0x4424: 965 case 0x4428: 966 case 0x442C: 967 case 0x4430: 968 case 0x4434: 969 case 0x4438: 970 case 0x443C: 971 /* TX_FILTER0_[0-15] */ 972 i = (reg - 0x4400) >> 2; 973 tmp = idx_value & 0x7; 974 if (tmp == 2 || tmp == 4 || tmp == 6) { 975 track->textures[i].roundup_w = false; 976 } 977 tmp = (idx_value >> 3) & 0x7; 978 if (tmp == 2 || tmp == 4 || tmp == 6) { 979 track->textures[i].roundup_h = false; 980 } 981 track->tex_dirty = true; 982 break; 983 case 0x4500: 984 case 0x4504: 985 case 0x4508: 986 case 0x450C: 987 case 0x4510: 988 case 0x4514: 989 case 0x4518: 990 case 0x451C: 991 case 0x4520: 992 case 0x4524: 993 case 0x4528: 994 case 0x452C: 995 case 0x4530: 996 case 0x4534: 997 case 0x4538: 998 case 0x453C: 999 /* TX_FORMAT2_[0-15] */ 1000 i = (reg - 0x4500) >> 2; 1001 tmp = idx_value & 0x3FFF; 1002 track->textures[i].pitch = tmp + 1; 1003 if (p->rdev->family >= CHIP_RV515) { 1004 tmp = ((idx_value >> 15) & 1) << 11; 1005 track->textures[i].width_11 = tmp; 1006 tmp = ((idx_value >> 16) & 1) << 11; 1007 track->textures[i].height_11 = tmp; 1008 1009 /* ATI1N */ 1010 if (idx_value & (1 << 14)) { 1011 /* The same rules apply as for DXT1. */ 1012 track->textures[i].compress_format = 1013 R100_TRACK_COMP_DXT1; 1014 } 1015 } else if (idx_value & (1 << 14)) { 1016 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1017 return -EINVAL; 1018 } 1019 track->tex_dirty = true; 1020 break; 1021 case 0x4480: 1022 case 0x4484: 1023 case 0x4488: 1024 case 0x448C: 1025 case 0x4490: 1026 case 0x4494: 1027 case 0x4498: 1028 case 0x449C: 1029 case 0x44A0: 1030 case 0x44A4: 1031 case 0x44A8: 1032 case 0x44AC: 1033 case 0x44B0: 1034 case 0x44B4: 1035 case 0x44B8: 1036 case 0x44BC: 1037 /* TX_FORMAT0_[0-15] */ 1038 i = (reg - 0x4480) >> 2; 1039 tmp = idx_value & 0x7FF; 1040 track->textures[i].width = tmp + 1; 1041 tmp = (idx_value >> 11) & 0x7FF; 1042 track->textures[i].height = tmp + 1; 1043 tmp = (idx_value >> 26) & 0xF; 1044 track->textures[i].num_levels = tmp; 1045 tmp = idx_value & (1 << 31); 1046 track->textures[i].use_pitch = !!tmp; 1047 tmp = (idx_value >> 22) & 0xF; 1048 track->textures[i].txdepth = tmp; 1049 track->tex_dirty = true; 1050 break; 1051 case R300_ZB_ZPASS_ADDR: 1052 r = r100_cs_packet_next_reloc(p, &reloc); 1053 if (r) { 1054 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1055 idx, reg); 1056 r100_cs_dump_packet(p, pkt); 1057 return r; 1058 } 1059 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1060 break; 1061 case 0x4e0c: 1062 /* RB3D_COLOR_CHANNEL_MASK */ 1063 track->color_channel_mask = idx_value; 1064 track->cb_dirty = true; 1065 break; 1066 case 0x43a4: 1067 /* SC_HYPERZ_EN */ 1068 /* r300c emits this register - we need to disable hyperz for it 1069 * without complaining */ 1070 if (p->rdev->hyperz_filp != p->filp) { 1071 if (idx_value & 0x1) 1072 ib[idx] = idx_value & ~1; 1073 } 1074 break; 1075 case 0x4f1c: 1076 /* ZB_BW_CNTL */ 1077 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1078 track->cb_dirty = true; 1079 track->zb_dirty = true; 1080 if (p->rdev->hyperz_filp != p->filp) { 1081 if (idx_value & (R300_HIZ_ENABLE | 1082 R300_RD_COMP_ENABLE | 1083 R300_WR_COMP_ENABLE | 1084 R300_FAST_FILL_ENABLE)) 1085 goto fail; 1086 } 1087 break; 1088 case 0x4e04: 1089 /* RB3D_BLENDCNTL */ 1090 track->blend_read_enable = !!(idx_value & (1 << 2)); 1091 track->cb_dirty = true; 1092 break; 1093 case R300_RB3D_AARESOLVE_OFFSET: 1094 r = r100_cs_packet_next_reloc(p, &reloc); 1095 if (r) { 1096 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1097 idx, reg); 1098 r100_cs_dump_packet(p, pkt); 1099 return r; 1100 } 1101 track->aa.robj = reloc->robj; 1102 track->aa.offset = idx_value; 1103 track->aa_dirty = true; 1104 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1105 break; 1106 case R300_RB3D_AARESOLVE_PITCH: 1107 track->aa.pitch = idx_value & 0x3FFE; 1108 track->aa_dirty = true; 1109 break; 1110 case R300_RB3D_AARESOLVE_CTL: 1111 track->aaresolve = idx_value & 0x1; 1112 track->aa_dirty = true; 1113 break; 1114 case 0x4f30: /* ZB_MASK_OFFSET */ 1115 case 0x4f34: /* ZB_ZMASK_PITCH */ 1116 case 0x4f44: /* ZB_HIZ_OFFSET */ 1117 case 0x4f54: /* ZB_HIZ_PITCH */ 1118 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1119 goto fail; 1120 break; 1121 case 0x4028: 1122 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1123 goto fail; 1124 /* GB_Z_PEQ_CONFIG */ 1125 if (p->rdev->family >= CHIP_RV350) 1126 break; 1127 goto fail; 1128 break; 1129 case 0x4be8: 1130 /* valid register only on RV530 */ 1131 if (p->rdev->family == CHIP_RV530) 1132 break; 1133 /* fallthrough do not move */ 1134 default: 1135 goto fail; 1136 } 1137 return 0; 1138 fail: 1139 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1140 reg, idx, idx_value); 1141 return -EINVAL; 1142 } 1143 1144 static int r300_packet3_check(struct radeon_cs_parser *p, 1145 struct radeon_cs_packet *pkt) 1146 { 1147 struct radeon_cs_reloc *reloc; 1148 struct r100_cs_track *track; 1149 volatile uint32_t *ib; 1150 unsigned idx; 1151 int r; 1152 1153 ib = p->ib.ptr; 1154 idx = pkt->idx + 1; 1155 track = (struct r100_cs_track *)p->track; 1156 switch(pkt->opcode) { 1157 case PACKET3_3D_LOAD_VBPNTR: 1158 r = r100_packet3_load_vbpntr(p, pkt, idx); 1159 if (r) 1160 return r; 1161 break; 1162 case PACKET3_INDX_BUFFER: 1163 r = r100_cs_packet_next_reloc(p, &reloc); 1164 if (r) { 1165 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1166 r100_cs_dump_packet(p, pkt); 1167 return r; 1168 } 1169 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1170 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1171 if (r) { 1172 return r; 1173 } 1174 break; 1175 /* Draw packet */ 1176 case PACKET3_3D_DRAW_IMMD: 1177 /* Number of dwords is vtx_size * (num_vertices - 1) 1178 * PRIM_WALK must be equal to 3 vertex data in embedded 1179 * in cmd stream */ 1180 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1181 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1182 return -EINVAL; 1183 } 1184 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1185 track->immd_dwords = pkt->count - 1; 1186 r = r100_cs_track_check(p->rdev, track); 1187 if (r) { 1188 return r; 1189 } 1190 break; 1191 case PACKET3_3D_DRAW_IMMD_2: 1192 /* Number of dwords is vtx_size * (num_vertices - 1) 1193 * PRIM_WALK must be equal to 3 vertex data in embedded 1194 * in cmd stream */ 1195 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1196 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1197 return -EINVAL; 1198 } 1199 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1200 track->immd_dwords = pkt->count; 1201 r = r100_cs_track_check(p->rdev, track); 1202 if (r) { 1203 return r; 1204 } 1205 break; 1206 case PACKET3_3D_DRAW_VBUF: 1207 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1208 r = r100_cs_track_check(p->rdev, track); 1209 if (r) { 1210 return r; 1211 } 1212 break; 1213 case PACKET3_3D_DRAW_VBUF_2: 1214 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1215 r = r100_cs_track_check(p->rdev, track); 1216 if (r) { 1217 return r; 1218 } 1219 break; 1220 case PACKET3_3D_DRAW_INDX: 1221 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1222 r = r100_cs_track_check(p->rdev, track); 1223 if (r) { 1224 return r; 1225 } 1226 break; 1227 case PACKET3_3D_DRAW_INDX_2: 1228 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1229 r = r100_cs_track_check(p->rdev, track); 1230 if (r) { 1231 return r; 1232 } 1233 break; 1234 case PACKET3_3D_CLEAR_HIZ: 1235 case PACKET3_3D_CLEAR_ZMASK: 1236 if (p->rdev->hyperz_filp != p->filp) 1237 return -EINVAL; 1238 break; 1239 case PACKET3_3D_CLEAR_CMASK: 1240 if (p->rdev->cmask_filp != p->filp) 1241 return -EINVAL; 1242 break; 1243 case PACKET3_NOP: 1244 break; 1245 default: 1246 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1247 return -EINVAL; 1248 } 1249 return 0; 1250 } 1251 1252 int r300_cs_parse(struct radeon_cs_parser *p) 1253 { 1254 struct radeon_cs_packet pkt; 1255 struct r100_cs_track *track; 1256 int r; 1257 1258 track = kzalloc(sizeof(*track), GFP_KERNEL); 1259 if (track == NULL) 1260 return -ENOMEM; 1261 r100_cs_track_clear(p->rdev, track); 1262 p->track = track; 1263 do { 1264 r = r100_cs_packet_parse(p, &pkt, p->idx); 1265 if (r) { 1266 return r; 1267 } 1268 p->idx += pkt.count + 2; 1269 switch (pkt.type) { 1270 case PACKET_TYPE0: 1271 r = r100_cs_parse_packet0(p, &pkt, 1272 p->rdev->config.r300.reg_safe_bm, 1273 p->rdev->config.r300.reg_safe_bm_size, 1274 &r300_packet0_check); 1275 break; 1276 case PACKET_TYPE2: 1277 break; 1278 case PACKET_TYPE3: 1279 r = r300_packet3_check(p, &pkt); 1280 break; 1281 default: 1282 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1283 return -EINVAL; 1284 } 1285 if (r) { 1286 return r; 1287 } 1288 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1289 return 0; 1290 } 1291 1292 void r300_set_reg_safe(struct radeon_device *rdev) 1293 { 1294 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1295 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1296 } 1297 1298 void r300_mc_program(struct radeon_device *rdev) 1299 { 1300 struct r100_mc_save save; 1301 int r; 1302 1303 r = r100_debugfs_mc_info_init(rdev); 1304 if (r) { 1305 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1306 } 1307 1308 /* Stops all mc clients */ 1309 r100_mc_stop(rdev, &save); 1310 if (rdev->flags & RADEON_IS_AGP) { 1311 WREG32(R_00014C_MC_AGP_LOCATION, 1312 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1313 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1314 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1315 WREG32(R_00015C_AGP_BASE_2, 1316 upper_32_bits(rdev->mc.agp_base) & 0xff); 1317 } else { 1318 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1319 WREG32(R_000170_AGP_BASE, 0); 1320 WREG32(R_00015C_AGP_BASE_2, 0); 1321 } 1322 /* Wait for mc idle */ 1323 if (r300_mc_wait_for_idle(rdev)) 1324 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1325 /* Program MC, should be a 32bits limited address space */ 1326 WREG32(R_000148_MC_FB_LOCATION, 1327 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1328 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1329 r100_mc_resume(rdev, &save); 1330 } 1331 1332 void r300_clock_startup(struct radeon_device *rdev) 1333 { 1334 u32 tmp; 1335 1336 if (radeon_dynclks != -1 && radeon_dynclks) 1337 radeon_legacy_set_clock_gating(rdev, 1); 1338 /* We need to force on some of the block */ 1339 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1340 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1341 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1342 tmp |= S_00000D_FORCE_VAP(1); 1343 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1344 } 1345 1346 static int r300_startup(struct radeon_device *rdev) 1347 { 1348 int r; 1349 1350 /* set common regs */ 1351 r100_set_common_regs(rdev); 1352 /* program mc */ 1353 r300_mc_program(rdev); 1354 /* Resume clock */ 1355 r300_clock_startup(rdev); 1356 /* Initialize GPU configuration (# pipes, ...) */ 1357 r300_gpu_init(rdev); 1358 /* Initialize GART (initialize after TTM so we can allocate 1359 * memory through TTM but finalize after TTM) */ 1360 if (rdev->flags & RADEON_IS_PCIE) { 1361 r = rv370_pcie_gart_enable(rdev); 1362 if (r) 1363 return r; 1364 } 1365 1366 if (rdev->family == CHIP_R300 || 1367 rdev->family == CHIP_R350 || 1368 rdev->family == CHIP_RV350) 1369 r100_enable_bm(rdev); 1370 1371 if (rdev->flags & RADEON_IS_PCI) { 1372 r = r100_pci_gart_enable(rdev); 1373 if (r) 1374 return r; 1375 } 1376 1377 /* allocate wb buffer */ 1378 r = radeon_wb_init(rdev); 1379 if (r) 1380 return r; 1381 1382 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1383 if (r) { 1384 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1385 return r; 1386 } 1387 1388 /* Enable IRQ */ 1389 if (!rdev->irq.installed) { 1390 r = radeon_irq_kms_init(rdev); 1391 if (r) 1392 return r; 1393 } 1394 1395 r100_irq_set(rdev); 1396 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1397 /* 1M ring buffer */ 1398 r = r100_cp_init(rdev, 1024 * 1024); 1399 if (r) { 1400 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1401 return r; 1402 } 1403 1404 r = radeon_ib_pool_init(rdev); 1405 if (r) { 1406 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1407 return r; 1408 } 1409 1410 return 0; 1411 } 1412 1413 int r300_resume(struct radeon_device *rdev) 1414 { 1415 int r; 1416 1417 /* Make sur GART are not working */ 1418 if (rdev->flags & RADEON_IS_PCIE) 1419 rv370_pcie_gart_disable(rdev); 1420 if (rdev->flags & RADEON_IS_PCI) 1421 r100_pci_gart_disable(rdev); 1422 /* Resume clock before doing reset */ 1423 r300_clock_startup(rdev); 1424 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1425 if (radeon_asic_reset(rdev)) { 1426 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1427 RREG32(R_000E40_RBBM_STATUS), 1428 RREG32(R_0007C0_CP_STAT)); 1429 } 1430 /* post */ 1431 radeon_combios_asic_init(rdev->ddev); 1432 /* Resume clock after posting */ 1433 r300_clock_startup(rdev); 1434 /* Initialize surface registers */ 1435 radeon_surface_init(rdev); 1436 1437 rdev->accel_working = true; 1438 r = r300_startup(rdev); 1439 if (r) { 1440 rdev->accel_working = false; 1441 } 1442 return r; 1443 } 1444 1445 int r300_suspend(struct radeon_device *rdev) 1446 { 1447 r100_cp_disable(rdev); 1448 radeon_wb_disable(rdev); 1449 r100_irq_disable(rdev); 1450 if (rdev->flags & RADEON_IS_PCIE) 1451 rv370_pcie_gart_disable(rdev); 1452 if (rdev->flags & RADEON_IS_PCI) 1453 r100_pci_gart_disable(rdev); 1454 return 0; 1455 } 1456 1457 void r300_fini(struct radeon_device *rdev) 1458 { 1459 r100_cp_fini(rdev); 1460 radeon_wb_fini(rdev); 1461 radeon_ib_pool_fini(rdev); 1462 radeon_gem_fini(rdev); 1463 if (rdev->flags & RADEON_IS_PCIE) 1464 rv370_pcie_gart_fini(rdev); 1465 if (rdev->flags & RADEON_IS_PCI) 1466 r100_pci_gart_fini(rdev); 1467 radeon_agp_fini(rdev); 1468 radeon_irq_kms_fini(rdev); 1469 radeon_fence_driver_fini(rdev); 1470 radeon_bo_fini(rdev); 1471 radeon_atombios_fini(rdev); 1472 kfree(rdev->bios); 1473 rdev->bios = NULL; 1474 } 1475 1476 int r300_init(struct radeon_device *rdev) 1477 { 1478 int r; 1479 1480 /* Disable VGA */ 1481 r100_vga_render_disable(rdev); 1482 /* Initialize scratch registers */ 1483 radeon_scratch_init(rdev); 1484 /* Initialize surface registers */ 1485 radeon_surface_init(rdev); 1486 /* TODO: disable VGA need to use VGA request */ 1487 /* restore some register to sane defaults */ 1488 r100_restore_sanity(rdev); 1489 /* BIOS*/ 1490 if (!radeon_get_bios(rdev)) { 1491 if (ASIC_IS_AVIVO(rdev)) 1492 return -EINVAL; 1493 } 1494 if (rdev->is_atom_bios) { 1495 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1496 return -EINVAL; 1497 } else { 1498 r = radeon_combios_init(rdev); 1499 if (r) 1500 return r; 1501 } 1502 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1503 if (radeon_asic_reset(rdev)) { 1504 dev_warn(rdev->dev, 1505 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1506 RREG32(R_000E40_RBBM_STATUS), 1507 RREG32(R_0007C0_CP_STAT)); 1508 } 1509 /* check if cards are posted or not */ 1510 if (radeon_boot_test_post_card(rdev) == false) 1511 return -EINVAL; 1512 /* Set asic errata */ 1513 r300_errata(rdev); 1514 /* Initialize clocks */ 1515 radeon_get_clock_info(rdev->ddev); 1516 /* initialize AGP */ 1517 if (rdev->flags & RADEON_IS_AGP) { 1518 r = radeon_agp_init(rdev); 1519 if (r) { 1520 radeon_agp_disable(rdev); 1521 } 1522 } 1523 /* initialize memory controller */ 1524 r300_mc_init(rdev); 1525 /* Fence driver */ 1526 r = radeon_fence_driver_init(rdev); 1527 if (r) 1528 return r; 1529 /* Memory manager */ 1530 r = radeon_bo_init(rdev); 1531 if (r) 1532 return r; 1533 if (rdev->flags & RADEON_IS_PCIE) { 1534 r = rv370_pcie_gart_init(rdev); 1535 if (r) 1536 return r; 1537 } 1538 if (rdev->flags & RADEON_IS_PCI) { 1539 r = r100_pci_gart_init(rdev); 1540 if (r) 1541 return r; 1542 } 1543 r300_set_reg_safe(rdev); 1544 1545 rdev->accel_working = true; 1546 r = r300_startup(rdev); 1547 if (r) { 1548 /* Somethings want wront with the accel init stop accel */ 1549 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1550 r100_cp_fini(rdev); 1551 radeon_wb_fini(rdev); 1552 radeon_ib_pool_fini(rdev); 1553 radeon_irq_kms_fini(rdev); 1554 if (rdev->flags & RADEON_IS_PCIE) 1555 rv370_pcie_gart_fini(rdev); 1556 if (rdev->flags & RADEON_IS_PCI) 1557 r100_pci_gart_fini(rdev); 1558 radeon_agp_fini(rdev); 1559 rdev->accel_working = false; 1560 } 1561 return 0; 1562 } 1563