1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 #include <linux/interval_tree.h> 68 #include <linux/hashtable.h> 69 #include <linux/dma-fence.h> 70 71 #ifdef CONFIG_MMU_NOTIFIER 72 #include <linux/mmu_notifier.h> 73 #endif 74 75 #include <drm/ttm/ttm_bo_api.h> 76 #include <drm/ttm/ttm_bo_driver.h> 77 #include <drm/ttm/ttm_placement.h> 78 #include <drm/ttm/ttm_module.h> 79 #include <drm/ttm/ttm_execbuf_util.h> 80 81 #include <drm/drm_gem.h> 82 #include <drm/drm_legacy.h> 83 84 #include <dev/wscons/wsconsio.h> 85 #include <dev/wscons/wsdisplayvar.h> 86 #include <dev/rasops/rasops.h> 87 88 #include <dev/pci/pcivar.h> 89 90 #ifdef __sparc64__ 91 #include <machine/fbvar.h> 92 #endif 93 94 #include "radeon_family.h" 95 #include "radeon_mode.h" 96 #include "radeon_reg.h" 97 98 /* 99 * Modules parameters. 100 */ 101 extern int radeon_no_wb; 102 extern int radeon_modeset; 103 extern int radeon_dynclks; 104 extern int radeon_r4xx_atom; 105 extern int radeon_agpmode; 106 extern int radeon_vram_limit; 107 extern int radeon_gart_size; 108 extern int radeon_benchmarking; 109 extern int radeon_testing; 110 extern int radeon_connector_table; 111 extern int radeon_tv; 112 extern int radeon_audio; 113 extern int radeon_disp_priority; 114 extern int radeon_hw_i2c; 115 extern int radeon_pcie_gen2; 116 extern int radeon_msi; 117 extern int radeon_lockup_timeout; 118 extern int radeon_fastfb; 119 extern int radeon_dpm; 120 extern int radeon_aspm; 121 extern int radeon_runtime_pm; 122 extern int radeon_hard_reset; 123 extern int radeon_vm_size; 124 extern int radeon_vm_block_size; 125 extern int radeon_deep_color; 126 extern int radeon_use_pflipirq; 127 extern int radeon_bapm; 128 extern int radeon_backlight; 129 extern int radeon_auxch; 130 extern int radeon_mst; 131 extern int radeon_uvd; 132 extern int radeon_vce; 133 extern int radeon_si_support; 134 extern int radeon_cik_support; 135 136 /* 137 * Copy from radeon_drv.h so we don't have to include both and have conflicting 138 * symbol; 139 */ 140 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 141 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 142 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 143 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 144 #define RADEON_IB_POOL_SIZE 16 145 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 146 #define RADEONFB_CONN_LIMIT 4 147 #define RADEON_BIOS_NUM_SCRATCH 8 148 149 /* internal ring indices */ 150 /* r1xx+ has gfx CP ring */ 151 #define RADEON_RING_TYPE_GFX_INDEX 0 152 153 /* cayman has 2 compute CP rings */ 154 #define CAYMAN_RING_TYPE_CP1_INDEX 1 155 #define CAYMAN_RING_TYPE_CP2_INDEX 2 156 157 /* R600+ has an async dma ring */ 158 #define R600_RING_TYPE_DMA_INDEX 3 159 /* cayman add a second async dma ring */ 160 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 161 162 /* R600+ */ 163 #define R600_RING_TYPE_UVD_INDEX 5 164 165 /* TN+ */ 166 #define TN_RING_TYPE_VCE1_INDEX 6 167 #define TN_RING_TYPE_VCE2_INDEX 7 168 169 /* max number of rings */ 170 #define RADEON_NUM_RINGS 8 171 172 /* number of hw syncs before falling back on blocking */ 173 #define RADEON_NUM_SYNCS 4 174 175 /* hardcode those limit for now */ 176 #define RADEON_VA_IB_OFFSET (1 << 20) 177 #define RADEON_VA_RESERVED_SIZE (8 << 20) 178 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 179 180 /* hard reset data */ 181 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 182 183 /* reset flags */ 184 #define RADEON_RESET_GFX (1 << 0) 185 #define RADEON_RESET_COMPUTE (1 << 1) 186 #define RADEON_RESET_DMA (1 << 2) 187 #define RADEON_RESET_CP (1 << 3) 188 #define RADEON_RESET_GRBM (1 << 4) 189 #define RADEON_RESET_DMA1 (1 << 5) 190 #define RADEON_RESET_RLC (1 << 6) 191 #define RADEON_RESET_SEM (1 << 7) 192 #define RADEON_RESET_IH (1 << 8) 193 #define RADEON_RESET_VMC (1 << 9) 194 #define RADEON_RESET_MC (1 << 10) 195 #define RADEON_RESET_DISPLAY (1 << 11) 196 197 /* CG block flags */ 198 #define RADEON_CG_BLOCK_GFX (1 << 0) 199 #define RADEON_CG_BLOCK_MC (1 << 1) 200 #define RADEON_CG_BLOCK_SDMA (1 << 2) 201 #define RADEON_CG_BLOCK_UVD (1 << 3) 202 #define RADEON_CG_BLOCK_VCE (1 << 4) 203 #define RADEON_CG_BLOCK_HDP (1 << 5) 204 #define RADEON_CG_BLOCK_BIF (1 << 6) 205 206 /* CG flags */ 207 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 208 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 209 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 210 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 211 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 212 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 213 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 214 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 215 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 216 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 217 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 218 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 219 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 220 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 221 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 222 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 223 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 224 225 /* PG flags */ 226 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 227 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 228 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 229 #define RADEON_PG_SUPPORT_UVD (1 << 3) 230 #define RADEON_PG_SUPPORT_VCE (1 << 4) 231 #define RADEON_PG_SUPPORT_CP (1 << 5) 232 #define RADEON_PG_SUPPORT_GDS (1 << 6) 233 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 234 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 235 #define RADEON_PG_SUPPORT_ACP (1 << 9) 236 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 237 238 /* max cursor sizes (in pixels) */ 239 #define CURSOR_WIDTH 64 240 #define CURSOR_HEIGHT 64 241 242 #define CIK_CURSOR_WIDTH 128 243 #define CIK_CURSOR_HEIGHT 128 244 245 /* 246 * Errata workarounds. 247 */ 248 enum radeon_pll_errata { 249 CHIP_ERRATA_R300_CG = 0x00000001, 250 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 251 CHIP_ERRATA_PLL_DELAY = 0x00000004 252 }; 253 254 255 struct radeon_device; 256 257 258 /* 259 * BIOS. 260 */ 261 bool radeon_get_bios(struct radeon_device *rdev); 262 263 /* 264 * Dummy page 265 */ 266 struct radeon_dummy_page { 267 uint64_t entry; 268 struct drm_dmamem *dmah; 269 dma_addr_t addr; 270 }; 271 int radeon_dummy_page_init(struct radeon_device *rdev); 272 void radeon_dummy_page_fini(struct radeon_device *rdev); 273 274 275 /* 276 * Clocks 277 */ 278 struct radeon_clock { 279 struct radeon_pll p1pll; 280 struct radeon_pll p2pll; 281 struct radeon_pll dcpll; 282 struct radeon_pll spll; 283 struct radeon_pll mpll; 284 /* 10 Khz units */ 285 uint32_t default_mclk; 286 uint32_t default_sclk; 287 uint32_t default_dispclk; 288 uint32_t current_dispclk; 289 uint32_t dp_extclk; 290 uint32_t max_pixel_clock; 291 uint32_t vco_freq; 292 }; 293 294 /* 295 * Power management 296 */ 297 int radeon_pm_init(struct radeon_device *rdev); 298 int radeon_pm_late_init(struct radeon_device *rdev); 299 void radeon_pm_fini(struct radeon_device *rdev); 300 void radeon_pm_compute_clocks(struct radeon_device *rdev); 301 void radeon_pm_suspend(struct radeon_device *rdev); 302 void radeon_pm_resume(struct radeon_device *rdev); 303 void radeon_combios_get_power_modes(struct radeon_device *rdev); 304 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 305 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 306 u8 clock_type, 307 u32 clock, 308 bool strobe_mode, 309 struct atom_clock_dividers *dividers); 310 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 311 u32 clock, 312 bool strobe_mode, 313 struct atom_mpll_param *mpll_param); 314 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 315 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 316 u16 voltage_level, u8 voltage_type, 317 u32 *gpio_value, u32 *gpio_mask); 318 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 319 u32 eng_clock, u32 mem_clock); 320 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 321 u8 voltage_type, u16 *voltage_step); 322 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 323 u16 voltage_id, u16 *voltage); 324 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 325 u16 *voltage, 326 u16 leakage_idx); 327 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 328 u16 *leakage_id); 329 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 330 u16 *vddc, u16 *vddci, 331 u16 virtual_voltage_id, 332 u16 vbios_voltage_id); 333 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 334 u16 virtual_voltage_id, 335 u16 *voltage); 336 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 337 u8 voltage_type, 338 u16 nominal_voltage, 339 u16 *true_voltage); 340 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 341 u8 voltage_type, u16 *min_voltage); 342 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 343 u8 voltage_type, u16 *max_voltage); 344 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 345 u8 voltage_type, u8 voltage_mode, 346 struct atom_voltage_table *voltage_table); 347 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 348 u8 voltage_type, u8 voltage_mode); 349 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 350 u8 voltage_type, 351 u8 *svd_gpio_id, u8 *svc_gpio_id); 352 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 353 u32 mem_clock); 354 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 355 u32 mem_clock); 356 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 357 u8 module_index, 358 struct atom_mc_reg_table *reg_table); 359 int radeon_atom_get_memory_info(struct radeon_device *rdev, 360 u8 module_index, struct atom_memory_info *mem_info); 361 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 362 bool gddr5, u8 module_index, 363 struct atom_memory_clock_range_table *mclk_range_table); 364 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 365 u16 voltage_id, u16 *voltage); 366 void rs690_pm_info(struct radeon_device *rdev); 367 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 368 unsigned *bankh, unsigned *mtaspect, 369 unsigned *tile_split); 370 371 /* 372 * Fences. 373 */ 374 struct radeon_fence_driver { 375 struct radeon_device *rdev; 376 uint32_t scratch_reg; 377 uint64_t gpu_addr; 378 volatile uint32_t *cpu_addr; 379 /* sync_seq is protected by ring emission lock */ 380 uint64_t sync_seq[RADEON_NUM_RINGS]; 381 atomic64_t last_seq; 382 bool initialized, delayed_irq; 383 struct delayed_work lockup_work; 384 }; 385 386 struct radeon_fence { 387 struct dma_fence base; 388 389 struct radeon_device *rdev; 390 uint64_t seq; 391 /* RB, DMA, etc. */ 392 unsigned ring; 393 bool is_vm_update; 394 395 wait_queue_entry_t fence_wake; 396 }; 397 398 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 399 int radeon_fence_driver_init(struct radeon_device *rdev); 400 void radeon_fence_driver_fini(struct radeon_device *rdev); 401 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 402 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 403 void radeon_fence_process(struct radeon_device *rdev, int ring); 404 bool radeon_fence_signaled(struct radeon_fence *fence); 405 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 406 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 407 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 408 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 409 int radeon_fence_wait_any(struct radeon_device *rdev, 410 struct radeon_fence **fences, 411 bool intr); 412 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 413 void radeon_fence_unref(struct radeon_fence **fence); 414 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 415 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 416 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 417 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 418 struct radeon_fence *b) 419 { 420 if (!a) { 421 return b; 422 } 423 424 if (!b) { 425 return a; 426 } 427 428 BUG_ON(a->ring != b->ring); 429 430 if (a->seq > b->seq) { 431 return a; 432 } else { 433 return b; 434 } 435 } 436 437 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 438 struct radeon_fence *b) 439 { 440 if (!a) { 441 return false; 442 } 443 444 if (!b) { 445 return true; 446 } 447 448 BUG_ON(a->ring != b->ring); 449 450 return a->seq < b->seq; 451 } 452 453 /* 454 * Tiling registers 455 */ 456 struct radeon_surface_reg { 457 struct radeon_bo *bo; 458 }; 459 460 #define RADEON_GEM_MAX_SURFACES 8 461 462 /* 463 * TTM. 464 */ 465 struct radeon_mman { 466 struct ttm_bo_device bdev; 467 bool initialized; 468 469 #if defined(CONFIG_DEBUG_FS) 470 struct dentry *vram; 471 struct dentry *gtt; 472 #endif 473 }; 474 475 struct radeon_bo_list { 476 struct radeon_bo *robj; 477 struct ttm_validate_buffer tv; 478 uint64_t gpu_offset; 479 unsigned preferred_domains; 480 unsigned allowed_domains; 481 uint32_t tiling_flags; 482 }; 483 484 /* bo virtual address in a specific vm */ 485 struct radeon_bo_va { 486 /* protected by bo being reserved */ 487 struct list_head bo_list; 488 uint32_t flags; 489 struct radeon_fence *last_pt_update; 490 unsigned ref_count; 491 492 /* protected by vm mutex */ 493 struct interval_tree_node it; 494 struct list_head vm_status; 495 496 /* constant after initialization */ 497 struct radeon_vm *vm; 498 struct radeon_bo *bo; 499 }; 500 501 struct radeon_bo { 502 /* Protected by gem.mutex */ 503 struct list_head list; 504 /* Protected by tbo.reserved */ 505 u32 initial_domain; 506 struct ttm_place placements[4]; 507 struct ttm_placement placement; 508 struct ttm_buffer_object tbo; 509 struct ttm_bo_kmap_obj kmap; 510 u32 flags; 511 unsigned pin_count; 512 void *kptr; 513 u32 tiling_flags; 514 u32 pitch; 515 int surface_reg; 516 unsigned prime_shared_count; 517 /* list of all virtual address to which this bo 518 * is associated to 519 */ 520 struct list_head va; 521 /* Constant after initialization */ 522 struct radeon_device *rdev; 523 524 struct ttm_bo_kmap_obj dma_buf_vmap; 525 pid_t pid; 526 527 #ifdef CONFIG_MMU_NOTIFIER 528 struct mmu_interval_notifier notifier; 529 #endif 530 }; 531 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 532 533 int radeon_gem_debugfs_init(struct radeon_device *rdev); 534 535 /* sub-allocation manager, it has to be protected by another lock. 536 * By conception this is an helper for other part of the driver 537 * like the indirect buffer or semaphore, which both have their 538 * locking. 539 * 540 * Principe is simple, we keep a list of sub allocation in offset 541 * order (first entry has offset == 0, last entry has the highest 542 * offset). 543 * 544 * When allocating new object we first check if there is room at 545 * the end total_size - (last_object_offset + last_object_size) >= 546 * alloc_size. If so we allocate new object there. 547 * 548 * When there is not enough room at the end, we start waiting for 549 * each sub object until we reach object_offset+object_size >= 550 * alloc_size, this object then become the sub object we return. 551 * 552 * Alignment can't be bigger than page size. 553 * 554 * Hole are not considered for allocation to keep things simple. 555 * Assumption is that there won't be hole (all object on same 556 * alignment). 557 */ 558 struct radeon_sa_manager { 559 wait_queue_head_t wq; 560 struct radeon_bo *bo; 561 struct list_head *hole; 562 struct list_head flist[RADEON_NUM_RINGS]; 563 struct list_head olist; 564 unsigned size; 565 uint64_t gpu_addr; 566 void *cpu_ptr; 567 uint32_t domain; 568 uint32_t align; 569 }; 570 571 struct radeon_sa_bo; 572 573 /* sub-allocation buffer */ 574 struct radeon_sa_bo { 575 struct list_head olist; 576 struct list_head flist; 577 struct radeon_sa_manager *manager; 578 unsigned soffset; 579 unsigned eoffset; 580 struct radeon_fence *fence; 581 }; 582 583 /* 584 * GEM objects. 585 */ 586 struct radeon_gem { 587 struct rwlock mutex; 588 struct list_head objects; 589 }; 590 591 int radeon_gem_init(struct radeon_device *rdev); 592 void radeon_gem_fini(struct radeon_device *rdev); 593 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 594 int alignment, int initial_domain, 595 u32 flags, bool kernel, 596 struct drm_gem_object **obj); 597 598 int radeon_mode_dumb_create(struct drm_file *file_priv, 599 struct drm_device *dev, 600 struct drm_mode_create_dumb *args); 601 int radeon_mode_dumb_mmap(struct drm_file *filp, 602 struct drm_device *dev, 603 uint32_t handle, uint64_t *offset_p); 604 605 /* 606 * Semaphores. 607 */ 608 struct radeon_semaphore { 609 struct radeon_sa_bo *sa_bo; 610 signed waiters; 611 uint64_t gpu_addr; 612 }; 613 614 int radeon_semaphore_create(struct radeon_device *rdev, 615 struct radeon_semaphore **semaphore); 616 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 617 struct radeon_semaphore *semaphore); 618 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 619 struct radeon_semaphore *semaphore); 620 void radeon_semaphore_free(struct radeon_device *rdev, 621 struct radeon_semaphore **semaphore, 622 struct radeon_fence *fence); 623 624 /* 625 * Synchronization 626 */ 627 struct radeon_sync { 628 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 629 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 630 struct radeon_fence *last_vm_update; 631 }; 632 633 void radeon_sync_create(struct radeon_sync *sync); 634 void radeon_sync_fence(struct radeon_sync *sync, 635 struct radeon_fence *fence); 636 int radeon_sync_resv(struct radeon_device *rdev, 637 struct radeon_sync *sync, 638 struct dma_resv *resv, 639 bool shared); 640 int radeon_sync_rings(struct radeon_device *rdev, 641 struct radeon_sync *sync, 642 int waiting_ring); 643 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 644 struct radeon_fence *fence); 645 646 /* 647 * GART structures, functions & helpers 648 */ 649 struct radeon_mc; 650 651 #define RADEON_GPU_PAGE_SIZE 4096 652 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 653 #define RADEON_GPU_PAGE_SHIFT 12 654 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 655 656 #define RADEON_GART_PAGE_DUMMY 0 657 #define RADEON_GART_PAGE_VALID (1 << 0) 658 #define RADEON_GART_PAGE_READ (1 << 1) 659 #define RADEON_GART_PAGE_WRITE (1 << 2) 660 #define RADEON_GART_PAGE_SNOOP (1 << 3) 661 662 struct radeon_gart { 663 dma_addr_t table_addr; 664 struct drm_dmamem *dmah; 665 struct radeon_bo *robj; 666 void *ptr; 667 unsigned num_gpu_pages; 668 unsigned num_cpu_pages; 669 unsigned table_size; 670 struct vm_page **pages; 671 uint64_t *pages_entry; 672 bool ready; 673 }; 674 675 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 676 void radeon_gart_table_ram_free(struct radeon_device *rdev); 677 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 678 void radeon_gart_table_vram_free(struct radeon_device *rdev); 679 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 680 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 681 int radeon_gart_init(struct radeon_device *rdev); 682 void radeon_gart_fini(struct radeon_device *rdev); 683 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 684 int pages); 685 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 686 int pages, struct vm_page **pagelist, 687 dma_addr_t *dma_addr, uint32_t flags); 688 689 690 /* 691 * GPU MC structures, functions & helpers 692 */ 693 struct radeon_mc { 694 resource_size_t aper_size; 695 resource_size_t aper_base; 696 resource_size_t agp_base; 697 /* for some chips with <= 32MB we need to lie 698 * about vram size near mc fb location */ 699 u64 mc_vram_size; 700 u64 visible_vram_size; 701 u64 gtt_size; 702 u64 gtt_start; 703 u64 gtt_end; 704 u64 vram_start; 705 u64 vram_end; 706 unsigned vram_width; 707 u64 real_vram_size; 708 int vram_mtrr; 709 bool vram_is_ddr; 710 bool igp_sideport_enabled; 711 u64 gtt_base_align; 712 u64 mc_mask; 713 }; 714 715 bool radeon_combios_sideport_present(struct radeon_device *rdev); 716 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 717 718 /* 719 * GPU scratch registers structures, functions & helpers 720 */ 721 struct radeon_scratch { 722 unsigned num_reg; 723 uint32_t reg_base; 724 bool free[32]; 725 uint32_t reg[32]; 726 }; 727 728 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 729 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 730 731 /* 732 * GPU doorbell structures, functions & helpers 733 */ 734 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 735 736 struct radeon_doorbell { 737 /* doorbell mmio */ 738 resource_size_t base; 739 resource_size_t size; 740 u32 __iomem *ptr; 741 bus_space_handle_t bsh; 742 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 743 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 744 }; 745 746 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 747 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 748 749 /* 750 * IRQS. 751 */ 752 753 struct radeon_flip_work { 754 struct work_struct flip_work; 755 struct work_struct unpin_work; 756 struct radeon_device *rdev; 757 int crtc_id; 758 u32 target_vblank; 759 uint64_t base; 760 struct drm_pending_vblank_event *event; 761 struct radeon_bo *old_rbo; 762 struct dma_fence *fence; 763 bool async; 764 }; 765 766 struct r500_irq_stat_regs { 767 u32 disp_int; 768 u32 hdmi0_status; 769 }; 770 771 struct r600_irq_stat_regs { 772 u32 disp_int; 773 u32 disp_int_cont; 774 u32 disp_int_cont2; 775 u32 d1grph_int; 776 u32 d2grph_int; 777 u32 hdmi0_status; 778 u32 hdmi1_status; 779 }; 780 781 struct evergreen_irq_stat_regs { 782 u32 disp_int[6]; 783 u32 grph_int[6]; 784 u32 afmt_status[6]; 785 }; 786 787 struct cik_irq_stat_regs { 788 u32 disp_int; 789 u32 disp_int_cont; 790 u32 disp_int_cont2; 791 u32 disp_int_cont3; 792 u32 disp_int_cont4; 793 u32 disp_int_cont5; 794 u32 disp_int_cont6; 795 u32 d1grph_int; 796 u32 d2grph_int; 797 u32 d3grph_int; 798 u32 d4grph_int; 799 u32 d5grph_int; 800 u32 d6grph_int; 801 }; 802 803 union radeon_irq_stat_regs { 804 struct r500_irq_stat_regs r500; 805 struct r600_irq_stat_regs r600; 806 struct evergreen_irq_stat_regs evergreen; 807 struct cik_irq_stat_regs cik; 808 }; 809 810 struct radeon_irq { 811 bool installed; 812 spinlock_t lock; 813 atomic_t ring_int[RADEON_NUM_RINGS]; 814 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 815 atomic_t pflip[RADEON_MAX_CRTCS]; 816 wait_queue_head_t vblank_queue; 817 bool hpd[RADEON_MAX_HPD_PINS]; 818 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 819 union radeon_irq_stat_regs stat_regs; 820 bool dpm_thermal; 821 }; 822 823 int radeon_irq_kms_init(struct radeon_device *rdev); 824 void radeon_irq_kms_fini(struct radeon_device *rdev); 825 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 826 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 827 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 828 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 829 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 830 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 831 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 832 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 833 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 834 835 /* 836 * CP & rings. 837 */ 838 839 struct radeon_ib { 840 struct radeon_sa_bo *sa_bo; 841 uint32_t length_dw; 842 uint64_t gpu_addr; 843 uint32_t *ptr; 844 int ring; 845 struct radeon_fence *fence; 846 struct radeon_vm *vm; 847 bool is_const_ib; 848 struct radeon_sync sync; 849 }; 850 851 struct radeon_ring { 852 struct radeon_bo *ring_obj; 853 volatile uint32_t *ring; 854 unsigned rptr_offs; 855 unsigned rptr_save_reg; 856 u64 next_rptr_gpu_addr; 857 volatile u32 *next_rptr_cpu_addr; 858 unsigned wptr; 859 unsigned wptr_old; 860 unsigned ring_size; 861 unsigned ring_free_dw; 862 int count_dw; 863 atomic_t last_rptr; 864 atomic64_t last_activity; 865 uint64_t gpu_addr; 866 uint32_t align_mask; 867 uint32_t ptr_mask; 868 bool ready; 869 u32 nop; 870 u32 idx; 871 u64 last_semaphore_signal_addr; 872 u64 last_semaphore_wait_addr; 873 /* for CIK queues */ 874 u32 me; 875 u32 pipe; 876 u32 queue; 877 struct radeon_bo *mqd_obj; 878 u32 doorbell_index; 879 unsigned wptr_offs; 880 }; 881 882 struct radeon_mec { 883 struct radeon_bo *hpd_eop_obj; 884 u64 hpd_eop_gpu_addr; 885 u32 num_pipe; 886 u32 num_mec; 887 u32 num_queue; 888 }; 889 890 /* 891 * VM 892 */ 893 894 /* maximum number of VMIDs */ 895 #define RADEON_NUM_VM 16 896 897 /* number of entries in page table */ 898 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 899 900 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 901 #define RADEON_VM_PTB_ALIGN_SIZE 32768 902 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 903 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 904 905 #define R600_PTE_VALID (1 << 0) 906 #define R600_PTE_SYSTEM (1 << 1) 907 #define R600_PTE_SNOOPED (1 << 2) 908 #define R600_PTE_READABLE (1 << 5) 909 #define R600_PTE_WRITEABLE (1 << 6) 910 911 /* PTE (Page Table Entry) fragment field for different page sizes */ 912 #define R600_PTE_FRAG_4KB (0 << 7) 913 #define R600_PTE_FRAG_64KB (4 << 7) 914 #define R600_PTE_FRAG_256KB (6 << 7) 915 916 /* flags needed to be set so we can copy directly from the GART table */ 917 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 918 R600_PTE_SYSTEM | R600_PTE_VALID ) 919 920 struct radeon_vm_pt { 921 struct radeon_bo *bo; 922 uint64_t addr; 923 }; 924 925 struct radeon_vm_id { 926 unsigned id; 927 uint64_t pd_gpu_addr; 928 /* last flushed PD/PT update */ 929 struct radeon_fence *flushed_updates; 930 /* last use of vmid */ 931 struct radeon_fence *last_id_use; 932 }; 933 934 struct radeon_vm { 935 struct rwlock mutex; 936 937 struct rb_root_cached va; 938 939 /* protecting invalidated and freed */ 940 spinlock_t status_lock; 941 942 /* BOs moved, but not yet updated in the PT */ 943 struct list_head invalidated; 944 945 /* BOs freed, but not yet updated in the PT */ 946 struct list_head freed; 947 948 /* BOs cleared in the PT */ 949 struct list_head cleared; 950 951 /* contains the page directory */ 952 struct radeon_bo *page_directory; 953 unsigned max_pde_used; 954 955 /* array of page tables, one for each page directory entry */ 956 struct radeon_vm_pt *page_tables; 957 958 struct radeon_bo_va *ib_bo_va; 959 960 /* for id and flush management per ring */ 961 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 962 }; 963 964 struct radeon_vm_manager { 965 struct radeon_fence *active[RADEON_NUM_VM]; 966 uint32_t max_pfn; 967 /* number of VMIDs */ 968 unsigned nvm; 969 /* vram base address for page table entry */ 970 u64 vram_base_offset; 971 /* is vm enabled? */ 972 bool enabled; 973 /* for hw to save the PD addr on suspend/resume */ 974 uint32_t saved_table_addr[RADEON_NUM_VM]; 975 }; 976 977 /* 978 * file private structure 979 */ 980 struct radeon_fpriv { 981 struct radeon_vm vm; 982 }; 983 984 /* 985 * R6xx+ IH ring 986 */ 987 struct r600_ih { 988 struct radeon_bo *ring_obj; 989 volatile uint32_t *ring; 990 unsigned rptr; 991 unsigned ring_size; 992 uint64_t gpu_addr; 993 uint32_t ptr_mask; 994 atomic_t lock; 995 bool enabled; 996 }; 997 998 /* 999 * RLC stuff 1000 */ 1001 #include "clearstate_defs.h" 1002 1003 struct radeon_rlc { 1004 /* for power gating */ 1005 struct radeon_bo *save_restore_obj; 1006 uint64_t save_restore_gpu_addr; 1007 volatile uint32_t *sr_ptr; 1008 const u32 *reg_list; 1009 u32 reg_list_size; 1010 /* for clear state */ 1011 struct radeon_bo *clear_state_obj; 1012 uint64_t clear_state_gpu_addr; 1013 volatile uint32_t *cs_ptr; 1014 const struct cs_section_def *cs_data; 1015 u32 clear_state_size; 1016 /* for cp tables */ 1017 struct radeon_bo *cp_table_obj; 1018 uint64_t cp_table_gpu_addr; 1019 volatile uint32_t *cp_table_ptr; 1020 u32 cp_table_size; 1021 }; 1022 1023 int radeon_ib_get(struct radeon_device *rdev, int ring, 1024 struct radeon_ib *ib, struct radeon_vm *vm, 1025 unsigned size); 1026 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1027 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1028 struct radeon_ib *const_ib, bool hdp_flush); 1029 int radeon_ib_pool_init(struct radeon_device *rdev); 1030 void radeon_ib_pool_fini(struct radeon_device *rdev); 1031 int radeon_ib_ring_tests(struct radeon_device *rdev); 1032 /* Ring access between begin & end cannot sleep */ 1033 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1034 struct radeon_ring *ring); 1035 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1036 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1037 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1038 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1039 bool hdp_flush); 1040 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1041 bool hdp_flush); 1042 void radeon_ring_undo(struct radeon_ring *ring); 1043 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1044 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1045 void radeon_ring_lockup_update(struct radeon_device *rdev, 1046 struct radeon_ring *ring); 1047 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1048 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1049 uint32_t **data); 1050 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1051 unsigned size, uint32_t *data); 1052 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1053 unsigned rptr_offs, u32 nop); 1054 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1055 1056 1057 /* r600 async dma */ 1058 void r600_dma_stop(struct radeon_device *rdev); 1059 int r600_dma_resume(struct radeon_device *rdev); 1060 void r600_dma_fini(struct radeon_device *rdev); 1061 1062 void cayman_dma_stop(struct radeon_device *rdev); 1063 int cayman_dma_resume(struct radeon_device *rdev); 1064 void cayman_dma_fini(struct radeon_device *rdev); 1065 1066 /* 1067 * CS. 1068 */ 1069 struct radeon_cs_chunk { 1070 uint32_t length_dw; 1071 uint32_t *kdata; 1072 void __user *user_ptr; 1073 }; 1074 1075 struct radeon_cs_parser { 1076 struct device *dev; 1077 struct radeon_device *rdev; 1078 struct drm_file *filp; 1079 /* chunks */ 1080 unsigned nchunks; 1081 struct radeon_cs_chunk *chunks; 1082 uint64_t *chunks_array; 1083 /* IB */ 1084 unsigned idx; 1085 /* relocations */ 1086 unsigned nrelocs; 1087 struct radeon_bo_list *relocs; 1088 struct radeon_bo_list *vm_bos; 1089 struct list_head validated; 1090 unsigned dma_reloc_idx; 1091 /* indices of various chunks */ 1092 struct radeon_cs_chunk *chunk_ib; 1093 struct radeon_cs_chunk *chunk_relocs; 1094 struct radeon_cs_chunk *chunk_flags; 1095 struct radeon_cs_chunk *chunk_const_ib; 1096 struct radeon_ib ib; 1097 struct radeon_ib const_ib; 1098 void *track; 1099 unsigned family; 1100 int parser_error; 1101 u32 cs_flags; 1102 u32 ring; 1103 s32 priority; 1104 struct ww_acquire_ctx ticket; 1105 }; 1106 1107 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1108 { 1109 struct radeon_cs_chunk *ibc = p->chunk_ib; 1110 1111 if (ibc->kdata) 1112 return ibc->kdata[idx]; 1113 return p->ib.ptr[idx]; 1114 } 1115 1116 1117 struct radeon_cs_packet { 1118 unsigned idx; 1119 unsigned type; 1120 unsigned reg; 1121 unsigned opcode; 1122 int count; 1123 unsigned one_reg_wr; 1124 }; 1125 1126 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1127 struct radeon_cs_packet *pkt, 1128 unsigned idx, unsigned reg); 1129 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1130 struct radeon_cs_packet *pkt); 1131 1132 1133 /* 1134 * AGP 1135 */ 1136 int radeon_agp_init(struct radeon_device *rdev); 1137 void radeon_agp_resume(struct radeon_device *rdev); 1138 void radeon_agp_suspend(struct radeon_device *rdev); 1139 void radeon_agp_fini(struct radeon_device *rdev); 1140 1141 1142 /* 1143 * Writeback 1144 */ 1145 struct radeon_wb { 1146 struct radeon_bo *wb_obj; 1147 volatile uint32_t *wb; 1148 uint64_t gpu_addr; 1149 bool enabled; 1150 bool use_event; 1151 }; 1152 1153 #define RADEON_WB_SCRATCH_OFFSET 0 1154 #define RADEON_WB_RING0_NEXT_RPTR 256 1155 #define RADEON_WB_CP_RPTR_OFFSET 1024 1156 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1157 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1158 #define R600_WB_DMA_RPTR_OFFSET 1792 1159 #define R600_WB_IH_WPTR_OFFSET 2048 1160 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1161 #define R600_WB_EVENT_OFFSET 3072 1162 #define CIK_WB_CP1_WPTR_OFFSET 3328 1163 #define CIK_WB_CP2_WPTR_OFFSET 3584 1164 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1165 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1166 1167 /** 1168 * struct radeon_pm - power management datas 1169 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1170 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1171 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1172 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1173 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1174 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1175 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1176 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1177 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1178 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1179 * @needed_bandwidth: current bandwidth needs 1180 * 1181 * It keeps track of various data needed to take powermanagement decision. 1182 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1183 * Equation between gpu/memory clock and available bandwidth is hw dependent 1184 * (type of memory, bus size, efficiency, ...) 1185 */ 1186 1187 enum radeon_pm_method { 1188 PM_METHOD_PROFILE, 1189 PM_METHOD_DYNPM, 1190 PM_METHOD_DPM, 1191 }; 1192 1193 enum radeon_dynpm_state { 1194 DYNPM_STATE_DISABLED, 1195 DYNPM_STATE_MINIMUM, 1196 DYNPM_STATE_PAUSED, 1197 DYNPM_STATE_ACTIVE, 1198 DYNPM_STATE_SUSPENDED, 1199 }; 1200 enum radeon_dynpm_action { 1201 DYNPM_ACTION_NONE, 1202 DYNPM_ACTION_MINIMUM, 1203 DYNPM_ACTION_DOWNCLOCK, 1204 DYNPM_ACTION_UPCLOCK, 1205 DYNPM_ACTION_DEFAULT 1206 }; 1207 1208 enum radeon_voltage_type { 1209 VOLTAGE_NONE = 0, 1210 VOLTAGE_GPIO, 1211 VOLTAGE_VDDC, 1212 VOLTAGE_SW 1213 }; 1214 1215 enum radeon_pm_state_type { 1216 /* not used for dpm */ 1217 POWER_STATE_TYPE_DEFAULT, 1218 POWER_STATE_TYPE_POWERSAVE, 1219 /* user selectable states */ 1220 POWER_STATE_TYPE_BATTERY, 1221 POWER_STATE_TYPE_BALANCED, 1222 POWER_STATE_TYPE_PERFORMANCE, 1223 /* internal states */ 1224 POWER_STATE_TYPE_INTERNAL_UVD, 1225 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1226 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1227 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1228 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1229 POWER_STATE_TYPE_INTERNAL_BOOT, 1230 POWER_STATE_TYPE_INTERNAL_THERMAL, 1231 POWER_STATE_TYPE_INTERNAL_ACPI, 1232 POWER_STATE_TYPE_INTERNAL_ULV, 1233 POWER_STATE_TYPE_INTERNAL_3DPERF, 1234 }; 1235 1236 enum radeon_pm_profile_type { 1237 PM_PROFILE_DEFAULT, 1238 PM_PROFILE_AUTO, 1239 PM_PROFILE_LOW, 1240 PM_PROFILE_MID, 1241 PM_PROFILE_HIGH, 1242 }; 1243 1244 #define PM_PROFILE_DEFAULT_IDX 0 1245 #define PM_PROFILE_LOW_SH_IDX 1 1246 #define PM_PROFILE_MID_SH_IDX 2 1247 #define PM_PROFILE_HIGH_SH_IDX 3 1248 #define PM_PROFILE_LOW_MH_IDX 4 1249 #define PM_PROFILE_MID_MH_IDX 5 1250 #define PM_PROFILE_HIGH_MH_IDX 6 1251 #define PM_PROFILE_MAX 7 1252 1253 struct radeon_pm_profile { 1254 int dpms_off_ps_idx; 1255 int dpms_on_ps_idx; 1256 int dpms_off_cm_idx; 1257 int dpms_on_cm_idx; 1258 }; 1259 1260 enum radeon_int_thermal_type { 1261 THERMAL_TYPE_NONE, 1262 THERMAL_TYPE_EXTERNAL, 1263 THERMAL_TYPE_EXTERNAL_GPIO, 1264 THERMAL_TYPE_RV6XX, 1265 THERMAL_TYPE_RV770, 1266 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1267 THERMAL_TYPE_EVERGREEN, 1268 THERMAL_TYPE_SUMO, 1269 THERMAL_TYPE_NI, 1270 THERMAL_TYPE_SI, 1271 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1272 THERMAL_TYPE_CI, 1273 THERMAL_TYPE_KV, 1274 }; 1275 1276 struct radeon_voltage { 1277 enum radeon_voltage_type type; 1278 /* gpio voltage */ 1279 struct radeon_gpio_rec gpio; 1280 u32 delay; /* delay in usec from voltage drop to sclk change */ 1281 bool active_high; /* voltage drop is active when bit is high */ 1282 /* VDDC voltage */ 1283 u8 vddc_id; /* index into vddc voltage table */ 1284 u8 vddci_id; /* index into vddci voltage table */ 1285 bool vddci_enabled; 1286 /* r6xx+ sw */ 1287 u16 voltage; 1288 /* evergreen+ vddci */ 1289 u16 vddci; 1290 }; 1291 1292 /* clock mode flags */ 1293 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1294 1295 struct radeon_pm_clock_info { 1296 /* memory clock */ 1297 u32 mclk; 1298 /* engine clock */ 1299 u32 sclk; 1300 /* voltage info */ 1301 struct radeon_voltage voltage; 1302 /* standardized clock flags */ 1303 u32 flags; 1304 }; 1305 1306 /* state flags */ 1307 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1308 1309 struct radeon_power_state { 1310 enum radeon_pm_state_type type; 1311 struct radeon_pm_clock_info *clock_info; 1312 /* number of valid clock modes in this power state */ 1313 int num_clock_modes; 1314 struct radeon_pm_clock_info *default_clock_mode; 1315 /* standardized state flags */ 1316 u32 flags; 1317 u32 misc; /* vbios specific flags */ 1318 u32 misc2; /* vbios specific flags */ 1319 int pcie_lanes; /* pcie lanes */ 1320 }; 1321 1322 /* 1323 * Some modes are overclocked by very low value, accept them 1324 */ 1325 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1326 1327 enum radeon_dpm_auto_throttle_src { 1328 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1329 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1330 }; 1331 1332 enum radeon_dpm_event_src { 1333 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1334 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1335 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1336 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1337 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1338 }; 1339 1340 #define RADEON_MAX_VCE_LEVELS 6 1341 1342 enum radeon_vce_level { 1343 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1344 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1345 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1346 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1347 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1348 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1349 }; 1350 1351 struct radeon_ps { 1352 u32 caps; /* vbios flags */ 1353 u32 class; /* vbios flags */ 1354 u32 class2; /* vbios flags */ 1355 /* UVD clocks */ 1356 u32 vclk; 1357 u32 dclk; 1358 /* VCE clocks */ 1359 u32 evclk; 1360 u32 ecclk; 1361 bool vce_active; 1362 enum radeon_vce_level vce_level; 1363 /* asic priv */ 1364 void *ps_priv; 1365 }; 1366 1367 struct radeon_dpm_thermal { 1368 /* thermal interrupt work */ 1369 struct work_struct work; 1370 /* low temperature threshold */ 1371 int min_temp; 1372 /* high temperature threshold */ 1373 int max_temp; 1374 /* was interrupt low to high or high to low */ 1375 bool high_to_low; 1376 }; 1377 1378 enum radeon_clk_action 1379 { 1380 RADEON_SCLK_UP = 1, 1381 RADEON_SCLK_DOWN 1382 }; 1383 1384 struct radeon_blacklist_clocks 1385 { 1386 u32 sclk; 1387 u32 mclk; 1388 enum radeon_clk_action action; 1389 }; 1390 1391 struct radeon_clock_and_voltage_limits { 1392 u32 sclk; 1393 u32 mclk; 1394 u16 vddc; 1395 u16 vddci; 1396 }; 1397 1398 struct radeon_clock_array { 1399 u32 count; 1400 u32 *values; 1401 }; 1402 1403 struct radeon_clock_voltage_dependency_entry { 1404 u32 clk; 1405 u16 v; 1406 }; 1407 1408 struct radeon_clock_voltage_dependency_table { 1409 u32 count; 1410 struct radeon_clock_voltage_dependency_entry *entries; 1411 }; 1412 1413 union radeon_cac_leakage_entry { 1414 struct { 1415 u16 vddc; 1416 u32 leakage; 1417 }; 1418 struct { 1419 u16 vddc1; 1420 u16 vddc2; 1421 u16 vddc3; 1422 }; 1423 }; 1424 1425 struct radeon_cac_leakage_table { 1426 u32 count; 1427 union radeon_cac_leakage_entry *entries; 1428 }; 1429 1430 struct radeon_phase_shedding_limits_entry { 1431 u16 voltage; 1432 u32 sclk; 1433 u32 mclk; 1434 }; 1435 1436 struct radeon_phase_shedding_limits_table { 1437 u32 count; 1438 struct radeon_phase_shedding_limits_entry *entries; 1439 }; 1440 1441 struct radeon_uvd_clock_voltage_dependency_entry { 1442 u32 vclk; 1443 u32 dclk; 1444 u16 v; 1445 }; 1446 1447 struct radeon_uvd_clock_voltage_dependency_table { 1448 u8 count; 1449 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1450 }; 1451 1452 struct radeon_vce_clock_voltage_dependency_entry { 1453 u32 ecclk; 1454 u32 evclk; 1455 u16 v; 1456 }; 1457 1458 struct radeon_vce_clock_voltage_dependency_table { 1459 u8 count; 1460 struct radeon_vce_clock_voltage_dependency_entry *entries; 1461 }; 1462 1463 struct radeon_ppm_table { 1464 u8 ppm_design; 1465 u16 cpu_core_number; 1466 u32 platform_tdp; 1467 u32 small_ac_platform_tdp; 1468 u32 platform_tdc; 1469 u32 small_ac_platform_tdc; 1470 u32 apu_tdp; 1471 u32 dgpu_tdp; 1472 u32 dgpu_ulv_power; 1473 u32 tj_max; 1474 }; 1475 1476 struct radeon_cac_tdp_table { 1477 u16 tdp; 1478 u16 configurable_tdp; 1479 u16 tdc; 1480 u16 battery_power_limit; 1481 u16 small_power_limit; 1482 u16 low_cac_leakage; 1483 u16 high_cac_leakage; 1484 u16 maximum_power_delivery_limit; 1485 }; 1486 1487 struct radeon_dpm_dynamic_state { 1488 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1489 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1490 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1491 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1492 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1493 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1494 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1495 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1496 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1497 struct radeon_clock_array valid_sclk_values; 1498 struct radeon_clock_array valid_mclk_values; 1499 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1500 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1501 u32 mclk_sclk_ratio; 1502 u32 sclk_mclk_delta; 1503 u16 vddc_vddci_delta; 1504 u16 min_vddc_for_pcie_gen2; 1505 struct radeon_cac_leakage_table cac_leakage_table; 1506 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1507 struct radeon_ppm_table *ppm_table; 1508 struct radeon_cac_tdp_table *cac_tdp_table; 1509 }; 1510 1511 struct radeon_dpm_fan { 1512 u16 t_min; 1513 u16 t_med; 1514 u16 t_high; 1515 u16 pwm_min; 1516 u16 pwm_med; 1517 u16 pwm_high; 1518 u8 t_hyst; 1519 u32 cycle_delay; 1520 u16 t_max; 1521 u8 control_mode; 1522 u16 default_max_fan_pwm; 1523 u16 default_fan_output_sensitivity; 1524 u16 fan_output_sensitivity; 1525 bool ucode_fan_control; 1526 }; 1527 1528 enum radeon_pcie_gen { 1529 RADEON_PCIE_GEN1 = 0, 1530 RADEON_PCIE_GEN2 = 1, 1531 RADEON_PCIE_GEN3 = 2, 1532 RADEON_PCIE_GEN_INVALID = 0xffff 1533 }; 1534 1535 enum radeon_dpm_forced_level { 1536 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1537 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1538 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1539 }; 1540 1541 struct radeon_vce_state { 1542 /* vce clocks */ 1543 u32 evclk; 1544 u32 ecclk; 1545 /* gpu clocks */ 1546 u32 sclk; 1547 u32 mclk; 1548 u8 clk_idx; 1549 u8 pstate; 1550 }; 1551 1552 struct radeon_dpm { 1553 struct radeon_ps *ps; 1554 /* number of valid power states */ 1555 int num_ps; 1556 /* current power state that is active */ 1557 struct radeon_ps *current_ps; 1558 /* requested power state */ 1559 struct radeon_ps *requested_ps; 1560 /* boot up power state */ 1561 struct radeon_ps *boot_ps; 1562 /* default uvd power state */ 1563 struct radeon_ps *uvd_ps; 1564 /* vce requirements */ 1565 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1566 enum radeon_vce_level vce_level; 1567 enum radeon_pm_state_type state; 1568 enum radeon_pm_state_type user_state; 1569 u32 platform_caps; 1570 u32 voltage_response_time; 1571 u32 backbias_response_time; 1572 void *priv; 1573 u32 new_active_crtcs; 1574 int new_active_crtc_count; 1575 u32 current_active_crtcs; 1576 int current_active_crtc_count; 1577 bool single_display; 1578 struct radeon_dpm_dynamic_state dyn_state; 1579 struct radeon_dpm_fan fan; 1580 u32 tdp_limit; 1581 u32 near_tdp_limit; 1582 u32 near_tdp_limit_adjusted; 1583 u32 sq_ramping_threshold; 1584 u32 cac_leakage; 1585 u16 tdp_od_limit; 1586 u32 tdp_adjustment; 1587 u16 load_line_slope; 1588 bool power_control; 1589 bool ac_power; 1590 /* special states active */ 1591 bool thermal_active; 1592 bool uvd_active; 1593 bool vce_active; 1594 /* thermal handling */ 1595 struct radeon_dpm_thermal thermal; 1596 /* forced levels */ 1597 enum radeon_dpm_forced_level forced_level; 1598 /* track UVD streams */ 1599 unsigned sd; 1600 unsigned hd; 1601 }; 1602 1603 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1604 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1605 1606 struct radeon_pm { 1607 struct rwlock mutex; 1608 /* write locked while reprogramming mclk */ 1609 struct rwlock mclk_lock; 1610 u32 active_crtcs; 1611 int active_crtc_count; 1612 int req_vblank; 1613 bool vblank_sync; 1614 fixed20_12 max_bandwidth; 1615 fixed20_12 igp_sideport_mclk; 1616 fixed20_12 igp_system_mclk; 1617 fixed20_12 igp_ht_link_clk; 1618 fixed20_12 igp_ht_link_width; 1619 fixed20_12 k8_bandwidth; 1620 fixed20_12 sideport_bandwidth; 1621 fixed20_12 ht_bandwidth; 1622 fixed20_12 core_bandwidth; 1623 fixed20_12 sclk; 1624 fixed20_12 mclk; 1625 fixed20_12 needed_bandwidth; 1626 struct radeon_power_state *power_state; 1627 /* number of valid power states */ 1628 int num_power_states; 1629 int current_power_state_index; 1630 int current_clock_mode_index; 1631 int requested_power_state_index; 1632 int requested_clock_mode_index; 1633 int default_power_state_index; 1634 u32 current_sclk; 1635 u32 current_mclk; 1636 u16 current_vddc; 1637 u16 current_vddci; 1638 u32 default_sclk; 1639 u32 default_mclk; 1640 u16 default_vddc; 1641 u16 default_vddci; 1642 struct radeon_i2c_chan *i2c_bus; 1643 /* selected pm method */ 1644 enum radeon_pm_method pm_method; 1645 /* dynpm power management */ 1646 struct delayed_work dynpm_idle_work; 1647 enum radeon_dynpm_state dynpm_state; 1648 enum radeon_dynpm_action dynpm_planned_action; 1649 unsigned long dynpm_action_timeout; 1650 bool dynpm_can_upclock; 1651 bool dynpm_can_downclock; 1652 /* profile-based power management */ 1653 enum radeon_pm_profile_type profile; 1654 int profile_index; 1655 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1656 /* internal thermal controller on rv6xx+ */ 1657 enum radeon_int_thermal_type int_thermal_type; 1658 struct device *int_hwmon_dev; 1659 /* fan control parameters */ 1660 bool no_fan; 1661 u8 fan_pulses_per_revolution; 1662 u8 fan_min_rpm; 1663 u8 fan_max_rpm; 1664 /* dpm */ 1665 bool dpm_enabled; 1666 bool sysfs_initialized; 1667 struct radeon_dpm dpm; 1668 }; 1669 1670 #define RADEON_PCIE_SPEED_25 1 1671 #define RADEON_PCIE_SPEED_50 2 1672 #define RADEON_PCIE_SPEED_80 4 1673 1674 int radeon_pm_get_type_index(struct radeon_device *rdev, 1675 enum radeon_pm_state_type ps_type, 1676 int instance); 1677 /* 1678 * UVD 1679 */ 1680 #define RADEON_DEFAULT_UVD_HANDLES 10 1681 #define RADEON_MAX_UVD_HANDLES 30 1682 #define RADEON_UVD_STACK_SIZE (200*1024) 1683 #define RADEON_UVD_HEAP_SIZE (256*1024) 1684 #define RADEON_UVD_SESSION_SIZE (50*1024) 1685 1686 struct radeon_uvd { 1687 bool fw_header_present; 1688 struct radeon_bo *vcpu_bo; 1689 void *cpu_addr; 1690 uint64_t gpu_addr; 1691 unsigned max_handles; 1692 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1693 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1694 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1695 struct delayed_work idle_work; 1696 }; 1697 1698 int radeon_uvd_init(struct radeon_device *rdev); 1699 void radeon_uvd_fini(struct radeon_device *rdev); 1700 int radeon_uvd_suspend(struct radeon_device *rdev); 1701 int radeon_uvd_resume(struct radeon_device *rdev); 1702 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1703 uint32_t handle, struct radeon_fence **fence); 1704 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1705 uint32_t handle, struct radeon_fence **fence); 1706 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1707 uint32_t allowed_domains); 1708 void radeon_uvd_free_handles(struct radeon_device *rdev, 1709 struct drm_file *filp); 1710 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1711 void radeon_uvd_note_usage(struct radeon_device *rdev); 1712 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1713 unsigned vclk, unsigned dclk, 1714 unsigned vco_min, unsigned vco_max, 1715 unsigned fb_factor, unsigned fb_mask, 1716 unsigned pd_min, unsigned pd_max, 1717 unsigned pd_even, 1718 unsigned *optimal_fb_div, 1719 unsigned *optimal_vclk_div, 1720 unsigned *optimal_dclk_div); 1721 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1722 unsigned cg_upll_func_cntl); 1723 1724 /* 1725 * VCE 1726 */ 1727 #define RADEON_MAX_VCE_HANDLES 16 1728 1729 struct radeon_vce { 1730 struct radeon_bo *vcpu_bo; 1731 uint64_t gpu_addr; 1732 unsigned fw_version; 1733 unsigned fb_version; 1734 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1735 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1736 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1737 struct delayed_work idle_work; 1738 uint32_t keyselect; 1739 }; 1740 1741 int radeon_vce_init(struct radeon_device *rdev); 1742 void radeon_vce_fini(struct radeon_device *rdev); 1743 int radeon_vce_suspend(struct radeon_device *rdev); 1744 int radeon_vce_resume(struct radeon_device *rdev); 1745 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1746 uint32_t handle, struct radeon_fence **fence); 1747 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1748 uint32_t handle, struct radeon_fence **fence); 1749 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1750 void radeon_vce_note_usage(struct radeon_device *rdev); 1751 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1752 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1753 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1754 struct radeon_ring *ring, 1755 struct radeon_semaphore *semaphore, 1756 bool emit_wait); 1757 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1758 void radeon_vce_fence_emit(struct radeon_device *rdev, 1759 struct radeon_fence *fence); 1760 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1761 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1762 1763 struct r600_audio_pin { 1764 int channels; 1765 int rate; 1766 int bits_per_sample; 1767 u8 status_bits; 1768 u8 category_code; 1769 u32 offset; 1770 bool connected; 1771 u32 id; 1772 }; 1773 1774 struct r600_audio { 1775 bool enabled; 1776 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1777 int num_pins; 1778 struct radeon_audio_funcs *hdmi_funcs; 1779 struct radeon_audio_funcs *dp_funcs; 1780 struct radeon_audio_basic_funcs *funcs; 1781 }; 1782 1783 /* 1784 * Benchmarking 1785 */ 1786 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1787 1788 1789 /* 1790 * Testing 1791 */ 1792 void radeon_test_moves(struct radeon_device *rdev); 1793 void radeon_test_ring_sync(struct radeon_device *rdev, 1794 struct radeon_ring *cpA, 1795 struct radeon_ring *cpB); 1796 void radeon_test_syncing(struct radeon_device *rdev); 1797 1798 /* 1799 * MMU Notifier 1800 */ 1801 #if defined(CONFIG_MMU_NOTIFIER) 1802 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1803 void radeon_mn_unregister(struct radeon_bo *bo); 1804 #else 1805 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1806 { 1807 return -ENODEV; 1808 } 1809 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1810 #endif 1811 1812 /* 1813 * Debugfs 1814 */ 1815 struct radeon_debugfs { 1816 struct drm_info_list *files; 1817 unsigned num_files; 1818 }; 1819 1820 int radeon_debugfs_add_files(struct radeon_device *rdev, 1821 struct drm_info_list *files, 1822 unsigned nfiles); 1823 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1824 1825 /* 1826 * ASIC ring specific functions. 1827 */ 1828 struct radeon_asic_ring { 1829 /* ring read/write ptr handling */ 1830 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1831 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1832 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1833 1834 /* validating and patching of IBs */ 1835 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1836 int (*cs_parse)(struct radeon_cs_parser *p); 1837 1838 /* command emmit functions */ 1839 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1840 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1841 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1842 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1843 struct radeon_semaphore *semaphore, bool emit_wait); 1844 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1845 unsigned vm_id, uint64_t pd_addr); 1846 1847 /* testing functions */ 1848 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1849 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1850 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1851 1852 /* deprecated */ 1853 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1854 }; 1855 1856 /* 1857 * ASIC specific functions. 1858 */ 1859 struct radeon_asic { 1860 int (*init)(struct radeon_device *rdev); 1861 void (*fini)(struct radeon_device *rdev); 1862 int (*resume)(struct radeon_device *rdev); 1863 int (*suspend)(struct radeon_device *rdev); 1864 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1865 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1866 /* Flush the HDP cache via MMIO */ 1867 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1868 /* check if 3D engine is idle */ 1869 bool (*gui_idle)(struct radeon_device *rdev); 1870 /* wait for mc_idle */ 1871 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1872 /* get the reference clock */ 1873 u32 (*get_xclk)(struct radeon_device *rdev); 1874 /* get the gpu clock counter */ 1875 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1876 /* get register for info ioctl */ 1877 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1878 /* gart */ 1879 struct { 1880 void (*tlb_flush)(struct radeon_device *rdev); 1881 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1882 void (*set_page)(struct radeon_device *rdev, unsigned i, 1883 uint64_t entry); 1884 } gart; 1885 struct { 1886 int (*init)(struct radeon_device *rdev); 1887 void (*fini)(struct radeon_device *rdev); 1888 void (*copy_pages)(struct radeon_device *rdev, 1889 struct radeon_ib *ib, 1890 uint64_t pe, uint64_t src, 1891 unsigned count); 1892 void (*write_pages)(struct radeon_device *rdev, 1893 struct radeon_ib *ib, 1894 uint64_t pe, 1895 uint64_t addr, unsigned count, 1896 uint32_t incr, uint32_t flags); 1897 void (*set_pages)(struct radeon_device *rdev, 1898 struct radeon_ib *ib, 1899 uint64_t pe, 1900 uint64_t addr, unsigned count, 1901 uint32_t incr, uint32_t flags); 1902 void (*pad_ib)(struct radeon_ib *ib); 1903 } vm; 1904 /* ring specific callbacks */ 1905 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1906 /* irqs */ 1907 struct { 1908 int (*set)(struct radeon_device *rdev); 1909 int (*process)(struct radeon_device *rdev); 1910 } irq; 1911 /* displays */ 1912 struct { 1913 /* display watermarks */ 1914 void (*bandwidth_update)(struct radeon_device *rdev); 1915 /* get frame count */ 1916 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1917 /* wait for vblank */ 1918 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1919 /* set backlight level */ 1920 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1921 /* get backlight level */ 1922 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1923 /* audio callbacks */ 1924 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1925 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1926 } display; 1927 /* copy functions for bo handling */ 1928 struct { 1929 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1930 uint64_t src_offset, 1931 uint64_t dst_offset, 1932 unsigned num_gpu_pages, 1933 struct dma_resv *resv); 1934 u32 blit_ring_index; 1935 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1936 uint64_t src_offset, 1937 uint64_t dst_offset, 1938 unsigned num_gpu_pages, 1939 struct dma_resv *resv); 1940 u32 dma_ring_index; 1941 /* method used for bo copy */ 1942 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1943 uint64_t src_offset, 1944 uint64_t dst_offset, 1945 unsigned num_gpu_pages, 1946 struct dma_resv *resv); 1947 /* ring used for bo copies */ 1948 u32 copy_ring_index; 1949 } copy; 1950 /* surfaces */ 1951 struct { 1952 int (*set_reg)(struct radeon_device *rdev, int reg, 1953 uint32_t tiling_flags, uint32_t pitch, 1954 uint32_t offset, uint32_t obj_size); 1955 void (*clear_reg)(struct radeon_device *rdev, int reg); 1956 } surface; 1957 /* hotplug detect */ 1958 struct { 1959 void (*init)(struct radeon_device *rdev); 1960 void (*fini)(struct radeon_device *rdev); 1961 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1962 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1963 } hpd; 1964 /* static power management */ 1965 struct { 1966 void (*misc)(struct radeon_device *rdev); 1967 void (*prepare)(struct radeon_device *rdev); 1968 void (*finish)(struct radeon_device *rdev); 1969 void (*init_profile)(struct radeon_device *rdev); 1970 void (*get_dynpm_state)(struct radeon_device *rdev); 1971 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1972 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1973 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1974 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1975 int (*get_pcie_lanes)(struct radeon_device *rdev); 1976 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1977 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1978 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1979 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1980 int (*get_temperature)(struct radeon_device *rdev); 1981 } pm; 1982 /* dynamic power management */ 1983 struct { 1984 int (*init)(struct radeon_device *rdev); 1985 void (*setup_asic)(struct radeon_device *rdev); 1986 int (*enable)(struct radeon_device *rdev); 1987 int (*late_enable)(struct radeon_device *rdev); 1988 void (*disable)(struct radeon_device *rdev); 1989 int (*pre_set_power_state)(struct radeon_device *rdev); 1990 int (*set_power_state)(struct radeon_device *rdev); 1991 void (*post_set_power_state)(struct radeon_device *rdev); 1992 void (*display_configuration_changed)(struct radeon_device *rdev); 1993 void (*fini)(struct radeon_device *rdev); 1994 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1995 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1996 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1997 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1998 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1999 bool (*vblank_too_short)(struct radeon_device *rdev); 2000 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 2001 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 2002 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 2003 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 2004 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 2005 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 2006 u32 (*get_current_sclk)(struct radeon_device *rdev); 2007 u32 (*get_current_mclk)(struct radeon_device *rdev); 2008 } dpm; 2009 /* pageflipping */ 2010 struct { 2011 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 2012 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2013 } pflip; 2014 }; 2015 2016 /* 2017 * Asic structures 2018 */ 2019 struct r100_asic { 2020 const unsigned *reg_safe_bm; 2021 unsigned reg_safe_bm_size; 2022 u32 hdp_cntl; 2023 }; 2024 2025 struct r300_asic { 2026 const unsigned *reg_safe_bm; 2027 unsigned reg_safe_bm_size; 2028 u32 resync_scratch; 2029 u32 hdp_cntl; 2030 }; 2031 2032 struct r600_asic { 2033 unsigned max_pipes; 2034 unsigned max_tile_pipes; 2035 unsigned max_simds; 2036 unsigned max_backends; 2037 unsigned max_gprs; 2038 unsigned max_threads; 2039 unsigned max_stack_entries; 2040 unsigned max_hw_contexts; 2041 unsigned max_gs_threads; 2042 unsigned sx_max_export_size; 2043 unsigned sx_max_export_pos_size; 2044 unsigned sx_max_export_smx_size; 2045 unsigned sq_num_cf_insts; 2046 unsigned tiling_nbanks; 2047 unsigned tiling_npipes; 2048 unsigned tiling_group_size; 2049 unsigned tile_config; 2050 unsigned backend_map; 2051 unsigned active_simds; 2052 }; 2053 2054 struct rv770_asic { 2055 unsigned max_pipes; 2056 unsigned max_tile_pipes; 2057 unsigned max_simds; 2058 unsigned max_backends; 2059 unsigned max_gprs; 2060 unsigned max_threads; 2061 unsigned max_stack_entries; 2062 unsigned max_hw_contexts; 2063 unsigned max_gs_threads; 2064 unsigned sx_max_export_size; 2065 unsigned sx_max_export_pos_size; 2066 unsigned sx_max_export_smx_size; 2067 unsigned sq_num_cf_insts; 2068 unsigned sx_num_of_sets; 2069 unsigned sc_prim_fifo_size; 2070 unsigned sc_hiz_tile_fifo_size; 2071 unsigned sc_earlyz_tile_fifo_fize; 2072 unsigned tiling_nbanks; 2073 unsigned tiling_npipes; 2074 unsigned tiling_group_size; 2075 unsigned tile_config; 2076 unsigned backend_map; 2077 unsigned active_simds; 2078 }; 2079 2080 struct evergreen_asic { 2081 unsigned num_ses; 2082 unsigned max_pipes; 2083 unsigned max_tile_pipes; 2084 unsigned max_simds; 2085 unsigned max_backends; 2086 unsigned max_gprs; 2087 unsigned max_threads; 2088 unsigned max_stack_entries; 2089 unsigned max_hw_contexts; 2090 unsigned max_gs_threads; 2091 unsigned sx_max_export_size; 2092 unsigned sx_max_export_pos_size; 2093 unsigned sx_max_export_smx_size; 2094 unsigned sq_num_cf_insts; 2095 unsigned sx_num_of_sets; 2096 unsigned sc_prim_fifo_size; 2097 unsigned sc_hiz_tile_fifo_size; 2098 unsigned sc_earlyz_tile_fifo_size; 2099 unsigned tiling_nbanks; 2100 unsigned tiling_npipes; 2101 unsigned tiling_group_size; 2102 unsigned tile_config; 2103 unsigned backend_map; 2104 unsigned active_simds; 2105 }; 2106 2107 struct cayman_asic { 2108 unsigned max_shader_engines; 2109 unsigned max_pipes_per_simd; 2110 unsigned max_tile_pipes; 2111 unsigned max_simds_per_se; 2112 unsigned max_backends_per_se; 2113 unsigned max_texture_channel_caches; 2114 unsigned max_gprs; 2115 unsigned max_threads; 2116 unsigned max_gs_threads; 2117 unsigned max_stack_entries; 2118 unsigned sx_num_of_sets; 2119 unsigned sx_max_export_size; 2120 unsigned sx_max_export_pos_size; 2121 unsigned sx_max_export_smx_size; 2122 unsigned max_hw_contexts; 2123 unsigned sq_num_cf_insts; 2124 unsigned sc_prim_fifo_size; 2125 unsigned sc_hiz_tile_fifo_size; 2126 unsigned sc_earlyz_tile_fifo_size; 2127 2128 unsigned num_shader_engines; 2129 unsigned num_shader_pipes_per_simd; 2130 unsigned num_tile_pipes; 2131 unsigned num_simds_per_se; 2132 unsigned num_backends_per_se; 2133 unsigned backend_disable_mask_per_asic; 2134 unsigned backend_map; 2135 unsigned num_texture_channel_caches; 2136 unsigned mem_max_burst_length_bytes; 2137 unsigned mem_row_size_in_kb; 2138 unsigned shader_engine_tile_size; 2139 unsigned num_gpus; 2140 unsigned multi_gpu_tile_size; 2141 2142 unsigned tile_config; 2143 unsigned active_simds; 2144 }; 2145 2146 struct si_asic { 2147 unsigned max_shader_engines; 2148 unsigned max_tile_pipes; 2149 unsigned max_cu_per_sh; 2150 unsigned max_sh_per_se; 2151 unsigned max_backends_per_se; 2152 unsigned max_texture_channel_caches; 2153 unsigned max_gprs; 2154 unsigned max_gs_threads; 2155 unsigned max_hw_contexts; 2156 unsigned sc_prim_fifo_size_frontend; 2157 unsigned sc_prim_fifo_size_backend; 2158 unsigned sc_hiz_tile_fifo_size; 2159 unsigned sc_earlyz_tile_fifo_size; 2160 2161 unsigned num_tile_pipes; 2162 unsigned backend_enable_mask; 2163 unsigned backend_disable_mask_per_asic; 2164 unsigned backend_map; 2165 unsigned num_texture_channel_caches; 2166 unsigned mem_max_burst_length_bytes; 2167 unsigned mem_row_size_in_kb; 2168 unsigned shader_engine_tile_size; 2169 unsigned num_gpus; 2170 unsigned multi_gpu_tile_size; 2171 2172 unsigned tile_config; 2173 uint32_t tile_mode_array[32]; 2174 uint32_t active_cus; 2175 }; 2176 2177 struct cik_asic { 2178 unsigned max_shader_engines; 2179 unsigned max_tile_pipes; 2180 unsigned max_cu_per_sh; 2181 unsigned max_sh_per_se; 2182 unsigned max_backends_per_se; 2183 unsigned max_texture_channel_caches; 2184 unsigned max_gprs; 2185 unsigned max_gs_threads; 2186 unsigned max_hw_contexts; 2187 unsigned sc_prim_fifo_size_frontend; 2188 unsigned sc_prim_fifo_size_backend; 2189 unsigned sc_hiz_tile_fifo_size; 2190 unsigned sc_earlyz_tile_fifo_size; 2191 2192 unsigned num_tile_pipes; 2193 unsigned backend_enable_mask; 2194 unsigned backend_disable_mask_per_asic; 2195 unsigned backend_map; 2196 unsigned num_texture_channel_caches; 2197 unsigned mem_max_burst_length_bytes; 2198 unsigned mem_row_size_in_kb; 2199 unsigned shader_engine_tile_size; 2200 unsigned num_gpus; 2201 unsigned multi_gpu_tile_size; 2202 2203 unsigned tile_config; 2204 uint32_t tile_mode_array[32]; 2205 uint32_t macrotile_mode_array[16]; 2206 uint32_t active_cus; 2207 }; 2208 2209 union radeon_asic_config { 2210 struct r300_asic r300; 2211 struct r100_asic r100; 2212 struct r600_asic r600; 2213 struct rv770_asic rv770; 2214 struct evergreen_asic evergreen; 2215 struct cayman_asic cayman; 2216 struct si_asic si; 2217 struct cik_asic cik; 2218 }; 2219 2220 /* 2221 * asic initizalization from radeon_asic.c 2222 */ 2223 void radeon_agp_disable(struct radeon_device *rdev); 2224 int radeon_asic_init(struct radeon_device *rdev); 2225 2226 2227 /* 2228 * IOCTL. 2229 */ 2230 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2231 struct drm_file *filp); 2232 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2233 struct drm_file *filp); 2234 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2235 struct drm_file *filp); 2236 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2237 struct drm_file *file_priv); 2238 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2239 struct drm_file *file_priv); 2240 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2241 struct drm_file *file_priv); 2242 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2243 struct drm_file *file_priv); 2244 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2245 struct drm_file *filp); 2246 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2247 struct drm_file *filp); 2248 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2249 struct drm_file *filp); 2250 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2251 struct drm_file *filp); 2252 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2253 struct drm_file *filp); 2254 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2255 struct drm_file *filp); 2256 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2257 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2258 struct drm_file *filp); 2259 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2260 struct drm_file *filp); 2261 2262 /* VRAM scratch page for HDP bug, default vram page */ 2263 struct r600_vram_scratch { 2264 struct radeon_bo *robj; 2265 volatile uint32_t *ptr; 2266 u64 gpu_addr; 2267 }; 2268 2269 /* 2270 * ACPI 2271 */ 2272 struct radeon_atif_notification_cfg { 2273 bool enabled; 2274 int command_code; 2275 }; 2276 2277 struct radeon_atif_notifications { 2278 bool display_switch; 2279 bool expansion_mode_change; 2280 bool thermal_state; 2281 bool forced_power_state; 2282 bool system_power_state; 2283 bool display_conf_change; 2284 bool px_gfx_switch; 2285 bool brightness_change; 2286 bool dgpu_display_event; 2287 }; 2288 2289 struct radeon_atif_functions { 2290 bool system_params; 2291 bool sbios_requests; 2292 bool select_active_disp; 2293 bool lid_state; 2294 bool get_tv_standard; 2295 bool set_tv_standard; 2296 bool get_panel_expansion_mode; 2297 bool set_panel_expansion_mode; 2298 bool temperature_change; 2299 bool graphics_device_types; 2300 }; 2301 2302 struct radeon_atif { 2303 struct radeon_atif_notifications notifications; 2304 struct radeon_atif_functions functions; 2305 struct radeon_atif_notification_cfg notification_cfg; 2306 struct radeon_encoder *encoder_for_bl; 2307 }; 2308 2309 struct radeon_atcs_functions { 2310 bool get_ext_state; 2311 bool pcie_perf_req; 2312 bool pcie_dev_rdy; 2313 bool pcie_bus_width; 2314 }; 2315 2316 struct radeon_atcs { 2317 struct radeon_atcs_functions functions; 2318 }; 2319 2320 /* 2321 * Core structure, functions and helpers. 2322 */ 2323 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2324 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2325 2326 struct radeon_device { 2327 struct device self; 2328 struct device *dev; 2329 struct drm_device *ddev; 2330 struct pci_dev *pdev; 2331 struct rwlock exclusive_lock; 2332 2333 pci_chipset_tag_t pc; 2334 pcitag_t pa_tag; 2335 pci_intr_handle_t intrh; 2336 bus_space_tag_t iot; 2337 bus_space_tag_t memt; 2338 bus_dma_tag_t dmat; 2339 void *irqh; 2340 2341 void (*switchcb)(void *, int, int); 2342 void *switchcbarg; 2343 void *switchcookie; 2344 struct task switchtask; 2345 struct rasops_info ro; 2346 int console; 2347 int primary; 2348 2349 struct task burner_task; 2350 int burner_fblank; 2351 2352 #ifdef __sparc64__ 2353 struct sunfb sf; 2354 bus_size_t fb_offset; 2355 bus_space_handle_t memh; 2356 #endif 2357 2358 unsigned long fb_aper_offset; 2359 unsigned long fb_aper_size; 2360 2361 /* ASIC */ 2362 union radeon_asic_config config; 2363 enum radeon_family family; 2364 unsigned long flags; 2365 int usec_timeout; 2366 enum radeon_pll_errata pll_errata; 2367 int num_gb_pipes; 2368 int num_z_pipes; 2369 int disp_priority; 2370 /* BIOS */ 2371 uint8_t *bios; 2372 bool is_atom_bios; 2373 uint16_t bios_header_start; 2374 struct radeon_bo *stolen_vga_memory; 2375 /* Register mmio */ 2376 resource_size_t rmmio_base; 2377 resource_size_t rmmio_size; 2378 /* protects concurrent MM_INDEX/DATA based register access */ 2379 spinlock_t mmio_idx_lock; 2380 /* protects concurrent SMC based register access */ 2381 spinlock_t smc_idx_lock; 2382 /* protects concurrent PLL register access */ 2383 spinlock_t pll_idx_lock; 2384 /* protects concurrent MC register access */ 2385 spinlock_t mc_idx_lock; 2386 /* protects concurrent PCIE register access */ 2387 spinlock_t pcie_idx_lock; 2388 /* protects concurrent PCIE_PORT register access */ 2389 spinlock_t pciep_idx_lock; 2390 /* protects concurrent PIF register access */ 2391 spinlock_t pif_idx_lock; 2392 /* protects concurrent CG register access */ 2393 spinlock_t cg_idx_lock; 2394 /* protects concurrent UVD register access */ 2395 spinlock_t uvd_idx_lock; 2396 /* protects concurrent RCU register access */ 2397 spinlock_t rcu_idx_lock; 2398 /* protects concurrent DIDT register access */ 2399 spinlock_t didt_idx_lock; 2400 /* protects concurrent ENDPOINT (audio) register access */ 2401 spinlock_t end_idx_lock; 2402 bus_space_handle_t rmmio_bsh; 2403 void __iomem *rmmio; 2404 radeon_rreg_t mc_rreg; 2405 radeon_wreg_t mc_wreg; 2406 radeon_rreg_t pll_rreg; 2407 radeon_wreg_t pll_wreg; 2408 uint32_t pcie_reg_mask; 2409 radeon_rreg_t pciep_rreg; 2410 radeon_wreg_t pciep_wreg; 2411 /* io port */ 2412 bus_space_handle_t rio_mem; 2413 resource_size_t rio_mem_size; 2414 struct radeon_clock clock; 2415 struct radeon_mc mc; 2416 struct radeon_gart gart; 2417 struct radeon_mode_info mode_info; 2418 struct radeon_scratch scratch; 2419 struct radeon_doorbell doorbell; 2420 struct radeon_mman mman; 2421 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2422 wait_queue_head_t fence_queue; 2423 u64 fence_context; 2424 struct rwlock ring_lock; 2425 struct radeon_ring ring[RADEON_NUM_RINGS]; 2426 bool ib_pool_ready; 2427 struct radeon_sa_manager ring_tmp_bo; 2428 struct radeon_irq irq; 2429 struct radeon_asic *asic; 2430 struct radeon_gem gem; 2431 struct radeon_pm pm; 2432 struct radeon_uvd uvd; 2433 struct radeon_vce vce; 2434 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2435 struct radeon_wb wb; 2436 struct radeon_dummy_page dummy_page; 2437 bool shutdown; 2438 bool need_swiotlb; 2439 bool accel_working; 2440 bool fastfb_working; /* IGP feature*/ 2441 bool needs_reset, in_reset; 2442 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2443 const struct firmware *me_fw; /* all family ME firmware */ 2444 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2445 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2446 const struct firmware *mc_fw; /* NI MC firmware */ 2447 const struct firmware *ce_fw; /* SI CE firmware */ 2448 const struct firmware *mec_fw; /* CIK MEC firmware */ 2449 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2450 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2451 const struct firmware *smc_fw; /* SMC firmware */ 2452 const struct firmware *uvd_fw; /* UVD firmware */ 2453 const struct firmware *vce_fw; /* VCE firmware */ 2454 bool new_fw; 2455 struct r600_vram_scratch vram_scratch; 2456 int msi_enabled; /* msi enabled */ 2457 struct r600_ih ih; /* r6/700 interrupt ring */ 2458 struct radeon_rlc rlc; 2459 struct radeon_mec mec; 2460 struct delayed_work hotplug_work; 2461 struct work_struct dp_work; 2462 struct work_struct audio_work; 2463 int num_crtc; /* number of crtcs */ 2464 struct rwlock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2465 bool has_uvd; 2466 bool has_vce; 2467 struct r600_audio audio; /* audio stuff */ 2468 struct notifier_block acpi_nb; 2469 /* only one userspace can use Hyperz features or CMASK at a time */ 2470 struct drm_file *hyperz_filp; 2471 struct drm_file *cmask_filp; 2472 /* i2c buses */ 2473 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2474 /* debugfs */ 2475 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2476 unsigned debugfs_count; 2477 /* virtual memory */ 2478 struct radeon_vm_manager vm_manager; 2479 struct rwlock gpu_clock_mutex; 2480 /* memory stats */ 2481 atomic64_t vram_usage; 2482 atomic64_t gtt_usage; 2483 atomic64_t num_bytes_moved; 2484 atomic_t gpu_reset_counter; 2485 /* ACPI interface */ 2486 struct radeon_atif atif; 2487 struct radeon_atcs atcs; 2488 /* srbm instance registers */ 2489 struct rwlock srbm_mutex; 2490 /* clock, powergating flags */ 2491 u32 cg_flags; 2492 u32 pg_flags; 2493 2494 struct dev_pm_domain vga_pm_domain; 2495 bool have_disp_power_ref; 2496 u32 px_quirk_flags; 2497 2498 /* tracking pinned memory */ 2499 u64 vram_pin_size; 2500 u64 gart_pin_size; 2501 }; 2502 2503 bool radeon_is_px(struct drm_device *dev); 2504 int radeon_device_init(struct radeon_device *rdev, 2505 struct drm_device *ddev, 2506 struct pci_dev *pdev, 2507 uint32_t flags); 2508 void radeon_device_fini(struct radeon_device *rdev); 2509 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2510 2511 #define RADEON_MIN_MMIO_SIZE 0x10000 2512 2513 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2514 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2515 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2516 bool always_indirect) 2517 { 2518 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2519 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2520 return readl(((void __iomem *)rdev->rmmio) + reg); 2521 else 2522 return r100_mm_rreg_slow(rdev, reg); 2523 } 2524 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2525 bool always_indirect) 2526 { 2527 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2528 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2529 else 2530 r100_mm_wreg_slow(rdev, reg, v); 2531 } 2532 2533 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2534 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2535 2536 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2537 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2538 2539 /* 2540 * Cast helper 2541 */ 2542 extern const struct dma_fence_ops radeon_fence_ops; 2543 2544 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2545 { 2546 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2547 2548 if (__f->base.ops == &radeon_fence_ops) 2549 return __f; 2550 2551 return NULL; 2552 } 2553 2554 /* 2555 * Registers read & write functions. 2556 */ 2557 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2558 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2559 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2560 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2561 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2562 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2563 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2564 r100_mm_rreg(rdev, (reg), false)) 2565 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2566 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2567 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2568 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2569 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2570 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2571 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2572 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2573 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2574 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2575 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2576 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2577 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2578 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2579 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2580 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2581 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2582 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2583 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2584 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2585 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2586 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2587 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2588 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2589 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2590 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2591 #define WREG32_P(reg, val, mask) \ 2592 do { \ 2593 uint32_t tmp_ = RREG32(reg); \ 2594 tmp_ &= (mask); \ 2595 tmp_ |= ((val) & ~(mask)); \ 2596 WREG32(reg, tmp_); \ 2597 } while (0) 2598 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2599 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2600 #define WREG32_PLL_P(reg, val, mask) \ 2601 do { \ 2602 uint32_t tmp_ = RREG32_PLL(reg); \ 2603 tmp_ &= (mask); \ 2604 tmp_ |= ((val) & ~(mask)); \ 2605 WREG32_PLL(reg, tmp_); \ 2606 } while (0) 2607 #define WREG32_SMC_P(reg, val, mask) \ 2608 do { \ 2609 uint32_t tmp_ = RREG32_SMC(reg); \ 2610 tmp_ &= (mask); \ 2611 tmp_ |= ((val) & ~(mask)); \ 2612 WREG32_SMC(reg, tmp_); \ 2613 } while (0) 2614 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2615 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2616 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2617 2618 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2619 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2620 2621 /* 2622 * Indirect registers accessors. 2623 * They used to be inlined, but this increases code size by ~65 kbytes. 2624 * Since each performs a pair of MMIO ops 2625 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2626 * the cost of call+ret is almost negligible. MMIO and locking 2627 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2628 */ 2629 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2630 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2631 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2632 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2633 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2634 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2635 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2636 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2637 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2638 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2639 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2640 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2641 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2642 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2643 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2644 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2645 2646 void r100_pll_errata_after_index(struct radeon_device *rdev); 2647 2648 2649 /* 2650 * ASICs helpers. 2651 */ 2652 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2653 (rdev->pdev->device == 0x5969)) 2654 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2655 (rdev->family == CHIP_RV200) || \ 2656 (rdev->family == CHIP_RS100) || \ 2657 (rdev->family == CHIP_RS200) || \ 2658 (rdev->family == CHIP_RV250) || \ 2659 (rdev->family == CHIP_RV280) || \ 2660 (rdev->family == CHIP_RS300)) 2661 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2662 (rdev->family == CHIP_RV350) || \ 2663 (rdev->family == CHIP_R350) || \ 2664 (rdev->family == CHIP_RV380) || \ 2665 (rdev->family == CHIP_R420) || \ 2666 (rdev->family == CHIP_R423) || \ 2667 (rdev->family == CHIP_RV410) || \ 2668 (rdev->family == CHIP_RS400) || \ 2669 (rdev->family == CHIP_RS480)) 2670 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2671 (rdev->ddev->pdev->device == 0x9443) || \ 2672 (rdev->ddev->pdev->device == 0x944B) || \ 2673 (rdev->ddev->pdev->device == 0x9506) || \ 2674 (rdev->ddev->pdev->device == 0x9509) || \ 2675 (rdev->ddev->pdev->device == 0x950F) || \ 2676 (rdev->ddev->pdev->device == 0x689C) || \ 2677 (rdev->ddev->pdev->device == 0x689D)) 2678 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2679 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2680 (rdev->family == CHIP_RS690) || \ 2681 (rdev->family == CHIP_RS740) || \ 2682 (rdev->family >= CHIP_R600)) 2683 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2684 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2685 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2686 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2687 (rdev->flags & RADEON_IS_IGP)) 2688 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2689 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2690 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2691 (rdev->flags & RADEON_IS_IGP)) 2692 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2693 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2694 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2695 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2696 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2697 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2698 (rdev->family == CHIP_MULLINS)) 2699 2700 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2701 (rdev->ddev->pdev->device == 0x6850) || \ 2702 (rdev->ddev->pdev->device == 0x6858) || \ 2703 (rdev->ddev->pdev->device == 0x6859) || \ 2704 (rdev->ddev->pdev->device == 0x6840) || \ 2705 (rdev->ddev->pdev->device == 0x6841) || \ 2706 (rdev->ddev->pdev->device == 0x6842) || \ 2707 (rdev->ddev->pdev->device == 0x6843)) 2708 2709 /* 2710 * BIOS helpers. 2711 */ 2712 #define RBIOS8(i) (rdev->bios[i]) 2713 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2714 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2715 2716 int radeon_combios_init(struct radeon_device *rdev); 2717 void radeon_combios_fini(struct radeon_device *rdev); 2718 int radeon_atombios_init(struct radeon_device *rdev); 2719 void radeon_atombios_fini(struct radeon_device *rdev); 2720 2721 2722 /* 2723 * RING helpers. 2724 */ 2725 2726 /** 2727 * radeon_ring_write - write a value to the ring 2728 * 2729 * @ring: radeon_ring structure holding ring information 2730 * @v: dword (dw) value to write 2731 * 2732 * Write a value to the requested ring buffer (all asics). 2733 */ 2734 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2735 { 2736 if (ring->count_dw <= 0) 2737 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2738 2739 ring->ring[ring->wptr++] = v; 2740 ring->wptr &= ring->ptr_mask; 2741 ring->count_dw--; 2742 ring->ring_free_dw--; 2743 } 2744 2745 /* 2746 * ASICs macro. 2747 */ 2748 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2749 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2750 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2751 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2752 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2753 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2754 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2755 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2756 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2757 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2758 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2759 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2760 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2761 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2762 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2763 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2764 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2765 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2766 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2767 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2768 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2769 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2770 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2771 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2772 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2773 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2774 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2775 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2776 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2777 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2778 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2779 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2780 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2781 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2782 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2783 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2784 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2785 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2786 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2787 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2788 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2789 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2790 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2791 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2792 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2793 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2794 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2795 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2796 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2797 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2798 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2799 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2800 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2801 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2802 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2803 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2804 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2805 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2806 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2807 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2808 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2809 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2810 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2811 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2812 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2813 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2814 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2815 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2816 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2817 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2818 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2819 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2820 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2821 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2822 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2823 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2824 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2825 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2826 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2827 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2828 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2829 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2830 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2831 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2832 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2833 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2834 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2835 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2836 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2837 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2838 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2839 2840 /* Common functions */ 2841 /* AGP */ 2842 extern int radeon_gpu_reset(struct radeon_device *rdev); 2843 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2844 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2845 extern void radeon_agp_disable(struct radeon_device *rdev); 2846 extern int radeon_modeset_init(struct radeon_device *rdev); 2847 extern void radeon_modeset_fini(struct radeon_device *rdev); 2848 extern bool radeon_card_posted(struct radeon_device *rdev); 2849 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2850 extern void radeon_update_display_priority(struct radeon_device *rdev); 2851 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2852 extern void radeon_scratch_init(struct radeon_device *rdev); 2853 extern void radeon_wb_fini(struct radeon_device *rdev); 2854 extern int radeon_wb_init(struct radeon_device *rdev); 2855 extern void radeon_wb_disable(struct radeon_device *rdev); 2856 extern void radeon_surface_init(struct radeon_device *rdev); 2857 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2858 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2859 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2860 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2861 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2862 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2863 uint32_t flags); 2864 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2865 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2866 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2867 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2868 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2869 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2870 bool fbcon, bool freeze); 2871 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2872 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2873 const u32 *registers, 2874 const u32 array_size); 2875 2876 /* 2877 * vm 2878 */ 2879 int radeon_vm_manager_init(struct radeon_device *rdev); 2880 void radeon_vm_manager_fini(struct radeon_device *rdev); 2881 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2882 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2883 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2884 struct radeon_vm *vm, 2885 struct list_head *head); 2886 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2887 struct radeon_vm *vm, int ring); 2888 void radeon_vm_flush(struct radeon_device *rdev, 2889 struct radeon_vm *vm, 2890 int ring, struct radeon_fence *fence); 2891 void radeon_vm_fence(struct radeon_device *rdev, 2892 struct radeon_vm *vm, 2893 struct radeon_fence *fence); 2894 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2895 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2896 struct radeon_vm *vm); 2897 int radeon_vm_clear_freed(struct radeon_device *rdev, 2898 struct radeon_vm *vm); 2899 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2900 struct radeon_vm *vm); 2901 int radeon_vm_bo_update(struct radeon_device *rdev, 2902 struct radeon_bo_va *bo_va, 2903 struct ttm_mem_reg *mem); 2904 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2905 struct radeon_bo *bo); 2906 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2907 struct radeon_bo *bo); 2908 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2909 struct radeon_vm *vm, 2910 struct radeon_bo *bo); 2911 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2912 struct radeon_bo_va *bo_va, 2913 uint64_t offset, 2914 uint32_t flags); 2915 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2916 struct radeon_bo_va *bo_va); 2917 2918 /* audio */ 2919 void r600_audio_update_hdmi(struct work_struct *work); 2920 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2921 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2922 void r600_audio_enable(struct radeon_device *rdev, 2923 struct r600_audio_pin *pin, 2924 u8 enable_mask); 2925 void dce6_audio_enable(struct radeon_device *rdev, 2926 struct r600_audio_pin *pin, 2927 u8 enable_mask); 2928 2929 /* 2930 * R600 vram scratch functions 2931 */ 2932 int r600_vram_scratch_init(struct radeon_device *rdev); 2933 void r600_vram_scratch_fini(struct radeon_device *rdev); 2934 2935 /* 2936 * r600 cs checking helper 2937 */ 2938 unsigned r600_mip_minify(unsigned size, unsigned level); 2939 bool r600_fmt_is_valid_color(u32 format); 2940 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2941 int r600_fmt_get_blocksize(u32 format); 2942 int r600_fmt_get_nblocksx(u32 format, u32 w); 2943 int r600_fmt_get_nblocksy(u32 format, u32 h); 2944 2945 /* 2946 * r600 functions used by radeon_encoder.c 2947 */ 2948 struct radeon_hdmi_acr { 2949 u32 clock; 2950 2951 int n_32khz; 2952 int cts_32khz; 2953 2954 int n_44_1khz; 2955 int cts_44_1khz; 2956 2957 int n_48khz; 2958 int cts_48khz; 2959 2960 }; 2961 2962 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2963 2964 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2965 u32 tiling_pipe_num, 2966 u32 max_rb_num, 2967 u32 total_max_rb_num, 2968 u32 enabled_rb_mask); 2969 2970 /* 2971 * evergreen functions used by radeon_encoder.c 2972 */ 2973 2974 extern int ni_init_microcode(struct radeon_device *rdev); 2975 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2976 2977 /* radeon_acpi.c */ 2978 #if defined(CONFIG_ACPI) 2979 extern int radeon_acpi_init(struct radeon_device *rdev); 2980 extern void radeon_acpi_fini(struct radeon_device *rdev); 2981 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2982 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2983 u8 perf_req, bool advertise); 2984 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2985 #else 2986 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2987 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2988 #endif 2989 2990 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2991 struct radeon_cs_packet *pkt, 2992 unsigned idx); 2993 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2994 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2995 struct radeon_cs_packet *pkt); 2996 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2997 struct radeon_bo_list **cs_reloc, 2998 int nomm); 2999 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3000 uint32_t *vline_start_end, 3001 uint32_t *vline_status); 3002 3003 /* interrupt control register helpers */ 3004 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 3005 u32 reg, u32 mask, 3006 bool enable, const char *name, 3007 unsigned n); 3008 3009 #include "radeon_object.h" 3010 3011 #endif 3012