1 /* $OpenBSD: radeon.h,v 1.18 2017/07/01 16:14:10 kettenis Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #ifndef __RADEON_H__ 30 #define __RADEON_H__ 31 32 /* TODO: Here are things that needs to be done : 33 * - surface allocator & initializer : (bit like scratch reg) should 34 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 35 * related to surface 36 * - WB : write back stuff (do it bit like scratch reg things) 37 * - Vblank : look at Jesse's rework and what we should do 38 * - r600/r700: gart & cp 39 * - cs : clean cs ioctl use bitmap & things like that. 40 * - power management stuff 41 * - Barrier in gart code 42 * - Unmappabled vram ? 43 * - TESTING, TESTING, TESTING 44 */ 45 46 /* Initialization path: 47 * We expect that acceleration initialization might fail for various 48 * reasons even thought we work hard to make it works on most 49 * configurations. In order to still have a working userspace in such 50 * situation the init path must succeed up to the memory controller 51 * initialization point. Failure before this point are considered as 52 * fatal error. Here is the init callchain : 53 * radeon_device_init perform common structure, mutex initialization 54 * asic_init setup the GPU memory layout and perform all 55 * one time initialization (failure in this 56 * function are considered fatal) 57 * asic_startup setup the GPU acceleration, in order to 58 * follow guideline the first thing this 59 * function should do is setting the GPU 60 * memory controller (only MC setup failure 61 * are considered as fatal) 62 */ 63 64 #include <dev/pci/drm/ttm/ttm_bo_api.h> 65 #include <dev/pci/drm/ttm/ttm_bo_driver.h> 66 #include <dev/pci/drm/ttm/ttm_placement.h> 67 #include <dev/pci/drm/ttm/ttm_module.h> 68 #include <dev/pci/drm/ttm/ttm_execbuf_util.h> 69 70 #include <dev/wscons/wsconsio.h> 71 #include <dev/wscons/wsdisplayvar.h> 72 #include <dev/rasops/rasops.h> 73 74 #ifdef __sparc64__ 75 #include <machine/fbvar.h> 76 #endif 77 78 #include "radeon_family.h" 79 #include "radeon_mode.h" 80 #include "radeon_reg.h" 81 82 /* 83 * Modules parameters. 84 */ 85 extern int radeon_no_wb; 86 extern int radeon_modeset; 87 extern int radeon_dynclks; 88 extern int radeon_r4xx_atom; 89 extern int radeon_agpmode; 90 extern int radeon_vram_limit; 91 extern int radeon_gart_size; 92 extern int radeon_benchmarking; 93 extern int radeon_testing; 94 extern int radeon_connector_table; 95 extern int radeon_tv; 96 extern int radeon_audio; 97 extern int radeon_disp_priority; 98 extern int radeon_hw_i2c; 99 extern int radeon_pcie_gen2; 100 extern int radeon_msi; 101 extern int radeon_lockup_timeout; 102 extern int radeon_auxch; 103 104 /* 105 * Copy from radeon_drv.h so we don't have to include both and have conflicting 106 * symbol; 107 */ 108 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 109 #define RADEON_FENCE_JIFFIES_TIMEOUT (hz / 2) 110 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 111 #define RADEON_IB_POOL_SIZE 16 112 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 113 #define RADEONFB_CONN_LIMIT 4 114 #define RADEON_BIOS_NUM_SCRATCH 8 115 116 /* max number of rings */ 117 #define RADEON_NUM_RINGS 5 118 119 /* fence seq are set to this number when signaled */ 120 #define RADEON_FENCE_SIGNALED_SEQ 0LL 121 122 /* internal ring indices */ 123 /* r1xx+ has gfx CP ring */ 124 #define RADEON_RING_TYPE_GFX_INDEX 0 125 126 /* cayman has 2 compute CP rings */ 127 #define CAYMAN_RING_TYPE_CP1_INDEX 1 128 #define CAYMAN_RING_TYPE_CP2_INDEX 2 129 130 /* R600+ has an async dma ring */ 131 #define R600_RING_TYPE_DMA_INDEX 3 132 /* cayman add a second async dma ring */ 133 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 134 135 /* hardcode those limit for now */ 136 #define RADEON_VA_IB_OFFSET (1 << 20) 137 #define RADEON_VA_RESERVED_SIZE (8 << 20) 138 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 139 140 /* reset flags */ 141 #define RADEON_RESET_GFX (1 << 0) 142 #define RADEON_RESET_COMPUTE (1 << 1) 143 #define RADEON_RESET_DMA (1 << 2) 144 145 /* 146 * Errata workarounds. 147 */ 148 enum radeon_pll_errata { 149 CHIP_ERRATA_R300_CG = 0x00000001, 150 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 151 CHIP_ERRATA_PLL_DELAY = 0x00000004 152 }; 153 154 155 struct radeon_device; 156 157 158 /* 159 * BIOS. 160 */ 161 bool radeon_get_bios(struct radeon_device *rdev); 162 163 /* 164 * Dummy page 165 */ 166 struct radeon_dummy_page { 167 struct drm_dmamem *dmah; 168 bus_addr_t addr; 169 }; 170 int radeon_dummy_page_init(struct radeon_device *rdev); 171 void radeon_dummy_page_fini(struct radeon_device *rdev); 172 173 174 /* 175 * Clocks 176 */ 177 struct radeon_clock { 178 struct radeon_pll p1pll; 179 struct radeon_pll p2pll; 180 struct radeon_pll dcpll; 181 struct radeon_pll spll; 182 struct radeon_pll mpll; 183 /* 10 Khz units */ 184 uint32_t default_mclk; 185 uint32_t default_sclk; 186 uint32_t default_dispclk; 187 uint32_t dp_extclk; 188 uint32_t max_pixel_clock; 189 }; 190 191 /* 192 * Power management 193 */ 194 int radeon_pm_init(struct radeon_device *rdev); 195 void radeon_pm_fini(struct radeon_device *rdev); 196 void radeon_pm_compute_clocks(struct radeon_device *rdev); 197 void radeon_pm_suspend(struct radeon_device *rdev); 198 void radeon_pm_resume(struct radeon_device *rdev); 199 void radeon_combios_get_power_modes(struct radeon_device *rdev); 200 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 201 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 202 void rs690_pm_info(struct radeon_device *rdev); 203 extern int rv6xx_get_temp(struct radeon_device *rdev); 204 extern int rv770_get_temp(struct radeon_device *rdev); 205 extern int evergreen_get_temp(struct radeon_device *rdev); 206 extern int sumo_get_temp(struct radeon_device *rdev); 207 extern int si_get_temp(struct radeon_device *rdev); 208 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 209 unsigned *bankh, unsigned *mtaspect, 210 unsigned *tile_split); 211 212 /* 213 * Fences. 214 */ 215 struct radeon_fence_driver { 216 uint32_t scratch_reg; 217 uint64_t gpu_addr; 218 volatile uint32_t *cpu_addr; 219 /* sync_seq is protected by ring emission lock */ 220 uint64_t sync_seq[RADEON_NUM_RINGS]; 221 atomic64_t last_seq; 222 unsigned long last_activity; 223 bool initialized; 224 }; 225 226 struct radeon_fence { 227 struct radeon_device *rdev; 228 struct kref kref; 229 /* protected by radeon_fence.lock */ 230 uint64_t seq; 231 /* RB, DMA, etc. */ 232 unsigned ring; 233 }; 234 235 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 236 int radeon_fence_driver_init(struct radeon_device *rdev); 237 void radeon_fence_driver_fini(struct radeon_device *rdev); 238 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 239 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 240 void radeon_fence_process(struct radeon_device *rdev, int ring); 241 bool radeon_fence_signaled(struct radeon_fence *fence); 242 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 243 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 244 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 245 int radeon_fence_wait_any(struct radeon_device *rdev, 246 struct radeon_fence **fences, 247 bool intr); 248 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 249 void radeon_fence_unref(struct radeon_fence **fence); 250 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 251 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 252 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 253 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 254 struct radeon_fence *b) 255 { 256 if (!a) { 257 return b; 258 } 259 260 if (!b) { 261 return a; 262 } 263 264 BUG_ON(a->ring != b->ring); 265 266 if (a->seq > b->seq) { 267 return a; 268 } else { 269 return b; 270 } 271 } 272 273 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 274 struct radeon_fence *b) 275 { 276 if (!a) { 277 return false; 278 } 279 280 if (!b) { 281 return true; 282 } 283 284 BUG_ON(a->ring != b->ring); 285 286 return a->seq < b->seq; 287 } 288 289 /* 290 * Tiling registers 291 */ 292 struct radeon_surface_reg { 293 struct radeon_bo *bo; 294 }; 295 296 #define RADEON_GEM_MAX_SURFACES 8 297 298 /* 299 * TTM. 300 */ 301 struct radeon_mman { 302 struct ttm_bo_global_ref bo_global_ref; 303 struct drm_global_reference mem_global_ref; 304 struct ttm_bo_device bdev; 305 bool mem_global_referenced; 306 bool initialized; 307 }; 308 309 /* bo virtual address in a specific vm */ 310 struct radeon_bo_va { 311 /* protected by bo being reserved */ 312 struct list_head bo_list; 313 uint64_t soffset; 314 uint64_t eoffset; 315 uint32_t flags; 316 bool valid; 317 unsigned ref_count; 318 319 /* protected by vm rwlock */ 320 struct list_head vm_list; 321 322 /* constant after initialization */ 323 struct radeon_vm *vm; 324 struct radeon_bo *bo; 325 }; 326 327 struct radeon_bo { 328 struct drm_gem_object gem_base; 329 /* Protected by gem.rwlock */ 330 struct list_head list; 331 /* Protected by tbo.reserved */ 332 u32 placements[3]; 333 struct ttm_placement placement; 334 struct ttm_buffer_object tbo; 335 struct ttm_bo_kmap_obj kmap; 336 unsigned pin_count; 337 void *kptr; 338 u32 tiling_flags; 339 u32 pitch; 340 int surface_reg; 341 /* list of all virtual address to which this bo 342 * is associated to 343 */ 344 struct list_head va; 345 /* Constant after initialization */ 346 struct radeon_device *rdev; 347 348 struct ttm_bo_kmap_obj dma_buf_vmap; 349 int vmapping_count; 350 }; 351 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 352 353 struct radeon_bo_list { 354 struct ttm_validate_buffer tv; 355 struct radeon_bo *bo; 356 uint64_t gpu_offset; 357 unsigned rdomain; 358 unsigned wdomain; 359 u32 tiling_flags; 360 }; 361 362 /* sub-allocation manager, it has to be protected by another lock. 363 * By conception this is an helper for other part of the driver 364 * like the indirect buffer or semaphore, which both have their 365 * locking. 366 * 367 * Principe is simple, we keep a list of sub allocation in offset 368 * order (first entry has offset == 0, last entry has the highest 369 * offset). 370 * 371 * When allocating new object we first check if there is room at 372 * the end total_size - (last_object_offset + last_object_size) >= 373 * alloc_size. If so we allocate new object there. 374 * 375 * When there is not enough room at the end, we start waiting for 376 * each sub object until we reach object_offset+object_size >= 377 * alloc_size, this object then become the sub object we return. 378 * 379 * Alignment can't be bigger than page size. 380 * 381 * Hole are not considered for allocation to keep things simple. 382 * Assumption is that there won't be hole (all object on same 383 * alignment). 384 */ 385 struct radeon_sa_manager { 386 wait_queue_head_t wq; 387 struct radeon_bo *bo; 388 struct list_head *hole; 389 struct list_head flist[RADEON_NUM_RINGS]; 390 struct list_head olist; 391 unsigned size; 392 uint64_t gpu_addr; 393 void *cpu_ptr; 394 uint32_t domain; 395 uint32_t align; 396 }; 397 398 struct radeon_sa_bo; 399 400 /* sub-allocation buffer */ 401 struct radeon_sa_bo { 402 struct list_head olist; 403 struct list_head flist; 404 struct radeon_sa_manager *manager; 405 unsigned soffset; 406 unsigned eoffset; 407 struct radeon_fence *fence; 408 }; 409 410 /* 411 * GEM objects. 412 */ 413 struct radeon_gem { 414 struct rwlock mutex; 415 struct list_head objects; 416 }; 417 418 int radeon_gem_init(struct radeon_device *rdev); 419 void radeon_gem_fini(struct radeon_device *rdev); 420 int radeon_gem_object_create(struct radeon_device *rdev, int size, 421 int alignment, int initial_domain, 422 bool discardable, bool kernel, 423 struct drm_gem_object **obj); 424 425 int radeon_mode_dumb_create(struct drm_file *file_priv, 426 struct drm_device *dev, 427 struct drm_mode_create_dumb *args); 428 int radeon_mode_dumb_mmap(struct drm_file *filp, 429 struct drm_device *dev, 430 uint32_t handle, uint64_t *offset_p); 431 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 432 struct drm_device *dev, 433 uint32_t handle); 434 435 /* 436 * Semaphores. 437 */ 438 /* everything here is constant */ 439 struct radeon_semaphore { 440 struct radeon_sa_bo *sa_bo; 441 signed waiters; 442 uint64_t gpu_addr; 443 }; 444 445 int radeon_semaphore_create(struct radeon_device *rdev, 446 struct radeon_semaphore **semaphore); 447 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 448 struct radeon_semaphore *semaphore); 449 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 450 struct radeon_semaphore *semaphore); 451 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 452 struct radeon_semaphore *semaphore, 453 int signaler, int waiter); 454 void radeon_semaphore_free(struct radeon_device *rdev, 455 struct radeon_semaphore **semaphore, 456 struct radeon_fence *fence); 457 458 /* 459 * GART structures, functions & helpers 460 */ 461 struct radeon_mc; 462 463 #define RADEON_GPU_PAGE_SIZE 4096 464 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 465 #define RADEON_GPU_PAGE_SHIFT 12 466 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 467 468 struct radeon_gart { 469 bus_addr_t table_addr; 470 struct drm_dmamem *dmah; 471 struct radeon_bo *robj; 472 void *ptr; 473 unsigned num_gpu_pages; 474 unsigned num_cpu_pages; 475 unsigned table_size; 476 struct vm_page **pages; 477 bus_addr_t *pages_addr; 478 bool ready; 479 }; 480 481 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 482 void radeon_gart_table_ram_free(struct radeon_device *rdev); 483 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 484 void radeon_gart_table_vram_free(struct radeon_device *rdev); 485 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 486 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 487 int radeon_gart_init(struct radeon_device *rdev); 488 void radeon_gart_fini(struct radeon_device *rdev); 489 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 490 int pages); 491 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 492 int pages, struct vm_page **pagelist, 493 bus_addr_t *dma_addr); 494 void radeon_gart_restore(struct radeon_device *rdev); 495 496 497 /* 498 * GPU MC structures, functions & helpers 499 */ 500 struct radeon_mc { 501 bus_size_t aper_size; 502 bus_addr_t aper_base; 503 bus_addr_t agp_base; 504 /* for some chips with <= 32MB we need to lie 505 * about vram size near mc fb location */ 506 u64 mc_vram_size; 507 u64 visible_vram_size; 508 u64 gtt_size; 509 u64 gtt_start; 510 u64 gtt_end; 511 u64 vram_start; 512 u64 vram_end; 513 unsigned vram_width; 514 u64 real_vram_size; 515 int vram_mtrr; 516 bool vram_is_ddr; 517 bool igp_sideport_enabled; 518 u64 gtt_base_align; 519 }; 520 521 bool radeon_combios_sideport_present(struct radeon_device *rdev); 522 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 523 524 /* 525 * GPU scratch registers structures, functions & helpers 526 */ 527 struct radeon_scratch { 528 unsigned num_reg; 529 uint32_t reg_base; 530 bool free[32]; 531 uint32_t reg[32]; 532 }; 533 534 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 535 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 536 537 538 /* 539 * IRQS. 540 */ 541 542 struct radeon_unpin_work { 543 struct task task; 544 struct radeon_device *rdev; 545 int crtc_id; 546 struct radeon_fence *fence; 547 struct drm_pending_vblank_event *event; 548 struct radeon_bo *old_rbo; 549 u64 new_crtc_base; 550 }; 551 552 struct r500_irq_stat_regs { 553 u32 disp_int; 554 u32 hdmi0_status; 555 }; 556 557 struct r600_irq_stat_regs { 558 u32 disp_int; 559 u32 disp_int_cont; 560 u32 disp_int_cont2; 561 u32 d1grph_int; 562 u32 d2grph_int; 563 u32 hdmi0_status; 564 u32 hdmi1_status; 565 }; 566 567 struct evergreen_irq_stat_regs { 568 u32 disp_int; 569 u32 disp_int_cont; 570 u32 disp_int_cont2; 571 u32 disp_int_cont3; 572 u32 disp_int_cont4; 573 u32 disp_int_cont5; 574 u32 d1grph_int; 575 u32 d2grph_int; 576 u32 d3grph_int; 577 u32 d4grph_int; 578 u32 d5grph_int; 579 u32 d6grph_int; 580 u32 afmt_status1; 581 u32 afmt_status2; 582 u32 afmt_status3; 583 u32 afmt_status4; 584 u32 afmt_status5; 585 u32 afmt_status6; 586 }; 587 588 union radeon_irq_stat_regs { 589 struct r500_irq_stat_regs r500; 590 struct r600_irq_stat_regs r600; 591 struct evergreen_irq_stat_regs evergreen; 592 }; 593 594 #define RADEON_MAX_HPD_PINS 6 595 #define RADEON_MAX_CRTCS 6 596 #define RADEON_MAX_AFMT_BLOCKS 6 597 598 struct radeon_irq { 599 bool installed; 600 spinlock_t lock; 601 atomic_t ring_int[RADEON_NUM_RINGS]; 602 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 603 atomic_t pflip[RADEON_MAX_CRTCS]; 604 wait_queue_head_t vblank_queue; 605 bool hpd[RADEON_MAX_HPD_PINS]; 606 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 607 union radeon_irq_stat_regs stat_regs; 608 }; 609 610 int radeon_irq_kms_init(struct radeon_device *rdev); 611 void radeon_irq_kms_fini(struct radeon_device *rdev); 612 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 613 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 614 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 615 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 616 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 617 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 618 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 619 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 620 bool radeon_msi_ok(struct radeon_device *rdev); 621 622 /* 623 * CP & rings. 624 */ 625 626 struct radeon_ib { 627 struct radeon_sa_bo *sa_bo; 628 uint32_t length_dw; 629 uint64_t gpu_addr; 630 uint32_t *ptr; 631 int ring; 632 struct radeon_fence *fence; 633 struct radeon_vm *vm; 634 bool is_const_ib; 635 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 636 struct radeon_semaphore *semaphore; 637 }; 638 639 struct radeon_ring { 640 struct radeon_bo *ring_obj; 641 volatile uint32_t *ring; 642 unsigned rptr; 643 unsigned rptr_offs; 644 unsigned rptr_reg; 645 unsigned rptr_save_reg; 646 u64 next_rptr_gpu_addr; 647 volatile u32 *next_rptr_cpu_addr; 648 unsigned wptr; 649 unsigned wptr_old; 650 unsigned wptr_reg; 651 unsigned ring_size; 652 unsigned ring_free_dw; 653 int count_dw; 654 unsigned long last_activity; 655 unsigned last_rptr; 656 uint64_t gpu_addr; 657 uint32_t align_mask; 658 uint32_t ptr_mask; 659 bool ready; 660 u32 ptr_reg_shift; 661 u32 ptr_reg_mask; 662 u32 nop; 663 u32 idx; 664 u64 last_semaphore_signal_addr; 665 u64 last_semaphore_wait_addr; 666 }; 667 668 /* 669 * VM 670 */ 671 672 /* maximum number of VMIDs */ 673 #define RADEON_NUM_VM 16 674 675 /* defines number of bits in page table versus page directory, 676 * a page is 4KB so we have 12 bits offset, 9 bits in the page 677 * table and the remaining 19 bits are in the page directory */ 678 #define RADEON_VM_BLOCK_SIZE 9 679 680 /* number of entries in page table */ 681 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 682 683 struct radeon_vm { 684 struct list_head list; 685 struct list_head va; 686 unsigned id; 687 688 /* contains the page directory */ 689 struct radeon_sa_bo *page_directory; 690 uint64_t pd_gpu_addr; 691 692 /* array of page tables, one for each page directory entry */ 693 struct radeon_sa_bo **page_tables; 694 695 struct rwlock mutex; 696 /* last fence for cs using this vm */ 697 struct radeon_fence *fence; 698 /* last flush or NULL if we still need to flush */ 699 struct radeon_fence *last_flush; 700 }; 701 702 struct radeon_vm_manager { 703 struct rwlock lock; 704 struct list_head lru_vm; 705 struct radeon_fence *active[RADEON_NUM_VM]; 706 struct radeon_sa_manager sa_manager; 707 uint32_t max_pfn; 708 /* number of VMIDs */ 709 unsigned nvm; 710 /* vram base address for page table entry */ 711 u64 vram_base_offset; 712 /* is vm enabled? */ 713 bool enabled; 714 }; 715 716 /* 717 * file private structure 718 */ 719 struct radeon_fpriv { 720 struct radeon_vm vm; 721 }; 722 723 /* 724 * R6xx+ IH ring 725 */ 726 struct r600_ih { 727 struct radeon_bo *ring_obj; 728 volatile uint32_t *ring; 729 unsigned rptr; 730 unsigned ring_size; 731 uint64_t gpu_addr; 732 uint32_t ptr_mask; 733 atomic_t lock; 734 bool enabled; 735 }; 736 737 struct r600_blit_cp_primitives { 738 void (*set_render_target)(struct radeon_device *rdev, int format, 739 int w, int h, u64 gpu_addr); 740 void (*cp_set_surface_sync)(struct radeon_device *rdev, 741 u32 sync_type, u32 size, 742 u64 mc_addr); 743 void (*set_shaders)(struct radeon_device *rdev); 744 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 745 void (*set_tex_resource)(struct radeon_device *rdev, 746 int format, int w, int h, int pitch, 747 u64 gpu_addr, u32 size); 748 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 749 int x2, int y2); 750 void (*draw_auto)(struct radeon_device *rdev); 751 void (*set_default_state)(struct radeon_device *rdev); 752 }; 753 754 struct r600_blit { 755 struct radeon_bo *shader_obj; 756 struct r600_blit_cp_primitives primitives; 757 int max_dim; 758 int ring_size_common; 759 int ring_size_per_loop; 760 u64 shader_gpu_addr; 761 u32 vs_offset, ps_offset; 762 u32 state_offset; 763 u32 state_len; 764 }; 765 766 /* 767 * SI RLC stuff 768 */ 769 struct si_rlc { 770 /* for power gating */ 771 struct radeon_bo *save_restore_obj; 772 uint64_t save_restore_gpu_addr; 773 /* for clear state */ 774 struct radeon_bo *clear_state_obj; 775 uint64_t clear_state_gpu_addr; 776 }; 777 778 int radeon_ib_get(struct radeon_device *rdev, int ring, 779 struct radeon_ib *ib, struct radeon_vm *vm, 780 unsigned size); 781 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 782 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 783 struct radeon_ib *const_ib); 784 int radeon_ib_pool_init(struct radeon_device *rdev); 785 void radeon_ib_pool_fini(struct radeon_device *rdev); 786 int radeon_ib_ring_tests(struct radeon_device *rdev); 787 /* Ring access between begin & end cannot sleep */ 788 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 789 struct radeon_ring *ring); 790 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 791 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 792 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 793 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 794 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 795 void radeon_ring_undo(struct radeon_ring *ring); 796 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 797 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 798 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 799 void radeon_ring_lockup_update(struct radeon_ring *ring); 800 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 801 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 802 uint32_t **data); 803 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 804 unsigned size, uint32_t *data); 805 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 806 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 807 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 808 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 809 810 811 /* r600 async dma */ 812 void r600_dma_stop(struct radeon_device *rdev); 813 int r600_dma_resume(struct radeon_device *rdev); 814 void r600_dma_fini(struct radeon_device *rdev); 815 816 void cayman_dma_stop(struct radeon_device *rdev); 817 int cayman_dma_resume(struct radeon_device *rdev); 818 void cayman_dma_fini(struct radeon_device *rdev); 819 820 /* 821 * CS. 822 */ 823 struct radeon_cs_reloc { 824 struct drm_gem_object *gobj; 825 struct radeon_bo *robj; 826 struct radeon_bo_list lobj; 827 uint32_t handle; 828 uint32_t flags; 829 }; 830 831 struct radeon_cs_chunk { 832 uint32_t chunk_id; 833 uint32_t length_dw; 834 int kpage_idx[2]; 835 uint32_t *kpage[2]; 836 uint32_t *kdata; 837 void __user *user_ptr; 838 int last_copied_page; 839 int last_page_index; 840 }; 841 842 struct radeon_cs_parser { 843 struct device *dev; 844 struct radeon_device *rdev; 845 struct drm_file *filp; 846 /* chunks */ 847 unsigned nchunks; 848 struct radeon_cs_chunk *chunks; 849 uint64_t *chunks_array; 850 /* IB */ 851 unsigned idx; 852 /* relocations */ 853 unsigned nrelocs; 854 struct radeon_cs_reloc *relocs; 855 struct radeon_cs_reloc **relocs_ptr; 856 struct list_head validated; 857 unsigned dma_reloc_idx; 858 /* indices of various chunks */ 859 int chunk_ib_idx; 860 int chunk_relocs_idx; 861 int chunk_flags_idx; 862 int chunk_const_ib_idx; 863 struct radeon_ib ib; 864 struct radeon_ib const_ib; 865 void *track; 866 unsigned family; 867 int parser_error; 868 u32 cs_flags; 869 u32 ring; 870 s32 priority; 871 }; 872 873 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 874 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 875 876 struct radeon_cs_packet { 877 unsigned idx; 878 unsigned type; 879 unsigned reg; 880 unsigned opcode; 881 int count; 882 unsigned one_reg_wr; 883 }; 884 885 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 886 struct radeon_cs_packet *pkt, 887 unsigned idx, unsigned reg); 888 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 889 struct radeon_cs_packet *pkt); 890 891 892 /* 893 * AGP 894 */ 895 int radeon_agp_init(struct radeon_device *rdev); 896 void radeon_agp_resume(struct radeon_device *rdev); 897 void radeon_agp_suspend(struct radeon_device *rdev); 898 void radeon_agp_fini(struct radeon_device *rdev); 899 900 901 /* 902 * Writeback 903 */ 904 struct radeon_wb { 905 struct radeon_bo *wb_obj; 906 volatile uint32_t *wb; 907 uint64_t gpu_addr; 908 bool enabled; 909 bool use_event; 910 }; 911 912 #define RADEON_WB_SCRATCH_OFFSET 0 913 #define RADEON_WB_RING0_NEXT_RPTR 256 914 #define RADEON_WB_CP_RPTR_OFFSET 1024 915 #define RADEON_WB_CP1_RPTR_OFFSET 1280 916 #define RADEON_WB_CP2_RPTR_OFFSET 1536 917 #define R600_WB_DMA_RPTR_OFFSET 1792 918 #define R600_WB_IH_WPTR_OFFSET 2048 919 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 920 #define R600_WB_EVENT_OFFSET 3072 921 922 /** 923 * struct radeon_pm - power management datas 924 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 925 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 926 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 927 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 928 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 929 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 930 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 931 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 932 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 933 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 934 * @needed_bandwidth: current bandwidth needs 935 * 936 * It keeps track of various data needed to take powermanagement decision. 937 * Bandwidth need is used to determine minimun clock of the GPU and memory. 938 * Equation between gpu/memory clock and available bandwidth is hw dependent 939 * (type of memory, bus size, efficiency, ...) 940 */ 941 942 enum radeon_pm_method { 943 PM_METHOD_PROFILE, 944 PM_METHOD_DYNPM, 945 }; 946 947 enum radeon_dynpm_state { 948 DYNPM_STATE_DISABLED, 949 DYNPM_STATE_MINIMUM, 950 DYNPM_STATE_PAUSED, 951 DYNPM_STATE_ACTIVE, 952 DYNPM_STATE_SUSPENDED, 953 }; 954 enum radeon_dynpm_action { 955 DYNPM_ACTION_NONE, 956 DYNPM_ACTION_MINIMUM, 957 DYNPM_ACTION_DOWNCLOCK, 958 DYNPM_ACTION_UPCLOCK, 959 DYNPM_ACTION_DEFAULT 960 }; 961 962 enum radeon_voltage_type { 963 VOLTAGE_NONE = 0, 964 VOLTAGE_GPIO, 965 VOLTAGE_VDDC, 966 VOLTAGE_SW 967 }; 968 969 enum radeon_pm_state_type { 970 POWER_STATE_TYPE_DEFAULT, 971 POWER_STATE_TYPE_POWERSAVE, 972 POWER_STATE_TYPE_BATTERY, 973 POWER_STATE_TYPE_BALANCED, 974 POWER_STATE_TYPE_PERFORMANCE, 975 }; 976 977 enum radeon_pm_profile_type { 978 PM_PROFILE_DEFAULT, 979 PM_PROFILE_AUTO, 980 PM_PROFILE_LOW, 981 PM_PROFILE_MID, 982 PM_PROFILE_HIGH, 983 }; 984 985 #define PM_PROFILE_DEFAULT_IDX 0 986 #define PM_PROFILE_LOW_SH_IDX 1 987 #define PM_PROFILE_MID_SH_IDX 2 988 #define PM_PROFILE_HIGH_SH_IDX 3 989 #define PM_PROFILE_LOW_MH_IDX 4 990 #define PM_PROFILE_MID_MH_IDX 5 991 #define PM_PROFILE_HIGH_MH_IDX 6 992 #define PM_PROFILE_MAX 7 993 994 struct radeon_pm_profile { 995 int dpms_off_ps_idx; 996 int dpms_on_ps_idx; 997 int dpms_off_cm_idx; 998 int dpms_on_cm_idx; 999 }; 1000 1001 enum radeon_int_thermal_type { 1002 THERMAL_TYPE_NONE, 1003 THERMAL_TYPE_RV6XX, 1004 THERMAL_TYPE_RV770, 1005 THERMAL_TYPE_EVERGREEN, 1006 THERMAL_TYPE_SUMO, 1007 THERMAL_TYPE_NI, 1008 THERMAL_TYPE_SI, 1009 }; 1010 1011 struct radeon_voltage { 1012 enum radeon_voltage_type type; 1013 /* gpio voltage */ 1014 struct radeon_gpio_rec gpio; 1015 u32 delay; /* delay in usec from voltage drop to sclk change */ 1016 bool active_high; /* voltage drop is active when bit is high */ 1017 /* VDDC voltage */ 1018 u8 vddc_id; /* index into vddc voltage table */ 1019 u8 vddci_id; /* index into vddci voltage table */ 1020 bool vddci_enabled; 1021 /* r6xx+ sw */ 1022 u16 voltage; 1023 /* evergreen+ vddci */ 1024 u16 vddci; 1025 }; 1026 1027 /* clock mode flags */ 1028 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1029 1030 struct radeon_pm_clock_info { 1031 /* memory clock */ 1032 u32 mclk; 1033 /* engine clock */ 1034 u32 sclk; 1035 /* voltage info */ 1036 struct radeon_voltage voltage; 1037 /* standardized clock flags */ 1038 u32 flags; 1039 }; 1040 1041 /* state flags */ 1042 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1043 1044 struct radeon_power_state { 1045 enum radeon_pm_state_type type; 1046 struct radeon_pm_clock_info *clock_info; 1047 /* number of valid clock modes in this power state */ 1048 int num_clock_modes; 1049 struct radeon_pm_clock_info *default_clock_mode; 1050 /* standardized state flags */ 1051 u32 flags; 1052 u32 misc; /* vbios specific flags */ 1053 u32 misc2; /* vbios specific flags */ 1054 int pcie_lanes; /* pcie lanes */ 1055 }; 1056 1057 /* 1058 * Some modes are overclocked by very low value, accept them 1059 */ 1060 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1061 1062 struct radeon_pm { 1063 struct rwlock mutex; 1064 /* write locked while reprogramming mclk */ 1065 struct rwlock mclk_lock; 1066 u32 active_crtcs; 1067 int active_crtc_count; 1068 int req_vblank; 1069 bool vblank_sync; 1070 fixed20_12 max_bandwidth; 1071 fixed20_12 igp_sideport_mclk; 1072 fixed20_12 igp_system_mclk; 1073 fixed20_12 igp_ht_link_clk; 1074 fixed20_12 igp_ht_link_width; 1075 fixed20_12 k8_bandwidth; 1076 fixed20_12 sideport_bandwidth; 1077 fixed20_12 ht_bandwidth; 1078 fixed20_12 core_bandwidth; 1079 fixed20_12 sclk; 1080 fixed20_12 mclk; 1081 fixed20_12 needed_bandwidth; 1082 struct radeon_power_state *power_state; 1083 /* number of valid power states */ 1084 int num_power_states; 1085 int current_power_state_index; 1086 int current_clock_mode_index; 1087 int requested_power_state_index; 1088 int requested_clock_mode_index; 1089 int default_power_state_index; 1090 u32 current_sclk; 1091 u32 current_mclk; 1092 u16 current_vddc; 1093 u16 current_vddci; 1094 u32 default_sclk; 1095 u32 default_mclk; 1096 u16 default_vddc; 1097 u16 default_vddci; 1098 struct radeon_i2c_chan *i2c_bus; 1099 /* selected pm method */ 1100 enum radeon_pm_method pm_method; 1101 /* dynpm power management */ 1102 struct delayed_work dynpm_idle_work; 1103 enum radeon_dynpm_state dynpm_state; 1104 enum radeon_dynpm_action dynpm_planned_action; 1105 unsigned long dynpm_action_timeout; 1106 bool dynpm_can_upclock; 1107 bool dynpm_can_downclock; 1108 /* profile-based power management */ 1109 enum radeon_pm_profile_type profile; 1110 int profile_index; 1111 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1112 /* internal thermal controller on rv6xx+ */ 1113 enum radeon_int_thermal_type int_thermal_type; 1114 struct device *int_hwmon_dev; 1115 }; 1116 1117 int radeon_pm_get_type_index(struct radeon_device *rdev, 1118 enum radeon_pm_state_type ps_type, 1119 int instance); 1120 1121 struct r600_audio { 1122 int channels; 1123 int rate; 1124 int bits_per_sample; 1125 u8 status_bits; 1126 u8 category_code; 1127 }; 1128 1129 /* 1130 * Benchmarking 1131 */ 1132 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1133 1134 1135 /* 1136 * Testing 1137 */ 1138 void radeon_test_moves(struct radeon_device *rdev); 1139 void radeon_test_ring_sync(struct radeon_device *rdev, 1140 struct radeon_ring *cpA, 1141 struct radeon_ring *cpB); 1142 void radeon_test_syncing(struct radeon_device *rdev); 1143 1144 1145 /* 1146 * Debugfs 1147 */ 1148 struct radeon_debugfs { 1149 struct drm_info_list *files; 1150 unsigned num_files; 1151 }; 1152 1153 int radeon_debugfs_add_files(struct radeon_device *rdev, 1154 struct drm_info_list *files, 1155 unsigned nfiles); 1156 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1157 1158 1159 /* 1160 * ASIC specific functions. 1161 */ 1162 struct radeon_asic { 1163 int (*init)(struct radeon_device *rdev); 1164 void (*fini)(struct radeon_device *rdev); 1165 int (*resume)(struct radeon_device *rdev); 1166 int (*suspend)(struct radeon_device *rdev); 1167 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1168 int (*asic_reset)(struct radeon_device *rdev); 1169 /* ioctl hw specific callback. Some hw might want to perform special 1170 * operation on specific ioctl. For instance on wait idle some hw 1171 * might want to perform and HDP flush through MMIO as it seems that 1172 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1173 * through ring. 1174 */ 1175 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1176 /* check if 3D engine is idle */ 1177 bool (*gui_idle)(struct radeon_device *rdev); 1178 /* wait for mc_idle */ 1179 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1180 /* gart */ 1181 struct { 1182 void (*tlb_flush)(struct radeon_device *rdev); 1183 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1184 } gart; 1185 struct { 1186 int (*init)(struct radeon_device *rdev); 1187 void (*fini)(struct radeon_device *rdev); 1188 1189 u32 pt_ring_index; 1190 void (*set_page)(struct radeon_device *rdev, uint64_t pe, 1191 uint64_t addr, unsigned count, 1192 uint32_t incr, uint32_t flags); 1193 } vm; 1194 /* ring specific callbacks */ 1195 struct { 1196 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1197 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1198 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1199 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1200 struct radeon_semaphore *semaphore, bool emit_wait); 1201 int (*cs_parse)(struct radeon_cs_parser *p); 1202 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1203 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1204 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1205 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1206 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1207 } ring[RADEON_NUM_RINGS]; 1208 /* irqs */ 1209 struct { 1210 int (*set)(struct radeon_device *rdev); 1211 int (*process)(struct radeon_device *rdev); 1212 } irq; 1213 /* displays */ 1214 struct { 1215 /* display watermarks */ 1216 void (*bandwidth_update)(struct radeon_device *rdev); 1217 /* get frame count */ 1218 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1219 /* wait for vblank */ 1220 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1221 /* set backlight level */ 1222 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1223 /* get backlight level */ 1224 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1225 } display; 1226 /* copy functions for bo handling */ 1227 struct { 1228 int (*blit)(struct radeon_device *rdev, 1229 uint64_t src_offset, 1230 uint64_t dst_offset, 1231 unsigned num_gpu_pages, 1232 struct radeon_fence **fence); 1233 u32 blit_ring_index; 1234 int (*dma)(struct radeon_device *rdev, 1235 uint64_t src_offset, 1236 uint64_t dst_offset, 1237 unsigned num_gpu_pages, 1238 struct radeon_fence **fence); 1239 u32 dma_ring_index; 1240 /* method used for bo copy */ 1241 int (*copy)(struct radeon_device *rdev, 1242 uint64_t src_offset, 1243 uint64_t dst_offset, 1244 unsigned num_gpu_pages, 1245 struct radeon_fence **fence); 1246 /* ring used for bo copies */ 1247 u32 copy_ring_index; 1248 } copy; 1249 /* surfaces */ 1250 struct { 1251 int (*set_reg)(struct radeon_device *rdev, int reg, 1252 uint32_t tiling_flags, uint32_t pitch, 1253 uint32_t offset, uint32_t obj_size); 1254 void (*clear_reg)(struct radeon_device *rdev, int reg); 1255 } surface; 1256 /* hotplug detect */ 1257 struct { 1258 void (*init)(struct radeon_device *rdev); 1259 void (*fini)(struct radeon_device *rdev); 1260 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1261 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1262 } hpd; 1263 /* power management */ 1264 struct { 1265 void (*misc)(struct radeon_device *rdev); 1266 void (*prepare)(struct radeon_device *rdev); 1267 void (*finish)(struct radeon_device *rdev); 1268 void (*init_profile)(struct radeon_device *rdev); 1269 void (*get_dynpm_state)(struct radeon_device *rdev); 1270 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1271 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1272 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1273 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1274 int (*get_pcie_lanes)(struct radeon_device *rdev); 1275 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1276 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1277 } pm; 1278 /* pageflipping */ 1279 struct { 1280 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1281 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1282 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1283 } pflip; 1284 }; 1285 1286 /* 1287 * Asic structures 1288 */ 1289 struct r100_asic { 1290 const unsigned *reg_safe_bm; 1291 unsigned reg_safe_bm_size; 1292 u32 hdp_cntl; 1293 }; 1294 1295 struct r300_asic { 1296 const unsigned *reg_safe_bm; 1297 unsigned reg_safe_bm_size; 1298 u32 resync_scratch; 1299 u32 hdp_cntl; 1300 }; 1301 1302 struct r600_asic { 1303 unsigned max_pipes; 1304 unsigned max_tile_pipes; 1305 unsigned max_simds; 1306 unsigned max_backends; 1307 unsigned max_gprs; 1308 unsigned max_threads; 1309 unsigned max_stack_entries; 1310 unsigned max_hw_contexts; 1311 unsigned max_gs_threads; 1312 unsigned sx_max_export_size; 1313 unsigned sx_max_export_pos_size; 1314 unsigned sx_max_export_smx_size; 1315 unsigned sq_num_cf_insts; 1316 unsigned tiling_nbanks; 1317 unsigned tiling_npipes; 1318 unsigned tiling_group_size; 1319 unsigned tile_config; 1320 unsigned backend_map; 1321 }; 1322 1323 struct rv770_asic { 1324 unsigned max_pipes; 1325 unsigned max_tile_pipes; 1326 unsigned max_simds; 1327 unsigned max_backends; 1328 unsigned max_gprs; 1329 unsigned max_threads; 1330 unsigned max_stack_entries; 1331 unsigned max_hw_contexts; 1332 unsigned max_gs_threads; 1333 unsigned sx_max_export_size; 1334 unsigned sx_max_export_pos_size; 1335 unsigned sx_max_export_smx_size; 1336 unsigned sq_num_cf_insts; 1337 unsigned sx_num_of_sets; 1338 unsigned sc_prim_fifo_size; 1339 unsigned sc_hiz_tile_fifo_size; 1340 unsigned sc_earlyz_tile_fifo_fize; 1341 unsigned tiling_nbanks; 1342 unsigned tiling_npipes; 1343 unsigned tiling_group_size; 1344 unsigned tile_config; 1345 unsigned backend_map; 1346 }; 1347 1348 struct evergreen_asic { 1349 unsigned num_ses; 1350 unsigned max_pipes; 1351 unsigned max_tile_pipes; 1352 unsigned max_simds; 1353 unsigned max_backends; 1354 unsigned max_gprs; 1355 unsigned max_threads; 1356 unsigned max_stack_entries; 1357 unsigned max_hw_contexts; 1358 unsigned max_gs_threads; 1359 unsigned sx_max_export_size; 1360 unsigned sx_max_export_pos_size; 1361 unsigned sx_max_export_smx_size; 1362 unsigned sq_num_cf_insts; 1363 unsigned sx_num_of_sets; 1364 unsigned sc_prim_fifo_size; 1365 unsigned sc_hiz_tile_fifo_size; 1366 unsigned sc_earlyz_tile_fifo_size; 1367 unsigned tiling_nbanks; 1368 unsigned tiling_npipes; 1369 unsigned tiling_group_size; 1370 unsigned tile_config; 1371 unsigned backend_map; 1372 }; 1373 1374 struct cayman_asic { 1375 unsigned max_shader_engines; 1376 unsigned max_pipes_per_simd; 1377 unsigned max_tile_pipes; 1378 unsigned max_simds_per_se; 1379 unsigned max_backends_per_se; 1380 unsigned max_texture_channel_caches; 1381 unsigned max_gprs; 1382 unsigned max_threads; 1383 unsigned max_gs_threads; 1384 unsigned max_stack_entries; 1385 unsigned sx_num_of_sets; 1386 unsigned sx_max_export_size; 1387 unsigned sx_max_export_pos_size; 1388 unsigned sx_max_export_smx_size; 1389 unsigned max_hw_contexts; 1390 unsigned sq_num_cf_insts; 1391 unsigned sc_prim_fifo_size; 1392 unsigned sc_hiz_tile_fifo_size; 1393 unsigned sc_earlyz_tile_fifo_size; 1394 1395 unsigned num_shader_engines; 1396 unsigned num_shader_pipes_per_simd; 1397 unsigned num_tile_pipes; 1398 unsigned num_simds_per_se; 1399 unsigned num_backends_per_se; 1400 unsigned backend_disable_mask_per_asic; 1401 unsigned backend_map; 1402 unsigned num_texture_channel_caches; 1403 unsigned mem_max_burst_length_bytes; 1404 unsigned mem_row_size_in_kb; 1405 unsigned shader_engine_tile_size; 1406 unsigned num_gpus; 1407 unsigned multi_gpu_tile_size; 1408 1409 unsigned tile_config; 1410 }; 1411 1412 struct si_asic { 1413 unsigned max_shader_engines; 1414 unsigned max_tile_pipes; 1415 unsigned max_cu_per_sh; 1416 unsigned max_sh_per_se; 1417 unsigned max_backends_per_se; 1418 unsigned max_texture_channel_caches; 1419 unsigned max_gprs; 1420 unsigned max_gs_threads; 1421 unsigned max_hw_contexts; 1422 unsigned sc_prim_fifo_size_frontend; 1423 unsigned sc_prim_fifo_size_backend; 1424 unsigned sc_hiz_tile_fifo_size; 1425 unsigned sc_earlyz_tile_fifo_size; 1426 1427 unsigned num_tile_pipes; 1428 unsigned backend_enable_mask; 1429 unsigned backend_disable_mask_per_asic; 1430 unsigned backend_map; 1431 unsigned num_texture_channel_caches; 1432 unsigned mem_max_burst_length_bytes; 1433 unsigned mem_row_size_in_kb; 1434 unsigned shader_engine_tile_size; 1435 unsigned num_gpus; 1436 unsigned multi_gpu_tile_size; 1437 1438 unsigned tile_config; 1439 }; 1440 1441 union radeon_asic_config { 1442 struct r300_asic r300; 1443 struct r100_asic r100; 1444 struct r600_asic r600; 1445 struct rv770_asic rv770; 1446 struct evergreen_asic evergreen; 1447 struct cayman_asic cayman; 1448 struct si_asic si; 1449 }; 1450 1451 /* 1452 * asic initizalization from radeon_asic.c 1453 */ 1454 void radeon_agp_disable(struct radeon_device *rdev); 1455 int radeon_asic_init(struct radeon_device *rdev); 1456 1457 1458 /* 1459 * IOCTL. 1460 */ 1461 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1462 struct drm_file *filp); 1463 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1464 struct drm_file *filp); 1465 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1466 struct drm_file *file_priv); 1467 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1468 struct drm_file *file_priv); 1469 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1470 struct drm_file *file_priv); 1471 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1472 struct drm_file *file_priv); 1473 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1474 struct drm_file *filp); 1475 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1476 struct drm_file *filp); 1477 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1478 struct drm_file *filp); 1479 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1480 struct drm_file *filp); 1481 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1482 struct drm_file *filp); 1483 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1484 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1485 struct drm_file *filp); 1486 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1487 struct drm_file *filp); 1488 1489 /* VRAM scratch page for HDP bug, default vram page */ 1490 struct r600_vram_scratch { 1491 struct radeon_bo *robj; 1492 volatile uint32_t *ptr; 1493 u64 gpu_addr; 1494 }; 1495 1496 /* 1497 * ACPI 1498 */ 1499 struct radeon_atif_notification_cfg { 1500 bool enabled; 1501 int command_code; 1502 }; 1503 1504 struct radeon_atif_notifications { 1505 bool display_switch; 1506 bool expansion_mode_change; 1507 bool thermal_state; 1508 bool forced_power_state; 1509 bool system_power_state; 1510 bool display_conf_change; 1511 bool px_gfx_switch; 1512 bool brightness_change; 1513 bool dgpu_display_event; 1514 }; 1515 1516 struct radeon_atif_functions { 1517 bool system_params; 1518 bool sbios_requests; 1519 bool select_active_disp; 1520 bool lid_state; 1521 bool get_tv_standard; 1522 bool set_tv_standard; 1523 bool get_panel_expansion_mode; 1524 bool set_panel_expansion_mode; 1525 bool temperature_change; 1526 bool graphics_device_types; 1527 }; 1528 1529 struct radeon_atif { 1530 struct radeon_atif_notifications notifications; 1531 struct radeon_atif_functions functions; 1532 struct radeon_atif_notification_cfg notification_cfg; 1533 struct radeon_encoder *encoder_for_bl; 1534 }; 1535 1536 struct radeon_atcs_functions { 1537 bool get_ext_state; 1538 bool pcie_perf_req; 1539 bool pcie_dev_rdy; 1540 bool pcie_bus_width; 1541 }; 1542 1543 struct radeon_atcs { 1544 struct radeon_atcs_functions functions; 1545 }; 1546 1547 /* 1548 * Core structure, functions and helpers. 1549 */ 1550 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1551 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1552 1553 struct radeon_device { 1554 struct device dev; 1555 struct drm_device *ddev; 1556 struct pci_dev *pdev; 1557 1558 pci_chipset_tag_t pc; 1559 pcitag_t pa_tag; 1560 pci_intr_handle_t intrh; 1561 bus_space_tag_t iot; 1562 bus_space_tag_t memt; 1563 bus_dma_tag_t dmat; 1564 void *irqh; 1565 1566 void (*switchcb)(void *, int, int); 1567 void *switchcbarg; 1568 void *switchcookie; 1569 struct task switchtask; 1570 struct rasops_info ro; 1571 int console; 1572 1573 struct task burner_task; 1574 int burner_fblank; 1575 1576 #ifdef __sparc64__ 1577 struct sunfb sf; 1578 bus_size_t fb_offset; 1579 bus_space_handle_t memh; 1580 #endif 1581 1582 struct rwlock exclusive_lock; 1583 1584 unsigned long fb_aper_offset; 1585 unsigned long fb_aper_size; 1586 1587 /* ASIC */ 1588 union radeon_asic_config config; 1589 enum radeon_family family; 1590 unsigned long flags; 1591 int usec_timeout; 1592 enum radeon_pll_errata pll_errata; 1593 int num_gb_pipes; 1594 int num_z_pipes; 1595 int disp_priority; 1596 /* BIOS */ 1597 uint8_t *bios; 1598 bool is_atom_bios; 1599 uint16_t bios_header_start; 1600 struct radeon_bo *stollen_vga_memory; 1601 /* Register mmio */ 1602 bus_addr_t rmmio_base; 1603 bus_size_t rmmio_size; 1604 /* protects concurrent MM_INDEX/DATA based register access */ 1605 spinlock_t mmio_idx_lock; 1606 bus_space_handle_t rmmio; 1607 radeon_rreg_t mc_rreg; 1608 radeon_wreg_t mc_wreg; 1609 radeon_rreg_t pll_rreg; 1610 radeon_wreg_t pll_wreg; 1611 uint32_t pcie_reg_mask; 1612 radeon_rreg_t pciep_rreg; 1613 radeon_wreg_t pciep_wreg; 1614 /* io port */ 1615 bus_space_handle_t rio_mem; 1616 bus_size_t rio_mem_size; 1617 struct radeon_clock clock; 1618 struct radeon_mc mc; 1619 struct radeon_gart gart; 1620 struct radeon_mode_info mode_info; 1621 struct radeon_scratch scratch; 1622 struct radeon_mman mman; 1623 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1624 wait_queue_head_t fence_queue; 1625 struct rwlock ring_lock; 1626 struct radeon_ring ring[RADEON_NUM_RINGS]; 1627 bool ib_pool_ready; 1628 struct radeon_sa_manager ring_tmp_bo; 1629 struct radeon_irq irq; 1630 struct radeon_asic *asic; 1631 struct radeon_gem gem; 1632 struct radeon_pm pm; 1633 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1634 struct radeon_wb wb; 1635 struct radeon_dummy_page dummy_page; 1636 bool shutdown; 1637 bool suspend; 1638 bool need_dma32; 1639 bool accel_working; 1640 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1641 u_char *me_fw; /* all family ME firmware */ 1642 size_t me_fw_size; 1643 u_char *pfp_fw; /* r6/700 PFP firmware */ 1644 size_t pfp_fw_size; 1645 u_char *rlc_fw; /* r6/700 RLC firmware */ 1646 size_t rlc_fw_size; 1647 u_char *mc_fw; /* NI MC firmware */ 1648 size_t mc_fw_size; 1649 u_char *ce_fw; /* SI CE firmware */ 1650 size_t ce_fw_size; 1651 struct r600_blit r600_blit; 1652 struct r600_vram_scratch vram_scratch; 1653 int msi_enabled; /* msi enabled */ 1654 struct r600_ih ih; /* r6/700 interrupt ring */ 1655 struct si_rlc rlc; 1656 struct task hotplug_task; 1657 struct task audio_task; 1658 int num_crtc; /* number of crtcs */ 1659 struct rwlock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1660 bool audio_enabled; 1661 struct r600_audio audio_status; /* audio stuff */ 1662 #ifdef notyet 1663 struct notifier_block acpi_nb; 1664 #endif 1665 /* only one userspace can use Hyperz features or CMASK at a time */ 1666 struct drm_file *hyperz_filp; 1667 struct drm_file *cmask_filp; 1668 /* i2c buses */ 1669 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1670 /* debugfs */ 1671 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1672 unsigned debugfs_count; 1673 /* virtual memory */ 1674 struct radeon_vm_manager vm_manager; 1675 struct rwlock gpu_clock_mutex; 1676 /* ACPI interface */ 1677 struct radeon_atif atif; 1678 struct radeon_atcs atcs; 1679 }; 1680 1681 int radeon_device_init(struct radeon_device *rdev, 1682 struct drm_device *ddev); 1683 void radeon_device_fini(struct radeon_device *rdev); 1684 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1685 1686 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 1687 bool always_indirect); 1688 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 1689 bool always_indirect); 1690 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1691 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1692 1693 /* 1694 * Cast helper 1695 */ 1696 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1697 1698 /* 1699 * Registers read & write functions. 1700 */ 1701 #define RREG8(reg) \ 1702 bus_space_read_1(rdev->memt, rdev->rmmio, (reg)) 1703 #define WREG8(reg, v) \ 1704 bus_space_write_1(rdev->memt, rdev->rmmio, (reg), (v)) 1705 #define RREG16(reg) \ 1706 bus_space_read_2(rdev->memt, rdev->rmmio, (reg)) 1707 #define WREG16(reg, v) \ 1708 bus_space_write_2(rdev->memt, rdev->rmmio, (reg), (v)) 1709 1710 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 1711 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 1712 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 1713 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 1714 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 1715 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1716 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1717 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1718 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1719 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1720 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1721 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1722 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1723 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1724 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1725 #define WREG32_P(reg, val, mask) \ 1726 do { \ 1727 uint32_t tmp_ = RREG32(reg); \ 1728 tmp_ &= (mask); \ 1729 tmp_ |= ((val) & ~(mask)); \ 1730 WREG32(reg, tmp_); \ 1731 } while (0) 1732 #define WREG32_PLL_P(reg, val, mask) \ 1733 do { \ 1734 uint32_t tmp_ = RREG32_PLL(reg); \ 1735 tmp_ &= (mask); \ 1736 tmp_ |= ((val) & ~(mask)); \ 1737 WREG32_PLL(reg, tmp_); \ 1738 } while (0) 1739 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 1740 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1741 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1742 1743 /* 1744 * Indirect registers accessor 1745 */ 1746 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1747 { 1748 uint32_t r; 1749 1750 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1751 r = RREG32(RADEON_PCIE_DATA); 1752 return r; 1753 } 1754 1755 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1756 { 1757 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1758 WREG32(RADEON_PCIE_DATA, (v)); 1759 } 1760 1761 void r100_pll_errata_after_index(struct radeon_device *rdev); 1762 1763 1764 /* 1765 * ASICs helpers. 1766 */ 1767 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 1768 (rdev->pdev->device == 0x5969)) 1769 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1770 (rdev->family == CHIP_RV200) || \ 1771 (rdev->family == CHIP_RS100) || \ 1772 (rdev->family == CHIP_RS200) || \ 1773 (rdev->family == CHIP_RV250) || \ 1774 (rdev->family == CHIP_RV280) || \ 1775 (rdev->family == CHIP_RS300)) 1776 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1777 (rdev->family == CHIP_RV350) || \ 1778 (rdev->family == CHIP_R350) || \ 1779 (rdev->family == CHIP_RV380) || \ 1780 (rdev->family == CHIP_R420) || \ 1781 (rdev->family == CHIP_R423) || \ 1782 (rdev->family == CHIP_RV410) || \ 1783 (rdev->family == CHIP_RS400) || \ 1784 (rdev->family == CHIP_RS480)) 1785 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 1786 (rdev->ddev->pdev->device == 0x9443) || \ 1787 (rdev->ddev->pdev->device == 0x944B) || \ 1788 (rdev->ddev->pdev->device == 0x9506) || \ 1789 (rdev->ddev->pdev->device == 0x9509) || \ 1790 (rdev->ddev->pdev->device == 0x950F) || \ 1791 (rdev->ddev->pdev->device == 0x689C) || \ 1792 (rdev->ddev->pdev->device == 0x689D)) 1793 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1794 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1795 (rdev->family == CHIP_RS690) || \ 1796 (rdev->family == CHIP_RS740) || \ 1797 (rdev->family >= CHIP_R600)) 1798 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1799 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1800 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1801 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1802 (rdev->flags & RADEON_IS_IGP)) 1803 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1804 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1805 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1806 (rdev->flags & RADEON_IS_IGP)) 1807 1808 /* 1809 * BIOS helpers. 1810 */ 1811 #define RBIOS8(i) (rdev->bios[i]) 1812 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1813 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1814 1815 int radeon_combios_init(struct radeon_device *rdev); 1816 void radeon_combios_fini(struct radeon_device *rdev); 1817 int radeon_atombios_init(struct radeon_device *rdev); 1818 void radeon_atombios_fini(struct radeon_device *rdev); 1819 1820 1821 /* 1822 * RING helpers. 1823 */ 1824 #if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 1825 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1826 { 1827 ring->ring[ring->wptr++] = v; 1828 ring->wptr &= ring->ptr_mask; 1829 ring->count_dw--; 1830 ring->ring_free_dw--; 1831 } 1832 #else 1833 /* With debugging this is just too big to inline */ 1834 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1835 #endif 1836 1837 /* 1838 * ASICs macro. 1839 */ 1840 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1841 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1842 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1843 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1844 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1845 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1846 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1847 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1848 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1849 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1850 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1851 #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) 1852 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1853 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1854 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1855 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1856 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1857 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1858 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 1859 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1860 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1861 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1862 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1863 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1864 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1865 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1866 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1867 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1868 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1869 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1870 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1871 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1872 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1873 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1874 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1875 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1876 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1877 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1878 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1879 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1880 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1881 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1882 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1883 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1884 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1885 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1886 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1887 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1888 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1889 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1890 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1891 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1892 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1893 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1894 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1895 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1896 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1897 1898 /* Common functions */ 1899 /* AGP */ 1900 extern int radeon_gpu_reset(struct radeon_device *rdev); 1901 extern void radeon_agp_disable(struct radeon_device *rdev); 1902 extern int radeon_modeset_init(struct radeon_device *rdev); 1903 extern void radeon_modeset_fini(struct radeon_device *rdev); 1904 extern bool radeon_card_posted(struct radeon_device *rdev); 1905 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1906 extern void radeon_update_display_priority(struct radeon_device *rdev); 1907 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1908 extern void radeon_scratch_init(struct radeon_device *rdev); 1909 extern void radeon_wb_fini(struct radeon_device *rdev); 1910 extern int radeon_wb_init(struct radeon_device *rdev); 1911 extern void radeon_wb_disable(struct radeon_device *rdev); 1912 extern void radeon_surface_init(struct radeon_device *rdev); 1913 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1914 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1915 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1916 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1917 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1918 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1919 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1920 extern int radeon_resume_kms(struct drm_device *dev); 1921 extern int radeon_suspend_kms(struct drm_device *dev); 1922 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1923 extern struct uvm_object *radeon_mmap(struct drm_device *, voff_t, vsize_t); 1924 1925 /* 1926 * vm 1927 */ 1928 int radeon_vm_manager_init(struct radeon_device *rdev); 1929 void radeon_vm_manager_fini(struct radeon_device *rdev); 1930 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1931 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1932 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1933 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 1934 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1935 struct radeon_vm *vm, int ring); 1936 void radeon_vm_fence(struct radeon_device *rdev, 1937 struct radeon_vm *vm, 1938 struct radeon_fence *fence); 1939 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 1940 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 1941 struct radeon_vm *vm, 1942 struct radeon_bo *bo, 1943 struct ttm_mem_reg *mem); 1944 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 1945 struct radeon_bo *bo); 1946 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 1947 struct radeon_bo *bo); 1948 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 1949 struct radeon_vm *vm, 1950 struct radeon_bo *bo); 1951 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 1952 struct radeon_bo_va *bo_va, 1953 uint64_t offset, 1954 uint32_t flags); 1955 int radeon_vm_bo_rmv(struct radeon_device *rdev, 1956 struct radeon_bo_va *bo_va); 1957 1958 /* audio */ 1959 void r600_audio_update_hdmi(void *arg1); 1960 1961 /* 1962 * R600 vram scratch functions 1963 */ 1964 int r600_vram_scratch_init(struct radeon_device *rdev); 1965 void r600_vram_scratch_fini(struct radeon_device *rdev); 1966 1967 /* 1968 * r600 cs checking helper 1969 */ 1970 unsigned r600_mip_minify(unsigned size, unsigned level); 1971 bool r600_fmt_is_valid_color(u32 format); 1972 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1973 int r600_fmt_get_blocksize(u32 format); 1974 int r600_fmt_get_nblocksx(u32 format, u32 w); 1975 int r600_fmt_get_nblocksy(u32 format, u32 h); 1976 1977 /* 1978 * r600 functions used by radeon_encoder.c 1979 */ 1980 struct radeon_hdmi_acr { 1981 u32 clock; 1982 1983 int n_32khz; 1984 int cts_32khz; 1985 1986 int n_44_1khz; 1987 int cts_44_1khz; 1988 1989 int n_48khz; 1990 int cts_48khz; 1991 1992 }; 1993 1994 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1995 1996 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1997 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1998 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1999 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2000 u32 tiling_pipe_num, 2001 u32 max_rb_num, 2002 u32 total_max_rb_num, 2003 u32 enabled_rb_mask); 2004 2005 /* 2006 * evergreen functions used by radeon_encoder.c 2007 */ 2008 2009 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 2010 2011 extern int ni_init_microcode(struct radeon_device *rdev); 2012 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2013 2014 /* radeon_acpi.c */ 2015 #if defined(CONFIG_ACPI) 2016 extern int radeon_acpi_init(struct radeon_device *rdev); 2017 extern void radeon_acpi_fini(struct radeon_device *rdev); 2018 #else 2019 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2020 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2021 #endif 2022 2023 #include "radeon_object.h" 2024 2025 #endif 2026