1 /* $OpenBSD: radeon_atombios.c,v 1.7 2015/04/18 14:47:35 jsg Exp $ */ 2 /* 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 #include <dev/pci/drm/drmP.h> 28 #include <dev/pci/drm/radeon_drm.h> 29 #include "radeon.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 34 /* from radeon_encoder.c */ 35 extern uint32_t 36 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 37 uint8_t dac); 38 extern void radeon_link_encoder_connector(struct drm_device *dev); 39 extern void 40 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, 41 uint32_t supported_device, u16 caps); 42 43 /* from radeon_connector.c */ 44 extern void 45 radeon_add_atom_connector(struct drm_device *dev, 46 uint32_t connector_id, 47 uint32_t supported_device, 48 int connector_type, 49 struct radeon_i2c_bus_rec *i2c_bus, 50 uint32_t igp_lane_info, 51 uint16_t connector_object_id, 52 struct radeon_hpd *hpd, 53 struct radeon_router *router); 54 55 /* from radeon_legacy_encoder.c */ 56 extern void 57 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 58 uint32_t supported_device); 59 60 /* local */ 61 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 62 u16 voltage_id, u16 *voltage); 63 64 union atom_supported_devices { 65 struct _ATOM_SUPPORTED_DEVICES_INFO info; 66 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 67 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 68 }; 69 70 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 71 ATOM_GPIO_I2C_ASSIGMENT *gpio, 72 u8 index) 73 { 74 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 75 if ((rdev->family == CHIP_R420) || 76 (rdev->family == CHIP_R423) || 77 (rdev->family == CHIP_RV410)) { 78 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 80 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 81 gpio->ucClkMaskShift = 0x19; 82 gpio->ucDataMaskShift = 0x18; 83 } 84 } 85 86 /* some evergreen boards have bad data for this entry */ 87 if (ASIC_IS_DCE4(rdev)) { 88 if ((index == 7) && 89 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 90 (gpio->sucI2cId.ucAccess == 0)) { 91 gpio->sucI2cId.ucAccess = 0x97; 92 gpio->ucDataMaskShift = 8; 93 gpio->ucDataEnShift = 8; 94 gpio->ucDataY_Shift = 8; 95 gpio->ucDataA_Shift = 8; 96 } 97 } 98 99 /* some DCE3 boards have bad data for this entry */ 100 if (ASIC_IS_DCE3(rdev)) { 101 if ((index == 4) && 102 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 103 (gpio->sucI2cId.ucAccess == 0x94)) 104 gpio->sucI2cId.ucAccess = 0x14; 105 } 106 } 107 108 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 109 { 110 struct radeon_i2c_bus_rec i2c; 111 112 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 113 114 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 115 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 116 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 117 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 118 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 119 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 120 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 121 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 122 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 123 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 124 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 125 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 126 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 127 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 128 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 129 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 130 131 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 132 i2c.hw_capable = true; 133 else 134 i2c.hw_capable = false; 135 136 if (gpio->sucI2cId.ucAccess == 0xa0) 137 i2c.mm_i2c = true; 138 else 139 i2c.mm_i2c = false; 140 141 i2c.i2c_id = gpio->sucI2cId.ucAccess; 142 143 if (i2c.mask_clk_reg) 144 i2c.valid = true; 145 else 146 i2c.valid = false; 147 148 return i2c; 149 } 150 151 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 152 uint8_t id) 153 { 154 struct atom_context *ctx = rdev->mode_info.atom_context; 155 ATOM_GPIO_I2C_ASSIGMENT *gpio; 156 struct radeon_i2c_bus_rec i2c; 157 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 158 struct _ATOM_GPIO_I2C_INFO *i2c_info; 159 uint16_t data_offset, size; 160 int i, num_indices; 161 162 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 163 i2c.valid = false; 164 165 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 166 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 167 168 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 169 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 170 171 for (i = 0; i < num_indices; i++) { 172 gpio = &i2c_info->asGPIO_Info[i]; 173 174 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 175 176 if (gpio->sucI2cId.ucAccess == id) { 177 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 178 break; 179 } 180 } 181 } 182 183 return i2c; 184 } 185 186 void radeon_atombios_i2c_init(struct radeon_device *rdev) 187 { 188 struct atom_context *ctx = rdev->mode_info.atom_context; 189 ATOM_GPIO_I2C_ASSIGMENT *gpio; 190 struct radeon_i2c_bus_rec i2c; 191 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 192 struct _ATOM_GPIO_I2C_INFO *i2c_info; 193 uint16_t data_offset, size; 194 int i, num_indices; 195 char stmp[32]; 196 197 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 198 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 199 200 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 201 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 202 203 for (i = 0; i < num_indices; i++) { 204 gpio = &i2c_info->asGPIO_Info[i]; 205 206 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 207 208 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 209 210 if (i2c.valid) { 211 snprintf(stmp, sizeof(stmp), "0x%x", i2c.i2c_id); 212 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 213 } 214 } 215 } 216 } 217 218 static struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev, 219 u8 id) 220 { 221 struct atom_context *ctx = rdev->mode_info.atom_context; 222 struct radeon_gpio_rec gpio; 223 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 224 struct _ATOM_GPIO_PIN_LUT *gpio_info; 225 ATOM_GPIO_PIN_ASSIGNMENT *pin; 226 u16 data_offset, size; 227 int i, num_indices; 228 229 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 230 gpio.valid = false; 231 232 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 233 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 234 235 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 236 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 237 238 for (i = 0; i < num_indices; i++) { 239 pin = &gpio_info->asGPIO_Pin[i]; 240 if (id == pin->ucGPIO_ID) { 241 gpio.id = pin->ucGPIO_ID; 242 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 243 gpio.mask = (1 << pin->ucGpioPinBitShift); 244 gpio.valid = true; 245 break; 246 } 247 } 248 } 249 250 return gpio; 251 } 252 253 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 254 struct radeon_gpio_rec *gpio) 255 { 256 struct radeon_hpd hpd; 257 u32 reg; 258 259 memset(&hpd, 0, sizeof(struct radeon_hpd)); 260 261 if (ASIC_IS_DCE6(rdev)) 262 reg = SI_DC_GPIO_HPD_A; 263 else if (ASIC_IS_DCE4(rdev)) 264 reg = EVERGREEN_DC_GPIO_HPD_A; 265 else 266 reg = AVIVO_DC_GPIO_HPD_A; 267 268 hpd.gpio = *gpio; 269 if (gpio->reg == reg) { 270 switch(gpio->mask) { 271 case (1 << 0): 272 hpd.hpd = RADEON_HPD_1; 273 break; 274 case (1 << 8): 275 hpd.hpd = RADEON_HPD_2; 276 break; 277 case (1 << 16): 278 hpd.hpd = RADEON_HPD_3; 279 break; 280 case (1 << 24): 281 hpd.hpd = RADEON_HPD_4; 282 break; 283 case (1 << 26): 284 hpd.hpd = RADEON_HPD_5; 285 break; 286 case (1 << 28): 287 hpd.hpd = RADEON_HPD_6; 288 break; 289 default: 290 hpd.hpd = RADEON_HPD_NONE; 291 break; 292 } 293 } else 294 hpd.hpd = RADEON_HPD_NONE; 295 return hpd; 296 } 297 298 static bool radeon_atom_apply_quirks(struct drm_device *dev, 299 uint32_t supported_device, 300 int *connector_type, 301 struct radeon_i2c_bus_rec *i2c_bus, 302 uint16_t *line_mux, 303 struct radeon_hpd *hpd) 304 { 305 306 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 307 if ((dev->pdev->device == 0x791e) && 308 (dev->pdev->subsystem_vendor == 0x1043) && 309 (dev->pdev->subsystem_device == 0x826d)) { 310 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 311 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 312 *connector_type = DRM_MODE_CONNECTOR_DVID; 313 } 314 315 /* Asrock RS600 board lists the DVI port as HDMI */ 316 if ((dev->pdev->device == 0x7941) && 317 (dev->pdev->subsystem_vendor == 0x1849) && 318 (dev->pdev->subsystem_device == 0x7941)) { 319 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 320 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 321 *connector_type = DRM_MODE_CONNECTOR_DVID; 322 } 323 324 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 325 if ((dev->pdev->device == 0x796e) && 326 (dev->pdev->subsystem_vendor == 0x1462) && 327 (dev->pdev->subsystem_device == 0x7302)) { 328 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 329 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 330 return false; 331 } 332 333 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 334 if ((dev->pdev->device == 0x7941) && 335 (dev->pdev->subsystem_vendor == 0x147b) && 336 (dev->pdev->subsystem_device == 0x2412)) { 337 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 338 return false; 339 } 340 341 /* Falcon NW laptop lists vga ddc line for LVDS */ 342 if ((dev->pdev->device == 0x5653) && 343 (dev->pdev->subsystem_vendor == 0x1462) && 344 (dev->pdev->subsystem_device == 0x0291)) { 345 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 346 i2c_bus->valid = false; 347 *line_mux = 53; 348 } 349 } 350 351 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 352 if ((dev->pdev->device == 0x7146) && 353 (dev->pdev->subsystem_vendor == 0x17af) && 354 (dev->pdev->subsystem_device == 0x2058)) { 355 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 356 return false; 357 } 358 359 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 360 if ((dev->pdev->device == 0x7142) && 361 (dev->pdev->subsystem_vendor == 0x1458) && 362 (dev->pdev->subsystem_device == 0x2134)) { 363 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 364 return false; 365 } 366 367 368 /* Funky macbooks */ 369 if ((dev->pdev->device == 0x71C5) && 370 (dev->pdev->subsystem_vendor == 0x106b) && 371 (dev->pdev->subsystem_device == 0x0080)) { 372 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 373 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 374 return false; 375 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 376 *line_mux = 0x90; 377 } 378 379 /* mac rv630, rv730, others */ 380 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 381 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 382 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 383 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 384 } 385 386 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 387 if ((dev->pdev->device == 0x9598) && 388 (dev->pdev->subsystem_vendor == 0x1043) && 389 (dev->pdev->subsystem_device == 0x01da)) { 390 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 391 *connector_type = DRM_MODE_CONNECTOR_DVII; 392 } 393 } 394 395 /* ASUS HD 3600 board lists the DVI port as HDMI */ 396 if ((dev->pdev->device == 0x9598) && 397 (dev->pdev->subsystem_vendor == 0x1043) && 398 (dev->pdev->subsystem_device == 0x01e4)) { 399 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 400 *connector_type = DRM_MODE_CONNECTOR_DVII; 401 } 402 } 403 404 /* ASUS HD 3450 board lists the DVI port as HDMI */ 405 if ((dev->pdev->device == 0x95C5) && 406 (dev->pdev->subsystem_vendor == 0x1043) && 407 (dev->pdev->subsystem_device == 0x01e2)) { 408 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 409 *connector_type = DRM_MODE_CONNECTOR_DVII; 410 } 411 } 412 413 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 414 * HDMI + VGA reporting as HDMI 415 */ 416 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 417 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 418 *connector_type = DRM_MODE_CONNECTOR_VGA; 419 *line_mux = 0; 420 } 421 } 422 423 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 424 * on the laptop and a DVI port on the docking station and 425 * both share the same encoder, hpd pin, and ddc line. 426 * So while the bios table is technically correct, 427 * we drop the DVI port here since xrandr has no concept of 428 * encoders and will try and drive both connectors 429 * with different crtcs which isn't possible on the hardware 430 * side and leaves no crtcs for LVDS or VGA. 431 */ 432 if (((dev->pdev->device == 0x95c4) || (dev->pdev->device == 0x9591)) && 433 (dev->pdev->subsystem_vendor == 0x1025) && 434 (dev->pdev->subsystem_device == 0x013c)) { 435 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 436 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 437 /* actually it's a DVI-D port not DVI-I */ 438 *connector_type = DRM_MODE_CONNECTOR_DVID; 439 return false; 440 } 441 } 442 443 /* XFX Pine Group device rv730 reports no VGA DDC lines 444 * even though they are wired up to record 0x93 445 */ 446 if ((dev->pdev->device == 0x9498) && 447 (dev->pdev->subsystem_vendor == 0x1682) && 448 (dev->pdev->subsystem_device == 0x2452) && 449 (i2c_bus->valid == false) && 450 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 451 struct radeon_device *rdev = dev->dev_private; 452 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 453 } 454 455 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 456 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) && 457 (dev->pdev->subsystem_vendor == 0x1734) && 458 (dev->pdev->subsystem_device == 0x11bd)) { 459 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 460 *connector_type = DRM_MODE_CONNECTOR_DVII; 461 *line_mux = 0x3103; 462 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 463 *connector_type = DRM_MODE_CONNECTOR_DVII; 464 } 465 } 466 467 468 return true; 469 } 470 471 const int supported_devices_connector_convert[] = { 472 DRM_MODE_CONNECTOR_Unknown, 473 DRM_MODE_CONNECTOR_VGA, 474 DRM_MODE_CONNECTOR_DVII, 475 DRM_MODE_CONNECTOR_DVID, 476 DRM_MODE_CONNECTOR_DVIA, 477 DRM_MODE_CONNECTOR_SVIDEO, 478 DRM_MODE_CONNECTOR_Composite, 479 DRM_MODE_CONNECTOR_LVDS, 480 DRM_MODE_CONNECTOR_Unknown, 481 DRM_MODE_CONNECTOR_Unknown, 482 DRM_MODE_CONNECTOR_HDMIA, 483 DRM_MODE_CONNECTOR_HDMIB, 484 DRM_MODE_CONNECTOR_Unknown, 485 DRM_MODE_CONNECTOR_Unknown, 486 DRM_MODE_CONNECTOR_9PinDIN, 487 DRM_MODE_CONNECTOR_DisplayPort 488 }; 489 490 const uint16_t supported_devices_connector_object_id_convert[] = { 491 CONNECTOR_OBJECT_ID_NONE, 492 CONNECTOR_OBJECT_ID_VGA, 493 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 494 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 495 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 496 CONNECTOR_OBJECT_ID_COMPOSITE, 497 CONNECTOR_OBJECT_ID_SVIDEO, 498 CONNECTOR_OBJECT_ID_LVDS, 499 CONNECTOR_OBJECT_ID_9PIN_DIN, 500 CONNECTOR_OBJECT_ID_9PIN_DIN, 501 CONNECTOR_OBJECT_ID_DISPLAYPORT, 502 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 503 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 504 CONNECTOR_OBJECT_ID_SVIDEO 505 }; 506 507 const int object_connector_convert[] = { 508 DRM_MODE_CONNECTOR_Unknown, 509 DRM_MODE_CONNECTOR_DVII, 510 DRM_MODE_CONNECTOR_DVII, 511 DRM_MODE_CONNECTOR_DVID, 512 DRM_MODE_CONNECTOR_DVID, 513 DRM_MODE_CONNECTOR_VGA, 514 DRM_MODE_CONNECTOR_Composite, 515 DRM_MODE_CONNECTOR_SVIDEO, 516 DRM_MODE_CONNECTOR_Unknown, 517 DRM_MODE_CONNECTOR_Unknown, 518 DRM_MODE_CONNECTOR_9PinDIN, 519 DRM_MODE_CONNECTOR_Unknown, 520 DRM_MODE_CONNECTOR_HDMIA, 521 DRM_MODE_CONNECTOR_HDMIB, 522 DRM_MODE_CONNECTOR_LVDS, 523 DRM_MODE_CONNECTOR_9PinDIN, 524 DRM_MODE_CONNECTOR_Unknown, 525 DRM_MODE_CONNECTOR_Unknown, 526 DRM_MODE_CONNECTOR_Unknown, 527 DRM_MODE_CONNECTOR_DisplayPort, 528 DRM_MODE_CONNECTOR_eDP, 529 DRM_MODE_CONNECTOR_Unknown 530 }; 531 532 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 533 { 534 struct radeon_device *rdev = dev->dev_private; 535 struct radeon_mode_info *mode_info = &rdev->mode_info; 536 struct atom_context *ctx = mode_info->atom_context; 537 int index = GetIndexIntoMasterTable(DATA, Object_Header); 538 u16 size, data_offset; 539 u8 frev, crev; 540 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 541 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 542 ATOM_OBJECT_TABLE *router_obj; 543 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 544 ATOM_OBJECT_HEADER *obj_header; 545 int i, j, k, path_size, device_support; 546 int connector_type; 547 u16 igp_lane_info, conn_id, connector_object_id; 548 struct radeon_i2c_bus_rec ddc_bus; 549 struct radeon_router router; 550 struct radeon_gpio_rec gpio; 551 struct radeon_hpd hpd; 552 553 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 554 return false; 555 556 if (crev < 2) 557 return false; 558 559 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 560 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 561 (ctx->bios + data_offset + 562 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 563 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 564 (ctx->bios + data_offset + 565 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 566 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 567 (ctx->bios + data_offset + 568 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 569 router_obj = (ATOM_OBJECT_TABLE *) 570 (ctx->bios + data_offset + 571 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 572 device_support = le16_to_cpu(obj_header->usDeviceSupport); 573 574 path_size = 0; 575 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 576 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 577 ATOM_DISPLAY_OBJECT_PATH *path; 578 addr += path_size; 579 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 580 path_size += le16_to_cpu(path->usSize); 581 582 if (device_support & le16_to_cpu(path->usDeviceTag)) { 583 uint8_t con_obj_id, con_obj_num, con_obj_type; 584 585 con_obj_id = 586 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 587 >> OBJECT_ID_SHIFT; 588 con_obj_num = 589 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 590 >> ENUM_ID_SHIFT; 591 con_obj_type = 592 (le16_to_cpu(path->usConnObjectId) & 593 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 594 595 /* TODO CV support */ 596 if (le16_to_cpu(path->usDeviceTag) == 597 ATOM_DEVICE_CV_SUPPORT) 598 continue; 599 600 /* IGP chips */ 601 if ((rdev->flags & RADEON_IS_IGP) && 602 (con_obj_id == 603 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 604 uint16_t igp_offset = 0; 605 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 606 607 index = 608 GetIndexIntoMasterTable(DATA, 609 IntegratedSystemInfo); 610 611 if (atom_parse_data_header(ctx, index, &size, &frev, 612 &crev, &igp_offset)) { 613 614 if (crev >= 2) { 615 igp_obj = 616 (ATOM_INTEGRATED_SYSTEM_INFO_V2 617 *) (ctx->bios + igp_offset); 618 619 if (igp_obj) { 620 uint32_t slot_config, ct; 621 622 if (con_obj_num == 1) 623 slot_config = 624 igp_obj-> 625 ulDDISlot1Config; 626 else 627 slot_config = 628 igp_obj-> 629 ulDDISlot2Config; 630 631 ct = (slot_config >> 16) & 0xff; 632 connector_type = 633 object_connector_convert 634 [ct]; 635 connector_object_id = ct; 636 igp_lane_info = 637 slot_config & 0xffff; 638 } else 639 continue; 640 } else 641 continue; 642 } else { 643 igp_lane_info = 0; 644 connector_type = 645 object_connector_convert[con_obj_id]; 646 connector_object_id = con_obj_id; 647 } 648 } else { 649 igp_lane_info = 0; 650 connector_type = 651 object_connector_convert[con_obj_id]; 652 connector_object_id = con_obj_id; 653 } 654 655 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 656 continue; 657 658 router.ddc_valid = false; 659 router.cd_valid = false; 660 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 661 uint8_t grph_obj_id, grph_obj_num, grph_obj_type; 662 663 grph_obj_id = 664 (le16_to_cpu(path->usGraphicObjIds[j]) & 665 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 666 grph_obj_num = 667 (le16_to_cpu(path->usGraphicObjIds[j]) & 668 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 669 grph_obj_type = 670 (le16_to_cpu(path->usGraphicObjIds[j]) & 671 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 672 673 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 674 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 675 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 676 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 677 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 678 (ctx->bios + data_offset + 679 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 680 ATOM_ENCODER_CAP_RECORD *cap_record; 681 u16 caps = 0; 682 683 while (record->ucRecordSize > 0 && 684 record->ucRecordType > 0 && 685 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 686 switch (record->ucRecordType) { 687 case ATOM_ENCODER_CAP_RECORD_TYPE: 688 cap_record =(ATOM_ENCODER_CAP_RECORD *) 689 record; 690 caps = le16_to_cpu(cap_record->usEncoderCap); 691 break; 692 } 693 record = (ATOM_COMMON_RECORD_HEADER *) 694 ((char *)record + record->ucRecordSize); 695 } 696 radeon_add_atom_encoder(dev, 697 encoder_obj, 698 le16_to_cpu 699 (path-> 700 usDeviceTag), 701 caps); 702 } 703 } 704 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 705 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 706 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 707 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 708 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 709 (ctx->bios + data_offset + 710 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 711 ATOM_I2C_RECORD *i2c_record; 712 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 713 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 714 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 715 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 716 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 717 (ctx->bios + data_offset + 718 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 719 u8 *num_dst_objs = (u8 *) 720 ((u8 *)router_src_dst_table + 1 + 721 (router_src_dst_table->ucNumberOfSrc * 2)); 722 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 723 int enum_id; 724 725 router.router_id = router_obj_id; 726 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 727 if (le16_to_cpu(path->usConnObjectId) == 728 le16_to_cpu(dst_objs[enum_id])) 729 break; 730 } 731 732 while (record->ucRecordSize > 0 && 733 record->ucRecordType > 0 && 734 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 735 switch (record->ucRecordType) { 736 case ATOM_I2C_RECORD_TYPE: 737 i2c_record = 738 (ATOM_I2C_RECORD *) 739 record; 740 i2c_config = 741 (ATOM_I2C_ID_CONFIG_ACCESS *) 742 &i2c_record->sucI2cId; 743 router.i2c_info = 744 radeon_lookup_i2c_gpio(rdev, 745 i2c_config-> 746 ucAccess); 747 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 748 break; 749 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 750 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 751 record; 752 router.ddc_valid = true; 753 router.ddc_mux_type = ddc_path->ucMuxType; 754 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 755 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 756 break; 757 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 758 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 759 record; 760 router.cd_valid = true; 761 router.cd_mux_type = cd_path->ucMuxType; 762 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 763 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 764 break; 765 } 766 record = (ATOM_COMMON_RECORD_HEADER *) 767 ((char *)record + record->ucRecordSize); 768 } 769 } 770 } 771 } 772 } 773 774 /* look up gpio for ddc, hpd */ 775 ddc_bus.valid = false; 776 hpd.hpd = RADEON_HPD_NONE; 777 if ((le16_to_cpu(path->usDeviceTag) & 778 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 779 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 780 if (le16_to_cpu(path->usConnObjectId) == 781 le16_to_cpu(con_obj->asObjects[j]. 782 usObjectID)) { 783 ATOM_COMMON_RECORD_HEADER 784 *record = 785 (ATOM_COMMON_RECORD_HEADER 786 *) 787 (ctx->bios + data_offset + 788 le16_to_cpu(con_obj-> 789 asObjects[j]. 790 usRecordOffset)); 791 ATOM_I2C_RECORD *i2c_record; 792 ATOM_HPD_INT_RECORD *hpd_record; 793 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 794 795 while (record->ucRecordSize > 0 && 796 record->ucRecordType > 0 && 797 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 798 switch (record->ucRecordType) { 799 case ATOM_I2C_RECORD_TYPE: 800 i2c_record = 801 (ATOM_I2C_RECORD *) 802 record; 803 i2c_config = 804 (ATOM_I2C_ID_CONFIG_ACCESS *) 805 &i2c_record->sucI2cId; 806 ddc_bus = radeon_lookup_i2c_gpio(rdev, 807 i2c_config-> 808 ucAccess); 809 break; 810 case ATOM_HPD_INT_RECORD_TYPE: 811 hpd_record = 812 (ATOM_HPD_INT_RECORD *) 813 record; 814 gpio = radeon_lookup_gpio(rdev, 815 hpd_record->ucHPDIntGPIOID); 816 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 817 hpd.plugged_state = hpd_record->ucPlugged_PinState; 818 break; 819 } 820 record = 821 (ATOM_COMMON_RECORD_HEADER 822 *) ((char *)record 823 + 824 record-> 825 ucRecordSize); 826 } 827 break; 828 } 829 } 830 } 831 832 /* needed for aux chan transactions */ 833 ddc_bus.hpd = hpd.hpd; 834 835 conn_id = le16_to_cpu(path->usConnObjectId); 836 837 if (!radeon_atom_apply_quirks 838 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 839 &ddc_bus, &conn_id, &hpd)) 840 continue; 841 842 radeon_add_atom_connector(dev, 843 conn_id, 844 le16_to_cpu(path-> 845 usDeviceTag), 846 connector_type, &ddc_bus, 847 igp_lane_info, 848 connector_object_id, 849 &hpd, 850 &router); 851 852 } 853 } 854 855 radeon_link_encoder_connector(dev); 856 857 return true; 858 } 859 860 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 861 int connector_type, 862 uint16_t devices) 863 { 864 struct radeon_device *rdev = dev->dev_private; 865 866 if (rdev->flags & RADEON_IS_IGP) { 867 return supported_devices_connector_object_id_convert 868 [connector_type]; 869 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 870 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 871 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 872 struct radeon_mode_info *mode_info = &rdev->mode_info; 873 struct atom_context *ctx = mode_info->atom_context; 874 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 875 uint16_t size, data_offset; 876 uint8_t frev, crev; 877 ATOM_XTMDS_INFO *xtmds; 878 879 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 880 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 881 882 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 883 if (connector_type == DRM_MODE_CONNECTOR_DVII) 884 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 885 else 886 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 887 } else { 888 if (connector_type == DRM_MODE_CONNECTOR_DVII) 889 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 890 else 891 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 892 } 893 } else 894 return supported_devices_connector_object_id_convert 895 [connector_type]; 896 } else { 897 return supported_devices_connector_object_id_convert 898 [connector_type]; 899 } 900 } 901 902 struct bios_connector { 903 bool valid; 904 uint16_t line_mux; 905 uint16_t devices; 906 int connector_type; 907 struct radeon_i2c_bus_rec ddc_bus; 908 struct radeon_hpd hpd; 909 }; 910 911 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 912 drm_device 913 *dev) 914 { 915 struct radeon_device *rdev = dev->dev_private; 916 struct radeon_mode_info *mode_info = &rdev->mode_info; 917 struct atom_context *ctx = mode_info->atom_context; 918 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 919 uint16_t size, data_offset; 920 uint8_t frev, crev; 921 uint16_t device_support; 922 uint8_t dac; 923 union atom_supported_devices *supported_devices; 924 int i, j, max_device; 925 struct bios_connector *bios_connectors; 926 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 927 struct radeon_router router; 928 929 router.ddc_valid = false; 930 router.cd_valid = false; 931 932 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 933 if (!bios_connectors) 934 return false; 935 936 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 937 &data_offset)) { 938 kfree(bios_connectors); 939 return false; 940 } 941 942 supported_devices = 943 (union atom_supported_devices *)(ctx->bios + data_offset); 944 945 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 946 947 if (frev > 1) 948 max_device = ATOM_MAX_SUPPORTED_DEVICE; 949 else 950 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 951 952 for (i = 0; i < max_device; i++) { 953 ATOM_CONNECTOR_INFO_I2C ci = 954 supported_devices->info.asConnInfo[i]; 955 956 bios_connectors[i].valid = false; 957 958 if (!(device_support & (1 << i))) { 959 continue; 960 } 961 962 if (i == ATOM_DEVICE_CV_INDEX) { 963 DRM_DEBUG_KMS("Skipping Component Video\n"); 964 continue; 965 } 966 967 bios_connectors[i].connector_type = 968 supported_devices_connector_convert[ci.sucConnectorInfo. 969 sbfAccess. 970 bfConnectorType]; 971 972 if (bios_connectors[i].connector_type == 973 DRM_MODE_CONNECTOR_Unknown) 974 continue; 975 976 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 977 978 bios_connectors[i].line_mux = 979 ci.sucI2cId.ucAccess; 980 981 /* give tv unique connector ids */ 982 if (i == ATOM_DEVICE_TV1_INDEX) { 983 bios_connectors[i].ddc_bus.valid = false; 984 bios_connectors[i].line_mux = 50; 985 } else if (i == ATOM_DEVICE_TV2_INDEX) { 986 bios_connectors[i].ddc_bus.valid = false; 987 bios_connectors[i].line_mux = 51; 988 } else if (i == ATOM_DEVICE_CV_INDEX) { 989 bios_connectors[i].ddc_bus.valid = false; 990 bios_connectors[i].line_mux = 52; 991 } else 992 bios_connectors[i].ddc_bus = 993 radeon_lookup_i2c_gpio(rdev, 994 bios_connectors[i].line_mux); 995 996 if ((crev > 1) && (frev > 1)) { 997 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 998 switch (isb) { 999 case 0x4: 1000 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 1001 break; 1002 case 0xa: 1003 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 1004 break; 1005 default: 1006 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 1007 break; 1008 } 1009 } else { 1010 if (i == ATOM_DEVICE_DFP1_INDEX) 1011 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 1012 else if (i == ATOM_DEVICE_DFP2_INDEX) 1013 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 1014 else 1015 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 1016 } 1017 1018 /* Always set the connector type to VGA for CRT1/CRT2. if they are 1019 * shared with a DVI port, we'll pick up the DVI connector when we 1020 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 1021 */ 1022 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 1023 bios_connectors[i].connector_type = 1024 DRM_MODE_CONNECTOR_VGA; 1025 1026 if (!radeon_atom_apply_quirks 1027 (dev, (1 << i), &bios_connectors[i].connector_type, 1028 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1029 &bios_connectors[i].hpd)) 1030 continue; 1031 1032 bios_connectors[i].valid = true; 1033 bios_connectors[i].devices = (1 << i); 1034 1035 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1036 radeon_add_atom_encoder(dev, 1037 radeon_get_encoder_enum(dev, 1038 (1 << i), 1039 dac), 1040 (1 << i), 1041 0); 1042 else 1043 radeon_add_legacy_encoder(dev, 1044 radeon_get_encoder_enum(dev, 1045 (1 << i), 1046 dac), 1047 (1 << i)); 1048 } 1049 1050 /* combine shared connectors */ 1051 for (i = 0; i < max_device; i++) { 1052 if (bios_connectors[i].valid) { 1053 for (j = 0; j < max_device; j++) { 1054 if (bios_connectors[j].valid && (i != j)) { 1055 if (bios_connectors[i].line_mux == 1056 bios_connectors[j].line_mux) { 1057 /* make sure not to combine LVDS */ 1058 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1059 bios_connectors[i].line_mux = 53; 1060 bios_connectors[i].ddc_bus.valid = false; 1061 continue; 1062 } 1063 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1064 bios_connectors[j].line_mux = 53; 1065 bios_connectors[j].ddc_bus.valid = false; 1066 continue; 1067 } 1068 /* combine analog and digital for DVI-I */ 1069 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1070 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1071 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1072 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1073 bios_connectors[i].devices |= 1074 bios_connectors[j].devices; 1075 bios_connectors[i].connector_type = 1076 DRM_MODE_CONNECTOR_DVII; 1077 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1078 bios_connectors[i].hpd = 1079 bios_connectors[j].hpd; 1080 bios_connectors[j].valid = false; 1081 } 1082 } 1083 } 1084 } 1085 } 1086 } 1087 1088 /* add the connectors */ 1089 for (i = 0; i < max_device; i++) { 1090 if (bios_connectors[i].valid) { 1091 uint16_t connector_object_id = 1092 atombios_get_connector_object_id(dev, 1093 bios_connectors[i].connector_type, 1094 bios_connectors[i].devices); 1095 radeon_add_atom_connector(dev, 1096 bios_connectors[i].line_mux, 1097 bios_connectors[i].devices, 1098 bios_connectors[i]. 1099 connector_type, 1100 &bios_connectors[i].ddc_bus, 1101 0, 1102 connector_object_id, 1103 &bios_connectors[i].hpd, 1104 &router); 1105 } 1106 } 1107 1108 radeon_link_encoder_connector(dev); 1109 1110 kfree(bios_connectors); 1111 return true; 1112 } 1113 1114 union firmware_info { 1115 ATOM_FIRMWARE_INFO info; 1116 ATOM_FIRMWARE_INFO_V1_2 info_12; 1117 ATOM_FIRMWARE_INFO_V1_3 info_13; 1118 ATOM_FIRMWARE_INFO_V1_4 info_14; 1119 ATOM_FIRMWARE_INFO_V2_1 info_21; 1120 ATOM_FIRMWARE_INFO_V2_2 info_22; 1121 }; 1122 1123 bool radeon_atom_get_clock_info(struct drm_device *dev) 1124 { 1125 struct radeon_device *rdev = dev->dev_private; 1126 struct radeon_mode_info *mode_info = &rdev->mode_info; 1127 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1128 union firmware_info *firmware_info; 1129 uint8_t frev, crev; 1130 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1131 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1132 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1133 struct radeon_pll *spll = &rdev->clock.spll; 1134 struct radeon_pll *mpll = &rdev->clock.mpll; 1135 uint16_t data_offset; 1136 1137 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1138 &frev, &crev, &data_offset)) { 1139 firmware_info = 1140 (union firmware_info *)(mode_info->atom_context->bios + 1141 data_offset); 1142 /* pixel clocks */ 1143 p1pll->reference_freq = 1144 le16_to_cpu(firmware_info->info.usReferenceClock); 1145 p1pll->reference_div = 0; 1146 1147 if (crev < 2) 1148 p1pll->pll_out_min = 1149 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1150 else 1151 p1pll->pll_out_min = 1152 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1153 p1pll->pll_out_max = 1154 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1155 1156 if (crev >= 4) { 1157 p1pll->lcd_pll_out_min = 1158 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1159 if (p1pll->lcd_pll_out_min == 0) 1160 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1161 p1pll->lcd_pll_out_max = 1162 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1163 if (p1pll->lcd_pll_out_max == 0) 1164 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1165 } else { 1166 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1167 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1168 } 1169 1170 if (p1pll->pll_out_min == 0) { 1171 if (ASIC_IS_AVIVO(rdev)) 1172 p1pll->pll_out_min = 64800; 1173 else 1174 p1pll->pll_out_min = 20000; 1175 } 1176 1177 p1pll->pll_in_min = 1178 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1179 p1pll->pll_in_max = 1180 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1181 1182 *p2pll = *p1pll; 1183 1184 /* system clock */ 1185 if (ASIC_IS_DCE4(rdev)) 1186 spll->reference_freq = 1187 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1188 else 1189 spll->reference_freq = 1190 le16_to_cpu(firmware_info->info.usReferenceClock); 1191 spll->reference_div = 0; 1192 1193 spll->pll_out_min = 1194 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1195 spll->pll_out_max = 1196 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1197 1198 /* ??? */ 1199 if (spll->pll_out_min == 0) { 1200 if (ASIC_IS_AVIVO(rdev)) 1201 spll->pll_out_min = 64800; 1202 else 1203 spll->pll_out_min = 20000; 1204 } 1205 1206 spll->pll_in_min = 1207 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1208 spll->pll_in_max = 1209 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1210 1211 /* memory clock */ 1212 if (ASIC_IS_DCE4(rdev)) 1213 mpll->reference_freq = 1214 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1215 else 1216 mpll->reference_freq = 1217 le16_to_cpu(firmware_info->info.usReferenceClock); 1218 mpll->reference_div = 0; 1219 1220 mpll->pll_out_min = 1221 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1222 mpll->pll_out_max = 1223 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1224 1225 /* ??? */ 1226 if (mpll->pll_out_min == 0) { 1227 if (ASIC_IS_AVIVO(rdev)) 1228 mpll->pll_out_min = 64800; 1229 else 1230 mpll->pll_out_min = 20000; 1231 } 1232 1233 mpll->pll_in_min = 1234 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1235 mpll->pll_in_max = 1236 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1237 1238 rdev->clock.default_sclk = 1239 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1240 rdev->clock.default_mclk = 1241 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1242 1243 if (ASIC_IS_DCE4(rdev)) { 1244 rdev->clock.default_dispclk = 1245 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1246 if (rdev->clock.default_dispclk == 0) { 1247 if (ASIC_IS_DCE5(rdev)) 1248 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1249 else 1250 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1251 } 1252 rdev->clock.dp_extclk = 1253 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1254 } 1255 *dcpll = *p1pll; 1256 1257 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1258 if (rdev->clock.max_pixel_clock == 0) 1259 rdev->clock.max_pixel_clock = 40000; 1260 1261 /* not technically a clock, but... */ 1262 rdev->mode_info.firmware_flags = 1263 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1264 1265 return true; 1266 } 1267 1268 return false; 1269 } 1270 1271 union igp_info { 1272 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1273 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1274 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1275 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1276 }; 1277 1278 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1279 { 1280 struct radeon_mode_info *mode_info = &rdev->mode_info; 1281 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1282 union igp_info *igp_info; 1283 u8 frev, crev; 1284 u16 data_offset; 1285 1286 /* sideport is AMD only */ 1287 if (rdev->family == CHIP_RS600) 1288 return false; 1289 1290 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1291 &frev, &crev, &data_offset)) { 1292 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1293 data_offset); 1294 switch (crev) { 1295 case 1: 1296 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1297 return true; 1298 break; 1299 case 2: 1300 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1301 return true; 1302 break; 1303 default: 1304 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1305 break; 1306 } 1307 } 1308 return false; 1309 } 1310 1311 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1312 struct radeon_encoder_int_tmds *tmds) 1313 { 1314 struct drm_device *dev = encoder->base.dev; 1315 struct radeon_device *rdev = dev->dev_private; 1316 struct radeon_mode_info *mode_info = &rdev->mode_info; 1317 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1318 uint16_t data_offset; 1319 struct _ATOM_TMDS_INFO *tmds_info; 1320 uint8_t frev, crev; 1321 uint16_t maxfreq; 1322 int i; 1323 1324 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1325 &frev, &crev, &data_offset)) { 1326 tmds_info = 1327 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1328 data_offset); 1329 1330 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1331 for (i = 0; i < 4; i++) { 1332 tmds->tmds_pll[i].freq = 1333 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1334 tmds->tmds_pll[i].value = 1335 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1336 tmds->tmds_pll[i].value |= 1337 (tmds_info->asMiscInfo[i]. 1338 ucPLL_VCO_Gain & 0x3f) << 6; 1339 tmds->tmds_pll[i].value |= 1340 (tmds_info->asMiscInfo[i]. 1341 ucPLL_DutyCycle & 0xf) << 12; 1342 tmds->tmds_pll[i].value |= 1343 (tmds_info->asMiscInfo[i]. 1344 ucPLL_VoltageSwing & 0xf) << 16; 1345 1346 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1347 tmds->tmds_pll[i].freq, 1348 tmds->tmds_pll[i].value); 1349 1350 if (maxfreq == tmds->tmds_pll[i].freq) { 1351 tmds->tmds_pll[i].freq = 0xffffffff; 1352 break; 1353 } 1354 } 1355 return true; 1356 } 1357 return false; 1358 } 1359 1360 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1361 struct radeon_atom_ss *ss, 1362 int id) 1363 { 1364 struct radeon_mode_info *mode_info = &rdev->mode_info; 1365 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1366 uint16_t data_offset, size; 1367 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1368 uint8_t frev, crev; 1369 int i, num_indices; 1370 1371 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1372 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1373 &frev, &crev, &data_offset)) { 1374 ss_info = 1375 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1376 1377 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1378 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1379 1380 for (i = 0; i < num_indices; i++) { 1381 if (ss_info->asSS_Info[i].ucSS_Id == id) { 1382 ss->percentage = 1383 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage); 1384 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType; 1385 ss->step = ss_info->asSS_Info[i].ucSS_Step; 1386 ss->delay = ss_info->asSS_Info[i].ucSS_Delay; 1387 ss->range = ss_info->asSS_Info[i].ucSS_Range; 1388 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div; 1389 return true; 1390 } 1391 } 1392 } 1393 return false; 1394 } 1395 1396 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1397 struct radeon_atom_ss *ss, 1398 int id) 1399 { 1400 struct radeon_mode_info *mode_info = &rdev->mode_info; 1401 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1402 u16 data_offset, size; 1403 union igp_info *igp_info; 1404 u8 frev, crev; 1405 u16 percentage = 0, rate = 0; 1406 1407 /* get any igp specific overrides */ 1408 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1409 &frev, &crev, &data_offset)) { 1410 igp_info = (union igp_info *) 1411 (mode_info->atom_context->bios + data_offset); 1412 switch (crev) { 1413 case 6: 1414 switch (id) { 1415 case ASIC_INTERNAL_SS_ON_TMDS: 1416 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1417 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1418 break; 1419 case ASIC_INTERNAL_SS_ON_HDMI: 1420 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1421 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1422 break; 1423 case ASIC_INTERNAL_SS_ON_LVDS: 1424 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1425 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1426 break; 1427 } 1428 break; 1429 case 7: 1430 switch (id) { 1431 case ASIC_INTERNAL_SS_ON_TMDS: 1432 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1433 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1434 break; 1435 case ASIC_INTERNAL_SS_ON_HDMI: 1436 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1437 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1438 break; 1439 case ASIC_INTERNAL_SS_ON_LVDS: 1440 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1441 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1442 break; 1443 } 1444 break; 1445 default: 1446 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1447 break; 1448 } 1449 if (percentage) 1450 ss->percentage = percentage; 1451 if (rate) 1452 ss->rate = rate; 1453 } 1454 } 1455 1456 union asic_ss_info { 1457 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1458 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1459 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1460 }; 1461 1462 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1463 struct radeon_atom_ss *ss, 1464 int id, u32 clock) 1465 { 1466 struct radeon_mode_info *mode_info = &rdev->mode_info; 1467 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1468 uint16_t data_offset, size; 1469 union asic_ss_info *ss_info; 1470 uint8_t frev, crev; 1471 int i, num_indices; 1472 1473 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1474 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1475 &frev, &crev, &data_offset)) { 1476 1477 ss_info = 1478 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1479 1480 switch (frev) { 1481 case 1: 1482 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1483 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1484 1485 for (i = 0; i < num_indices; i++) { 1486 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) && 1487 (clock <= le32_to_cpu(ss_info->info.asSpreadSpectrum[i].ulTargetClockRange))) { 1488 ss->percentage = 1489 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1490 ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1491 ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz); 1492 return true; 1493 } 1494 } 1495 break; 1496 case 2: 1497 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1498 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1499 for (i = 0; i < num_indices; i++) { 1500 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) && 1501 (clock <= le32_to_cpu(ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange))) { 1502 ss->percentage = 1503 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1504 ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1505 ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz); 1506 return true; 1507 } 1508 } 1509 break; 1510 case 3: 1511 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1512 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1513 for (i = 0; i < num_indices; i++) { 1514 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) && 1515 (clock <= le32_to_cpu(ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange))) { 1516 ss->percentage = 1517 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage); 1518 ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; 1519 ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz); 1520 if (rdev->flags & RADEON_IS_IGP) 1521 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1522 return true; 1523 } 1524 } 1525 break; 1526 default: 1527 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1528 break; 1529 } 1530 1531 } 1532 return false; 1533 } 1534 1535 union lvds_info { 1536 struct _ATOM_LVDS_INFO info; 1537 struct _ATOM_LVDS_INFO_V12 info_12; 1538 }; 1539 1540 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1541 radeon_encoder 1542 *encoder) 1543 { 1544 struct drm_device *dev = encoder->base.dev; 1545 struct radeon_device *rdev = dev->dev_private; 1546 struct radeon_mode_info *mode_info = &rdev->mode_info; 1547 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1548 uint16_t data_offset, misc; 1549 union lvds_info *lvds_info; 1550 uint8_t frev, crev; 1551 struct radeon_encoder_atom_dig *lvds = NULL; 1552 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1553 1554 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1555 &frev, &crev, &data_offset)) { 1556 lvds_info = 1557 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1558 lvds = 1559 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1560 1561 if (!lvds) 1562 return NULL; 1563 1564 lvds->native_mode.clock = 1565 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1566 lvds->native_mode.hdisplay = 1567 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1568 lvds->native_mode.vdisplay = 1569 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1570 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1571 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1572 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1573 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1574 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1575 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1576 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1577 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1578 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1579 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1580 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1581 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1582 lvds->panel_pwr_delay = 1583 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1584 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1585 1586 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1587 if (misc & ATOM_VSYNC_POLARITY) 1588 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1589 if (misc & ATOM_HSYNC_POLARITY) 1590 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1591 if (misc & ATOM_COMPOSITESYNC) 1592 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1593 if (misc & ATOM_INTERLACE) 1594 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1595 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1596 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1597 1598 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1599 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1600 1601 /* set crtc values */ 1602 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1603 1604 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1605 1606 encoder->native_mode = lvds->native_mode; 1607 1608 if (encoder_enum == 2) 1609 lvds->linkb = true; 1610 else 1611 lvds->linkb = false; 1612 1613 /* parse the lcd record table */ 1614 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1615 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1616 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1617 bool bad_record = false; 1618 u8 *record; 1619 1620 if ((frev == 1) && (crev < 2)) 1621 /* absolute */ 1622 record = (u8 *)(mode_info->atom_context->bios + 1623 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1624 else 1625 /* relative */ 1626 record = (u8 *)(mode_info->atom_context->bios + 1627 data_offset + 1628 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1629 while (*record != ATOM_RECORD_END_TYPE) { 1630 switch (*record) { 1631 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1632 record += sizeof(ATOM_PATCH_RECORD_MODE); 1633 break; 1634 case LCD_RTS_RECORD_TYPE: 1635 record += sizeof(ATOM_LCD_RTS_RECORD); 1636 break; 1637 case LCD_CAP_RECORD_TYPE: 1638 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1639 break; 1640 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1641 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1642 if (fake_edid_record->ucFakeEDIDLength) { 1643 struct edid *edid; 1644 int edid_size = 1645 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1646 edid = kmalloc(edid_size, GFP_KERNEL); 1647 if (edid) { 1648 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1649 fake_edid_record->ucFakeEDIDLength); 1650 1651 if (drm_edid_is_valid(edid)) { 1652 rdev->mode_info.bios_hardcoded_edid = edid; 1653 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1654 } else 1655 kfree(edid); 1656 } 1657 } 1658 record += fake_edid_record->ucFakeEDIDLength ? 1659 fake_edid_record->ucFakeEDIDLength + 2 : 1660 sizeof(ATOM_FAKE_EDID_PATCH_RECORD); 1661 break; 1662 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1663 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1664 lvds->native_mode.width_mm = panel_res_record->usHSize; 1665 lvds->native_mode.height_mm = panel_res_record->usVSize; 1666 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1667 break; 1668 default: 1669 DRM_ERROR("Bad LCD record %d\n", *record); 1670 bad_record = true; 1671 break; 1672 } 1673 if (bad_record) 1674 break; 1675 } 1676 } 1677 } 1678 return lvds; 1679 } 1680 1681 struct radeon_encoder_primary_dac * 1682 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1683 { 1684 struct drm_device *dev = encoder->base.dev; 1685 struct radeon_device *rdev = dev->dev_private; 1686 struct radeon_mode_info *mode_info = &rdev->mode_info; 1687 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1688 uint16_t data_offset; 1689 struct _COMPASSIONATE_DATA *dac_info; 1690 uint8_t frev, crev; 1691 uint8_t bg, dac; 1692 struct radeon_encoder_primary_dac *p_dac = NULL; 1693 1694 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1695 &frev, &crev, &data_offset)) { 1696 dac_info = (struct _COMPASSIONATE_DATA *) 1697 (mode_info->atom_context->bios + data_offset); 1698 1699 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1700 1701 if (!p_dac) 1702 return NULL; 1703 1704 bg = dac_info->ucDAC1_BG_Adjustment; 1705 dac = dac_info->ucDAC1_DAC_Adjustment; 1706 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1707 1708 } 1709 return p_dac; 1710 } 1711 1712 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1713 struct drm_display_mode *mode) 1714 { 1715 struct radeon_mode_info *mode_info = &rdev->mode_info; 1716 ATOM_ANALOG_TV_INFO *tv_info; 1717 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1718 ATOM_DTD_FORMAT *dtd_timings; 1719 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1720 u8 frev, crev; 1721 u16 data_offset, misc; 1722 1723 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1724 &frev, &crev, &data_offset)) 1725 return false; 1726 1727 switch (crev) { 1728 case 1: 1729 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1730 if (index >= MAX_SUPPORTED_TV_TIMING) 1731 return false; 1732 1733 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1734 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1735 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1736 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1737 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1738 1739 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1740 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1741 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1742 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1743 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1744 1745 mode->flags = 0; 1746 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1747 if (misc & ATOM_VSYNC_POLARITY) 1748 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1749 if (misc & ATOM_HSYNC_POLARITY) 1750 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1751 if (misc & ATOM_COMPOSITESYNC) 1752 mode->flags |= DRM_MODE_FLAG_CSYNC; 1753 if (misc & ATOM_INTERLACE) 1754 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1755 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1756 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1757 1758 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1759 1760 if (index == 1) { 1761 /* PAL timings appear to have wrong values for totals */ 1762 mode->crtc_htotal -= 1; 1763 mode->crtc_vtotal -= 1; 1764 } 1765 break; 1766 case 2: 1767 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1768 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1769 return false; 1770 1771 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1772 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1773 le16_to_cpu(dtd_timings->usHBlanking_Time); 1774 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1775 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1776 le16_to_cpu(dtd_timings->usHSyncOffset); 1777 mode->crtc_hsync_end = mode->crtc_hsync_start + 1778 le16_to_cpu(dtd_timings->usHSyncWidth); 1779 1780 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1781 le16_to_cpu(dtd_timings->usVBlanking_Time); 1782 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1783 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1784 le16_to_cpu(dtd_timings->usVSyncOffset); 1785 mode->crtc_vsync_end = mode->crtc_vsync_start + 1786 le16_to_cpu(dtd_timings->usVSyncWidth); 1787 1788 mode->flags = 0; 1789 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1790 if (misc & ATOM_VSYNC_POLARITY) 1791 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1792 if (misc & ATOM_HSYNC_POLARITY) 1793 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1794 if (misc & ATOM_COMPOSITESYNC) 1795 mode->flags |= DRM_MODE_FLAG_CSYNC; 1796 if (misc & ATOM_INTERLACE) 1797 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1798 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1799 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1800 1801 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10; 1802 break; 1803 } 1804 return true; 1805 } 1806 1807 enum radeon_tv_std 1808 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1809 { 1810 struct radeon_mode_info *mode_info = &rdev->mode_info; 1811 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1812 uint16_t data_offset; 1813 uint8_t frev, crev; 1814 struct _ATOM_ANALOG_TV_INFO *tv_info; 1815 enum radeon_tv_std tv_std = TV_STD_NTSC; 1816 1817 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1818 &frev, &crev, &data_offset)) { 1819 1820 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1821 (mode_info->atom_context->bios + data_offset); 1822 1823 switch (tv_info->ucTV_BootUpDefaultStandard) { 1824 case ATOM_TV_NTSC: 1825 tv_std = TV_STD_NTSC; 1826 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1827 break; 1828 case ATOM_TV_NTSCJ: 1829 tv_std = TV_STD_NTSC_J; 1830 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1831 break; 1832 case ATOM_TV_PAL: 1833 tv_std = TV_STD_PAL; 1834 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1835 break; 1836 case ATOM_TV_PALM: 1837 tv_std = TV_STD_PAL_M; 1838 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1839 break; 1840 case ATOM_TV_PALN: 1841 tv_std = TV_STD_PAL_N; 1842 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1843 break; 1844 case ATOM_TV_PALCN: 1845 tv_std = TV_STD_PAL_CN; 1846 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1847 break; 1848 case ATOM_TV_PAL60: 1849 tv_std = TV_STD_PAL_60; 1850 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1851 break; 1852 case ATOM_TV_SECAM: 1853 tv_std = TV_STD_SECAM; 1854 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1855 break; 1856 default: 1857 tv_std = TV_STD_NTSC; 1858 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1859 break; 1860 } 1861 } 1862 return tv_std; 1863 } 1864 1865 struct radeon_encoder_tv_dac * 1866 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1867 { 1868 struct drm_device *dev = encoder->base.dev; 1869 struct radeon_device *rdev = dev->dev_private; 1870 struct radeon_mode_info *mode_info = &rdev->mode_info; 1871 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1872 uint16_t data_offset; 1873 struct _COMPASSIONATE_DATA *dac_info; 1874 uint8_t frev, crev; 1875 uint8_t bg, dac; 1876 struct radeon_encoder_tv_dac *tv_dac = NULL; 1877 1878 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1879 &frev, &crev, &data_offset)) { 1880 1881 dac_info = (struct _COMPASSIONATE_DATA *) 1882 (mode_info->atom_context->bios + data_offset); 1883 1884 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1885 1886 if (!tv_dac) 1887 return NULL; 1888 1889 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1890 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1891 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1892 1893 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1894 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1895 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1896 1897 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1898 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1899 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1900 1901 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1902 } 1903 return tv_dac; 1904 } 1905 1906 static const char *thermal_controller_names[] = { 1907 "NONE", 1908 "lm63", 1909 "adm1032", 1910 "adm1030", 1911 "max6649", 1912 "lm64", 1913 "f75375", 1914 "asc7xxx", 1915 }; 1916 1917 static const char *pp_lib_thermal_controller_names[] = { 1918 "NONE", 1919 "lm63", 1920 "adm1032", 1921 "adm1030", 1922 "max6649", 1923 "lm64", 1924 "f75375", 1925 "RV6xx", 1926 "RV770", 1927 "adt7473", 1928 "NONE", 1929 "External GPIO", 1930 "Evergreen", 1931 "emc2103", 1932 "Sumo", 1933 "Northern Islands", 1934 "Southern Islands", 1935 "lm96163", 1936 }; 1937 1938 union power_info { 1939 struct _ATOM_POWERPLAY_INFO info; 1940 struct _ATOM_POWERPLAY_INFO_V2 info_2; 1941 struct _ATOM_POWERPLAY_INFO_V3 info_3; 1942 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 1943 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 1944 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 1945 }; 1946 1947 union pplib_clock_info { 1948 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 1949 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 1950 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 1951 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 1952 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 1953 }; 1954 1955 union pplib_power_state { 1956 struct _ATOM_PPLIB_STATE v1; 1957 struct _ATOM_PPLIB_STATE_V2 v2; 1958 }; 1959 1960 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 1961 int state_index, 1962 u32 misc, u32 misc2) 1963 { 1964 rdev->pm.power_state[state_index].misc = misc; 1965 rdev->pm.power_state[state_index].misc2 = misc2; 1966 /* order matters! */ 1967 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 1968 rdev->pm.power_state[state_index].type = 1969 POWER_STATE_TYPE_POWERSAVE; 1970 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 1971 rdev->pm.power_state[state_index].type = 1972 POWER_STATE_TYPE_BATTERY; 1973 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 1974 rdev->pm.power_state[state_index].type = 1975 POWER_STATE_TYPE_BATTERY; 1976 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 1977 rdev->pm.power_state[state_index].type = 1978 POWER_STATE_TYPE_BALANCED; 1979 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 1980 rdev->pm.power_state[state_index].type = 1981 POWER_STATE_TYPE_PERFORMANCE; 1982 rdev->pm.power_state[state_index].flags &= 1983 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 1984 } 1985 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 1986 rdev->pm.power_state[state_index].type = 1987 POWER_STATE_TYPE_BALANCED; 1988 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 1989 rdev->pm.power_state[state_index].type = 1990 POWER_STATE_TYPE_DEFAULT; 1991 rdev->pm.default_power_state_index = state_index; 1992 rdev->pm.power_state[state_index].default_clock_mode = 1993 &rdev->pm.power_state[state_index].clock_info[0]; 1994 } else if (state_index == 0) { 1995 rdev->pm.power_state[state_index].clock_info[0].flags |= 1996 RADEON_PM_MODE_NO_DISPLAY; 1997 } 1998 } 1999 2000 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2001 { 2002 struct radeon_mode_info *mode_info = &rdev->mode_info; 2003 u32 misc, misc2 = 0; 2004 int num_modes = 0, i; 2005 int state_index = 0; 2006 struct radeon_i2c_bus_rec i2c_bus; 2007 union power_info *power_info; 2008 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2009 u16 data_offset; 2010 u8 frev, crev; 2011 2012 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2013 &frev, &crev, &data_offset)) 2014 return state_index; 2015 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2016 2017 /* add the i2c bus for thermal/fan chip */ 2018 if ((power_info->info.ucOverdriveThermalController > 0) && 2019 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2020 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2021 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2022 power_info->info.ucOverdriveControllerAddress >> 1); 2023 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2024 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2025 #ifdef notyet 2026 if (rdev->pm.i2c_bus) { 2027 struct i2c_board_info info = { }; 2028 const char *name = thermal_controller_names[power_info->info. 2029 ucOverdriveThermalController]; 2030 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2031 strlcpy(info.type, name, sizeof(info.type)); 2032 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2033 } 2034 #endif 2035 } 2036 num_modes = power_info->info.ucNumOfPowerModeEntries; 2037 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2038 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2039 if (num_modes == 0) 2040 return state_index; 2041 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL); 2042 if (!rdev->pm.power_state) 2043 return state_index; 2044 /* last mode is usually default, array is low to high */ 2045 for (i = 0; i < num_modes; i++) { 2046 rdev->pm.power_state[state_index].clock_info = 2047 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2048 if (!rdev->pm.power_state[state_index].clock_info) 2049 return state_index; 2050 rdev->pm.power_state[state_index].num_clock_modes = 1; 2051 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2052 switch (frev) { 2053 case 1: 2054 rdev->pm.power_state[state_index].clock_info[0].mclk = 2055 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2056 rdev->pm.power_state[state_index].clock_info[0].sclk = 2057 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2058 /* skip invalid modes */ 2059 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2060 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2061 continue; 2062 rdev->pm.power_state[state_index].pcie_lanes = 2063 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2064 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2065 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2066 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2067 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2068 VOLTAGE_GPIO; 2069 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2070 radeon_lookup_gpio(rdev, 2071 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2072 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2073 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2074 true; 2075 else 2076 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2077 false; 2078 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2079 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2080 VOLTAGE_VDDC; 2081 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2082 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2083 } 2084 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2085 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2086 state_index++; 2087 break; 2088 case 2: 2089 rdev->pm.power_state[state_index].clock_info[0].mclk = 2090 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2091 rdev->pm.power_state[state_index].clock_info[0].sclk = 2092 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2093 /* skip invalid modes */ 2094 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2095 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2096 continue; 2097 rdev->pm.power_state[state_index].pcie_lanes = 2098 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2099 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2100 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2101 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2102 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2103 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2104 VOLTAGE_GPIO; 2105 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2106 radeon_lookup_gpio(rdev, 2107 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2108 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2109 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2110 true; 2111 else 2112 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2113 false; 2114 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2115 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2116 VOLTAGE_VDDC; 2117 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2118 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2119 } 2120 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2121 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2122 state_index++; 2123 break; 2124 case 3: 2125 rdev->pm.power_state[state_index].clock_info[0].mclk = 2126 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2127 rdev->pm.power_state[state_index].clock_info[0].sclk = 2128 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2129 /* skip invalid modes */ 2130 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2131 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2132 continue; 2133 rdev->pm.power_state[state_index].pcie_lanes = 2134 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2135 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2136 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2137 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2138 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2139 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2140 VOLTAGE_GPIO; 2141 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2142 radeon_lookup_gpio(rdev, 2143 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2144 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2145 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2146 true; 2147 else 2148 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2149 false; 2150 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2151 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2152 VOLTAGE_VDDC; 2153 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2154 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2155 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2156 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2157 true; 2158 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2159 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2160 } 2161 } 2162 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2163 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2164 state_index++; 2165 break; 2166 } 2167 } 2168 /* last mode is usually default */ 2169 if (rdev->pm.default_power_state_index == -1) { 2170 rdev->pm.power_state[state_index - 1].type = 2171 POWER_STATE_TYPE_DEFAULT; 2172 rdev->pm.default_power_state_index = state_index - 1; 2173 rdev->pm.power_state[state_index - 1].default_clock_mode = 2174 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2175 rdev->pm.power_state[state_index].flags &= 2176 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2177 rdev->pm.power_state[state_index].misc = 0; 2178 rdev->pm.power_state[state_index].misc2 = 0; 2179 } 2180 return state_index; 2181 } 2182 2183 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2184 ATOM_PPLIB_THERMALCONTROLLER *controller) 2185 { 2186 struct radeon_i2c_bus_rec i2c_bus; 2187 2188 /* add the i2c bus for thermal/fan chip */ 2189 if (controller->ucType > 0) { 2190 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2191 DRM_INFO("Internal thermal controller %s fan control\n", 2192 (controller->ucFanParameters & 2193 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2194 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2195 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2196 DRM_INFO("Internal thermal controller %s fan control\n", 2197 (controller->ucFanParameters & 2198 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2199 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2200 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2201 DRM_INFO("Internal thermal controller %s fan control\n", 2202 (controller->ucFanParameters & 2203 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2204 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2205 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2206 DRM_INFO("Internal thermal controller %s fan control\n", 2207 (controller->ucFanParameters & 2208 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2209 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2210 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2211 DRM_INFO("Internal thermal controller %s fan control\n", 2212 (controller->ucFanParameters & 2213 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2214 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2215 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2216 DRM_INFO("Internal thermal controller %s fan control\n", 2217 (controller->ucFanParameters & 2218 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2219 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2220 } else if ((controller->ucType == 2221 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || 2222 (controller->ucType == 2223 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) || 2224 (controller->ucType == 2225 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) { 2226 DRM_INFO("Special thermal controller config\n"); 2227 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2228 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2229 pp_lib_thermal_controller_names[controller->ucType], 2230 controller->ucI2cAddress >> 1, 2231 (controller->ucFanParameters & 2232 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2233 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2234 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2235 #ifdef notyet 2236 if (rdev->pm.i2c_bus) { 2237 struct i2c_board_info info = { }; 2238 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2239 info.addr = controller->ucI2cAddress >> 1; 2240 strlcpy(info.type, name, sizeof(info.type)); 2241 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2242 } 2243 #endif 2244 } else { 2245 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2246 controller->ucType, 2247 controller->ucI2cAddress >> 1, 2248 (controller->ucFanParameters & 2249 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2250 } 2251 } 2252 } 2253 2254 static void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2255 u16 *vddc, u16 *vddci) 2256 { 2257 struct radeon_mode_info *mode_info = &rdev->mode_info; 2258 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2259 u8 frev, crev; 2260 u16 data_offset; 2261 union firmware_info *firmware_info; 2262 2263 *vddc = 0; 2264 *vddci = 0; 2265 2266 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2267 &frev, &crev, &data_offset)) { 2268 firmware_info = 2269 (union firmware_info *)(mode_info->atom_context->bios + 2270 data_offset); 2271 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2272 if ((frev == 2) && (crev >= 2)) 2273 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2274 } 2275 } 2276 2277 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2278 int state_index, int mode_index, 2279 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2280 { 2281 int j; 2282 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2283 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2284 u16 vddc, vddci; 2285 2286 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci); 2287 2288 rdev->pm.power_state[state_index].misc = misc; 2289 rdev->pm.power_state[state_index].misc2 = misc2; 2290 rdev->pm.power_state[state_index].pcie_lanes = 2291 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2292 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2293 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2294 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2295 rdev->pm.power_state[state_index].type = 2296 POWER_STATE_TYPE_BATTERY; 2297 break; 2298 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2299 rdev->pm.power_state[state_index].type = 2300 POWER_STATE_TYPE_BALANCED; 2301 break; 2302 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2303 rdev->pm.power_state[state_index].type = 2304 POWER_STATE_TYPE_PERFORMANCE; 2305 break; 2306 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2307 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2308 rdev->pm.power_state[state_index].type = 2309 POWER_STATE_TYPE_PERFORMANCE; 2310 break; 2311 } 2312 rdev->pm.power_state[state_index].flags = 0; 2313 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2314 rdev->pm.power_state[state_index].flags |= 2315 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2316 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2317 rdev->pm.power_state[state_index].type = 2318 POWER_STATE_TYPE_DEFAULT; 2319 rdev->pm.default_power_state_index = state_index; 2320 rdev->pm.power_state[state_index].default_clock_mode = 2321 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2322 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 2323 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2324 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2325 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2326 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2327 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2328 } else { 2329 /* patch the table values with the default slck/mclk from firmware info */ 2330 for (j = 0; j < mode_index; j++) { 2331 rdev->pm.power_state[state_index].clock_info[j].mclk = 2332 rdev->clock.default_mclk; 2333 rdev->pm.power_state[state_index].clock_info[j].sclk = 2334 rdev->clock.default_sclk; 2335 if (vddc) 2336 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2337 vddc; 2338 } 2339 } 2340 } 2341 } 2342 2343 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2344 int state_index, int mode_index, 2345 union pplib_clock_info *clock_info) 2346 { 2347 u32 sclk, mclk; 2348 u16 vddc; 2349 2350 if (rdev->flags & RADEON_IS_IGP) { 2351 if (rdev->family >= CHIP_PALM) { 2352 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2353 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2354 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2355 } else { 2356 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2357 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2358 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2359 } 2360 } else if (ASIC_IS_DCE6(rdev)) { 2361 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2362 sclk |= clock_info->si.ucEngineClockHigh << 16; 2363 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2364 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2365 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2366 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2367 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2368 VOLTAGE_SW; 2369 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2370 le16_to_cpu(clock_info->si.usVDDC); 2371 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2372 le16_to_cpu(clock_info->si.usVDDCI); 2373 } else if (ASIC_IS_DCE4(rdev)) { 2374 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2375 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2376 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2377 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2378 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2379 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2380 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2381 VOLTAGE_SW; 2382 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2383 le16_to_cpu(clock_info->evergreen.usVDDC); 2384 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2385 le16_to_cpu(clock_info->evergreen.usVDDCI); 2386 } else { 2387 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2388 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2389 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2390 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2391 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2392 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2393 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2394 VOLTAGE_SW; 2395 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2396 le16_to_cpu(clock_info->r600.usVDDC); 2397 } 2398 2399 /* patch up vddc if necessary */ 2400 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2401 case ATOM_VIRTUAL_VOLTAGE_ID0: 2402 case ATOM_VIRTUAL_VOLTAGE_ID1: 2403 case ATOM_VIRTUAL_VOLTAGE_ID2: 2404 case ATOM_VIRTUAL_VOLTAGE_ID3: 2405 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2406 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2407 &vddc) == 0) 2408 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2409 break; 2410 default: 2411 break; 2412 } 2413 2414 if (rdev->flags & RADEON_IS_IGP) { 2415 /* skip invalid modes */ 2416 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2417 return false; 2418 } else { 2419 /* skip invalid modes */ 2420 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2421 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2422 return false; 2423 } 2424 return true; 2425 } 2426 2427 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2428 { 2429 struct radeon_mode_info *mode_info = &rdev->mode_info; 2430 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2431 union pplib_power_state *power_state; 2432 int i, j; 2433 int state_index = 0, mode_index = 0; 2434 union pplib_clock_info *clock_info; 2435 bool valid; 2436 union power_info *power_info; 2437 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2438 u16 data_offset; 2439 u8 frev, crev; 2440 2441 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2442 &frev, &crev, &data_offset)) 2443 return state_index; 2444 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2445 2446 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2447 if (power_info->pplib.ucNumStates == 0) 2448 return state_index; 2449 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2450 power_info->pplib.ucNumStates, GFP_KERNEL); 2451 if (!rdev->pm.power_state) 2452 return state_index; 2453 /* first mode is usually default, followed by low to high */ 2454 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2455 mode_index = 0; 2456 power_state = (union pplib_power_state *) 2457 (mode_info->atom_context->bios + data_offset + 2458 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2459 i * power_info->pplib.ucStateEntrySize); 2460 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2461 (mode_info->atom_context->bios + data_offset + 2462 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2463 (power_state->v1.ucNonClockStateIndex * 2464 power_info->pplib.ucNonClockSize)); 2465 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2466 ((power_info->pplib.ucStateEntrySize - 1) ? 2467 (power_info->pplib.ucStateEntrySize - 1) : 1), 2468 GFP_KERNEL); 2469 if (!rdev->pm.power_state[i].clock_info) 2470 return state_index; 2471 if (power_info->pplib.ucStateEntrySize - 1) { 2472 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2473 clock_info = (union pplib_clock_info *) 2474 (mode_info->atom_context->bios + data_offset + 2475 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2476 (power_state->v1.ucClockStateIndices[j] * 2477 power_info->pplib.ucClockInfoSize)); 2478 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2479 state_index, mode_index, 2480 clock_info); 2481 if (valid) 2482 mode_index++; 2483 } 2484 } else { 2485 rdev->pm.power_state[state_index].clock_info[0].mclk = 2486 rdev->clock.default_mclk; 2487 rdev->pm.power_state[state_index].clock_info[0].sclk = 2488 rdev->clock.default_sclk; 2489 mode_index++; 2490 } 2491 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2492 if (mode_index) { 2493 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2494 non_clock_info); 2495 state_index++; 2496 } 2497 } 2498 /* if multiple clock modes, mark the lowest as no display */ 2499 for (i = 0; i < state_index; i++) { 2500 if (rdev->pm.power_state[i].num_clock_modes > 1) 2501 rdev->pm.power_state[i].clock_info[0].flags |= 2502 RADEON_PM_MODE_NO_DISPLAY; 2503 } 2504 /* first mode is usually default */ 2505 if (rdev->pm.default_power_state_index == -1) { 2506 rdev->pm.power_state[0].type = 2507 POWER_STATE_TYPE_DEFAULT; 2508 rdev->pm.default_power_state_index = 0; 2509 rdev->pm.power_state[0].default_clock_mode = 2510 &rdev->pm.power_state[0].clock_info[0]; 2511 } 2512 return state_index; 2513 } 2514 2515 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2516 { 2517 struct radeon_mode_info *mode_info = &rdev->mode_info; 2518 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2519 union pplib_power_state *power_state; 2520 int i, j, non_clock_array_index, clock_array_index; 2521 int state_index = 0, mode_index = 0; 2522 union pplib_clock_info *clock_info; 2523 struct _StateArray *state_array; 2524 struct _ClockInfoArray *clock_info_array; 2525 struct _NonClockInfoArray *non_clock_info_array; 2526 bool valid; 2527 union power_info *power_info; 2528 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2529 u16 data_offset; 2530 u8 frev, crev; 2531 u8 *power_state_offset; 2532 2533 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2534 &frev, &crev, &data_offset)) 2535 return state_index; 2536 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2537 2538 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2539 state_array = (struct _StateArray *) 2540 (mode_info->atom_context->bios + data_offset + 2541 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2542 clock_info_array = (struct _ClockInfoArray *) 2543 (mode_info->atom_context->bios + data_offset + 2544 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2545 non_clock_info_array = (struct _NonClockInfoArray *) 2546 (mode_info->atom_context->bios + data_offset + 2547 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2548 if (state_array->ucNumEntries == 0) 2549 return state_index; 2550 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2551 state_array->ucNumEntries, GFP_KERNEL); 2552 if (!rdev->pm.power_state) 2553 return state_index; 2554 power_state_offset = (u8 *)state_array->states; 2555 for (i = 0; i < state_array->ucNumEntries; i++) { 2556 mode_index = 0; 2557 power_state = (union pplib_power_state *)power_state_offset; 2558 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2559 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2560 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2561 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) * 2562 (power_state->v2.ucNumDPMLevels ? 2563 power_state->v2.ucNumDPMLevels : 1), 2564 GFP_KERNEL); 2565 if (!rdev->pm.power_state[i].clock_info) 2566 return state_index; 2567 if (power_state->v2.ucNumDPMLevels) { 2568 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2569 clock_array_index = power_state->v2.clockInfoIndex[j]; 2570 clock_info = (union pplib_clock_info *) 2571 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2572 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2573 state_index, mode_index, 2574 clock_info); 2575 if (valid) 2576 mode_index++; 2577 } 2578 } else { 2579 rdev->pm.power_state[state_index].clock_info[0].mclk = 2580 rdev->clock.default_mclk; 2581 rdev->pm.power_state[state_index].clock_info[0].sclk = 2582 rdev->clock.default_sclk; 2583 mode_index++; 2584 } 2585 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2586 if (mode_index) { 2587 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2588 non_clock_info); 2589 state_index++; 2590 } 2591 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2592 } 2593 /* if multiple clock modes, mark the lowest as no display */ 2594 for (i = 0; i < state_index; i++) { 2595 if (rdev->pm.power_state[i].num_clock_modes > 1) 2596 rdev->pm.power_state[i].clock_info[0].flags |= 2597 RADEON_PM_MODE_NO_DISPLAY; 2598 } 2599 /* first mode is usually default */ 2600 if (rdev->pm.default_power_state_index == -1) { 2601 rdev->pm.power_state[0].type = 2602 POWER_STATE_TYPE_DEFAULT; 2603 rdev->pm.default_power_state_index = 0; 2604 rdev->pm.power_state[0].default_clock_mode = 2605 &rdev->pm.power_state[0].clock_info[0]; 2606 } 2607 return state_index; 2608 } 2609 2610 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2611 { 2612 struct radeon_mode_info *mode_info = &rdev->mode_info; 2613 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2614 u16 data_offset; 2615 u8 frev, crev; 2616 int state_index = 0; 2617 2618 rdev->pm.default_power_state_index = -1; 2619 2620 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2621 &frev, &crev, &data_offset)) { 2622 switch (frev) { 2623 case 1: 2624 case 2: 2625 case 3: 2626 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2627 break; 2628 case 4: 2629 case 5: 2630 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2631 break; 2632 case 6: 2633 state_index = radeon_atombios_parse_power_table_6(rdev); 2634 break; 2635 default: 2636 break; 2637 } 2638 } 2639 2640 if (state_index == 0) { 2641 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2642 if (rdev->pm.power_state) { 2643 rdev->pm.power_state[0].clock_info = 2644 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2645 if (rdev->pm.power_state[0].clock_info) { 2646 /* add the default mode */ 2647 rdev->pm.power_state[state_index].type = 2648 POWER_STATE_TYPE_DEFAULT; 2649 rdev->pm.power_state[state_index].num_clock_modes = 1; 2650 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2651 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2652 rdev->pm.power_state[state_index].default_clock_mode = 2653 &rdev->pm.power_state[state_index].clock_info[0]; 2654 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2655 rdev->pm.power_state[state_index].pcie_lanes = 16; 2656 rdev->pm.default_power_state_index = state_index; 2657 rdev->pm.power_state[state_index].flags = 0; 2658 state_index++; 2659 } 2660 } 2661 } 2662 2663 rdev->pm.num_power_states = state_index; 2664 2665 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2666 rdev->pm.current_clock_mode_index = 0; 2667 if (rdev->pm.default_power_state_index >= 0) 2668 rdev->pm.current_vddc = 2669 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2670 else 2671 rdev->pm.current_vddc = 0; 2672 } 2673 2674 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 2675 { 2676 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 2677 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 2678 2679 args.ucEnable = enable; 2680 2681 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2682 } 2683 2684 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 2685 { 2686 GET_ENGINE_CLOCK_PS_ALLOCATION args; 2687 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 2688 2689 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2690 return le32_to_cpu(args.ulReturnEngineClock); 2691 } 2692 2693 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 2694 { 2695 GET_MEMORY_CLOCK_PS_ALLOCATION args; 2696 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 2697 2698 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2699 return le32_to_cpu(args.ulReturnMemoryClock); 2700 } 2701 2702 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 2703 uint32_t eng_clock) 2704 { 2705 SET_ENGINE_CLOCK_PS_ALLOCATION args; 2706 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 2707 2708 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 2709 2710 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2711 } 2712 2713 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 2714 uint32_t mem_clock) 2715 { 2716 SET_MEMORY_CLOCK_PS_ALLOCATION args; 2717 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 2718 2719 if (rdev->flags & RADEON_IS_IGP) 2720 return; 2721 2722 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 2723 2724 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2725 } 2726 2727 union set_voltage { 2728 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 2729 struct _SET_VOLTAGE_PARAMETERS v1; 2730 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 2731 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 2732 }; 2733 2734 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 2735 { 2736 union set_voltage args; 2737 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 2738 u8 frev, crev, volt_index = voltage_level; 2739 2740 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2741 return; 2742 2743 /* 0xff01 is a flag rather then an actual voltage */ 2744 if (voltage_level == 0xff01) 2745 return; 2746 2747 switch (crev) { 2748 case 1: 2749 args.v1.ucVoltageType = voltage_type; 2750 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 2751 args.v1.ucVoltageIndex = volt_index; 2752 break; 2753 case 2: 2754 args.v2.ucVoltageType = voltage_type; 2755 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 2756 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 2757 break; 2758 case 3: 2759 args.v3.ucVoltageType = voltage_type; 2760 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 2761 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 2762 break; 2763 default: 2764 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 2765 return; 2766 } 2767 2768 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2769 } 2770 2771 static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 2772 u16 voltage_id, u16 *voltage) 2773 { 2774 union set_voltage args; 2775 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 2776 u8 frev, crev; 2777 2778 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2779 return -EINVAL; 2780 2781 switch (crev) { 2782 case 1: 2783 return -EINVAL; 2784 case 2: 2785 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 2786 args.v2.ucVoltageMode = 0; 2787 args.v2.usVoltageLevel = 0; 2788 2789 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2790 2791 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 2792 break; 2793 case 3: 2794 args.v3.ucVoltageType = voltage_type; 2795 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 2796 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 2797 2798 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2799 2800 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 2801 break; 2802 default: 2803 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 2804 return -EINVAL; 2805 } 2806 2807 return 0; 2808 } 2809 2810 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 2811 { 2812 struct radeon_device *rdev = dev->dev_private; 2813 uint32_t bios_2_scratch, bios_6_scratch; 2814 2815 if (rdev->family >= CHIP_R600) { 2816 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 2817 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 2818 } else { 2819 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 2820 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2821 } 2822 2823 /* let the bios control the backlight */ 2824 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 2825 2826 /* tell the bios not to handle mode switching */ 2827 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 2828 2829 /* clear the vbios dpms state */ 2830 if (ASIC_IS_DCE4(rdev)) 2831 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 2832 2833 if (rdev->family >= CHIP_R600) { 2834 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 2835 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 2836 } else { 2837 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 2838 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2839 } 2840 2841 } 2842 2843 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 2844 { 2845 uint32_t scratch_reg; 2846 int i; 2847 2848 if (rdev->family >= CHIP_R600) 2849 scratch_reg = R600_BIOS_0_SCRATCH; 2850 else 2851 scratch_reg = RADEON_BIOS_0_SCRATCH; 2852 2853 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 2854 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 2855 } 2856 2857 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 2858 { 2859 uint32_t scratch_reg; 2860 int i; 2861 2862 if (rdev->family >= CHIP_R600) 2863 scratch_reg = R600_BIOS_0_SCRATCH; 2864 else 2865 scratch_reg = RADEON_BIOS_0_SCRATCH; 2866 2867 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 2868 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 2869 } 2870 2871 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 2872 { 2873 struct drm_device *dev = encoder->dev; 2874 struct radeon_device *rdev = dev->dev_private; 2875 uint32_t bios_6_scratch; 2876 2877 if (rdev->family >= CHIP_R600) 2878 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 2879 else 2880 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2881 2882 if (lock) { 2883 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 2884 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 2885 } else { 2886 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 2887 bios_6_scratch |= ATOM_S6_ACC_MODE; 2888 } 2889 2890 if (rdev->family >= CHIP_R600) 2891 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 2892 else 2893 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 2894 } 2895 2896 /* at some point we may want to break this out into individual functions */ 2897 void 2898 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 2899 struct drm_encoder *encoder, 2900 bool connected) 2901 { 2902 struct drm_device *dev = connector->dev; 2903 struct radeon_device *rdev = dev->dev_private; 2904 struct radeon_connector *radeon_connector = 2905 to_radeon_connector(connector); 2906 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2907 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 2908 2909 if (rdev->family >= CHIP_R600) { 2910 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2911 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 2912 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 2913 } else { 2914 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2915 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 2916 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 2917 } 2918 2919 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 2920 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 2921 if (connected) { 2922 DRM_DEBUG_KMS("TV1 connected\n"); 2923 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 2924 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 2925 } else { 2926 DRM_DEBUG_KMS("TV1 disconnected\n"); 2927 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 2928 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 2929 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 2930 } 2931 } 2932 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 2933 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 2934 if (connected) { 2935 DRM_DEBUG_KMS("CV connected\n"); 2936 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 2937 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 2938 } else { 2939 DRM_DEBUG_KMS("CV disconnected\n"); 2940 bios_0_scratch &= ~ATOM_S0_CV_MASK; 2941 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 2942 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 2943 } 2944 } 2945 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 2946 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 2947 if (connected) { 2948 DRM_DEBUG_KMS("LCD1 connected\n"); 2949 bios_0_scratch |= ATOM_S0_LCD1; 2950 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 2951 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 2952 } else { 2953 DRM_DEBUG_KMS("LCD1 disconnected\n"); 2954 bios_0_scratch &= ~ATOM_S0_LCD1; 2955 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 2956 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 2957 } 2958 } 2959 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 2960 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 2961 if (connected) { 2962 DRM_DEBUG_KMS("CRT1 connected\n"); 2963 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 2964 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 2965 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 2966 } else { 2967 DRM_DEBUG_KMS("CRT1 disconnected\n"); 2968 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 2969 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 2970 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 2971 } 2972 } 2973 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 2974 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 2975 if (connected) { 2976 DRM_DEBUG_KMS("CRT2 connected\n"); 2977 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 2978 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 2979 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 2980 } else { 2981 DRM_DEBUG_KMS("CRT2 disconnected\n"); 2982 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 2983 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 2984 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 2985 } 2986 } 2987 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 2988 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 2989 if (connected) { 2990 DRM_DEBUG_KMS("DFP1 connected\n"); 2991 bios_0_scratch |= ATOM_S0_DFP1; 2992 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 2993 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 2994 } else { 2995 DRM_DEBUG_KMS("DFP1 disconnected\n"); 2996 bios_0_scratch &= ~ATOM_S0_DFP1; 2997 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 2998 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 2999 } 3000 } 3001 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3002 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3003 if (connected) { 3004 DRM_DEBUG_KMS("DFP2 connected\n"); 3005 bios_0_scratch |= ATOM_S0_DFP2; 3006 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 3007 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 3008 } else { 3009 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3010 bios_0_scratch &= ~ATOM_S0_DFP2; 3011 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 3012 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 3013 } 3014 } 3015 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 3016 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 3017 if (connected) { 3018 DRM_DEBUG_KMS("DFP3 connected\n"); 3019 bios_0_scratch |= ATOM_S0_DFP3; 3020 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 3021 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 3022 } else { 3023 DRM_DEBUG_KMS("DFP3 disconnected\n"); 3024 bios_0_scratch &= ~ATOM_S0_DFP3; 3025 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 3026 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 3027 } 3028 } 3029 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 3030 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 3031 if (connected) { 3032 DRM_DEBUG_KMS("DFP4 connected\n"); 3033 bios_0_scratch |= ATOM_S0_DFP4; 3034 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 3035 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 3036 } else { 3037 DRM_DEBUG_KMS("DFP4 disconnected\n"); 3038 bios_0_scratch &= ~ATOM_S0_DFP4; 3039 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 3040 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 3041 } 3042 } 3043 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 3044 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 3045 if (connected) { 3046 DRM_DEBUG_KMS("DFP5 connected\n"); 3047 bios_0_scratch |= ATOM_S0_DFP5; 3048 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 3049 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 3050 } else { 3051 DRM_DEBUG_KMS("DFP5 disconnected\n"); 3052 bios_0_scratch &= ~ATOM_S0_DFP5; 3053 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 3054 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 3055 } 3056 } 3057 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 3058 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 3059 if (connected) { 3060 DRM_DEBUG_KMS("DFP6 connected\n"); 3061 bios_0_scratch |= ATOM_S0_DFP6; 3062 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 3063 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 3064 } else { 3065 DRM_DEBUG_KMS("DFP6 disconnected\n"); 3066 bios_0_scratch &= ~ATOM_S0_DFP6; 3067 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 3068 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 3069 } 3070 } 3071 3072 if (rdev->family >= CHIP_R600) { 3073 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 3074 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 3075 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 3076 } else { 3077 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3078 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 3079 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3080 } 3081 } 3082 3083 void 3084 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3085 { 3086 struct drm_device *dev = encoder->dev; 3087 struct radeon_device *rdev = dev->dev_private; 3088 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3089 uint32_t bios_3_scratch; 3090 3091 if (ASIC_IS_DCE4(rdev)) 3092 return; 3093 3094 if (rdev->family >= CHIP_R600) 3095 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 3096 else 3097 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 3098 3099 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3100 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 3101 bios_3_scratch |= (crtc << 18); 3102 } 3103 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 3104 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 3105 bios_3_scratch |= (crtc << 24); 3106 } 3107 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3108 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 3109 bios_3_scratch |= (crtc << 16); 3110 } 3111 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3112 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 3113 bios_3_scratch |= (crtc << 20); 3114 } 3115 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3116 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 3117 bios_3_scratch |= (crtc << 17); 3118 } 3119 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3120 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 3121 bios_3_scratch |= (crtc << 19); 3122 } 3123 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3124 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 3125 bios_3_scratch |= (crtc << 23); 3126 } 3127 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 3128 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 3129 bios_3_scratch |= (crtc << 25); 3130 } 3131 3132 if (rdev->family >= CHIP_R600) 3133 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 3134 else 3135 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 3136 } 3137 3138 void 3139 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3140 { 3141 struct drm_device *dev = encoder->dev; 3142 struct radeon_device *rdev = dev->dev_private; 3143 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3144 uint32_t bios_2_scratch; 3145 3146 if (ASIC_IS_DCE4(rdev)) 3147 return; 3148 3149 if (rdev->family >= CHIP_R600) 3150 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 3151 else 3152 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 3153 3154 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3155 if (on) 3156 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 3157 else 3158 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 3159 } 3160 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 3161 if (on) 3162 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 3163 else 3164 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 3165 } 3166 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3167 if (on) 3168 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 3169 else 3170 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 3171 } 3172 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3173 if (on) 3174 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 3175 else 3176 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 3177 } 3178 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3179 if (on) 3180 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 3181 else 3182 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 3183 } 3184 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3185 if (on) 3186 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 3187 else 3188 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 3189 } 3190 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3191 if (on) 3192 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 3193 else 3194 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 3195 } 3196 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 3197 if (on) 3198 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 3199 else 3200 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 3201 } 3202 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 3203 if (on) 3204 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 3205 else 3206 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 3207 } 3208 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 3209 if (on) 3210 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 3211 else 3212 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 3213 } 3214 3215 if (rdev->family >= CHIP_R600) 3216 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 3217 else 3218 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 3219 } 3220