1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #include <drm/drmP.h> 29 #include "radeon_reg.h" 30 #include "radeon.h" 31 #include "atom.h" 32 33 #include <linux/slab.h> 34 #include <linux/acpi.h> 35 36 #if defined(__amd64__) || defined(__i386__) 37 #include <dev/isa/isareg.h> 38 #include <dev/isa/isavar.h> 39 #endif 40 41 #if defined (__loongson__) 42 #include <machine/autoconf.h> 43 #endif 44 45 /* 46 * BIOS. 47 */ 48 49 /* If you boot an IGP board with a discrete card as the primary, 50 * the IGP rom is not accessible via the rom bar as the IGP rom is 51 * part of the system bios. On boot, the system bios puts a 52 * copy of the igp rom at the start of vram if a discrete card is 53 * present. 54 */ 55 #ifdef __linux__ 56 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 57 { 58 uint8_t __iomem *bios; 59 resource_size_t vram_base; 60 resource_size_t size = 256 * 1024; /* ??? */ 61 62 if (!(rdev->flags & RADEON_IS_IGP)) 63 if (!radeon_card_posted(rdev)) 64 return false; 65 66 rdev->bios = NULL; 67 vram_base = pci_resource_start(rdev->pdev, 0); 68 bios = ioremap(vram_base, size); 69 if (!bios) { 70 return false; 71 } 72 73 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 74 iounmap(bios); 75 return false; 76 } 77 rdev->bios = kmalloc(size, GFP_KERNEL); 78 if (rdev->bios == NULL) { 79 iounmap(bios); 80 return false; 81 } 82 memcpy_fromio(rdev->bios, bios, size); 83 iounmap(bios); 84 return true; 85 } 86 #else 87 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 88 { 89 uint8_t __iomem *bios; 90 bus_size_t size = 256 * 1024; /* ??? */ 91 bus_space_handle_t bsh; 92 bus_space_tag_t bst = rdev->memt; 93 94 if (!(rdev->flags & RADEON_IS_IGP)) 95 if (!radeon_card_posted(rdev)) 96 return false; 97 98 rdev->bios = NULL; 99 100 if (bus_space_map(bst, rdev->fb_aper_offset, size, BUS_SPACE_MAP_LINEAR, &bsh) != 0) 101 return false; 102 103 bios = bus_space_vaddr(rdev->memt, bsh); 104 if (bios == NULL) { 105 bus_space_unmap(bst, bsh, size); 106 return false; 107 } 108 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 109 bus_space_unmap(bst, bsh, size); 110 return false; 111 } 112 113 rdev->bios = kmalloc(size, GFP_KERNEL); 114 if (rdev->bios == NULL) { 115 bus_space_unmap(bst, bsh, size); 116 return false; 117 } 118 memcpy_fromio(rdev->bios, bios, size); 119 bus_space_unmap(bst, bsh, size); 120 return true; 121 } 122 #endif 123 124 #ifdef __linux__ 125 static bool radeon_read_bios(struct radeon_device *rdev) 126 { 127 uint8_t __iomem *bios, val1, val2; 128 size_t size; 129 130 rdev->bios = NULL; 131 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 132 bios = pci_map_rom(rdev->pdev, &size); 133 if (!bios) { 134 return false; 135 } 136 137 val1 = readb(&bios[0]); 138 val2 = readb(&bios[1]); 139 140 if (size == 0 || val1 != 0x55 || val2 != 0xaa) { 141 pci_unmap_rom(rdev->pdev, bios); 142 return false; 143 } 144 rdev->bios = kzalloc(size, GFP_KERNEL); 145 if (rdev->bios == NULL) { 146 pci_unmap_rom(rdev->pdev, bios); 147 return false; 148 } 149 memcpy_fromio(rdev->bios, bios, size); 150 pci_unmap_rom(rdev->pdev, bios); 151 return true; 152 } 153 #else 154 static bool radeon_read_bios(struct radeon_device *rdev) 155 { 156 uint8_t __iomem *bios; 157 bus_size_t size; 158 pcireg_t address, mask; 159 bus_space_handle_t romh; 160 int rc; 161 162 rdev->bios = NULL; 163 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 164 165 address = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 166 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 167 mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 168 address |= PCI_ROM_ENABLE; 169 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, address); 170 171 size = PCI_ROM_SIZE(mask); 172 if (size == 0) 173 return false; 174 rc = bus_space_map(rdev->memt, PCI_ROM_ADDR(address), size, 175 BUS_SPACE_MAP_LINEAR, &romh); 176 if (rc != 0) { 177 printf(": can't map PCI ROM (%d)\n", rc); 178 return false; 179 } 180 bios = (uint8_t *)bus_space_vaddr(rdev->memt, romh); 181 if (!bios) { 182 printf(": bus_space_vaddr failed\n"); 183 return false; 184 } 185 186 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) 187 goto fail; 188 rdev->bios = kmalloc(size, GFP_KERNEL); 189 memcpy(rdev->bios, bios, size); 190 bus_space_unmap(rdev->memt, romh, size); 191 return true; 192 fail: 193 bus_space_unmap(rdev->memt, romh, size); 194 return false; 195 } 196 197 #endif 198 199 #ifdef __linux__ 200 static bool radeon_read_platform_bios(struct radeon_device *rdev) 201 { 202 uint8_t __iomem *bios; 203 size_t size; 204 205 rdev->bios = NULL; 206 207 bios = pci_platform_rom(rdev->pdev, &size); 208 if (!bios) { 209 return false; 210 } 211 212 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 213 return false; 214 } 215 rdev->bios = kmemdup(bios, size, GFP_KERNEL); 216 if (rdev->bios == NULL) { 217 return false; 218 } 219 220 return true; 221 } 222 #else 223 static bool radeon_read_platform_bios(struct radeon_device *rdev) 224 { 225 #if defined(__amd64__) || defined(__i386__) || defined(__loongson__) 226 uint8_t __iomem *bios; 227 bus_size_t size = 256 * 1024; /* ??? */ 228 uint8_t *found = NULL; 229 int i; 230 231 if (!(rdev->flags & RADEON_IS_IGP)) 232 if (!radeon_card_posted(rdev)) 233 return false; 234 235 rdev->bios = NULL; 236 237 #if defined(__loongson__) 238 if (loongson_videobios == NULL) 239 return false; 240 bios = loongson_videobios; 241 #else 242 bios = (u8 *)ISA_HOLE_VADDR(0xc0000); 243 #endif 244 245 for (i = 0; i + 2 < size; i++) { 246 if (bios[i] == 0x55 && bios[i + 1] == 0xaa) { 247 found = bios + i; 248 break; 249 } 250 251 } 252 if (found == NULL) { 253 DRM_ERROR("bios size zero or checksum mismatch\n"); 254 return false; 255 } 256 257 rdev->bios = kmalloc(size, GFP_KERNEL); 258 if (rdev->bios == NULL) 259 return false; 260 261 memcpy(rdev->bios, found, size); 262 263 return true; 264 #endif 265 return false; 266 } 267 #endif 268 269 #ifdef CONFIG_ACPI 270 /* ATRM is used to get the BIOS on the discrete cards in 271 * dual-gpu systems. 272 */ 273 /* retrieve the ROM in 4k blocks */ 274 #define ATRM_BIOS_PAGE 4096 275 /** 276 * radeon_atrm_call - fetch a chunk of the vbios 277 * 278 * @atrm_handle: acpi ATRM handle 279 * @bios: vbios image pointer 280 * @offset: offset of vbios image data to fetch 281 * @len: length of vbios image data to fetch 282 * 283 * Executes ATRM to fetch a chunk of the discrete 284 * vbios image on PX systems (all asics). 285 * Returns the length of the buffer fetched. 286 */ 287 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 288 int offset, int len) 289 { 290 acpi_status status; 291 union acpi_object atrm_arg_elements[2], *obj; 292 struct acpi_object_list atrm_arg; 293 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 294 295 atrm_arg.count = 2; 296 atrm_arg.pointer = &atrm_arg_elements[0]; 297 298 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 299 atrm_arg_elements[0].integer.value = offset; 300 301 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 302 atrm_arg_elements[1].integer.value = len; 303 304 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 305 if (ACPI_FAILURE(status)) { 306 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 307 return -ENODEV; 308 } 309 310 obj = (union acpi_object *)buffer.pointer; 311 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 312 len = obj->buffer.length; 313 kfree(buffer.pointer); 314 return len; 315 } 316 317 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 318 { 319 int ret; 320 int size = 256 * 1024; 321 int i; 322 struct pci_dev *pdev = NULL; 323 acpi_handle dhandle, atrm_handle; 324 acpi_status status; 325 bool found = false; 326 327 /* ATRM is for the discrete card only */ 328 if (rdev->flags & RADEON_IS_IGP) 329 return false; 330 331 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 332 dhandle = ACPI_HANDLE(&pdev->dev); 333 if (!dhandle) 334 continue; 335 336 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 337 if (!ACPI_FAILURE(status)) { 338 found = true; 339 break; 340 } 341 } 342 343 if (!found) { 344 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 345 dhandle = ACPI_HANDLE(&pdev->dev); 346 if (!dhandle) 347 continue; 348 349 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 350 if (!ACPI_FAILURE(status)) { 351 found = true; 352 break; 353 } 354 } 355 } 356 357 if (!found) 358 return false; 359 360 rdev->bios = kmalloc(size, GFP_KERNEL); 361 if (!rdev->bios) { 362 DRM_ERROR("Unable to allocate bios\n"); 363 return false; 364 } 365 366 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 367 ret = radeon_atrm_call(atrm_handle, 368 rdev->bios, 369 (i * ATRM_BIOS_PAGE), 370 ATRM_BIOS_PAGE); 371 if (ret < ATRM_BIOS_PAGE) 372 break; 373 } 374 375 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 376 kfree(rdev->bios); 377 return false; 378 } 379 return true; 380 } 381 #else 382 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 383 { 384 return false; 385 } 386 #endif 387 388 static bool ni_read_disabled_bios(struct radeon_device *rdev) 389 { 390 u32 bus_cntl; 391 u32 d1vga_control; 392 u32 d2vga_control; 393 u32 vga_render_control; 394 u32 rom_cntl; 395 bool r; 396 397 bus_cntl = RREG32(R600_BUS_CNTL); 398 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 399 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 400 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 401 rom_cntl = RREG32(R600_ROM_CNTL); 402 403 /* enable the rom */ 404 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 405 if (!ASIC_IS_NODCE(rdev)) { 406 /* Disable VGA mode */ 407 WREG32(AVIVO_D1VGA_CONTROL, 408 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 409 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 410 WREG32(AVIVO_D2VGA_CONTROL, 411 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 412 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 413 WREG32(AVIVO_VGA_RENDER_CONTROL, 414 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 415 } 416 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 417 418 r = radeon_read_bios(rdev); 419 420 /* restore regs */ 421 WREG32(R600_BUS_CNTL, bus_cntl); 422 if (!ASIC_IS_NODCE(rdev)) { 423 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 424 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 425 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 426 } 427 WREG32(R600_ROM_CNTL, rom_cntl); 428 return r; 429 } 430 431 static bool r700_read_disabled_bios(struct radeon_device *rdev) 432 { 433 uint32_t viph_control; 434 uint32_t bus_cntl; 435 uint32_t d1vga_control; 436 uint32_t d2vga_control; 437 uint32_t vga_render_control; 438 uint32_t rom_cntl; 439 uint32_t cg_spll_func_cntl = 0; 440 uint32_t cg_spll_status; 441 bool r; 442 443 viph_control = RREG32(RADEON_VIPH_CONTROL); 444 bus_cntl = RREG32(R600_BUS_CNTL); 445 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 446 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 447 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 448 rom_cntl = RREG32(R600_ROM_CNTL); 449 450 /* disable VIP */ 451 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 452 /* enable the rom */ 453 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 454 /* Disable VGA mode */ 455 WREG32(AVIVO_D1VGA_CONTROL, 456 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 457 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 458 WREG32(AVIVO_D2VGA_CONTROL, 459 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 460 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 461 WREG32(AVIVO_VGA_RENDER_CONTROL, 462 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 463 464 if (rdev->family == CHIP_RV730) { 465 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 466 467 /* enable bypass mode */ 468 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 469 R600_SPLL_BYPASS_EN)); 470 471 /* wait for SPLL_CHG_STATUS to change to 1 */ 472 cg_spll_status = 0; 473 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 474 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 475 476 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 477 } else 478 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 479 480 r = radeon_read_bios(rdev); 481 482 /* restore regs */ 483 if (rdev->family == CHIP_RV730) { 484 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 485 486 /* wait for SPLL_CHG_STATUS to change to 1 */ 487 cg_spll_status = 0; 488 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 489 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 490 } 491 WREG32(RADEON_VIPH_CONTROL, viph_control); 492 WREG32(R600_BUS_CNTL, bus_cntl); 493 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 494 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 495 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 496 WREG32(R600_ROM_CNTL, rom_cntl); 497 return r; 498 } 499 500 static bool r600_read_disabled_bios(struct radeon_device *rdev) 501 { 502 uint32_t viph_control; 503 uint32_t bus_cntl; 504 uint32_t d1vga_control; 505 uint32_t d2vga_control; 506 uint32_t vga_render_control; 507 uint32_t rom_cntl; 508 uint32_t general_pwrmgt; 509 uint32_t low_vid_lower_gpio_cntl; 510 uint32_t medium_vid_lower_gpio_cntl; 511 uint32_t high_vid_lower_gpio_cntl; 512 uint32_t ctxsw_vid_lower_gpio_cntl; 513 uint32_t lower_gpio_enable; 514 bool r; 515 516 viph_control = RREG32(RADEON_VIPH_CONTROL); 517 bus_cntl = RREG32(R600_BUS_CNTL); 518 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 519 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 520 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 521 rom_cntl = RREG32(R600_ROM_CNTL); 522 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 523 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 524 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 525 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 526 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 527 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 528 529 /* disable VIP */ 530 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 531 /* enable the rom */ 532 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 533 /* Disable VGA mode */ 534 WREG32(AVIVO_D1VGA_CONTROL, 535 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 536 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 537 WREG32(AVIVO_D2VGA_CONTROL, 538 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 539 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 540 WREG32(AVIVO_VGA_RENDER_CONTROL, 541 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 542 543 WREG32(R600_ROM_CNTL, 544 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 545 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 546 R600_SCK_OVERWRITE)); 547 548 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 549 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 550 (low_vid_lower_gpio_cntl & ~0x400)); 551 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 552 (medium_vid_lower_gpio_cntl & ~0x400)); 553 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 554 (high_vid_lower_gpio_cntl & ~0x400)); 555 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 556 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 557 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 558 559 r = radeon_read_bios(rdev); 560 561 /* restore regs */ 562 WREG32(RADEON_VIPH_CONTROL, viph_control); 563 WREG32(R600_BUS_CNTL, bus_cntl); 564 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 565 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 566 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 567 WREG32(R600_ROM_CNTL, rom_cntl); 568 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 569 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 570 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 571 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 572 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 573 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 574 return r; 575 } 576 577 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 578 { 579 uint32_t seprom_cntl1; 580 uint32_t viph_control; 581 uint32_t bus_cntl; 582 uint32_t d1vga_control; 583 uint32_t d2vga_control; 584 uint32_t vga_render_control; 585 uint32_t gpiopad_a; 586 uint32_t gpiopad_en; 587 uint32_t gpiopad_mask; 588 bool r; 589 590 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 591 viph_control = RREG32(RADEON_VIPH_CONTROL); 592 bus_cntl = RREG32(RV370_BUS_CNTL); 593 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 594 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 595 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 596 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 597 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 598 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 599 600 WREG32(RADEON_SEPROM_CNTL1, 601 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 602 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 603 WREG32(RADEON_GPIOPAD_A, 0); 604 WREG32(RADEON_GPIOPAD_EN, 0); 605 WREG32(RADEON_GPIOPAD_MASK, 0); 606 607 /* disable VIP */ 608 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 609 610 /* enable the rom */ 611 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 612 613 /* Disable VGA mode */ 614 WREG32(AVIVO_D1VGA_CONTROL, 615 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 616 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 617 WREG32(AVIVO_D2VGA_CONTROL, 618 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 619 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 620 WREG32(AVIVO_VGA_RENDER_CONTROL, 621 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 622 623 r = radeon_read_bios(rdev); 624 625 /* restore regs */ 626 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 627 WREG32(RADEON_VIPH_CONTROL, viph_control); 628 WREG32(RV370_BUS_CNTL, bus_cntl); 629 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 630 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 631 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 632 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 633 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 634 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 635 return r; 636 } 637 638 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 639 { 640 uint32_t seprom_cntl1; 641 uint32_t viph_control; 642 uint32_t bus_cntl; 643 uint32_t crtc_gen_cntl; 644 uint32_t crtc2_gen_cntl; 645 uint32_t crtc_ext_cntl; 646 uint32_t fp2_gen_cntl; 647 bool r; 648 649 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 650 viph_control = RREG32(RADEON_VIPH_CONTROL); 651 if (rdev->flags & RADEON_IS_PCIE) 652 bus_cntl = RREG32(RV370_BUS_CNTL); 653 else 654 bus_cntl = RREG32(RADEON_BUS_CNTL); 655 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 656 crtc2_gen_cntl = 0; 657 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 658 fp2_gen_cntl = 0; 659 660 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 661 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 662 } 663 664 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 665 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 666 } 667 668 WREG32(RADEON_SEPROM_CNTL1, 669 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 670 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 671 672 /* disable VIP */ 673 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 674 675 /* enable the rom */ 676 if (rdev->flags & RADEON_IS_PCIE) 677 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 678 else 679 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 680 681 /* Turn off mem requests and CRTC for both controllers */ 682 WREG32(RADEON_CRTC_GEN_CNTL, 683 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 684 (RADEON_CRTC_DISP_REQ_EN_B | 685 RADEON_CRTC_EXT_DISP_EN))); 686 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 687 WREG32(RADEON_CRTC2_GEN_CNTL, 688 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 689 RADEON_CRTC2_DISP_REQ_EN_B)); 690 } 691 /* Turn off CRTC */ 692 WREG32(RADEON_CRTC_EXT_CNTL, 693 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 694 (RADEON_CRTC_SYNC_TRISTAT | 695 RADEON_CRTC_DISPLAY_DIS))); 696 697 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 698 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 699 } 700 701 r = radeon_read_bios(rdev); 702 703 /* restore regs */ 704 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 705 WREG32(RADEON_VIPH_CONTROL, viph_control); 706 if (rdev->flags & RADEON_IS_PCIE) 707 WREG32(RV370_BUS_CNTL, bus_cntl); 708 else 709 WREG32(RADEON_BUS_CNTL, bus_cntl); 710 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 711 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 712 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 713 } 714 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 715 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) { 716 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 717 } 718 return r; 719 } 720 721 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 722 { 723 if (rdev->flags & RADEON_IS_IGP) 724 return igp_read_bios_from_vram(rdev); 725 else if (rdev->family >= CHIP_BARTS) 726 return ni_read_disabled_bios(rdev); 727 else if (rdev->family >= CHIP_RV770) 728 return r700_read_disabled_bios(rdev); 729 else if (rdev->family >= CHIP_R600) 730 return r600_read_disabled_bios(rdev); 731 else if (rdev->family >= CHIP_RS600) 732 return avivo_read_disabled_bios(rdev); 733 else 734 return legacy_read_disabled_bios(rdev); 735 } 736 737 #ifdef CONFIG_ACPI 738 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 739 { 740 struct acpi_table_header *hdr; 741 acpi_size tbl_size; 742 UEFI_ACPI_VFCT *vfct; 743 unsigned offset; 744 745 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr))) 746 return false; 747 tbl_size = hdr->length; 748 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 749 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 750 return false; 751 } 752 753 vfct = (UEFI_ACPI_VFCT *)hdr; 754 offset = vfct->VBIOSImageOffset; 755 756 while (offset < tbl_size) { 757 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset); 758 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader; 759 760 offset += sizeof(VFCT_IMAGE_HEADER); 761 if (offset > tbl_size) { 762 DRM_ERROR("ACPI VFCT image header truncated\n"); 763 return false; 764 } 765 766 offset += vhdr->ImageLength; 767 if (offset > tbl_size) { 768 DRM_ERROR("ACPI VFCT image truncated\n"); 769 return false; 770 } 771 772 if (vhdr->ImageLength && 773 vhdr->PCIBus == rdev->pdev->bus->number && 774 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) && 775 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) && 776 vhdr->VendorID == rdev->pdev->vendor && 777 vhdr->DeviceID == rdev->pdev->device) { 778 rdev->bios = kmemdup(&vbios->VbiosContent, 779 vhdr->ImageLength, 780 GFP_KERNEL); 781 782 if (!rdev->bios) 783 return false; 784 return true; 785 } 786 } 787 788 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 789 return false; 790 } 791 #else 792 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 793 { 794 return false; 795 } 796 #endif 797 798 bool radeon_get_bios(struct radeon_device *rdev) 799 { 800 bool r; 801 uint16_t tmp; 802 803 r = radeon_atrm_get_bios(rdev); 804 if (r == false) 805 r = radeon_acpi_vfct_bios(rdev); 806 if (r == false) 807 r = igp_read_bios_from_vram(rdev); 808 if (r == false) 809 r = radeon_read_bios(rdev); 810 if (r == false) 811 r = radeon_read_disabled_bios(rdev); 812 if (r == false) 813 r = radeon_read_platform_bios(rdev); 814 if (r == false || rdev->bios == NULL) { 815 DRM_ERROR("Unable to locate a BIOS ROM\n"); 816 rdev->bios = NULL; 817 return false; 818 } 819 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 820 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 821 goto free_bios; 822 } 823 824 tmp = RBIOS16(0x18); 825 if (RBIOS8(tmp + 0x14) != 0x0) { 826 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 827 goto free_bios; 828 } 829 830 rdev->bios_header_start = RBIOS16(0x48); 831 if (!rdev->bios_header_start) { 832 goto free_bios; 833 } 834 tmp = rdev->bios_header_start + 4; 835 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 836 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 837 rdev->is_atom_bios = true; 838 } else { 839 rdev->is_atom_bios = false; 840 } 841 842 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 843 return true; 844 free_bios: 845 kfree(rdev->bios); 846 rdev->bios = NULL; 847 return false; 848 } 849