1 /* $OpenBSD: radeon_clocks.c,v 1.3 2015/04/18 14:47:35 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include <dev/pci/drm/radeon_drm.h> 31 #include "radeon_reg.h" 32 #include "radeon.h" 33 #include "atom.h" 34 35 #if defined(__macppc__) || defined(__sparc64__) 36 #include <dev/ofw/openfirm.h> 37 #endif 38 39 /* 10 khz */ 40 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) 41 { 42 struct radeon_pll *spll = &rdev->clock.spll; 43 uint32_t fb_div, ref_div, post_div, sclk; 44 45 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); 46 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; 47 fb_div <<= 1; 48 fb_div *= spll->reference_freq; 49 50 ref_div = 51 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; 52 53 if (ref_div == 0) 54 return 0; 55 56 sclk = fb_div / ref_div; 57 58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; 59 if (post_div == 2) 60 sclk >>= 1; 61 else if (post_div == 3) 62 sclk >>= 2; 63 else if (post_div == 4) 64 sclk >>= 3; 65 66 return sclk; 67 } 68 69 /* 10 khz */ 70 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) 71 { 72 struct radeon_pll *mpll = &rdev->clock.mpll; 73 uint32_t fb_div, ref_div, post_div, mclk; 74 75 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); 76 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; 77 fb_div <<= 1; 78 fb_div *= mpll->reference_freq; 79 80 ref_div = 81 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; 82 83 if (ref_div == 0) 84 return 0; 85 86 mclk = fb_div / ref_div; 87 88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; 89 if (post_div == 2) 90 mclk >>= 1; 91 else if (post_div == 3) 92 mclk >>= 2; 93 else if (post_div == 4) 94 mclk >>= 3; 95 96 return mclk; 97 } 98 99 #ifdef __linux__ 100 101 #ifdef CONFIG_OF 102 /* 103 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device 104 * tree. Hopefully, ATI OF driver is kind enough to fill these 105 */ 106 static bool radeon_read_clocks_OF(struct drm_device *dev) 107 { 108 struct radeon_device *rdev = dev->dev_private; 109 struct device_node *dp = rdev->pdev->dev.of_node; 110 const u32 *val; 111 struct radeon_pll *p1pll = &rdev->clock.p1pll; 112 struct radeon_pll *p2pll = &rdev->clock.p2pll; 113 struct radeon_pll *spll = &rdev->clock.spll; 114 struct radeon_pll *mpll = &rdev->clock.mpll; 115 116 if (dp == NULL) 117 return false; 118 val = of_get_property(dp, "ATY,RefCLK", NULL); 119 if (!val || !*val) { 120 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); 121 return false; 122 } 123 p1pll->reference_freq = p2pll->reference_freq = (*val) / 10; 124 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 125 if (p1pll->reference_div < 2) 126 p1pll->reference_div = 12; 127 p2pll->reference_div = p1pll->reference_div; 128 129 /* These aren't in the device-tree */ 130 if (rdev->family >= CHIP_R420) { 131 p1pll->pll_in_min = 100; 132 p1pll->pll_in_max = 1350; 133 p1pll->pll_out_min = 20000; 134 p1pll->pll_out_max = 50000; 135 p2pll->pll_in_min = 100; 136 p2pll->pll_in_max = 1350; 137 p2pll->pll_out_min = 20000; 138 p2pll->pll_out_max = 50000; 139 } else { 140 p1pll->pll_in_min = 40; 141 p1pll->pll_in_max = 500; 142 p1pll->pll_out_min = 12500; 143 p1pll->pll_out_max = 35000; 144 p2pll->pll_in_min = 40; 145 p2pll->pll_in_max = 500; 146 p2pll->pll_out_min = 12500; 147 p2pll->pll_out_max = 35000; 148 } 149 /* not sure what the max should be in all cases */ 150 rdev->clock.max_pixel_clock = 35000; 151 152 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; 153 spll->reference_div = mpll->reference_div = 154 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & 155 RADEON_M_SPLL_REF_DIV_MASK; 156 157 val = of_get_property(dp, "ATY,SCLK", NULL); 158 if (val && *val) 159 rdev->clock.default_sclk = (*val) / 10; 160 else 161 rdev->clock.default_sclk = 162 radeon_legacy_get_engine_clock(rdev); 163 164 val = of_get_property(dp, "ATY,MCLK", NULL); 165 if (val && *val) 166 rdev->clock.default_mclk = (*val) / 10; 167 else 168 rdev->clock.default_mclk = 169 radeon_legacy_get_memory_clock(rdev); 170 171 DRM_INFO("Using device-tree clock info\n"); 172 173 return true; 174 } 175 #else 176 static bool radeon_read_clocks_OF(struct drm_device *dev) 177 { 178 return false; 179 } 180 #endif /* CONFIG_OF */ 181 182 #else 183 184 #if defined(__macppc__) || defined(__sparc64__) 185 /* 186 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device 187 * tree. Hopefully, ATI OF driver is kind enough to fill these 188 */ 189 static bool radeon_read_clocks_OF(struct drm_device *dev) 190 { 191 struct radeon_device *rdev = dev->dev_private; 192 int node = PCITAG_NODE(rdev->pa_tag); 193 uint32_t val; 194 struct radeon_pll *p1pll = &rdev->clock.p1pll; 195 struct radeon_pll *p2pll = &rdev->clock.p2pll; 196 struct radeon_pll *spll = &rdev->clock.spll; 197 struct radeon_pll *mpll = &rdev->clock.mpll; 198 199 if (OF_getprop(node, "ATY,RefCLK", &val, sizeof(val)) != sizeof(val) || !val) 200 return false; 201 p1pll->reference_freq = p2pll->reference_freq = (val) / 10; 202 p1pll->reference_div = RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 203 if (p1pll->reference_div < 2) 204 p1pll->reference_div = 12; 205 p2pll->reference_div = p1pll->reference_div; 206 207 /* These aren't in the device-tree */ 208 if (rdev->family >= CHIP_R420) { 209 p1pll->pll_in_min = 100; 210 p1pll->pll_in_max = 1350; 211 p1pll->pll_out_min = 20000; 212 p1pll->pll_out_max = 50000; 213 p2pll->pll_in_min = 100; 214 p2pll->pll_in_max = 1350; 215 p2pll->pll_out_min = 20000; 216 p2pll->pll_out_max = 50000; 217 } else { 218 p1pll->pll_in_min = 40; 219 p1pll->pll_in_max = 500; 220 p1pll->pll_out_min = 12500; 221 p1pll->pll_out_max = 35000; 222 p2pll->pll_in_min = 40; 223 p2pll->pll_in_max = 500; 224 p2pll->pll_out_min = 12500; 225 p2pll->pll_out_max = 35000; 226 } 227 /* not sure what the max should be in all cases */ 228 rdev->clock.max_pixel_clock = 35000; 229 230 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; 231 spll->reference_div = mpll->reference_div = 232 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & 233 RADEON_M_SPLL_REF_DIV_MASK; 234 235 if (OF_getprop(node, "ATY,SCLK", &val, sizeof(val)) == sizeof(val) && val) 236 rdev->clock.default_sclk = (val) / 10; 237 else 238 rdev->clock.default_sclk = 239 radeon_legacy_get_engine_clock(rdev); 240 241 if (OF_getprop(node, "ATY,MCLK", &val, sizeof(val)) == sizeof(val) && val) 242 rdev->clock.default_mclk = (val) / 10; 243 else 244 rdev->clock.default_mclk = 245 radeon_legacy_get_memory_clock(rdev); 246 247 DRM_INFO("Using device-tree clock info\n"); 248 249 return true; 250 } 251 #else 252 static bool radeon_read_clocks_OF(struct drm_device *dev) 253 { 254 return false; 255 } 256 #endif /* CONFIG_OF */ 257 258 #endif 259 260 void radeon_get_clock_info(struct drm_device *dev) 261 { 262 struct radeon_device *rdev = dev->dev_private; 263 struct radeon_pll *p1pll = &rdev->clock.p1pll; 264 struct radeon_pll *p2pll = &rdev->clock.p2pll; 265 struct radeon_pll *dcpll = &rdev->clock.dcpll; 266 struct radeon_pll *spll = &rdev->clock.spll; 267 struct radeon_pll *mpll = &rdev->clock.mpll; 268 int ret; 269 270 if (rdev->is_atom_bios) 271 ret = radeon_atom_get_clock_info(dev); 272 else 273 ret = radeon_combios_get_clock_info(dev); 274 if (!ret) 275 ret = radeon_read_clocks_OF(dev); 276 277 if (ret) { 278 if (p1pll->reference_div < 2) { 279 if (!ASIC_IS_AVIVO(rdev)) { 280 u32 tmp = RREG32_PLL(RADEON_PPLL_REF_DIV); 281 if (ASIC_IS_R300(rdev)) 282 p1pll->reference_div = 283 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; 284 else 285 p1pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; 286 if (p1pll->reference_div < 2) 287 p1pll->reference_div = 12; 288 } else 289 p1pll->reference_div = 12; 290 } 291 if (p2pll->reference_div < 2) 292 p2pll->reference_div = 12; 293 if (rdev->family < CHIP_RS600) { 294 if (spll->reference_div < 2) 295 spll->reference_div = 296 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & 297 RADEON_M_SPLL_REF_DIV_MASK; 298 } 299 if (mpll->reference_div < 2) 300 mpll->reference_div = spll->reference_div; 301 } else { 302 if (ASIC_IS_AVIVO(rdev)) { 303 /* TODO FALLBACK */ 304 } else { 305 DRM_INFO("Using generic clock info\n"); 306 307 /* may need to be per card */ 308 rdev->clock.max_pixel_clock = 35000; 309 310 if (rdev->flags & RADEON_IS_IGP) { 311 p1pll->reference_freq = 1432; 312 p2pll->reference_freq = 1432; 313 spll->reference_freq = 1432; 314 mpll->reference_freq = 1432; 315 } else { 316 p1pll->reference_freq = 2700; 317 p2pll->reference_freq = 2700; 318 spll->reference_freq = 2700; 319 mpll->reference_freq = 2700; 320 } 321 p1pll->reference_div = 322 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 323 if (p1pll->reference_div < 2) 324 p1pll->reference_div = 12; 325 p2pll->reference_div = p1pll->reference_div; 326 327 if (rdev->family >= CHIP_R420) { 328 p1pll->pll_in_min = 100; 329 p1pll->pll_in_max = 1350; 330 p1pll->pll_out_min = 20000; 331 p1pll->pll_out_max = 50000; 332 p2pll->pll_in_min = 100; 333 p2pll->pll_in_max = 1350; 334 p2pll->pll_out_min = 20000; 335 p2pll->pll_out_max = 50000; 336 } else { 337 p1pll->pll_in_min = 40; 338 p1pll->pll_in_max = 500; 339 p1pll->pll_out_min = 12500; 340 p1pll->pll_out_max = 35000; 341 p2pll->pll_in_min = 40; 342 p2pll->pll_in_max = 500; 343 p2pll->pll_out_min = 12500; 344 p2pll->pll_out_max = 35000; 345 } 346 347 spll->reference_div = 348 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & 349 RADEON_M_SPLL_REF_DIV_MASK; 350 mpll->reference_div = spll->reference_div; 351 rdev->clock.default_sclk = 352 radeon_legacy_get_engine_clock(rdev); 353 rdev->clock.default_mclk = 354 radeon_legacy_get_memory_clock(rdev); 355 } 356 } 357 358 /* pixel clocks */ 359 if (ASIC_IS_AVIVO(rdev)) { 360 p1pll->min_post_div = 2; 361 p1pll->max_post_div = 0x7f; 362 p1pll->min_frac_feedback_div = 0; 363 p1pll->max_frac_feedback_div = 9; 364 p2pll->min_post_div = 2; 365 p2pll->max_post_div = 0x7f; 366 p2pll->min_frac_feedback_div = 0; 367 p2pll->max_frac_feedback_div = 9; 368 } else { 369 p1pll->min_post_div = 1; 370 p1pll->max_post_div = 16; 371 p1pll->min_frac_feedback_div = 0; 372 p1pll->max_frac_feedback_div = 0; 373 p2pll->min_post_div = 1; 374 p2pll->max_post_div = 12; 375 p2pll->min_frac_feedback_div = 0; 376 p2pll->max_frac_feedback_div = 0; 377 } 378 379 /* dcpll is DCE4 only */ 380 dcpll->min_post_div = 2; 381 dcpll->max_post_div = 0x7f; 382 dcpll->min_frac_feedback_div = 0; 383 dcpll->max_frac_feedback_div = 9; 384 dcpll->min_ref_div = 2; 385 dcpll->max_ref_div = 0x3ff; 386 dcpll->min_feedback_div = 4; 387 dcpll->max_feedback_div = 0xfff; 388 dcpll->best_vco = 0; 389 390 p1pll->min_ref_div = 2; 391 p1pll->max_ref_div = 0x3ff; 392 p1pll->min_feedback_div = 4; 393 p1pll->max_feedback_div = 0x7ff; 394 p1pll->best_vco = 0; 395 396 p2pll->min_ref_div = 2; 397 p2pll->max_ref_div = 0x3ff; 398 p2pll->min_feedback_div = 4; 399 p2pll->max_feedback_div = 0x7ff; 400 p2pll->best_vco = 0; 401 402 /* system clock */ 403 spll->min_post_div = 1; 404 spll->max_post_div = 1; 405 spll->min_ref_div = 2; 406 spll->max_ref_div = 0xff; 407 spll->min_feedback_div = 4; 408 spll->max_feedback_div = 0xff; 409 spll->best_vco = 0; 410 411 /* memory clock */ 412 mpll->min_post_div = 1; 413 mpll->max_post_div = 1; 414 mpll->min_ref_div = 2; 415 mpll->max_ref_div = 0xff; 416 mpll->min_feedback_div = 4; 417 mpll->max_feedback_div = 0xff; 418 mpll->best_vco = 0; 419 420 if (!rdev->clock.default_sclk) 421 rdev->clock.default_sclk = radeon_get_engine_clock(rdev); 422 if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock) 423 rdev->clock.default_mclk = radeon_get_memory_clock(rdev); 424 425 rdev->pm.current_sclk = rdev->clock.default_sclk; 426 rdev->pm.current_mclk = rdev->clock.default_mclk; 427 428 } 429 430 /* 10 khz */ 431 static uint32_t calc_eng_mem_clock(struct radeon_device *rdev, 432 uint32_t req_clock, 433 int *fb_div, int *post_div) 434 { 435 struct radeon_pll *spll = &rdev->clock.spll; 436 int ref_div = spll->reference_div; 437 438 if (!ref_div) 439 ref_div = 440 RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & 441 RADEON_M_SPLL_REF_DIV_MASK; 442 443 if (req_clock < 15000) { 444 *post_div = 8; 445 req_clock *= 8; 446 } else if (req_clock < 30000) { 447 *post_div = 4; 448 req_clock *= 4; 449 } else if (req_clock < 60000) { 450 *post_div = 2; 451 req_clock *= 2; 452 } else 453 *post_div = 1; 454 455 req_clock *= ref_div; 456 req_clock += spll->reference_freq; 457 req_clock /= (2 * spll->reference_freq); 458 459 *fb_div = req_clock & 0xff; 460 461 req_clock = (req_clock & 0xffff) << 1; 462 req_clock *= spll->reference_freq; 463 req_clock /= ref_div; 464 req_clock /= *post_div; 465 466 return req_clock; 467 } 468 469 /* 10 khz */ 470 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, 471 uint32_t eng_clock) 472 { 473 uint32_t tmp; 474 int fb_div, post_div; 475 476 /* XXX: wait for idle */ 477 478 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); 479 480 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); 481 tmp &= ~RADEON_DONT_USE_XTALIN; 482 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); 483 484 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 485 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; 486 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 487 488 udelay(10); 489 490 tmp = RREG32_PLL(RADEON_SPLL_CNTL); 491 tmp |= RADEON_SPLL_SLEEP; 492 WREG32_PLL(RADEON_SPLL_CNTL, tmp); 493 494 udelay(2); 495 496 tmp = RREG32_PLL(RADEON_SPLL_CNTL); 497 tmp |= RADEON_SPLL_RESET; 498 WREG32_PLL(RADEON_SPLL_CNTL, tmp); 499 500 udelay(200); 501 502 tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); 503 tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); 504 tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; 505 WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); 506 507 /* XXX: verify on different asics */ 508 tmp = RREG32_PLL(RADEON_SPLL_CNTL); 509 tmp &= ~RADEON_SPLL_PVG_MASK; 510 if ((eng_clock * post_div) >= 90000) 511 tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); 512 else 513 tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); 514 WREG32_PLL(RADEON_SPLL_CNTL, tmp); 515 516 tmp = RREG32_PLL(RADEON_SPLL_CNTL); 517 tmp &= ~RADEON_SPLL_SLEEP; 518 WREG32_PLL(RADEON_SPLL_CNTL, tmp); 519 520 udelay(2); 521 522 tmp = RREG32_PLL(RADEON_SPLL_CNTL); 523 tmp &= ~RADEON_SPLL_RESET; 524 WREG32_PLL(RADEON_SPLL_CNTL, tmp); 525 526 udelay(200); 527 528 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 529 tmp &= ~RADEON_SCLK_SRC_SEL_MASK; 530 switch (post_div) { 531 case 1: 532 default: 533 tmp |= 1; 534 break; 535 case 2: 536 tmp |= 2; 537 break; 538 case 4: 539 tmp |= 3; 540 break; 541 case 8: 542 tmp |= 4; 543 break; 544 } 545 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 546 547 udelay(20); 548 549 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); 550 tmp |= RADEON_DONT_USE_XTALIN; 551 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); 552 553 udelay(10); 554 } 555 556 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) 557 { 558 uint32_t tmp; 559 560 if (enable) { 561 if (rdev->flags & RADEON_SINGLE_CRTC) { 562 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 563 if ((RREG32(RADEON_CONFIG_CNTL) & 564 RADEON_CFG_ATI_REV_ID_MASK) > 565 RADEON_CFG_ATI_REV_A13) { 566 tmp &= 567 ~(RADEON_SCLK_FORCE_CP | 568 RADEON_SCLK_FORCE_RB); 569 } 570 tmp &= 571 ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 572 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | 573 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | 574 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | 575 RADEON_SCLK_FORCE_TDM); 576 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 577 } else if (ASIC_IS_R300(rdev)) { 578 if ((rdev->family == CHIP_RS400) || 579 (rdev->family == CHIP_RS480)) { 580 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 581 tmp &= 582 ~(RADEON_SCLK_FORCE_DISP2 | 583 RADEON_SCLK_FORCE_CP | 584 RADEON_SCLK_FORCE_HDP | 585 RADEON_SCLK_FORCE_DISP1 | 586 RADEON_SCLK_FORCE_TOP | 587 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP 588 | RADEON_SCLK_FORCE_IDCT | 589 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR 590 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX 591 | R300_SCLK_FORCE_US | 592 RADEON_SCLK_FORCE_TV_SCLK | 593 R300_SCLK_FORCE_SU | 594 RADEON_SCLK_FORCE_OV0); 595 tmp |= RADEON_DYN_STOP_LAT_MASK; 596 tmp |= 597 RADEON_SCLK_FORCE_TOP | 598 RADEON_SCLK_FORCE_VIP; 599 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 600 601 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); 602 tmp &= ~RADEON_SCLK_MORE_FORCEON; 603 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; 604 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); 605 606 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 607 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 608 RADEON_PIXCLK_DAC_ALWAYS_ONb); 609 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 610 611 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); 612 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 613 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 614 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 615 R300_DVOCLK_ALWAYS_ONb | 616 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 617 RADEON_PIXCLK_GV_ALWAYS_ONb | 618 R300_PIXCLK_DVO_ALWAYS_ONb | 619 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 620 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 621 R300_PIXCLK_TRANS_ALWAYS_ONb | 622 R300_PIXCLK_TVO_ALWAYS_ONb | 623 R300_P2G2CLK_ALWAYS_ONb | 624 R300_P2G2CLK_DAC_ALWAYS_ONb); 625 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 626 } else if (rdev->family >= CHIP_RV350) { 627 tmp = RREG32_PLL(R300_SCLK_CNTL2); 628 tmp &= ~(R300_SCLK_FORCE_TCL | 629 R300_SCLK_FORCE_GA | 630 R300_SCLK_FORCE_CBA); 631 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | 632 R300_SCLK_GA_MAX_DYN_STOP_LAT | 633 R300_SCLK_CBA_MAX_DYN_STOP_LAT); 634 WREG32_PLL(R300_SCLK_CNTL2, tmp); 635 636 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 637 tmp &= 638 ~(RADEON_SCLK_FORCE_DISP2 | 639 RADEON_SCLK_FORCE_CP | 640 RADEON_SCLK_FORCE_HDP | 641 RADEON_SCLK_FORCE_DISP1 | 642 RADEON_SCLK_FORCE_TOP | 643 RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP 644 | RADEON_SCLK_FORCE_IDCT | 645 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR 646 | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX 647 | R300_SCLK_FORCE_US | 648 RADEON_SCLK_FORCE_TV_SCLK | 649 R300_SCLK_FORCE_SU | 650 RADEON_SCLK_FORCE_OV0); 651 tmp |= RADEON_DYN_STOP_LAT_MASK; 652 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 653 654 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); 655 tmp &= ~RADEON_SCLK_MORE_FORCEON; 656 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; 657 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); 658 659 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 660 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 661 RADEON_PIXCLK_DAC_ALWAYS_ONb); 662 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 663 664 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); 665 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 666 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 667 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 668 R300_DVOCLK_ALWAYS_ONb | 669 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 670 RADEON_PIXCLK_GV_ALWAYS_ONb | 671 R300_PIXCLK_DVO_ALWAYS_ONb | 672 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 673 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 674 R300_PIXCLK_TRANS_ALWAYS_ONb | 675 R300_PIXCLK_TVO_ALWAYS_ONb | 676 R300_P2G2CLK_ALWAYS_ONb | 677 R300_P2G2CLK_DAC_ALWAYS_ONb); 678 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 679 680 tmp = RREG32_PLL(RADEON_MCLK_MISC); 681 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | 682 RADEON_IO_MCLK_DYN_ENABLE); 683 WREG32_PLL(RADEON_MCLK_MISC, tmp); 684 685 tmp = RREG32_PLL(RADEON_MCLK_CNTL); 686 tmp |= (RADEON_FORCEON_MCLKA | 687 RADEON_FORCEON_MCLKB); 688 689 tmp &= ~(RADEON_FORCEON_YCLKA | 690 RADEON_FORCEON_YCLKB | 691 RADEON_FORCEON_MC); 692 693 /* Some releases of vbios have set DISABLE_MC_MCLKA 694 and DISABLE_MC_MCLKB bits in the vbios table. Setting these 695 bits will cause H/W hang when reading video memory with dynamic clocking 696 enabled. */ 697 if ((tmp & R300_DISABLE_MC_MCLKA) && 698 (tmp & R300_DISABLE_MC_MCLKB)) { 699 /* If both bits are set, then check the active channels */ 700 tmp = RREG32_PLL(RADEON_MCLK_CNTL); 701 if (rdev->mc.vram_width == 64) { 702 if (RREG32(RADEON_MEM_CNTL) & 703 R300_MEM_USE_CD_CH_ONLY) 704 tmp &= 705 ~R300_DISABLE_MC_MCLKB; 706 else 707 tmp &= 708 ~R300_DISABLE_MC_MCLKA; 709 } else { 710 tmp &= ~(R300_DISABLE_MC_MCLKA | 711 R300_DISABLE_MC_MCLKB); 712 } 713 } 714 715 WREG32_PLL(RADEON_MCLK_CNTL, tmp); 716 } else { 717 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 718 tmp &= ~(R300_SCLK_FORCE_VAP); 719 tmp |= RADEON_SCLK_FORCE_CP; 720 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 721 mdelay(15); 722 723 tmp = RREG32_PLL(R300_SCLK_CNTL2); 724 tmp &= ~(R300_SCLK_FORCE_TCL | 725 R300_SCLK_FORCE_GA | 726 R300_SCLK_FORCE_CBA); 727 WREG32_PLL(R300_SCLK_CNTL2, tmp); 728 } 729 } else { 730 tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 731 732 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | 733 RADEON_DISP_DYN_STOP_LAT_MASK | 734 RADEON_DYN_STOP_MODE_MASK); 735 736 tmp |= (RADEON_ENGIN_DYNCLK_MODE | 737 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); 738 WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); 739 mdelay(15); 740 741 tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); 742 tmp |= RADEON_SCLK_DYN_START_CNTL; 743 WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); 744 mdelay(15); 745 746 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 747 to lockup randomly, leave them as set by BIOS. 748 */ 749 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 750 /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */ 751 tmp &= ~RADEON_SCLK_FORCEON_MASK; 752 753 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */ 754 if (((rdev->family == CHIP_RV250) && 755 ((RREG32(RADEON_CONFIG_CNTL) & 756 RADEON_CFG_ATI_REV_ID_MASK) < 757 RADEON_CFG_ATI_REV_A13)) 758 || ((rdev->family == CHIP_RV100) 759 && 760 ((RREG32(RADEON_CONFIG_CNTL) & 761 RADEON_CFG_ATI_REV_ID_MASK) <= 762 RADEON_CFG_ATI_REV_A13))) { 763 tmp |= RADEON_SCLK_FORCE_CP; 764 tmp |= RADEON_SCLK_FORCE_VIP; 765 } 766 767 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 768 769 if ((rdev->family == CHIP_RV200) || 770 (rdev->family == CHIP_RV250) || 771 (rdev->family == CHIP_RV280)) { 772 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); 773 tmp &= ~RADEON_SCLK_MORE_FORCEON; 774 775 /* RV200::A11 A12 RV250::A11 A12 */ 776 if (((rdev->family == CHIP_RV200) || 777 (rdev->family == CHIP_RV250)) && 778 ((RREG32(RADEON_CONFIG_CNTL) & 779 RADEON_CFG_ATI_REV_ID_MASK) < 780 RADEON_CFG_ATI_REV_A13)) { 781 tmp |= RADEON_SCLK_MORE_FORCEON; 782 } 783 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); 784 mdelay(15); 785 } 786 787 /* RV200::A11 A12, RV250::A11 A12 */ 788 if (((rdev->family == CHIP_RV200) || 789 (rdev->family == CHIP_RV250)) && 790 ((RREG32(RADEON_CONFIG_CNTL) & 791 RADEON_CFG_ATI_REV_ID_MASK) < 792 RADEON_CFG_ATI_REV_A13)) { 793 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 794 tmp |= RADEON_TCL_BYPASS_DISABLE; 795 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 796 } 797 mdelay(15); 798 799 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ 800 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); 801 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 802 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 803 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 804 RADEON_PIXCLK_GV_ALWAYS_ONb | 805 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 806 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 807 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 808 809 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 810 mdelay(15); 811 812 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 813 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 814 RADEON_PIXCLK_DAC_ALWAYS_ONb); 815 816 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 817 mdelay(15); 818 } 819 } else { 820 /* Turn everything OFF (ForceON to everything) */ 821 if (rdev->flags & RADEON_SINGLE_CRTC) { 822 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 823 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | 824 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP 825 | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | 826 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | 827 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | 828 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | 829 RADEON_SCLK_FORCE_RB); 830 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 831 } else if ((rdev->family == CHIP_RS400) || 832 (rdev->family == CHIP_RS480)) { 833 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 834 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 835 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 836 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 837 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 838 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 839 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 840 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 841 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 842 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 843 844 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); 845 tmp |= RADEON_SCLK_MORE_FORCEON; 846 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); 847 848 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 849 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 850 RADEON_PIXCLK_DAC_ALWAYS_ONb | 851 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); 852 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 853 854 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); 855 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 856 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 857 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 858 R300_DVOCLK_ALWAYS_ONb | 859 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 860 RADEON_PIXCLK_GV_ALWAYS_ONb | 861 R300_PIXCLK_DVO_ALWAYS_ONb | 862 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 863 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 864 R300_PIXCLK_TRANS_ALWAYS_ONb | 865 R300_PIXCLK_TVO_ALWAYS_ONb | 866 R300_P2G2CLK_ALWAYS_ONb | 867 R300_P2G2CLK_DAC_ALWAYS_ONb | 868 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); 869 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 870 } else if (rdev->family >= CHIP_RV350) { 871 /* for RV350/M10, no delays are required. */ 872 tmp = RREG32_PLL(R300_SCLK_CNTL2); 873 tmp |= (R300_SCLK_FORCE_TCL | 874 R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA); 875 WREG32_PLL(R300_SCLK_CNTL2, tmp); 876 877 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 878 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 879 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 880 | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 881 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 882 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 883 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 884 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 885 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 886 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 887 888 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); 889 tmp |= RADEON_SCLK_MORE_FORCEON; 890 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); 891 892 tmp = RREG32_PLL(RADEON_MCLK_CNTL); 893 tmp |= (RADEON_FORCEON_MCLKA | 894 RADEON_FORCEON_MCLKB | 895 RADEON_FORCEON_YCLKA | 896 RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC); 897 WREG32_PLL(RADEON_MCLK_CNTL, tmp); 898 899 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 900 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 901 RADEON_PIXCLK_DAC_ALWAYS_ONb | 902 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); 903 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 904 905 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); 906 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 907 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 908 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 909 R300_DVOCLK_ALWAYS_ONb | 910 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 911 RADEON_PIXCLK_GV_ALWAYS_ONb | 912 R300_PIXCLK_DVO_ALWAYS_ONb | 913 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 914 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 915 R300_PIXCLK_TRANS_ALWAYS_ONb | 916 R300_PIXCLK_TVO_ALWAYS_ONb | 917 R300_P2G2CLK_ALWAYS_ONb | 918 R300_P2G2CLK_DAC_ALWAYS_ONb | 919 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); 920 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 921 } else { 922 tmp = RREG32_PLL(RADEON_SCLK_CNTL); 923 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); 924 tmp |= RADEON_SCLK_FORCE_SE; 925 926 if (rdev->flags & RADEON_SINGLE_CRTC) { 927 tmp |= (RADEON_SCLK_FORCE_RB | 928 RADEON_SCLK_FORCE_TDM | 929 RADEON_SCLK_FORCE_TAM | 930 RADEON_SCLK_FORCE_PB | 931 RADEON_SCLK_FORCE_RE | 932 RADEON_SCLK_FORCE_VIP | 933 RADEON_SCLK_FORCE_IDCT | 934 RADEON_SCLK_FORCE_TOP | 935 RADEON_SCLK_FORCE_DISP1 | 936 RADEON_SCLK_FORCE_DISP2 | 937 RADEON_SCLK_FORCE_HDP); 938 } else if ((rdev->family == CHIP_R300) || 939 (rdev->family == CHIP_R350)) { 940 tmp |= (RADEON_SCLK_FORCE_HDP | 941 RADEON_SCLK_FORCE_DISP1 | 942 RADEON_SCLK_FORCE_DISP2 | 943 RADEON_SCLK_FORCE_TOP | 944 RADEON_SCLK_FORCE_IDCT | 945 RADEON_SCLK_FORCE_VIP); 946 } 947 WREG32_PLL(RADEON_SCLK_CNTL, tmp); 948 949 mdelay(16); 950 951 if ((rdev->family == CHIP_R300) || 952 (rdev->family == CHIP_R350)) { 953 tmp = RREG32_PLL(R300_SCLK_CNTL2); 954 tmp |= (R300_SCLK_FORCE_TCL | 955 R300_SCLK_FORCE_GA | 956 R300_SCLK_FORCE_CBA); 957 WREG32_PLL(R300_SCLK_CNTL2, tmp); 958 mdelay(16); 959 } 960 961 if (rdev->flags & RADEON_IS_IGP) { 962 tmp = RREG32_PLL(RADEON_MCLK_CNTL); 963 tmp &= ~(RADEON_FORCEON_MCLKA | 964 RADEON_FORCEON_YCLKA); 965 WREG32_PLL(RADEON_MCLK_CNTL, tmp); 966 mdelay(16); 967 } 968 969 if ((rdev->family == CHIP_RV200) || 970 (rdev->family == CHIP_RV250) || 971 (rdev->family == CHIP_RV280)) { 972 tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); 973 tmp |= RADEON_SCLK_MORE_FORCEON; 974 WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); 975 mdelay(16); 976 } 977 978 tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); 979 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 980 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 981 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 982 RADEON_PIXCLK_GV_ALWAYS_ONb | 983 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 984 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 985 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 986 987 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 988 mdelay(16); 989 990 tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 991 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 992 RADEON_PIXCLK_DAC_ALWAYS_ONb); 993 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 994 } 995 } 996 } 997 998