1 /* $OpenBSD: radeon_device.c,v 1.13 2015/04/12 03:54:10 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include <dev/pci/drm/drm_crtc_helper.h> 31 #include <dev/pci/drm/radeon_drm.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "atom.h" 35 36 static const char radeon_family_name[][16] = { 37 "R100", 38 "RV100", 39 "RS100", 40 "RV200", 41 "RS200", 42 "R200", 43 "RV250", 44 "RS300", 45 "RV280", 46 "R300", 47 "R350", 48 "RV350", 49 "RV380", 50 "R420", 51 "R423", 52 "RV410", 53 "RS400", 54 "RS480", 55 "RS600", 56 "RS690", 57 "RS740", 58 "RV515", 59 "R520", 60 "RV530", 61 "RV560", 62 "RV570", 63 "R580", 64 "R600", 65 "RV610", 66 "RV630", 67 "RV670", 68 "RV620", 69 "RV635", 70 "RS780", 71 "RS880", 72 "RV770", 73 "RV730", 74 "RV710", 75 "RV740", 76 "CEDAR", 77 "REDWOOD", 78 "JUNIPER", 79 "CYPRESS", 80 "HEMLOCK", 81 "PALM", 82 "SUMO", 83 "SUMO2", 84 "BARTS", 85 "TURKS", 86 "CAICOS", 87 "CAYMAN", 88 "ARUBA", 89 "TAHITI", 90 "PITCAIRN", 91 "VERDE", 92 "LAST", 93 }; 94 95 /** 96 * radeon_surface_init - Clear GPU surface registers. 97 * 98 * @rdev: radeon_device pointer 99 * 100 * Clear GPU surface registers (r1xx-r5xx). 101 */ 102 void radeon_surface_init(struct radeon_device *rdev) 103 { 104 /* FIXME: check this out */ 105 if (rdev->family < CHIP_R600) { 106 int i; 107 108 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 109 if (rdev->surface_regs[i].bo) 110 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 111 else 112 radeon_clear_surface_reg(rdev, i); 113 } 114 /* enable surfaces */ 115 WREG32(RADEON_SURFACE_CNTL, 0); 116 } 117 } 118 119 /* 120 * GPU scratch registers helpers function. 121 */ 122 /** 123 * radeon_scratch_init - Init scratch register driver information. 124 * 125 * @rdev: radeon_device pointer 126 * 127 * Init CP scratch register driver information (r1xx-r5xx) 128 */ 129 void radeon_scratch_init(struct radeon_device *rdev) 130 { 131 int i; 132 133 /* FIXME: check this out */ 134 if (rdev->family < CHIP_R300) { 135 rdev->scratch.num_reg = 5; 136 } else { 137 rdev->scratch.num_reg = 7; 138 } 139 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 140 for (i = 0; i < rdev->scratch.num_reg; i++) { 141 rdev->scratch.free[i] = true; 142 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 143 } 144 } 145 146 /** 147 * radeon_scratch_get - Allocate a scratch register 148 * 149 * @rdev: radeon_device pointer 150 * @reg: scratch register mmio offset 151 * 152 * Allocate a CP scratch register for use by the driver (all asics). 153 * Returns 0 on success or -EINVAL on failure. 154 */ 155 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 156 { 157 int i; 158 159 for (i = 0; i < rdev->scratch.num_reg; i++) { 160 if (rdev->scratch.free[i]) { 161 rdev->scratch.free[i] = false; 162 *reg = rdev->scratch.reg[i]; 163 return 0; 164 } 165 } 166 return -EINVAL; 167 } 168 169 /** 170 * radeon_scratch_free - Free a scratch register 171 * 172 * @rdev: radeon_device pointer 173 * @reg: scratch register mmio offset 174 * 175 * Free a CP scratch register allocated for use by the driver (all asics) 176 */ 177 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 178 { 179 int i; 180 181 for (i = 0; i < rdev->scratch.num_reg; i++) { 182 if (rdev->scratch.reg[i] == reg) { 183 rdev->scratch.free[i] = true; 184 return; 185 } 186 } 187 } 188 189 /* 190 * radeon_wb_*() 191 * Writeback is the the method by which the the GPU updates special pages 192 * in memory with the status of certain GPU events (fences, ring pointers, 193 * etc.). 194 */ 195 196 /** 197 * radeon_wb_disable - Disable Writeback 198 * 199 * @rdev: radeon_device pointer 200 * 201 * Disables Writeback (all asics). Used for suspend. 202 */ 203 void radeon_wb_disable(struct radeon_device *rdev) 204 { 205 int r; 206 207 if (rdev->wb.wb_obj) { 208 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 209 if (unlikely(r != 0)) 210 return; 211 radeon_bo_kunmap(rdev->wb.wb_obj); 212 radeon_bo_unpin(rdev->wb.wb_obj); 213 radeon_bo_unreserve(rdev->wb.wb_obj); 214 } 215 rdev->wb.enabled = false; 216 } 217 218 /** 219 * radeon_wb_fini - Disable Writeback and free memory 220 * 221 * @rdev: radeon_device pointer 222 * 223 * Disables Writeback and frees the Writeback memory (all asics). 224 * Used at driver shutdown. 225 */ 226 void radeon_wb_fini(struct radeon_device *rdev) 227 { 228 radeon_wb_disable(rdev); 229 if (rdev->wb.wb_obj) { 230 radeon_bo_unref(&rdev->wb.wb_obj); 231 rdev->wb.wb = NULL; 232 rdev->wb.wb_obj = NULL; 233 } 234 } 235 236 /** 237 * radeon_wb_init- Init Writeback driver info and allocate memory 238 * 239 * @rdev: radeon_device pointer 240 * 241 * Disables Writeback and frees the Writeback memory (all asics). 242 * Used at driver startup. 243 * Returns 0 on success or an -error on failure. 244 */ 245 int radeon_wb_init(struct radeon_device *rdev) 246 { 247 int r; 248 249 if (rdev->wb.wb_obj == NULL) { 250 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 251 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); 252 if (r) { 253 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 254 return r; 255 } 256 } 257 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 258 if (unlikely(r != 0)) { 259 radeon_wb_fini(rdev); 260 return r; 261 } 262 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 263 &rdev->wb.gpu_addr); 264 if (r) { 265 radeon_bo_unreserve(rdev->wb.wb_obj); 266 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 267 radeon_wb_fini(rdev); 268 return r; 269 } 270 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 271 radeon_bo_unreserve(rdev->wb.wb_obj); 272 if (r) { 273 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 274 radeon_wb_fini(rdev); 275 return r; 276 } 277 278 /* clear wb memory */ 279 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); 280 /* disable event_write fences */ 281 rdev->wb.use_event = false; 282 /* disabled via module param */ 283 if (radeon_no_wb == 1) { 284 rdev->wb.enabled = false; 285 } else { 286 if (rdev->flags & RADEON_IS_AGP) { 287 /* often unreliable on AGP */ 288 rdev->wb.enabled = false; 289 } else if (rdev->family < CHIP_R300) { 290 /* often unreliable on pre-r300 */ 291 rdev->wb.enabled = false; 292 } else { 293 rdev->wb.enabled = true; 294 /* event_write fences are only available on r600+ */ 295 if (rdev->family >= CHIP_R600) { 296 rdev->wb.use_event = true; 297 } 298 } 299 } 300 /* always use writeback/events on NI, APUs */ 301 if (rdev->family >= CHIP_PALM) { 302 rdev->wb.enabled = true; 303 rdev->wb.use_event = true; 304 } 305 306 #ifdef DRMDEBUG 307 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 308 #endif 309 310 return 0; 311 } 312 313 /** 314 * radeon_vram_location - try to find VRAM location 315 * @rdev: radeon device structure holding all necessary informations 316 * @mc: memory controller structure holding memory informations 317 * @base: base address at which to put VRAM 318 * 319 * Function will place try to place VRAM at base address provided 320 * as parameter (which is so far either PCI aperture address or 321 * for IGP TOM base address). 322 * 323 * If there is not enough space to fit the unvisible VRAM in the 32bits 324 * address space then we limit the VRAM size to the aperture. 325 * 326 * If we are using AGP and if the AGP aperture doesn't allow us to have 327 * room for all the VRAM than we restrict the VRAM to the PCI aperture 328 * size and print a warning. 329 * 330 * This function will never fails, worst case are limiting VRAM. 331 * 332 * Note: GTT start, end, size should be initialized before calling this 333 * function on AGP platform. 334 * 335 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 336 * this shouldn't be a problem as we are using the PCI aperture as a reference. 337 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 338 * not IGP. 339 * 340 * Note: we use mc_vram_size as on some board we need to program the mc to 341 * cover the whole aperture even if VRAM size is inferior to aperture size 342 * Novell bug 204882 + along with lots of ubuntu ones 343 * 344 * Note: when limiting vram it's safe to overwritte real_vram_size because 345 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 346 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 347 * ones) 348 * 349 * Note: IGP TOM addr should be the same as the aperture addr, we don't 350 * explicitly check for that thought. 351 * 352 * FIXME: when reducing VRAM size align new size on power of 2. 353 */ 354 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 355 { 356 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 357 358 mc->vram_start = base; 359 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { 360 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 361 mc->real_vram_size = mc->aper_size; 362 mc->mc_vram_size = mc->aper_size; 363 } 364 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 365 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 366 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 367 mc->real_vram_size = mc->aper_size; 368 mc->mc_vram_size = mc->aper_size; 369 } 370 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 371 if (limit && limit < mc->real_vram_size) 372 mc->real_vram_size = limit; 373 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 374 mc->mc_vram_size >> 20, mc->vram_start, 375 mc->vram_end, mc->real_vram_size >> 20); 376 } 377 378 /** 379 * radeon_gtt_location - try to find GTT location 380 * @rdev: radeon device structure holding all necessary informations 381 * @mc: memory controller structure holding memory informations 382 * 383 * Function will place try to place GTT before or after VRAM. 384 * 385 * If GTT size is bigger than space left then we ajust GTT size. 386 * Thus function will never fails. 387 * 388 * FIXME: when reducing GTT size align new size on power of 2. 389 */ 390 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 391 { 392 u64 size_af, size_bf; 393 394 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 395 size_bf = mc->vram_start & ~mc->gtt_base_align; 396 if (size_bf > size_af) { 397 if (mc->gtt_size > size_bf) { 398 dev_warn(rdev->dev, "limiting GTT\n"); 399 mc->gtt_size = size_bf; 400 } 401 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 402 } else { 403 if (mc->gtt_size > size_af) { 404 dev_warn(rdev->dev, "limiting GTT\n"); 405 mc->gtt_size = size_af; 406 } 407 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 408 } 409 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 410 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 411 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 412 } 413 414 /* 415 * GPU helpers function. 416 */ 417 /** 418 * radeon_card_posted - check if the hw has already been initialized 419 * 420 * @rdev: radeon_device pointer 421 * 422 * Check if the asic has been initialized (all asics). 423 * Used at driver startup. 424 * Returns true if initialized or false if not. 425 */ 426 bool radeon_card_posted(struct radeon_device *rdev) 427 { 428 uint32_t reg; 429 430 #ifdef notyet 431 if (efi_enabled(EFI_BOOT) && 432 rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) 433 return false; 434 #endif 435 436 /* first check CRTCs */ 437 if (ASIC_IS_DCE4(rdev)) { 438 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 439 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 440 if (rdev->num_crtc >= 4) { 441 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 442 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 443 } 444 if (rdev->num_crtc >= 6) { 445 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 446 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 447 } 448 if (reg & EVERGREEN_CRTC_MASTER_EN) 449 return true; 450 } else if (ASIC_IS_AVIVO(rdev)) { 451 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 452 RREG32(AVIVO_D2CRTC_CONTROL); 453 if (reg & AVIVO_CRTC_EN) { 454 return true; 455 } 456 } else { 457 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 458 RREG32(RADEON_CRTC2_GEN_CNTL); 459 if (reg & RADEON_CRTC_EN) { 460 return true; 461 } 462 } 463 464 /* then check MEM_SIZE, in case the crtcs are off */ 465 if (rdev->family >= CHIP_R600) 466 reg = RREG32(R600_CONFIG_MEMSIZE); 467 else 468 reg = RREG32(RADEON_CONFIG_MEMSIZE); 469 470 if (reg) 471 return true; 472 473 return false; 474 475 } 476 477 /** 478 * radeon_update_bandwidth_info - update display bandwidth params 479 * 480 * @rdev: radeon_device pointer 481 * 482 * Used when sclk/mclk are switched or display modes are set. 483 * params are used to calculate display watermarks (all asics) 484 */ 485 void radeon_update_bandwidth_info(struct radeon_device *rdev) 486 { 487 fixed20_12 a; 488 u32 sclk = rdev->pm.current_sclk; 489 u32 mclk = rdev->pm.current_mclk; 490 491 /* sclk/mclk in Mhz */ 492 a.full = dfixed_const(100); 493 rdev->pm.sclk.full = dfixed_const(sclk); 494 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 495 rdev->pm.mclk.full = dfixed_const(mclk); 496 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 497 498 if (rdev->flags & RADEON_IS_IGP) { 499 a.full = dfixed_const(16); 500 /* core_bandwidth = sclk(Mhz) * 16 */ 501 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 502 } 503 } 504 505 /** 506 * radeon_boot_test_post_card - check and possibly initialize the hw 507 * 508 * @rdev: radeon_device pointer 509 * 510 * Check if the asic is initialized and if not, attempt to initialize 511 * it (all asics). 512 * Returns true if initialized or false if not. 513 */ 514 bool radeon_boot_test_post_card(struct radeon_device *rdev) 515 { 516 if (radeon_card_posted(rdev)) 517 return true; 518 519 if (rdev->bios) { 520 DRM_INFO("GPU not posted. posting now...\n"); 521 if (rdev->is_atom_bios) 522 atom_asic_init(rdev->mode_info.atom_context); 523 else 524 radeon_combios_asic_init(rdev->ddev); 525 return true; 526 } else { 527 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 528 return false; 529 } 530 } 531 532 /** 533 * radeon_dummy_page_init - init dummy page used by the driver 534 * 535 * @rdev: radeon_device pointer 536 * 537 * Allocate the dummy page used by the driver (all asics). 538 * This dummy page is used by the driver as a filler for gart entries 539 * when pages are taken out of the GART 540 * Returns 0 on sucess, -ENOMEM on failure. 541 */ 542 int radeon_dummy_page_init(struct radeon_device *rdev) 543 { 544 if (rdev->dummy_page.dmah) 545 return 0; 546 rdev->dummy_page.dmah = drm_dmamem_alloc(rdev->dmat, PAGE_SIZE, PAGE_SIZE, 1, 547 PAGE_SIZE, 0, BUS_DMA_WAITOK); 548 if (!rdev->dummy_page.dmah) 549 return -ENOMEM; 550 rdev->dummy_page.addr = (bus_addr_t)rdev->dummy_page.dmah->map->dm_segs[0].ds_addr; 551 return 0; 552 } 553 554 /** 555 * radeon_dummy_page_fini - free dummy page used by the driver 556 * 557 * @rdev: radeon_device pointer 558 * 559 * Frees the dummy page used by the driver (all asics). 560 */ 561 void radeon_dummy_page_fini(struct radeon_device *rdev) 562 { 563 if (rdev->dummy_page.dmah == NULL) 564 return; 565 566 drm_dmamem_free(rdev->dmat, rdev->dummy_page.dmah); 567 rdev->dummy_page.dmah = NULL; 568 rdev->dummy_page.addr = 0; 569 } 570 571 572 /* ATOM accessor methods */ 573 /* 574 * ATOM is an interpreted byte code stored in tables in the vbios. The 575 * driver registers callbacks to access registers and the interpreter 576 * in the driver parses the tables and executes then to program specific 577 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 578 * atombios.h, and atom.c 579 */ 580 581 /** 582 * cail_pll_read - read PLL register 583 * 584 * @info: atom card_info pointer 585 * @reg: PLL register offset 586 * 587 * Provides a PLL register accessor for the atom interpreter (r4xx+). 588 * Returns the value of the PLL register. 589 */ 590 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 591 { 592 struct radeon_device *rdev = info->dev->dev_private; 593 uint32_t r; 594 595 r = rdev->pll_rreg(rdev, reg); 596 return r; 597 } 598 599 /** 600 * cail_pll_write - write PLL register 601 * 602 * @info: atom card_info pointer 603 * @reg: PLL register offset 604 * @val: value to write to the pll register 605 * 606 * Provides a PLL register accessor for the atom interpreter (r4xx+). 607 */ 608 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 609 { 610 struct radeon_device *rdev = info->dev->dev_private; 611 612 rdev->pll_wreg(rdev, reg, val); 613 } 614 615 /** 616 * cail_mc_read - read MC (Memory Controller) register 617 * 618 * @info: atom card_info pointer 619 * @reg: MC register offset 620 * 621 * Provides an MC register accessor for the atom interpreter (r4xx+). 622 * Returns the value of the MC register. 623 */ 624 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 625 { 626 struct radeon_device *rdev = info->dev->dev_private; 627 uint32_t r; 628 629 r = rdev->mc_rreg(rdev, reg); 630 return r; 631 } 632 633 /** 634 * cail_mc_write - write MC (Memory Controller) register 635 * 636 * @info: atom card_info pointer 637 * @reg: MC register offset 638 * @val: value to write to the pll register 639 * 640 * Provides a MC register accessor for the atom interpreter (r4xx+). 641 */ 642 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 643 { 644 struct radeon_device *rdev = info->dev->dev_private; 645 646 rdev->mc_wreg(rdev, reg, val); 647 } 648 649 /** 650 * cail_reg_write - write MMIO register 651 * 652 * @info: atom card_info pointer 653 * @reg: MMIO register offset 654 * @val: value to write to the pll register 655 * 656 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 657 */ 658 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 659 { 660 struct radeon_device *rdev = info->dev->dev_private; 661 662 WREG32(reg*4, val); 663 } 664 665 /** 666 * cail_reg_read - read MMIO register 667 * 668 * @info: atom card_info pointer 669 * @reg: MMIO register offset 670 * 671 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 672 * Returns the value of the MMIO register. 673 */ 674 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 675 { 676 struct radeon_device *rdev = info->dev->dev_private; 677 uint32_t r; 678 679 r = RREG32(reg*4); 680 return r; 681 } 682 683 /** 684 * cail_ioreg_write - write IO register 685 * 686 * @info: atom card_info pointer 687 * @reg: IO register offset 688 * @val: value to write to the pll register 689 * 690 * Provides a IO register accessor for the atom interpreter (r4xx+). 691 */ 692 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 693 { 694 struct radeon_device *rdev = info->dev->dev_private; 695 696 WREG32_IO(reg*4, val); 697 } 698 699 /** 700 * cail_ioreg_read - read IO register 701 * 702 * @info: atom card_info pointer 703 * @reg: IO register offset 704 * 705 * Provides an IO register accessor for the atom interpreter (r4xx+). 706 * Returns the value of the IO register. 707 */ 708 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 709 { 710 struct radeon_device *rdev = info->dev->dev_private; 711 uint32_t r; 712 713 r = RREG32_IO(reg*4); 714 return r; 715 } 716 717 /** 718 * radeon_atombios_init - init the driver info and callbacks for atombios 719 * 720 * @rdev: radeon_device pointer 721 * 722 * Initializes the driver info and register access callbacks for the 723 * ATOM interpreter (r4xx+). 724 * Returns 0 on sucess, -ENOMEM on failure. 725 * Called at driver startup. 726 */ 727 int radeon_atombios_init(struct radeon_device *rdev) 728 { 729 struct card_info *atom_card_info = 730 kzalloc(sizeof(struct card_info), GFP_KERNEL); 731 732 if (!atom_card_info) 733 return -ENOMEM; 734 735 rdev->mode_info.atom_card_info = atom_card_info; 736 atom_card_info->dev = rdev->ddev; 737 atom_card_info->reg_read = cail_reg_read; 738 atom_card_info->reg_write = cail_reg_write; 739 /* needed for iio ops */ 740 if (rdev->rio_mem_size > 0) { 741 atom_card_info->ioreg_read = cail_ioreg_read; 742 atom_card_info->ioreg_write = cail_ioreg_write; 743 } else { 744 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 745 atom_card_info->ioreg_read = cail_reg_read; 746 atom_card_info->ioreg_write = cail_reg_write; 747 } 748 atom_card_info->mc_read = cail_mc_read; 749 atom_card_info->mc_write = cail_mc_write; 750 atom_card_info->pll_read = cail_pll_read; 751 atom_card_info->pll_write = cail_pll_write; 752 753 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 754 rw_init(&rdev->mode_info.atom_context->mutex, "atomcon"); 755 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 756 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 757 return 0; 758 } 759 760 /** 761 * radeon_atombios_fini - free the driver info and callbacks for atombios 762 * 763 * @rdev: radeon_device pointer 764 * 765 * Frees the driver info and register access callbacks for the ATOM 766 * interpreter (r4xx+). 767 * Called at driver shutdown. 768 */ 769 void radeon_atombios_fini(struct radeon_device *rdev) 770 { 771 if (rdev->mode_info.atom_context) { 772 kfree(rdev->mode_info.atom_context->scratch); 773 kfree(rdev->mode_info.atom_context); 774 } 775 kfree(rdev->mode_info.atom_card_info); 776 } 777 778 /* COMBIOS */ 779 /* 780 * COMBIOS is the bios format prior to ATOM. It provides 781 * command tables similar to ATOM, but doesn't have a unified 782 * parser. See radeon_combios.c 783 */ 784 785 /** 786 * radeon_combios_init - init the driver info for combios 787 * 788 * @rdev: radeon_device pointer 789 * 790 * Initializes the driver info for combios (r1xx-r3xx). 791 * Returns 0 on sucess. 792 * Called at driver startup. 793 */ 794 int radeon_combios_init(struct radeon_device *rdev) 795 { 796 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 797 return 0; 798 } 799 800 /** 801 * radeon_combios_fini - free the driver info for combios 802 * 803 * @rdev: radeon_device pointer 804 * 805 * Frees the driver info for combios (r1xx-r3xx). 806 * Called at driver shutdown. 807 */ 808 void radeon_combios_fini(struct radeon_device *rdev) 809 { 810 } 811 812 /* if we get transitioned to only one device, take VGA back */ 813 /** 814 * radeon_vga_set_decode - enable/disable vga decode 815 * 816 * @cookie: radeon_device pointer 817 * @state: enable/disable vga decode 818 * 819 * Enable/disable vga decode (all asics). 820 * Returns VGA resource flags. 821 */ 822 #ifdef notyet 823 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 824 { 825 struct radeon_device *rdev = cookie; 826 radeon_vga_set_state(rdev, state); 827 if (state) 828 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 829 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 830 else 831 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 832 } 833 #endif 834 835 /** 836 * radeon_check_pot_argument - check that argument is a power of two 837 * 838 * @arg: value to check 839 * 840 * Validates that a certain argument is a power of two (all asics). 841 * Returns true if argument is valid. 842 */ 843 static bool radeon_check_pot_argument(int arg) 844 { 845 return (arg & (arg - 1)) == 0; 846 } 847 848 /** 849 * radeon_check_arguments - validate module params 850 * 851 * @rdev: radeon_device pointer 852 * 853 * Validates certain module parameters and updates 854 * the associated values used by the driver (all asics). 855 */ 856 static void radeon_check_arguments(struct radeon_device *rdev) 857 { 858 /* vramlimit must be a power of two */ 859 if (!radeon_check_pot_argument(radeon_vram_limit)) { 860 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 861 radeon_vram_limit); 862 radeon_vram_limit = 0; 863 } 864 865 /* gtt size must be power of two and greater or equal to 32M */ 866 if (radeon_gart_size < 32) { 867 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", 868 radeon_gart_size); 869 radeon_gart_size = 512; 870 871 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 872 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 873 radeon_gart_size); 874 radeon_gart_size = 512; 875 } 876 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 877 878 /* AGP mode can only be -1, 1, 2, 4, 8 */ 879 switch (radeon_agpmode) { 880 case -1: 881 case 0: 882 case 1: 883 case 2: 884 case 4: 885 case 8: 886 break; 887 default: 888 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 889 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 890 radeon_agpmode = 0; 891 break; 892 } 893 } 894 895 #ifdef notyet 896 /** 897 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is 898 * needed for waking up. 899 * 900 * @pdev: pci dev pointer 901 */ 902 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev) 903 { 904 905 /* 6600m in a macbook pro */ 906 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 907 pdev->subsystem_device == 0x00e2) { 908 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n"); 909 return true; 910 } 911 912 return false; 913 } 914 915 /** 916 * radeon_switcheroo_set_state - set switcheroo state 917 * 918 * @pdev: pci dev pointer 919 * @state: vga switcheroo state 920 * 921 * Callback for the switcheroo driver. Suspends or resumes the 922 * the asics before or after it is powered up using ACPI methods. 923 */ 924 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 925 { 926 struct drm_device *dev = pci_get_drvdata(pdev); 927 pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; 928 if (state == VGA_SWITCHEROO_ON) { 929 unsigned d3_delay = dev->pdev->d3_delay; 930 931 printk(KERN_INFO "radeon: switched on\n"); 932 /* don't suspend or resume card normally */ 933 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 934 935 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev)) 936 dev->pdev->d3_delay = 20; 937 938 radeon_resume_kms(dev); 939 940 dev->pdev->d3_delay = d3_delay; 941 942 dev->switch_power_state = DRM_SWITCH_POWER_ON; 943 drm_kms_helper_poll_enable(dev); 944 } else { 945 printk(KERN_INFO "radeon: switched off\n"); 946 drm_kms_helper_poll_disable(dev); 947 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 948 radeon_suspend_kms(dev, pmm); 949 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 950 } 951 } 952 953 /** 954 * radeon_switcheroo_can_switch - see if switcheroo state can change 955 * 956 * @pdev: pci dev pointer 957 * 958 * Callback for the switcheroo driver. Check of the switcheroo 959 * state can be changed. 960 * Returns true if the state can be changed, false if not. 961 */ 962 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 963 { 964 struct drm_device *dev = pci_get_drvdata(pdev); 965 bool can_switch; 966 967 spin_lock(&dev->count_lock); 968 can_switch = (dev->open_count == 0); 969 spin_unlock(&dev->count_lock); 970 return can_switch; 971 } 972 973 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 974 .set_gpu_state = radeon_switcheroo_set_state, 975 .reprobe = NULL, 976 .can_switch = radeon_switcheroo_can_switch, 977 }; 978 #endif 979 980 /** 981 * radeon_device_init - initialize the driver 982 * 983 * @rdev: radeon_device pointer 984 * @pdev: drm dev pointer 985 * @pdev: pci dev pointer 986 * @flags: driver flags 987 * 988 * Initializes the driver info and hw (all asics). 989 * Returns 0 for success or an error on failure. 990 * Called at driver startup. 991 */ 992 int radeon_device_init(struct radeon_device *rdev, 993 struct drm_device *ddev) 994 { 995 #ifdef DRMDEBUG 996 struct pci_dev *pdev = ddev->pdev; 997 #endif 998 int r, i; 999 int dma_bits; 1000 1001 rdev->shutdown = false; 1002 rdev->family = rdev->flags & RADEON_FAMILY_MASK; 1003 rdev->is_atom_bios = false; 1004 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1005 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 1006 rdev->accel_working = false; 1007 /* set up ring ids */ 1008 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1009 rdev->ring[i].idx = i; 1010 } 1011 1012 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1013 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1014 pdev->subsystem_vendor, pdev->subsystem_device); 1015 1016 /* mutex initialization are all done here so we 1017 * can recall function without having locking issues */ 1018 rw_init(&rdev->ring_lock, "ring"); 1019 rw_init(&rdev->dc_hw_i2c_mutex, "dciic"); 1020 atomic_set(&rdev->ih.lock, 0); 1021 rw_init(&rdev->gem.mutex, "gem"); 1022 rw_init(&rdev->pm.mutex, "pm"); 1023 rw_init(&rdev->gpu_clock_mutex, "gpuclk"); 1024 rw_init(&rdev->pm.mclk_lock, "mclk"); 1025 rw_init(&rdev->exclusive_lock, "rdnexc"); 1026 init_waitqueue_head(&rdev->irq.vblank_queue); 1027 r = radeon_gem_init(rdev); 1028 if (r) 1029 return r; 1030 /* initialize vm here */ 1031 rw_init(&rdev->vm_manager.lock, "vmmgr"); 1032 /* Adjust VM size here. 1033 * Currently set to 4GB ((1 << 20) 4k pages). 1034 * Max GPUVM size for cayman and SI is 40 bits. 1035 */ 1036 rdev->vm_manager.max_pfn = 1 << 20; 1037 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); 1038 1039 /* Set asic functions */ 1040 r = radeon_asic_init(rdev); 1041 if (r) 1042 return r; 1043 radeon_check_arguments(rdev); 1044 1045 /* all of the newer IGP chips have an internal gart 1046 * However some rs4xx report as AGP, so remove that here. 1047 */ 1048 if ((rdev->family >= CHIP_RS400) && 1049 (rdev->flags & RADEON_IS_IGP)) { 1050 rdev->flags &= ~RADEON_IS_AGP; 1051 } 1052 1053 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1054 radeon_agp_disable(rdev); 1055 } 1056 1057 /* set DMA mask + need_dma32 flags. 1058 * PCIE - can handle 40-bits. 1059 * IGP - can handle 40-bits 1060 * AGP - generally dma32 is safest 1061 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1062 */ 1063 rdev->need_dma32 = false; 1064 if (rdev->flags & RADEON_IS_AGP) 1065 rdev->need_dma32 = true; 1066 if ((rdev->flags & RADEON_IS_PCI) && 1067 (rdev->family <= CHIP_RS740)) 1068 rdev->need_dma32 = true; 1069 1070 dma_bits = rdev->need_dma32 ? 32 : 40; 1071 #ifdef notyet 1072 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1073 if (r) { 1074 rdev->need_dma32 = true; 1075 dma_bits = 32; 1076 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1077 } 1078 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1079 if (r) { 1080 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1081 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1082 } 1083 1084 /* Registers mapping */ 1085 /* TODO: block userspace mapping of io register */ 1086 #endif 1087 mtx_init(&rdev->mmio_idx_lock, IPL_TTY); 1088 #ifdef notyet 1089 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1090 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1091 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1092 if (rdev->rmmio == NULL) { 1093 return -ENOMEM; 1094 } 1095 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1096 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1097 1098 /* io port mapping */ 1099 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1100 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 1101 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1102 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 1103 break; 1104 } 1105 } 1106 if (rdev->rio_mem == NULL) 1107 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1108 1109 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1110 /* this will fail for cards that aren't VGA class devices, just 1111 * ignore it */ 1112 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1113 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops); 1114 #endif 1115 1116 r = radeon_init(rdev); 1117 if (r) 1118 return r; 1119 1120 r = radeon_ib_ring_tests(rdev); 1121 if (r) 1122 DRM_ERROR("ib ring test failed (%d).\n", r); 1123 1124 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1125 /* Acceleration not working on AGP card try again 1126 * with fallback to PCI or PCIE GART 1127 */ 1128 radeon_asic_reset(rdev); 1129 radeon_fini(rdev); 1130 radeon_agp_disable(rdev); 1131 r = radeon_init(rdev); 1132 if (r) 1133 return r; 1134 } 1135 if ((radeon_testing & 1)) { 1136 if (rdev->accel_working) 1137 radeon_test_moves(rdev); 1138 else 1139 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1140 } 1141 if ((radeon_testing & 2)) { 1142 if (rdev->accel_working) 1143 radeon_test_syncing(rdev); 1144 else 1145 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1146 } 1147 if (radeon_benchmarking) { 1148 if (rdev->accel_working) 1149 radeon_benchmark(rdev, radeon_benchmarking); 1150 else 1151 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1152 } 1153 return 0; 1154 } 1155 1156 #ifdef __linux__ 1157 static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1158 #endif 1159 1160 /** 1161 * radeon_device_fini - tear down the driver 1162 * 1163 * @rdev: radeon_device pointer 1164 * 1165 * Tear down the driver info (all asics). 1166 * Called at driver shutdown. 1167 */ 1168 void radeon_device_fini(struct radeon_device *rdev) 1169 { 1170 DRM_INFO("radeon: finishing device.\n"); 1171 rdev->shutdown = true; 1172 /* evict vram memory */ 1173 radeon_bo_evict_vram(rdev); 1174 radeon_fini(rdev); 1175 #ifdef notyet 1176 vga_switcheroo_unregister_client(rdev->pdev); 1177 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1178 if (rdev->rio_mem) 1179 pci_iounmap(rdev->pdev, rdev->rio_mem); 1180 rdev->rio_mem = NULL; 1181 iounmap(rdev->rmmio); 1182 rdev->rmmio = NULL; 1183 radeon_debugfs_remove_files(rdev); 1184 #endif 1185 } 1186 1187 /* 1188 * Suspend & resume. 1189 */ 1190 /** 1191 * radeon_suspend_kms - initiate device suspend 1192 * 1193 * @pdev: drm dev pointer 1194 * @state: suspend state 1195 * 1196 * Puts the hw in the suspend state (all asics). 1197 * Returns 0 for success or an error on failure. 1198 * Called at driver suspend. 1199 */ 1200 int radeon_suspend_kms(struct drm_device *dev) 1201 { 1202 struct radeon_device *rdev; 1203 struct drm_crtc *crtc; 1204 struct drm_connector *connector; 1205 int i, r; 1206 bool force_completion = false; 1207 1208 if (dev == NULL || dev->dev_private == NULL) { 1209 return -ENODEV; 1210 } 1211 #ifdef notyet 1212 if (state.event == PM_EVENT_PRETHAW) { 1213 return 0; 1214 } 1215 #endif 1216 rdev = dev->dev_private; 1217 if (rdev->shutdown) 1218 return 0; 1219 1220 #ifdef notyet 1221 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1222 return 0; 1223 #endif 1224 1225 drm_kms_helper_poll_disable(dev); 1226 1227 /* turn off display hw */ 1228 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1229 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1230 } 1231 1232 /* unpin the front buffers */ 1233 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1234 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb); 1235 struct radeon_bo *robj; 1236 1237 if (rfb == NULL || rfb->obj == NULL) { 1238 continue; 1239 } 1240 robj = gem_to_radeon_bo(rfb->obj); 1241 /* don't unpin kernel fb objects */ 1242 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1243 r = radeon_bo_reserve(robj, false); 1244 if (r == 0) { 1245 radeon_bo_unpin(robj); 1246 radeon_bo_unreserve(robj); 1247 } 1248 } 1249 } 1250 /* evict vram memory */ 1251 radeon_bo_evict_vram(rdev); 1252 1253 mutex_lock(&rdev->ring_lock); 1254 /* wait for gpu to finish processing current batch */ 1255 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1256 r = radeon_fence_wait_empty_locked(rdev, i); 1257 if (r) { 1258 /* delay GPU reset to resume */ 1259 force_completion = true; 1260 } 1261 } 1262 if (force_completion) { 1263 radeon_fence_driver_force_completion(rdev); 1264 } 1265 mutex_unlock(&rdev->ring_lock); 1266 1267 radeon_save_bios_scratch_regs(rdev); 1268 1269 radeon_pm_suspend(rdev); 1270 radeon_suspend(rdev); 1271 radeon_hpd_fini(rdev); 1272 /* evict remaining vram memory */ 1273 radeon_bo_evict_vram(rdev); 1274 1275 radeon_agp_suspend(rdev); 1276 1277 #ifdef notyet 1278 pci_save_state(dev->pdev); 1279 if (state.event == PM_EVENT_SUSPEND) { 1280 /* Shut down the device */ 1281 pci_disable_device(dev->pdev); 1282 pci_set_power_state(dev->pdev, PCI_D3hot); 1283 } 1284 #endif 1285 console_lock(); 1286 radeon_fbdev_set_suspend(rdev, 1); 1287 console_unlock(); 1288 return 0; 1289 } 1290 1291 /** 1292 * radeon_resume_kms - initiate device resume 1293 * 1294 * @pdev: drm dev pointer 1295 * 1296 * Bring the hw back to operating state (all asics). 1297 * Returns 0 for success or an error on failure. 1298 * Called at driver resume. 1299 */ 1300 int radeon_resume_kms(struct drm_device *dev) 1301 { 1302 struct drm_connector *connector; 1303 struct radeon_device *rdev = dev->dev_private; 1304 int r; 1305 1306 #ifdef notyet 1307 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1308 return 0; 1309 #endif 1310 1311 console_lock(); 1312 #ifdef notyet 1313 pci_set_power_state(dev->pdev, PCI_D0); 1314 pci_restore_state(dev->pdev); 1315 if (pci_enable_device(dev->pdev)) { 1316 console_unlock(); 1317 return -1; 1318 } 1319 #endif 1320 /* resume AGP if in use */ 1321 radeon_agp_resume(rdev); 1322 radeon_resume(rdev); 1323 1324 r = radeon_ib_ring_tests(rdev); 1325 if (r) 1326 DRM_ERROR("ib ring test failed (%d).\n", r); 1327 1328 radeon_pm_resume(rdev); 1329 radeon_restore_bios_scratch_regs(rdev); 1330 1331 radeon_fbdev_set_suspend(rdev, 0); 1332 console_unlock(); 1333 1334 /* init dig PHYs, disp eng pll */ 1335 if (rdev->is_atom_bios) { 1336 radeon_atom_encoder_init(rdev); 1337 radeon_atom_disp_eng_pll_init(rdev); 1338 /* turn on the BL */ 1339 if (rdev->mode_info.bl_encoder) { 1340 u8 bl_level = radeon_get_backlight_level(rdev, 1341 rdev->mode_info.bl_encoder); 1342 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1343 bl_level); 1344 } 1345 } 1346 /* reset hpd state */ 1347 radeon_hpd_init(rdev); 1348 /* blat the mode back in */ 1349 drm_helper_resume_force_mode(dev); 1350 /* turn on display hw */ 1351 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1352 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1353 } 1354 1355 drm_kms_helper_poll_enable(dev); 1356 return 0; 1357 } 1358 1359 /** 1360 * radeon_gpu_reset - reset the asic 1361 * 1362 * @rdev: radeon device pointer 1363 * 1364 * Attempt the reset the GPU if it has hung (all asics). 1365 * Returns 0 for success or an error on failure. 1366 */ 1367 int radeon_gpu_reset(struct radeon_device *rdev) 1368 { 1369 unsigned ring_sizes[RADEON_NUM_RINGS]; 1370 uint32_t *ring_data[RADEON_NUM_RINGS]; 1371 1372 bool saved = false; 1373 1374 int i, r; 1375 int resched; 1376 1377 down_write(&rdev->exclusive_lock); 1378 radeon_save_bios_scratch_regs(rdev); 1379 /* block TTM */ 1380 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1381 radeon_suspend(rdev); 1382 1383 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1384 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1385 &ring_data[i]); 1386 if (ring_sizes[i]) { 1387 saved = true; 1388 dev_info(rdev->dev, "Saved %d dwords of commands " 1389 "on ring %d.\n", ring_sizes[i], i); 1390 } 1391 } 1392 1393 retry: 1394 r = radeon_asic_reset(rdev); 1395 if (!r) { 1396 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1397 radeon_resume(rdev); 1398 } 1399 1400 radeon_restore_bios_scratch_regs(rdev); 1401 1402 if (!r) { 1403 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1404 radeon_ring_restore(rdev, &rdev->ring[i], 1405 ring_sizes[i], ring_data[i]); 1406 ring_sizes[i] = 0; 1407 ring_data[i] = NULL; 1408 } 1409 1410 r = radeon_ib_ring_tests(rdev); 1411 if (r) { 1412 dev_err(rdev->dev, "ib ring test failed (%d).\n", r); 1413 if (saved) { 1414 saved = false; 1415 radeon_suspend(rdev); 1416 goto retry; 1417 } 1418 } 1419 } else { 1420 radeon_fence_driver_force_completion(rdev); 1421 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1422 kfree(ring_data[i]); 1423 } 1424 } 1425 1426 drm_helper_resume_force_mode(rdev->ddev); 1427 1428 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1429 if (r) { 1430 /* bad news, how to tell it to userspace ? */ 1431 dev_info(rdev->dev, "GPU reset failed\n"); 1432 } 1433 1434 up_write(&rdev->exclusive_lock); 1435 return r; 1436 } 1437 1438 1439 #ifdef __linux__ 1440 /* 1441 * Debugfs 1442 */ 1443 int radeon_debugfs_add_files(struct radeon_device *rdev, 1444 struct drm_info_list *files, 1445 unsigned nfiles) 1446 { 1447 unsigned i; 1448 1449 for (i = 0; i < rdev->debugfs_count; i++) { 1450 if (rdev->debugfs[i].files == files) { 1451 /* Already registered */ 1452 return 0; 1453 } 1454 } 1455 1456 i = rdev->debugfs_count + 1; 1457 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1458 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1459 DRM_ERROR("Report so we increase " 1460 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1461 return -EINVAL; 1462 } 1463 rdev->debugfs[rdev->debugfs_count].files = files; 1464 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1465 rdev->debugfs_count = i; 1466 #if defined(CONFIG_DEBUG_FS) 1467 drm_debugfs_create_files(files, nfiles, 1468 rdev->ddev->control->debugfs_root, 1469 rdev->ddev->control); 1470 drm_debugfs_create_files(files, nfiles, 1471 rdev->ddev->primary->debugfs_root, 1472 rdev->ddev->primary); 1473 #endif 1474 return 0; 1475 } 1476 1477 static void radeon_debugfs_remove_files(struct radeon_device *rdev) 1478 { 1479 #if defined(CONFIG_DEBUG_FS) 1480 unsigned i; 1481 1482 for (i = 0; i < rdev->debugfs_count; i++) { 1483 drm_debugfs_remove_files(rdev->debugfs[i].files, 1484 rdev->debugfs[i].num_files, 1485 rdev->ddev->control); 1486 drm_debugfs_remove_files(rdev->debugfs[i].files, 1487 rdev->debugfs[i].num_files, 1488 rdev->ddev->primary); 1489 } 1490 #endif 1491 } 1492 1493 #if defined(CONFIG_DEBUG_FS) 1494 int radeon_debugfs_init(struct drm_minor *minor) 1495 { 1496 return 0; 1497 } 1498 1499 void radeon_debugfs_cleanup(struct drm_minor *minor) 1500 { 1501 } 1502 #endif 1503 #endif // __linux__ 1504