1 /* $OpenBSD: radeon_i2c.c,v 1.5 2015/04/06 07:38:49 jsg Exp $ */ 2 /* 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 28 #include <dev/pci/drm/drmP.h> 29 #include <dev/pci/drm/drm_edid.h> 30 #include <dev/pci/drm/radeon_drm.h> 31 #include "radeon.h" 32 #include "atom.h" 33 34 #include <dev/i2c/i2cvar.h> 35 #include <dev/i2c/i2c_bitbang.h> 36 37 #ifdef notyet 38 extern int radeon_atom_hw_i2c_xfer(struct i2c_controller *i2c_adap, 39 struct i2c_msg *msgs, int num); 40 #endif 41 extern u32 radeon_atom_hw_i2c_func(struct i2c_controller *adap); 42 43 /** 44 * radeon_ddc_probe 45 * 46 */ 47 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 48 { 49 u8 out = 0x0; 50 u8 buf[8]; 51 int ret; 52 53 /* on hw with routers, select right port */ 54 if (radeon_connector->router.ddc_valid) 55 radeon_router_select_ddc_port(radeon_connector); 56 57 if (use_aux) { 58 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 59 iic_acquire_bus(&dig->dp_i2c_bus->adapter, 0); 60 ret = iic_exec(&dig->dp_i2c_bus->adapter, I2C_OP_READ_WITH_STOP, DDC_ADDR, &out, 1, buf, 8, 0); 61 iic_release_bus(&dig->dp_i2c_bus->adapter, 0); 62 } else { 63 iic_acquire_bus(&radeon_connector->ddc_bus->adapter, 0); 64 ret = iic_exec(&radeon_connector->ddc_bus->adapter, I2C_OP_READ_WITH_STOP, DDC_ADDR, &out, 1, buf, 8, 0); 65 iic_release_bus(&radeon_connector->ddc_bus->adapter, 0); 66 } 67 68 if (ret) 69 /* Couldn't find an accessible DDC on this connector */ 70 return false; 71 /* Probe also for valid EDID header 72 * EDID header starts with: 73 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 74 * Only the first 6 bytes must be valid as 75 * drm_edid_block_valid() can fix the last 2 bytes */ 76 if (drm_edid_header_is_valid(buf) < 6) { 77 /* Couldn't find an accessible EDID on this 78 * connector */ 79 return false; 80 } 81 return true; 82 } 83 84 /* bit banging i2c */ 85 86 static int pre_xfer(void *cookie) 87 { 88 struct radeon_i2c_chan *i2c = cookie; 89 struct radeon_device *rdev = i2c->dev->dev_private; 90 struct radeon_i2c_bus_rec *rec = &i2c->rec; 91 uint32_t temp; 92 93 /* RV410 appears to have a bug where the hw i2c in reset 94 * holds the i2c port in a bad state - switch hw i2c away before 95 * doing DDC - do this for all r200s/r300s/r400s for safety sake 96 */ 97 if (rec->hw_capable) { 98 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 99 u32 reg; 100 101 if (rdev->family >= CHIP_RV350) 102 reg = RADEON_GPIO_MONID; 103 else if ((rdev->family == CHIP_R300) || 104 (rdev->family == CHIP_R350)) 105 reg = RADEON_GPIO_DVI_DDC; 106 else 107 reg = RADEON_GPIO_CRT2_DDC; 108 109 mutex_lock(&rdev->dc_hw_i2c_mutex); 110 if (rec->a_clk_reg == reg) { 111 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 112 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 113 } else { 114 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 115 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 116 } 117 mutex_unlock(&rdev->dc_hw_i2c_mutex); 118 } 119 } 120 121 /* switch the pads to ddc mode */ 122 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 123 temp = RREG32(rec->mask_clk_reg); 124 temp &= ~(1 << 16); 125 WREG32(rec->mask_clk_reg, temp); 126 } 127 128 /* clear the output pin values */ 129 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 130 WREG32(rec->a_clk_reg, temp); 131 132 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 133 WREG32(rec->a_data_reg, temp); 134 135 /* set the pins to input */ 136 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 137 WREG32(rec->en_clk_reg, temp); 138 139 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 140 WREG32(rec->en_data_reg, temp); 141 142 /* mask the gpio pins for software use */ 143 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 144 WREG32(rec->mask_clk_reg, temp); 145 temp = RREG32(rec->mask_clk_reg); 146 147 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 148 WREG32(rec->mask_data_reg, temp); 149 temp = RREG32(rec->mask_data_reg); 150 151 return 0; 152 } 153 154 static void post_xfer(void *cookie) 155 { 156 struct radeon_i2c_chan *i2c = cookie; 157 struct radeon_device *rdev = i2c->dev->dev_private; 158 struct radeon_i2c_bus_rec *rec = &i2c->rec; 159 uint32_t temp; 160 161 /* unmask the gpio pins for software use */ 162 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 163 WREG32(rec->mask_clk_reg, temp); 164 temp = RREG32(rec->mask_clk_reg); 165 166 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 167 WREG32(rec->mask_data_reg, temp); 168 temp = RREG32(rec->mask_data_reg); 169 } 170 171 static int get_clock(void *i2c_priv) 172 { 173 struct radeon_i2c_chan *i2c = i2c_priv; 174 struct radeon_device *rdev = i2c->dev->dev_private; 175 struct radeon_i2c_bus_rec *rec = &i2c->rec; 176 uint32_t val; 177 178 /* read the value off the pin */ 179 val = RREG32(rec->y_clk_reg); 180 val &= rec->y_clk_mask; 181 182 return (val != 0); 183 } 184 185 186 static int get_data(void *i2c_priv) 187 { 188 struct radeon_i2c_chan *i2c = i2c_priv; 189 struct radeon_device *rdev = i2c->dev->dev_private; 190 struct radeon_i2c_bus_rec *rec = &i2c->rec; 191 uint32_t val; 192 193 /* read the value off the pin */ 194 val = RREG32(rec->y_data_reg); 195 val &= rec->y_data_mask; 196 197 return (val != 0); 198 } 199 200 static void set_clock(void *i2c_priv, int clock) 201 { 202 struct radeon_i2c_chan *i2c = i2c_priv; 203 struct radeon_device *rdev = i2c->dev->dev_private; 204 struct radeon_i2c_bus_rec *rec = &i2c->rec; 205 uint32_t val; 206 207 /* set pin direction */ 208 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 209 val |= clock ? 0 : rec->en_clk_mask; 210 WREG32(rec->en_clk_reg, val); 211 } 212 213 static void set_data(void *i2c_priv, int data) 214 { 215 struct radeon_i2c_chan *i2c = i2c_priv; 216 struct radeon_device *rdev = i2c->dev->dev_private; 217 struct radeon_i2c_bus_rec *rec = &i2c->rec; 218 uint32_t val; 219 220 /* set pin direction */ 221 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 222 val |= data ? 0 : rec->en_data_mask; 223 WREG32(rec->en_data_reg, val); 224 } 225 226 void radeon_bb_set_bits(void *, uint32_t); 227 void radeon_bb_set_dir(void *, uint32_t); 228 uint32_t radeon_bb_read_bits(void *); 229 230 int radeon_acquire_bus(void *, int); 231 void radeon_release_bus(void *, int); 232 int radeon_send_start(void *, int); 233 int radeon_send_stop(void *, int); 234 int radeon_initiate_xfer(void *, i2c_addr_t, int); 235 int radeon_read_byte(void *, u_int8_t *, int); 236 int radeon_write_byte(void *, u_int8_t, int); 237 238 #define RADEON_BB_SDA (1 << I2C_BIT_SDA) 239 #define RADEON_BB_SCL (1 << I2C_BIT_SCL) 240 241 struct i2c_bitbang_ops radeon_bbops = { 242 radeon_bb_set_bits, 243 radeon_bb_set_dir, 244 radeon_bb_read_bits, 245 { RADEON_BB_SDA, RADEON_BB_SCL, 0, 0 } 246 }; 247 248 void 249 radeon_bb_set_bits(void *cookie, uint32_t bits) 250 { 251 set_clock(cookie, bits & RADEON_BB_SCL); 252 set_data(cookie, bits & RADEON_BB_SDA); 253 } 254 255 void 256 radeon_bb_set_dir(void *cookie, uint32_t bits) 257 { 258 } 259 260 uint32_t 261 radeon_bb_read_bits(void *cookie) 262 { 263 uint32_t bits = 0; 264 265 if (get_clock(cookie)) 266 bits |= RADEON_BB_SCL; 267 if (get_data(cookie)) 268 bits |= RADEON_BB_SDA; 269 270 return bits; 271 } 272 273 int 274 radeon_acquire_bus(void *cookie, int flags) 275 { 276 pre_xfer(cookie); 277 return (0); 278 } 279 280 void 281 radeon_release_bus(void *cookie, int flags) 282 { 283 post_xfer(cookie); 284 } 285 286 int 287 radeon_send_start(void *cookie, int flags) 288 { 289 return (i2c_bitbang_send_start(cookie, flags, &radeon_bbops)); 290 } 291 292 int 293 radeon_send_stop(void *cookie, int flags) 294 { 295 return (i2c_bitbang_send_stop(cookie, flags, &radeon_bbops)); 296 } 297 298 int 299 radeon_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 300 { 301 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &radeon_bbops)); 302 } 303 304 int 305 radeon_read_byte(void *cookie, u_int8_t *bytep, int flags) 306 { 307 return (i2c_bitbang_read_byte(cookie, bytep, flags, &radeon_bbops)); 308 } 309 310 int 311 radeon_write_byte(void *cookie, u_int8_t byte, int flags) 312 { 313 return (i2c_bitbang_write_byte(cookie, byte, flags, &radeon_bbops)); 314 } 315 316 /* hw i2c */ 317 318 #ifdef notyet 319 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 320 { 321 u32 sclk = rdev->pm.current_sclk; 322 u32 prescale = 0; 323 u32 nm; 324 u8 n, m, loop; 325 int i2c_clock; 326 327 switch (rdev->family) { 328 case CHIP_R100: 329 case CHIP_RV100: 330 case CHIP_RS100: 331 case CHIP_RV200: 332 case CHIP_RS200: 333 case CHIP_R200: 334 case CHIP_RV250: 335 case CHIP_RS300: 336 case CHIP_RV280: 337 case CHIP_R300: 338 case CHIP_R350: 339 case CHIP_RV350: 340 i2c_clock = 60; 341 nm = (sclk * 10) / (i2c_clock * 4); 342 for (loop = 1; loop < 255; loop++) { 343 if ((nm / loop) < loop) 344 break; 345 } 346 n = loop - 1; 347 m = loop - 2; 348 prescale = m | (n << 8); 349 break; 350 case CHIP_RV380: 351 case CHIP_RS400: 352 case CHIP_RS480: 353 case CHIP_R420: 354 case CHIP_R423: 355 case CHIP_RV410: 356 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 357 break; 358 case CHIP_RS600: 359 case CHIP_RS690: 360 case CHIP_RS740: 361 /* todo */ 362 break; 363 case CHIP_RV515: 364 case CHIP_R520: 365 case CHIP_RV530: 366 case CHIP_RV560: 367 case CHIP_RV570: 368 case CHIP_R580: 369 i2c_clock = 50; 370 if (rdev->family == CHIP_R520) 371 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 372 else 373 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 374 break; 375 case CHIP_R600: 376 case CHIP_RV610: 377 case CHIP_RV630: 378 case CHIP_RV670: 379 /* todo */ 380 break; 381 case CHIP_RV620: 382 case CHIP_RV635: 383 case CHIP_RS780: 384 case CHIP_RS880: 385 case CHIP_RV770: 386 case CHIP_RV730: 387 case CHIP_RV710: 388 case CHIP_RV740: 389 /* todo */ 390 break; 391 case CHIP_CEDAR: 392 case CHIP_REDWOOD: 393 case CHIP_JUNIPER: 394 case CHIP_CYPRESS: 395 case CHIP_HEMLOCK: 396 /* todo */ 397 break; 398 default: 399 DRM_ERROR("i2c: unhandled radeon chip\n"); 400 break; 401 } 402 return prescale; 403 } 404 405 406 /* hw i2c engine for r1xx-4xx hardware 407 * hw can buffer up to 15 bytes 408 */ 409 static int r100_hw_i2c_xfer(struct i2c_controller *i2c_adap, 410 struct i2c_msg *msgs, int num) 411 { 412 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 413 struct radeon_device *rdev = i2c->dev->dev_private; 414 struct radeon_i2c_bus_rec *rec = &i2c->rec; 415 struct i2c_msg *p; 416 int i, j, k, ret = num; 417 u32 prescale; 418 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 419 u32 tmp, reg; 420 421 mutex_lock(&rdev->dc_hw_i2c_mutex); 422 /* take the pm lock since we need a constant sclk */ 423 mutex_lock(&rdev->pm.mutex); 424 425 prescale = radeon_get_i2c_prescale(rdev); 426 427 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 428 RADEON_I2C_DRIVE_EN | 429 RADEON_I2C_START | 430 RADEON_I2C_STOP | 431 RADEON_I2C_GO); 432 433 if (rdev->is_atom_bios) { 434 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 435 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 436 } 437 438 if (rec->mm_i2c) { 439 i2c_cntl_0 = RADEON_I2C_CNTL_0; 440 i2c_cntl_1 = RADEON_I2C_CNTL_1; 441 i2c_data = RADEON_I2C_DATA; 442 } else { 443 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 444 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 445 i2c_data = RADEON_DVI_I2C_DATA; 446 447 switch (rdev->family) { 448 case CHIP_R100: 449 case CHIP_RV100: 450 case CHIP_RS100: 451 case CHIP_RV200: 452 case CHIP_RS200: 453 case CHIP_RS300: 454 switch (rec->mask_clk_reg) { 455 case RADEON_GPIO_DVI_DDC: 456 /* no gpio select bit */ 457 break; 458 default: 459 DRM_ERROR("gpio not supported with hw i2c\n"); 460 ret = -EINVAL; 461 goto done; 462 } 463 break; 464 case CHIP_R200: 465 /* only bit 4 on r200 */ 466 switch (rec->mask_clk_reg) { 467 case RADEON_GPIO_DVI_DDC: 468 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 469 break; 470 case RADEON_GPIO_MONID: 471 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 472 break; 473 default: 474 DRM_ERROR("gpio not supported with hw i2c\n"); 475 ret = -EINVAL; 476 goto done; 477 } 478 break; 479 case CHIP_RV250: 480 case CHIP_RV280: 481 /* bits 3 and 4 */ 482 switch (rec->mask_clk_reg) { 483 case RADEON_GPIO_DVI_DDC: 484 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 485 break; 486 case RADEON_GPIO_VGA_DDC: 487 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 488 break; 489 case RADEON_GPIO_CRT2_DDC: 490 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 491 break; 492 default: 493 DRM_ERROR("gpio not supported with hw i2c\n"); 494 ret = -EINVAL; 495 goto done; 496 } 497 break; 498 case CHIP_R300: 499 case CHIP_R350: 500 /* only bit 4 on r300/r350 */ 501 switch (rec->mask_clk_reg) { 502 case RADEON_GPIO_VGA_DDC: 503 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 504 break; 505 case RADEON_GPIO_DVI_DDC: 506 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 507 break; 508 default: 509 DRM_ERROR("gpio not supported with hw i2c\n"); 510 ret = -EINVAL; 511 goto done; 512 } 513 break; 514 case CHIP_RV350: 515 case CHIP_RV380: 516 case CHIP_R420: 517 case CHIP_R423: 518 case CHIP_RV410: 519 case CHIP_RS400: 520 case CHIP_RS480: 521 /* bits 3 and 4 */ 522 switch (rec->mask_clk_reg) { 523 case RADEON_GPIO_VGA_DDC: 524 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 525 break; 526 case RADEON_GPIO_DVI_DDC: 527 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 528 break; 529 case RADEON_GPIO_MONID: 530 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 531 break; 532 default: 533 DRM_ERROR("gpio not supported with hw i2c\n"); 534 ret = -EINVAL; 535 goto done; 536 } 537 break; 538 default: 539 DRM_ERROR("unsupported asic\n"); 540 ret = -EINVAL; 541 goto done; 542 break; 543 } 544 } 545 546 /* check for bus probe */ 547 p = &msgs[0]; 548 if ((num == 1) && (p->len == 0)) { 549 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 550 RADEON_I2C_NACK | 551 RADEON_I2C_HALT | 552 RADEON_I2C_SOFT_RST)); 553 WREG32(i2c_data, (p->addr << 1) & 0xff); 554 WREG32(i2c_data, 0); 555 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 556 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 557 RADEON_I2C_EN | 558 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 559 WREG32(i2c_cntl_0, reg); 560 for (k = 0; k < 32; k++) { 561 udelay(10); 562 tmp = RREG32(i2c_cntl_0); 563 if (tmp & RADEON_I2C_GO) 564 continue; 565 tmp = RREG32(i2c_cntl_0); 566 if (tmp & RADEON_I2C_DONE) 567 break; 568 else { 569 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 570 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 571 ret = -EIO; 572 goto done; 573 } 574 } 575 goto done; 576 } 577 578 for (i = 0; i < num; i++) { 579 p = &msgs[i]; 580 for (j = 0; j < p->len; j++) { 581 if (p->flags & I2C_M_RD) { 582 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 583 RADEON_I2C_NACK | 584 RADEON_I2C_HALT | 585 RADEON_I2C_SOFT_RST)); 586 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 587 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 588 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 589 RADEON_I2C_EN | 590 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 591 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 592 for (k = 0; k < 32; k++) { 593 udelay(10); 594 tmp = RREG32(i2c_cntl_0); 595 if (tmp & RADEON_I2C_GO) 596 continue; 597 tmp = RREG32(i2c_cntl_0); 598 if (tmp & RADEON_I2C_DONE) 599 break; 600 else { 601 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 602 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 603 ret = -EIO; 604 goto done; 605 } 606 } 607 p->buf[j] = RREG32(i2c_data) & 0xff; 608 } else { 609 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 610 RADEON_I2C_NACK | 611 RADEON_I2C_HALT | 612 RADEON_I2C_SOFT_RST)); 613 WREG32(i2c_data, (p->addr << 1) & 0xff); 614 WREG32(i2c_data, p->buf[j]); 615 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 616 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 617 RADEON_I2C_EN | 618 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 619 WREG32(i2c_cntl_0, reg); 620 for (k = 0; k < 32; k++) { 621 udelay(10); 622 tmp = RREG32(i2c_cntl_0); 623 if (tmp & RADEON_I2C_GO) 624 continue; 625 tmp = RREG32(i2c_cntl_0); 626 if (tmp & RADEON_I2C_DONE) 627 break; 628 else { 629 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 630 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 631 ret = -EIO; 632 goto done; 633 } 634 } 635 } 636 } 637 } 638 639 done: 640 WREG32(i2c_cntl_0, 0); 641 WREG32(i2c_cntl_1, 0); 642 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 643 RADEON_I2C_NACK | 644 RADEON_I2C_HALT | 645 RADEON_I2C_SOFT_RST)); 646 647 if (rdev->is_atom_bios) { 648 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 649 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 650 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 651 } 652 653 mutex_unlock(&rdev->pm.mutex); 654 mutex_unlock(&rdev->dc_hw_i2c_mutex); 655 656 return ret; 657 } 658 659 /* hw i2c engine for r5xx hardware 660 * hw can buffer up to 15 bytes 661 */ 662 static int r500_hw_i2c_xfer(struct i2c_controller *i2c_adap, 663 struct i2c_msg *msgs, int num) 664 { 665 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 666 struct radeon_device *rdev = i2c->dev->dev_private; 667 struct radeon_i2c_bus_rec *rec = &i2c->rec; 668 struct i2c_msg *p; 669 int i, j, remaining, current_count, buffer_offset, ret = num; 670 u32 prescale; 671 u32 tmp, reg; 672 u32 saved1, saved2; 673 674 mutex_lock(&rdev->dc_hw_i2c_mutex); 675 /* take the pm lock since we need a constant sclk */ 676 mutex_lock(&rdev->pm.mutex); 677 678 prescale = radeon_get_i2c_prescale(rdev); 679 680 /* clear gpio mask bits */ 681 tmp = RREG32(rec->mask_clk_reg); 682 tmp &= ~rec->mask_clk_mask; 683 WREG32(rec->mask_clk_reg, tmp); 684 tmp = RREG32(rec->mask_clk_reg); 685 686 tmp = RREG32(rec->mask_data_reg); 687 tmp &= ~rec->mask_data_mask; 688 WREG32(rec->mask_data_reg, tmp); 689 tmp = RREG32(rec->mask_data_reg); 690 691 /* clear pin values */ 692 tmp = RREG32(rec->a_clk_reg); 693 tmp &= ~rec->a_clk_mask; 694 WREG32(rec->a_clk_reg, tmp); 695 tmp = RREG32(rec->a_clk_reg); 696 697 tmp = RREG32(rec->a_data_reg); 698 tmp &= ~rec->a_data_mask; 699 WREG32(rec->a_data_reg, tmp); 700 tmp = RREG32(rec->a_data_reg); 701 702 /* set the pins to input */ 703 tmp = RREG32(rec->en_clk_reg); 704 tmp &= ~rec->en_clk_mask; 705 WREG32(rec->en_clk_reg, tmp); 706 tmp = RREG32(rec->en_clk_reg); 707 708 tmp = RREG32(rec->en_data_reg); 709 tmp &= ~rec->en_data_mask; 710 WREG32(rec->en_data_reg, tmp); 711 tmp = RREG32(rec->en_data_reg); 712 713 /* */ 714 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 715 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 716 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 717 saved2 = RREG32(0x494); 718 WREG32(0x494, saved2 | 0x1); 719 720 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 721 for (i = 0; i < 50; i++) { 722 udelay(1); 723 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 724 break; 725 } 726 if (i == 50) { 727 DRM_ERROR("failed to get i2c bus\n"); 728 ret = -EBUSY; 729 goto done; 730 } 731 732 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 733 switch (rec->mask_clk_reg) { 734 case AVIVO_DC_GPIO_DDC1_MASK: 735 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 736 break; 737 case AVIVO_DC_GPIO_DDC2_MASK: 738 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 739 break; 740 case AVIVO_DC_GPIO_DDC3_MASK: 741 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 742 break; 743 default: 744 DRM_ERROR("gpio not supported with hw i2c\n"); 745 ret = -EINVAL; 746 goto done; 747 } 748 749 /* check for bus probe */ 750 p = &msgs[0]; 751 if ((num == 1) && (p->len == 0)) { 752 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 753 AVIVO_DC_I2C_NACK | 754 AVIVO_DC_I2C_HALT)); 755 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 756 udelay(1); 757 WREG32(AVIVO_DC_I2C_RESET, 0); 758 759 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 760 WREG32(AVIVO_DC_I2C_DATA, 0); 761 762 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 763 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 764 AVIVO_DC_I2C_DATA_COUNT(1) | 765 (prescale << 16))); 766 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 767 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 768 for (j = 0; j < 200; j++) { 769 udelay(50); 770 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 771 if (tmp & AVIVO_DC_I2C_GO) 772 continue; 773 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 774 if (tmp & AVIVO_DC_I2C_DONE) 775 break; 776 else { 777 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 778 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 779 ret = -EIO; 780 goto done; 781 } 782 } 783 goto done; 784 } 785 786 for (i = 0; i < num; i++) { 787 p = &msgs[i]; 788 remaining = p->len; 789 buffer_offset = 0; 790 if (p->flags & I2C_M_RD) { 791 while (remaining) { 792 if (remaining > 15) 793 current_count = 15; 794 else 795 current_count = remaining; 796 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 797 AVIVO_DC_I2C_NACK | 798 AVIVO_DC_I2C_HALT)); 799 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 800 udelay(1); 801 WREG32(AVIVO_DC_I2C_RESET, 0); 802 803 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 804 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 805 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 806 AVIVO_DC_I2C_DATA_COUNT(current_count) | 807 (prescale << 16))); 808 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 809 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 810 for (j = 0; j < 200; j++) { 811 udelay(50); 812 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 813 if (tmp & AVIVO_DC_I2C_GO) 814 continue; 815 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 816 if (tmp & AVIVO_DC_I2C_DONE) 817 break; 818 else { 819 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 820 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 821 ret = -EIO; 822 goto done; 823 } 824 } 825 for (j = 0; j < current_count; j++) 826 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 827 remaining -= current_count; 828 buffer_offset += current_count; 829 } 830 } else { 831 while (remaining) { 832 if (remaining > 15) 833 current_count = 15; 834 else 835 current_count = remaining; 836 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 837 AVIVO_DC_I2C_NACK | 838 AVIVO_DC_I2C_HALT)); 839 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 840 udelay(1); 841 WREG32(AVIVO_DC_I2C_RESET, 0); 842 843 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 844 for (j = 0; j < current_count; j++) 845 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 846 847 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 848 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 849 AVIVO_DC_I2C_DATA_COUNT(current_count) | 850 (prescale << 16))); 851 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 852 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 853 for (j = 0; j < 200; j++) { 854 udelay(50); 855 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 856 if (tmp & AVIVO_DC_I2C_GO) 857 continue; 858 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 859 if (tmp & AVIVO_DC_I2C_DONE) 860 break; 861 else { 862 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 863 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 864 ret = -EIO; 865 goto done; 866 } 867 } 868 remaining -= current_count; 869 buffer_offset += current_count; 870 } 871 } 872 } 873 874 done: 875 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 876 AVIVO_DC_I2C_NACK | 877 AVIVO_DC_I2C_HALT)); 878 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 879 udelay(1); 880 WREG32(AVIVO_DC_I2C_RESET, 0); 881 882 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 883 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 884 WREG32(0x494, saved2); 885 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 886 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 887 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 888 889 mutex_unlock(&rdev->pm.mutex); 890 mutex_unlock(&rdev->dc_hw_i2c_mutex); 891 892 return ret; 893 } 894 895 static int radeon_hw_i2c_xfer(struct i2c_controller *i2c_adap, 896 struct i2c_msg *msgs, int num) 897 { 898 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 899 struct radeon_device *rdev = i2c->dev->dev_private; 900 struct radeon_i2c_bus_rec *rec = &i2c->rec; 901 int ret = 0; 902 903 switch (rdev->family) { 904 case CHIP_R100: 905 case CHIP_RV100: 906 case CHIP_RS100: 907 case CHIP_RV200: 908 case CHIP_RS200: 909 case CHIP_R200: 910 case CHIP_RV250: 911 case CHIP_RS300: 912 case CHIP_RV280: 913 case CHIP_R300: 914 case CHIP_R350: 915 case CHIP_RV350: 916 case CHIP_RV380: 917 case CHIP_R420: 918 case CHIP_R423: 919 case CHIP_RV410: 920 case CHIP_RS400: 921 case CHIP_RS480: 922 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 923 break; 924 case CHIP_RS600: 925 case CHIP_RS690: 926 case CHIP_RS740: 927 /* XXX fill in hw i2c implementation */ 928 break; 929 case CHIP_RV515: 930 case CHIP_R520: 931 case CHIP_RV530: 932 case CHIP_RV560: 933 case CHIP_RV570: 934 case CHIP_R580: 935 if (rec->mm_i2c) 936 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 937 else 938 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 939 break; 940 case CHIP_R600: 941 case CHIP_RV610: 942 case CHIP_RV630: 943 case CHIP_RV670: 944 /* XXX fill in hw i2c implementation */ 945 break; 946 case CHIP_RV620: 947 case CHIP_RV635: 948 case CHIP_RS780: 949 case CHIP_RS880: 950 case CHIP_RV770: 951 case CHIP_RV730: 952 case CHIP_RV710: 953 case CHIP_RV740: 954 /* XXX fill in hw i2c implementation */ 955 break; 956 case CHIP_CEDAR: 957 case CHIP_REDWOOD: 958 case CHIP_JUNIPER: 959 case CHIP_CYPRESS: 960 case CHIP_HEMLOCK: 961 /* XXX fill in hw i2c implementation */ 962 break; 963 default: 964 DRM_ERROR("i2c: unhandled radeon chip\n"); 965 ret = -EIO; 966 break; 967 } 968 969 return ret; 970 } 971 972 static u32 radeon_hw_i2c_func(struct i2c_controller *adap) 973 { 974 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 975 } 976 977 static const struct i2c_algorithm radeon_i2c_algo = { 978 .master_xfer = radeon_hw_i2c_xfer, 979 .functionality = radeon_hw_i2c_func, 980 }; 981 982 static const struct i2c_algorithm radeon_atom_i2c_algo = { 983 .master_xfer = radeon_atom_hw_i2c_xfer, 984 .functionality = radeon_atom_hw_i2c_func, 985 }; 986 #endif // notyet 987 988 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 989 struct radeon_i2c_bus_rec *rec, 990 const char *name) 991 { 992 struct radeon_device *rdev = dev->dev_private; 993 struct radeon_i2c_chan *i2c; 994 int ret = 0; 995 996 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 997 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 998 return NULL; 999 1000 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1001 if (i2c == NULL) 1002 return NULL; 1003 1004 i2c->rec = *rec; 1005 #ifdef notyet 1006 i2c->adapter.owner = THIS_MODULE; 1007 i2c->adapter.class = I2C_CLASS_DDC; 1008 i2c->adapter.dev.parent = &dev->pdev->dev; 1009 #else 1010 i2c->adapter.ic_cookie = i2c; 1011 i2c->adapter.ic_acquire_bus = radeon_acquire_bus; 1012 i2c->adapter.ic_release_bus = radeon_release_bus; 1013 i2c->adapter.ic_send_start = radeon_send_start; 1014 i2c->adapter.ic_send_stop = radeon_send_stop; 1015 i2c->adapter.ic_initiate_xfer = radeon_initiate_xfer; 1016 i2c->adapter.ic_read_byte = radeon_read_byte; 1017 i2c->adapter.ic_write_byte = radeon_write_byte; 1018 #endif 1019 i2c->dev = dev; 1020 #ifdef notyet 1021 i2c_set_adapdata(&i2c->adapter, i2c); 1022 #endif 1023 if (rec->mm_i2c || 1024 (rec->hw_capable && 1025 radeon_hw_i2c && 1026 ((rdev->family <= CHIP_RS480) || 1027 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 1028 /* set the radeon hw i2c adapter */ 1029 #ifdef notyet 1030 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1031 "Radeon i2c hw bus %s", name); 1032 i2c->adapter.algo = &radeon_i2c_algo; 1033 ret = i2c_add_adapter(&i2c->adapter); 1034 #endif 1035 if (ret) { 1036 DRM_ERROR("Failed to register hw i2c %s\n", name); 1037 goto out_free; 1038 } 1039 } else if (rec->hw_capable && 1040 radeon_hw_i2c && 1041 ASIC_IS_DCE3(rdev)) { 1042 /* hw i2c using atom */ 1043 #ifdef notyet 1044 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1045 "Radeon i2c hw bus %s", name); 1046 i2c->adapter.algo = &radeon_atom_i2c_algo; 1047 ret = i2c_add_adapter(&i2c->adapter); 1048 #endif 1049 if (ret) { 1050 DRM_ERROR("Failed to register hw i2c %s\n", name); 1051 goto out_free; 1052 } 1053 } else { 1054 /* set the radeon bit adapter */ 1055 #ifdef notyet 1056 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1057 "Radeon i2c bit bus %s", name); 1058 i2c->adapter.algo_data = &i2c->algo.bit; 1059 i2c->algo.bit.pre_xfer = pre_xfer; 1060 i2c->algo.bit.post_xfer = post_xfer; 1061 i2c->algo.bit.setsda = set_data; 1062 i2c->algo.bit.setscl = set_clock; 1063 i2c->algo.bit.getsda = get_data; 1064 i2c->algo.bit.getscl = get_clock; 1065 i2c->algo.bit.udelay = 10; 1066 i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 1067 i2c->algo.bit.data = i2c; 1068 ret = i2c_bit_add_bus(&i2c->adapter); 1069 #endif 1070 if (ret) { 1071 DRM_ERROR("Failed to register bit i2c %s\n", name); 1072 goto out_free; 1073 } 1074 } 1075 1076 return i2c; 1077 out_free: 1078 kfree(i2c); 1079 return NULL; 1080 } 1081 1082 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 1083 struct radeon_i2c_bus_rec *rec, 1084 const char *name) 1085 { 1086 struct radeon_i2c_chan *i2c; 1087 int ret = 0; 1088 1089 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1090 if (i2c == NULL) 1091 return NULL; 1092 1093 i2c->rec = *rec; 1094 #ifdef notyet 1095 i2c->adapter.owner = THIS_MODULE; 1096 i2c->adapter.class = I2C_CLASS_DDC; 1097 i2c->adapter.dev.parent = &dev->pdev->dev; 1098 #endif 1099 i2c->dev = dev; 1100 #ifdef notyet 1101 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1102 "Radeon aux bus %s", name); 1103 i2c_set_adapdata(&i2c->adapter, i2c); 1104 i2c->adapter.algo_data = &i2c->algo.dp; 1105 #endif 1106 i2c->adapter.ic_cookie = &i2c->algo.dp; 1107 i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; 1108 i2c->algo.dp.adapter = &i2c->adapter; 1109 i2c->algo.dp.address = 0; 1110 ret = i2c_dp_aux_add_bus(&i2c->adapter); 1111 if (ret) { 1112 DRM_INFO("Failed to register i2c %s\n", name); 1113 goto out_free; 1114 } 1115 1116 return i2c; 1117 out_free: 1118 kfree(i2c); 1119 return NULL; 1120 } 1121 1122 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 1123 { 1124 printf("%s stub\n", __func__); 1125 #ifdef notyet 1126 if (!i2c) 1127 return; 1128 i2c_del_adapter(&i2c->adapter); 1129 kfree(i2c); 1130 #endif 1131 } 1132 1133 /* Add the default buses */ 1134 void radeon_i2c_init(struct radeon_device *rdev) 1135 { 1136 if (radeon_hw_i2c) 1137 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1138 1139 if (rdev->is_atom_bios) 1140 radeon_atombios_i2c_init(rdev); 1141 else 1142 radeon_combios_i2c_init(rdev); 1143 } 1144 1145 /* remove all the buses */ 1146 void radeon_i2c_fini(struct radeon_device *rdev) 1147 { 1148 int i; 1149 1150 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1151 if (rdev->i2c_bus[i]) { 1152 radeon_i2c_destroy(rdev->i2c_bus[i]); 1153 rdev->i2c_bus[i] = NULL; 1154 } 1155 } 1156 } 1157 1158 /* Add additional buses */ 1159 void radeon_i2c_add(struct radeon_device *rdev, 1160 struct radeon_i2c_bus_rec *rec, 1161 const char *name) 1162 { 1163 struct drm_device *dev = rdev->ddev; 1164 int i; 1165 1166 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1167 if (!rdev->i2c_bus[i]) { 1168 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1169 return; 1170 } 1171 } 1172 } 1173 1174 /* looks up bus based on id */ 1175 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1176 struct radeon_i2c_bus_rec *i2c_bus) 1177 { 1178 int i; 1179 1180 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1181 if (rdev->i2c_bus[i] && 1182 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1183 return rdev->i2c_bus[i]; 1184 } 1185 } 1186 return NULL; 1187 } 1188 1189 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) 1190 { 1191 return NULL; 1192 } 1193 1194 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1195 u8 slave_addr, 1196 u8 addr, 1197 u8 *val) 1198 { 1199 printf("%s stub\n", __func__); 1200 #ifdef notyet 1201 u8 out_buf[2]; 1202 u8 in_buf[2]; 1203 struct i2c_msg msgs[] = { 1204 { 1205 .addr = slave_addr, 1206 .flags = 0, 1207 .len = 1, 1208 .buf = out_buf, 1209 }, 1210 { 1211 .addr = slave_addr, 1212 .flags = I2C_M_RD, 1213 .len = 1, 1214 .buf = in_buf, 1215 } 1216 }; 1217 1218 out_buf[0] = addr; 1219 out_buf[1] = 0; 1220 1221 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1222 *val = in_buf[0]; 1223 DRM_DEBUG("val = 0x%02x\n", *val); 1224 } else { 1225 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1226 addr, *val); 1227 } 1228 #endif 1229 } 1230 1231 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1232 u8 slave_addr, 1233 u8 addr, 1234 u8 val) 1235 { 1236 printf("%s stub\n", __func__); 1237 #ifdef notyet 1238 uint8_t out_buf[2]; 1239 struct i2c_msg msg = { 1240 .addr = slave_addr, 1241 .flags = 0, 1242 .len = 2, 1243 .buf = out_buf, 1244 }; 1245 1246 out_buf[0] = addr; 1247 out_buf[1] = val; 1248 1249 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1250 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1251 addr, val); 1252 #endif 1253 } 1254 1255 /* ddc router switching */ 1256 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1257 { 1258 u8 val; 1259 1260 if (!radeon_connector->router.ddc_valid) 1261 return; 1262 1263 if (!radeon_connector->router_bus) 1264 return; 1265 1266 radeon_i2c_get_byte(radeon_connector->router_bus, 1267 radeon_connector->router.i2c_addr, 1268 0x3, &val); 1269 val &= ~radeon_connector->router.ddc_mux_control_pin; 1270 radeon_i2c_put_byte(radeon_connector->router_bus, 1271 radeon_connector->router.i2c_addr, 1272 0x3, val); 1273 radeon_i2c_get_byte(radeon_connector->router_bus, 1274 radeon_connector->router.i2c_addr, 1275 0x1, &val); 1276 val &= ~radeon_connector->router.ddc_mux_control_pin; 1277 val |= radeon_connector->router.ddc_mux_state; 1278 radeon_i2c_put_byte(radeon_connector->router_bus, 1279 radeon_connector->router.i2c_addr, 1280 0x1, val); 1281 } 1282 1283 /* clock/data router switching */ 1284 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1285 { 1286 u8 val; 1287 1288 if (!radeon_connector->router.cd_valid) 1289 return; 1290 1291 if (!radeon_connector->router_bus) 1292 return; 1293 1294 radeon_i2c_get_byte(radeon_connector->router_bus, 1295 radeon_connector->router.i2c_addr, 1296 0x3, &val); 1297 val &= ~radeon_connector->router.cd_mux_control_pin; 1298 radeon_i2c_put_byte(radeon_connector->router_bus, 1299 radeon_connector->router.i2c_addr, 1300 0x3, val); 1301 radeon_i2c_get_byte(radeon_connector->router_bus, 1302 radeon_connector->router.i2c_addr, 1303 0x1, &val); 1304 val &= ~radeon_connector->router.cd_mux_control_pin; 1305 val |= radeon_connector->router.cd_mux_state; 1306 radeon_i2c_put_byte(radeon_connector->router_bus, 1307 radeon_connector->router.i2c_addr, 1308 0x1, val); 1309 } 1310 1311