1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <linux/export.h> 27 28 #include <drm/drmP.h> 29 #include <drm/drm_edid.h> 30 #include <drm/radeon_drm.h> 31 #include "radeon.h" 32 #include "atom.h" 33 34 #include <dev/i2c/i2cvar.h> 35 #include <dev/i2c/i2c_bitbang.h> 36 37 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 38 struct i2c_msg *msgs, int num); 39 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); 40 41 /** 42 * radeon_ddc_probe 43 * 44 */ 45 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 46 { 47 u8 out = 0x0; 48 u8 buf[8]; 49 int ret; 50 struct i2c_msg msgs[] = { 51 { 52 .addr = DDC_ADDR, 53 .flags = 0, 54 .len = 1, 55 .buf = &out, 56 }, 57 { 58 .addr = DDC_ADDR, 59 .flags = I2C_M_RD, 60 .len = 8, 61 .buf = buf, 62 } 63 }; 64 65 /* on hw with routers, select right port */ 66 if (radeon_connector->router.ddc_valid) 67 radeon_router_select_ddc_port(radeon_connector); 68 69 if (use_aux) { 70 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); 71 } else { 72 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 73 } 74 75 if (ret != 2) 76 /* Couldn't find an accessible DDC on this connector */ 77 return false; 78 /* Probe also for valid EDID header 79 * EDID header starts with: 80 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 81 * Only the first 6 bytes must be valid as 82 * drm_edid_block_valid() can fix the last 2 bytes */ 83 if (drm_edid_header_is_valid(buf) < 6) { 84 /* Couldn't find an accessible EDID on this 85 * connector */ 86 return false; 87 } 88 return true; 89 } 90 91 /* bit banging i2c */ 92 93 static int pre_xfer(struct i2c_adapter *i2c_adap) 94 { 95 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 96 struct radeon_device *rdev = i2c->dev->dev_private; 97 struct radeon_i2c_bus_rec *rec = &i2c->rec; 98 uint32_t temp; 99 100 mutex_lock(&i2c->mutex); 101 102 /* RV410 appears to have a bug where the hw i2c in reset 103 * holds the i2c port in a bad state - switch hw i2c away before 104 * doing DDC - do this for all r200s/r300s/r400s for safety sake 105 */ 106 if (rec->hw_capable) { 107 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 108 u32 reg; 109 110 if (rdev->family >= CHIP_RV350) 111 reg = RADEON_GPIO_MONID; 112 else if ((rdev->family == CHIP_R300) || 113 (rdev->family == CHIP_R350)) 114 reg = RADEON_GPIO_DVI_DDC; 115 else 116 reg = RADEON_GPIO_CRT2_DDC; 117 118 mutex_lock(&rdev->dc_hw_i2c_mutex); 119 if (rec->a_clk_reg == reg) { 120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 121 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 122 } else { 123 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 124 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 125 } 126 mutex_unlock(&rdev->dc_hw_i2c_mutex); 127 } 128 } 129 130 /* switch the pads to ddc mode */ 131 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 132 temp = RREG32(rec->mask_clk_reg); 133 temp &= ~(1 << 16); 134 WREG32(rec->mask_clk_reg, temp); 135 } 136 137 /* clear the output pin values */ 138 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 139 WREG32(rec->a_clk_reg, temp); 140 141 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 142 WREG32(rec->a_data_reg, temp); 143 144 /* set the pins to input */ 145 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 146 WREG32(rec->en_clk_reg, temp); 147 148 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 149 WREG32(rec->en_data_reg, temp); 150 151 /* mask the gpio pins for software use */ 152 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 153 WREG32(rec->mask_clk_reg, temp); 154 temp = RREG32(rec->mask_clk_reg); 155 156 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 157 WREG32(rec->mask_data_reg, temp); 158 temp = RREG32(rec->mask_data_reg); 159 160 return 0; 161 } 162 163 static void post_xfer(struct i2c_adapter *i2c_adap) 164 { 165 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 166 struct radeon_device *rdev = i2c->dev->dev_private; 167 struct radeon_i2c_bus_rec *rec = &i2c->rec; 168 uint32_t temp; 169 170 /* unmask the gpio pins for software use */ 171 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 172 WREG32(rec->mask_clk_reg, temp); 173 temp = RREG32(rec->mask_clk_reg); 174 175 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 176 WREG32(rec->mask_data_reg, temp); 177 temp = RREG32(rec->mask_data_reg); 178 179 mutex_unlock(&i2c->mutex); 180 } 181 182 static int get_clock(void *i2c_priv) 183 { 184 struct radeon_i2c_chan *i2c = i2c_priv; 185 struct radeon_device *rdev = i2c->dev->dev_private; 186 struct radeon_i2c_bus_rec *rec = &i2c->rec; 187 uint32_t val; 188 189 /* read the value off the pin */ 190 val = RREG32(rec->y_clk_reg); 191 val &= rec->y_clk_mask; 192 193 return (val != 0); 194 } 195 196 197 static int get_data(void *i2c_priv) 198 { 199 struct radeon_i2c_chan *i2c = i2c_priv; 200 struct radeon_device *rdev = i2c->dev->dev_private; 201 struct radeon_i2c_bus_rec *rec = &i2c->rec; 202 uint32_t val; 203 204 /* read the value off the pin */ 205 val = RREG32(rec->y_data_reg); 206 val &= rec->y_data_mask; 207 208 return (val != 0); 209 } 210 211 static void set_clock(void *i2c_priv, int clock) 212 { 213 struct radeon_i2c_chan *i2c = i2c_priv; 214 struct radeon_device *rdev = i2c->dev->dev_private; 215 struct radeon_i2c_bus_rec *rec = &i2c->rec; 216 uint32_t val; 217 218 /* set pin direction */ 219 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 220 val |= clock ? 0 : rec->en_clk_mask; 221 WREG32(rec->en_clk_reg, val); 222 } 223 224 static void set_data(void *i2c_priv, int data) 225 { 226 struct radeon_i2c_chan *i2c = i2c_priv; 227 struct radeon_device *rdev = i2c->dev->dev_private; 228 struct radeon_i2c_bus_rec *rec = &i2c->rec; 229 uint32_t val; 230 231 /* set pin direction */ 232 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 233 val |= data ? 0 : rec->en_data_mask; 234 WREG32(rec->en_data_reg, val); 235 } 236 237 void radeon_bb_set_bits(void *, uint32_t); 238 void radeon_bb_set_dir(void *, uint32_t); 239 uint32_t radeon_bb_read_bits(void *); 240 241 int radeon_acquire_bus(void *, int); 242 void radeon_release_bus(void *, int); 243 int radeon_send_start(void *, int); 244 int radeon_send_stop(void *, int); 245 int radeon_initiate_xfer(void *, i2c_addr_t, int); 246 int radeon_read_byte(void *, u_int8_t *, int); 247 int radeon_write_byte(void *, u_int8_t, int); 248 249 #define RADEON_BB_SDA (1 << I2C_BIT_SDA) 250 #define RADEON_BB_SCL (1 << I2C_BIT_SCL) 251 252 struct i2c_bitbang_ops radeon_bbops = { 253 radeon_bb_set_bits, 254 radeon_bb_set_dir, 255 radeon_bb_read_bits, 256 { RADEON_BB_SDA, RADEON_BB_SCL, 0, 0 } 257 }; 258 259 void 260 radeon_bb_set_bits(void *cookie, uint32_t bits) 261 { 262 set_clock(cookie, bits & RADEON_BB_SCL); 263 set_data(cookie, bits & RADEON_BB_SDA); 264 } 265 266 void 267 radeon_bb_set_dir(void *cookie, uint32_t bits) 268 { 269 } 270 271 uint32_t 272 radeon_bb_read_bits(void *cookie) 273 { 274 uint32_t bits = 0; 275 276 if (get_clock(cookie)) 277 bits |= RADEON_BB_SCL; 278 if (get_data(cookie)) 279 bits |= RADEON_BB_SDA; 280 281 return bits; 282 } 283 284 int 285 radeon_acquire_bus(void *cookie, int flags) 286 { 287 struct radeon_i2c_chan *i2c = cookie; 288 pre_xfer(&i2c->adapter); 289 return (0); 290 } 291 292 void 293 radeon_release_bus(void *cookie, int flags) 294 { 295 struct radeon_i2c_chan *i2c = cookie; 296 post_xfer(&i2c->adapter); 297 } 298 299 int 300 radeon_send_start(void *cookie, int flags) 301 { 302 return (i2c_bitbang_send_start(cookie, flags, &radeon_bbops)); 303 } 304 305 int 306 radeon_send_stop(void *cookie, int flags) 307 { 308 return (i2c_bitbang_send_stop(cookie, flags, &radeon_bbops)); 309 } 310 311 int 312 radeon_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 313 { 314 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &radeon_bbops)); 315 } 316 317 int 318 radeon_read_byte(void *cookie, u_int8_t *bytep, int flags) 319 { 320 return (i2c_bitbang_read_byte(cookie, bytep, flags, &radeon_bbops)); 321 } 322 323 int 324 radeon_write_byte(void *cookie, u_int8_t byte, int flags) 325 { 326 return (i2c_bitbang_write_byte(cookie, byte, flags, &radeon_bbops)); 327 } 328 329 330 /* hw i2c */ 331 332 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 333 { 334 u32 sclk = rdev->pm.current_sclk; 335 u32 prescale = 0; 336 u32 nm; 337 u8 n, m, loop; 338 int i2c_clock; 339 340 switch (rdev->family) { 341 case CHIP_R100: 342 case CHIP_RV100: 343 case CHIP_RS100: 344 case CHIP_RV200: 345 case CHIP_RS200: 346 case CHIP_R200: 347 case CHIP_RV250: 348 case CHIP_RS300: 349 case CHIP_RV280: 350 case CHIP_R300: 351 case CHIP_R350: 352 case CHIP_RV350: 353 i2c_clock = 60; 354 nm = (sclk * 10) / (i2c_clock * 4); 355 for (loop = 1; loop < 255; loop++) { 356 if ((nm / loop) < loop) 357 break; 358 } 359 n = loop - 1; 360 m = loop - 2; 361 prescale = m | (n << 8); 362 break; 363 case CHIP_RV380: 364 case CHIP_RS400: 365 case CHIP_RS480: 366 case CHIP_R420: 367 case CHIP_R423: 368 case CHIP_RV410: 369 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 370 break; 371 case CHIP_RS600: 372 case CHIP_RS690: 373 case CHIP_RS740: 374 /* todo */ 375 break; 376 case CHIP_RV515: 377 case CHIP_R520: 378 case CHIP_RV530: 379 case CHIP_RV560: 380 case CHIP_RV570: 381 case CHIP_R580: 382 i2c_clock = 50; 383 if (rdev->family == CHIP_R520) 384 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 385 else 386 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 387 break; 388 case CHIP_R600: 389 case CHIP_RV610: 390 case CHIP_RV630: 391 case CHIP_RV670: 392 /* todo */ 393 break; 394 case CHIP_RV620: 395 case CHIP_RV635: 396 case CHIP_RS780: 397 case CHIP_RS880: 398 case CHIP_RV770: 399 case CHIP_RV730: 400 case CHIP_RV710: 401 case CHIP_RV740: 402 /* todo */ 403 break; 404 case CHIP_CEDAR: 405 case CHIP_REDWOOD: 406 case CHIP_JUNIPER: 407 case CHIP_CYPRESS: 408 case CHIP_HEMLOCK: 409 /* todo */ 410 break; 411 default: 412 DRM_ERROR("i2c: unhandled radeon chip\n"); 413 break; 414 } 415 return prescale; 416 } 417 418 419 /* hw i2c engine for r1xx-4xx hardware 420 * hw can buffer up to 15 bytes 421 */ 422 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 423 struct i2c_msg *msgs, int num) 424 { 425 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 426 struct radeon_device *rdev = i2c->dev->dev_private; 427 struct radeon_i2c_bus_rec *rec = &i2c->rec; 428 struct i2c_msg *p; 429 int i, j, k, ret = num; 430 u32 prescale; 431 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 432 u32 tmp, reg; 433 434 mutex_lock(&rdev->dc_hw_i2c_mutex); 435 /* take the pm lock since we need a constant sclk */ 436 mutex_lock(&rdev->pm.mutex); 437 438 prescale = radeon_get_i2c_prescale(rdev); 439 440 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 441 RADEON_I2C_DRIVE_EN | 442 RADEON_I2C_START | 443 RADEON_I2C_STOP | 444 RADEON_I2C_GO); 445 446 if (rdev->is_atom_bios) { 447 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 448 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 449 } 450 451 if (rec->mm_i2c) { 452 i2c_cntl_0 = RADEON_I2C_CNTL_0; 453 i2c_cntl_1 = RADEON_I2C_CNTL_1; 454 i2c_data = RADEON_I2C_DATA; 455 } else { 456 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 457 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 458 i2c_data = RADEON_DVI_I2C_DATA; 459 460 switch (rdev->family) { 461 case CHIP_R100: 462 case CHIP_RV100: 463 case CHIP_RS100: 464 case CHIP_RV200: 465 case CHIP_RS200: 466 case CHIP_RS300: 467 switch (rec->mask_clk_reg) { 468 case RADEON_GPIO_DVI_DDC: 469 /* no gpio select bit */ 470 break; 471 default: 472 DRM_ERROR("gpio not supported with hw i2c\n"); 473 ret = -EINVAL; 474 goto done; 475 } 476 break; 477 case CHIP_R200: 478 /* only bit 4 on r200 */ 479 switch (rec->mask_clk_reg) { 480 case RADEON_GPIO_DVI_DDC: 481 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 482 break; 483 case RADEON_GPIO_MONID: 484 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 485 break; 486 default: 487 DRM_ERROR("gpio not supported with hw i2c\n"); 488 ret = -EINVAL; 489 goto done; 490 } 491 break; 492 case CHIP_RV250: 493 case CHIP_RV280: 494 /* bits 3 and 4 */ 495 switch (rec->mask_clk_reg) { 496 case RADEON_GPIO_DVI_DDC: 497 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 498 break; 499 case RADEON_GPIO_VGA_DDC: 500 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 501 break; 502 case RADEON_GPIO_CRT2_DDC: 503 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 504 break; 505 default: 506 DRM_ERROR("gpio not supported with hw i2c\n"); 507 ret = -EINVAL; 508 goto done; 509 } 510 break; 511 case CHIP_R300: 512 case CHIP_R350: 513 /* only bit 4 on r300/r350 */ 514 switch (rec->mask_clk_reg) { 515 case RADEON_GPIO_VGA_DDC: 516 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 517 break; 518 case RADEON_GPIO_DVI_DDC: 519 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 520 break; 521 default: 522 DRM_ERROR("gpio not supported with hw i2c\n"); 523 ret = -EINVAL; 524 goto done; 525 } 526 break; 527 case CHIP_RV350: 528 case CHIP_RV380: 529 case CHIP_R420: 530 case CHIP_R423: 531 case CHIP_RV410: 532 case CHIP_RS400: 533 case CHIP_RS480: 534 /* bits 3 and 4 */ 535 switch (rec->mask_clk_reg) { 536 case RADEON_GPIO_VGA_DDC: 537 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 538 break; 539 case RADEON_GPIO_DVI_DDC: 540 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 541 break; 542 case RADEON_GPIO_MONID: 543 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 544 break; 545 default: 546 DRM_ERROR("gpio not supported with hw i2c\n"); 547 ret = -EINVAL; 548 goto done; 549 } 550 break; 551 default: 552 DRM_ERROR("unsupported asic\n"); 553 ret = -EINVAL; 554 goto done; 555 break; 556 } 557 } 558 559 /* check for bus probe */ 560 p = &msgs[0]; 561 if ((num == 1) && (p->len == 0)) { 562 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 563 RADEON_I2C_NACK | 564 RADEON_I2C_HALT | 565 RADEON_I2C_SOFT_RST)); 566 WREG32(i2c_data, (p->addr << 1) & 0xff); 567 WREG32(i2c_data, 0); 568 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 569 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 570 RADEON_I2C_EN | 571 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 572 WREG32(i2c_cntl_0, reg); 573 for (k = 0; k < 32; k++) { 574 udelay(10); 575 tmp = RREG32(i2c_cntl_0); 576 if (tmp & RADEON_I2C_GO) 577 continue; 578 tmp = RREG32(i2c_cntl_0); 579 if (tmp & RADEON_I2C_DONE) 580 break; 581 else { 582 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 583 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 584 ret = -EIO; 585 goto done; 586 } 587 } 588 goto done; 589 } 590 591 for (i = 0; i < num; i++) { 592 p = &msgs[i]; 593 for (j = 0; j < p->len; j++) { 594 if (p->flags & I2C_M_RD) { 595 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 596 RADEON_I2C_NACK | 597 RADEON_I2C_HALT | 598 RADEON_I2C_SOFT_RST)); 599 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 600 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 601 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 602 RADEON_I2C_EN | 603 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 604 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 605 for (k = 0; k < 32; k++) { 606 udelay(10); 607 tmp = RREG32(i2c_cntl_0); 608 if (tmp & RADEON_I2C_GO) 609 continue; 610 tmp = RREG32(i2c_cntl_0); 611 if (tmp & RADEON_I2C_DONE) 612 break; 613 else { 614 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 615 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 616 ret = -EIO; 617 goto done; 618 } 619 } 620 p->buf[j] = RREG32(i2c_data) & 0xff; 621 } else { 622 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 623 RADEON_I2C_NACK | 624 RADEON_I2C_HALT | 625 RADEON_I2C_SOFT_RST)); 626 WREG32(i2c_data, (p->addr << 1) & 0xff); 627 WREG32(i2c_data, p->buf[j]); 628 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 629 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 630 RADEON_I2C_EN | 631 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 632 WREG32(i2c_cntl_0, reg); 633 for (k = 0; k < 32; k++) { 634 udelay(10); 635 tmp = RREG32(i2c_cntl_0); 636 if (tmp & RADEON_I2C_GO) 637 continue; 638 tmp = RREG32(i2c_cntl_0); 639 if (tmp & RADEON_I2C_DONE) 640 break; 641 else { 642 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 643 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 644 ret = -EIO; 645 goto done; 646 } 647 } 648 } 649 } 650 } 651 652 done: 653 WREG32(i2c_cntl_0, 0); 654 WREG32(i2c_cntl_1, 0); 655 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 656 RADEON_I2C_NACK | 657 RADEON_I2C_HALT | 658 RADEON_I2C_SOFT_RST)); 659 660 if (rdev->is_atom_bios) { 661 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 662 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 663 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 664 } 665 666 mutex_unlock(&rdev->pm.mutex); 667 mutex_unlock(&rdev->dc_hw_i2c_mutex); 668 669 return ret; 670 } 671 672 /* hw i2c engine for r5xx hardware 673 * hw can buffer up to 15 bytes 674 */ 675 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 676 struct i2c_msg *msgs, int num) 677 { 678 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 679 struct radeon_device *rdev = i2c->dev->dev_private; 680 struct radeon_i2c_bus_rec *rec = &i2c->rec; 681 struct i2c_msg *p; 682 int i, j, remaining, current_count, buffer_offset, ret = num; 683 u32 prescale; 684 u32 tmp, reg; 685 u32 saved1, saved2; 686 687 mutex_lock(&rdev->dc_hw_i2c_mutex); 688 /* take the pm lock since we need a constant sclk */ 689 mutex_lock(&rdev->pm.mutex); 690 691 prescale = radeon_get_i2c_prescale(rdev); 692 693 /* clear gpio mask bits */ 694 tmp = RREG32(rec->mask_clk_reg); 695 tmp &= ~rec->mask_clk_mask; 696 WREG32(rec->mask_clk_reg, tmp); 697 tmp = RREG32(rec->mask_clk_reg); 698 699 tmp = RREG32(rec->mask_data_reg); 700 tmp &= ~rec->mask_data_mask; 701 WREG32(rec->mask_data_reg, tmp); 702 tmp = RREG32(rec->mask_data_reg); 703 704 /* clear pin values */ 705 tmp = RREG32(rec->a_clk_reg); 706 tmp &= ~rec->a_clk_mask; 707 WREG32(rec->a_clk_reg, tmp); 708 tmp = RREG32(rec->a_clk_reg); 709 710 tmp = RREG32(rec->a_data_reg); 711 tmp &= ~rec->a_data_mask; 712 WREG32(rec->a_data_reg, tmp); 713 tmp = RREG32(rec->a_data_reg); 714 715 /* set the pins to input */ 716 tmp = RREG32(rec->en_clk_reg); 717 tmp &= ~rec->en_clk_mask; 718 WREG32(rec->en_clk_reg, tmp); 719 tmp = RREG32(rec->en_clk_reg); 720 721 tmp = RREG32(rec->en_data_reg); 722 tmp &= ~rec->en_data_mask; 723 WREG32(rec->en_data_reg, tmp); 724 tmp = RREG32(rec->en_data_reg); 725 726 /* */ 727 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 728 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 729 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 730 saved2 = RREG32(0x494); 731 WREG32(0x494, saved2 | 0x1); 732 733 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 734 for (i = 0; i < 50; i++) { 735 udelay(1); 736 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 737 break; 738 } 739 if (i == 50) { 740 DRM_ERROR("failed to get i2c bus\n"); 741 ret = -EBUSY; 742 goto done; 743 } 744 745 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 746 switch (rec->mask_clk_reg) { 747 case AVIVO_DC_GPIO_DDC1_MASK: 748 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 749 break; 750 case AVIVO_DC_GPIO_DDC2_MASK: 751 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 752 break; 753 case AVIVO_DC_GPIO_DDC3_MASK: 754 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 755 break; 756 default: 757 DRM_ERROR("gpio not supported with hw i2c\n"); 758 ret = -EINVAL; 759 goto done; 760 } 761 762 /* check for bus probe */ 763 p = &msgs[0]; 764 if ((num == 1) && (p->len == 0)) { 765 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 766 AVIVO_DC_I2C_NACK | 767 AVIVO_DC_I2C_HALT)); 768 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 769 udelay(1); 770 WREG32(AVIVO_DC_I2C_RESET, 0); 771 772 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 773 WREG32(AVIVO_DC_I2C_DATA, 0); 774 775 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 776 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 777 AVIVO_DC_I2C_DATA_COUNT(1) | 778 (prescale << 16))); 779 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 780 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 781 for (j = 0; j < 200; j++) { 782 udelay(50); 783 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 784 if (tmp & AVIVO_DC_I2C_GO) 785 continue; 786 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 787 if (tmp & AVIVO_DC_I2C_DONE) 788 break; 789 else { 790 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 791 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 792 ret = -EIO; 793 goto done; 794 } 795 } 796 goto done; 797 } 798 799 for (i = 0; i < num; i++) { 800 p = &msgs[i]; 801 remaining = p->len; 802 buffer_offset = 0; 803 if (p->flags & I2C_M_RD) { 804 while (remaining) { 805 if (remaining > 15) 806 current_count = 15; 807 else 808 current_count = remaining; 809 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 810 AVIVO_DC_I2C_NACK | 811 AVIVO_DC_I2C_HALT)); 812 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 813 udelay(1); 814 WREG32(AVIVO_DC_I2C_RESET, 0); 815 816 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 817 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 818 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 819 AVIVO_DC_I2C_DATA_COUNT(current_count) | 820 (prescale << 16))); 821 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 822 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 823 for (j = 0; j < 200; j++) { 824 udelay(50); 825 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 826 if (tmp & AVIVO_DC_I2C_GO) 827 continue; 828 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 829 if (tmp & AVIVO_DC_I2C_DONE) 830 break; 831 else { 832 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 833 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 834 ret = -EIO; 835 goto done; 836 } 837 } 838 for (j = 0; j < current_count; j++) 839 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 840 remaining -= current_count; 841 buffer_offset += current_count; 842 } 843 } else { 844 while (remaining) { 845 if (remaining > 15) 846 current_count = 15; 847 else 848 current_count = remaining; 849 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 850 AVIVO_DC_I2C_NACK | 851 AVIVO_DC_I2C_HALT)); 852 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 853 udelay(1); 854 WREG32(AVIVO_DC_I2C_RESET, 0); 855 856 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 857 for (j = 0; j < current_count; j++) 858 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 859 860 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 861 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 862 AVIVO_DC_I2C_DATA_COUNT(current_count) | 863 (prescale << 16))); 864 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 865 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 866 for (j = 0; j < 200; j++) { 867 udelay(50); 868 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 869 if (tmp & AVIVO_DC_I2C_GO) 870 continue; 871 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 872 if (tmp & AVIVO_DC_I2C_DONE) 873 break; 874 else { 875 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 876 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 877 ret = -EIO; 878 goto done; 879 } 880 } 881 remaining -= current_count; 882 buffer_offset += current_count; 883 } 884 } 885 } 886 887 done: 888 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 889 AVIVO_DC_I2C_NACK | 890 AVIVO_DC_I2C_HALT)); 891 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 892 udelay(1); 893 WREG32(AVIVO_DC_I2C_RESET, 0); 894 895 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 896 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 897 WREG32(0x494, saved2); 898 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 899 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 900 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 901 902 mutex_unlock(&rdev->pm.mutex); 903 mutex_unlock(&rdev->dc_hw_i2c_mutex); 904 905 return ret; 906 } 907 908 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 909 struct i2c_msg *msgs, int num) 910 { 911 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 912 struct radeon_device *rdev = i2c->dev->dev_private; 913 struct radeon_i2c_bus_rec *rec = &i2c->rec; 914 int ret = 0; 915 916 mutex_lock(&i2c->mutex); 917 918 switch (rdev->family) { 919 case CHIP_R100: 920 case CHIP_RV100: 921 case CHIP_RS100: 922 case CHIP_RV200: 923 case CHIP_RS200: 924 case CHIP_R200: 925 case CHIP_RV250: 926 case CHIP_RS300: 927 case CHIP_RV280: 928 case CHIP_R300: 929 case CHIP_R350: 930 case CHIP_RV350: 931 case CHIP_RV380: 932 case CHIP_R420: 933 case CHIP_R423: 934 case CHIP_RV410: 935 case CHIP_RS400: 936 case CHIP_RS480: 937 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 938 break; 939 case CHIP_RS600: 940 case CHIP_RS690: 941 case CHIP_RS740: 942 /* XXX fill in hw i2c implementation */ 943 break; 944 case CHIP_RV515: 945 case CHIP_R520: 946 case CHIP_RV530: 947 case CHIP_RV560: 948 case CHIP_RV570: 949 case CHIP_R580: 950 if (rec->mm_i2c) 951 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 952 else 953 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 954 break; 955 case CHIP_R600: 956 case CHIP_RV610: 957 case CHIP_RV630: 958 case CHIP_RV670: 959 /* XXX fill in hw i2c implementation */ 960 break; 961 case CHIP_RV620: 962 case CHIP_RV635: 963 case CHIP_RS780: 964 case CHIP_RS880: 965 case CHIP_RV770: 966 case CHIP_RV730: 967 case CHIP_RV710: 968 case CHIP_RV740: 969 /* XXX fill in hw i2c implementation */ 970 break; 971 case CHIP_CEDAR: 972 case CHIP_REDWOOD: 973 case CHIP_JUNIPER: 974 case CHIP_CYPRESS: 975 case CHIP_HEMLOCK: 976 /* XXX fill in hw i2c implementation */ 977 break; 978 default: 979 DRM_ERROR("i2c: unhandled radeon chip\n"); 980 ret = -EIO; 981 break; 982 } 983 984 mutex_unlock(&i2c->mutex); 985 986 return ret; 987 } 988 989 static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 990 { 991 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 992 } 993 994 static const struct i2c_algorithm radeon_i2c_algo = { 995 .master_xfer = radeon_hw_i2c_xfer, 996 .functionality = radeon_hw_i2c_func, 997 }; 998 999 static const struct i2c_algorithm radeon_atom_i2c_algo = { 1000 .master_xfer = radeon_atom_hw_i2c_xfer, 1001 .functionality = radeon_atom_hw_i2c_func, 1002 }; 1003 1004 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 1005 struct radeon_i2c_bus_rec *rec, 1006 const char *name) 1007 { 1008 struct radeon_device *rdev = dev->dev_private; 1009 struct radeon_i2c_chan *i2c; 1010 int ret; 1011 1012 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 1013 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 1014 return NULL; 1015 1016 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1017 if (i2c == NULL) 1018 return NULL; 1019 1020 i2c->rec = *rec; 1021 #ifdef __linux__ 1022 i2c->adapter.owner = THIS_MODULE; 1023 i2c->adapter.class = I2C_CLASS_DDC; 1024 i2c->adapter.dev.parent = &dev->pdev->dev; 1025 #endif 1026 i2c->dev = dev; 1027 i2c_set_adapdata(&i2c->adapter, i2c); 1028 rw_init(&i2c->mutex, "riic"); 1029 if (rec->mm_i2c || 1030 (rec->hw_capable && 1031 radeon_hw_i2c && 1032 ((rdev->family <= CHIP_RS480) || 1033 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 1034 /* set the radeon hw i2c adapter */ 1035 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1036 "Radeon i2c hw bus %s", name); 1037 i2c->adapter.algo = &radeon_i2c_algo; 1038 ret = i2c_add_adapter(&i2c->adapter); 1039 if (ret) { 1040 DRM_ERROR("Failed to register hw i2c %s\n", name); 1041 goto out_free; 1042 } 1043 } else if (rec->hw_capable && 1044 radeon_hw_i2c && 1045 ASIC_IS_DCE3(rdev)) { 1046 /* hw i2c using atom */ 1047 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1048 "Radeon i2c hw bus %s", name); 1049 i2c->adapter.algo = &radeon_atom_i2c_algo; 1050 ret = i2c_add_adapter(&i2c->adapter); 1051 if (ret) { 1052 DRM_ERROR("Failed to register hw i2c %s\n", name); 1053 goto out_free; 1054 } 1055 } else { 1056 /* set the radeon bit adapter */ 1057 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1058 "Radeon i2c bit bus %s", name); 1059 i2c->adapter.algo_data = &i2c->bit; 1060 #ifdef notyet 1061 i2c->bit.pre_xfer = pre_xfer; 1062 i2c->bit.post_xfer = post_xfer; 1063 i2c->bit.setsda = set_data; 1064 i2c->bit.setscl = set_clock; 1065 i2c->bit.getsda = get_data; 1066 i2c->bit.getscl = get_clock; 1067 i2c->bit.udelay = 10; 1068 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 1069 i2c->bit.data = i2c; 1070 #else 1071 i2c->bit.ic.ic_cookie = i2c; 1072 i2c->bit.ic.ic_acquire_bus = radeon_acquire_bus; 1073 i2c->bit.ic.ic_release_bus = radeon_release_bus; 1074 i2c->bit.ic.ic_send_start = radeon_send_start; 1075 i2c->bit.ic.ic_send_stop = radeon_send_stop; 1076 i2c->bit.ic.ic_initiate_xfer = radeon_initiate_xfer; 1077 i2c->bit.ic.ic_read_byte = radeon_read_byte; 1078 i2c->bit.ic.ic_write_byte = radeon_write_byte; 1079 #endif 1080 ret = i2c_bit_add_bus(&i2c->adapter); 1081 if (ret) { 1082 DRM_ERROR("Failed to register bit i2c %s\n", name); 1083 goto out_free; 1084 } 1085 } 1086 1087 return i2c; 1088 out_free: 1089 kfree(i2c); 1090 return NULL; 1091 1092 } 1093 1094 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 1095 { 1096 if (!i2c) 1097 return; 1098 i2c_del_adapter(&i2c->adapter); 1099 if (i2c->has_aux) 1100 drm_dp_aux_unregister(&i2c->aux); 1101 kfree(i2c); 1102 } 1103 1104 /* Add the default buses */ 1105 void radeon_i2c_init(struct radeon_device *rdev) 1106 { 1107 if (radeon_hw_i2c) 1108 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1109 1110 if (rdev->is_atom_bios) 1111 radeon_atombios_i2c_init(rdev); 1112 else 1113 radeon_combios_i2c_init(rdev); 1114 } 1115 1116 /* remove all the buses */ 1117 void radeon_i2c_fini(struct radeon_device *rdev) 1118 { 1119 int i; 1120 1121 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1122 if (rdev->i2c_bus[i]) { 1123 radeon_i2c_destroy(rdev->i2c_bus[i]); 1124 rdev->i2c_bus[i] = NULL; 1125 } 1126 } 1127 } 1128 1129 /* Add additional buses */ 1130 void radeon_i2c_add(struct radeon_device *rdev, 1131 struct radeon_i2c_bus_rec *rec, 1132 const char *name) 1133 { 1134 struct drm_device *dev = rdev->ddev; 1135 int i; 1136 1137 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1138 if (!rdev->i2c_bus[i]) { 1139 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1140 return; 1141 } 1142 } 1143 } 1144 1145 /* looks up bus based on id */ 1146 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1147 struct radeon_i2c_bus_rec *i2c_bus) 1148 { 1149 int i; 1150 1151 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1152 if (rdev->i2c_bus[i] && 1153 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1154 return rdev->i2c_bus[i]; 1155 } 1156 } 1157 return NULL; 1158 } 1159 1160 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1161 u8 slave_addr, 1162 u8 addr, 1163 u8 *val) 1164 { 1165 u8 out_buf[2]; 1166 u8 in_buf[2]; 1167 struct i2c_msg msgs[] = { 1168 { 1169 .addr = slave_addr, 1170 .flags = 0, 1171 .len = 1, 1172 .buf = out_buf, 1173 }, 1174 { 1175 .addr = slave_addr, 1176 .flags = I2C_M_RD, 1177 .len = 1, 1178 .buf = in_buf, 1179 } 1180 }; 1181 1182 out_buf[0] = addr; 1183 out_buf[1] = 0; 1184 1185 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1186 *val = in_buf[0]; 1187 DRM_DEBUG("val = 0x%02x\n", *val); 1188 } else { 1189 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1190 addr, *val); 1191 } 1192 } 1193 1194 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1195 u8 slave_addr, 1196 u8 addr, 1197 u8 val) 1198 { 1199 uint8_t out_buf[2]; 1200 struct i2c_msg msg = { 1201 .addr = slave_addr, 1202 .flags = 0, 1203 .len = 2, 1204 .buf = out_buf, 1205 }; 1206 1207 out_buf[0] = addr; 1208 out_buf[1] = val; 1209 1210 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1211 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1212 addr, val); 1213 } 1214 1215 /* ddc router switching */ 1216 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1217 { 1218 u8 val; 1219 1220 if (!radeon_connector->router.ddc_valid) 1221 return; 1222 1223 if (!radeon_connector->router_bus) 1224 return; 1225 1226 radeon_i2c_get_byte(radeon_connector->router_bus, 1227 radeon_connector->router.i2c_addr, 1228 0x3, &val); 1229 val &= ~radeon_connector->router.ddc_mux_control_pin; 1230 radeon_i2c_put_byte(radeon_connector->router_bus, 1231 radeon_connector->router.i2c_addr, 1232 0x3, val); 1233 radeon_i2c_get_byte(radeon_connector->router_bus, 1234 radeon_connector->router.i2c_addr, 1235 0x1, &val); 1236 val &= ~radeon_connector->router.ddc_mux_control_pin; 1237 val |= radeon_connector->router.ddc_mux_state; 1238 radeon_i2c_put_byte(radeon_connector->router_bus, 1239 radeon_connector->router.i2c_addr, 1240 0x1, val); 1241 } 1242 1243 /* clock/data router switching */ 1244 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1245 { 1246 u8 val; 1247 1248 if (!radeon_connector->router.cd_valid) 1249 return; 1250 1251 if (!radeon_connector->router_bus) 1252 return; 1253 1254 radeon_i2c_get_byte(radeon_connector->router_bus, 1255 radeon_connector->router.i2c_addr, 1256 0x3, &val); 1257 val &= ~radeon_connector->router.cd_mux_control_pin; 1258 radeon_i2c_put_byte(radeon_connector->router_bus, 1259 radeon_connector->router.i2c_addr, 1260 0x3, val); 1261 radeon_i2c_get_byte(radeon_connector->router_bus, 1262 radeon_connector->router.i2c_addr, 1263 0x1, &val); 1264 val &= ~radeon_connector->router.cd_mux_control_pin; 1265 val |= radeon_connector->router.cd_mux_state; 1266 radeon_i2c_put_byte(radeon_connector->router_bus, 1267 radeon_connector->router.i2c_addr, 1268 0x1, val); 1269 } 1270 1271