1 /* $OpenBSD: radeon_i2c.c,v 1.6 2017/07/01 16:14:10 kettenis Exp $ */ 2 /* 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 28 #include <dev/pci/drm/drmP.h> 29 #include <dev/pci/drm/drm_edid.h> 30 #include <dev/pci/drm/radeon_drm.h> 31 #include "radeon.h" 32 #include "atom.h" 33 34 #include <dev/i2c/i2cvar.h> 35 #include <dev/i2c/i2c_bitbang.h> 36 37 extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 38 struct i2c_msg *msgs, int num); 39 extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); 40 41 /** 42 * radeon_ddc_probe 43 * 44 */ 45 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 46 { 47 u8 out = 0x0; 48 u8 buf[8]; 49 int ret; 50 struct i2c_msg msgs[] = { 51 { 52 .addr = DDC_ADDR, 53 .flags = 0, 54 .len = 1, 55 .buf = &out, 56 }, 57 { 58 .addr = DDC_ADDR, 59 .flags = I2C_M_RD, 60 .len = 8, 61 .buf = buf, 62 } 63 }; 64 65 /* on hw with routers, select right port */ 66 if (radeon_connector->router.ddc_valid) 67 radeon_router_select_ddc_port(radeon_connector); 68 69 if (use_aux) { 70 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); 71 } else { 72 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 73 } 74 75 if (ret != 2) 76 /* Couldn't find an accessible DDC on this connector */ 77 return false; 78 /* Probe also for valid EDID header 79 * EDID header starts with: 80 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 81 * Only the first 6 bytes must be valid as 82 * drm_edid_block_valid() can fix the last 2 bytes */ 83 if (drm_edid_header_is_valid(buf) < 6) { 84 /* Couldn't find an accessible EDID on this 85 * connector */ 86 return false; 87 } 88 return true; 89 } 90 91 /* bit banging i2c */ 92 93 static int pre_xfer(void *cookie) 94 { 95 struct radeon_i2c_chan *i2c = cookie; 96 struct radeon_device *rdev = i2c->dev->dev_private; 97 struct radeon_i2c_bus_rec *rec = &i2c->rec; 98 uint32_t temp; 99 100 /* RV410 appears to have a bug where the hw i2c in reset 101 * holds the i2c port in a bad state - switch hw i2c away before 102 * doing DDC - do this for all r200s/r300s/r400s for safety sake 103 */ 104 if (rec->hw_capable) { 105 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 106 u32 reg; 107 108 if (rdev->family >= CHIP_RV350) 109 reg = RADEON_GPIO_MONID; 110 else if ((rdev->family == CHIP_R300) || 111 (rdev->family == CHIP_R350)) 112 reg = RADEON_GPIO_DVI_DDC; 113 else 114 reg = RADEON_GPIO_CRT2_DDC; 115 116 mutex_lock(&rdev->dc_hw_i2c_mutex); 117 if (rec->a_clk_reg == reg) { 118 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 119 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 120 } else { 121 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 122 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 123 } 124 mutex_unlock(&rdev->dc_hw_i2c_mutex); 125 } 126 } 127 128 /* switch the pads to ddc mode */ 129 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 130 temp = RREG32(rec->mask_clk_reg); 131 temp &= ~(1 << 16); 132 WREG32(rec->mask_clk_reg, temp); 133 } 134 135 /* clear the output pin values */ 136 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 137 WREG32(rec->a_clk_reg, temp); 138 139 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 140 WREG32(rec->a_data_reg, temp); 141 142 /* set the pins to input */ 143 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 144 WREG32(rec->en_clk_reg, temp); 145 146 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 147 WREG32(rec->en_data_reg, temp); 148 149 /* mask the gpio pins for software use */ 150 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 151 WREG32(rec->mask_clk_reg, temp); 152 temp = RREG32(rec->mask_clk_reg); 153 154 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 155 WREG32(rec->mask_data_reg, temp); 156 temp = RREG32(rec->mask_data_reg); 157 158 return 0; 159 } 160 161 static void post_xfer(void *cookie) 162 { 163 struct radeon_i2c_chan *i2c = cookie; 164 struct radeon_device *rdev = i2c->dev->dev_private; 165 struct radeon_i2c_bus_rec *rec = &i2c->rec; 166 uint32_t temp; 167 168 /* unmask the gpio pins for software use */ 169 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 170 WREG32(rec->mask_clk_reg, temp); 171 temp = RREG32(rec->mask_clk_reg); 172 173 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 174 WREG32(rec->mask_data_reg, temp); 175 temp = RREG32(rec->mask_data_reg); 176 } 177 178 static int get_clock(void *i2c_priv) 179 { 180 struct radeon_i2c_chan *i2c = i2c_priv; 181 struct radeon_device *rdev = i2c->dev->dev_private; 182 struct radeon_i2c_bus_rec *rec = &i2c->rec; 183 uint32_t val; 184 185 /* read the value off the pin */ 186 val = RREG32(rec->y_clk_reg); 187 val &= rec->y_clk_mask; 188 189 return (val != 0); 190 } 191 192 193 static int get_data(void *i2c_priv) 194 { 195 struct radeon_i2c_chan *i2c = i2c_priv; 196 struct radeon_device *rdev = i2c->dev->dev_private; 197 struct radeon_i2c_bus_rec *rec = &i2c->rec; 198 uint32_t val; 199 200 /* read the value off the pin */ 201 val = RREG32(rec->y_data_reg); 202 val &= rec->y_data_mask; 203 204 return (val != 0); 205 } 206 207 static void set_clock(void *i2c_priv, int clock) 208 { 209 struct radeon_i2c_chan *i2c = i2c_priv; 210 struct radeon_device *rdev = i2c->dev->dev_private; 211 struct radeon_i2c_bus_rec *rec = &i2c->rec; 212 uint32_t val; 213 214 /* set pin direction */ 215 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 216 val |= clock ? 0 : rec->en_clk_mask; 217 WREG32(rec->en_clk_reg, val); 218 } 219 220 static void set_data(void *i2c_priv, int data) 221 { 222 struct radeon_i2c_chan *i2c = i2c_priv; 223 struct radeon_device *rdev = i2c->dev->dev_private; 224 struct radeon_i2c_bus_rec *rec = &i2c->rec; 225 uint32_t val; 226 227 /* set pin direction */ 228 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 229 val |= data ? 0 : rec->en_data_mask; 230 WREG32(rec->en_data_reg, val); 231 } 232 233 void radeon_bb_set_bits(void *, uint32_t); 234 void radeon_bb_set_dir(void *, uint32_t); 235 uint32_t radeon_bb_read_bits(void *); 236 237 int radeon_acquire_bus(void *, int); 238 void radeon_release_bus(void *, int); 239 int radeon_send_start(void *, int); 240 int radeon_send_stop(void *, int); 241 int radeon_initiate_xfer(void *, i2c_addr_t, int); 242 int radeon_read_byte(void *, u_int8_t *, int); 243 int radeon_write_byte(void *, u_int8_t, int); 244 245 #define RADEON_BB_SDA (1 << I2C_BIT_SDA) 246 #define RADEON_BB_SCL (1 << I2C_BIT_SCL) 247 248 struct i2c_bitbang_ops radeon_bbops = { 249 radeon_bb_set_bits, 250 radeon_bb_set_dir, 251 radeon_bb_read_bits, 252 { RADEON_BB_SDA, RADEON_BB_SCL, 0, 0 } 253 }; 254 255 void 256 radeon_bb_set_bits(void *cookie, uint32_t bits) 257 { 258 set_clock(cookie, bits & RADEON_BB_SCL); 259 set_data(cookie, bits & RADEON_BB_SDA); 260 } 261 262 void 263 radeon_bb_set_dir(void *cookie, uint32_t bits) 264 { 265 } 266 267 uint32_t 268 radeon_bb_read_bits(void *cookie) 269 { 270 uint32_t bits = 0; 271 272 if (get_clock(cookie)) 273 bits |= RADEON_BB_SCL; 274 if (get_data(cookie)) 275 bits |= RADEON_BB_SDA; 276 277 return bits; 278 } 279 280 int 281 radeon_acquire_bus(void *cookie, int flags) 282 { 283 pre_xfer(cookie); 284 return (0); 285 } 286 287 void 288 radeon_release_bus(void *cookie, int flags) 289 { 290 post_xfer(cookie); 291 } 292 293 int 294 radeon_send_start(void *cookie, int flags) 295 { 296 return (i2c_bitbang_send_start(cookie, flags, &radeon_bbops)); 297 } 298 299 int 300 radeon_send_stop(void *cookie, int flags) 301 { 302 return (i2c_bitbang_send_stop(cookie, flags, &radeon_bbops)); 303 } 304 305 int 306 radeon_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 307 { 308 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &radeon_bbops)); 309 } 310 311 int 312 radeon_read_byte(void *cookie, u_int8_t *bytep, int flags) 313 { 314 return (i2c_bitbang_read_byte(cookie, bytep, flags, &radeon_bbops)); 315 } 316 317 int 318 radeon_write_byte(void *cookie, u_int8_t byte, int flags) 319 { 320 return (i2c_bitbang_write_byte(cookie, byte, flags, &radeon_bbops)); 321 } 322 323 /* hw i2c */ 324 325 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 326 { 327 u32 sclk = rdev->pm.current_sclk; 328 u32 prescale = 0; 329 u32 nm; 330 u8 n, m, loop; 331 int i2c_clock; 332 333 switch (rdev->family) { 334 case CHIP_R100: 335 case CHIP_RV100: 336 case CHIP_RS100: 337 case CHIP_RV200: 338 case CHIP_RS200: 339 case CHIP_R200: 340 case CHIP_RV250: 341 case CHIP_RS300: 342 case CHIP_RV280: 343 case CHIP_R300: 344 case CHIP_R350: 345 case CHIP_RV350: 346 i2c_clock = 60; 347 nm = (sclk * 10) / (i2c_clock * 4); 348 for (loop = 1; loop < 255; loop++) { 349 if ((nm / loop) < loop) 350 break; 351 } 352 n = loop - 1; 353 m = loop - 2; 354 prescale = m | (n << 8); 355 break; 356 case CHIP_RV380: 357 case CHIP_RS400: 358 case CHIP_RS480: 359 case CHIP_R420: 360 case CHIP_R423: 361 case CHIP_RV410: 362 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 363 break; 364 case CHIP_RS600: 365 case CHIP_RS690: 366 case CHIP_RS740: 367 /* todo */ 368 break; 369 case CHIP_RV515: 370 case CHIP_R520: 371 case CHIP_RV530: 372 case CHIP_RV560: 373 case CHIP_RV570: 374 case CHIP_R580: 375 i2c_clock = 50; 376 if (rdev->family == CHIP_R520) 377 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 378 else 379 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 380 break; 381 case CHIP_R600: 382 case CHIP_RV610: 383 case CHIP_RV630: 384 case CHIP_RV670: 385 /* todo */ 386 break; 387 case CHIP_RV620: 388 case CHIP_RV635: 389 case CHIP_RS780: 390 case CHIP_RS880: 391 case CHIP_RV770: 392 case CHIP_RV730: 393 case CHIP_RV710: 394 case CHIP_RV740: 395 /* todo */ 396 break; 397 case CHIP_CEDAR: 398 case CHIP_REDWOOD: 399 case CHIP_JUNIPER: 400 case CHIP_CYPRESS: 401 case CHIP_HEMLOCK: 402 /* todo */ 403 break; 404 default: 405 DRM_ERROR("i2c: unhandled radeon chip\n"); 406 break; 407 } 408 return prescale; 409 } 410 411 412 /* hw i2c engine for r1xx-4xx hardware 413 * hw can buffer up to 15 bytes 414 */ 415 static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 416 struct i2c_msg *msgs, int num) 417 { 418 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 419 struct radeon_device *rdev = i2c->dev->dev_private; 420 struct radeon_i2c_bus_rec *rec = &i2c->rec; 421 struct i2c_msg *p; 422 int i, j, k, ret = num; 423 u32 prescale; 424 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 425 u32 tmp, reg; 426 427 mutex_lock(&rdev->dc_hw_i2c_mutex); 428 /* take the pm lock since we need a constant sclk */ 429 mutex_lock(&rdev->pm.mutex); 430 431 prescale = radeon_get_i2c_prescale(rdev); 432 433 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 434 RADEON_I2C_DRIVE_EN | 435 RADEON_I2C_START | 436 RADEON_I2C_STOP | 437 RADEON_I2C_GO); 438 439 if (rdev->is_atom_bios) { 440 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 441 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 442 } 443 444 if (rec->mm_i2c) { 445 i2c_cntl_0 = RADEON_I2C_CNTL_0; 446 i2c_cntl_1 = RADEON_I2C_CNTL_1; 447 i2c_data = RADEON_I2C_DATA; 448 } else { 449 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 450 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 451 i2c_data = RADEON_DVI_I2C_DATA; 452 453 switch (rdev->family) { 454 case CHIP_R100: 455 case CHIP_RV100: 456 case CHIP_RS100: 457 case CHIP_RV200: 458 case CHIP_RS200: 459 case CHIP_RS300: 460 switch (rec->mask_clk_reg) { 461 case RADEON_GPIO_DVI_DDC: 462 /* no gpio select bit */ 463 break; 464 default: 465 DRM_ERROR("gpio not supported with hw i2c\n"); 466 ret = -EINVAL; 467 goto done; 468 } 469 break; 470 case CHIP_R200: 471 /* only bit 4 on r200 */ 472 switch (rec->mask_clk_reg) { 473 case RADEON_GPIO_DVI_DDC: 474 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 475 break; 476 case RADEON_GPIO_MONID: 477 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 478 break; 479 default: 480 DRM_ERROR("gpio not supported with hw i2c\n"); 481 ret = -EINVAL; 482 goto done; 483 } 484 break; 485 case CHIP_RV250: 486 case CHIP_RV280: 487 /* bits 3 and 4 */ 488 switch (rec->mask_clk_reg) { 489 case RADEON_GPIO_DVI_DDC: 490 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 491 break; 492 case RADEON_GPIO_VGA_DDC: 493 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 494 break; 495 case RADEON_GPIO_CRT2_DDC: 496 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 497 break; 498 default: 499 DRM_ERROR("gpio not supported with hw i2c\n"); 500 ret = -EINVAL; 501 goto done; 502 } 503 break; 504 case CHIP_R300: 505 case CHIP_R350: 506 /* only bit 4 on r300/r350 */ 507 switch (rec->mask_clk_reg) { 508 case RADEON_GPIO_VGA_DDC: 509 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 510 break; 511 case RADEON_GPIO_DVI_DDC: 512 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 513 break; 514 default: 515 DRM_ERROR("gpio not supported with hw i2c\n"); 516 ret = -EINVAL; 517 goto done; 518 } 519 break; 520 case CHIP_RV350: 521 case CHIP_RV380: 522 case CHIP_R420: 523 case CHIP_R423: 524 case CHIP_RV410: 525 case CHIP_RS400: 526 case CHIP_RS480: 527 /* bits 3 and 4 */ 528 switch (rec->mask_clk_reg) { 529 case RADEON_GPIO_VGA_DDC: 530 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 531 break; 532 case RADEON_GPIO_DVI_DDC: 533 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 534 break; 535 case RADEON_GPIO_MONID: 536 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 537 break; 538 default: 539 DRM_ERROR("gpio not supported with hw i2c\n"); 540 ret = -EINVAL; 541 goto done; 542 } 543 break; 544 default: 545 DRM_ERROR("unsupported asic\n"); 546 ret = -EINVAL; 547 goto done; 548 break; 549 } 550 } 551 552 /* check for bus probe */ 553 p = &msgs[0]; 554 if ((num == 1) && (p->len == 0)) { 555 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 556 RADEON_I2C_NACK | 557 RADEON_I2C_HALT | 558 RADEON_I2C_SOFT_RST)); 559 WREG32(i2c_data, (p->addr << 1) & 0xff); 560 WREG32(i2c_data, 0); 561 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 562 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 563 RADEON_I2C_EN | 564 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 565 WREG32(i2c_cntl_0, reg); 566 for (k = 0; k < 32; k++) { 567 udelay(10); 568 tmp = RREG32(i2c_cntl_0); 569 if (tmp & RADEON_I2C_GO) 570 continue; 571 tmp = RREG32(i2c_cntl_0); 572 if (tmp & RADEON_I2C_DONE) 573 break; 574 else { 575 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 576 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 577 ret = -EIO; 578 goto done; 579 } 580 } 581 goto done; 582 } 583 584 for (i = 0; i < num; i++) { 585 p = &msgs[i]; 586 for (j = 0; j < p->len; j++) { 587 if (p->flags & I2C_M_RD) { 588 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 589 RADEON_I2C_NACK | 590 RADEON_I2C_HALT | 591 RADEON_I2C_SOFT_RST)); 592 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 593 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 594 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 595 RADEON_I2C_EN | 596 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 597 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 598 for (k = 0; k < 32; k++) { 599 udelay(10); 600 tmp = RREG32(i2c_cntl_0); 601 if (tmp & RADEON_I2C_GO) 602 continue; 603 tmp = RREG32(i2c_cntl_0); 604 if (tmp & RADEON_I2C_DONE) 605 break; 606 else { 607 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 608 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 609 ret = -EIO; 610 goto done; 611 } 612 } 613 p->buf[j] = RREG32(i2c_data) & 0xff; 614 } else { 615 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 616 RADEON_I2C_NACK | 617 RADEON_I2C_HALT | 618 RADEON_I2C_SOFT_RST)); 619 WREG32(i2c_data, (p->addr << 1) & 0xff); 620 WREG32(i2c_data, p->buf[j]); 621 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 622 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 623 RADEON_I2C_EN | 624 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 625 WREG32(i2c_cntl_0, reg); 626 for (k = 0; k < 32; k++) { 627 udelay(10); 628 tmp = RREG32(i2c_cntl_0); 629 if (tmp & RADEON_I2C_GO) 630 continue; 631 tmp = RREG32(i2c_cntl_0); 632 if (tmp & RADEON_I2C_DONE) 633 break; 634 else { 635 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 636 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 637 ret = -EIO; 638 goto done; 639 } 640 } 641 } 642 } 643 } 644 645 done: 646 WREG32(i2c_cntl_0, 0); 647 WREG32(i2c_cntl_1, 0); 648 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 649 RADEON_I2C_NACK | 650 RADEON_I2C_HALT | 651 RADEON_I2C_SOFT_RST)); 652 653 if (rdev->is_atom_bios) { 654 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 655 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 656 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 657 } 658 659 mutex_unlock(&rdev->pm.mutex); 660 mutex_unlock(&rdev->dc_hw_i2c_mutex); 661 662 return ret; 663 } 664 665 /* hw i2c engine for r5xx hardware 666 * hw can buffer up to 15 bytes 667 */ 668 static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 669 struct i2c_msg *msgs, int num) 670 { 671 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 672 struct radeon_device *rdev = i2c->dev->dev_private; 673 struct radeon_i2c_bus_rec *rec = &i2c->rec; 674 struct i2c_msg *p; 675 int i, j, remaining, current_count, buffer_offset, ret = num; 676 u32 prescale; 677 u32 tmp, reg; 678 u32 saved1, saved2; 679 680 mutex_lock(&rdev->dc_hw_i2c_mutex); 681 /* take the pm lock since we need a constant sclk */ 682 mutex_lock(&rdev->pm.mutex); 683 684 prescale = radeon_get_i2c_prescale(rdev); 685 686 /* clear gpio mask bits */ 687 tmp = RREG32(rec->mask_clk_reg); 688 tmp &= ~rec->mask_clk_mask; 689 WREG32(rec->mask_clk_reg, tmp); 690 tmp = RREG32(rec->mask_clk_reg); 691 692 tmp = RREG32(rec->mask_data_reg); 693 tmp &= ~rec->mask_data_mask; 694 WREG32(rec->mask_data_reg, tmp); 695 tmp = RREG32(rec->mask_data_reg); 696 697 /* clear pin values */ 698 tmp = RREG32(rec->a_clk_reg); 699 tmp &= ~rec->a_clk_mask; 700 WREG32(rec->a_clk_reg, tmp); 701 tmp = RREG32(rec->a_clk_reg); 702 703 tmp = RREG32(rec->a_data_reg); 704 tmp &= ~rec->a_data_mask; 705 WREG32(rec->a_data_reg, tmp); 706 tmp = RREG32(rec->a_data_reg); 707 708 /* set the pins to input */ 709 tmp = RREG32(rec->en_clk_reg); 710 tmp &= ~rec->en_clk_mask; 711 WREG32(rec->en_clk_reg, tmp); 712 tmp = RREG32(rec->en_clk_reg); 713 714 tmp = RREG32(rec->en_data_reg); 715 tmp &= ~rec->en_data_mask; 716 WREG32(rec->en_data_reg, tmp); 717 tmp = RREG32(rec->en_data_reg); 718 719 /* */ 720 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 721 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 722 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 723 saved2 = RREG32(0x494); 724 WREG32(0x494, saved2 | 0x1); 725 726 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 727 for (i = 0; i < 50; i++) { 728 udelay(1); 729 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 730 break; 731 } 732 if (i == 50) { 733 DRM_ERROR("failed to get i2c bus\n"); 734 ret = -EBUSY; 735 goto done; 736 } 737 738 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 739 switch (rec->mask_clk_reg) { 740 case AVIVO_DC_GPIO_DDC1_MASK: 741 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 742 break; 743 case AVIVO_DC_GPIO_DDC2_MASK: 744 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 745 break; 746 case AVIVO_DC_GPIO_DDC3_MASK: 747 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 748 break; 749 default: 750 DRM_ERROR("gpio not supported with hw i2c\n"); 751 ret = -EINVAL; 752 goto done; 753 } 754 755 /* check for bus probe */ 756 p = &msgs[0]; 757 if ((num == 1) && (p->len == 0)) { 758 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 759 AVIVO_DC_I2C_NACK | 760 AVIVO_DC_I2C_HALT)); 761 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 762 udelay(1); 763 WREG32(AVIVO_DC_I2C_RESET, 0); 764 765 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 766 WREG32(AVIVO_DC_I2C_DATA, 0); 767 768 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 769 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 770 AVIVO_DC_I2C_DATA_COUNT(1) | 771 (prescale << 16))); 772 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 773 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 774 for (j = 0; j < 200; j++) { 775 udelay(50); 776 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 777 if (tmp & AVIVO_DC_I2C_GO) 778 continue; 779 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 780 if (tmp & AVIVO_DC_I2C_DONE) 781 break; 782 else { 783 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 784 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 785 ret = -EIO; 786 goto done; 787 } 788 } 789 goto done; 790 } 791 792 for (i = 0; i < num; i++) { 793 p = &msgs[i]; 794 remaining = p->len; 795 buffer_offset = 0; 796 if (p->flags & I2C_M_RD) { 797 while (remaining) { 798 if (remaining > 15) 799 current_count = 15; 800 else 801 current_count = remaining; 802 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 803 AVIVO_DC_I2C_NACK | 804 AVIVO_DC_I2C_HALT)); 805 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 806 udelay(1); 807 WREG32(AVIVO_DC_I2C_RESET, 0); 808 809 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 810 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 811 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 812 AVIVO_DC_I2C_DATA_COUNT(current_count) | 813 (prescale << 16))); 814 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 815 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 816 for (j = 0; j < 200; j++) { 817 udelay(50); 818 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 819 if (tmp & AVIVO_DC_I2C_GO) 820 continue; 821 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 822 if (tmp & AVIVO_DC_I2C_DONE) 823 break; 824 else { 825 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 826 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 827 ret = -EIO; 828 goto done; 829 } 830 } 831 for (j = 0; j < current_count; j++) 832 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 833 remaining -= current_count; 834 buffer_offset += current_count; 835 } 836 } else { 837 while (remaining) { 838 if (remaining > 15) 839 current_count = 15; 840 else 841 current_count = remaining; 842 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 843 AVIVO_DC_I2C_NACK | 844 AVIVO_DC_I2C_HALT)); 845 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 846 udelay(1); 847 WREG32(AVIVO_DC_I2C_RESET, 0); 848 849 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 850 for (j = 0; j < current_count; j++) 851 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 852 853 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 854 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 855 AVIVO_DC_I2C_DATA_COUNT(current_count) | 856 (prescale << 16))); 857 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 858 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 859 for (j = 0; j < 200; j++) { 860 udelay(50); 861 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 862 if (tmp & AVIVO_DC_I2C_GO) 863 continue; 864 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 865 if (tmp & AVIVO_DC_I2C_DONE) 866 break; 867 else { 868 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 869 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 870 ret = -EIO; 871 goto done; 872 } 873 } 874 remaining -= current_count; 875 buffer_offset += current_count; 876 } 877 } 878 } 879 880 done: 881 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 882 AVIVO_DC_I2C_NACK | 883 AVIVO_DC_I2C_HALT)); 884 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 885 udelay(1); 886 WREG32(AVIVO_DC_I2C_RESET, 0); 887 888 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 889 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 890 WREG32(0x494, saved2); 891 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 892 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 893 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 894 895 mutex_unlock(&rdev->pm.mutex); 896 mutex_unlock(&rdev->dc_hw_i2c_mutex); 897 898 return ret; 899 } 900 901 static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 902 struct i2c_msg *msgs, int num) 903 { 904 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 905 struct radeon_device *rdev = i2c->dev->dev_private; 906 struct radeon_i2c_bus_rec *rec = &i2c->rec; 907 int ret = 0; 908 909 switch (rdev->family) { 910 case CHIP_R100: 911 case CHIP_RV100: 912 case CHIP_RS100: 913 case CHIP_RV200: 914 case CHIP_RS200: 915 case CHIP_R200: 916 case CHIP_RV250: 917 case CHIP_RS300: 918 case CHIP_RV280: 919 case CHIP_R300: 920 case CHIP_R350: 921 case CHIP_RV350: 922 case CHIP_RV380: 923 case CHIP_R420: 924 case CHIP_R423: 925 case CHIP_RV410: 926 case CHIP_RS400: 927 case CHIP_RS480: 928 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 929 break; 930 case CHIP_RS600: 931 case CHIP_RS690: 932 case CHIP_RS740: 933 /* XXX fill in hw i2c implementation */ 934 break; 935 case CHIP_RV515: 936 case CHIP_R520: 937 case CHIP_RV530: 938 case CHIP_RV560: 939 case CHIP_RV570: 940 case CHIP_R580: 941 if (rec->mm_i2c) 942 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 943 else 944 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 945 break; 946 case CHIP_R600: 947 case CHIP_RV610: 948 case CHIP_RV630: 949 case CHIP_RV670: 950 /* XXX fill in hw i2c implementation */ 951 break; 952 case CHIP_RV620: 953 case CHIP_RV635: 954 case CHIP_RS780: 955 case CHIP_RS880: 956 case CHIP_RV770: 957 case CHIP_RV730: 958 case CHIP_RV710: 959 case CHIP_RV740: 960 /* XXX fill in hw i2c implementation */ 961 break; 962 case CHIP_CEDAR: 963 case CHIP_REDWOOD: 964 case CHIP_JUNIPER: 965 case CHIP_CYPRESS: 966 case CHIP_HEMLOCK: 967 /* XXX fill in hw i2c implementation */ 968 break; 969 default: 970 DRM_ERROR("i2c: unhandled radeon chip\n"); 971 ret = -EIO; 972 break; 973 } 974 975 return ret; 976 } 977 978 #ifdef notyet 979 static u32 radeon_hw_i2c_func(struct i2c_controller *adap) 980 { 981 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 982 } 983 #endif 984 985 static const struct i2c_algorithm radeon_i2c_algo = { 986 .master_xfer = radeon_hw_i2c_xfer, 987 #ifdef notyet 988 .functionality = radeon_hw_i2c_func, 989 #endif 990 }; 991 992 static const struct i2c_algorithm radeon_atom_i2c_algo = { 993 .master_xfer = radeon_atom_hw_i2c_xfer, 994 #ifdef notyet 995 .functionality = radeon_atom_hw_i2c_func, 996 #endif 997 }; 998 999 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 1000 struct radeon_i2c_bus_rec *rec, 1001 const char *name) 1002 { 1003 struct radeon_device *rdev = dev->dev_private; 1004 struct radeon_i2c_chan *i2c; 1005 int ret = 0; 1006 1007 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 1008 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 1009 return NULL; 1010 1011 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 1012 if (i2c == NULL) 1013 return NULL; 1014 1015 i2c->rec = *rec; 1016 #ifdef notyet 1017 i2c->adapter.owner = THIS_MODULE; 1018 i2c->adapter.class = I2C_CLASS_DDC; 1019 i2c->adapter.dev.parent = &dev->pdev->dev; 1020 #endif 1021 i2c->dev = dev; 1022 i2c_set_adapdata(&i2c->adapter, i2c); 1023 if (rec->mm_i2c || 1024 (rec->hw_capable && 1025 radeon_hw_i2c && 1026 ((rdev->family <= CHIP_RS480) || 1027 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 1028 /* set the radeon hw i2c adapter */ 1029 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1030 "Radeon i2c hw bus %s", name); 1031 i2c->adapter.algo = &radeon_i2c_algo; 1032 ret = i2c_add_adapter(&i2c->adapter); 1033 if (ret) { 1034 DRM_ERROR("Failed to register hw i2c %s\n", name); 1035 goto out_free; 1036 } 1037 } else if (rec->hw_capable && 1038 radeon_hw_i2c && 1039 ASIC_IS_DCE3(rdev)) { 1040 /* hw i2c using atom */ 1041 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1042 "Radeon i2c hw bus %s", name); 1043 i2c->adapter.algo = &radeon_atom_i2c_algo; 1044 ret = i2c_add_adapter(&i2c->adapter); 1045 if (ret) { 1046 DRM_ERROR("Failed to register hw i2c %s\n", name); 1047 goto out_free; 1048 } 1049 } else { 1050 /* set the radeon bit adapter */ 1051 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 1052 "Radeon i2c bit bus %s", name); 1053 #ifdef notyet 1054 i2c->adapter.algo_data = &i2c->algo.bit; 1055 i2c->algo.bit.pre_xfer = pre_xfer; 1056 i2c->algo.bit.post_xfer = post_xfer; 1057 i2c->algo.bit.setsda = set_data; 1058 i2c->algo.bit.setscl = set_clock; 1059 i2c->algo.bit.getsda = get_data; 1060 i2c->algo.bit.getscl = get_clock; 1061 i2c->algo.bit.udelay = 10; 1062 i2c->algo.bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 1063 i2c->algo.bit.data = i2c; 1064 ret = i2c_bit_add_bus(&i2c->adapter); 1065 #else 1066 i2c->adapter.ic.ic_cookie = i2c; 1067 i2c->adapter.ic.ic_acquire_bus = radeon_acquire_bus; 1068 i2c->adapter.ic.ic_release_bus = radeon_release_bus; 1069 i2c->adapter.ic.ic_send_start = radeon_send_start; 1070 i2c->adapter.ic.ic_send_stop = radeon_send_stop; 1071 i2c->adapter.ic.ic_initiate_xfer = radeon_initiate_xfer; 1072 i2c->adapter.ic.ic_read_byte = radeon_read_byte; 1073 i2c->adapter.ic.ic_write_byte = radeon_write_byte; 1074 #endif 1075 if (ret) { 1076 DRM_ERROR("Failed to register bit i2c %s\n", name); 1077 goto out_free; 1078 } 1079 } 1080 1081 return i2c; 1082 out_free: 1083 kfree(i2c); 1084 return NULL; 1085 } 1086 1087 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 1088 { 1089 if (!i2c) 1090 return; 1091 i2c_del_adapter(&i2c->adapter); 1092 if (i2c->has_aux) 1093 drm_dp_aux_unregister(&i2c->aux); 1094 kfree(i2c); 1095 } 1096 1097 /* Add the default buses */ 1098 void radeon_i2c_init(struct radeon_device *rdev) 1099 { 1100 if (radeon_hw_i2c) 1101 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 1102 1103 if (rdev->is_atom_bios) 1104 radeon_atombios_i2c_init(rdev); 1105 else 1106 radeon_combios_i2c_init(rdev); 1107 } 1108 1109 /* remove all the buses */ 1110 void radeon_i2c_fini(struct radeon_device *rdev) 1111 { 1112 int i; 1113 1114 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1115 if (rdev->i2c_bus[i]) { 1116 radeon_i2c_destroy(rdev->i2c_bus[i]); 1117 rdev->i2c_bus[i] = NULL; 1118 } 1119 } 1120 } 1121 1122 /* Add additional buses */ 1123 void radeon_i2c_add(struct radeon_device *rdev, 1124 struct radeon_i2c_bus_rec *rec, 1125 const char *name) 1126 { 1127 struct drm_device *dev = rdev->ddev; 1128 int i; 1129 1130 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1131 if (!rdev->i2c_bus[i]) { 1132 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1133 return; 1134 } 1135 } 1136 } 1137 1138 /* looks up bus based on id */ 1139 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1140 struct radeon_i2c_bus_rec *i2c_bus) 1141 { 1142 int i; 1143 1144 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1145 if (rdev->i2c_bus[i] && 1146 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1147 return rdev->i2c_bus[i]; 1148 } 1149 } 1150 return NULL; 1151 } 1152 1153 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector) 1154 { 1155 return NULL; 1156 } 1157 1158 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1159 u8 slave_addr, 1160 u8 addr, 1161 u8 *val) 1162 { 1163 u8 out_buf[2]; 1164 u8 in_buf[2]; 1165 struct i2c_msg msgs[] = { 1166 { 1167 .addr = slave_addr, 1168 .flags = 0, 1169 .len = 1, 1170 .buf = out_buf, 1171 }, 1172 { 1173 .addr = slave_addr, 1174 .flags = I2C_M_RD, 1175 .len = 1, 1176 .buf = in_buf, 1177 } 1178 }; 1179 1180 out_buf[0] = addr; 1181 out_buf[1] = 0; 1182 1183 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1184 *val = in_buf[0]; 1185 DRM_DEBUG("val = 0x%02x\n", *val); 1186 } else { 1187 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1188 addr, *val); 1189 } 1190 } 1191 1192 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1193 u8 slave_addr, 1194 u8 addr, 1195 u8 val) 1196 { 1197 uint8_t out_buf[2]; 1198 struct i2c_msg msg = { 1199 .addr = slave_addr, 1200 .flags = 0, 1201 .len = 2, 1202 .buf = out_buf, 1203 }; 1204 1205 out_buf[0] = addr; 1206 out_buf[1] = val; 1207 1208 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1209 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1210 addr, val); 1211 } 1212 1213 /* ddc router switching */ 1214 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1215 { 1216 u8 val; 1217 1218 if (!radeon_connector->router.ddc_valid) 1219 return; 1220 1221 if (!radeon_connector->router_bus) 1222 return; 1223 1224 radeon_i2c_get_byte(radeon_connector->router_bus, 1225 radeon_connector->router.i2c_addr, 1226 0x3, &val); 1227 val &= ~radeon_connector->router.ddc_mux_control_pin; 1228 radeon_i2c_put_byte(radeon_connector->router_bus, 1229 radeon_connector->router.i2c_addr, 1230 0x3, val); 1231 radeon_i2c_get_byte(radeon_connector->router_bus, 1232 radeon_connector->router.i2c_addr, 1233 0x1, &val); 1234 val &= ~radeon_connector->router.ddc_mux_control_pin; 1235 val |= radeon_connector->router.ddc_mux_state; 1236 radeon_i2c_put_byte(radeon_connector->router_bus, 1237 radeon_connector->router.i2c_addr, 1238 0x1, val); 1239 } 1240 1241 /* clock/data router switching */ 1242 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1243 { 1244 u8 val; 1245 1246 if (!radeon_connector->router.cd_valid) 1247 return; 1248 1249 if (!radeon_connector->router_bus) 1250 return; 1251 1252 radeon_i2c_get_byte(radeon_connector->router_bus, 1253 radeon_connector->router.i2c_addr, 1254 0x3, &val); 1255 val &= ~radeon_connector->router.cd_mux_control_pin; 1256 radeon_i2c_put_byte(radeon_connector->router_bus, 1257 radeon_connector->router.i2c_addr, 1258 0x3, val); 1259 radeon_i2c_get_byte(radeon_connector->router_bus, 1260 radeon_connector->router.i2c_addr, 1261 0x1, &val); 1262 val &= ~radeon_connector->router.cd_mux_control_pin; 1263 val |= radeon_connector->router.cd_mux_state; 1264 radeon_i2c_put_byte(radeon_connector->router_bus, 1265 radeon_connector->router.i2c_addr, 1266 0x1, val); 1267 } 1268 1269