1 /* $OpenBSD: radeon_object.c,v 1.10 2015/04/18 11:41:29 jsg Exp $ */ 2 /* 3 * Copyright 2009 Jerome Glisse. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: 29 * Jerome Glisse <glisse@freedesktop.org> 30 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 31 * Dave Airlie 32 */ 33 #include <dev/pci/drm/drmP.h> 34 #include <dev/pci/drm/radeon_drm.h> 35 #include "radeon.h" 36 #include "radeon_trace.h" 37 38 39 int radeon_ttm_init(struct radeon_device *rdev); 40 void radeon_ttm_fini(struct radeon_device *rdev); 41 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 42 43 /* 44 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 45 * function are calling it. 46 */ 47 48 void radeon_bo_clear_va(struct radeon_bo *bo) 49 { 50 struct radeon_bo_va *bo_va, *tmp; 51 52 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) { 53 /* remove from all vm address space */ 54 radeon_vm_bo_rmv(bo->rdev, bo_va); 55 } 56 } 57 58 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 59 { 60 struct radeon_bo *bo; 61 62 bo = container_of(tbo, struct radeon_bo, tbo); 63 mutex_lock(&bo->rdev->gem.mutex); 64 list_del_init(&bo->list); 65 mutex_unlock(&bo->rdev->gem.mutex); 66 radeon_bo_clear_surface_reg(bo); 67 radeon_bo_clear_va(bo); 68 drm_gem_object_release(&bo->gem_base); 69 pool_put(&bo->rdev->ddev->objpl, bo); 70 } 71 72 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 73 { 74 if (bo->destroy == &radeon_ttm_bo_destroy) 75 return true; 76 return false; 77 } 78 79 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 80 { 81 u32 c = 0; 82 83 rbo->placement.fpfn = 0; 84 rbo->placement.lpfn = 0; 85 rbo->placement.placement = rbo->placements; 86 rbo->placement.busy_placement = rbo->placements; 87 if (domain & RADEON_GEM_DOMAIN_VRAM) 88 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 89 TTM_PL_FLAG_VRAM; 90 if (domain & RADEON_GEM_DOMAIN_GTT) { 91 if (rbo->rdev->flags & RADEON_IS_AGP) { 92 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT; 93 } else { 94 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 95 } 96 } 97 if (domain & RADEON_GEM_DOMAIN_CPU) { 98 if (rbo->rdev->flags & RADEON_IS_AGP) { 99 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM; 100 } else { 101 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; 102 } 103 } 104 if (!c) 105 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 106 rbo->placement.num_placement = c; 107 rbo->placement.num_busy_placement = c; 108 } 109 110 int radeon_bo_create(struct radeon_device *rdev, 111 unsigned long size, int byte_align, bool kernel, u32 domain, 112 struct sg_table *sg, struct radeon_bo **bo_ptr) 113 { 114 struct radeon_bo *bo; 115 enum ttm_bo_type type; 116 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 117 size_t acc_size; 118 int r; 119 120 size = PAGE_ALIGN(size); 121 122 #ifdef notyet 123 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; 124 #endif 125 if (kernel) { 126 type = ttm_bo_type_kernel; 127 } else if (sg) { 128 type = ttm_bo_type_sg; 129 } else { 130 type = ttm_bo_type_device; 131 } 132 *bo_ptr = NULL; 133 134 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 135 sizeof(struct radeon_bo)); 136 137 bo = pool_get(&rdev->ddev->objpl, PR_WAITOK | PR_ZERO); 138 if (bo == NULL) 139 return -ENOMEM; 140 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size); 141 if (unlikely(r)) { 142 pool_put(&rdev->ddev->objpl, bo); 143 return r; 144 } 145 bo->rdev = rdev; 146 bo->surface_reg = -1; 147 INIT_LIST_HEAD(&bo->list); 148 INIT_LIST_HEAD(&bo->va); 149 radeon_ttm_placement_from_domain(bo, domain); 150 /* Kernel allocation are uninterruptible */ 151 down_read(&rdev->pm.mclk_lock); 152 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 153 &bo->placement, page_align, !kernel, NULL, 154 acc_size, sg, &radeon_ttm_bo_destroy); 155 up_read(&rdev->pm.mclk_lock); 156 if (unlikely(r != 0)) { 157 return r; 158 } 159 *bo_ptr = bo; 160 161 trace_radeon_bo_create(bo); 162 163 return 0; 164 } 165 166 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 167 { 168 bool is_iomem; 169 int r; 170 171 if (bo->kptr) { 172 if (ptr) { 173 *ptr = bo->kptr; 174 } 175 return 0; 176 } 177 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 178 if (r) { 179 return r; 180 } 181 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 182 if (ptr) { 183 *ptr = bo->kptr; 184 } 185 radeon_bo_check_tiling(bo, 0, 0); 186 return 0; 187 } 188 189 void radeon_bo_kunmap(struct radeon_bo *bo) 190 { 191 if (bo->kptr == NULL) 192 return; 193 bo->kptr = NULL; 194 radeon_bo_check_tiling(bo, 0, 0); 195 ttm_bo_kunmap(&bo->kmap); 196 } 197 198 void radeon_bo_unref(struct radeon_bo **bo) 199 { 200 struct ttm_buffer_object *tbo; 201 struct radeon_device *rdev; 202 203 if ((*bo) == NULL) 204 return; 205 rdev = (*bo)->rdev; 206 tbo = &((*bo)->tbo); 207 down_read(&rdev->pm.mclk_lock); 208 ttm_bo_unref(&tbo); 209 up_read(&rdev->pm.mclk_lock); 210 if (tbo == NULL) 211 *bo = NULL; 212 } 213 214 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 215 u64 *gpu_addr) 216 { 217 int r, i; 218 219 if (bo->pin_count) { 220 bo->pin_count++; 221 if (gpu_addr) 222 *gpu_addr = radeon_bo_gpu_offset(bo); 223 224 if (max_offset != 0) { 225 u64 domain_start; 226 227 if (domain == RADEON_GEM_DOMAIN_VRAM) 228 domain_start = bo->rdev->mc.vram_start; 229 else 230 domain_start = bo->rdev->mc.gtt_start; 231 WARN_ON_ONCE(max_offset < 232 (radeon_bo_gpu_offset(bo) - domain_start)); 233 } 234 235 return 0; 236 } 237 radeon_ttm_placement_from_domain(bo, domain); 238 if (domain == RADEON_GEM_DOMAIN_VRAM) { 239 /* force to pin into visible video ram */ 240 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 241 } 242 if (max_offset) { 243 u64 lpfn = max_offset >> PAGE_SHIFT; 244 245 if (!bo->placement.lpfn) 246 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; 247 248 if (lpfn < bo->placement.lpfn) 249 bo->placement.lpfn = lpfn; 250 } 251 for (i = 0; i < bo->placement.num_placement; i++) 252 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; 253 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 254 if (likely(r == 0)) { 255 bo->pin_count = 1; 256 if (gpu_addr != NULL) 257 *gpu_addr = radeon_bo_gpu_offset(bo); 258 } 259 if (unlikely(r != 0)) 260 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 261 return r; 262 } 263 264 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 265 { 266 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 267 } 268 269 int radeon_bo_unpin(struct radeon_bo *bo) 270 { 271 int r, i; 272 273 if (!bo->pin_count) { 274 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 275 return 0; 276 } 277 bo->pin_count--; 278 if (bo->pin_count) 279 return 0; 280 for (i = 0; i < bo->placement.num_placement; i++) 281 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; 282 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 283 if (unlikely(r != 0)) 284 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 285 return r; 286 } 287 288 int radeon_bo_evict_vram(struct radeon_device *rdev) 289 { 290 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 291 if (0 && (rdev->flags & RADEON_IS_IGP)) { 292 if (rdev->mc.igp_sideport_enabled == false) 293 /* Useless to evict on IGP chips */ 294 return 0; 295 } 296 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 297 } 298 299 void radeon_bo_force_delete(struct radeon_device *rdev) 300 { 301 struct radeon_bo *bo, *n; 302 303 if (list_empty(&rdev->gem.objects)) { 304 return; 305 } 306 dev_err(rdev->dev, "Userspace still has active objects !\n"); 307 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 308 mutex_lock(&rdev->ddev->struct_mutex); 309 #ifdef notyet 310 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 311 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 312 *((unsigned long *)&bo->gem_base.refcount)); 313 #endif 314 mutex_lock(&bo->rdev->gem.mutex); 315 list_del_init(&bo->list); 316 mutex_unlock(&bo->rdev->gem.mutex); 317 /* this should unref the ttm bo */ 318 drm_gem_object_unreference(&bo->gem_base); 319 mutex_unlock(&rdev->ddev->struct_mutex); 320 } 321 } 322 323 int radeon_bo_init(struct radeon_device *rdev) 324 { 325 paddr_t start, end; 326 327 /* Add an MTRR for the VRAM */ 328 drm_mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, DRM_MTRR_WC); 329 /* fake a 'cookie', seems to be unused? */ 330 rdev->mc.vram_mtrr = 1; 331 332 start = atop(bus_space_mmap(rdev->memt, rdev->mc.aper_base, 0, 0, 0)); 333 end = start + atop(rdev->mc.aper_size); 334 uvm_page_physload(start, end, start, end, PHYSLOAD_DEVICE); 335 336 #ifdef DRMDEBUG 337 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 338 rdev->mc.mc_vram_size >> 20, 339 (unsigned long long)rdev->mc.aper_size >> 20); 340 DRM_INFO("RAM width %dbits %cDR\n", 341 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 342 #endif 343 return radeon_ttm_init(rdev); 344 } 345 346 void radeon_bo_fini(struct radeon_device *rdev) 347 { 348 radeon_ttm_fini(rdev); 349 } 350 351 void radeon_bo_list_add_object(struct radeon_bo_list *lobj, 352 struct list_head *head) 353 { 354 if (lobj->wdomain) { 355 list_add(&lobj->tv.head, head); 356 } else { 357 list_add_tail(&lobj->tv.head, head); 358 } 359 } 360 361 int radeon_bo_list_validate(struct list_head *head) 362 { 363 struct radeon_bo_list *lobj; 364 struct radeon_bo *bo; 365 u32 domain; 366 int r; 367 368 r = ttm_eu_reserve_buffers(head); 369 if (unlikely(r != 0)) { 370 return r; 371 } 372 list_for_each_entry(lobj, head, tv.head) { 373 bo = lobj->bo; 374 if (!bo->pin_count) { 375 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain; 376 377 retry: 378 radeon_ttm_placement_from_domain(bo, domain); 379 r = ttm_bo_validate(&bo->tbo, &bo->placement, 380 true, false); 381 if (unlikely(r)) { 382 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) { 383 domain |= RADEON_GEM_DOMAIN_GTT; 384 goto retry; 385 } 386 return r; 387 } 388 } 389 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 390 lobj->tiling_flags = bo->tiling_flags; 391 } 392 return 0; 393 } 394 395 #ifdef notyet 396 int radeon_bo_fbdev_mmap(struct radeon_bo *bo, 397 struct vm_area_struct *vma) 398 { 399 return ttm_fbdev_mmap(vma, &bo->tbo); 400 } 401 #endif 402 403 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 404 { 405 struct radeon_device *rdev = bo->rdev; 406 struct radeon_surface_reg *reg; 407 struct radeon_bo *old_object; 408 int steal; 409 int i; 410 411 BUG_ON(!radeon_bo_is_reserved(bo)); 412 413 if (!bo->tiling_flags) 414 return 0; 415 416 if (bo->surface_reg >= 0) { 417 reg = &rdev->surface_regs[bo->surface_reg]; 418 i = bo->surface_reg; 419 goto out; 420 } 421 422 steal = -1; 423 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 424 425 reg = &rdev->surface_regs[i]; 426 if (!reg->bo) 427 break; 428 429 old_object = reg->bo; 430 if (old_object->pin_count == 0) 431 steal = i; 432 } 433 434 /* if we are all out */ 435 if (i == RADEON_GEM_MAX_SURFACES) { 436 if (steal == -1) 437 return -ENOMEM; 438 /* find someone with a surface reg and nuke their BO */ 439 reg = &rdev->surface_regs[steal]; 440 old_object = reg->bo; 441 /* blow away the mapping */ 442 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 443 ttm_bo_unmap_virtual(&old_object->tbo); 444 old_object->surface_reg = -1; 445 i = steal; 446 } 447 448 bo->surface_reg = i; 449 reg->bo = bo; 450 451 out: 452 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 453 bo->tbo.mem.start << PAGE_SHIFT, 454 bo->tbo.num_pages << PAGE_SHIFT); 455 return 0; 456 } 457 458 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 459 { 460 struct radeon_device *rdev = bo->rdev; 461 struct radeon_surface_reg *reg; 462 463 if (bo->surface_reg == -1) 464 return; 465 466 reg = &rdev->surface_regs[bo->surface_reg]; 467 radeon_clear_surface_reg(rdev, bo->surface_reg); 468 469 reg->bo = NULL; 470 bo->surface_reg = -1; 471 } 472 473 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 474 uint32_t tiling_flags, uint32_t pitch) 475 { 476 struct radeon_device *rdev = bo->rdev; 477 int r; 478 479 if (rdev->family >= CHIP_CEDAR) { 480 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 481 482 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 483 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 484 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 485 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 486 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 487 switch (bankw) { 488 case 0: 489 case 1: 490 case 2: 491 case 4: 492 case 8: 493 break; 494 default: 495 return -EINVAL; 496 } 497 switch (bankh) { 498 case 0: 499 case 1: 500 case 2: 501 case 4: 502 case 8: 503 break; 504 default: 505 return -EINVAL; 506 } 507 switch (mtaspect) { 508 case 0: 509 case 1: 510 case 2: 511 case 4: 512 case 8: 513 break; 514 default: 515 return -EINVAL; 516 } 517 if (tilesplit > 6) { 518 return -EINVAL; 519 } 520 if (stilesplit > 6) { 521 return -EINVAL; 522 } 523 } 524 r = radeon_bo_reserve(bo, false); 525 if (unlikely(r != 0)) 526 return r; 527 bo->tiling_flags = tiling_flags; 528 bo->pitch = pitch; 529 radeon_bo_unreserve(bo); 530 return 0; 531 } 532 533 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 534 uint32_t *tiling_flags, 535 uint32_t *pitch) 536 { 537 BUG_ON(!radeon_bo_is_reserved(bo)); 538 if (tiling_flags) 539 *tiling_flags = bo->tiling_flags; 540 if (pitch) 541 *pitch = bo->pitch; 542 } 543 544 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 545 bool force_drop) 546 { 547 BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop); 548 549 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 550 return 0; 551 552 if (force_drop) { 553 radeon_bo_clear_surface_reg(bo); 554 return 0; 555 } 556 557 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 558 if (!has_moved) 559 return 0; 560 561 if (bo->surface_reg >= 0) 562 radeon_bo_clear_surface_reg(bo); 563 return 0; 564 } 565 566 if ((bo->surface_reg >= 0) && !has_moved) 567 return 0; 568 569 return radeon_bo_get_surface_reg(bo); 570 } 571 572 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 573 struct ttm_mem_reg *mem) 574 { 575 struct radeon_bo *rbo; 576 if (!radeon_ttm_bo_is_radeon_bo(bo)) 577 return; 578 rbo = container_of(bo, struct radeon_bo, tbo); 579 radeon_bo_check_tiling(rbo, 0, 1); 580 radeon_vm_bo_invalidate(rbo->rdev, rbo); 581 } 582 583 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 584 { 585 struct radeon_device *rdev; 586 struct radeon_bo *rbo; 587 unsigned long offset, size; 588 int r; 589 590 if (!radeon_ttm_bo_is_radeon_bo(bo)) 591 return 0; 592 rbo = container_of(bo, struct radeon_bo, tbo); 593 radeon_bo_check_tiling(rbo, 0, 0); 594 rdev = rbo->rdev; 595 if (bo->mem.mem_type != TTM_PL_VRAM) 596 return 0; 597 598 size = bo->mem.num_pages << PAGE_SHIFT; 599 offset = bo->mem.start << PAGE_SHIFT; 600 if ((offset + size) <= rdev->mc.visible_vram_size) 601 return 0; 602 603 /* hurrah the memory is not visible ! */ 604 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 605 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 606 r = ttm_bo_validate(bo, &rbo->placement, false, false); 607 if (unlikely(r == -ENOMEM)) { 608 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 609 return ttm_bo_validate(bo, &rbo->placement, false, false); 610 } else if (unlikely(r != 0)) { 611 return r; 612 } 613 614 offset = bo->mem.start << PAGE_SHIFT; 615 /* this should never happen */ 616 if ((offset + size) > rdev->mc.visible_vram_size) 617 return -EINVAL; 618 619 return 0; 620 } 621 622 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 623 { 624 int r; 625 626 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0); 627 if (unlikely(r != 0)) 628 return r; 629 spin_lock(&bo->tbo.bdev->fence_lock); 630 if (mem_type) 631 *mem_type = bo->tbo.mem.mem_type; 632 if (bo->tbo.sync_obj) 633 r = ttm_bo_wait(&bo->tbo, true, true, no_wait); 634 spin_unlock(&bo->tbo.bdev->fence_lock); 635 ttm_bo_unreserve(&bo->tbo); 636 return r; 637 } 638 639 640 /** 641 * radeon_bo_reserve - reserve bo 642 * @bo: bo structure 643 * @no_intr: don't return -ERESTARTSYS on pending signal 644 * 645 * Returns: 646 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 647 * a signal. Release all buffer reservations and return to user-space. 648 */ 649 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr) 650 { 651 int r; 652 653 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); 654 if (unlikely(r != 0)) { 655 if (r != -ERESTARTSYS) 656 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 657 return r; 658 } 659 return 0; 660 } 661