1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 #include <drm/drmP.h> 24 #include "radeon.h" 25 #include "avivod.h" 26 #include "atom.h" 27 #include "r600_dpm.h" 28 #include <linux/power_supply.h> 29 #include <linux/hwmon.h> 30 #include <linux/hwmon-sysfs.h> 31 32 #define RADEON_IDLE_LOOP_MS 100 33 #define RADEON_RECLOCK_DELAY_MS 200 34 #define RADEON_WAIT_VBLANK_TIMEOUT 200 35 36 #ifdef DRMDEBUG 37 static const char *radeon_pm_state_type_name[5] = { 38 "", 39 "Powersave", 40 "Battery", 41 "Balanced", 42 "Performance", 43 }; 44 #endif 45 46 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 47 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 48 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 49 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 50 static void radeon_pm_update_profile(struct radeon_device *rdev); 51 static void radeon_pm_set_clocks(struct radeon_device *rdev); 52 53 int radeon_pm_get_type_index(struct radeon_device *rdev, 54 enum radeon_pm_state_type ps_type, 55 int instance) 56 { 57 int i; 58 int found_instance = -1; 59 60 for (i = 0; i < rdev->pm.num_power_states; i++) { 61 if (rdev->pm.power_state[i].type == ps_type) { 62 found_instance++; 63 if (found_instance == instance) 64 return i; 65 } 66 } 67 /* return default if no match */ 68 return rdev->pm.default_power_state_index; 69 } 70 71 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 72 { 73 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 74 mutex_lock(&rdev->pm.mutex); 75 if (power_supply_is_system_supplied() > 0) 76 rdev->pm.dpm.ac_power = true; 77 else 78 rdev->pm.dpm.ac_power = false; 79 if (rdev->family == CHIP_ARUBA) { 80 if (rdev->asic->dpm.enable_bapm) 81 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 82 } 83 mutex_unlock(&rdev->pm.mutex); 84 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 85 if (rdev->pm.profile == PM_PROFILE_AUTO) { 86 mutex_lock(&rdev->pm.mutex); 87 radeon_pm_update_profile(rdev); 88 radeon_pm_set_clocks(rdev); 89 mutex_unlock(&rdev->pm.mutex); 90 } 91 } 92 } 93 94 static void radeon_pm_update_profile(struct radeon_device *rdev) 95 { 96 switch (rdev->pm.profile) { 97 case PM_PROFILE_DEFAULT: 98 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 99 break; 100 case PM_PROFILE_AUTO: 101 if (power_supply_is_system_supplied() > 0) { 102 if (rdev->pm.active_crtc_count > 1) 103 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 104 else 105 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 106 } else { 107 if (rdev->pm.active_crtc_count > 1) 108 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 109 else 110 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 111 } 112 break; 113 case PM_PROFILE_LOW: 114 if (rdev->pm.active_crtc_count > 1) 115 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 116 else 117 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 118 break; 119 case PM_PROFILE_MID: 120 if (rdev->pm.active_crtc_count > 1) 121 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 122 else 123 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 124 break; 125 case PM_PROFILE_HIGH: 126 if (rdev->pm.active_crtc_count > 1) 127 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 128 else 129 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 130 break; 131 } 132 133 if (rdev->pm.active_crtc_count == 0) { 134 rdev->pm.requested_power_state_index = 135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 136 rdev->pm.requested_clock_mode_index = 137 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 138 } else { 139 rdev->pm.requested_power_state_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 141 rdev->pm.requested_clock_mode_index = 142 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 143 } 144 } 145 146 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 147 { 148 struct radeon_bo *bo, *n; 149 150 if (list_empty(&rdev->gem.objects)) 151 return; 152 153 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 154 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 155 ttm_bo_unmap_virtual(&bo->tbo); 156 } 157 } 158 159 static void radeon_sync_with_vblank(struct radeon_device *rdev) 160 { 161 if (rdev->pm.active_crtcs) { 162 rdev->pm.vblank_sync = false; 163 wait_event_timeout( 164 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 165 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 166 } 167 } 168 169 static void radeon_set_power_state(struct radeon_device *rdev) 170 { 171 u32 sclk, mclk; 172 bool misc_after = false; 173 174 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 175 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 176 return; 177 178 if (radeon_gui_idle(rdev)) { 179 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 180 clock_info[rdev->pm.requested_clock_mode_index].sclk; 181 if (sclk > rdev->pm.default_sclk) 182 sclk = rdev->pm.default_sclk; 183 184 /* starting with BTC, there is one state that is used for both 185 * MH and SH. Difference is that we always use the high clock index for 186 * mclk and vddci. 187 */ 188 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 189 (rdev->family >= CHIP_BARTS) && 190 rdev->pm.active_crtc_count && 191 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 192 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 193 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 194 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 195 else 196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 197 clock_info[rdev->pm.requested_clock_mode_index].mclk; 198 199 if (mclk > rdev->pm.default_mclk) 200 mclk = rdev->pm.default_mclk; 201 202 /* upvolt before raising clocks, downvolt after lowering clocks */ 203 if (sclk < rdev->pm.current_sclk) 204 misc_after = true; 205 206 radeon_sync_with_vblank(rdev); 207 208 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 209 if (!radeon_pm_in_vbl(rdev)) 210 return; 211 } 212 213 radeon_pm_prepare(rdev); 214 215 if (!misc_after) 216 /* voltage, pcie lanes, etc.*/ 217 radeon_pm_misc(rdev); 218 219 /* set engine clock */ 220 if (sclk != rdev->pm.current_sclk) { 221 radeon_pm_debug_check_in_vbl(rdev, false); 222 radeon_set_engine_clock(rdev, sclk); 223 radeon_pm_debug_check_in_vbl(rdev, true); 224 rdev->pm.current_sclk = sclk; 225 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 226 } 227 228 /* set memory clock */ 229 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 230 radeon_pm_debug_check_in_vbl(rdev, false); 231 radeon_set_memory_clock(rdev, mclk); 232 radeon_pm_debug_check_in_vbl(rdev, true); 233 rdev->pm.current_mclk = mclk; 234 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 235 } 236 237 if (misc_after) 238 /* voltage, pcie lanes, etc.*/ 239 radeon_pm_misc(rdev); 240 241 radeon_pm_finish(rdev); 242 243 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 244 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 245 } else 246 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 247 } 248 249 static void radeon_pm_set_clocks(struct radeon_device *rdev) 250 { 251 struct drm_crtc *crtc; 252 int i, r; 253 254 /* no need to take locks, etc. if nothing's going to change */ 255 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 256 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 257 return; 258 259 down_write(&rdev->pm.mclk_lock); 260 mutex_lock(&rdev->ring_lock); 261 262 /* wait for the rings to drain */ 263 for (i = 0; i < RADEON_NUM_RINGS; i++) { 264 struct radeon_ring *ring = &rdev->ring[i]; 265 if (!ring->ready) { 266 continue; 267 } 268 r = radeon_fence_wait_empty(rdev, i); 269 if (r) { 270 /* needs a GPU reset dont reset here */ 271 mutex_unlock(&rdev->ring_lock); 272 up_write(&rdev->pm.mclk_lock); 273 return; 274 } 275 } 276 277 radeon_unmap_vram_bos(rdev); 278 279 if (rdev->irq.installed) { 280 i = 0; 281 drm_for_each_crtc(crtc, rdev->ddev) { 282 if (rdev->pm.active_crtcs & (1 << i)) { 283 /* This can fail if a modeset is in progress */ 284 if (drm_crtc_vblank_get(crtc) == 0) 285 rdev->pm.req_vblank |= (1 << i); 286 else 287 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", 288 i); 289 } 290 i++; 291 } 292 } 293 294 radeon_set_power_state(rdev); 295 296 if (rdev->irq.installed) { 297 i = 0; 298 drm_for_each_crtc(crtc, rdev->ddev) { 299 if (rdev->pm.req_vblank & (1 << i)) { 300 rdev->pm.req_vblank &= ~(1 << i); 301 drm_crtc_vblank_put(crtc); 302 } 303 i++; 304 } 305 } 306 307 /* update display watermarks based on new power state */ 308 radeon_update_bandwidth_info(rdev); 309 if (rdev->pm.active_crtc_count) 310 radeon_bandwidth_update(rdev); 311 312 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 313 314 mutex_unlock(&rdev->ring_lock); 315 up_write(&rdev->pm.mclk_lock); 316 } 317 318 static void radeon_pm_print_states(struct radeon_device *rdev) 319 { 320 int i, j; 321 struct radeon_power_state *power_state; 322 struct radeon_pm_clock_info *clock_info; 323 324 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 325 for (i = 0; i < rdev->pm.num_power_states; i++) { 326 power_state = &rdev->pm.power_state[i]; 327 DRM_DEBUG_DRIVER("State %d: %s\n", i, 328 radeon_pm_state_type_name[power_state->type]); 329 if (i == rdev->pm.default_power_state_index) 330 DRM_DEBUG_DRIVER("\tDefault"); 331 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 332 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 333 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 334 DRM_DEBUG_DRIVER("\tSingle display only\n"); 335 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 336 for (j = 0; j < power_state->num_clock_modes; j++) { 337 clock_info = &(power_state->clock_info[j]); 338 if (rdev->flags & RADEON_IS_IGP) 339 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 340 j, 341 clock_info->sclk * 10); 342 else 343 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 344 j, 345 clock_info->sclk * 10, 346 clock_info->mclk * 10, 347 clock_info->voltage.voltage); 348 } 349 } 350 } 351 352 #ifdef notyet 353 static ssize_t radeon_get_pm_profile(struct device *dev, 354 struct device_attribute *attr, 355 char *buf) 356 { 357 struct drm_device *ddev = dev_get_drvdata(dev); 358 struct radeon_device *rdev = ddev->dev_private; 359 int cp = rdev->pm.profile; 360 361 return snprintf(buf, PAGE_SIZE, "%s\n", 362 (cp == PM_PROFILE_AUTO) ? "auto" : 363 (cp == PM_PROFILE_LOW) ? "low" : 364 (cp == PM_PROFILE_MID) ? "mid" : 365 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 366 } 367 368 static ssize_t radeon_set_pm_profile(struct device *dev, 369 struct device_attribute *attr, 370 const char *buf, 371 size_t count) 372 { 373 struct drm_device *ddev = dev_get_drvdata(dev); 374 struct radeon_device *rdev = ddev->dev_private; 375 376 /* Can't set profile when the card is off */ 377 #ifdef notyet 378 if ((rdev->flags & RADEON_IS_PX) && 379 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 380 return -EINVAL; 381 #endif 382 383 mutex_lock(&rdev->pm.mutex); 384 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 385 if (strncmp("default", buf, strlen("default")) == 0) 386 rdev->pm.profile = PM_PROFILE_DEFAULT; 387 else if (strncmp("auto", buf, strlen("auto")) == 0) 388 rdev->pm.profile = PM_PROFILE_AUTO; 389 else if (strncmp("low", buf, strlen("low")) == 0) 390 rdev->pm.profile = PM_PROFILE_LOW; 391 else if (strncmp("mid", buf, strlen("mid")) == 0) 392 rdev->pm.profile = PM_PROFILE_MID; 393 else if (strncmp("high", buf, strlen("high")) == 0) 394 rdev->pm.profile = PM_PROFILE_HIGH; 395 else { 396 count = -EINVAL; 397 goto fail; 398 } 399 radeon_pm_update_profile(rdev); 400 radeon_pm_set_clocks(rdev); 401 } else 402 count = -EINVAL; 403 404 fail: 405 mutex_unlock(&rdev->pm.mutex); 406 407 return count; 408 } 409 410 static ssize_t radeon_get_pm_method(struct device *dev, 411 struct device_attribute *attr, 412 char *buf) 413 { 414 struct drm_device *ddev = dev_get_drvdata(dev); 415 struct radeon_device *rdev = ddev->dev_private; 416 int pm = rdev->pm.pm_method; 417 418 return snprintf(buf, PAGE_SIZE, "%s\n", 419 (pm == PM_METHOD_DYNPM) ? "dynpm" : 420 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 421 } 422 423 static ssize_t radeon_set_pm_method(struct device *dev, 424 struct device_attribute *attr, 425 const char *buf, 426 size_t count) 427 { 428 struct drm_device *ddev = dev_get_drvdata(dev); 429 struct radeon_device *rdev = ddev->dev_private; 430 431 #ifdef notyet 432 /* Can't set method when the card is off */ 433 if ((rdev->flags & RADEON_IS_PX) && 434 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 435 count = -EINVAL; 436 goto fail; 437 } 438 #endif 439 440 /* we don't support the legacy modes with dpm */ 441 if (rdev->pm.pm_method == PM_METHOD_DPM) { 442 count = -EINVAL; 443 goto fail; 444 } 445 446 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 447 mutex_lock(&rdev->pm.mutex); 448 rdev->pm.pm_method = PM_METHOD_DYNPM; 449 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 450 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 451 mutex_unlock(&rdev->pm.mutex); 452 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 453 mutex_lock(&rdev->pm.mutex); 454 /* disable dynpm */ 455 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 456 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 457 rdev->pm.pm_method = PM_METHOD_PROFILE; 458 mutex_unlock(&rdev->pm.mutex); 459 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 460 } else { 461 count = -EINVAL; 462 goto fail; 463 } 464 radeon_pm_compute_clocks(rdev); 465 fail: 466 return count; 467 } 468 469 static ssize_t radeon_get_dpm_state(struct device *dev, 470 struct device_attribute *attr, 471 char *buf) 472 { 473 struct drm_device *ddev = dev_get_drvdata(dev); 474 struct radeon_device *rdev = ddev->dev_private; 475 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 476 477 return snprintf(buf, PAGE_SIZE, "%s\n", 478 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 479 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 480 } 481 482 static ssize_t radeon_set_dpm_state(struct device *dev, 483 struct device_attribute *attr, 484 const char *buf, 485 size_t count) 486 { 487 struct drm_device *ddev = dev_get_drvdata(dev); 488 struct radeon_device *rdev = ddev->dev_private; 489 490 mutex_lock(&rdev->pm.mutex); 491 if (strncmp("battery", buf, strlen("battery")) == 0) 492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 493 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 494 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 495 else if (strncmp("performance", buf, strlen("performance")) == 0) 496 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 497 else { 498 mutex_unlock(&rdev->pm.mutex); 499 count = -EINVAL; 500 goto fail; 501 } 502 mutex_unlock(&rdev->pm.mutex); 503 504 /* Can't set dpm state when the card is off */ 505 #ifdef notyet 506 if (!(rdev->flags & RADEON_IS_PX) || 507 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 508 #endif 509 radeon_pm_compute_clocks(rdev); 510 511 fail: 512 return count; 513 } 514 515 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 516 struct device_attribute *attr, 517 char *buf) 518 { 519 struct drm_device *ddev = dev_get_drvdata(dev); 520 struct radeon_device *rdev = ddev->dev_private; 521 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 522 523 #ifdef notyet 524 if ((rdev->flags & RADEON_IS_PX) && 525 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 526 return snprintf(buf, PAGE_SIZE, "off\n"); 527 #endif 528 529 return snprintf(buf, PAGE_SIZE, "%s\n", 530 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 531 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 532 } 533 534 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 535 struct device_attribute *attr, 536 const char *buf, 537 size_t count) 538 { 539 struct drm_device *ddev = dev_get_drvdata(dev); 540 struct radeon_device *rdev = ddev->dev_private; 541 enum radeon_dpm_forced_level level; 542 int ret = 0; 543 544 /* Can't force performance level when the card is off */ 545 #ifdef notyet 546 if ((rdev->flags & RADEON_IS_PX) && 547 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 548 return -EINVAL; 549 #endif 550 551 mutex_lock(&rdev->pm.mutex); 552 if (strncmp("low", buf, strlen("low")) == 0) { 553 level = RADEON_DPM_FORCED_LEVEL_LOW; 554 } else if (strncmp("high", buf, strlen("high")) == 0) { 555 level = RADEON_DPM_FORCED_LEVEL_HIGH; 556 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 557 level = RADEON_DPM_FORCED_LEVEL_AUTO; 558 } else { 559 count = -EINVAL; 560 goto fail; 561 } 562 if (rdev->asic->dpm.force_performance_level) { 563 if (rdev->pm.dpm.thermal_active) { 564 count = -EINVAL; 565 goto fail; 566 } 567 ret = radeon_dpm_force_performance_level(rdev, level); 568 if (ret) 569 count = -EINVAL; 570 } 571 fail: 572 mutex_unlock(&rdev->pm.mutex); 573 574 return count; 575 } 576 #endif 577 578 #ifdef notyet 579 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 580 struct device_attribute *attr, 581 char *buf) 582 { 583 struct radeon_device *rdev = dev_get_drvdata(dev); 584 u32 pwm_mode = 0; 585 586 if (rdev->asic->dpm.fan_ctrl_get_mode) 587 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 588 589 /* never 0 (full-speed), fuse or smc-controlled always */ 590 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 591 } 592 593 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 594 struct device_attribute *attr, 595 const char *buf, 596 size_t count) 597 { 598 struct radeon_device *rdev = dev_get_drvdata(dev); 599 int err; 600 int value; 601 602 if(!rdev->asic->dpm.fan_ctrl_set_mode) 603 return -EINVAL; 604 605 err = kstrtoint(buf, 10, &value); 606 if (err) 607 return err; 608 609 switch (value) { 610 case 1: /* manual, percent-based */ 611 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 612 break; 613 default: /* disable */ 614 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 615 break; 616 } 617 618 return count; 619 } 620 621 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 622 struct device_attribute *attr, 623 char *buf) 624 { 625 return sprintf(buf, "%i\n", 0); 626 } 627 628 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 629 struct device_attribute *attr, 630 char *buf) 631 { 632 return sprintf(buf, "%i\n", 255); 633 } 634 635 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 636 struct device_attribute *attr, 637 const char *buf, size_t count) 638 { 639 struct radeon_device *rdev = dev_get_drvdata(dev); 640 int err; 641 u32 value; 642 643 err = kstrtou32(buf, 10, &value); 644 if (err) 645 return err; 646 647 value = (value * 100) / 255; 648 649 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 650 if (err) 651 return err; 652 653 return count; 654 } 655 656 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 657 struct device_attribute *attr, 658 char *buf) 659 { 660 struct radeon_device *rdev = dev_get_drvdata(dev); 661 int err; 662 u32 speed; 663 664 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 665 if (err) 666 return err; 667 668 speed = (speed * 255) / 100; 669 670 return sprintf(buf, "%i\n", speed); 671 } 672 673 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 674 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 675 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 676 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 677 radeon_get_dpm_forced_performance_level, 678 radeon_set_dpm_forced_performance_level); 679 680 static ssize_t radeon_hwmon_show_temp(struct device *dev, 681 struct device_attribute *attr, 682 char *buf) 683 { 684 struct radeon_device *rdev = dev_get_drvdata(dev); 685 struct drm_device *ddev = rdev->ddev; 686 int temp; 687 688 /* Can't get temperature when the card is off */ 689 if ((rdev->flags & RADEON_IS_PX) && 690 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 691 return -EINVAL; 692 693 if (rdev->asic->pm.get_temperature) 694 temp = radeon_get_temperature(rdev); 695 else 696 temp = 0; 697 698 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 699 } 700 701 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 702 struct device_attribute *attr, 703 char *buf) 704 { 705 struct radeon_device *rdev = dev_get_drvdata(dev); 706 int hyst = to_sensor_dev_attr(attr)->index; 707 int temp; 708 709 if (hyst) 710 temp = rdev->pm.dpm.thermal.min_temp; 711 else 712 temp = rdev->pm.dpm.thermal.max_temp; 713 714 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 715 } 716 717 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 718 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 719 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 720 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 721 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 722 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 723 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 724 725 726 static struct attribute *hwmon_attributes[] = { 727 &sensor_dev_attr_temp1_input.dev_attr.attr, 728 &sensor_dev_attr_temp1_crit.dev_attr.attr, 729 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 730 &sensor_dev_attr_pwm1.dev_attr.attr, 731 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 732 &sensor_dev_attr_pwm1_min.dev_attr.attr, 733 &sensor_dev_attr_pwm1_max.dev_attr.attr, 734 NULL 735 }; 736 737 static umode_t hwmon_attributes_visible(struct kobject *kobj, 738 struct attribute *attr, int index) 739 { 740 struct device *dev = kobj_to_dev(kobj); 741 struct radeon_device *rdev = dev_get_drvdata(dev); 742 umode_t effective_mode = attr->mode; 743 744 /* Skip attributes if DPM is not enabled */ 745 if (rdev->pm.pm_method != PM_METHOD_DPM && 746 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 747 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 748 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 749 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 750 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 751 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 752 return 0; 753 754 /* Skip fan attributes if fan is not present */ 755 if (rdev->pm.no_fan && 756 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 757 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 758 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 759 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 760 return 0; 761 762 /* mask fan attributes if we have no bindings for this asic to expose */ 763 if ((!rdev->asic->dpm.get_fan_speed_percent && 764 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 765 (!rdev->asic->dpm.fan_ctrl_get_mode && 766 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 767 effective_mode &= ~S_IRUGO; 768 769 if ((!rdev->asic->dpm.set_fan_speed_percent && 770 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 771 (!rdev->asic->dpm.fan_ctrl_set_mode && 772 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 773 effective_mode &= ~S_IWUSR; 774 775 /* hide max/min values if we can't both query and manage the fan */ 776 if ((!rdev->asic->dpm.set_fan_speed_percent && 777 !rdev->asic->dpm.get_fan_speed_percent) && 778 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 779 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 780 return 0; 781 782 return effective_mode; 783 } 784 785 static const struct attribute_group hwmon_attrgroup = { 786 .attrs = hwmon_attributes, 787 .is_visible = hwmon_attributes_visible, 788 }; 789 790 static const struct attribute_group *hwmon_groups[] = { 791 &hwmon_attrgroup, 792 NULL 793 }; 794 #endif 795 796 static int radeon_hwmon_init(struct radeon_device *rdev) 797 { 798 int err = 0; 799 800 switch (rdev->pm.int_thermal_type) { 801 case THERMAL_TYPE_RV6XX: 802 case THERMAL_TYPE_RV770: 803 case THERMAL_TYPE_EVERGREEN: 804 case THERMAL_TYPE_NI: 805 case THERMAL_TYPE_SUMO: 806 case THERMAL_TYPE_SI: 807 case THERMAL_TYPE_CI: 808 case THERMAL_TYPE_KV: 809 if (rdev->asic->pm.get_temperature == NULL) 810 return err; 811 #ifdef notyet 812 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 813 "radeon", rdev, 814 hwmon_groups); 815 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 816 err = PTR_ERR(rdev->pm.int_hwmon_dev); 817 dev_err(rdev->dev, 818 "Unable to register hwmon device: %d\n", err); 819 } 820 #endif 821 break; 822 default: 823 break; 824 } 825 826 return err; 827 } 828 829 static void radeon_hwmon_fini(struct radeon_device *rdev) 830 { 831 #ifdef notyet 832 if (rdev->pm.int_hwmon_dev) 833 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 834 #endif 835 } 836 837 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 838 { 839 struct radeon_device *rdev = 840 container_of(work, struct radeon_device, 841 pm.dpm.thermal.work); 842 /* switch to the thermal state */ 843 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 844 845 if (!rdev->pm.dpm_enabled) 846 return; 847 848 if (rdev->asic->pm.get_temperature) { 849 int temp = radeon_get_temperature(rdev); 850 851 if (temp < rdev->pm.dpm.thermal.min_temp) 852 /* switch back the user state */ 853 dpm_state = rdev->pm.dpm.user_state; 854 } else { 855 if (rdev->pm.dpm.thermal.high_to_low) 856 /* switch back the user state */ 857 dpm_state = rdev->pm.dpm.user_state; 858 } 859 mutex_lock(&rdev->pm.mutex); 860 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 861 rdev->pm.dpm.thermal_active = true; 862 else 863 rdev->pm.dpm.thermal_active = false; 864 rdev->pm.dpm.state = dpm_state; 865 mutex_unlock(&rdev->pm.mutex); 866 867 radeon_pm_compute_clocks(rdev); 868 } 869 870 static bool radeon_dpm_single_display(struct radeon_device *rdev) 871 { 872 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 873 true : false; 874 875 /* check if the vblank period is too short to adjust the mclk */ 876 if (single_display && rdev->asic->dpm.vblank_too_short) { 877 if (radeon_dpm_vblank_too_short(rdev)) 878 single_display = false; 879 } 880 881 /* 120hz tends to be problematic even if they are under the 882 * vblank limit. 883 */ 884 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 885 single_display = false; 886 887 return single_display; 888 } 889 890 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 891 enum radeon_pm_state_type dpm_state) 892 { 893 int i; 894 struct radeon_ps *ps; 895 u32 ui_class; 896 bool single_display = radeon_dpm_single_display(rdev); 897 898 /* certain older asics have a separare 3D performance state, 899 * so try that first if the user selected performance 900 */ 901 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 902 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 903 /* balanced states don't exist at the moment */ 904 if (dpm_state == POWER_STATE_TYPE_BALANCED) 905 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 906 907 restart_search: 908 /* Pick the best power state based on current conditions */ 909 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 910 ps = &rdev->pm.dpm.ps[i]; 911 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 912 switch (dpm_state) { 913 /* user states */ 914 case POWER_STATE_TYPE_BATTERY: 915 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 916 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 917 if (single_display) 918 return ps; 919 } else 920 return ps; 921 } 922 break; 923 case POWER_STATE_TYPE_BALANCED: 924 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 925 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 926 if (single_display) 927 return ps; 928 } else 929 return ps; 930 } 931 break; 932 case POWER_STATE_TYPE_PERFORMANCE: 933 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 934 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 935 if (single_display) 936 return ps; 937 } else 938 return ps; 939 } 940 break; 941 /* internal states */ 942 case POWER_STATE_TYPE_INTERNAL_UVD: 943 if (rdev->pm.dpm.uvd_ps) 944 return rdev->pm.dpm.uvd_ps; 945 else 946 break; 947 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 948 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 949 return ps; 950 break; 951 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 952 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 953 return ps; 954 break; 955 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 956 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 957 return ps; 958 break; 959 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 960 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 961 return ps; 962 break; 963 case POWER_STATE_TYPE_INTERNAL_BOOT: 964 return rdev->pm.dpm.boot_ps; 965 case POWER_STATE_TYPE_INTERNAL_THERMAL: 966 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 967 return ps; 968 break; 969 case POWER_STATE_TYPE_INTERNAL_ACPI: 970 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 971 return ps; 972 break; 973 case POWER_STATE_TYPE_INTERNAL_ULV: 974 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 975 return ps; 976 break; 977 case POWER_STATE_TYPE_INTERNAL_3DPERF: 978 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 979 return ps; 980 break; 981 default: 982 break; 983 } 984 } 985 /* use a fallback state if we didn't match */ 986 switch (dpm_state) { 987 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 988 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 989 goto restart_search; 990 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 991 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 992 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 993 if (rdev->pm.dpm.uvd_ps) { 994 return rdev->pm.dpm.uvd_ps; 995 } else { 996 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 997 goto restart_search; 998 } 999 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1000 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 1001 goto restart_search; 1002 case POWER_STATE_TYPE_INTERNAL_ACPI: 1003 dpm_state = POWER_STATE_TYPE_BATTERY; 1004 goto restart_search; 1005 case POWER_STATE_TYPE_BATTERY: 1006 case POWER_STATE_TYPE_BALANCED: 1007 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1008 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1009 goto restart_search; 1010 default: 1011 break; 1012 } 1013 1014 return NULL; 1015 } 1016 1017 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 1018 { 1019 int i; 1020 struct radeon_ps *ps; 1021 enum radeon_pm_state_type dpm_state; 1022 int ret; 1023 bool single_display = radeon_dpm_single_display(rdev); 1024 1025 /* if dpm init failed */ 1026 if (!rdev->pm.dpm_enabled) 1027 return; 1028 1029 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1030 /* add other state override checks here */ 1031 if ((!rdev->pm.dpm.thermal_active) && 1032 (!rdev->pm.dpm.uvd_active)) 1033 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1034 } 1035 dpm_state = rdev->pm.dpm.state; 1036 1037 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1038 if (ps) 1039 rdev->pm.dpm.requested_ps = ps; 1040 else 1041 return; 1042 1043 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1044 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1045 /* vce just modifies an existing state so force a change */ 1046 if (ps->vce_active != rdev->pm.dpm.vce_active) 1047 goto force; 1048 /* user has made a display change (such as timing) */ 1049 if (rdev->pm.dpm.single_display != single_display) 1050 goto force; 1051 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1052 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1053 * all we need to do is update the display configuration. 1054 */ 1055 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1056 /* update display watermarks based on new power state */ 1057 radeon_bandwidth_update(rdev); 1058 /* update displays */ 1059 radeon_dpm_display_configuration_changed(rdev); 1060 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1061 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1062 } 1063 return; 1064 } else { 1065 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1066 * nothing to do, if the num crtcs is > 1 and state is the same, 1067 * update display configuration. 1068 */ 1069 if (rdev->pm.dpm.new_active_crtcs == 1070 rdev->pm.dpm.current_active_crtcs) { 1071 return; 1072 } else { 1073 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1074 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1075 /* update display watermarks based on new power state */ 1076 radeon_bandwidth_update(rdev); 1077 /* update displays */ 1078 radeon_dpm_display_configuration_changed(rdev); 1079 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1080 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1081 return; 1082 } 1083 } 1084 } 1085 } 1086 1087 force: 1088 if (radeon_dpm == 1) { 1089 printk("switching from power state:\n"); 1090 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1091 printk("switching to power state:\n"); 1092 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1093 } 1094 1095 down_write(&rdev->pm.mclk_lock); 1096 mutex_lock(&rdev->ring_lock); 1097 1098 /* update whether vce is active */ 1099 ps->vce_active = rdev->pm.dpm.vce_active; 1100 1101 ret = radeon_dpm_pre_set_power_state(rdev); 1102 if (ret) 1103 goto done; 1104 1105 /* update display watermarks based on new power state */ 1106 radeon_bandwidth_update(rdev); 1107 /* update displays */ 1108 radeon_dpm_display_configuration_changed(rdev); 1109 1110 /* wait for the rings to drain */ 1111 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1112 struct radeon_ring *ring = &rdev->ring[i]; 1113 if (ring->ready) 1114 radeon_fence_wait_empty(rdev, i); 1115 } 1116 1117 /* program the new power state */ 1118 radeon_dpm_set_power_state(rdev); 1119 1120 /* update current power state */ 1121 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1122 1123 radeon_dpm_post_set_power_state(rdev); 1124 1125 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1126 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1127 rdev->pm.dpm.single_display = single_display; 1128 1129 if (rdev->asic->dpm.force_performance_level) { 1130 if (rdev->pm.dpm.thermal_active) { 1131 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1132 /* force low perf level for thermal */ 1133 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1134 /* save the user's level */ 1135 rdev->pm.dpm.forced_level = level; 1136 } else { 1137 /* otherwise, user selected level */ 1138 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1139 } 1140 } 1141 1142 done: 1143 mutex_unlock(&rdev->ring_lock); 1144 up_write(&rdev->pm.mclk_lock); 1145 } 1146 1147 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1148 { 1149 enum radeon_pm_state_type dpm_state; 1150 1151 if (rdev->asic->dpm.powergate_uvd) { 1152 mutex_lock(&rdev->pm.mutex); 1153 /* don't powergate anything if we 1154 have active but pause streams */ 1155 enable |= rdev->pm.dpm.sd > 0; 1156 enable |= rdev->pm.dpm.hd > 0; 1157 /* enable/disable UVD */ 1158 radeon_dpm_powergate_uvd(rdev, !enable); 1159 mutex_unlock(&rdev->pm.mutex); 1160 } else { 1161 if (enable) { 1162 mutex_lock(&rdev->pm.mutex); 1163 rdev->pm.dpm.uvd_active = true; 1164 /* disable this for now */ 1165 #if 0 1166 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1167 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1168 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1169 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1170 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1171 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1172 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1173 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1174 else 1175 #endif 1176 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1177 rdev->pm.dpm.state = dpm_state; 1178 mutex_unlock(&rdev->pm.mutex); 1179 } else { 1180 mutex_lock(&rdev->pm.mutex); 1181 rdev->pm.dpm.uvd_active = false; 1182 mutex_unlock(&rdev->pm.mutex); 1183 } 1184 1185 radeon_pm_compute_clocks(rdev); 1186 } 1187 } 1188 1189 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1190 { 1191 if (enable) { 1192 mutex_lock(&rdev->pm.mutex); 1193 rdev->pm.dpm.vce_active = true; 1194 /* XXX select vce level based on ring/task */ 1195 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1196 mutex_unlock(&rdev->pm.mutex); 1197 } else { 1198 mutex_lock(&rdev->pm.mutex); 1199 rdev->pm.dpm.vce_active = false; 1200 mutex_unlock(&rdev->pm.mutex); 1201 } 1202 1203 radeon_pm_compute_clocks(rdev); 1204 } 1205 1206 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1207 { 1208 mutex_lock(&rdev->pm.mutex); 1209 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1210 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1211 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1212 } 1213 mutex_unlock(&rdev->pm.mutex); 1214 1215 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1216 } 1217 1218 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1219 { 1220 mutex_lock(&rdev->pm.mutex); 1221 /* disable dpm */ 1222 radeon_dpm_disable(rdev); 1223 /* reset the power state */ 1224 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1225 rdev->pm.dpm_enabled = false; 1226 mutex_unlock(&rdev->pm.mutex); 1227 } 1228 1229 void radeon_pm_suspend(struct radeon_device *rdev) 1230 { 1231 if (rdev->pm.pm_method == PM_METHOD_DPM) 1232 radeon_pm_suspend_dpm(rdev); 1233 else 1234 radeon_pm_suspend_old(rdev); 1235 } 1236 1237 static void radeon_pm_resume_old(struct radeon_device *rdev) 1238 { 1239 /* set up the default clocks if the MC ucode is loaded */ 1240 if ((rdev->family >= CHIP_BARTS) && 1241 (rdev->family <= CHIP_CAYMAN) && 1242 rdev->mc_fw) { 1243 if (rdev->pm.default_vddc) 1244 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1245 SET_VOLTAGE_TYPE_ASIC_VDDC); 1246 if (rdev->pm.default_vddci) 1247 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1248 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1249 if (rdev->pm.default_sclk) 1250 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1251 if (rdev->pm.default_mclk) 1252 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1253 } 1254 /* asic init will reset the default power state */ 1255 mutex_lock(&rdev->pm.mutex); 1256 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1257 rdev->pm.current_clock_mode_index = 0; 1258 rdev->pm.current_sclk = rdev->pm.default_sclk; 1259 rdev->pm.current_mclk = rdev->pm.default_mclk; 1260 if (rdev->pm.power_state) { 1261 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1262 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1263 } 1264 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1265 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1266 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1267 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1268 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1269 } 1270 mutex_unlock(&rdev->pm.mutex); 1271 radeon_pm_compute_clocks(rdev); 1272 } 1273 1274 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1275 { 1276 int ret; 1277 1278 /* asic init will reset to the boot state */ 1279 mutex_lock(&rdev->pm.mutex); 1280 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1281 radeon_dpm_setup_asic(rdev); 1282 ret = radeon_dpm_enable(rdev); 1283 mutex_unlock(&rdev->pm.mutex); 1284 if (ret) 1285 goto dpm_resume_fail; 1286 rdev->pm.dpm_enabled = true; 1287 return; 1288 1289 dpm_resume_fail: 1290 DRM_ERROR("radeon: dpm resume failed\n"); 1291 if ((rdev->family >= CHIP_BARTS) && 1292 (rdev->family <= CHIP_CAYMAN) && 1293 rdev->mc_fw) { 1294 if (rdev->pm.default_vddc) 1295 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1296 SET_VOLTAGE_TYPE_ASIC_VDDC); 1297 if (rdev->pm.default_vddci) 1298 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1299 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1300 if (rdev->pm.default_sclk) 1301 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1302 if (rdev->pm.default_mclk) 1303 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1304 } 1305 } 1306 1307 void radeon_pm_resume(struct radeon_device *rdev) 1308 { 1309 if (rdev->pm.pm_method == PM_METHOD_DPM) 1310 radeon_pm_resume_dpm(rdev); 1311 else 1312 radeon_pm_resume_old(rdev); 1313 } 1314 1315 static int radeon_pm_init_old(struct radeon_device *rdev) 1316 { 1317 int ret; 1318 1319 rdev->pm.profile = PM_PROFILE_DEFAULT; 1320 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1321 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1322 rdev->pm.dynpm_can_upclock = true; 1323 rdev->pm.dynpm_can_downclock = true; 1324 rdev->pm.default_sclk = rdev->clock.default_sclk; 1325 rdev->pm.default_mclk = rdev->clock.default_mclk; 1326 rdev->pm.current_sclk = rdev->clock.default_sclk; 1327 rdev->pm.current_mclk = rdev->clock.default_mclk; 1328 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1329 1330 if (rdev->bios) { 1331 if (rdev->is_atom_bios) 1332 radeon_atombios_get_power_modes(rdev); 1333 else 1334 radeon_combios_get_power_modes(rdev); 1335 radeon_pm_print_states(rdev); 1336 radeon_pm_init_profile(rdev); 1337 /* set up the default clocks if the MC ucode is loaded */ 1338 if ((rdev->family >= CHIP_BARTS) && 1339 (rdev->family <= CHIP_CAYMAN) && 1340 rdev->mc_fw) { 1341 if (rdev->pm.default_vddc) 1342 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1343 SET_VOLTAGE_TYPE_ASIC_VDDC); 1344 if (rdev->pm.default_vddci) 1345 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1346 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1347 if (rdev->pm.default_sclk) 1348 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1349 if (rdev->pm.default_mclk) 1350 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1351 } 1352 } 1353 1354 /* set up the internal thermal sensor if applicable */ 1355 ret = radeon_hwmon_init(rdev); 1356 if (ret) 1357 return ret; 1358 1359 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1360 1361 if (rdev->pm.num_power_states > 1) { 1362 if (radeon_debugfs_pm_init(rdev)) { 1363 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1364 } 1365 1366 DRM_INFO("radeon: power management initialized\n"); 1367 } 1368 1369 return 0; 1370 } 1371 1372 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1373 { 1374 int i; 1375 1376 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1377 printk("== power state %d ==\n", i); 1378 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1379 } 1380 } 1381 1382 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1383 { 1384 int ret; 1385 1386 /* default to balanced state */ 1387 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1388 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1389 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1390 rdev->pm.default_sclk = rdev->clock.default_sclk; 1391 rdev->pm.default_mclk = rdev->clock.default_mclk; 1392 rdev->pm.current_sclk = rdev->clock.default_sclk; 1393 rdev->pm.current_mclk = rdev->clock.default_mclk; 1394 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1395 1396 if (rdev->bios && rdev->is_atom_bios) 1397 radeon_atombios_get_power_modes(rdev); 1398 else 1399 return -EINVAL; 1400 1401 /* set up the internal thermal sensor if applicable */ 1402 ret = radeon_hwmon_init(rdev); 1403 if (ret) 1404 return ret; 1405 1406 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1407 mutex_lock(&rdev->pm.mutex); 1408 radeon_dpm_init(rdev); 1409 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1410 if (radeon_dpm == 1) 1411 radeon_dpm_print_power_states(rdev); 1412 radeon_dpm_setup_asic(rdev); 1413 ret = radeon_dpm_enable(rdev); 1414 mutex_unlock(&rdev->pm.mutex); 1415 if (ret) 1416 goto dpm_failed; 1417 rdev->pm.dpm_enabled = true; 1418 1419 if (radeon_debugfs_pm_init(rdev)) { 1420 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1421 } 1422 1423 DRM_INFO("radeon: dpm initialized\n"); 1424 1425 return 0; 1426 1427 dpm_failed: 1428 rdev->pm.dpm_enabled = false; 1429 if ((rdev->family >= CHIP_BARTS) && 1430 (rdev->family <= CHIP_CAYMAN) && 1431 rdev->mc_fw) { 1432 if (rdev->pm.default_vddc) 1433 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1434 SET_VOLTAGE_TYPE_ASIC_VDDC); 1435 if (rdev->pm.default_vddci) 1436 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1437 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1438 if (rdev->pm.default_sclk) 1439 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1440 if (rdev->pm.default_mclk) 1441 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1442 } 1443 DRM_ERROR("radeon: dpm initialization failed\n"); 1444 return ret; 1445 } 1446 1447 struct radeon_dpm_quirk { 1448 u32 chip_vendor; 1449 u32 chip_device; 1450 u32 subsys_vendor; 1451 u32 subsys_device; 1452 }; 1453 1454 /* cards with dpm stability problems */ 1455 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1456 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1457 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1458 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1459 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1460 { 0, 0, 0, 0 }, 1461 }; 1462 1463 int radeon_pm_init(struct radeon_device *rdev) 1464 { 1465 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1466 bool disable_dpm = false; 1467 1468 /* Apply dpm quirks */ 1469 while (p && p->chip_device != 0) { 1470 if (rdev->pdev->vendor == p->chip_vendor && 1471 rdev->pdev->device == p->chip_device && 1472 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1473 rdev->pdev->subsystem_device == p->subsys_device) { 1474 disable_dpm = true; 1475 break; 1476 } 1477 ++p; 1478 } 1479 1480 /* enable dpm on rv6xx+ */ 1481 switch (rdev->family) { 1482 case CHIP_RV610: 1483 case CHIP_RV630: 1484 case CHIP_RV620: 1485 case CHIP_RV635: 1486 case CHIP_RV670: 1487 case CHIP_RS780: 1488 case CHIP_RS880: 1489 case CHIP_RV770: 1490 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1491 if (!rdev->rlc_fw) 1492 rdev->pm.pm_method = PM_METHOD_PROFILE; 1493 else if ((rdev->family >= CHIP_RV770) && 1494 (!(rdev->flags & RADEON_IS_IGP)) && 1495 (!rdev->smc_fw)) 1496 rdev->pm.pm_method = PM_METHOD_PROFILE; 1497 else if (radeon_dpm == 1) 1498 rdev->pm.pm_method = PM_METHOD_DPM; 1499 else 1500 rdev->pm.pm_method = PM_METHOD_PROFILE; 1501 break; 1502 case CHIP_RV730: 1503 case CHIP_RV710: 1504 case CHIP_RV740: 1505 case CHIP_CEDAR: 1506 case CHIP_REDWOOD: 1507 case CHIP_JUNIPER: 1508 case CHIP_CYPRESS: 1509 case CHIP_HEMLOCK: 1510 case CHIP_PALM: 1511 case CHIP_SUMO: 1512 case CHIP_SUMO2: 1513 case CHIP_BARTS: 1514 case CHIP_TURKS: 1515 case CHIP_CAICOS: 1516 case CHIP_CAYMAN: 1517 case CHIP_ARUBA: 1518 case CHIP_TAHITI: 1519 case CHIP_PITCAIRN: 1520 case CHIP_VERDE: 1521 case CHIP_OLAND: 1522 case CHIP_HAINAN: 1523 case CHIP_BONAIRE: 1524 case CHIP_KABINI: 1525 case CHIP_KAVERI: 1526 case CHIP_HAWAII: 1527 case CHIP_MULLINS: 1528 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1529 if (!rdev->rlc_fw) 1530 rdev->pm.pm_method = PM_METHOD_PROFILE; 1531 else if ((rdev->family >= CHIP_RV770) && 1532 (!(rdev->flags & RADEON_IS_IGP)) && 1533 (!rdev->smc_fw)) 1534 rdev->pm.pm_method = PM_METHOD_PROFILE; 1535 else if (disable_dpm && (radeon_dpm == -1)) 1536 rdev->pm.pm_method = PM_METHOD_PROFILE; 1537 else if (radeon_dpm == 0) 1538 rdev->pm.pm_method = PM_METHOD_PROFILE; 1539 else 1540 rdev->pm.pm_method = PM_METHOD_DPM; 1541 break; 1542 default: 1543 /* default to profile method */ 1544 rdev->pm.pm_method = PM_METHOD_PROFILE; 1545 break; 1546 } 1547 1548 if (rdev->pm.pm_method == PM_METHOD_DPM) 1549 return radeon_pm_init_dpm(rdev); 1550 else 1551 return radeon_pm_init_old(rdev); 1552 } 1553 1554 int radeon_pm_late_init(struct radeon_device *rdev) 1555 { 1556 int ret = 0; 1557 1558 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1559 if (rdev->pm.dpm_enabled) { 1560 #ifdef __linux__ 1561 if (!rdev->pm.sysfs_initialized) { 1562 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1563 if (ret) 1564 DRM_ERROR("failed to create device file for dpm state\n"); 1565 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1566 if (ret) 1567 DRM_ERROR("failed to create device file for dpm state\n"); 1568 /* XXX: these are noops for dpm but are here for backwards compat */ 1569 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1570 if (ret) 1571 DRM_ERROR("failed to create device file for power profile\n"); 1572 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1573 if (ret) 1574 DRM_ERROR("failed to create device file for power method\n"); 1575 rdev->pm.sysfs_initialized = true; 1576 } 1577 #endif 1578 1579 mutex_lock(&rdev->pm.mutex); 1580 ret = radeon_dpm_late_enable(rdev); 1581 mutex_unlock(&rdev->pm.mutex); 1582 if (ret) { 1583 rdev->pm.dpm_enabled = false; 1584 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1585 } else { 1586 /* set the dpm state for PX since there won't be 1587 * a modeset to call this. 1588 */ 1589 radeon_pm_compute_clocks(rdev); 1590 } 1591 } 1592 } else { 1593 #ifdef __linux__ 1594 if ((rdev->pm.num_power_states > 1) && 1595 (!rdev->pm.sysfs_initialized)) { 1596 /* where's the best place to put these? */ 1597 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1598 if (ret) 1599 DRM_ERROR("failed to create device file for power profile\n"); 1600 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1601 if (ret) 1602 DRM_ERROR("failed to create device file for power method\n"); 1603 if (!ret) 1604 rdev->pm.sysfs_initialized = true; 1605 } 1606 #endif 1607 } 1608 return ret; 1609 } 1610 1611 static void radeon_pm_fini_old(struct radeon_device *rdev) 1612 { 1613 if (rdev->pm.num_power_states > 1) { 1614 mutex_lock(&rdev->pm.mutex); 1615 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1616 rdev->pm.profile = PM_PROFILE_DEFAULT; 1617 radeon_pm_update_profile(rdev); 1618 radeon_pm_set_clocks(rdev); 1619 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1620 /* reset default clocks */ 1621 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1622 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1623 radeon_pm_set_clocks(rdev); 1624 } 1625 mutex_unlock(&rdev->pm.mutex); 1626 1627 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1628 1629 #ifdef __linux__ 1630 device_remove_file(rdev->dev, &dev_attr_power_profile); 1631 device_remove_file(rdev->dev, &dev_attr_power_method); 1632 #endif 1633 } 1634 1635 radeon_hwmon_fini(rdev); 1636 kfree(rdev->pm.power_state); 1637 } 1638 1639 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1640 { 1641 if (rdev->pm.num_power_states > 1) { 1642 mutex_lock(&rdev->pm.mutex); 1643 radeon_dpm_disable(rdev); 1644 mutex_unlock(&rdev->pm.mutex); 1645 1646 #ifdef __linux__ 1647 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1648 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1649 /* XXX backwards compat */ 1650 device_remove_file(rdev->dev, &dev_attr_power_profile); 1651 device_remove_file(rdev->dev, &dev_attr_power_method); 1652 #endif 1653 } 1654 radeon_dpm_fini(rdev); 1655 1656 radeon_hwmon_fini(rdev); 1657 kfree(rdev->pm.power_state); 1658 } 1659 1660 void radeon_pm_fini(struct radeon_device *rdev) 1661 { 1662 if (rdev->pm.pm_method == PM_METHOD_DPM) 1663 radeon_pm_fini_dpm(rdev); 1664 else 1665 radeon_pm_fini_old(rdev); 1666 } 1667 1668 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1669 { 1670 struct drm_device *ddev = rdev->ddev; 1671 struct drm_crtc *crtc; 1672 struct radeon_crtc *radeon_crtc; 1673 1674 if (rdev->pm.num_power_states < 2) 1675 return; 1676 1677 mutex_lock(&rdev->pm.mutex); 1678 1679 rdev->pm.active_crtcs = 0; 1680 rdev->pm.active_crtc_count = 0; 1681 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1682 list_for_each_entry(crtc, 1683 &ddev->mode_config.crtc_list, head) { 1684 radeon_crtc = to_radeon_crtc(crtc); 1685 if (radeon_crtc->enabled) { 1686 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1687 rdev->pm.active_crtc_count++; 1688 } 1689 } 1690 } 1691 1692 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1693 radeon_pm_update_profile(rdev); 1694 radeon_pm_set_clocks(rdev); 1695 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1696 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1697 if (rdev->pm.active_crtc_count > 1) { 1698 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1699 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1700 1701 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1702 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1703 radeon_pm_get_dynpm_state(rdev); 1704 radeon_pm_set_clocks(rdev); 1705 1706 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1707 } 1708 } else if (rdev->pm.active_crtc_count == 1) { 1709 /* TODO: Increase clocks if needed for current mode */ 1710 1711 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1712 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1713 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1714 radeon_pm_get_dynpm_state(rdev); 1715 radeon_pm_set_clocks(rdev); 1716 1717 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1718 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1719 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1720 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1721 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1722 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1723 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1724 } 1725 } else { /* count == 0 */ 1726 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1727 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1728 1729 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1730 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1731 radeon_pm_get_dynpm_state(rdev); 1732 radeon_pm_set_clocks(rdev); 1733 } 1734 } 1735 } 1736 } 1737 1738 mutex_unlock(&rdev->pm.mutex); 1739 } 1740 1741 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1742 { 1743 struct drm_device *ddev = rdev->ddev; 1744 struct drm_crtc *crtc; 1745 struct radeon_crtc *radeon_crtc; 1746 1747 if (!rdev->pm.dpm_enabled) 1748 return; 1749 1750 mutex_lock(&rdev->pm.mutex); 1751 1752 /* update active crtc counts */ 1753 rdev->pm.dpm.new_active_crtcs = 0; 1754 rdev->pm.dpm.new_active_crtc_count = 0; 1755 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1756 list_for_each_entry(crtc, 1757 &ddev->mode_config.crtc_list, head) { 1758 radeon_crtc = to_radeon_crtc(crtc); 1759 if (crtc->enabled) { 1760 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1761 rdev->pm.dpm.new_active_crtc_count++; 1762 } 1763 } 1764 } 1765 1766 /* update battery/ac status */ 1767 if (power_supply_is_system_supplied() > 0) 1768 rdev->pm.dpm.ac_power = true; 1769 else 1770 rdev->pm.dpm.ac_power = false; 1771 1772 radeon_dpm_change_power_state_locked(rdev); 1773 1774 mutex_unlock(&rdev->pm.mutex); 1775 1776 } 1777 1778 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1779 { 1780 if (rdev->pm.pm_method == PM_METHOD_DPM) 1781 radeon_pm_compute_clocks_dpm(rdev); 1782 else 1783 radeon_pm_compute_clocks_old(rdev); 1784 } 1785 1786 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1787 { 1788 int crtc, vpos, hpos, vbl_status; 1789 bool in_vbl = true; 1790 1791 /* Iterate over all active crtc's. All crtc's must be in vblank, 1792 * otherwise return in_vbl == false. 1793 */ 1794 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1795 if (rdev->pm.active_crtcs & (1 << crtc)) { 1796 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1797 crtc, 1798 USE_REAL_VBLANKSTART, 1799 &vpos, &hpos, NULL, NULL, 1800 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1801 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1802 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1803 in_vbl = false; 1804 } 1805 } 1806 1807 return in_vbl; 1808 } 1809 1810 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1811 { 1812 #ifdef DRMDEBUG 1813 u32 stat_crtc = 0; 1814 #endif 1815 bool in_vbl = radeon_pm_in_vbl(rdev); 1816 1817 if (in_vbl == false) 1818 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1819 finish ? "exit" : "entry"); 1820 return in_vbl; 1821 } 1822 1823 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1824 { 1825 struct radeon_device *rdev; 1826 int resched; 1827 rdev = container_of(work, struct radeon_device, 1828 pm.dynpm_idle_work.work); 1829 1830 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1831 mutex_lock(&rdev->pm.mutex); 1832 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1833 int not_processed = 0; 1834 int i; 1835 1836 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1837 struct radeon_ring *ring = &rdev->ring[i]; 1838 1839 if (ring->ready) { 1840 not_processed += radeon_fence_count_emitted(rdev, i); 1841 if (not_processed >= 3) 1842 break; 1843 } 1844 } 1845 1846 if (not_processed >= 3) { /* should upclock */ 1847 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1848 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1849 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1850 rdev->pm.dynpm_can_upclock) { 1851 rdev->pm.dynpm_planned_action = 1852 DYNPM_ACTION_UPCLOCK; 1853 rdev->pm.dynpm_action_timeout = jiffies + 1854 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1855 } 1856 } else if (not_processed == 0) { /* should downclock */ 1857 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1858 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1859 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1860 rdev->pm.dynpm_can_downclock) { 1861 rdev->pm.dynpm_planned_action = 1862 DYNPM_ACTION_DOWNCLOCK; 1863 rdev->pm.dynpm_action_timeout = jiffies + 1864 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1865 } 1866 } 1867 1868 /* Note, radeon_pm_set_clocks is called with static_switch set 1869 * to false since we want to wait for vbl to avoid flicker. 1870 */ 1871 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1872 jiffies > rdev->pm.dynpm_action_timeout) { 1873 radeon_pm_get_dynpm_state(rdev); 1874 radeon_pm_set_clocks(rdev); 1875 } 1876 1877 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1878 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1879 } 1880 mutex_unlock(&rdev->pm.mutex); 1881 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1882 } 1883 1884 /* 1885 * Debugfs info 1886 */ 1887 #if defined(CONFIG_DEBUG_FS) 1888 1889 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1890 { 1891 struct drm_info_node *node = (struct drm_info_node *) m->private; 1892 struct drm_device *dev = node->minor->dev; 1893 struct radeon_device *rdev = dev->dev_private; 1894 struct drm_device *ddev = rdev->ddev; 1895 1896 if ((rdev->flags & RADEON_IS_PX) && 1897 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1898 seq_printf(m, "PX asic powered off\n"); 1899 } else if (rdev->pm.dpm_enabled) { 1900 mutex_lock(&rdev->pm.mutex); 1901 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1902 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1903 else 1904 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1905 mutex_unlock(&rdev->pm.mutex); 1906 } else { 1907 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1908 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1909 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1910 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1911 else 1912 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1913 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1914 if (rdev->asic->pm.get_memory_clock) 1915 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1916 if (rdev->pm.current_vddc) 1917 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1918 if (rdev->asic->pm.get_pcie_lanes) 1919 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1920 } 1921 1922 return 0; 1923 } 1924 1925 static struct drm_info_list radeon_pm_info_list[] = { 1926 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1927 }; 1928 #endif 1929 1930 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 1931 { 1932 #if defined(CONFIG_DEBUG_FS) 1933 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 1934 #else 1935 return 0; 1936 #endif 1937 } 1938