1 /* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 24 #include <linux/hwmon-sysfs.h> 25 #include <linux/hwmon.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 29 #include <drm/drm_debugfs.h> 30 #include <drm/drm_vblank.h> 31 32 #include "atom.h" 33 #include "avivod.h" 34 #include "r600_dpm.h" 35 #include "radeon.h" 36 37 #define RADEON_IDLE_LOOP_MS 100 38 #define RADEON_RECLOCK_DELAY_MS 200 39 #define RADEON_WAIT_VBLANK_TIMEOUT 200 40 41 static const char *radeon_pm_state_type_name[5] = { 42 "", 43 "Powersave", 44 "Battery", 45 "Balanced", 46 "Performance", 47 }; 48 49 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 50 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 51 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 52 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 53 static void radeon_pm_update_profile(struct radeon_device *rdev); 54 static void radeon_pm_set_clocks(struct radeon_device *rdev); 55 56 int radeon_pm_get_type_index(struct radeon_device *rdev, 57 enum radeon_pm_state_type ps_type, 58 int instance) 59 { 60 int i; 61 int found_instance = -1; 62 63 for (i = 0; i < rdev->pm.num_power_states; i++) { 64 if (rdev->pm.power_state[i].type == ps_type) { 65 found_instance++; 66 if (found_instance == instance) 67 return i; 68 } 69 } 70 /* return default if no match */ 71 return rdev->pm.default_power_state_index; 72 } 73 74 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 75 { 76 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 77 mutex_lock(&rdev->pm.mutex); 78 if (power_supply_is_system_supplied() > 0) 79 rdev->pm.dpm.ac_power = true; 80 else 81 rdev->pm.dpm.ac_power = false; 82 if (rdev->family == CHIP_ARUBA) { 83 if (rdev->asic->dpm.enable_bapm) 84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 85 } 86 mutex_unlock(&rdev->pm.mutex); 87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 88 if (rdev->pm.profile == PM_PROFILE_AUTO) { 89 mutex_lock(&rdev->pm.mutex); 90 radeon_pm_update_profile(rdev); 91 radeon_pm_set_clocks(rdev); 92 mutex_unlock(&rdev->pm.mutex); 93 } 94 } 95 } 96 97 static void radeon_pm_update_profile(struct radeon_device *rdev) 98 { 99 switch (rdev->pm.profile) { 100 case PM_PROFILE_DEFAULT: 101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 102 break; 103 case PM_PROFILE_AUTO: 104 if (power_supply_is_system_supplied() > 0) { 105 if (rdev->pm.active_crtc_count > 1) 106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 107 else 108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 109 } else { 110 if (rdev->pm.active_crtc_count > 1) 111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 112 else 113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 114 } 115 break; 116 case PM_PROFILE_LOW: 117 if (rdev->pm.active_crtc_count > 1) 118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 119 else 120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 121 break; 122 case PM_PROFILE_MID: 123 if (rdev->pm.active_crtc_count > 1) 124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 125 else 126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 127 break; 128 case PM_PROFILE_HIGH: 129 if (rdev->pm.active_crtc_count > 1) 130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 131 else 132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 133 break; 134 } 135 136 if (rdev->pm.active_crtc_count == 0) { 137 rdev->pm.requested_power_state_index = 138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 139 rdev->pm.requested_clock_mode_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 141 } else { 142 rdev->pm.requested_power_state_index = 143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 144 rdev->pm.requested_clock_mode_index = 145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 146 } 147 } 148 149 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 150 { 151 struct radeon_bo *bo, *n; 152 153 if (list_empty(&rdev->gem.objects)) 154 return; 155 156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 157 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 158 ttm_bo_unmap_virtual(&bo->tbo); 159 } 160 } 161 162 static void radeon_sync_with_vblank(struct radeon_device *rdev) 163 { 164 if (rdev->pm.active_crtcs) { 165 rdev->pm.vblank_sync = false; 166 wait_event_timeout( 167 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 168 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 169 } 170 } 171 172 static void radeon_set_power_state(struct radeon_device *rdev) 173 { 174 u32 sclk, mclk; 175 bool misc_after = false; 176 177 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 178 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 179 return; 180 181 if (radeon_gui_idle(rdev)) { 182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 183 clock_info[rdev->pm.requested_clock_mode_index].sclk; 184 if (sclk > rdev->pm.default_sclk) 185 sclk = rdev->pm.default_sclk; 186 187 /* starting with BTC, there is one state that is used for both 188 * MH and SH. Difference is that we always use the high clock index for 189 * mclk and vddci. 190 */ 191 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 192 (rdev->family >= CHIP_BARTS) && 193 rdev->pm.active_crtc_count && 194 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 195 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 197 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 198 else 199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 200 clock_info[rdev->pm.requested_clock_mode_index].mclk; 201 202 if (mclk > rdev->pm.default_mclk) 203 mclk = rdev->pm.default_mclk; 204 205 /* upvolt before raising clocks, downvolt after lowering clocks */ 206 if (sclk < rdev->pm.current_sclk) 207 misc_after = true; 208 209 radeon_sync_with_vblank(rdev); 210 211 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 212 if (!radeon_pm_in_vbl(rdev)) 213 return; 214 } 215 216 radeon_pm_prepare(rdev); 217 218 if (!misc_after) 219 /* voltage, pcie lanes, etc.*/ 220 radeon_pm_misc(rdev); 221 222 /* set engine clock */ 223 if (sclk != rdev->pm.current_sclk) { 224 radeon_pm_debug_check_in_vbl(rdev, false); 225 radeon_set_engine_clock(rdev, sclk); 226 radeon_pm_debug_check_in_vbl(rdev, true); 227 rdev->pm.current_sclk = sclk; 228 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 229 } 230 231 /* set memory clock */ 232 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 233 radeon_pm_debug_check_in_vbl(rdev, false); 234 radeon_set_memory_clock(rdev, mclk); 235 radeon_pm_debug_check_in_vbl(rdev, true); 236 rdev->pm.current_mclk = mclk; 237 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 238 } 239 240 if (misc_after) 241 /* voltage, pcie lanes, etc.*/ 242 radeon_pm_misc(rdev); 243 244 radeon_pm_finish(rdev); 245 246 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 247 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 248 } else 249 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 250 } 251 252 static void radeon_pm_set_clocks(struct radeon_device *rdev) 253 { 254 struct drm_crtc *crtc; 255 int i, r; 256 257 /* no need to take locks, etc. if nothing's going to change */ 258 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 259 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 260 return; 261 262 down_write(&rdev->pm.mclk_lock); 263 mutex_lock(&rdev->ring_lock); 264 265 /* wait for the rings to drain */ 266 for (i = 0; i < RADEON_NUM_RINGS; i++) { 267 struct radeon_ring *ring = &rdev->ring[i]; 268 if (!ring->ready) { 269 continue; 270 } 271 r = radeon_fence_wait_empty(rdev, i); 272 if (r) { 273 /* needs a GPU reset dont reset here */ 274 mutex_unlock(&rdev->ring_lock); 275 up_write(&rdev->pm.mclk_lock); 276 return; 277 } 278 } 279 280 radeon_unmap_vram_bos(rdev); 281 282 if (rdev->irq.installed) { 283 i = 0; 284 drm_for_each_crtc(crtc, rdev->ddev) { 285 if (rdev->pm.active_crtcs & (1 << i)) { 286 /* This can fail if a modeset is in progress */ 287 if (drm_crtc_vblank_get(crtc) == 0) 288 rdev->pm.req_vblank |= (1 << i); 289 else 290 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", 291 i); 292 } 293 i++; 294 } 295 } 296 297 radeon_set_power_state(rdev); 298 299 if (rdev->irq.installed) { 300 i = 0; 301 drm_for_each_crtc(crtc, rdev->ddev) { 302 if (rdev->pm.req_vblank & (1 << i)) { 303 rdev->pm.req_vblank &= ~(1 << i); 304 drm_crtc_vblank_put(crtc); 305 } 306 i++; 307 } 308 } 309 310 /* update display watermarks based on new power state */ 311 radeon_update_bandwidth_info(rdev); 312 if (rdev->pm.active_crtc_count) 313 radeon_bandwidth_update(rdev); 314 315 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 316 317 mutex_unlock(&rdev->ring_lock); 318 up_write(&rdev->pm.mclk_lock); 319 } 320 321 static void radeon_pm_print_states(struct radeon_device *rdev) 322 { 323 int i, j; 324 struct radeon_power_state *power_state; 325 struct radeon_pm_clock_info *clock_info; 326 327 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 328 for (i = 0; i < rdev->pm.num_power_states; i++) { 329 power_state = &rdev->pm.power_state[i]; 330 DRM_DEBUG_DRIVER("State %d: %s\n", i, 331 radeon_pm_state_type_name[power_state->type]); 332 if (i == rdev->pm.default_power_state_index) 333 DRM_DEBUG_DRIVER("\tDefault"); 334 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 335 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 336 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 337 DRM_DEBUG_DRIVER("\tSingle display only\n"); 338 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 339 for (j = 0; j < power_state->num_clock_modes; j++) { 340 clock_info = &(power_state->clock_info[j]); 341 if (rdev->flags & RADEON_IS_IGP) 342 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 343 j, 344 clock_info->sclk * 10); 345 else 346 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 347 j, 348 clock_info->sclk * 10, 349 clock_info->mclk * 10, 350 clock_info->voltage.voltage); 351 } 352 } 353 } 354 355 #ifdef notyet 356 static ssize_t radeon_get_pm_profile(struct device *dev, 357 struct device_attribute *attr, 358 char *buf) 359 { 360 struct drm_device *ddev = dev_get_drvdata(dev); 361 struct radeon_device *rdev = ddev->dev_private; 362 int cp = rdev->pm.profile; 363 364 return snprintf(buf, PAGE_SIZE, "%s\n", 365 (cp == PM_PROFILE_AUTO) ? "auto" : 366 (cp == PM_PROFILE_LOW) ? "low" : 367 (cp == PM_PROFILE_MID) ? "mid" : 368 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 369 } 370 371 static ssize_t radeon_set_pm_profile(struct device *dev, 372 struct device_attribute *attr, 373 const char *buf, 374 size_t count) 375 { 376 struct drm_device *ddev = dev_get_drvdata(dev); 377 struct radeon_device *rdev = ddev->dev_private; 378 379 /* Can't set profile when the card is off */ 380 #ifdef notyet 381 if ((rdev->flags & RADEON_IS_PX) && 382 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 383 return -EINVAL; 384 #endif 385 386 mutex_lock(&rdev->pm.mutex); 387 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 388 if (strncmp("default", buf, strlen("default")) == 0) 389 rdev->pm.profile = PM_PROFILE_DEFAULT; 390 else if (strncmp("auto", buf, strlen("auto")) == 0) 391 rdev->pm.profile = PM_PROFILE_AUTO; 392 else if (strncmp("low", buf, strlen("low")) == 0) 393 rdev->pm.profile = PM_PROFILE_LOW; 394 else if (strncmp("mid", buf, strlen("mid")) == 0) 395 rdev->pm.profile = PM_PROFILE_MID; 396 else if (strncmp("high", buf, strlen("high")) == 0) 397 rdev->pm.profile = PM_PROFILE_HIGH; 398 else { 399 count = -EINVAL; 400 goto fail; 401 } 402 radeon_pm_update_profile(rdev); 403 radeon_pm_set_clocks(rdev); 404 } else 405 count = -EINVAL; 406 407 fail: 408 mutex_unlock(&rdev->pm.mutex); 409 410 return count; 411 } 412 413 static ssize_t radeon_get_pm_method(struct device *dev, 414 struct device_attribute *attr, 415 char *buf) 416 { 417 struct drm_device *ddev = dev_get_drvdata(dev); 418 struct radeon_device *rdev = ddev->dev_private; 419 int pm = rdev->pm.pm_method; 420 421 return snprintf(buf, PAGE_SIZE, "%s\n", 422 (pm == PM_METHOD_DYNPM) ? "dynpm" : 423 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 424 } 425 426 static ssize_t radeon_set_pm_method(struct device *dev, 427 struct device_attribute *attr, 428 const char *buf, 429 size_t count) 430 { 431 struct drm_device *ddev = dev_get_drvdata(dev); 432 struct radeon_device *rdev = ddev->dev_private; 433 434 #ifdef notyet 435 /* Can't set method when the card is off */ 436 if ((rdev->flags & RADEON_IS_PX) && 437 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 438 count = -EINVAL; 439 goto fail; 440 } 441 #endif 442 443 /* we don't support the legacy modes with dpm */ 444 if (rdev->pm.pm_method == PM_METHOD_DPM) { 445 count = -EINVAL; 446 goto fail; 447 } 448 449 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 450 mutex_lock(&rdev->pm.mutex); 451 rdev->pm.pm_method = PM_METHOD_DYNPM; 452 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 453 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 454 mutex_unlock(&rdev->pm.mutex); 455 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 456 mutex_lock(&rdev->pm.mutex); 457 /* disable dynpm */ 458 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 459 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 460 rdev->pm.pm_method = PM_METHOD_PROFILE; 461 mutex_unlock(&rdev->pm.mutex); 462 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 463 } else { 464 count = -EINVAL; 465 goto fail; 466 } 467 radeon_pm_compute_clocks(rdev); 468 fail: 469 return count; 470 } 471 472 static ssize_t radeon_get_dpm_state(struct device *dev, 473 struct device_attribute *attr, 474 char *buf) 475 { 476 struct drm_device *ddev = dev_get_drvdata(dev); 477 struct radeon_device *rdev = ddev->dev_private; 478 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 479 480 return snprintf(buf, PAGE_SIZE, "%s\n", 481 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 482 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 483 } 484 485 static ssize_t radeon_set_dpm_state(struct device *dev, 486 struct device_attribute *attr, 487 const char *buf, 488 size_t count) 489 { 490 struct drm_device *ddev = dev_get_drvdata(dev); 491 struct radeon_device *rdev = ddev->dev_private; 492 493 mutex_lock(&rdev->pm.mutex); 494 if (strncmp("battery", buf, strlen("battery")) == 0) 495 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 496 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 497 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 498 else if (strncmp("performance", buf, strlen("performance")) == 0) 499 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 500 else { 501 mutex_unlock(&rdev->pm.mutex); 502 count = -EINVAL; 503 goto fail; 504 } 505 mutex_unlock(&rdev->pm.mutex); 506 507 /* Can't set dpm state when the card is off */ 508 #ifdef notyet 509 if (!(rdev->flags & RADEON_IS_PX) || 510 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 511 #endif 512 radeon_pm_compute_clocks(rdev); 513 514 fail: 515 return count; 516 } 517 518 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 519 struct device_attribute *attr, 520 char *buf) 521 { 522 struct drm_device *ddev = dev_get_drvdata(dev); 523 struct radeon_device *rdev = ddev->dev_private; 524 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 525 526 #ifdef notyet 527 if ((rdev->flags & RADEON_IS_PX) && 528 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 529 return snprintf(buf, PAGE_SIZE, "off\n"); 530 #endif 531 532 return snprintf(buf, PAGE_SIZE, "%s\n", 533 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 534 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 535 } 536 537 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 538 struct device_attribute *attr, 539 const char *buf, 540 size_t count) 541 { 542 struct drm_device *ddev = dev_get_drvdata(dev); 543 struct radeon_device *rdev = ddev->dev_private; 544 enum radeon_dpm_forced_level level; 545 int ret = 0; 546 547 /* Can't force performance level when the card is off */ 548 #ifdef notyet 549 if ((rdev->flags & RADEON_IS_PX) && 550 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 551 return -EINVAL; 552 #endif 553 554 mutex_lock(&rdev->pm.mutex); 555 if (strncmp("low", buf, strlen("low")) == 0) { 556 level = RADEON_DPM_FORCED_LEVEL_LOW; 557 } else if (strncmp("high", buf, strlen("high")) == 0) { 558 level = RADEON_DPM_FORCED_LEVEL_HIGH; 559 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 560 level = RADEON_DPM_FORCED_LEVEL_AUTO; 561 } else { 562 count = -EINVAL; 563 goto fail; 564 } 565 if (rdev->asic->dpm.force_performance_level) { 566 if (rdev->pm.dpm.thermal_active) { 567 count = -EINVAL; 568 goto fail; 569 } 570 ret = radeon_dpm_force_performance_level(rdev, level); 571 if (ret) 572 count = -EINVAL; 573 } 574 fail: 575 mutex_unlock(&rdev->pm.mutex); 576 577 return count; 578 } 579 #endif 580 581 #ifdef notyet 582 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 583 struct device_attribute *attr, 584 char *buf) 585 { 586 struct radeon_device *rdev = dev_get_drvdata(dev); 587 u32 pwm_mode = 0; 588 589 if (rdev->asic->dpm.fan_ctrl_get_mode) 590 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 591 592 /* never 0 (full-speed), fuse or smc-controlled always */ 593 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 594 } 595 596 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 597 struct device_attribute *attr, 598 const char *buf, 599 size_t count) 600 { 601 struct radeon_device *rdev = dev_get_drvdata(dev); 602 int err; 603 int value; 604 605 if(!rdev->asic->dpm.fan_ctrl_set_mode) 606 return -EINVAL; 607 608 err = kstrtoint(buf, 10, &value); 609 if (err) 610 return err; 611 612 switch (value) { 613 case 1: /* manual, percent-based */ 614 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 615 break; 616 default: /* disable */ 617 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 618 break; 619 } 620 621 return count; 622 } 623 624 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 625 struct device_attribute *attr, 626 char *buf) 627 { 628 return sprintf(buf, "%i\n", 0); 629 } 630 631 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 632 struct device_attribute *attr, 633 char *buf) 634 { 635 return sprintf(buf, "%i\n", 255); 636 } 637 638 static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 639 struct device_attribute *attr, 640 const char *buf, size_t count) 641 { 642 struct radeon_device *rdev = dev_get_drvdata(dev); 643 int err; 644 u32 value; 645 646 err = kstrtou32(buf, 10, &value); 647 if (err) 648 return err; 649 650 value = (value * 100) / 255; 651 652 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 653 if (err) 654 return err; 655 656 return count; 657 } 658 659 static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 660 struct device_attribute *attr, 661 char *buf) 662 { 663 struct radeon_device *rdev = dev_get_drvdata(dev); 664 int err; 665 u32 speed; 666 667 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 668 if (err) 669 return err; 670 671 speed = (speed * 255) / 100; 672 673 return sprintf(buf, "%i\n", speed); 674 } 675 676 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 677 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 678 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 679 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 680 radeon_get_dpm_forced_performance_level, 681 radeon_set_dpm_forced_performance_level); 682 683 static ssize_t radeon_hwmon_show_temp(struct device *dev, 684 struct device_attribute *attr, 685 char *buf) 686 { 687 struct radeon_device *rdev = dev_get_drvdata(dev); 688 struct drm_device *ddev = rdev->ddev; 689 int temp; 690 691 /* Can't get temperature when the card is off */ 692 if ((rdev->flags & RADEON_IS_PX) && 693 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 694 return -EINVAL; 695 696 if (rdev->asic->pm.get_temperature) 697 temp = radeon_get_temperature(rdev); 698 else 699 temp = 0; 700 701 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 702 } 703 704 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 705 struct device_attribute *attr, 706 char *buf) 707 { 708 struct radeon_device *rdev = dev_get_drvdata(dev); 709 int hyst = to_sensor_dev_attr(attr)->index; 710 int temp; 711 712 if (hyst) 713 temp = rdev->pm.dpm.thermal.min_temp; 714 else 715 temp = rdev->pm.dpm.thermal.max_temp; 716 717 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 718 } 719 720 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 721 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 722 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 723 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 724 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 725 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 726 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 727 728 729 static struct attribute *hwmon_attributes[] = { 730 &sensor_dev_attr_temp1_input.dev_attr.attr, 731 &sensor_dev_attr_temp1_crit.dev_attr.attr, 732 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 733 &sensor_dev_attr_pwm1.dev_attr.attr, 734 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 735 &sensor_dev_attr_pwm1_min.dev_attr.attr, 736 &sensor_dev_attr_pwm1_max.dev_attr.attr, 737 NULL 738 }; 739 740 static umode_t hwmon_attributes_visible(struct kobject *kobj, 741 struct attribute *attr, int index) 742 { 743 struct device *dev = kobj_to_dev(kobj); 744 struct radeon_device *rdev = dev_get_drvdata(dev); 745 umode_t effective_mode = attr->mode; 746 747 /* Skip attributes if DPM is not enabled */ 748 if (rdev->pm.pm_method != PM_METHOD_DPM && 749 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 750 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 751 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 752 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 753 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 754 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 755 return 0; 756 757 /* Skip fan attributes if fan is not present */ 758 if (rdev->pm.no_fan && 759 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 760 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 761 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 762 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 763 return 0; 764 765 /* mask fan attributes if we have no bindings for this asic to expose */ 766 if ((!rdev->asic->dpm.get_fan_speed_percent && 767 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 768 (!rdev->asic->dpm.fan_ctrl_get_mode && 769 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 770 effective_mode &= ~S_IRUGO; 771 772 if ((!rdev->asic->dpm.set_fan_speed_percent && 773 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 774 (!rdev->asic->dpm.fan_ctrl_set_mode && 775 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 776 effective_mode &= ~S_IWUSR; 777 778 /* hide max/min values if we can't both query and manage the fan */ 779 if ((!rdev->asic->dpm.set_fan_speed_percent && 780 !rdev->asic->dpm.get_fan_speed_percent) && 781 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 782 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 783 return 0; 784 785 return effective_mode; 786 } 787 788 static const struct attribute_group hwmon_attrgroup = { 789 .attrs = hwmon_attributes, 790 .is_visible = hwmon_attributes_visible, 791 }; 792 793 static const struct attribute_group *hwmon_groups[] = { 794 &hwmon_attrgroup, 795 NULL 796 }; 797 #endif 798 799 static int radeon_hwmon_init(struct radeon_device *rdev) 800 { 801 int err = 0; 802 803 switch (rdev->pm.int_thermal_type) { 804 case THERMAL_TYPE_RV6XX: 805 case THERMAL_TYPE_RV770: 806 case THERMAL_TYPE_EVERGREEN: 807 case THERMAL_TYPE_NI: 808 case THERMAL_TYPE_SUMO: 809 case THERMAL_TYPE_SI: 810 case THERMAL_TYPE_CI: 811 case THERMAL_TYPE_KV: 812 if (rdev->asic->pm.get_temperature == NULL) 813 return err; 814 #ifdef notyet 815 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 816 "radeon", rdev, 817 hwmon_groups); 818 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 819 err = PTR_ERR(rdev->pm.int_hwmon_dev); 820 dev_err(rdev->dev, 821 "Unable to register hwmon device: %d\n", err); 822 } 823 #endif 824 break; 825 default: 826 break; 827 } 828 829 return err; 830 } 831 832 static void radeon_hwmon_fini(struct radeon_device *rdev) 833 { 834 #ifdef notyet 835 if (rdev->pm.int_hwmon_dev) 836 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 837 #endif 838 } 839 840 static void radeon_dpm_thermal_work_handler(struct work_struct *work) 841 { 842 struct radeon_device *rdev = 843 container_of(work, struct radeon_device, 844 pm.dpm.thermal.work); 845 /* switch to the thermal state */ 846 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 847 848 if (!rdev->pm.dpm_enabled) 849 return; 850 851 if (rdev->asic->pm.get_temperature) { 852 int temp = radeon_get_temperature(rdev); 853 854 if (temp < rdev->pm.dpm.thermal.min_temp) 855 /* switch back the user state */ 856 dpm_state = rdev->pm.dpm.user_state; 857 } else { 858 if (rdev->pm.dpm.thermal.high_to_low) 859 /* switch back the user state */ 860 dpm_state = rdev->pm.dpm.user_state; 861 } 862 mutex_lock(&rdev->pm.mutex); 863 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 864 rdev->pm.dpm.thermal_active = true; 865 else 866 rdev->pm.dpm.thermal_active = false; 867 rdev->pm.dpm.state = dpm_state; 868 mutex_unlock(&rdev->pm.mutex); 869 870 radeon_pm_compute_clocks(rdev); 871 } 872 873 static bool radeon_dpm_single_display(struct radeon_device *rdev) 874 { 875 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 876 true : false; 877 878 /* check if the vblank period is too short to adjust the mclk */ 879 if (single_display && rdev->asic->dpm.vblank_too_short) { 880 if (radeon_dpm_vblank_too_short(rdev)) 881 single_display = false; 882 } 883 884 /* 120hz tends to be problematic even if they are under the 885 * vblank limit. 886 */ 887 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 888 single_display = false; 889 890 return single_display; 891 } 892 893 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 894 enum radeon_pm_state_type dpm_state) 895 { 896 int i; 897 struct radeon_ps *ps; 898 u32 ui_class; 899 bool single_display = radeon_dpm_single_display(rdev); 900 901 /* certain older asics have a separare 3D performance state, 902 * so try that first if the user selected performance 903 */ 904 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 905 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 906 /* balanced states don't exist at the moment */ 907 if (dpm_state == POWER_STATE_TYPE_BALANCED) 908 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 909 910 restart_search: 911 /* Pick the best power state based on current conditions */ 912 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 913 ps = &rdev->pm.dpm.ps[i]; 914 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 915 switch (dpm_state) { 916 /* user states */ 917 case POWER_STATE_TYPE_BATTERY: 918 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 919 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 920 if (single_display) 921 return ps; 922 } else 923 return ps; 924 } 925 break; 926 case POWER_STATE_TYPE_BALANCED: 927 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 928 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 929 if (single_display) 930 return ps; 931 } else 932 return ps; 933 } 934 break; 935 case POWER_STATE_TYPE_PERFORMANCE: 936 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 937 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 938 if (single_display) 939 return ps; 940 } else 941 return ps; 942 } 943 break; 944 /* internal states */ 945 case POWER_STATE_TYPE_INTERNAL_UVD: 946 if (rdev->pm.dpm.uvd_ps) 947 return rdev->pm.dpm.uvd_ps; 948 else 949 break; 950 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 951 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 952 return ps; 953 break; 954 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 955 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 956 return ps; 957 break; 958 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 959 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 960 return ps; 961 break; 962 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 963 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 964 return ps; 965 break; 966 case POWER_STATE_TYPE_INTERNAL_BOOT: 967 return rdev->pm.dpm.boot_ps; 968 case POWER_STATE_TYPE_INTERNAL_THERMAL: 969 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 970 return ps; 971 break; 972 case POWER_STATE_TYPE_INTERNAL_ACPI: 973 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 974 return ps; 975 break; 976 case POWER_STATE_TYPE_INTERNAL_ULV: 977 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 978 return ps; 979 break; 980 case POWER_STATE_TYPE_INTERNAL_3DPERF: 981 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 982 return ps; 983 break; 984 default: 985 break; 986 } 987 } 988 /* use a fallback state if we didn't match */ 989 switch (dpm_state) { 990 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 991 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 992 goto restart_search; 993 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 994 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 995 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 996 if (rdev->pm.dpm.uvd_ps) { 997 return rdev->pm.dpm.uvd_ps; 998 } else { 999 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1000 goto restart_search; 1001 } 1002 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1003 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 1004 goto restart_search; 1005 case POWER_STATE_TYPE_INTERNAL_ACPI: 1006 dpm_state = POWER_STATE_TYPE_BATTERY; 1007 goto restart_search; 1008 case POWER_STATE_TYPE_BATTERY: 1009 case POWER_STATE_TYPE_BALANCED: 1010 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1011 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1012 goto restart_search; 1013 default: 1014 break; 1015 } 1016 1017 return NULL; 1018 } 1019 1020 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 1021 { 1022 int i; 1023 struct radeon_ps *ps; 1024 enum radeon_pm_state_type dpm_state; 1025 int ret; 1026 bool single_display = radeon_dpm_single_display(rdev); 1027 1028 /* if dpm init failed */ 1029 if (!rdev->pm.dpm_enabled) 1030 return; 1031 1032 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1033 /* add other state override checks here */ 1034 if ((!rdev->pm.dpm.thermal_active) && 1035 (!rdev->pm.dpm.uvd_active)) 1036 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1037 } 1038 dpm_state = rdev->pm.dpm.state; 1039 1040 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1041 if (ps) 1042 rdev->pm.dpm.requested_ps = ps; 1043 else 1044 return; 1045 1046 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1047 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1048 /* vce just modifies an existing state so force a change */ 1049 if (ps->vce_active != rdev->pm.dpm.vce_active) 1050 goto force; 1051 /* user has made a display change (such as timing) */ 1052 if (rdev->pm.dpm.single_display != single_display) 1053 goto force; 1054 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1055 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1056 * all we need to do is update the display configuration. 1057 */ 1058 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1059 /* update display watermarks based on new power state */ 1060 radeon_bandwidth_update(rdev); 1061 /* update displays */ 1062 radeon_dpm_display_configuration_changed(rdev); 1063 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1064 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1065 } 1066 return; 1067 } else { 1068 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1069 * nothing to do, if the num crtcs is > 1 and state is the same, 1070 * update display configuration. 1071 */ 1072 if (rdev->pm.dpm.new_active_crtcs == 1073 rdev->pm.dpm.current_active_crtcs) { 1074 return; 1075 } else { 1076 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1077 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1078 /* update display watermarks based on new power state */ 1079 radeon_bandwidth_update(rdev); 1080 /* update displays */ 1081 radeon_dpm_display_configuration_changed(rdev); 1082 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1083 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1084 return; 1085 } 1086 } 1087 } 1088 } 1089 1090 force: 1091 if (radeon_dpm == 1) { 1092 printk("switching from power state:\n"); 1093 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1094 printk("switching to power state:\n"); 1095 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1096 } 1097 1098 down_write(&rdev->pm.mclk_lock); 1099 mutex_lock(&rdev->ring_lock); 1100 1101 /* update whether vce is active */ 1102 ps->vce_active = rdev->pm.dpm.vce_active; 1103 1104 ret = radeon_dpm_pre_set_power_state(rdev); 1105 if (ret) 1106 goto done; 1107 1108 /* update display watermarks based on new power state */ 1109 radeon_bandwidth_update(rdev); 1110 /* update displays */ 1111 radeon_dpm_display_configuration_changed(rdev); 1112 1113 /* wait for the rings to drain */ 1114 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1115 struct radeon_ring *ring = &rdev->ring[i]; 1116 if (ring->ready) 1117 radeon_fence_wait_empty(rdev, i); 1118 } 1119 1120 /* program the new power state */ 1121 radeon_dpm_set_power_state(rdev); 1122 1123 /* update current power state */ 1124 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1125 1126 radeon_dpm_post_set_power_state(rdev); 1127 1128 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1129 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1130 rdev->pm.dpm.single_display = single_display; 1131 1132 if (rdev->asic->dpm.force_performance_level) { 1133 if (rdev->pm.dpm.thermal_active) { 1134 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1135 /* force low perf level for thermal */ 1136 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1137 /* save the user's level */ 1138 rdev->pm.dpm.forced_level = level; 1139 } else { 1140 /* otherwise, user selected level */ 1141 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1142 } 1143 } 1144 1145 done: 1146 mutex_unlock(&rdev->ring_lock); 1147 up_write(&rdev->pm.mclk_lock); 1148 } 1149 1150 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1151 { 1152 enum radeon_pm_state_type dpm_state; 1153 1154 if (rdev->asic->dpm.powergate_uvd) { 1155 mutex_lock(&rdev->pm.mutex); 1156 /* don't powergate anything if we 1157 have active but pause streams */ 1158 enable |= rdev->pm.dpm.sd > 0; 1159 enable |= rdev->pm.dpm.hd > 0; 1160 /* enable/disable UVD */ 1161 radeon_dpm_powergate_uvd(rdev, !enable); 1162 mutex_unlock(&rdev->pm.mutex); 1163 } else { 1164 if (enable) { 1165 mutex_lock(&rdev->pm.mutex); 1166 rdev->pm.dpm.uvd_active = true; 1167 /* disable this for now */ 1168 #if 0 1169 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1170 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1171 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1172 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1173 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1174 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1175 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1176 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1177 else 1178 #endif 1179 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1180 rdev->pm.dpm.state = dpm_state; 1181 mutex_unlock(&rdev->pm.mutex); 1182 } else { 1183 mutex_lock(&rdev->pm.mutex); 1184 rdev->pm.dpm.uvd_active = false; 1185 mutex_unlock(&rdev->pm.mutex); 1186 } 1187 1188 radeon_pm_compute_clocks(rdev); 1189 } 1190 } 1191 1192 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1193 { 1194 if (enable) { 1195 mutex_lock(&rdev->pm.mutex); 1196 rdev->pm.dpm.vce_active = true; 1197 /* XXX select vce level based on ring/task */ 1198 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1199 mutex_unlock(&rdev->pm.mutex); 1200 } else { 1201 mutex_lock(&rdev->pm.mutex); 1202 rdev->pm.dpm.vce_active = false; 1203 mutex_unlock(&rdev->pm.mutex); 1204 } 1205 1206 radeon_pm_compute_clocks(rdev); 1207 } 1208 1209 static void radeon_pm_suspend_old(struct radeon_device *rdev) 1210 { 1211 mutex_lock(&rdev->pm.mutex); 1212 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1213 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1214 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1215 } 1216 mutex_unlock(&rdev->pm.mutex); 1217 1218 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1219 } 1220 1221 static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1222 { 1223 mutex_lock(&rdev->pm.mutex); 1224 /* disable dpm */ 1225 radeon_dpm_disable(rdev); 1226 /* reset the power state */ 1227 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1228 rdev->pm.dpm_enabled = false; 1229 mutex_unlock(&rdev->pm.mutex); 1230 } 1231 1232 void radeon_pm_suspend(struct radeon_device *rdev) 1233 { 1234 if (rdev->pm.pm_method == PM_METHOD_DPM) 1235 radeon_pm_suspend_dpm(rdev); 1236 else 1237 radeon_pm_suspend_old(rdev); 1238 } 1239 1240 static void radeon_pm_resume_old(struct radeon_device *rdev) 1241 { 1242 /* set up the default clocks if the MC ucode is loaded */ 1243 if ((rdev->family >= CHIP_BARTS) && 1244 (rdev->family <= CHIP_CAYMAN) && 1245 rdev->mc_fw) { 1246 if (rdev->pm.default_vddc) 1247 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1248 SET_VOLTAGE_TYPE_ASIC_VDDC); 1249 if (rdev->pm.default_vddci) 1250 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1251 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1252 if (rdev->pm.default_sclk) 1253 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1254 if (rdev->pm.default_mclk) 1255 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1256 } 1257 /* asic init will reset the default power state */ 1258 mutex_lock(&rdev->pm.mutex); 1259 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1260 rdev->pm.current_clock_mode_index = 0; 1261 rdev->pm.current_sclk = rdev->pm.default_sclk; 1262 rdev->pm.current_mclk = rdev->pm.default_mclk; 1263 if (rdev->pm.power_state) { 1264 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1265 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1266 } 1267 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1268 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1269 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1270 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1271 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1272 } 1273 mutex_unlock(&rdev->pm.mutex); 1274 radeon_pm_compute_clocks(rdev); 1275 } 1276 1277 static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1278 { 1279 int ret; 1280 1281 /* asic init will reset to the boot state */ 1282 mutex_lock(&rdev->pm.mutex); 1283 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1284 radeon_dpm_setup_asic(rdev); 1285 ret = radeon_dpm_enable(rdev); 1286 mutex_unlock(&rdev->pm.mutex); 1287 if (ret) 1288 goto dpm_resume_fail; 1289 rdev->pm.dpm_enabled = true; 1290 return; 1291 1292 dpm_resume_fail: 1293 DRM_ERROR("radeon: dpm resume failed\n"); 1294 if ((rdev->family >= CHIP_BARTS) && 1295 (rdev->family <= CHIP_CAYMAN) && 1296 rdev->mc_fw) { 1297 if (rdev->pm.default_vddc) 1298 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1299 SET_VOLTAGE_TYPE_ASIC_VDDC); 1300 if (rdev->pm.default_vddci) 1301 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1302 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1303 if (rdev->pm.default_sclk) 1304 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1305 if (rdev->pm.default_mclk) 1306 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1307 } 1308 } 1309 1310 void radeon_pm_resume(struct radeon_device *rdev) 1311 { 1312 if (rdev->pm.pm_method == PM_METHOD_DPM) 1313 radeon_pm_resume_dpm(rdev); 1314 else 1315 radeon_pm_resume_old(rdev); 1316 } 1317 1318 static int radeon_pm_init_old(struct radeon_device *rdev) 1319 { 1320 int ret; 1321 1322 rdev->pm.profile = PM_PROFILE_DEFAULT; 1323 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1324 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1325 rdev->pm.dynpm_can_upclock = true; 1326 rdev->pm.dynpm_can_downclock = true; 1327 rdev->pm.default_sclk = rdev->clock.default_sclk; 1328 rdev->pm.default_mclk = rdev->clock.default_mclk; 1329 rdev->pm.current_sclk = rdev->clock.default_sclk; 1330 rdev->pm.current_mclk = rdev->clock.default_mclk; 1331 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1332 1333 if (rdev->bios) { 1334 if (rdev->is_atom_bios) 1335 radeon_atombios_get_power_modes(rdev); 1336 else 1337 radeon_combios_get_power_modes(rdev); 1338 radeon_pm_print_states(rdev); 1339 radeon_pm_init_profile(rdev); 1340 /* set up the default clocks if the MC ucode is loaded */ 1341 if ((rdev->family >= CHIP_BARTS) && 1342 (rdev->family <= CHIP_CAYMAN) && 1343 rdev->mc_fw) { 1344 if (rdev->pm.default_vddc) 1345 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1346 SET_VOLTAGE_TYPE_ASIC_VDDC); 1347 if (rdev->pm.default_vddci) 1348 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1349 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1350 if (rdev->pm.default_sclk) 1351 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1352 if (rdev->pm.default_mclk) 1353 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1354 } 1355 } 1356 1357 /* set up the internal thermal sensor if applicable */ 1358 ret = radeon_hwmon_init(rdev); 1359 if (ret) 1360 return ret; 1361 1362 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1363 1364 if (rdev->pm.num_power_states > 1) { 1365 if (radeon_debugfs_pm_init(rdev)) { 1366 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1367 } 1368 1369 DRM_INFO("radeon: power management initialized\n"); 1370 } 1371 1372 return 0; 1373 } 1374 1375 static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1376 { 1377 int i; 1378 1379 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1380 printk("== power state %d ==\n", i); 1381 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1382 } 1383 } 1384 1385 static int radeon_pm_init_dpm(struct radeon_device *rdev) 1386 { 1387 int ret; 1388 1389 /* default to balanced state */ 1390 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1391 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1392 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1393 rdev->pm.default_sclk = rdev->clock.default_sclk; 1394 rdev->pm.default_mclk = rdev->clock.default_mclk; 1395 rdev->pm.current_sclk = rdev->clock.default_sclk; 1396 rdev->pm.current_mclk = rdev->clock.default_mclk; 1397 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1398 1399 if (rdev->bios && rdev->is_atom_bios) 1400 radeon_atombios_get_power_modes(rdev); 1401 else 1402 return -EINVAL; 1403 1404 /* set up the internal thermal sensor if applicable */ 1405 ret = radeon_hwmon_init(rdev); 1406 if (ret) 1407 return ret; 1408 1409 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1410 mutex_lock(&rdev->pm.mutex); 1411 radeon_dpm_init(rdev); 1412 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1413 if (radeon_dpm == 1) 1414 radeon_dpm_print_power_states(rdev); 1415 radeon_dpm_setup_asic(rdev); 1416 ret = radeon_dpm_enable(rdev); 1417 mutex_unlock(&rdev->pm.mutex); 1418 if (ret) 1419 goto dpm_failed; 1420 rdev->pm.dpm_enabled = true; 1421 1422 if (radeon_debugfs_pm_init(rdev)) { 1423 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1424 } 1425 1426 DRM_INFO("radeon: dpm initialized\n"); 1427 1428 return 0; 1429 1430 dpm_failed: 1431 rdev->pm.dpm_enabled = false; 1432 if ((rdev->family >= CHIP_BARTS) && 1433 (rdev->family <= CHIP_CAYMAN) && 1434 rdev->mc_fw) { 1435 if (rdev->pm.default_vddc) 1436 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1437 SET_VOLTAGE_TYPE_ASIC_VDDC); 1438 if (rdev->pm.default_vddci) 1439 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1440 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1441 if (rdev->pm.default_sclk) 1442 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1443 if (rdev->pm.default_mclk) 1444 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1445 } 1446 DRM_ERROR("radeon: dpm initialization failed\n"); 1447 return ret; 1448 } 1449 1450 struct radeon_dpm_quirk { 1451 u32 chip_vendor; 1452 u32 chip_device; 1453 u32 subsys_vendor; 1454 u32 subsys_device; 1455 }; 1456 1457 /* cards with dpm stability problems */ 1458 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1459 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1460 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1461 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1462 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1463 { 0, 0, 0, 0 }, 1464 }; 1465 1466 int radeon_pm_init(struct radeon_device *rdev) 1467 { 1468 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1469 bool disable_dpm = false; 1470 1471 /* Apply dpm quirks */ 1472 while (p && p->chip_device != 0) { 1473 if (rdev->pdev->vendor == p->chip_vendor && 1474 rdev->pdev->device == p->chip_device && 1475 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1476 rdev->pdev->subsystem_device == p->subsys_device) { 1477 disable_dpm = true; 1478 break; 1479 } 1480 ++p; 1481 } 1482 1483 /* enable dpm on rv6xx+ */ 1484 switch (rdev->family) { 1485 case CHIP_RV610: 1486 case CHIP_RV630: 1487 case CHIP_RV620: 1488 case CHIP_RV635: 1489 case CHIP_RV670: 1490 case CHIP_RS780: 1491 case CHIP_RS880: 1492 case CHIP_RV770: 1493 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1494 if (!rdev->rlc_fw) 1495 rdev->pm.pm_method = PM_METHOD_PROFILE; 1496 else if ((rdev->family >= CHIP_RV770) && 1497 (!(rdev->flags & RADEON_IS_IGP)) && 1498 (!rdev->smc_fw)) 1499 rdev->pm.pm_method = PM_METHOD_PROFILE; 1500 else if (radeon_dpm == 1) 1501 rdev->pm.pm_method = PM_METHOD_DPM; 1502 else 1503 rdev->pm.pm_method = PM_METHOD_PROFILE; 1504 break; 1505 case CHIP_RV730: 1506 case CHIP_RV710: 1507 case CHIP_RV740: 1508 case CHIP_CEDAR: 1509 case CHIP_REDWOOD: 1510 case CHIP_JUNIPER: 1511 case CHIP_CYPRESS: 1512 case CHIP_HEMLOCK: 1513 case CHIP_PALM: 1514 case CHIP_SUMO: 1515 case CHIP_SUMO2: 1516 case CHIP_BARTS: 1517 case CHIP_TURKS: 1518 case CHIP_CAICOS: 1519 case CHIP_CAYMAN: 1520 case CHIP_ARUBA: 1521 case CHIP_TAHITI: 1522 case CHIP_PITCAIRN: 1523 case CHIP_VERDE: 1524 case CHIP_OLAND: 1525 case CHIP_HAINAN: 1526 case CHIP_BONAIRE: 1527 case CHIP_KABINI: 1528 case CHIP_KAVERI: 1529 case CHIP_HAWAII: 1530 case CHIP_MULLINS: 1531 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1532 if (!rdev->rlc_fw) 1533 rdev->pm.pm_method = PM_METHOD_PROFILE; 1534 else if ((rdev->family >= CHIP_RV770) && 1535 (!(rdev->flags & RADEON_IS_IGP)) && 1536 (!rdev->smc_fw)) 1537 rdev->pm.pm_method = PM_METHOD_PROFILE; 1538 else if (disable_dpm && (radeon_dpm == -1)) 1539 rdev->pm.pm_method = PM_METHOD_PROFILE; 1540 else if (radeon_dpm == 0) 1541 rdev->pm.pm_method = PM_METHOD_PROFILE; 1542 else 1543 rdev->pm.pm_method = PM_METHOD_DPM; 1544 break; 1545 default: 1546 /* default to profile method */ 1547 rdev->pm.pm_method = PM_METHOD_PROFILE; 1548 break; 1549 } 1550 1551 if (rdev->pm.pm_method == PM_METHOD_DPM) 1552 return radeon_pm_init_dpm(rdev); 1553 else 1554 return radeon_pm_init_old(rdev); 1555 } 1556 1557 int radeon_pm_late_init(struct radeon_device *rdev) 1558 { 1559 int ret = 0; 1560 1561 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1562 if (rdev->pm.dpm_enabled) { 1563 #ifdef __linux__ 1564 if (!rdev->pm.sysfs_initialized) { 1565 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1566 if (ret) 1567 DRM_ERROR("failed to create device file for dpm state\n"); 1568 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1569 if (ret) 1570 DRM_ERROR("failed to create device file for dpm state\n"); 1571 /* XXX: these are noops for dpm but are here for backwards compat */ 1572 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1573 if (ret) 1574 DRM_ERROR("failed to create device file for power profile\n"); 1575 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1576 if (ret) 1577 DRM_ERROR("failed to create device file for power method\n"); 1578 rdev->pm.sysfs_initialized = true; 1579 } 1580 #endif 1581 1582 mutex_lock(&rdev->pm.mutex); 1583 ret = radeon_dpm_late_enable(rdev); 1584 mutex_unlock(&rdev->pm.mutex); 1585 if (ret) { 1586 rdev->pm.dpm_enabled = false; 1587 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1588 } else { 1589 /* set the dpm state for PX since there won't be 1590 * a modeset to call this. 1591 */ 1592 radeon_pm_compute_clocks(rdev); 1593 } 1594 } 1595 } else { 1596 #ifdef __linux__ 1597 if ((rdev->pm.num_power_states > 1) && 1598 (!rdev->pm.sysfs_initialized)) { 1599 /* where's the best place to put these? */ 1600 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1601 if (ret) 1602 DRM_ERROR("failed to create device file for power profile\n"); 1603 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1604 if (ret) 1605 DRM_ERROR("failed to create device file for power method\n"); 1606 if (!ret) 1607 rdev->pm.sysfs_initialized = true; 1608 } 1609 #endif 1610 } 1611 return ret; 1612 } 1613 1614 static void radeon_pm_fini_old(struct radeon_device *rdev) 1615 { 1616 if (rdev->pm.num_power_states > 1) { 1617 mutex_lock(&rdev->pm.mutex); 1618 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1619 rdev->pm.profile = PM_PROFILE_DEFAULT; 1620 radeon_pm_update_profile(rdev); 1621 radeon_pm_set_clocks(rdev); 1622 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1623 /* reset default clocks */ 1624 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1625 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1626 radeon_pm_set_clocks(rdev); 1627 } 1628 mutex_unlock(&rdev->pm.mutex); 1629 1630 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1631 1632 device_remove_file(rdev->dev, &dev_attr_power_profile); 1633 device_remove_file(rdev->dev, &dev_attr_power_method); 1634 } 1635 1636 radeon_hwmon_fini(rdev); 1637 kfree(rdev->pm.power_state); 1638 } 1639 1640 static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1641 { 1642 if (rdev->pm.num_power_states > 1) { 1643 mutex_lock(&rdev->pm.mutex); 1644 radeon_dpm_disable(rdev); 1645 mutex_unlock(&rdev->pm.mutex); 1646 1647 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1648 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1649 /* XXX backwards compat */ 1650 device_remove_file(rdev->dev, &dev_attr_power_profile); 1651 device_remove_file(rdev->dev, &dev_attr_power_method); 1652 } 1653 radeon_dpm_fini(rdev); 1654 1655 radeon_hwmon_fini(rdev); 1656 kfree(rdev->pm.power_state); 1657 } 1658 1659 void radeon_pm_fini(struct radeon_device *rdev) 1660 { 1661 if (rdev->pm.pm_method == PM_METHOD_DPM) 1662 radeon_pm_fini_dpm(rdev); 1663 else 1664 radeon_pm_fini_old(rdev); 1665 } 1666 1667 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1668 { 1669 struct drm_device *ddev = rdev->ddev; 1670 struct drm_crtc *crtc; 1671 struct radeon_crtc *radeon_crtc; 1672 1673 if (rdev->pm.num_power_states < 2) 1674 return; 1675 1676 mutex_lock(&rdev->pm.mutex); 1677 1678 rdev->pm.active_crtcs = 0; 1679 rdev->pm.active_crtc_count = 0; 1680 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1681 list_for_each_entry(crtc, 1682 &ddev->mode_config.crtc_list, head) { 1683 radeon_crtc = to_radeon_crtc(crtc); 1684 if (radeon_crtc->enabled) { 1685 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1686 rdev->pm.active_crtc_count++; 1687 } 1688 } 1689 } 1690 1691 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1692 radeon_pm_update_profile(rdev); 1693 radeon_pm_set_clocks(rdev); 1694 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1695 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1696 if (rdev->pm.active_crtc_count > 1) { 1697 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1698 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1699 1700 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1701 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1702 radeon_pm_get_dynpm_state(rdev); 1703 radeon_pm_set_clocks(rdev); 1704 1705 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1706 } 1707 } else if (rdev->pm.active_crtc_count == 1) { 1708 /* TODO: Increase clocks if needed for current mode */ 1709 1710 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1711 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1712 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1713 radeon_pm_get_dynpm_state(rdev); 1714 radeon_pm_set_clocks(rdev); 1715 1716 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1717 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1718 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1719 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1720 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1721 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1722 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1723 } 1724 } else { /* count == 0 */ 1725 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1726 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1727 1728 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1729 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1730 radeon_pm_get_dynpm_state(rdev); 1731 radeon_pm_set_clocks(rdev); 1732 } 1733 } 1734 } 1735 } 1736 1737 mutex_unlock(&rdev->pm.mutex); 1738 } 1739 1740 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1741 { 1742 struct drm_device *ddev = rdev->ddev; 1743 struct drm_crtc *crtc; 1744 struct radeon_crtc *radeon_crtc; 1745 1746 if (!rdev->pm.dpm_enabled) 1747 return; 1748 1749 mutex_lock(&rdev->pm.mutex); 1750 1751 /* update active crtc counts */ 1752 rdev->pm.dpm.new_active_crtcs = 0; 1753 rdev->pm.dpm.new_active_crtc_count = 0; 1754 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1755 list_for_each_entry(crtc, 1756 &ddev->mode_config.crtc_list, head) { 1757 radeon_crtc = to_radeon_crtc(crtc); 1758 if (crtc->enabled) { 1759 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1760 rdev->pm.dpm.new_active_crtc_count++; 1761 } 1762 } 1763 } 1764 1765 /* update battery/ac status */ 1766 if (power_supply_is_system_supplied() > 0) 1767 rdev->pm.dpm.ac_power = true; 1768 else 1769 rdev->pm.dpm.ac_power = false; 1770 1771 radeon_dpm_change_power_state_locked(rdev); 1772 1773 mutex_unlock(&rdev->pm.mutex); 1774 1775 } 1776 1777 void radeon_pm_compute_clocks(struct radeon_device *rdev) 1778 { 1779 if (rdev->pm.pm_method == PM_METHOD_DPM) 1780 radeon_pm_compute_clocks_dpm(rdev); 1781 else 1782 radeon_pm_compute_clocks_old(rdev); 1783 } 1784 1785 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1786 { 1787 int crtc, vpos, hpos, vbl_status; 1788 bool in_vbl = true; 1789 1790 /* Iterate over all active crtc's. All crtc's must be in vblank, 1791 * otherwise return in_vbl == false. 1792 */ 1793 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1794 if (rdev->pm.active_crtcs & (1 << crtc)) { 1795 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1796 crtc, 1797 USE_REAL_VBLANKSTART, 1798 &vpos, &hpos, NULL, NULL, 1799 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1800 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1801 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1802 in_vbl = false; 1803 } 1804 } 1805 1806 return in_vbl; 1807 } 1808 1809 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1810 { 1811 u32 stat_crtc = 0; 1812 bool in_vbl = radeon_pm_in_vbl(rdev); 1813 1814 if (!in_vbl) 1815 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1816 finish ? "exit" : "entry"); 1817 return in_vbl; 1818 } 1819 1820 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1821 { 1822 struct radeon_device *rdev; 1823 int resched; 1824 rdev = container_of(work, struct radeon_device, 1825 pm.dynpm_idle_work.work); 1826 1827 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1828 mutex_lock(&rdev->pm.mutex); 1829 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1830 int not_processed = 0; 1831 int i; 1832 1833 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1834 struct radeon_ring *ring = &rdev->ring[i]; 1835 1836 if (ring->ready) { 1837 not_processed += radeon_fence_count_emitted(rdev, i); 1838 if (not_processed >= 3) 1839 break; 1840 } 1841 } 1842 1843 if (not_processed >= 3) { /* should upclock */ 1844 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1845 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1846 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1847 rdev->pm.dynpm_can_upclock) { 1848 rdev->pm.dynpm_planned_action = 1849 DYNPM_ACTION_UPCLOCK; 1850 rdev->pm.dynpm_action_timeout = jiffies + 1851 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1852 } 1853 } else if (not_processed == 0) { /* should downclock */ 1854 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1855 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1856 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1857 rdev->pm.dynpm_can_downclock) { 1858 rdev->pm.dynpm_planned_action = 1859 DYNPM_ACTION_DOWNCLOCK; 1860 rdev->pm.dynpm_action_timeout = jiffies + 1861 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1862 } 1863 } 1864 1865 /* Note, radeon_pm_set_clocks is called with static_switch set 1866 * to false since we want to wait for vbl to avoid flicker. 1867 */ 1868 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1869 jiffies > rdev->pm.dynpm_action_timeout) { 1870 radeon_pm_get_dynpm_state(rdev); 1871 radeon_pm_set_clocks(rdev); 1872 } 1873 1874 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1875 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1876 } 1877 mutex_unlock(&rdev->pm.mutex); 1878 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1879 } 1880 1881 /* 1882 * Debugfs info 1883 */ 1884 #if defined(CONFIG_DEBUG_FS) 1885 1886 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1887 { 1888 struct drm_info_node *node = (struct drm_info_node *) m->private; 1889 struct drm_device *dev = node->minor->dev; 1890 struct radeon_device *rdev = dev->dev_private; 1891 struct drm_device *ddev = rdev->ddev; 1892 1893 if ((rdev->flags & RADEON_IS_PX) && 1894 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1895 seq_printf(m, "PX asic powered off\n"); 1896 } else if (rdev->pm.dpm_enabled) { 1897 mutex_lock(&rdev->pm.mutex); 1898 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1899 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1900 else 1901 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1902 mutex_unlock(&rdev->pm.mutex); 1903 } else { 1904 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1905 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1906 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1907 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1908 else 1909 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1910 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1911 if (rdev->asic->pm.get_memory_clock) 1912 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1913 if (rdev->pm.current_vddc) 1914 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1915 if (rdev->asic->pm.get_pcie_lanes) 1916 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1917 } 1918 1919 return 0; 1920 } 1921 1922 static struct drm_info_list radeon_pm_info_list[] = { 1923 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1924 }; 1925 #endif 1926 1927 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 1928 { 1929 #if defined(CONFIG_DEBUG_FS) 1930 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 1931 #else 1932 return 0; 1933 #endif 1934 } 1935