1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/pagemap.h> 35 #include <linux/pci.h> 36 #include <linux/seq_file.h> 37 #include <linux/slab.h> 38 #include <linux/swap.h> 39 #include <linux/swiotlb.h> 40 41 #include <drm/drm_agpsupport.h> 42 #include <drm/drm_debugfs.h> 43 #include <drm/drm_device.h> 44 #include <drm/drm_file.h> 45 #include <drm/drm_prime.h> 46 #include <drm/radeon_drm.h> 47 #include <drm/ttm/ttm_bo_api.h> 48 #include <drm/ttm/ttm_bo_driver.h> 49 #include <drm/ttm/ttm_module.h> 50 #include <drm/ttm/ttm_page_alloc.h> 51 #include <drm/ttm/ttm_placement.h> 52 53 #include "radeon_reg.h" 54 #include "radeon.h" 55 56 #ifdef __amd64__ 57 #include "efifb.h" 58 #endif 59 60 #if NEFIFB > 0 61 #include <machine/efifbvar.h> 62 #endif 63 64 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 65 66 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 67 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 68 69 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 70 { 71 struct radeon_mman *mman; 72 struct radeon_device *rdev; 73 74 mman = container_of(bdev, struct radeon_mman, bdev); 75 rdev = container_of(mman, struct radeon_device, mman); 76 return rdev; 77 } 78 79 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 80 struct ttm_mem_type_manager *man) 81 { 82 struct radeon_device *rdev; 83 84 rdev = radeon_get_rdev(bdev); 85 86 switch (type) { 87 case TTM_PL_SYSTEM: 88 /* System memory */ 89 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 90 man->available_caching = TTM_PL_MASK_CACHING; 91 man->default_caching = TTM_PL_FLAG_CACHED; 92 break; 93 case TTM_PL_TT: 94 man->func = &ttm_bo_manager_func; 95 man->gpu_offset = rdev->mc.gtt_start; 96 man->available_caching = TTM_PL_MASK_CACHING; 97 man->default_caching = TTM_PL_FLAG_CACHED; 98 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 99 #if IS_ENABLED(CONFIG_AGP) 100 if (rdev->flags & RADEON_IS_AGP) { 101 if (!rdev->ddev->agp) { 102 DRM_ERROR("AGP is not enabled for memory type %u\n", 103 (unsigned)type); 104 return -EINVAL; 105 } 106 if (!rdev->ddev->agp->cant_use_aperture) 107 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 108 man->available_caching = TTM_PL_FLAG_UNCACHED | 109 TTM_PL_FLAG_WC; 110 man->default_caching = TTM_PL_FLAG_WC; 111 } 112 #endif 113 break; 114 case TTM_PL_VRAM: 115 /* "On-card" video ram */ 116 man->func = &ttm_bo_manager_func; 117 man->gpu_offset = rdev->mc.vram_start; 118 man->flags = TTM_MEMTYPE_FLAG_FIXED | 119 TTM_MEMTYPE_FLAG_MAPPABLE; 120 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 121 man->default_caching = TTM_PL_FLAG_WC; 122 break; 123 default: 124 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 125 return -EINVAL; 126 } 127 return 0; 128 } 129 130 static void radeon_evict_flags(struct ttm_buffer_object *bo, 131 struct ttm_placement *placement) 132 { 133 static const struct ttm_place placements = { 134 .fpfn = 0, 135 .lpfn = 0, 136 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM 137 }; 138 139 struct radeon_bo *rbo; 140 141 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 142 placement->placement = &placements; 143 placement->busy_placement = &placements; 144 placement->num_placement = 1; 145 placement->num_busy_placement = 1; 146 return; 147 } 148 rbo = container_of(bo, struct radeon_bo, tbo); 149 switch (bo->mem.mem_type) { 150 case TTM_PL_VRAM: 151 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) 152 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 153 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && 154 bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { 155 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 156 int i; 157 158 /* Try evicting to the CPU inaccessible part of VRAM 159 * first, but only set GTT as busy placement, so this 160 * BO will be evicted to GTT rather than causing other 161 * BOs to be evicted from VRAM 162 */ 163 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | 164 RADEON_GEM_DOMAIN_GTT); 165 rbo->placement.num_busy_placement = 0; 166 for (i = 0; i < rbo->placement.num_placement; i++) { 167 if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { 168 if (rbo->placements[i].fpfn < fpfn) 169 rbo->placements[i].fpfn = fpfn; 170 } else { 171 rbo->placement.busy_placement = 172 &rbo->placements[i]; 173 rbo->placement.num_busy_placement = 1; 174 } 175 } 176 } else 177 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 178 break; 179 case TTM_PL_TT: 180 default: 181 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 182 } 183 *placement = rbo->placement; 184 } 185 186 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) 187 { 188 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 189 struct drm_file *file_priv = (void *)filp; 190 191 if (radeon_ttm_tt_has_userptr(bo->ttm)) 192 return -EPERM; 193 return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, file_priv); 194 } 195 196 static void radeon_move_null(struct ttm_buffer_object *bo, 197 struct ttm_mem_reg *new_mem) 198 { 199 struct ttm_mem_reg *old_mem = &bo->mem; 200 201 BUG_ON(old_mem->mm_node != NULL); 202 *old_mem = *new_mem; 203 new_mem->mm_node = NULL; 204 } 205 206 static int radeon_move_blit(struct ttm_buffer_object *bo, 207 bool evict, bool no_wait_gpu, 208 struct ttm_mem_reg *new_mem, 209 struct ttm_mem_reg *old_mem) 210 { 211 struct radeon_device *rdev; 212 uint64_t old_start, new_start; 213 struct radeon_fence *fence; 214 unsigned num_pages; 215 int r, ridx; 216 217 rdev = radeon_get_rdev(bo->bdev); 218 ridx = radeon_copy_ring_index(rdev); 219 old_start = (u64)old_mem->start << PAGE_SHIFT; 220 new_start = (u64)new_mem->start << PAGE_SHIFT; 221 222 switch (old_mem->mem_type) { 223 case TTM_PL_VRAM: 224 old_start += rdev->mc.vram_start; 225 break; 226 case TTM_PL_TT: 227 old_start += rdev->mc.gtt_start; 228 break; 229 default: 230 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 231 return -EINVAL; 232 } 233 switch (new_mem->mem_type) { 234 case TTM_PL_VRAM: 235 new_start += rdev->mc.vram_start; 236 break; 237 case TTM_PL_TT: 238 new_start += rdev->mc.gtt_start; 239 break; 240 default: 241 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 242 return -EINVAL; 243 } 244 if (!rdev->ring[ridx].ready) { 245 DRM_ERROR("Trying to move memory with ring turned off.\n"); 246 return -EINVAL; 247 } 248 249 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 250 251 num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); 252 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv); 253 if (IS_ERR(fence)) 254 return PTR_ERR(fence); 255 256 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem); 257 radeon_fence_unref(&fence); 258 return r; 259 } 260 261 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 262 bool evict, bool interruptible, 263 bool no_wait_gpu, 264 struct ttm_mem_reg *new_mem) 265 { 266 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 267 struct ttm_mem_reg *old_mem = &bo->mem; 268 struct ttm_mem_reg tmp_mem; 269 struct ttm_place placements; 270 struct ttm_placement placement; 271 int r; 272 273 tmp_mem = *new_mem; 274 tmp_mem.mm_node = NULL; 275 placement.num_placement = 1; 276 placement.placement = &placements; 277 placement.num_busy_placement = 1; 278 placement.busy_placement = &placements; 279 placements.fpfn = 0; 280 placements.lpfn = 0; 281 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 282 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 283 if (unlikely(r)) { 284 return r; 285 } 286 287 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 288 if (unlikely(r)) { 289 goto out_cleanup; 290 } 291 292 r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx); 293 if (unlikely(r)) { 294 goto out_cleanup; 295 } 296 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 297 if (unlikely(r)) { 298 goto out_cleanup; 299 } 300 r = ttm_bo_move_ttm(bo, &ctx, new_mem); 301 out_cleanup: 302 ttm_bo_mem_put(bo, &tmp_mem); 303 return r; 304 } 305 306 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 307 bool evict, bool interruptible, 308 bool no_wait_gpu, 309 struct ttm_mem_reg *new_mem) 310 { 311 struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu }; 312 struct ttm_mem_reg *old_mem = &bo->mem; 313 struct ttm_mem_reg tmp_mem; 314 struct ttm_placement placement; 315 struct ttm_place placements; 316 int r; 317 318 tmp_mem = *new_mem; 319 tmp_mem.mm_node = NULL; 320 placement.num_placement = 1; 321 placement.placement = &placements; 322 placement.num_busy_placement = 1; 323 placement.busy_placement = &placements; 324 placements.fpfn = 0; 325 placements.lpfn = 0; 326 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 327 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx); 328 if (unlikely(r)) { 329 return r; 330 } 331 r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem); 332 if (unlikely(r)) { 333 goto out_cleanup; 334 } 335 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 336 if (unlikely(r)) { 337 goto out_cleanup; 338 } 339 out_cleanup: 340 ttm_bo_mem_put(bo, &tmp_mem); 341 return r; 342 } 343 344 static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict, 345 struct ttm_operation_ctx *ctx, 346 struct ttm_mem_reg *new_mem) 347 { 348 struct radeon_device *rdev; 349 struct radeon_bo *rbo; 350 struct ttm_mem_reg *old_mem = &bo->mem; 351 int r; 352 353 r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu); 354 if (r) 355 return r; 356 357 /* Can't move a pinned BO */ 358 rbo = container_of(bo, struct radeon_bo, tbo); 359 if (WARN_ON_ONCE(rbo->pin_count > 0)) 360 return -EINVAL; 361 362 rdev = radeon_get_rdev(bo->bdev); 363 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 364 radeon_move_null(bo, new_mem); 365 return 0; 366 } 367 if ((old_mem->mem_type == TTM_PL_TT && 368 new_mem->mem_type == TTM_PL_SYSTEM) || 369 (old_mem->mem_type == TTM_PL_SYSTEM && 370 new_mem->mem_type == TTM_PL_TT)) { 371 /* bind is enough */ 372 radeon_move_null(bo, new_mem); 373 return 0; 374 } 375 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 376 rdev->asic->copy.copy == NULL) { 377 /* use memcpy */ 378 goto memcpy; 379 } 380 381 if (old_mem->mem_type == TTM_PL_VRAM && 382 new_mem->mem_type == TTM_PL_SYSTEM) { 383 r = radeon_move_vram_ram(bo, evict, ctx->interruptible, 384 ctx->no_wait_gpu, new_mem); 385 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 386 new_mem->mem_type == TTM_PL_VRAM) { 387 r = radeon_move_ram_vram(bo, evict, ctx->interruptible, 388 ctx->no_wait_gpu, new_mem); 389 } else { 390 r = radeon_move_blit(bo, evict, ctx->no_wait_gpu, 391 new_mem, old_mem); 392 } 393 394 if (r) { 395 memcpy: 396 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 397 if (r) { 398 return r; 399 } 400 } 401 402 /* update statistics */ 403 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 404 return 0; 405 } 406 407 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 408 { 409 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 410 struct radeon_device *rdev = radeon_get_rdev(bdev); 411 412 mem->bus.addr = NULL; 413 mem->bus.offset = 0; 414 mem->bus.size = mem->num_pages << PAGE_SHIFT; 415 mem->bus.base = 0; 416 mem->bus.is_iomem = false; 417 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 418 return -EINVAL; 419 switch (mem->mem_type) { 420 case TTM_PL_SYSTEM: 421 /* system memory */ 422 return 0; 423 case TTM_PL_TT: 424 #if IS_ENABLED(CONFIG_AGP) 425 if (rdev->flags & RADEON_IS_AGP) { 426 /* RADEON_IS_AGP is set only if AGP is active */ 427 mem->bus.offset = mem->start << PAGE_SHIFT; 428 mem->bus.base = rdev->mc.agp_base; 429 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 430 } 431 #endif 432 break; 433 case TTM_PL_VRAM: 434 mem->bus.offset = mem->start << PAGE_SHIFT; 435 /* check if it's visible */ 436 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 437 return -EINVAL; 438 mem->bus.base = rdev->mc.aper_base; 439 mem->bus.is_iomem = true; 440 #ifdef __alpha__ 441 /* 442 * Alpha: use bus.addr to hold the ioremap() return, 443 * so we can modify bus.base below. 444 */ 445 if (mem->placement & TTM_PL_FLAG_WC) 446 mem->bus.addr = 447 ioremap_wc(mem->bus.base + mem->bus.offset, 448 mem->bus.size); 449 else 450 mem->bus.addr = 451 ioremap(mem->bus.base + mem->bus.offset, 452 mem->bus.size); 453 if (!mem->bus.addr) 454 return -ENOMEM; 455 456 /* 457 * Alpha: Use just the bus offset plus 458 * the hose/domain memory base for bus.base. 459 * It then can be used to build PTEs for VRAM 460 * access, as done in ttm_bo_vm_fault(). 461 */ 462 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 463 rdev->ddev->hose->dense_mem_base; 464 #endif 465 break; 466 default: 467 return -EINVAL; 468 } 469 return 0; 470 } 471 472 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 473 { 474 } 475 476 /* 477 * TTM backend functions. 478 */ 479 struct radeon_ttm_tt { 480 struct ttm_dma_tt ttm; 481 struct radeon_device *rdev; 482 u64 offset; 483 484 uint64_t userptr; 485 struct mm_struct *usermm; 486 uint32_t userflags; 487 }; 488 489 /* prepare the sg table with the user pages */ 490 static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm) 491 { 492 STUB(); 493 return -ENOSYS; 494 #ifdef notyet 495 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 496 struct radeon_ttm_tt *gtt = (void *)ttm; 497 unsigned pinned = 0, nents; 498 int r; 499 500 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 501 enum dma_data_direction direction = write ? 502 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 503 504 if (current->mm != gtt->usermm) 505 return -EPERM; 506 507 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) { 508 /* check that we only pin down anonymous memory 509 to prevent problems with writeback */ 510 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; 511 struct vm_area_struct *vma; 512 vma = find_vma(gtt->usermm, gtt->userptr); 513 if (!vma || vma->vm_file || vma->vm_end < end) 514 return -EPERM; 515 } 516 517 do { 518 unsigned num_pages = ttm->num_pages - pinned; 519 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; 520 struct vm_page **pages = ttm->pages + pinned; 521 522 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0, 523 pages, NULL); 524 if (r < 0) 525 goto release_pages; 526 527 pinned += r; 528 529 } while (pinned < ttm->num_pages); 530 531 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 532 ttm->num_pages << PAGE_SHIFT, 533 GFP_KERNEL); 534 if (r) 535 goto release_sg; 536 537 r = -ENOMEM; 538 nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 539 if (nents == 0) 540 goto release_sg; 541 542 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 543 gtt->ttm.dma_address, ttm->num_pages); 544 545 return 0; 546 547 release_sg: 548 kfree(ttm->sg); 549 550 release_pages: 551 release_pages(ttm->pages, pinned); 552 return r; 553 #endif 554 } 555 556 static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm) 557 { 558 STUB(); 559 #ifdef notyet 560 struct radeon_device *rdev = radeon_get_rdev(ttm->bdev); 561 struct radeon_ttm_tt *gtt = (void *)ttm; 562 struct sg_page_iter sg_iter; 563 564 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 565 enum dma_data_direction direction = write ? 566 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 567 568 /* double check that we don't free the table twice */ 569 if (!ttm->sg->sgl) 570 return; 571 572 /* free the sg table and pages again */ 573 dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction); 574 575 for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) { 576 struct vm_page *page = sg_page_iter_page(&sg_iter); 577 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY)) 578 set_page_dirty(page); 579 580 mark_page_accessed(page); 581 put_page(page); 582 } 583 584 sg_free_table(ttm->sg); 585 #endif 586 } 587 588 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 589 struct ttm_mem_reg *bo_mem) 590 { 591 struct radeon_ttm_tt *gtt = (void*)ttm; 592 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ | 593 RADEON_GART_PAGE_WRITE; 594 int r; 595 596 if (gtt->userptr) { 597 radeon_ttm_tt_pin_userptr(ttm); 598 flags &= ~RADEON_GART_PAGE_WRITE; 599 } 600 601 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 602 if (!ttm->num_pages) { 603 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 604 ttm->num_pages, bo_mem, ttm); 605 } 606 if (ttm->caching_state == tt_cached) 607 flags |= RADEON_GART_PAGE_SNOOP; 608 r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages, 609 ttm->pages, gtt->ttm.dma_address, flags); 610 if (r) { 611 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 612 ttm->num_pages, (unsigned)gtt->offset); 613 return r; 614 } 615 return 0; 616 } 617 618 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 619 { 620 struct radeon_ttm_tt *gtt = (void *)ttm; 621 622 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 623 624 if (gtt->userptr) 625 radeon_ttm_tt_unpin_userptr(ttm); 626 627 return 0; 628 } 629 630 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 631 { 632 struct radeon_ttm_tt *gtt = (void *)ttm; 633 634 ttm_dma_tt_fini(>t->ttm); 635 kfree(gtt); 636 } 637 638 static struct ttm_backend_func radeon_backend_func = { 639 .bind = &radeon_ttm_backend_bind, 640 .unbind = &radeon_ttm_backend_unbind, 641 .destroy = &radeon_ttm_backend_destroy, 642 }; 643 644 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo, 645 uint32_t page_flags) 646 { 647 struct radeon_device *rdev; 648 struct radeon_ttm_tt *gtt; 649 650 rdev = radeon_get_rdev(bo->bdev); 651 #if IS_ENABLED(CONFIG_AGP) 652 if (rdev->flags & RADEON_IS_AGP) { 653 return ttm_agp_tt_create(bo, rdev->ddev->agp, 654 page_flags); 655 } 656 #endif 657 658 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 659 if (gtt == NULL) { 660 return NULL; 661 } 662 gtt->ttm.ttm.func = &radeon_backend_func; 663 gtt->rdev = rdev; 664 if (ttm_dma_tt_init(>t->ttm, bo, page_flags)) { 665 kfree(gtt); 666 return NULL; 667 } 668 return >t->ttm.ttm; 669 } 670 671 static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm) 672 { 673 if (!ttm || ttm->func != &radeon_backend_func) 674 return NULL; 675 return (struct radeon_ttm_tt *)ttm; 676 } 677 678 static int radeon_ttm_tt_populate(struct ttm_tt *ttm, 679 struct ttm_operation_ctx *ctx) 680 { 681 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 682 struct radeon_device *rdev; 683 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 684 685 if (gtt && gtt->userptr) { 686 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 687 if (!ttm->sg) 688 return -ENOMEM; 689 690 ttm->page_flags |= TTM_PAGE_FLAG_SG; 691 ttm->state = tt_unbound; 692 return 0; 693 } 694 695 if (slave && ttm->sg) { 696 #ifdef notyet 697 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 698 gtt->ttm.dma_address, ttm->num_pages); 699 #endif 700 ttm->state = tt_unbound; 701 return 0; 702 } 703 704 rdev = radeon_get_rdev(ttm->bdev); 705 #if IS_ENABLED(CONFIG_AGP) 706 if (rdev->flags & RADEON_IS_AGP) { 707 return ttm_agp_tt_populate(ttm, ctx); 708 } 709 #endif 710 711 #ifdef CONFIG_SWIOTLB 712 if (rdev->need_swiotlb && swiotlb_nr_tbl()) { 713 return ttm_dma_populate(>t->ttm, rdev->dev, ctx); 714 } 715 #endif 716 717 return ttm_populate_and_map_pages(rdev->dev, >t->ttm, ctx); 718 } 719 720 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 721 { 722 struct radeon_device *rdev; 723 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 724 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 725 726 if (gtt && gtt->userptr) { 727 kfree(ttm->sg); 728 ttm->page_flags &= ~TTM_PAGE_FLAG_SG; 729 return; 730 } 731 732 if (slave) 733 return; 734 735 rdev = radeon_get_rdev(ttm->bdev); 736 #if IS_ENABLED(CONFIG_AGP) 737 if (rdev->flags & RADEON_IS_AGP) { 738 ttm_agp_tt_unpopulate(ttm); 739 return; 740 } 741 #endif 742 743 #ifdef CONFIG_SWIOTLB 744 if (rdev->need_swiotlb && swiotlb_nr_tbl()) { 745 ttm_dma_unpopulate(>t->ttm, rdev->dev); 746 return; 747 } 748 #endif 749 750 ttm_unmap_and_unpopulate_pages(rdev->dev, >t->ttm); 751 } 752 753 int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 754 uint32_t flags) 755 { 756 STUB(); 757 return -ENOSYS; 758 #if 0 759 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 760 761 if (gtt == NULL) 762 return -EINVAL; 763 764 gtt->userptr = addr; 765 gtt->usermm = current->mm; 766 gtt->userflags = flags; 767 return 0; 768 #endif 769 } 770 771 bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm) 772 { 773 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 774 775 if (gtt == NULL) 776 return false; 777 778 return !!gtt->userptr; 779 } 780 781 bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm) 782 { 783 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm); 784 785 if (gtt == NULL) 786 return false; 787 788 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY); 789 } 790 791 static struct ttm_bo_driver radeon_bo_driver = { 792 .ttm_tt_create = &radeon_ttm_tt_create, 793 .ttm_tt_populate = &radeon_ttm_tt_populate, 794 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 795 .init_mem_type = &radeon_init_mem_type, 796 .eviction_valuable = ttm_bo_eviction_valuable, 797 .evict_flags = &radeon_evict_flags, 798 .move = &radeon_bo_move, 799 .verify_access = &radeon_verify_access, 800 .move_notify = &radeon_bo_move_notify, 801 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 802 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 803 .io_mem_free = &radeon_ttm_io_mem_free, 804 }; 805 806 int radeon_ttm_init(struct radeon_device *rdev) 807 { 808 int r; 809 unsigned long stolen_size = 0; 810 811 #if NEFIFB > 0 812 stolen_size = efifb_stolen(); 813 #endif 814 if (stolen_size == 0) 815 stolen_size = 256 * 1024; 816 817 /* No others user of address space so set it to 0 */ 818 #ifdef notyet 819 r = ttm_bo_device_init(&rdev->mman.bdev, 820 &radeon_bo_driver, 821 rdev->ddev->anon_inode->i_mapping, 822 rdev->ddev->vma_offset_manager, 823 dma_addressing_limited(&rdev->pdev->dev)); 824 #else 825 r = ttm_bo_device_init(&rdev->mman.bdev, 826 &radeon_bo_driver, 827 /*rdev->ddev->anon_inode->i_mapping*/ NULL, 828 rdev->ddev->vma_offset_manager, 829 dma_addressing_limited(&rdev->pdev->dev)); 830 #endif 831 if (r) { 832 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 833 return r; 834 } 835 rdev->mman.bdev.iot = rdev->iot; 836 rdev->mman.bdev.memt = rdev->memt; 837 rdev->mman.bdev.dmat = rdev->dmat; 838 rdev->mman.initialized = true; 839 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 840 rdev->mc.real_vram_size >> PAGE_SHIFT); 841 if (r) { 842 DRM_ERROR("Failed initializing VRAM heap.\n"); 843 return r; 844 } 845 /* Change the size here instead of the init above so only lpfn is affected */ 846 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 847 848 #ifdef __sparc64__ 849 r = radeon_bo_create(rdev, rdev->fb_offset, PAGE_SIZE, true, 850 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 851 NULL, &rdev->stolen_vga_memory); 852 #else 853 r = radeon_bo_create(rdev, stolen_size, PAGE_SIZE, true, 854 RADEON_GEM_DOMAIN_VRAM, 0, NULL, 855 NULL, &rdev->stolen_vga_memory); 856 #endif 857 if (r) { 858 return r; 859 } 860 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 861 if (r) 862 return r; 863 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 864 radeon_bo_unreserve(rdev->stolen_vga_memory); 865 if (r) { 866 radeon_bo_unref(&rdev->stolen_vga_memory); 867 return r; 868 } 869 DRM_INFO("radeon: %uM of VRAM memory ready\n", 870 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 871 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 872 rdev->mc.gtt_size >> PAGE_SHIFT); 873 if (r) { 874 DRM_ERROR("Failed initializing GTT heap.\n"); 875 return r; 876 } 877 DRM_INFO("radeon: %uM of GTT memory ready.\n", 878 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 879 880 r = radeon_ttm_debugfs_init(rdev); 881 if (r) { 882 DRM_ERROR("Failed to init debugfs\n"); 883 return r; 884 } 885 return 0; 886 } 887 888 void radeon_ttm_fini(struct radeon_device *rdev) 889 { 890 int r; 891 892 if (!rdev->mman.initialized) 893 return; 894 radeon_ttm_debugfs_fini(rdev); 895 if (rdev->stolen_vga_memory) { 896 r = radeon_bo_reserve(rdev->stolen_vga_memory, false); 897 if (r == 0) { 898 radeon_bo_unpin(rdev->stolen_vga_memory); 899 radeon_bo_unreserve(rdev->stolen_vga_memory); 900 } 901 radeon_bo_unref(&rdev->stolen_vga_memory); 902 } 903 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 904 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 905 ttm_bo_device_release(&rdev->mman.bdev); 906 radeon_gart_fini(rdev); 907 rdev->mman.initialized = false; 908 DRM_INFO("radeon: ttm finalized\n"); 909 } 910 911 /* this should only be called at bootup or when userspace 912 * isn't running */ 913 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 914 { 915 struct ttm_mem_type_manager *man; 916 917 if (!rdev->mman.initialized) 918 return; 919 920 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 921 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 922 man->size = size >> PAGE_SHIFT; 923 } 924 925 #ifdef __linux__ 926 927 static vm_fault_t radeon_ttm_fault(struct vm_fault *vmf) 928 { 929 struct ttm_buffer_object *bo; 930 struct radeon_device *rdev; 931 vm_fault_t ret; 932 933 bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data; 934 if (bo == NULL) 935 return VM_FAULT_NOPAGE; 936 937 rdev = radeon_get_rdev(bo->bdev); 938 down_read(&rdev->pm.mclk_lock); 939 ret = ttm_bo_vm_fault(vmf); 940 up_read(&rdev->pm.mclk_lock); 941 return ret; 942 } 943 944 static struct vm_operations_struct radeon_ttm_vm_ops = { 945 .fault = radeon_ttm_fault, 946 .open = ttm_bo_vm_open, 947 .close = ttm_bo_vm_close, 948 .access = ttm_bo_vm_access 949 }; 950 951 int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 952 { 953 int r; 954 struct drm_file *file_priv = filp->private_data; 955 struct radeon_device *rdev = file_priv->minor->dev->dev_private; 956 957 if (rdev == NULL) 958 return -EINVAL; 959 960 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 961 if (unlikely(r != 0)) 962 return r; 963 964 vma->vm_ops = &radeon_ttm_vm_ops; 965 return 0; 966 } 967 #else 968 969 static struct uvm_pagerops radeon_ttm_vm_ops; 970 static const struct uvm_pagerops *ttm_vm_ops = NULL; 971 972 static int 973 radeon_ttm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps, 974 int npages, int centeridx, vm_fault_t fault_type, 975 vm_prot_t access_type, int flags) 976 { 977 struct drm_gem_object *bo; 978 struct radeon_device *rdev; 979 int r; 980 981 bo = (struct drm_gem_object *)ufi->entry->object.uvm_obj; 982 rdev = bo->dev->dev_private; 983 down_read(&rdev->pm.mclk_lock); 984 r = ttm_vm_ops->pgo_fault(ufi, vaddr, pps, npages, centeridx, 985 fault_type, access_type, flags); 986 up_read(&rdev->pm.mclk_lock); 987 return r; 988 } 989 990 struct uvm_object * 991 radeon_mmap(struct file *filp, vm_prot_t accessprot, voff_t off, 992 vsize_t size) 993 { 994 struct drm_file *file_priv = (void *)filp; 995 struct radeon_device *rdev = file_priv->minor->dev->dev_private; 996 struct uvm_object *uobj; 997 998 if (rdev == NULL) 999 return NULL; 1000 1001 if (unlikely(off < DRM_FILE_PAGE_OFFSET)) 1002 return NULL; 1003 1004 uobj = ttm_bo_mmap(filp, off, size, &rdev->mman.bdev); 1005 if (unlikely(uobj == NULL)) { 1006 return NULL; 1007 } 1008 if (unlikely(ttm_vm_ops == NULL)) { 1009 ttm_vm_ops = uobj->pgops; 1010 radeon_ttm_vm_ops = *ttm_vm_ops; 1011 radeon_ttm_vm_ops.pgo_fault = &radeon_ttm_fault; 1012 } 1013 uobj->pgops = &radeon_ttm_vm_ops; 1014 return uobj; 1015 } 1016 #endif 1017 1018 #if defined(CONFIG_DEBUG_FS) 1019 1020 static int radeon_mm_dump_table(struct seq_file *m, void *data) 1021 { 1022 struct drm_info_node *node = (struct drm_info_node *)m->private; 1023 unsigned ttm_pl = *(int*)node->info_ent->data; 1024 struct drm_device *dev = node->minor->dev; 1025 struct radeon_device *rdev = dev->dev_private; 1026 struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl]; 1027 struct drm_printer p = drm_seq_file_printer(m); 1028 1029 man->func->debug(man, &p); 1030 return 0; 1031 } 1032 1033 1034 static int ttm_pl_vram = TTM_PL_VRAM; 1035 static int ttm_pl_tt = TTM_PL_TT; 1036 1037 static struct drm_info_list radeon_ttm_debugfs_list[] = { 1038 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 1039 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 1040 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 1041 #ifdef CONFIG_SWIOTLB 1042 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 1043 #endif 1044 }; 1045 1046 static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 1047 { 1048 struct radeon_device *rdev = inode->i_private; 1049 i_size_write(inode, rdev->mc.mc_vram_size); 1050 filep->private_data = inode->i_private; 1051 return 0; 1052 } 1053 1054 static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 1055 size_t size, loff_t *pos) 1056 { 1057 struct radeon_device *rdev = f->private_data; 1058 ssize_t result = 0; 1059 int r; 1060 1061 if (size & 0x3 || *pos & 0x3) 1062 return -EINVAL; 1063 1064 while (size) { 1065 unsigned long flags; 1066 uint32_t value; 1067 1068 if (*pos >= rdev->mc.mc_vram_size) 1069 return result; 1070 1071 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 1072 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 1073 if (rdev->family >= CHIP_CEDAR) 1074 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 1075 value = RREG32(RADEON_MM_DATA); 1076 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 1077 1078 r = put_user(value, (uint32_t *)buf); 1079 if (r) 1080 return r; 1081 1082 result += 4; 1083 buf += 4; 1084 *pos += 4; 1085 size -= 4; 1086 } 1087 1088 return result; 1089 } 1090 1091 static const struct file_operations radeon_ttm_vram_fops = { 1092 .owner = THIS_MODULE, 1093 .open = radeon_ttm_vram_open, 1094 .read = radeon_ttm_vram_read, 1095 .llseek = default_llseek 1096 }; 1097 1098 static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 1099 { 1100 struct radeon_device *rdev = inode->i_private; 1101 i_size_write(inode, rdev->mc.gtt_size); 1102 filep->private_data = inode->i_private; 1103 return 0; 1104 } 1105 1106 static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 1107 size_t size, loff_t *pos) 1108 { 1109 struct radeon_device *rdev = f->private_data; 1110 ssize_t result = 0; 1111 int r; 1112 1113 while (size) { 1114 loff_t p = *pos / PAGE_SIZE; 1115 unsigned off = *pos & PAGE_MASK; 1116 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1117 struct vm_page *page; 1118 void *ptr; 1119 1120 if (p >= rdev->gart.num_cpu_pages) 1121 return result; 1122 1123 page = rdev->gart.pages[p]; 1124 if (page) { 1125 ptr = kmap(page); 1126 ptr += off; 1127 1128 r = copy_to_user(buf, ptr, cur_size); 1129 kunmap(ptr); 1130 } else 1131 r = clear_user(buf, cur_size); 1132 1133 if (r) 1134 return -EFAULT; 1135 1136 result += cur_size; 1137 buf += cur_size; 1138 *pos += cur_size; 1139 size -= cur_size; 1140 } 1141 1142 return result; 1143 } 1144 1145 static const struct file_operations radeon_ttm_gtt_fops = { 1146 .owner = THIS_MODULE, 1147 .open = radeon_ttm_gtt_open, 1148 .read = radeon_ttm_gtt_read, 1149 .llseek = default_llseek 1150 }; 1151 1152 #endif 1153 1154 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 1155 { 1156 #if defined(CONFIG_DEBUG_FS) 1157 unsigned count; 1158 1159 struct drm_minor *minor = rdev->ddev->primary; 1160 struct dentry *root = minor->debugfs_root; 1161 1162 rdev->mman.vram = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, 1163 root, rdev, 1164 &radeon_ttm_vram_fops); 1165 1166 rdev->mman.gtt = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, 1167 root, rdev, &radeon_ttm_gtt_fops); 1168 1169 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1170 1171 #ifdef CONFIG_SWIOTLB 1172 if (!(rdev->need_swiotlb && swiotlb_nr_tbl())) 1173 --count; 1174 #endif 1175 1176 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1177 #else 1178 1179 return 0; 1180 #endif 1181 } 1182 1183 static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1184 { 1185 #if defined(CONFIG_DEBUG_FS) 1186 1187 debugfs_remove(rdev->mman.vram); 1188 rdev->mman.vram = NULL; 1189 1190 debugfs_remove(rdev->mman.gtt); 1191 rdev->mman.gtt = NULL; 1192 #endif 1193 } 1194