1 /* $OpenBSD: radeon_ttm.c,v 1.12 2015/12/18 03:22:39 mmcc Exp $ */ 2 /* 3 * Copyright 2009 Jerome Glisse. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 * 26 */ 27 /* 28 * Authors: 29 * Jerome Glisse <glisse@freedesktop.org> 30 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 31 * Dave Airlie 32 */ 33 #include <dev/pci/drm/ttm/ttm_bo_api.h> 34 #include <dev/pci/drm/ttm/ttm_bo_driver.h> 35 #include <dev/pci/drm/ttm/ttm_placement.h> 36 #include <dev/pci/drm/ttm/ttm_module.h> 37 #include <dev/pci/drm/ttm/ttm_page_alloc.h> 38 #include <dev/pci/drm/drmP.h> 39 #include <dev/pci/drm/radeon_drm.h> 40 #include "radeon_reg.h" 41 #include "radeon.h" 42 43 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 44 45 static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 46 47 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 48 { 49 struct radeon_mman *mman; 50 struct radeon_device *rdev; 51 52 mman = container_of(bdev, struct radeon_mman, bdev); 53 rdev = container_of(mman, struct radeon_device, mman); 54 return rdev; 55 } 56 57 58 /* 59 * Global memory. 60 */ 61 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) 62 { 63 return ttm_mem_global_init(ref->object); 64 } 65 66 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) 67 { 68 ttm_mem_global_release(ref->object); 69 } 70 71 static int radeon_ttm_global_init(struct radeon_device *rdev) 72 { 73 struct drm_global_reference *global_ref; 74 int r; 75 76 rdev->mman.mem_global_referenced = false; 77 global_ref = &rdev->mman.mem_global_ref; 78 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 79 global_ref->size = sizeof(struct ttm_mem_global); 80 global_ref->init = &radeon_ttm_mem_global_init; 81 global_ref->release = &radeon_ttm_mem_global_release; 82 r = drm_global_item_ref(global_ref); 83 if (r != 0) { 84 DRM_ERROR("Failed setting up TTM memory accounting " 85 "subsystem.\n"); 86 return r; 87 } 88 89 rdev->mman.bo_global_ref.mem_glob = 90 rdev->mman.mem_global_ref.object; 91 global_ref = &rdev->mman.bo_global_ref.ref; 92 global_ref->global_type = DRM_GLOBAL_TTM_BO; 93 global_ref->size = sizeof(struct ttm_bo_global); 94 global_ref->init = &ttm_bo_global_init; 95 global_ref->release = &ttm_bo_global_release; 96 r = drm_global_item_ref(global_ref); 97 if (r != 0) { 98 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 99 drm_global_item_unref(&rdev->mman.mem_global_ref); 100 return r; 101 } 102 103 rdev->mman.mem_global_referenced = true; 104 return 0; 105 } 106 107 static void radeon_ttm_global_fini(struct radeon_device *rdev) 108 { 109 if (rdev->mman.mem_global_referenced) { 110 drm_global_item_unref(&rdev->mman.bo_global_ref.ref); 111 drm_global_item_unref(&rdev->mman.mem_global_ref); 112 rdev->mman.mem_global_referenced = false; 113 } 114 } 115 116 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 117 { 118 return 0; 119 } 120 121 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 122 struct ttm_mem_type_manager *man) 123 { 124 struct radeon_device *rdev; 125 126 rdev = radeon_get_rdev(bdev); 127 128 switch (type) { 129 case TTM_PL_SYSTEM: 130 /* System memory */ 131 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 132 man->available_caching = TTM_PL_MASK_CACHING; 133 man->default_caching = TTM_PL_FLAG_CACHED; 134 break; 135 case TTM_PL_TT: 136 man->func = &ttm_bo_manager_func; 137 man->gpu_offset = rdev->mc.gtt_start; 138 man->available_caching = TTM_PL_MASK_CACHING; 139 man->default_caching = TTM_PL_FLAG_CACHED; 140 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 141 #if __OS_HAS_AGP 142 if (rdev->flags & RADEON_IS_AGP) { 143 #ifdef notyet 144 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) { 145 DRM_ERROR("AGP is not enabled for memory type %u\n", 146 (unsigned)type); 147 return -EINVAL; 148 } 149 #endif 150 if (!rdev->ddev->agp->cant_use_aperture) 151 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 152 man->available_caching = TTM_PL_FLAG_UNCACHED | 153 TTM_PL_FLAG_WC; 154 man->default_caching = TTM_PL_FLAG_WC; 155 } 156 #endif 157 break; 158 case TTM_PL_VRAM: 159 /* "On-card" video ram */ 160 man->func = &ttm_bo_manager_func; 161 man->gpu_offset = rdev->mc.vram_start; 162 man->flags = TTM_MEMTYPE_FLAG_FIXED | 163 TTM_MEMTYPE_FLAG_MAPPABLE; 164 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 165 man->default_caching = TTM_PL_FLAG_WC; 166 break; 167 default: 168 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 169 return -EINVAL; 170 } 171 return 0; 172 } 173 174 static void radeon_evict_flags(struct ttm_buffer_object *bo, 175 struct ttm_placement *placement) 176 { 177 struct radeon_bo *rbo; 178 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 179 180 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 181 placement->fpfn = 0; 182 placement->lpfn = 0; 183 placement->placement = &placements; 184 placement->busy_placement = &placements; 185 placement->num_placement = 1; 186 placement->num_busy_placement = 1; 187 return; 188 } 189 rbo = container_of(bo, struct radeon_bo, tbo); 190 switch (bo->mem.mem_type) { 191 case TTM_PL_VRAM: 192 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) 193 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 194 else 195 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 196 break; 197 case TTM_PL_TT: 198 default: 199 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 200 } 201 *placement = rbo->placement; 202 } 203 204 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) 205 { 206 return 0; 207 } 208 209 static void radeon_move_null(struct ttm_buffer_object *bo, 210 struct ttm_mem_reg *new_mem) 211 { 212 struct ttm_mem_reg *old_mem = &bo->mem; 213 214 BUG_ON(old_mem->mm_node != NULL); 215 *old_mem = *new_mem; 216 new_mem->mm_node = NULL; 217 } 218 219 static int radeon_move_blit(struct ttm_buffer_object *bo, 220 bool evict, bool no_wait_gpu, 221 struct ttm_mem_reg *new_mem, 222 struct ttm_mem_reg *old_mem) 223 { 224 struct radeon_device *rdev; 225 uint64_t old_start, new_start; 226 struct radeon_fence *fence; 227 int r, ridx; 228 229 rdev = radeon_get_rdev(bo->bdev); 230 ridx = radeon_copy_ring_index(rdev); 231 old_start = old_mem->start << PAGE_SHIFT; 232 new_start = new_mem->start << PAGE_SHIFT; 233 234 switch (old_mem->mem_type) { 235 case TTM_PL_VRAM: 236 old_start += rdev->mc.vram_start; 237 break; 238 case TTM_PL_TT: 239 old_start += rdev->mc.gtt_start; 240 break; 241 default: 242 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 243 return -EINVAL; 244 } 245 switch (new_mem->mem_type) { 246 case TTM_PL_VRAM: 247 new_start += rdev->mc.vram_start; 248 break; 249 case TTM_PL_TT: 250 new_start += rdev->mc.gtt_start; 251 break; 252 default: 253 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 254 return -EINVAL; 255 } 256 if (!rdev->ring[ridx].ready) { 257 DRM_ERROR("Trying to move memory with ring turned off.\n"); 258 return -EINVAL; 259 } 260 261 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 262 263 /* sync other rings */ 264 fence = bo->sync_obj; 265 r = radeon_copy(rdev, old_start, new_start, 266 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ 267 &fence); 268 /* FIXME: handle copy error */ 269 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, 270 evict, no_wait_gpu, new_mem); 271 radeon_fence_unref(&fence); 272 return r; 273 } 274 275 static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 276 bool evict, bool interruptible, 277 bool no_wait_gpu, 278 struct ttm_mem_reg *new_mem) 279 { 280 struct radeon_device *rdev; 281 struct ttm_mem_reg *old_mem = &bo->mem; 282 struct ttm_mem_reg tmp_mem; 283 u32 placements; 284 struct ttm_placement placement; 285 int r; 286 287 rdev = radeon_get_rdev(bo->bdev); 288 tmp_mem = *new_mem; 289 tmp_mem.mm_node = NULL; 290 placement.fpfn = 0; 291 placement.lpfn = 0; 292 placement.num_placement = 1; 293 placement.placement = &placements; 294 placement.num_busy_placement = 1; 295 placement.busy_placement = &placements; 296 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 297 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 298 interruptible, no_wait_gpu); 299 if (unlikely(r)) { 300 return r; 301 } 302 303 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 304 if (unlikely(r)) { 305 goto out_cleanup; 306 } 307 308 r = ttm_tt_bind(bo->ttm, &tmp_mem); 309 if (unlikely(r)) { 310 goto out_cleanup; 311 } 312 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 313 if (unlikely(r)) { 314 goto out_cleanup; 315 } 316 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 317 out_cleanup: 318 ttm_bo_mem_put(bo, &tmp_mem); 319 return r; 320 } 321 322 static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 323 bool evict, bool interruptible, 324 bool no_wait_gpu, 325 struct ttm_mem_reg *new_mem) 326 { 327 struct radeon_device *rdev; 328 struct ttm_mem_reg *old_mem = &bo->mem; 329 struct ttm_mem_reg tmp_mem; 330 struct ttm_placement placement; 331 u32 placements; 332 int r; 333 334 rdev = radeon_get_rdev(bo->bdev); 335 tmp_mem = *new_mem; 336 tmp_mem.mm_node = NULL; 337 placement.fpfn = 0; 338 placement.lpfn = 0; 339 placement.num_placement = 1; 340 placement.placement = &placements; 341 placement.num_busy_placement = 1; 342 placement.busy_placement = &placements; 343 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 344 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 345 interruptible, no_wait_gpu); 346 if (unlikely(r)) { 347 return r; 348 } 349 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 350 if (unlikely(r)) { 351 goto out_cleanup; 352 } 353 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 354 if (unlikely(r)) { 355 goto out_cleanup; 356 } 357 out_cleanup: 358 ttm_bo_mem_put(bo, &tmp_mem); 359 return r; 360 } 361 362 static int radeon_bo_move(struct ttm_buffer_object *bo, 363 bool evict, bool interruptible, 364 bool no_wait_gpu, 365 struct ttm_mem_reg *new_mem) 366 { 367 struct radeon_device *rdev; 368 struct ttm_mem_reg *old_mem = &bo->mem; 369 int r; 370 371 rdev = radeon_get_rdev(bo->bdev); 372 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 373 radeon_move_null(bo, new_mem); 374 return 0; 375 } 376 if ((old_mem->mem_type == TTM_PL_TT && 377 new_mem->mem_type == TTM_PL_SYSTEM) || 378 (old_mem->mem_type == TTM_PL_SYSTEM && 379 new_mem->mem_type == TTM_PL_TT)) { 380 /* bind is enough */ 381 radeon_move_null(bo, new_mem); 382 return 0; 383 } 384 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 385 rdev->asic->copy.copy == NULL) { 386 /* use memcpy */ 387 goto memcpy; 388 } 389 390 if (old_mem->mem_type == TTM_PL_VRAM && 391 new_mem->mem_type == TTM_PL_SYSTEM) { 392 r = radeon_move_vram_ram(bo, evict, interruptible, 393 no_wait_gpu, new_mem); 394 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 395 new_mem->mem_type == TTM_PL_VRAM) { 396 r = radeon_move_ram_vram(bo, evict, interruptible, 397 no_wait_gpu, new_mem); 398 } else { 399 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 400 } 401 402 if (r) { 403 memcpy: 404 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 405 } 406 return r; 407 } 408 409 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 410 { 411 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 412 struct radeon_device *rdev = radeon_get_rdev(bdev); 413 414 mem->bus.addr = NULL; 415 mem->bus.offset = 0; 416 mem->bus.size = mem->num_pages << PAGE_SHIFT; 417 mem->bus.base = 0; 418 mem->bus.is_iomem = false; 419 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 420 return -EINVAL; 421 switch (mem->mem_type) { 422 case TTM_PL_SYSTEM: 423 /* system memory */ 424 return 0; 425 case TTM_PL_TT: 426 #if __OS_HAS_AGP 427 if (rdev->flags & RADEON_IS_AGP) { 428 /* RADEON_IS_AGP is set only if AGP is active */ 429 mem->bus.offset = mem->start << PAGE_SHIFT; 430 mem->bus.base = rdev->mc.agp_base; 431 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 432 } 433 #endif 434 break; 435 case TTM_PL_VRAM: 436 mem->bus.offset = mem->start << PAGE_SHIFT; 437 /* check if it's visible */ 438 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 439 return -EINVAL; 440 mem->bus.base = rdev->mc.aper_base; 441 mem->bus.is_iomem = true; 442 #ifdef __alpha__ 443 /* 444 * Alpha: use bus.addr to hold the ioremap() return, 445 * so we can modify bus.base below. 446 */ 447 if (mem->placement & TTM_PL_FLAG_WC) 448 mem->bus.addr = 449 ioremap_wc(mem->bus.base + mem->bus.offset, 450 mem->bus.size); 451 else 452 mem->bus.addr = 453 ioremap_nocache(mem->bus.base + mem->bus.offset, 454 mem->bus.size); 455 456 /* 457 * Alpha: Use just the bus offset plus 458 * the hose/domain memory base for bus.base. 459 * It then can be used to build PTEs for VRAM 460 * access, as done in ttm_bo_vm_fault(). 461 */ 462 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 463 rdev->ddev->hose->dense_mem_base; 464 #endif 465 break; 466 default: 467 return -EINVAL; 468 } 469 return 0; 470 } 471 472 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 473 { 474 } 475 476 static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) 477 { 478 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); 479 } 480 481 static int radeon_sync_obj_flush(void *sync_obj) 482 { 483 return 0; 484 } 485 486 static void radeon_sync_obj_unref(void **sync_obj) 487 { 488 radeon_fence_unref((struct radeon_fence **)sync_obj); 489 } 490 491 static void *radeon_sync_obj_ref(void *sync_obj) 492 { 493 return radeon_fence_ref((struct radeon_fence *)sync_obj); 494 } 495 496 static bool radeon_sync_obj_signaled(void *sync_obj) 497 { 498 return radeon_fence_signaled((struct radeon_fence *)sync_obj); 499 } 500 501 /* 502 * TTM backend functions. 503 */ 504 struct radeon_ttm_tt { 505 struct ttm_dma_tt ttm; 506 struct radeon_device *rdev; 507 bus_dmamap_t map; 508 bus_dma_segment_t *segs; 509 u64 offset; 510 }; 511 512 static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 513 struct ttm_mem_reg *bo_mem) 514 { 515 struct radeon_ttm_tt *gtt = (void*)ttm; 516 int r; 517 518 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 519 if (!ttm->num_pages) { 520 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 521 ttm->num_pages, bo_mem, ttm); 522 } 523 r = radeon_gart_bind(gtt->rdev, gtt->offset, 524 ttm->num_pages, ttm->pages, gtt->ttm.dma_address); 525 if (r) { 526 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 527 ttm->num_pages, (unsigned)gtt->offset); 528 return r; 529 } 530 return 0; 531 } 532 533 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 534 { 535 struct radeon_ttm_tt *gtt = (void *)ttm; 536 537 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 538 return 0; 539 } 540 541 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 542 { 543 struct radeon_ttm_tt *gtt = (void *)ttm; 544 545 bus_dmamap_destroy(gtt->rdev->dmat, gtt->map); 546 free(gtt->segs, M_DRM, 0); 547 ttm_dma_tt_fini(>t->ttm); 548 kfree(gtt); 549 } 550 551 static struct ttm_backend_func radeon_backend_func = { 552 .bind = &radeon_ttm_backend_bind, 553 .unbind = &radeon_ttm_backend_unbind, 554 .destroy = &radeon_ttm_backend_destroy, 555 }; 556 557 static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, 558 unsigned long size, uint32_t page_flags, 559 struct vm_page *dummy_read_page) 560 { 561 struct radeon_device *rdev; 562 struct radeon_ttm_tt *gtt; 563 564 rdev = radeon_get_rdev(bdev); 565 #if __OS_HAS_AGP 566 if (rdev->flags & RADEON_IS_AGP) { 567 return ttm_agp_tt_create(bdev, rdev->ddev->agp, 568 size, page_flags, dummy_read_page); 569 } 570 #endif 571 572 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 573 if (gtt == NULL) { 574 return NULL; 575 } 576 gtt->ttm.ttm.func = &radeon_backend_func; 577 gtt->rdev = rdev; 578 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 579 kfree(gtt); 580 return NULL; 581 } 582 583 gtt->segs = mallocarray(gtt->ttm.ttm.num_pages, 584 sizeof(bus_dma_segment_t), M_DRM, M_WAITOK | M_ZERO); 585 586 if (bus_dmamap_create(rdev->dmat, size, gtt->ttm.ttm.num_pages, size, 587 0, BUS_DMA_WAITOK, >t->map)) { 588 free(gtt->segs, M_DRM, 0); 589 ttm_dma_tt_fini(>t->ttm); 590 free(gtt, M_DRM, 0); 591 return NULL; 592 } 593 594 return >t->ttm.ttm; 595 } 596 597 static int radeon_ttm_tt_populate(struct ttm_tt *ttm) 598 { 599 struct radeon_device *rdev; 600 struct radeon_ttm_tt *gtt = (void *)ttm; 601 unsigned i; 602 int r, seg; 603 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 604 605 if (ttm->state != tt_unpopulated) 606 return 0; 607 608 if (slave && ttm->sg) { 609 #ifdef notyet 610 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 611 gtt->ttm.dma_address, ttm->num_pages); 612 #endif 613 ttm->state = tt_unbound; 614 return 0; 615 } 616 617 rdev = radeon_get_rdev(ttm->bdev); 618 #if __OS_HAS_AGP 619 if (rdev->flags & RADEON_IS_AGP) { 620 return ttm_agp_tt_populate(ttm); 621 } 622 #endif 623 624 #ifdef CONFIG_SWIOTLB 625 if (swiotlb_nr_tbl()) { 626 return ttm_dma_populate(>t->ttm, rdev->dev); 627 } 628 #endif 629 630 r = ttm_pool_populate(ttm); 631 if (r) { 632 return r; 633 } 634 635 for (i = 0; i < ttm->num_pages; i++) { 636 gtt->segs[i].ds_addr = VM_PAGE_TO_PHYS(ttm->pages[i]); 637 gtt->segs[i].ds_len = PAGE_SIZE; 638 } 639 640 if (bus_dmamap_load_raw(rdev->dmat, gtt->map, gtt->segs, 641 ttm->num_pages, 642 ttm->num_pages * PAGE_SIZE, 0)) { 643 ttm_pool_unpopulate(ttm); 644 return -EFAULT; 645 } 646 647 for (seg = 0, i = 0; seg < gtt->map->dm_nsegs; seg++) { 648 bus_addr_t addr = gtt->map->dm_segs[seg].ds_addr; 649 bus_size_t len = gtt->map->dm_segs[seg].ds_len; 650 651 while (len > 0) { 652 gtt->ttm.dma_address[i++] = addr; 653 addr += PAGE_SIZE; 654 len -= PAGE_SIZE; 655 } 656 } 657 658 return 0; 659 } 660 661 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 662 { 663 struct radeon_device *rdev; 664 struct radeon_ttm_tt *gtt = (void *)ttm; 665 unsigned i; 666 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 667 668 if (slave) 669 return; 670 671 rdev = radeon_get_rdev(ttm->bdev); 672 #if __OS_HAS_AGP 673 if (rdev->flags & RADEON_IS_AGP) { 674 ttm_agp_tt_unpopulate(ttm); 675 return; 676 } 677 #endif 678 679 #ifdef CONFIG_SWIOTLB 680 if (swiotlb_nr_tbl()) { 681 ttm_dma_unpopulate(>t->ttm, rdev->dev); 682 return; 683 } 684 #endif 685 686 bus_dmamap_unload(rdev->dmat, gtt->map); 687 for (i = 0; i < ttm->num_pages; i++) 688 gtt->ttm.dma_address[i] = 0; 689 690 ttm_pool_unpopulate(ttm); 691 } 692 693 static struct ttm_bo_driver radeon_bo_driver = { 694 .ttm_tt_create = &radeon_ttm_tt_create, 695 .ttm_tt_populate = &radeon_ttm_tt_populate, 696 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 697 .invalidate_caches = &radeon_invalidate_caches, 698 .init_mem_type = &radeon_init_mem_type, 699 .evict_flags = &radeon_evict_flags, 700 .move = &radeon_bo_move, 701 .verify_access = &radeon_verify_access, 702 .sync_obj_signaled = &radeon_sync_obj_signaled, 703 .sync_obj_wait = &radeon_sync_obj_wait, 704 .sync_obj_flush = &radeon_sync_obj_flush, 705 .sync_obj_unref = &radeon_sync_obj_unref, 706 .sync_obj_ref = &radeon_sync_obj_ref, 707 .move_notify = &radeon_bo_move_notify, 708 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 709 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 710 .io_mem_free = &radeon_ttm_io_mem_free, 711 }; 712 713 int radeon_ttm_init(struct radeon_device *rdev) 714 { 715 int r; 716 717 r = radeon_ttm_global_init(rdev); 718 if (r) { 719 return r; 720 } 721 /* No others user of address space so set it to 0 */ 722 r = ttm_bo_device_init(&rdev->mman.bdev, 723 rdev->mman.bo_global_ref.ref.object, 724 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET, 725 rdev->need_dma32); 726 if (r) { 727 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 728 return r; 729 } 730 rdev->mman.bdev.iot = rdev->iot; 731 rdev->mman.bdev.memt = rdev->memt; 732 rdev->mman.bdev.dmat = rdev->dmat; 733 rdev->mman.initialized = true; 734 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 735 rdev->mc.real_vram_size >> PAGE_SHIFT); 736 if (r) { 737 DRM_ERROR("Failed initializing VRAM heap.\n"); 738 return r; 739 } 740 /* Change the size here instead of the init above so only lpfn is affected */ 741 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 742 743 #ifdef __sparc64__ 744 r = radeon_bo_create(rdev, rdev->fb_offset, PAGE_SIZE, true, 745 RADEON_GEM_DOMAIN_VRAM, 746 NULL, &rdev->stollen_vga_memory); 747 #else 748 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 749 RADEON_GEM_DOMAIN_VRAM, 750 NULL, &rdev->stollen_vga_memory); 751 #endif 752 if (r) { 753 return r; 754 } 755 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 756 if (r) 757 return r; 758 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 759 radeon_bo_unreserve(rdev->stollen_vga_memory); 760 if (r) { 761 radeon_bo_unref(&rdev->stollen_vga_memory); 762 return r; 763 } 764 DRM_INFO("radeon: %uM of VRAM memory ready\n", 765 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 766 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 767 rdev->mc.gtt_size >> PAGE_SHIFT); 768 if (r) { 769 DRM_ERROR("Failed initializing GTT heap.\n"); 770 return r; 771 } 772 DRM_INFO("radeon: %uM of GTT memory ready.\n", 773 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 774 #ifdef notyet 775 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping; 776 #endif 777 778 r = radeon_ttm_debugfs_init(rdev); 779 if (r) { 780 DRM_ERROR("Failed to init debugfs\n"); 781 return r; 782 } 783 return 0; 784 } 785 786 void radeon_ttm_fini(struct radeon_device *rdev) 787 { 788 int r; 789 790 if (!rdev->mman.initialized) 791 return; 792 if (rdev->stollen_vga_memory) { 793 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 794 if (r == 0) { 795 radeon_bo_unpin(rdev->stollen_vga_memory); 796 radeon_bo_unreserve(rdev->stollen_vga_memory); 797 } 798 radeon_bo_unref(&rdev->stollen_vga_memory); 799 } 800 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 801 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 802 ttm_bo_device_release(&rdev->mman.bdev); 803 radeon_gart_fini(rdev); 804 radeon_ttm_global_fini(rdev); 805 rdev->mman.initialized = false; 806 DRM_INFO("radeon: ttm finalized\n"); 807 } 808 809 /* this should only be called at bootup or when userspace 810 * isn't running */ 811 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 812 { 813 struct ttm_mem_type_manager *man; 814 815 if (!rdev->mman.initialized) 816 return; 817 818 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 819 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 820 man->size = size >> PAGE_SHIFT; 821 } 822 823 static struct uvm_pagerops radeon_ttm_vm_ops; 824 static const struct uvm_pagerops *ttm_vm_ops = NULL; 825 826 static int 827 radeon_ttm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps, 828 int npages, int centeridx, vm_fault_t fault_type, 829 vm_prot_t access_type, int flags) 830 { 831 struct ttm_buffer_object *bo; 832 struct radeon_device *rdev; 833 int r; 834 835 bo = (struct ttm_buffer_object *)ufi->entry->object.uvm_obj; 836 rdev = radeon_get_rdev(bo->bdev); 837 down_read(&rdev->pm.mclk_lock); 838 r = ttm_vm_ops->pgo_fault(ufi, vaddr, pps, npages, centeridx, 839 fault_type, access_type, flags); 840 up_read(&rdev->pm.mclk_lock); 841 return r; 842 } 843 844 struct uvm_object * 845 radeon_mmap(struct drm_device *dev, voff_t off, vsize_t size) 846 { 847 struct radeon_device *rdev = dev->dev_private; 848 struct uvm_object *uobj; 849 850 if (unlikely(off < DRM_FILE_PAGE_OFFSET)) 851 return NULL; 852 853 #if 0 854 file_priv = filp->private_data; 855 rdev = file_priv->minor->dev->dev_private; 856 if (rdev == NULL) { 857 return -EINVAL; 858 } 859 #endif 860 uobj = ttm_bo_mmap(off, size, &rdev->mman.bdev); 861 if (unlikely(uobj == NULL)) { 862 return NULL; 863 } 864 if (unlikely(ttm_vm_ops == NULL)) { 865 ttm_vm_ops = uobj->pgops; 866 radeon_ttm_vm_ops = *ttm_vm_ops; 867 radeon_ttm_vm_ops.pgo_fault = &radeon_ttm_fault; 868 } 869 uobj->pgops = &radeon_ttm_vm_ops; 870 return uobj; 871 } 872 873 874 #define RADEON_DEBUGFS_MEM_TYPES 2 875 876 #if defined(CONFIG_DEBUG_FS) 877 static int radeon_mm_dump_table(struct seq_file *m, void *data) 878 { 879 struct drm_info_node *node = (struct drm_info_node *)m->private; 880 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data; 881 struct drm_device *dev = node->minor->dev; 882 struct radeon_device *rdev = dev->dev_private; 883 int ret; 884 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 885 886 spin_lock(&glob->lru_lock); 887 ret = drm_mm_dump_table(m, mm); 888 spin_unlock(&glob->lru_lock); 889 return ret; 890 } 891 #endif 892 893 static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 894 { 895 #if defined(CONFIG_DEBUG_FS) 896 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2]; 897 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32]; 898 unsigned i; 899 900 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { 901 if (i == 0) 902 sprintf(radeon_mem_types_names[i], "radeon_vram_mm"); 903 else 904 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm"); 905 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 906 radeon_mem_types_list[i].show = &radeon_mm_dump_table; 907 radeon_mem_types_list[i].driver_features = 0; 908 if (i == 0) 909 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv; 910 else 911 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv; 912 913 } 914 /* Add ttm page pool to debugfs */ 915 sprintf(radeon_mem_types_names[i], "ttm_page_pool"); 916 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 917 radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; 918 radeon_mem_types_list[i].driver_features = 0; 919 radeon_mem_types_list[i++].data = NULL; 920 #ifdef CONFIG_SWIOTLB 921 if (swiotlb_nr_tbl()) { 922 sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool"); 923 radeon_mem_types_list[i].name = radeon_mem_types_names[i]; 924 radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs; 925 radeon_mem_types_list[i].driver_features = 0; 926 radeon_mem_types_list[i++].data = NULL; 927 } 928 #endif 929 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i); 930 931 #endif 932 return 0; 933 } 934