1 /* $OpenBSD: rs400.c,v 1.7 2015/04/06 03:49:47 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "rs400d.h" 33 34 /* This files gather functions specifics to : rs400,rs480 */ 35 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 36 37 void rs400_gart_adjust_size(struct radeon_device *rdev) 38 { 39 /* Check gart size */ 40 switch (rdev->mc.gtt_size/(1024*1024)) { 41 case 32: 42 case 64: 43 case 128: 44 case 256: 45 case 512: 46 case 1024: 47 case 2048: 48 break; 49 default: 50 DRM_ERROR("Unable to use IGP GART size %uM\n", 51 (unsigned)(rdev->mc.gtt_size >> 20)); 52 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 53 DRM_ERROR("Forcing to 32M GART size\n"); 54 rdev->mc.gtt_size = 32 * 1024 * 1024; 55 return; 56 } 57 } 58 59 void rs400_gart_tlb_flush(struct radeon_device *rdev) 60 { 61 uint32_t tmp; 62 unsigned int timeout = rdev->usec_timeout; 63 64 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 65 do { 66 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 67 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 68 break; 69 DRM_UDELAY(1); 70 timeout--; 71 } while (timeout > 0); 72 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 73 } 74 75 int rs400_gart_init(struct radeon_device *rdev) 76 { 77 int r; 78 79 if (rdev->gart.ptr) { 80 WARN(1, "RS400 GART already initialized\n"); 81 return 0; 82 } 83 /* Check gart size */ 84 switch(rdev->mc.gtt_size / (1024 * 1024)) { 85 case 32: 86 case 64: 87 case 128: 88 case 256: 89 case 512: 90 case 1024: 91 case 2048: 92 break; 93 default: 94 return -EINVAL; 95 } 96 /* Initialize common gart structure */ 97 r = radeon_gart_init(rdev); 98 if (r) 99 return r; 100 if (rs400_debugfs_pcie_gart_info_init(rdev)) 101 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 102 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 103 return radeon_gart_table_ram_alloc(rdev); 104 } 105 106 int rs400_gart_enable(struct radeon_device *rdev) 107 { 108 uint32_t size_reg; 109 uint32_t tmp; 110 111 radeon_gart_restore(rdev); 112 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 113 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 114 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 115 /* Check gart size */ 116 switch(rdev->mc.gtt_size / (1024 * 1024)) { 117 case 32: 118 size_reg = RS480_VA_SIZE_32MB; 119 break; 120 case 64: 121 size_reg = RS480_VA_SIZE_64MB; 122 break; 123 case 128: 124 size_reg = RS480_VA_SIZE_128MB; 125 break; 126 case 256: 127 size_reg = RS480_VA_SIZE_256MB; 128 break; 129 case 512: 130 size_reg = RS480_VA_SIZE_512MB; 131 break; 132 case 1024: 133 size_reg = RS480_VA_SIZE_1GB; 134 break; 135 case 2048: 136 size_reg = RS480_VA_SIZE_2GB; 137 break; 138 default: 139 return -EINVAL; 140 } 141 /* It should be fine to program it to max value */ 142 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 143 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 144 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 145 } else { 146 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 147 WREG32(RS480_AGP_BASE_2, 0); 148 } 149 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 150 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 151 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 152 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 153 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 154 WREG32(RADEON_BUS_CNTL, tmp); 155 } else { 156 WREG32(RADEON_MC_AGP_LOCATION, tmp); 157 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 158 WREG32(RADEON_BUS_CNTL, tmp); 159 } 160 /* Table should be in 32bits address space so ignore bits above. */ 161 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 162 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 163 164 WREG32_MC(RS480_GART_BASE, tmp); 165 /* TODO: more tweaking here */ 166 WREG32_MC(RS480_GART_FEATURE_ID, 167 (RS480_TLB_ENABLE | 168 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 169 /* Disable snooping */ 170 WREG32_MC(RS480_AGP_MODE_CNTL, 171 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 172 /* Disable AGP mode */ 173 /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, 174 * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ 175 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 176 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 177 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; 178 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 179 } else { 180 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 181 tmp |= RS480_GART_INDEX_REG_EN; 182 WREG32_MC(RS480_MC_MISC_CNTL, tmp); 183 } 184 /* Enable gart */ 185 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 186 rs400_gart_tlb_flush(rdev); 187 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 188 (unsigned)(rdev->mc.gtt_size >> 20), 189 (unsigned long long)rdev->gart.table_addr); 190 rdev->gart.ready = true; 191 return 0; 192 } 193 194 void rs400_gart_disable(struct radeon_device *rdev) 195 { 196 uint32_t tmp; 197 198 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 199 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 200 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 201 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 202 } 203 204 void rs400_gart_fini(struct radeon_device *rdev) 205 { 206 radeon_gart_fini(rdev); 207 rs400_gart_disable(rdev); 208 radeon_gart_table_ram_free(rdev); 209 } 210 211 #define RS400_PTE_WRITEABLE (1 << 2) 212 #define RS400_PTE_READABLE (1 << 3) 213 214 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 215 { 216 uint32_t entry; 217 u32 *gtt = rdev->gart.ptr; 218 219 if (i < 0 || i > rdev->gart.num_gpu_pages) { 220 return -EINVAL; 221 } 222 223 entry = (lower_32_bits(addr) & ~PAGE_MASK) | 224 ((upper_32_bits(addr) & 0xff) << 4) | 225 RS400_PTE_WRITEABLE | RS400_PTE_READABLE; 226 entry = cpu_to_le32(entry); 227 gtt[i] = entry; 228 return 0; 229 } 230 231 int rs400_mc_wait_for_idle(struct radeon_device *rdev) 232 { 233 unsigned i; 234 uint32_t tmp; 235 236 for (i = 0; i < rdev->usec_timeout; i++) { 237 /* read MC_STATUS */ 238 tmp = RREG32(RADEON_MC_STATUS); 239 if (tmp & RADEON_MC_IDLE) { 240 return 0; 241 } 242 DRM_UDELAY(1); 243 } 244 return -1; 245 } 246 247 static void rs400_gpu_init(struct radeon_device *rdev) 248 { 249 /* FIXME: is this correct ? */ 250 r420_pipes_init(rdev); 251 if (rs400_mc_wait_for_idle(rdev)) { 252 printk(KERN_WARNING "rs400: Failed to wait MC idle while " 253 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); 254 } 255 } 256 257 static void rs400_mc_init(struct radeon_device *rdev) 258 { 259 u64 base; 260 261 rs400_gart_adjust_size(rdev); 262 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 263 /* DDR for all card after R300 & IGP */ 264 rdev->mc.vram_is_ddr = true; 265 rdev->mc.vram_width = 128; 266 r100_vram_init_sizes(rdev); 267 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 268 radeon_vram_location(rdev, &rdev->mc, base); 269 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 270 radeon_gtt_location(rdev, &rdev->mc); 271 radeon_update_bandwidth_info(rdev); 272 } 273 274 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 275 { 276 uint32_t r; 277 278 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 279 r = RREG32(RS480_NB_MC_DATA); 280 WREG32(RS480_NB_MC_INDEX, 0xff); 281 return r; 282 } 283 284 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 285 { 286 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 287 WREG32(RS480_NB_MC_DATA, (v)); 288 WREG32(RS480_NB_MC_INDEX, 0xff); 289 } 290 291 #if defined(CONFIG_DEBUG_FS) 292 static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 293 { 294 struct drm_info_node *node = (struct drm_info_node *) m->private; 295 struct drm_device *dev = node->minor->dev; 296 struct radeon_device *rdev = dev->dev_private; 297 uint32_t tmp; 298 299 tmp = RREG32(RADEON_HOST_PATH_CNTL); 300 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 301 tmp = RREG32(RADEON_BUS_CNTL); 302 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 303 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 304 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 305 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 306 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 307 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 308 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 309 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 310 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 311 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 312 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 313 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 314 tmp = RREG32(RS690_HDP_FB_LOCATION); 315 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 316 } else { 317 tmp = RREG32(RADEON_AGP_BASE); 318 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 319 tmp = RREG32(RS480_AGP_BASE_2); 320 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 321 tmp = RREG32(RADEON_MC_AGP_LOCATION); 322 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 323 } 324 tmp = RREG32_MC(RS480_GART_BASE); 325 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 326 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 327 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 328 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 329 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 330 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 331 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 332 tmp = RREG32_MC(0x5F); 333 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 334 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 335 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 336 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 337 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 338 tmp = RREG32_MC(0x3B); 339 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 340 tmp = RREG32_MC(0x3C); 341 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 342 tmp = RREG32_MC(0x30); 343 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 344 tmp = RREG32_MC(0x31); 345 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 346 tmp = RREG32_MC(0x32); 347 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 348 tmp = RREG32_MC(0x33); 349 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 350 tmp = RREG32_MC(0x34); 351 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 352 tmp = RREG32_MC(0x35); 353 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 354 tmp = RREG32_MC(0x36); 355 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 356 tmp = RREG32_MC(0x37); 357 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 358 return 0; 359 } 360 361 static struct drm_info_list rs400_gart_info_list[] = { 362 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 363 }; 364 #endif 365 366 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 367 { 368 #if defined(CONFIG_DEBUG_FS) 369 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 370 #else 371 return 0; 372 #endif 373 } 374 375 static void rs400_mc_program(struct radeon_device *rdev) 376 { 377 struct r100_mc_save save; 378 379 /* Stops all mc clients */ 380 r100_mc_stop(rdev, &save); 381 382 /* Wait for mc idle */ 383 if (rs400_mc_wait_for_idle(rdev)) 384 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 385 WREG32(R_000148_MC_FB_LOCATION, 386 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 387 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 388 389 r100_mc_resume(rdev, &save); 390 } 391 392 static int rs400_startup(struct radeon_device *rdev) 393 { 394 int r; 395 396 r100_set_common_regs(rdev); 397 398 rs400_mc_program(rdev); 399 /* Resume clock */ 400 r300_clock_startup(rdev); 401 /* Initialize GPU configuration (# pipes, ...) */ 402 rs400_gpu_init(rdev); 403 r100_enable_bm(rdev); 404 /* Initialize GART (initialize after TTM so we can allocate 405 * memory through TTM but finalize after TTM) */ 406 r = rs400_gart_enable(rdev); 407 if (r) 408 return r; 409 410 /* allocate wb buffer */ 411 r = radeon_wb_init(rdev); 412 if (r) 413 return r; 414 415 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 416 if (r) { 417 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 418 return r; 419 } 420 421 /* Enable IRQ */ 422 if (!rdev->irq.installed) { 423 r = radeon_irq_kms_init(rdev); 424 if (r) 425 return r; 426 } 427 428 r100_irq_set(rdev); 429 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 430 /* 1M ring buffer */ 431 r = r100_cp_init(rdev, 1024 * 1024); 432 if (r) { 433 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 434 return r; 435 } 436 437 r = radeon_ib_pool_init(rdev); 438 if (r) { 439 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 440 return r; 441 } 442 443 return 0; 444 } 445 446 int rs400_resume(struct radeon_device *rdev) 447 { 448 int r; 449 450 /* Make sur GART are not working */ 451 rs400_gart_disable(rdev); 452 /* Resume clock before doing reset */ 453 r300_clock_startup(rdev); 454 /* setup MC before calling post tables */ 455 rs400_mc_program(rdev); 456 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 457 if (radeon_asic_reset(rdev)) { 458 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 459 RREG32(R_000E40_RBBM_STATUS), 460 RREG32(R_0007C0_CP_STAT)); 461 } 462 /* post */ 463 radeon_combios_asic_init(rdev->ddev); 464 /* Resume clock after posting */ 465 r300_clock_startup(rdev); 466 /* Initialize surface registers */ 467 radeon_surface_init(rdev); 468 469 rdev->accel_working = true; 470 r = rs400_startup(rdev); 471 if (r) { 472 rdev->accel_working = false; 473 } 474 return r; 475 } 476 477 int rs400_suspend(struct radeon_device *rdev) 478 { 479 r100_cp_disable(rdev); 480 radeon_wb_disable(rdev); 481 r100_irq_disable(rdev); 482 rs400_gart_disable(rdev); 483 return 0; 484 } 485 486 void rs400_fini(struct radeon_device *rdev) 487 { 488 r100_cp_fini(rdev); 489 radeon_wb_fini(rdev); 490 radeon_ib_pool_fini(rdev); 491 radeon_gem_fini(rdev); 492 rs400_gart_fini(rdev); 493 radeon_irq_kms_fini(rdev); 494 radeon_fence_driver_fini(rdev); 495 radeon_bo_fini(rdev); 496 radeon_atombios_fini(rdev); 497 kfree(rdev->bios); 498 rdev->bios = NULL; 499 } 500 501 int rs400_init(struct radeon_device *rdev) 502 { 503 int r; 504 505 /* Disable VGA */ 506 r100_vga_render_disable(rdev); 507 /* Initialize scratch registers */ 508 radeon_scratch_init(rdev); 509 /* Initialize surface registers */ 510 radeon_surface_init(rdev); 511 /* TODO: disable VGA need to use VGA request */ 512 /* restore some register to sane defaults */ 513 r100_restore_sanity(rdev); 514 /* BIOS*/ 515 if (!radeon_get_bios(rdev)) { 516 if (ASIC_IS_AVIVO(rdev)) 517 return -EINVAL; 518 } 519 if (rdev->is_atom_bios) { 520 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 521 return -EINVAL; 522 } else { 523 r = radeon_combios_init(rdev); 524 if (r) 525 return r; 526 } 527 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 528 if (radeon_asic_reset(rdev)) { 529 dev_warn(rdev->dev, 530 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 531 RREG32(R_000E40_RBBM_STATUS), 532 RREG32(R_0007C0_CP_STAT)); 533 } 534 /* check if cards are posted or not */ 535 if (radeon_boot_test_post_card(rdev) == false) 536 return -EINVAL; 537 538 /* Initialize clocks */ 539 radeon_get_clock_info(rdev->ddev); 540 /* initialize memory controller */ 541 rs400_mc_init(rdev); 542 /* Fence driver */ 543 r = radeon_fence_driver_init(rdev); 544 if (r) 545 return r; 546 /* Memory manager */ 547 r = radeon_bo_init(rdev); 548 if (r) 549 return r; 550 r = rs400_gart_init(rdev); 551 if (r) 552 return r; 553 r300_set_reg_safe(rdev); 554 555 rdev->accel_working = true; 556 r = rs400_startup(rdev); 557 if (r) { 558 /* Somethings want wront with the accel init stop accel */ 559 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 560 r100_cp_fini(rdev); 561 radeon_wb_fini(rdev); 562 radeon_ib_pool_fini(rdev); 563 rs400_gart_fini(rdev); 564 radeon_irq_kms_fini(rdev); 565 rdev->accel_working = false; 566 } 567 return 0; 568 } 569