1 /* $OpenBSD: si.c,v 1.22 2015/04/06 14:10:59 jsg Exp $ */ 2 /* 3 * Copyright 2011 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Alex Deucher 24 */ 25 #include <dev/pci/drm/drmP.h> 26 #include "radeon.h" 27 #include "radeon_asic.h" 28 #include <dev/pci/drm/radeon_drm.h> 29 #include "sid.h" 30 #include "atom.h" 31 #include "si_blit_shaders.h" 32 33 #define SI_PFP_UCODE_SIZE 2144 34 #define SI_PM4_UCODE_SIZE 2144 35 #define SI_CE_UCODE_SIZE 2144 36 #define SI_RLC_UCODE_SIZE 2048 37 #define SI_MC_UCODE_SIZE 7769 38 39 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin"); 40 MODULE_FIRMWARE("radeon/TAHITI_me.bin"); 41 MODULE_FIRMWARE("radeon/TAHITI_ce.bin"); 42 MODULE_FIRMWARE("radeon/TAHITI_mc.bin"); 43 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin"); 44 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin"); 45 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin"); 46 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin"); 47 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin"); 48 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin"); 49 MODULE_FIRMWARE("radeon/VERDE_pfp.bin"); 50 MODULE_FIRMWARE("radeon/VERDE_me.bin"); 51 MODULE_FIRMWARE("radeon/VERDE_ce.bin"); 52 MODULE_FIRMWARE("radeon/VERDE_mc.bin"); 53 MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); 54 55 extern int r600_ih_ring_alloc(struct radeon_device *rdev); 56 extern void r600_ih_ring_fini(struct radeon_device *rdev); 57 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 58 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 59 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 60 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 61 62 /* get temperature in millidegrees */ 63 int si_get_temp(struct radeon_device *rdev) 64 { 65 u32 temp; 66 int actual_temp = 0; 67 68 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> 69 CTF_TEMP_SHIFT; 70 71 if (temp & 0x200) 72 actual_temp = 255; 73 else 74 actual_temp = temp & 0x1ff; 75 76 actual_temp = (actual_temp * 1000); 77 78 return actual_temp; 79 } 80 81 #define TAHITI_IO_MC_REGS_SIZE 36 82 83 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 84 {0x0000006f, 0x03044000}, 85 {0x00000070, 0x0480c018}, 86 {0x00000071, 0x00000040}, 87 {0x00000072, 0x01000000}, 88 {0x00000074, 0x000000ff}, 89 {0x00000075, 0x00143400}, 90 {0x00000076, 0x08ec0800}, 91 {0x00000077, 0x040000cc}, 92 {0x00000079, 0x00000000}, 93 {0x0000007a, 0x21000409}, 94 {0x0000007c, 0x00000000}, 95 {0x0000007d, 0xe8000000}, 96 {0x0000007e, 0x044408a8}, 97 {0x0000007f, 0x00000003}, 98 {0x00000080, 0x00000000}, 99 {0x00000081, 0x01000000}, 100 {0x00000082, 0x02000000}, 101 {0x00000083, 0x00000000}, 102 {0x00000084, 0xe3f3e4f4}, 103 {0x00000085, 0x00052024}, 104 {0x00000087, 0x00000000}, 105 {0x00000088, 0x66036603}, 106 {0x00000089, 0x01000000}, 107 {0x0000008b, 0x1c0a0000}, 108 {0x0000008c, 0xff010000}, 109 {0x0000008e, 0xffffefff}, 110 {0x0000008f, 0xfff3efff}, 111 {0x00000090, 0xfff3efbf}, 112 {0x00000094, 0x00101101}, 113 {0x00000095, 0x00000fff}, 114 {0x00000096, 0x00116fff}, 115 {0x00000097, 0x60010000}, 116 {0x00000098, 0x10010000}, 117 {0x00000099, 0x00006000}, 118 {0x0000009a, 0x00001000}, 119 {0x0000009f, 0x00a77400} 120 }; 121 122 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 123 {0x0000006f, 0x03044000}, 124 {0x00000070, 0x0480c018}, 125 {0x00000071, 0x00000040}, 126 {0x00000072, 0x01000000}, 127 {0x00000074, 0x000000ff}, 128 {0x00000075, 0x00143400}, 129 {0x00000076, 0x08ec0800}, 130 {0x00000077, 0x040000cc}, 131 {0x00000079, 0x00000000}, 132 {0x0000007a, 0x21000409}, 133 {0x0000007c, 0x00000000}, 134 {0x0000007d, 0xe8000000}, 135 {0x0000007e, 0x044408a8}, 136 {0x0000007f, 0x00000003}, 137 {0x00000080, 0x00000000}, 138 {0x00000081, 0x01000000}, 139 {0x00000082, 0x02000000}, 140 {0x00000083, 0x00000000}, 141 {0x00000084, 0xe3f3e4f4}, 142 {0x00000085, 0x00052024}, 143 {0x00000087, 0x00000000}, 144 {0x00000088, 0x66036603}, 145 {0x00000089, 0x01000000}, 146 {0x0000008b, 0x1c0a0000}, 147 {0x0000008c, 0xff010000}, 148 {0x0000008e, 0xffffefff}, 149 {0x0000008f, 0xfff3efff}, 150 {0x00000090, 0xfff3efbf}, 151 {0x00000094, 0x00101101}, 152 {0x00000095, 0x00000fff}, 153 {0x00000096, 0x00116fff}, 154 {0x00000097, 0x60010000}, 155 {0x00000098, 0x10010000}, 156 {0x00000099, 0x00006000}, 157 {0x0000009a, 0x00001000}, 158 {0x0000009f, 0x00a47400} 159 }; 160 161 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 162 {0x0000006f, 0x03044000}, 163 {0x00000070, 0x0480c018}, 164 {0x00000071, 0x00000040}, 165 {0x00000072, 0x01000000}, 166 {0x00000074, 0x000000ff}, 167 {0x00000075, 0x00143400}, 168 {0x00000076, 0x08ec0800}, 169 {0x00000077, 0x040000cc}, 170 {0x00000079, 0x00000000}, 171 {0x0000007a, 0x21000409}, 172 {0x0000007c, 0x00000000}, 173 {0x0000007d, 0xe8000000}, 174 {0x0000007e, 0x044408a8}, 175 {0x0000007f, 0x00000003}, 176 {0x00000080, 0x00000000}, 177 {0x00000081, 0x01000000}, 178 {0x00000082, 0x02000000}, 179 {0x00000083, 0x00000000}, 180 {0x00000084, 0xe3f3e4f4}, 181 {0x00000085, 0x00052024}, 182 {0x00000087, 0x00000000}, 183 {0x00000088, 0x66036603}, 184 {0x00000089, 0x01000000}, 185 {0x0000008b, 0x1c0a0000}, 186 {0x0000008c, 0xff010000}, 187 {0x0000008e, 0xffffefff}, 188 {0x0000008f, 0xfff3efff}, 189 {0x00000090, 0xfff3efbf}, 190 {0x00000094, 0x00101101}, 191 {0x00000095, 0x00000fff}, 192 {0x00000096, 0x00116fff}, 193 {0x00000097, 0x60010000}, 194 {0x00000098, 0x10010000}, 195 {0x00000099, 0x00006000}, 196 {0x0000009a, 0x00001000}, 197 {0x0000009f, 0x00a37400} 198 }; 199 200 /* ucode loading */ 201 static int si_mc_load_microcode(struct radeon_device *rdev) 202 { 203 const __be32 *fw_data; 204 u32 running, blackout = 0; 205 u32 *io_mc_regs; 206 int i, regs_size, ucode_size; 207 208 if (!rdev->mc_fw) 209 return -EINVAL; 210 211 ucode_size = rdev->mc_fw_size / 4; 212 213 switch (rdev->family) { 214 case CHIP_TAHITI: 215 io_mc_regs = (u32 *)&tahiti_io_mc_regs; 216 ucode_size = SI_MC_UCODE_SIZE; 217 regs_size = TAHITI_IO_MC_REGS_SIZE; 218 break; 219 case CHIP_PITCAIRN: 220 io_mc_regs = (u32 *)&pitcairn_io_mc_regs; 221 ucode_size = SI_MC_UCODE_SIZE; 222 regs_size = TAHITI_IO_MC_REGS_SIZE; 223 break; 224 case CHIP_VERDE: 225 default: 226 io_mc_regs = (u32 *)&verde_io_mc_regs; 227 ucode_size = SI_MC_UCODE_SIZE; 228 regs_size = TAHITI_IO_MC_REGS_SIZE; 229 break; 230 } 231 232 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 233 234 if (running == 0) { 235 if (running) { 236 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 237 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); 238 } 239 240 /* reset the engine and set to writable */ 241 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 242 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 243 244 /* load mc io regs */ 245 for (i = 0; i < regs_size; i++) { 246 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 247 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 248 } 249 /* load the MC ucode */ 250 fw_data = (const __be32 *)rdev->mc_fw; 251 for (i = 0; i < ucode_size; i++) 252 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 253 254 /* put the engine back into the active state */ 255 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 256 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 257 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 258 259 /* wait for training to complete */ 260 for (i = 0; i < rdev->usec_timeout; i++) { 261 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) 262 break; 263 udelay(1); 264 } 265 for (i = 0; i < rdev->usec_timeout; i++) { 266 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) 267 break; 268 udelay(1); 269 } 270 271 if (running) 272 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 273 } 274 275 return 0; 276 } 277 278 static int si_init_microcode(struct radeon_device *rdev) 279 { 280 const char *chip_name; 281 const char *rlc_chip_name; 282 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size; 283 char fw_name[30]; 284 int err; 285 286 DRM_DEBUG("\n"); 287 288 switch (rdev->family) { 289 case CHIP_TAHITI: 290 chip_name = "tahiti"; 291 rlc_chip_name = "tahiti"; 292 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 293 me_req_size = SI_PM4_UCODE_SIZE * 4; 294 ce_req_size = SI_CE_UCODE_SIZE * 4; 295 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 296 mc_req_size = SI_MC_UCODE_SIZE * 4; 297 break; 298 case CHIP_PITCAIRN: 299 chip_name = "pitcairn"; 300 rlc_chip_name = "pitcairn"; 301 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 302 me_req_size = SI_PM4_UCODE_SIZE * 4; 303 ce_req_size = SI_CE_UCODE_SIZE * 4; 304 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 305 mc_req_size = SI_MC_UCODE_SIZE * 4; 306 break; 307 case CHIP_VERDE: 308 chip_name = "verde"; 309 rlc_chip_name = "verde"; 310 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 311 me_req_size = SI_PM4_UCODE_SIZE * 4; 312 ce_req_size = SI_CE_UCODE_SIZE * 4; 313 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 314 mc_req_size = SI_MC_UCODE_SIZE * 4; 315 break; 316 default: BUG(); 317 } 318 319 DRM_INFO("Loading %s Microcode\n", chip_name); 320 321 snprintf(fw_name, sizeof(fw_name), "radeon-%s_pfp", chip_name); 322 err = loadfirmware(fw_name, &rdev->pfp_fw, &rdev->pfp_fw_size); 323 if (err) 324 goto out; 325 if (rdev->pfp_fw_size != pfp_req_size) { 326 DRM_ERROR( 327 "si_cp: Bogus length %zu in firmware \"%s\"\n", 328 rdev->pfp_fw_size, fw_name); 329 err = -EINVAL; 330 goto out; 331 } 332 333 snprintf(fw_name, sizeof(fw_name), "radeon-%s_me", chip_name); 334 err = loadfirmware(fw_name, &rdev->me_fw, &rdev->me_fw_size); 335 if (err) 336 goto out; 337 if (rdev->me_fw_size != me_req_size) { 338 DRM_ERROR( 339 "si_cp: Bogus length %zu in firmware \"%s\"\n", 340 rdev->me_fw_size, fw_name); 341 err = -EINVAL; 342 } 343 344 snprintf(fw_name, sizeof(fw_name), "radeon-%s_ce", chip_name); 345 err = loadfirmware(fw_name, &rdev->ce_fw, &rdev->ce_fw_size); 346 if (err) 347 goto out; 348 if (rdev->ce_fw_size != ce_req_size) { 349 DRM_ERROR( 350 "si_cp: Bogus length %zu in firmware \"%s\"\n", 351 rdev->ce_fw_size, fw_name); 352 err = -EINVAL; 353 } 354 355 snprintf(fw_name, sizeof(fw_name), "radeon-%s_rlc", rlc_chip_name); 356 err = loadfirmware(fw_name, &rdev->rlc_fw, &rdev->rlc_fw_size); 357 if (err) 358 goto out; 359 if (rdev->rlc_fw_size != rlc_req_size) { 360 DRM_ERROR( 361 "si_rlc: Bogus length %zu in firmware \"%s\"\n", 362 rdev->rlc_fw_size, fw_name); 363 err = -EINVAL; 364 } 365 366 snprintf(fw_name, sizeof(fw_name), "radeon-%s_mc", chip_name); 367 err = loadfirmware(fw_name, &rdev->mc_fw, &rdev->mc_fw_size); 368 if (err) 369 goto out; 370 if (rdev->mc_fw_size != mc_req_size) { 371 DRM_ERROR( 372 "si_mc: Bogus length %zu in firmware \"%s\"\n", 373 rdev->mc_fw_size, fw_name); 374 err = -EINVAL; 375 } 376 377 out: 378 if (err) { 379 if (err != -EINVAL) 380 printk(KERN_ERR 381 "si_cp: Failed to load firmware \"%s\"\n", 382 fw_name); 383 if (rdev->pfp_fw) { 384 free(rdev->pfp_fw, M_DEVBUF, 0); 385 rdev->pfp_fw = NULL; 386 } 387 if (rdev->me_fw) { 388 free(rdev->pfp_fw, M_DEVBUF, 0); 389 rdev->me_fw = NULL; 390 } 391 if (rdev->ce_fw) { 392 free(rdev->ce_fw, M_DEVBUF, 0); 393 rdev->ce_fw = NULL; 394 } 395 if (rdev->rlc_fw) { 396 free(rdev->rlc_fw, M_DEVBUF, 0); 397 rdev->rlc_fw = NULL; 398 } 399 if (rdev->mc_fw) { 400 free(rdev->mc_fw, M_DEVBUF, 0); 401 rdev->mc_fw = NULL; 402 } 403 } 404 return err; 405 } 406 407 /* watermark setup */ 408 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev, 409 struct radeon_crtc *radeon_crtc, 410 struct drm_display_mode *mode, 411 struct drm_display_mode *other_mode) 412 { 413 u32 tmp, buffer_alloc, i; 414 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; 415 /* 416 * Line Buffer Setup 417 * There are 3 line buffers, each one shared by 2 display controllers. 418 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 419 * the display controllers. The paritioning is done via one of four 420 * preset allocations specified in bits 21:20: 421 * 0 - half lb 422 * 2 - whole lb, other crtc must be disabled 423 */ 424 /* this can get tricky if we have two large displays on a paired group 425 * of crtcs. Ideally for multiple large displays we'd assign them to 426 * non-linked crtcs for maximum line buffer allocation. 427 */ 428 if (radeon_crtc->base.enabled && mode) { 429 if (other_mode) { 430 tmp = 0; /* 1/2 */ 431 buffer_alloc = 1; 432 } else { 433 tmp = 2; /* whole */ 434 buffer_alloc = 2; 435 } 436 } else { 437 tmp = 0; 438 buffer_alloc = 0; 439 } 440 441 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, 442 DC_LB_MEMORY_CONFIG(tmp)); 443 444 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 445 DMIF_BUFFERS_ALLOCATED(buffer_alloc)); 446 for (i = 0; i < rdev->usec_timeout; i++) { 447 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 448 DMIF_BUFFERS_ALLOCATED_COMPLETED) 449 break; 450 udelay(1); 451 } 452 453 if (radeon_crtc->base.enabled && mode) { 454 switch (tmp) { 455 case 0: 456 default: 457 return 4096 * 2; 458 case 2: 459 return 8192 * 2; 460 } 461 } 462 463 /* controller not enabled, so no lb used */ 464 return 0; 465 } 466 467 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev) 468 { 469 u32 tmp = RREG32(MC_SHARED_CHMAP); 470 471 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 472 case 0: 473 default: 474 return 1; 475 case 1: 476 return 2; 477 case 2: 478 return 4; 479 case 3: 480 return 8; 481 case 4: 482 return 3; 483 case 5: 484 return 6; 485 case 6: 486 return 10; 487 case 7: 488 return 12; 489 case 8: 490 return 16; 491 } 492 } 493 494 struct dce6_wm_params { 495 u32 dram_channels; /* number of dram channels */ 496 u32 yclk; /* bandwidth per dram data pin in kHz */ 497 u32 sclk; /* engine clock in kHz */ 498 u32 disp_clk; /* display clock in kHz */ 499 u32 src_width; /* viewport width */ 500 u32 active_time; /* active display time in ns */ 501 u32 blank_time; /* blank time in ns */ 502 bool interlaced; /* mode is interlaced */ 503 fixed20_12 vsc; /* vertical scale ratio */ 504 u32 num_heads; /* number of active crtcs */ 505 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 506 u32 lb_size; /* line buffer allocated to pipe */ 507 u32 vtaps; /* vertical scaler taps */ 508 }; 509 510 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm) 511 { 512 /* Calculate raw DRAM Bandwidth */ 513 fixed20_12 dram_efficiency; /* 0.7 */ 514 fixed20_12 yclk, dram_channels, bandwidth; 515 fixed20_12 a; 516 517 a.full = dfixed_const(1000); 518 yclk.full = dfixed_const(wm->yclk); 519 yclk.full = dfixed_div(yclk, a); 520 dram_channels.full = dfixed_const(wm->dram_channels * 4); 521 a.full = dfixed_const(10); 522 dram_efficiency.full = dfixed_const(7); 523 dram_efficiency.full = dfixed_div(dram_efficiency, a); 524 bandwidth.full = dfixed_mul(dram_channels, yclk); 525 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 526 527 return dfixed_trunc(bandwidth); 528 } 529 530 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm) 531 { 532 /* Calculate DRAM Bandwidth and the part allocated to display. */ 533 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 534 fixed20_12 yclk, dram_channels, bandwidth; 535 fixed20_12 a; 536 537 a.full = dfixed_const(1000); 538 yclk.full = dfixed_const(wm->yclk); 539 yclk.full = dfixed_div(yclk, a); 540 dram_channels.full = dfixed_const(wm->dram_channels * 4); 541 a.full = dfixed_const(10); 542 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 543 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 544 bandwidth.full = dfixed_mul(dram_channels, yclk); 545 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 546 547 return dfixed_trunc(bandwidth); 548 } 549 550 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm) 551 { 552 /* Calculate the display Data return Bandwidth */ 553 fixed20_12 return_efficiency; /* 0.8 */ 554 fixed20_12 sclk, bandwidth; 555 fixed20_12 a; 556 557 a.full = dfixed_const(1000); 558 sclk.full = dfixed_const(wm->sclk); 559 sclk.full = dfixed_div(sclk, a); 560 a.full = dfixed_const(10); 561 return_efficiency.full = dfixed_const(8); 562 return_efficiency.full = dfixed_div(return_efficiency, a); 563 a.full = dfixed_const(32); 564 bandwidth.full = dfixed_mul(a, sclk); 565 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 566 567 return dfixed_trunc(bandwidth); 568 } 569 570 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm) 571 { 572 return 32; 573 } 574 575 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm) 576 { 577 /* Calculate the DMIF Request Bandwidth */ 578 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 579 fixed20_12 disp_clk, sclk, bandwidth; 580 fixed20_12 a, b1, b2; 581 u32 min_bandwidth; 582 583 a.full = dfixed_const(1000); 584 disp_clk.full = dfixed_const(wm->disp_clk); 585 disp_clk.full = dfixed_div(disp_clk, a); 586 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2); 587 b1.full = dfixed_mul(a, disp_clk); 588 589 a.full = dfixed_const(1000); 590 sclk.full = dfixed_const(wm->sclk); 591 sclk.full = dfixed_div(sclk, a); 592 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm)); 593 b2.full = dfixed_mul(a, sclk); 594 595 a.full = dfixed_const(10); 596 disp_clk_request_efficiency.full = dfixed_const(8); 597 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 598 599 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2)); 600 601 a.full = dfixed_const(min_bandwidth); 602 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency); 603 604 return dfixed_trunc(bandwidth); 605 } 606 607 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm) 608 { 609 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 610 u32 dram_bandwidth = dce6_dram_bandwidth(wm); 611 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm); 612 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm); 613 614 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 615 } 616 617 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm) 618 { 619 /* Calculate the display mode Average Bandwidth 620 * DisplayMode should contain the source and destination dimensions, 621 * timing, etc. 622 */ 623 fixed20_12 bpp; 624 fixed20_12 line_time; 625 fixed20_12 src_width; 626 fixed20_12 bandwidth; 627 fixed20_12 a; 628 629 a.full = dfixed_const(1000); 630 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 631 line_time.full = dfixed_div(line_time, a); 632 bpp.full = dfixed_const(wm->bytes_per_pixel); 633 src_width.full = dfixed_const(wm->src_width); 634 bandwidth.full = dfixed_mul(src_width, bpp); 635 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 636 bandwidth.full = dfixed_div(bandwidth, line_time); 637 638 return dfixed_trunc(bandwidth); 639 } 640 641 static u32 dce6_latency_watermark(struct dce6_wm_params *wm) 642 { 643 /* First calcualte the latency in ns */ 644 u32 mc_latency = 2000; /* 2000 ns. */ 645 u32 available_bandwidth = dce6_available_bandwidth(wm); 646 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 647 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 648 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 649 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 650 (wm->num_heads * cursor_line_pair_return_time); 651 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 652 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 653 u32 tmp, dmif_size = 12288; 654 fixed20_12 a, b, c; 655 656 if (wm->num_heads == 0) 657 return 0; 658 659 a.full = dfixed_const(2); 660 b.full = dfixed_const(1); 661 if ((wm->vsc.full > a.full) || 662 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 663 (wm->vtaps >= 5) || 664 ((wm->vsc.full >= a.full) && wm->interlaced)) 665 max_src_lines_per_dst_line = 4; 666 else 667 max_src_lines_per_dst_line = 2; 668 669 a.full = dfixed_const(available_bandwidth); 670 b.full = dfixed_const(wm->num_heads); 671 a.full = dfixed_div(a, b); 672 673 b.full = dfixed_const(mc_latency + 512); 674 c.full = dfixed_const(wm->disp_clk); 675 b.full = dfixed_div(b, c); 676 677 c.full = dfixed_const(dmif_size); 678 b.full = dfixed_div(c, b); 679 680 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 681 682 b.full = dfixed_const(1000); 683 c.full = dfixed_const(wm->disp_clk); 684 b.full = dfixed_div(c, b); 685 c.full = dfixed_const(wm->bytes_per_pixel); 686 b.full = dfixed_mul(b, c); 687 688 lb_fill_bw = min(tmp, dfixed_trunc(b)); 689 690 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 691 b.full = dfixed_const(1000); 692 c.full = dfixed_const(lb_fill_bw); 693 b.full = dfixed_div(c, b); 694 a.full = dfixed_div(a, b); 695 line_fill_time = dfixed_trunc(a); 696 697 if (line_fill_time < wm->active_time) 698 return latency; 699 else 700 return latency + (line_fill_time - wm->active_time); 701 702 } 703 704 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 705 { 706 if (dce6_average_bandwidth(wm) <= 707 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) 708 return true; 709 else 710 return false; 711 }; 712 713 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 714 { 715 if (dce6_average_bandwidth(wm) <= 716 (dce6_available_bandwidth(wm) / wm->num_heads)) 717 return true; 718 else 719 return false; 720 }; 721 722 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm) 723 { 724 u32 lb_partitions = wm->lb_size / wm->src_width; 725 u32 line_time = wm->active_time + wm->blank_time; 726 u32 latency_tolerant_lines; 727 u32 latency_hiding; 728 fixed20_12 a; 729 730 a.full = dfixed_const(1); 731 if (wm->vsc.full > a.full) 732 latency_tolerant_lines = 1; 733 else { 734 if (lb_partitions <= (wm->vtaps + 1)) 735 latency_tolerant_lines = 1; 736 else 737 latency_tolerant_lines = 2; 738 } 739 740 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 741 742 if (dce6_latency_watermark(wm) <= latency_hiding) 743 return true; 744 else 745 return false; 746 } 747 748 static void dce6_program_watermarks(struct radeon_device *rdev, 749 struct radeon_crtc *radeon_crtc, 750 u32 lb_size, u32 num_heads) 751 { 752 struct drm_display_mode *mode = &radeon_crtc->base.mode; 753 struct dce6_wm_params wm; 754 u32 pixel_period; 755 u32 line_time = 0; 756 u32 latency_watermark_a = 0, latency_watermark_b = 0; 757 u32 priority_a_mark = 0, priority_b_mark = 0; 758 u32 priority_a_cnt = PRIORITY_OFF; 759 u32 priority_b_cnt = PRIORITY_OFF; 760 u32 tmp, arb_control3; 761 fixed20_12 a, b, c; 762 763 if (radeon_crtc->base.enabled && num_heads && mode) { 764 pixel_period = 1000000 / (u32)mode->clock; 765 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 766 priority_a_cnt = 0; 767 priority_b_cnt = 0; 768 769 wm.yclk = rdev->pm.current_mclk * 10; 770 wm.sclk = rdev->pm.current_sclk * 10; 771 wm.disp_clk = mode->clock; 772 wm.src_width = mode->crtc_hdisplay; 773 wm.active_time = mode->crtc_hdisplay * pixel_period; 774 wm.blank_time = line_time - wm.active_time; 775 wm.interlaced = false; 776 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 777 wm.interlaced = true; 778 wm.vsc = radeon_crtc->vsc; 779 wm.vtaps = 1; 780 if (radeon_crtc->rmx_type != RMX_OFF) 781 wm.vtaps = 2; 782 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ 783 wm.lb_size = lb_size; 784 if (rdev->family == CHIP_ARUBA) 785 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); 786 else 787 wm.dram_channels = si_get_number_of_dram_channels(rdev); 788 wm.num_heads = num_heads; 789 790 /* set for high clocks */ 791 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535); 792 /* set for low clocks */ 793 /* wm.yclk = low clk; wm.sclk = low clk */ 794 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535); 795 796 /* possibly force display priority to high */ 797 /* should really do this at mode validation time... */ 798 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || 799 !dce6_average_bandwidth_vs_available_bandwidth(&wm) || 800 !dce6_check_latency_hiding(&wm) || 801 (rdev->disp_priority == 2)) { 802 DRM_DEBUG_KMS("force priority to high\n"); 803 priority_a_cnt |= PRIORITY_ALWAYS_ON; 804 priority_b_cnt |= PRIORITY_ALWAYS_ON; 805 } 806 807 a.full = dfixed_const(1000); 808 b.full = dfixed_const(mode->clock); 809 b.full = dfixed_div(b, a); 810 c.full = dfixed_const(latency_watermark_a); 811 c.full = dfixed_mul(c, b); 812 c.full = dfixed_mul(c, radeon_crtc->hsc); 813 c.full = dfixed_div(c, a); 814 a.full = dfixed_const(16); 815 c.full = dfixed_div(c, a); 816 priority_a_mark = dfixed_trunc(c); 817 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 818 819 a.full = dfixed_const(1000); 820 b.full = dfixed_const(mode->clock); 821 b.full = dfixed_div(b, a); 822 c.full = dfixed_const(latency_watermark_b); 823 c.full = dfixed_mul(c, b); 824 c.full = dfixed_mul(c, radeon_crtc->hsc); 825 c.full = dfixed_div(c, a); 826 a.full = dfixed_const(16); 827 c.full = dfixed_div(c, a); 828 priority_b_mark = dfixed_trunc(c); 829 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 830 } 831 832 /* select wm A */ 833 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); 834 tmp = arb_control3; 835 tmp &= ~LATENCY_WATERMARK_MASK(3); 836 tmp |= LATENCY_WATERMARK_MASK(1); 837 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); 838 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, 839 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 840 LATENCY_HIGH_WATERMARK(line_time))); 841 /* select wm B */ 842 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); 843 tmp &= ~LATENCY_WATERMARK_MASK(3); 844 tmp |= LATENCY_WATERMARK_MASK(2); 845 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); 846 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, 847 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 848 LATENCY_HIGH_WATERMARK(line_time))); 849 /* restore original selection */ 850 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); 851 852 /* write the priority marks */ 853 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 854 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 855 856 } 857 858 void dce6_bandwidth_update(struct radeon_device *rdev) 859 { 860 struct drm_display_mode *mode0 = NULL; 861 struct drm_display_mode *mode1 = NULL; 862 u32 num_heads = 0, lb_size; 863 int i; 864 865 radeon_update_display_priority(rdev); 866 867 for (i = 0; i < rdev->num_crtc; i++) { 868 if (rdev->mode_info.crtcs[i]->base.enabled) 869 num_heads++; 870 } 871 for (i = 0; i < rdev->num_crtc; i += 2) { 872 mode0 = &rdev->mode_info.crtcs[i]->base.mode; 873 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; 874 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); 875 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); 876 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); 877 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); 878 } 879 } 880 881 /* 882 * Core functions 883 */ 884 static void si_tiling_mode_table_init(struct radeon_device *rdev) 885 { 886 const u32 num_tile_mode_states = 32; 887 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; 888 889 switch (rdev->config.si.mem_row_size_in_kb) { 890 case 1: 891 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 892 break; 893 case 2: 894 default: 895 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 896 break; 897 case 4: 898 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 899 break; 900 } 901 902 if ((rdev->family == CHIP_TAHITI) || 903 (rdev->family == CHIP_PITCAIRN)) { 904 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 905 switch (reg_offset) { 906 case 0: /* non-AA compressed depth or any compressed stencil */ 907 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 908 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 909 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 911 NUM_BANKS(ADDR_SURF_16_BANK) | 912 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 913 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 914 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 915 break; 916 case 1: /* 2xAA/4xAA compressed depth only */ 917 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 918 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 919 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 920 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 921 NUM_BANKS(ADDR_SURF_16_BANK) | 922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 925 break; 926 case 2: /* 8xAA compressed depth only */ 927 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 928 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 929 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 930 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 931 NUM_BANKS(ADDR_SURF_16_BANK) | 932 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 933 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 934 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 935 break; 936 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 937 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 938 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 939 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 940 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 941 NUM_BANKS(ADDR_SURF_16_BANK) | 942 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 943 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 944 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 945 break; 946 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 947 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 948 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 949 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 950 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 951 NUM_BANKS(ADDR_SURF_16_BANK) | 952 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 953 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 954 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 955 break; 956 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 957 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 958 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 959 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 960 TILE_SPLIT(split_equal_to_row_size) | 961 NUM_BANKS(ADDR_SURF_16_BANK) | 962 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 963 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 964 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 965 break; 966 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 967 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 968 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 969 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 970 TILE_SPLIT(split_equal_to_row_size) | 971 NUM_BANKS(ADDR_SURF_16_BANK) | 972 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 973 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 974 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 975 break; 976 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 977 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 978 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 979 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 980 TILE_SPLIT(split_equal_to_row_size) | 981 NUM_BANKS(ADDR_SURF_16_BANK) | 982 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 983 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 984 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 985 break; 986 case 8: /* 1D and 1D Array Surfaces */ 987 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 988 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 989 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 990 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 991 NUM_BANKS(ADDR_SURF_16_BANK) | 992 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 993 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 994 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 995 break; 996 case 9: /* Displayable maps. */ 997 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 998 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 999 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1000 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1001 NUM_BANKS(ADDR_SURF_16_BANK) | 1002 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1003 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1004 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1005 break; 1006 case 10: /* Display 8bpp. */ 1007 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1008 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1009 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1010 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1011 NUM_BANKS(ADDR_SURF_16_BANK) | 1012 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1013 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1014 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1015 break; 1016 case 11: /* Display 16bpp. */ 1017 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1018 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1019 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1020 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1021 NUM_BANKS(ADDR_SURF_16_BANK) | 1022 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1023 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1024 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1025 break; 1026 case 12: /* Display 32bpp. */ 1027 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1028 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1029 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1030 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1031 NUM_BANKS(ADDR_SURF_16_BANK) | 1032 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1033 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1034 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1035 break; 1036 case 13: /* Thin. */ 1037 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1038 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1039 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1040 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1041 NUM_BANKS(ADDR_SURF_16_BANK) | 1042 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1043 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1044 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1045 break; 1046 case 14: /* Thin 8 bpp. */ 1047 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1048 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1049 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1050 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1051 NUM_BANKS(ADDR_SURF_16_BANK) | 1052 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1053 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1054 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1055 break; 1056 case 15: /* Thin 16 bpp. */ 1057 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1058 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1059 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1060 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1061 NUM_BANKS(ADDR_SURF_16_BANK) | 1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1065 break; 1066 case 16: /* Thin 32 bpp. */ 1067 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1068 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1069 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1070 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1071 NUM_BANKS(ADDR_SURF_16_BANK) | 1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1075 break; 1076 case 17: /* Thin 64 bpp. */ 1077 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1078 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1079 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1080 TILE_SPLIT(split_equal_to_row_size) | 1081 NUM_BANKS(ADDR_SURF_16_BANK) | 1082 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1083 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1084 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1085 break; 1086 case 21: /* 8 bpp PRT. */ 1087 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1088 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1091 NUM_BANKS(ADDR_SURF_16_BANK) | 1092 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1093 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1094 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1095 break; 1096 case 22: /* 16 bpp PRT */ 1097 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1098 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1099 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1100 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1101 NUM_BANKS(ADDR_SURF_16_BANK) | 1102 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1103 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1104 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1105 break; 1106 case 23: /* 32 bpp PRT */ 1107 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1108 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1109 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1111 NUM_BANKS(ADDR_SURF_16_BANK) | 1112 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1113 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1114 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1115 break; 1116 case 24: /* 64 bpp PRT */ 1117 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1118 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1119 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1120 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1121 NUM_BANKS(ADDR_SURF_16_BANK) | 1122 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1123 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1124 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1125 break; 1126 case 25: /* 128 bpp PRT */ 1127 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1128 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1129 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1130 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1131 NUM_BANKS(ADDR_SURF_8_BANK) | 1132 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1133 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1134 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1135 break; 1136 default: 1137 gb_tile_moden = 0; 1138 break; 1139 } 1140 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1141 } 1142 } else if (rdev->family == CHIP_VERDE) { 1143 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1144 switch (reg_offset) { 1145 case 0: /* non-AA compressed depth or any compressed stencil */ 1146 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1147 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1148 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1149 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1150 NUM_BANKS(ADDR_SURF_16_BANK) | 1151 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1152 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1153 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1154 break; 1155 case 1: /* 2xAA/4xAA compressed depth only */ 1156 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1157 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1158 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1159 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1160 NUM_BANKS(ADDR_SURF_16_BANK) | 1161 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1164 break; 1165 case 2: /* 8xAA compressed depth only */ 1166 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1167 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1168 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1169 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1170 NUM_BANKS(ADDR_SURF_16_BANK) | 1171 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1172 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1173 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1174 break; 1175 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 1176 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1177 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1178 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1179 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1180 NUM_BANKS(ADDR_SURF_16_BANK) | 1181 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1182 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1183 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1184 break; 1185 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 1186 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1187 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1188 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1189 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1190 NUM_BANKS(ADDR_SURF_16_BANK) | 1191 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1192 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1193 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1194 break; 1195 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 1196 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1197 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1198 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1199 TILE_SPLIT(split_equal_to_row_size) | 1200 NUM_BANKS(ADDR_SURF_16_BANK) | 1201 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1202 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1203 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1204 break; 1205 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 1206 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1207 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1208 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1209 TILE_SPLIT(split_equal_to_row_size) | 1210 NUM_BANKS(ADDR_SURF_16_BANK) | 1211 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1214 break; 1215 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 1216 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1217 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1218 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1219 TILE_SPLIT(split_equal_to_row_size) | 1220 NUM_BANKS(ADDR_SURF_16_BANK) | 1221 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1224 break; 1225 case 8: /* 1D and 1D Array Surfaces */ 1226 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1227 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1228 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1229 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1230 NUM_BANKS(ADDR_SURF_16_BANK) | 1231 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1232 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1233 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1234 break; 1235 case 9: /* Displayable maps. */ 1236 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1237 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1238 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1239 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1240 NUM_BANKS(ADDR_SURF_16_BANK) | 1241 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1242 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1243 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1244 break; 1245 case 10: /* Display 8bpp. */ 1246 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1247 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1248 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1249 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1250 NUM_BANKS(ADDR_SURF_16_BANK) | 1251 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1252 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1253 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1254 break; 1255 case 11: /* Display 16bpp. */ 1256 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1257 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1258 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1260 NUM_BANKS(ADDR_SURF_16_BANK) | 1261 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1264 break; 1265 case 12: /* Display 32bpp. */ 1266 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1267 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1268 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1269 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1270 NUM_BANKS(ADDR_SURF_16_BANK) | 1271 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1272 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1273 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1274 break; 1275 case 13: /* Thin. */ 1276 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1277 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1278 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1279 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1280 NUM_BANKS(ADDR_SURF_16_BANK) | 1281 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1282 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1283 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1284 break; 1285 case 14: /* Thin 8 bpp. */ 1286 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1287 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1288 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1289 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1290 NUM_BANKS(ADDR_SURF_16_BANK) | 1291 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1292 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1293 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1294 break; 1295 case 15: /* Thin 16 bpp. */ 1296 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1297 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1298 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1299 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1300 NUM_BANKS(ADDR_SURF_16_BANK) | 1301 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1302 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1303 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1304 break; 1305 case 16: /* Thin 32 bpp. */ 1306 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1307 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1308 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1309 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1310 NUM_BANKS(ADDR_SURF_16_BANK) | 1311 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1312 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1313 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1314 break; 1315 case 17: /* Thin 64 bpp. */ 1316 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1317 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1318 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1319 TILE_SPLIT(split_equal_to_row_size) | 1320 NUM_BANKS(ADDR_SURF_16_BANK) | 1321 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1322 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1323 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1324 break; 1325 case 21: /* 8 bpp PRT. */ 1326 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1327 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1328 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1329 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1330 NUM_BANKS(ADDR_SURF_16_BANK) | 1331 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1334 break; 1335 case 22: /* 16 bpp PRT */ 1336 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1337 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1338 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1339 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1340 NUM_BANKS(ADDR_SURF_16_BANK) | 1341 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1342 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1343 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1344 break; 1345 case 23: /* 32 bpp PRT */ 1346 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1347 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1348 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1349 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1350 NUM_BANKS(ADDR_SURF_16_BANK) | 1351 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1354 break; 1355 case 24: /* 64 bpp PRT */ 1356 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1357 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1358 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1359 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1360 NUM_BANKS(ADDR_SURF_16_BANK) | 1361 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1362 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1363 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1364 break; 1365 case 25: /* 128 bpp PRT */ 1366 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1367 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1368 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1369 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1370 NUM_BANKS(ADDR_SURF_8_BANK) | 1371 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1374 break; 1375 default: 1376 gb_tile_moden = 0; 1377 break; 1378 } 1379 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1380 } 1381 } else 1382 DRM_ERROR("unknown asic: 0x%x\n", rdev->family); 1383 } 1384 1385 static void si_select_se_sh(struct radeon_device *rdev, 1386 u32 se_num, u32 sh_num) 1387 { 1388 u32 data = INSTANCE_BROADCAST_WRITES; 1389 1390 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1391 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; 1392 else if (se_num == 0xffffffff) 1393 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 1394 else if (sh_num == 0xffffffff) 1395 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); 1396 else 1397 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); 1398 WREG32(GRBM_GFX_INDEX, data); 1399 } 1400 1401 static u32 si_create_bitmask(u32 bit_width) 1402 { 1403 u32 i, mask = 0; 1404 1405 for (i = 0; i < bit_width; i++) { 1406 mask <<= 1; 1407 mask |= 1; 1408 } 1409 return mask; 1410 } 1411 1412 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh) 1413 { 1414 u32 data, mask; 1415 1416 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); 1417 if (data & 1) 1418 data &= INACTIVE_CUS_MASK; 1419 else 1420 data = 0; 1421 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); 1422 1423 data >>= INACTIVE_CUS_SHIFT; 1424 1425 mask = si_create_bitmask(cu_per_sh); 1426 1427 return ~data & mask; 1428 } 1429 1430 static void si_setup_spi(struct radeon_device *rdev, 1431 u32 se_num, u32 sh_per_se, 1432 u32 cu_per_sh) 1433 { 1434 int i, j, k; 1435 u32 data, mask, active_cu; 1436 1437 for (i = 0; i < se_num; i++) { 1438 for (j = 0; j < sh_per_se; j++) { 1439 si_select_se_sh(rdev, i, j); 1440 data = RREG32(SPI_STATIC_THREAD_MGMT_3); 1441 active_cu = si_get_cu_enabled(rdev, cu_per_sh); 1442 1443 mask = 1; 1444 for (k = 0; k < 16; k++) { 1445 mask <<= k; 1446 if (active_cu & mask) { 1447 data &= ~mask; 1448 WREG32(SPI_STATIC_THREAD_MGMT_3, data); 1449 break; 1450 } 1451 } 1452 } 1453 } 1454 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1455 } 1456 1457 static u32 si_get_rb_disabled(struct radeon_device *rdev, 1458 u32 max_rb_num_per_se, 1459 u32 sh_per_se) 1460 { 1461 u32 data, mask; 1462 1463 data = RREG32(CC_RB_BACKEND_DISABLE); 1464 if (data & 1) 1465 data &= BACKEND_DISABLE_MASK; 1466 else 1467 data = 0; 1468 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); 1469 1470 data >>= BACKEND_DISABLE_SHIFT; 1471 1472 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se); 1473 1474 return data & mask; 1475 } 1476 1477 static void si_setup_rb(struct radeon_device *rdev, 1478 u32 se_num, u32 sh_per_se, 1479 u32 max_rb_num_per_se) 1480 { 1481 int i, j; 1482 u32 data, mask; 1483 u32 disabled_rbs = 0; 1484 u32 enabled_rbs = 0; 1485 1486 for (i = 0; i < se_num; i++) { 1487 for (j = 0; j < sh_per_se; j++) { 1488 si_select_se_sh(rdev, i, j); 1489 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se); 1490 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); 1491 } 1492 } 1493 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1494 1495 mask = 1; 1496 for (i = 0; i < max_rb_num_per_se * se_num; i++) { 1497 if (!(disabled_rbs & mask)) 1498 enabled_rbs |= mask; 1499 mask <<= 1; 1500 } 1501 1502 rdev->config.si.backend_enable_mask = enabled_rbs; 1503 1504 for (i = 0; i < se_num; i++) { 1505 si_select_se_sh(rdev, i, 0xffffffff); 1506 data = 0; 1507 for (j = 0; j < sh_per_se; j++) { 1508 switch (enabled_rbs & 3) { 1509 case 1: 1510 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); 1511 break; 1512 case 2: 1513 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2); 1514 break; 1515 case 3: 1516 default: 1517 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2); 1518 break; 1519 } 1520 enabled_rbs >>= 2; 1521 } 1522 WREG32(PA_SC_RASTER_CONFIG, data); 1523 } 1524 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1525 } 1526 1527 static void si_gpu_init(struct radeon_device *rdev) 1528 { 1529 u32 gb_addr_config = 0; 1530 u32 mc_shared_chmap, mc_arb_ramcfg; 1531 u32 sx_debug_1; 1532 u32 hdp_host_path_cntl; 1533 u32 tmp; 1534 int i, j; 1535 1536 switch (rdev->family) { 1537 case CHIP_TAHITI: 1538 rdev->config.si.max_shader_engines = 2; 1539 rdev->config.si.max_tile_pipes = 12; 1540 rdev->config.si.max_cu_per_sh = 8; 1541 rdev->config.si.max_sh_per_se = 2; 1542 rdev->config.si.max_backends_per_se = 4; 1543 rdev->config.si.max_texture_channel_caches = 12; 1544 rdev->config.si.max_gprs = 256; 1545 rdev->config.si.max_gs_threads = 32; 1546 rdev->config.si.max_hw_contexts = 8; 1547 1548 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1549 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1550 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1551 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1552 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1553 break; 1554 case CHIP_PITCAIRN: 1555 rdev->config.si.max_shader_engines = 2; 1556 rdev->config.si.max_tile_pipes = 8; 1557 rdev->config.si.max_cu_per_sh = 5; 1558 rdev->config.si.max_sh_per_se = 2; 1559 rdev->config.si.max_backends_per_se = 4; 1560 rdev->config.si.max_texture_channel_caches = 8; 1561 rdev->config.si.max_gprs = 256; 1562 rdev->config.si.max_gs_threads = 32; 1563 rdev->config.si.max_hw_contexts = 8; 1564 1565 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1566 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1567 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1568 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1569 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1570 break; 1571 case CHIP_VERDE: 1572 default: 1573 rdev->config.si.max_shader_engines = 1; 1574 rdev->config.si.max_tile_pipes = 4; 1575 rdev->config.si.max_cu_per_sh = 5; 1576 rdev->config.si.max_sh_per_se = 2; 1577 rdev->config.si.max_backends_per_se = 4; 1578 rdev->config.si.max_texture_channel_caches = 4; 1579 rdev->config.si.max_gprs = 256; 1580 rdev->config.si.max_gs_threads = 32; 1581 rdev->config.si.max_hw_contexts = 8; 1582 1583 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1584 rdev->config.si.sc_prim_fifo_size_backend = 0x40; 1585 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1586 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1587 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1588 break; 1589 } 1590 1591 /* Initialize HDP */ 1592 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1593 WREG32((0x2c14 + j), 0x00000000); 1594 WREG32((0x2c18 + j), 0x00000000); 1595 WREG32((0x2c1c + j), 0x00000000); 1596 WREG32((0x2c20 + j), 0x00000000); 1597 WREG32((0x2c24 + j), 0x00000000); 1598 } 1599 1600 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1601 1602 evergreen_fix_pci_max_read_req_size(rdev); 1603 1604 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 1605 1606 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1607 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1608 1609 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; 1610 rdev->config.si.mem_max_burst_length_bytes = 256; 1611 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1612 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1613 if (rdev->config.si.mem_row_size_in_kb > 4) 1614 rdev->config.si.mem_row_size_in_kb = 4; 1615 /* XXX use MC settings? */ 1616 rdev->config.si.shader_engine_tile_size = 32; 1617 rdev->config.si.num_gpus = 1; 1618 rdev->config.si.multi_gpu_tile_size = 64; 1619 1620 /* fix up row size */ 1621 gb_addr_config &= ~ROW_SIZE_MASK; 1622 switch (rdev->config.si.mem_row_size_in_kb) { 1623 case 1: 1624 default: 1625 gb_addr_config |= ROW_SIZE(0); 1626 break; 1627 case 2: 1628 gb_addr_config |= ROW_SIZE(1); 1629 break; 1630 case 4: 1631 gb_addr_config |= ROW_SIZE(2); 1632 break; 1633 } 1634 1635 /* setup tiling info dword. gb_addr_config is not adequate since it does 1636 * not have bank info, so create a custom tiling dword. 1637 * bits 3:0 num_pipes 1638 * bits 7:4 num_banks 1639 * bits 11:8 group_size 1640 * bits 15:12 row_size 1641 */ 1642 rdev->config.si.tile_config = 0; 1643 switch (rdev->config.si.num_tile_pipes) { 1644 case 1: 1645 rdev->config.si.tile_config |= (0 << 0); 1646 break; 1647 case 2: 1648 rdev->config.si.tile_config |= (1 << 0); 1649 break; 1650 case 4: 1651 rdev->config.si.tile_config |= (2 << 0); 1652 break; 1653 case 8: 1654 default: 1655 /* XXX what about 12? */ 1656 rdev->config.si.tile_config |= (3 << 0); 1657 break; 1658 } 1659 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 1660 case 0: /* four banks */ 1661 rdev->config.si.tile_config |= 0 << 4; 1662 break; 1663 case 1: /* eight banks */ 1664 rdev->config.si.tile_config |= 1 << 4; 1665 break; 1666 case 2: /* sixteen banks */ 1667 default: 1668 rdev->config.si.tile_config |= 2 << 4; 1669 break; 1670 } 1671 rdev->config.si.tile_config |= 1672 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1673 rdev->config.si.tile_config |= 1674 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1675 1676 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1677 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1678 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1679 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1680 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1681 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1682 1683 si_tiling_mode_table_init(rdev); 1684 1685 si_setup_rb(rdev, rdev->config.si.max_shader_engines, 1686 rdev->config.si.max_sh_per_se, 1687 rdev->config.si.max_backends_per_se); 1688 1689 si_setup_spi(rdev, rdev->config.si.max_shader_engines, 1690 rdev->config.si.max_sh_per_se, 1691 rdev->config.si.max_cu_per_sh); 1692 1693 1694 /* set HW defaults for 3D engine */ 1695 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1696 ROQ_IB2_START(0x2b))); 1697 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1698 1699 sx_debug_1 = RREG32(SX_DEBUG_1); 1700 WREG32(SX_DEBUG_1, sx_debug_1); 1701 1702 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1703 1704 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | 1705 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) | 1706 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) | 1707 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size))); 1708 1709 WREG32(VGT_NUM_INSTANCES, 1); 1710 1711 WREG32(CP_PERFMON_CNTL, 0); 1712 1713 WREG32(SQ_CONFIG, 0); 1714 1715 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1716 FORCE_EOV_MAX_REZ_CNT(255))); 1717 1718 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1719 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1720 1721 WREG32(VGT_GS_VERTEX_REUSE, 16); 1722 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1723 1724 WREG32(CB_PERFCOUNTER0_SELECT0, 0); 1725 WREG32(CB_PERFCOUNTER0_SELECT1, 0); 1726 WREG32(CB_PERFCOUNTER1_SELECT0, 0); 1727 WREG32(CB_PERFCOUNTER1_SELECT1, 0); 1728 WREG32(CB_PERFCOUNTER2_SELECT0, 0); 1729 WREG32(CB_PERFCOUNTER2_SELECT1, 0); 1730 WREG32(CB_PERFCOUNTER3_SELECT0, 0); 1731 WREG32(CB_PERFCOUNTER3_SELECT1, 0); 1732 1733 tmp = RREG32(HDP_MISC_CNTL); 1734 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 1735 WREG32(HDP_MISC_CNTL, tmp); 1736 1737 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1738 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1739 1740 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1741 1742 udelay(50); 1743 } 1744 1745 /* 1746 * GPU scratch registers helpers function. 1747 */ 1748 static void si_scratch_init(struct radeon_device *rdev) 1749 { 1750 int i; 1751 1752 rdev->scratch.num_reg = 7; 1753 rdev->scratch.reg_base = SCRATCH_REG0; 1754 for (i = 0; i < rdev->scratch.num_reg; i++) { 1755 rdev->scratch.free[i] = true; 1756 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 1757 } 1758 } 1759 1760 void si_fence_ring_emit(struct radeon_device *rdev, 1761 struct radeon_fence *fence) 1762 { 1763 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1764 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1765 1766 /* flush read cache over gart */ 1767 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1768 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1769 radeon_ring_write(ring, 0); 1770 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1771 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1772 PACKET3_TC_ACTION_ENA | 1773 PACKET3_SH_KCACHE_ACTION_ENA | 1774 PACKET3_SH_ICACHE_ACTION_ENA); 1775 radeon_ring_write(ring, 0xFFFFFFFF); 1776 radeon_ring_write(ring, 0); 1777 radeon_ring_write(ring, 10); /* poll interval */ 1778 /* EVENT_WRITE_EOP - flush caches, send int */ 1779 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1780 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1781 radeon_ring_write(ring, addr & 0xffffffff); 1782 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1783 radeon_ring_write(ring, fence->seq); 1784 radeon_ring_write(ring, 0); 1785 } 1786 1787 /* 1788 * IB stuff 1789 */ 1790 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1791 { 1792 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1793 u32 header; 1794 1795 if (ib->is_const_ib) { 1796 /* set switch buffer packet before const IB */ 1797 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1798 radeon_ring_write(ring, 0); 1799 1800 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1801 } else { 1802 u32 next_rptr; 1803 if (ring->rptr_save_reg) { 1804 next_rptr = ring->wptr + 3 + 4 + 8; 1805 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1806 radeon_ring_write(ring, ((ring->rptr_save_reg - 1807 PACKET3_SET_CONFIG_REG_START) >> 2)); 1808 radeon_ring_write(ring, next_rptr); 1809 } else if (rdev->wb.enabled) { 1810 next_rptr = ring->wptr + 5 + 4 + 8; 1811 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1812 radeon_ring_write(ring, (1 << 8)); 1813 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 1814 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 1815 radeon_ring_write(ring, next_rptr); 1816 } 1817 1818 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1819 } 1820 1821 radeon_ring_write(ring, header); 1822 radeon_ring_write(ring, 1823 #ifdef __BIG_ENDIAN 1824 (2 << 0) | 1825 #endif 1826 (ib->gpu_addr & 0xFFFFFFFC)); 1827 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1828 radeon_ring_write(ring, ib->length_dw | 1829 (ib->vm ? (ib->vm->id << 24) : 0)); 1830 1831 if (!ib->is_const_ib) { 1832 /* flush read cache over gart for this vmid */ 1833 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1834 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1835 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); 1836 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1837 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1838 PACKET3_TC_ACTION_ENA | 1839 PACKET3_SH_KCACHE_ACTION_ENA | 1840 PACKET3_SH_ICACHE_ACTION_ENA); 1841 radeon_ring_write(ring, 0xFFFFFFFF); 1842 radeon_ring_write(ring, 0); 1843 radeon_ring_write(ring, 10); /* poll interval */ 1844 } 1845 } 1846 1847 /* 1848 * CP. 1849 */ 1850 static void si_cp_enable(struct radeon_device *rdev, bool enable) 1851 { 1852 if (enable) 1853 WREG32(CP_ME_CNTL, 0); 1854 else { 1855 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1856 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); 1857 WREG32(SCRATCH_UMSK, 0); 1858 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1859 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1860 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1861 } 1862 udelay(50); 1863 } 1864 1865 static int si_cp_load_microcode(struct radeon_device *rdev) 1866 { 1867 const __be32 *fw_data; 1868 int i; 1869 1870 if (!rdev->me_fw || !rdev->pfp_fw) 1871 return -EINVAL; 1872 1873 si_cp_enable(rdev, false); 1874 1875 /* PFP */ 1876 fw_data = (const __be32 *)rdev->pfp_fw; 1877 WREG32(CP_PFP_UCODE_ADDR, 0); 1878 for (i = 0; i < SI_PFP_UCODE_SIZE; i++) 1879 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1880 WREG32(CP_PFP_UCODE_ADDR, 0); 1881 1882 /* CE */ 1883 fw_data = (const __be32 *)rdev->ce_fw; 1884 WREG32(CP_CE_UCODE_ADDR, 0); 1885 for (i = 0; i < SI_CE_UCODE_SIZE; i++) 1886 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); 1887 WREG32(CP_CE_UCODE_ADDR, 0); 1888 1889 /* ME */ 1890 fw_data = (const __be32 *)rdev->me_fw; 1891 WREG32(CP_ME_RAM_WADDR, 0); 1892 for (i = 0; i < SI_PM4_UCODE_SIZE; i++) 1893 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1894 WREG32(CP_ME_RAM_WADDR, 0); 1895 1896 WREG32(CP_PFP_UCODE_ADDR, 0); 1897 WREG32(CP_CE_UCODE_ADDR, 0); 1898 WREG32(CP_ME_RAM_WADDR, 0); 1899 WREG32(CP_ME_RAM_RADDR, 0); 1900 return 0; 1901 } 1902 1903 static int si_cp_start(struct radeon_device *rdev) 1904 { 1905 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1906 int r, i; 1907 1908 r = radeon_ring_lock(rdev, ring, 7 + 4); 1909 if (r) { 1910 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1911 return r; 1912 } 1913 /* init the CP */ 1914 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1915 radeon_ring_write(ring, 0x1); 1916 radeon_ring_write(ring, 0x0); 1917 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); 1918 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1919 radeon_ring_write(ring, 0); 1920 radeon_ring_write(ring, 0); 1921 1922 /* init the CE partitions */ 1923 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 1924 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 1925 radeon_ring_write(ring, 0xc000); 1926 radeon_ring_write(ring, 0xe000); 1927 radeon_ring_unlock_commit(rdev, ring); 1928 1929 si_cp_enable(rdev, true); 1930 1931 r = radeon_ring_lock(rdev, ring, si_default_size + 10); 1932 if (r) { 1933 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1934 return r; 1935 } 1936 1937 /* setup clear context state */ 1938 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1939 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1940 1941 for (i = 0; i < si_default_size; i++) 1942 radeon_ring_write(ring, si_default_state[i]); 1943 1944 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1945 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1946 1947 /* set clear context state */ 1948 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1949 radeon_ring_write(ring, 0); 1950 1951 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 1952 radeon_ring_write(ring, 0x00000316); 1953 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1954 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 1955 1956 radeon_ring_unlock_commit(rdev, ring); 1957 1958 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { 1959 ring = &rdev->ring[i]; 1960 r = radeon_ring_lock(rdev, ring, 2); 1961 1962 /* clear the compute context state */ 1963 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); 1964 radeon_ring_write(ring, 0); 1965 1966 radeon_ring_unlock_commit(rdev, ring); 1967 } 1968 1969 return 0; 1970 } 1971 1972 static void si_cp_fini(struct radeon_device *rdev) 1973 { 1974 struct radeon_ring *ring; 1975 si_cp_enable(rdev, false); 1976 1977 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1978 radeon_ring_fini(rdev, ring); 1979 radeon_scratch_free(rdev, ring->rptr_save_reg); 1980 1981 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 1982 radeon_ring_fini(rdev, ring); 1983 radeon_scratch_free(rdev, ring->rptr_save_reg); 1984 1985 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 1986 radeon_ring_fini(rdev, ring); 1987 radeon_scratch_free(rdev, ring->rptr_save_reg); 1988 } 1989 1990 static int si_cp_resume(struct radeon_device *rdev) 1991 { 1992 struct radeon_ring *ring; 1993 u32 tmp; 1994 u32 rb_bufsz; 1995 int r; 1996 1997 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 1998 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 1999 SOFT_RESET_PA | 2000 SOFT_RESET_VGT | 2001 SOFT_RESET_SPI | 2002 SOFT_RESET_SX)); 2003 RREG32(GRBM_SOFT_RESET); 2004 mdelay(15); 2005 WREG32(GRBM_SOFT_RESET, 0); 2006 RREG32(GRBM_SOFT_RESET); 2007 2008 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2009 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2010 2011 /* Set the write pointer delay */ 2012 WREG32(CP_RB_WPTR_DELAY, 0); 2013 2014 WREG32(CP_DEBUG, 0); 2015 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2016 2017 /* ring 0 - compute and gfx */ 2018 /* Set ring buffer size */ 2019 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2020 rb_bufsz = drm_order(ring->ring_size / 8); 2021 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2022 #ifdef __BIG_ENDIAN 2023 tmp |= BUF_SWAP_32BIT; 2024 #endif 2025 WREG32(CP_RB0_CNTL, tmp); 2026 2027 /* Initialize the ring buffer's read and write pointers */ 2028 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 2029 ring->wptr = 0; 2030 WREG32(CP_RB0_WPTR, ring->wptr); 2031 2032 /* set the wb address whether it's enabled or not */ 2033 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 2034 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2035 2036 if (rdev->wb.enabled) 2037 WREG32(SCRATCH_UMSK, 0xff); 2038 else { 2039 tmp |= RB_NO_UPDATE; 2040 WREG32(SCRATCH_UMSK, 0); 2041 } 2042 2043 mdelay(1); 2044 WREG32(CP_RB0_CNTL, tmp); 2045 2046 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); 2047 2048 ring->rptr = RREG32(CP_RB0_RPTR); 2049 2050 /* ring1 - compute only */ 2051 /* Set ring buffer size */ 2052 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 2053 rb_bufsz = drm_order(ring->ring_size / 8); 2054 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2055 #ifdef __BIG_ENDIAN 2056 tmp |= BUF_SWAP_32BIT; 2057 #endif 2058 WREG32(CP_RB1_CNTL, tmp); 2059 2060 /* Initialize the ring buffer's read and write pointers */ 2061 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 2062 ring->wptr = 0; 2063 WREG32(CP_RB1_WPTR, ring->wptr); 2064 2065 /* set the wb address whether it's enabled or not */ 2066 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); 2067 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); 2068 2069 mdelay(1); 2070 WREG32(CP_RB1_CNTL, tmp); 2071 2072 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); 2073 2074 ring->rptr = RREG32(CP_RB1_RPTR); 2075 2076 /* ring2 - compute only */ 2077 /* Set ring buffer size */ 2078 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 2079 rb_bufsz = drm_order(ring->ring_size / 8); 2080 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2081 #ifdef __BIG_ENDIAN 2082 tmp |= BUF_SWAP_32BIT; 2083 #endif 2084 WREG32(CP_RB2_CNTL, tmp); 2085 2086 /* Initialize the ring buffer's read and write pointers */ 2087 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 2088 ring->wptr = 0; 2089 WREG32(CP_RB2_WPTR, ring->wptr); 2090 2091 /* set the wb address whether it's enabled or not */ 2092 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); 2093 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); 2094 2095 mdelay(1); 2096 WREG32(CP_RB2_CNTL, tmp); 2097 2098 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); 2099 2100 ring->rptr = RREG32(CP_RB2_RPTR); 2101 2102 /* start the rings */ 2103 si_cp_start(rdev); 2104 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 2105 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; 2106 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true; 2107 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 2108 if (r) { 2109 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2110 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 2111 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 2112 return r; 2113 } 2114 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); 2115 if (r) { 2116 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 2117 } 2118 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); 2119 if (r) { 2120 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 2121 } 2122 2123 return 0; 2124 } 2125 2126 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2127 { 2128 u32 srbm_status; 2129 u32 grbm_status, grbm_status2; 2130 u32 grbm_status_se0, grbm_status_se1; 2131 2132 srbm_status = RREG32(SRBM_STATUS); 2133 grbm_status = RREG32(GRBM_STATUS); 2134 grbm_status2 = RREG32(GRBM_STATUS2); 2135 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 2136 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 2137 if (!(grbm_status & GUI_ACTIVE)) { 2138 radeon_ring_lockup_update(ring); 2139 return false; 2140 } 2141 /* force CP activities */ 2142 radeon_ring_force_activity(rdev, ring); 2143 return radeon_ring_test_lockup(rdev, ring); 2144 } 2145 2146 static void si_gpu_soft_reset_gfx(struct radeon_device *rdev) 2147 { 2148 u32 grbm_reset = 0; 2149 2150 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2151 return; 2152 2153 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2154 RREG32(GRBM_STATUS)); 2155 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", 2156 RREG32(GRBM_STATUS2)); 2157 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2158 RREG32(GRBM_STATUS_SE0)); 2159 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2160 RREG32(GRBM_STATUS_SE1)); 2161 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2162 RREG32(SRBM_STATUS)); 2163 2164 /* Disable CP parsing/prefetching */ 2165 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); 2166 2167 /* reset all the gfx blocks */ 2168 grbm_reset = (SOFT_RESET_CP | 2169 SOFT_RESET_CB | 2170 SOFT_RESET_DB | 2171 SOFT_RESET_GDS | 2172 SOFT_RESET_PA | 2173 SOFT_RESET_SC | 2174 SOFT_RESET_BCI | 2175 SOFT_RESET_SPI | 2176 SOFT_RESET_SX | 2177 SOFT_RESET_TC | 2178 SOFT_RESET_TA | 2179 SOFT_RESET_VGT | 2180 SOFT_RESET_IA); 2181 2182 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); 2183 WREG32(GRBM_SOFT_RESET, grbm_reset); 2184 (void)RREG32(GRBM_SOFT_RESET); 2185 udelay(50); 2186 WREG32(GRBM_SOFT_RESET, 0); 2187 (void)RREG32(GRBM_SOFT_RESET); 2188 2189 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2190 RREG32(GRBM_STATUS)); 2191 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", 2192 RREG32(GRBM_STATUS2)); 2193 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2194 RREG32(GRBM_STATUS_SE0)); 2195 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2196 RREG32(GRBM_STATUS_SE1)); 2197 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2198 RREG32(SRBM_STATUS)); 2199 } 2200 2201 static void si_gpu_soft_reset_dma(struct radeon_device *rdev) 2202 { 2203 u32 tmp; 2204 2205 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2206 return; 2207 2208 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", 2209 RREG32(DMA_STATUS_REG)); 2210 2211 /* dma0 */ 2212 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 2213 tmp &= ~DMA_RB_ENABLE; 2214 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); 2215 2216 /* dma1 */ 2217 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 2218 tmp &= ~DMA_RB_ENABLE; 2219 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); 2220 2221 /* Reset dma */ 2222 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); 2223 RREG32(SRBM_SOFT_RESET); 2224 udelay(50); 2225 WREG32(SRBM_SOFT_RESET, 0); 2226 2227 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", 2228 RREG32(DMA_STATUS_REG)); 2229 } 2230 2231 static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 2232 { 2233 struct evergreen_mc_save save; 2234 2235 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2236 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE); 2237 2238 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2239 reset_mask &= ~RADEON_RESET_DMA; 2240 2241 if (reset_mask == 0) 2242 return 0; 2243 2244 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 2245 2246 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 2247 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 2248 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 2249 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 2250 2251 evergreen_mc_stop(rdev, &save); 2252 if (radeon_mc_wait_for_idle(rdev)) { 2253 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2254 } 2255 2256 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 2257 si_gpu_soft_reset_gfx(rdev); 2258 2259 if (reset_mask & RADEON_RESET_DMA) 2260 si_gpu_soft_reset_dma(rdev); 2261 2262 /* Wait a little for things to settle down */ 2263 udelay(50); 2264 2265 evergreen_mc_resume(rdev, &save); 2266 return 0; 2267 } 2268 2269 int si_asic_reset(struct radeon_device *rdev) 2270 { 2271 return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 2272 RADEON_RESET_COMPUTE | 2273 RADEON_RESET_DMA)); 2274 } 2275 2276 /* MC */ 2277 static void si_mc_program(struct radeon_device *rdev) 2278 { 2279 struct evergreen_mc_save save; 2280 u32 tmp; 2281 int i, j; 2282 2283 /* Initialize HDP */ 2284 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2285 WREG32((0x2c14 + j), 0x00000000); 2286 WREG32((0x2c18 + j), 0x00000000); 2287 WREG32((0x2c1c + j), 0x00000000); 2288 WREG32((0x2c20 + j), 0x00000000); 2289 WREG32((0x2c24 + j), 0x00000000); 2290 } 2291 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 2292 2293 evergreen_mc_stop(rdev, &save); 2294 if (radeon_mc_wait_for_idle(rdev)) { 2295 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2296 } 2297 /* Lockout access through VGA aperture*/ 2298 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 2299 /* Update configuration */ 2300 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 2301 rdev->mc.vram_start >> 12); 2302 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 2303 rdev->mc.vram_end >> 12); 2304 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 2305 rdev->vram_scratch.gpu_addr >> 12); 2306 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 2307 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 2308 WREG32(MC_VM_FB_LOCATION, tmp); 2309 /* XXX double check these! */ 2310 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 2311 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 2312 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 2313 WREG32(MC_VM_AGP_BASE, 0); 2314 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 2315 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 2316 if (radeon_mc_wait_for_idle(rdev)) { 2317 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2318 } 2319 evergreen_mc_resume(rdev, &save); 2320 /* we need to own VRAM, so turn off the VGA renderer here 2321 * to stop it overwriting our objects */ 2322 rv515_vga_render_disable(rdev); 2323 } 2324 2325 /* SI MC address space is 40 bits */ 2326 static void si_vram_location(struct radeon_device *rdev, 2327 struct radeon_mc *mc, u64 base) 2328 { 2329 mc->vram_start = base; 2330 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) { 2331 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 2332 mc->real_vram_size = mc->aper_size; 2333 mc->mc_vram_size = mc->aper_size; 2334 } 2335 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 2336 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 2337 mc->mc_vram_size >> 20, mc->vram_start, 2338 mc->vram_end, mc->real_vram_size >> 20); 2339 } 2340 2341 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 2342 { 2343 u64 size_af, size_bf; 2344 2345 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 2346 size_bf = mc->vram_start & ~mc->gtt_base_align; 2347 if (size_bf > size_af) { 2348 if (mc->gtt_size > size_bf) { 2349 dev_warn(rdev->dev, "limiting GTT\n"); 2350 mc->gtt_size = size_bf; 2351 } 2352 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 2353 } else { 2354 if (mc->gtt_size > size_af) { 2355 dev_warn(rdev->dev, "limiting GTT\n"); 2356 mc->gtt_size = size_af; 2357 } 2358 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 2359 } 2360 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 2361 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 2362 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 2363 } 2364 2365 static void si_vram_gtt_location(struct radeon_device *rdev, 2366 struct radeon_mc *mc) 2367 { 2368 if (mc->mc_vram_size > 0xFFC0000000ULL) { 2369 /* leave room for at least 1024M GTT */ 2370 dev_warn(rdev->dev, "limiting VRAM\n"); 2371 mc->real_vram_size = 0xFFC0000000ULL; 2372 mc->mc_vram_size = 0xFFC0000000ULL; 2373 } 2374 si_vram_location(rdev, &rdev->mc, 0); 2375 rdev->mc.gtt_base_align = 0; 2376 si_gtt_location(rdev, mc); 2377 } 2378 2379 static int si_mc_init(struct radeon_device *rdev) 2380 { 2381 u32 tmp; 2382 int chansize, numchan; 2383 2384 /* Get VRAM informations */ 2385 rdev->mc.vram_is_ddr = true; 2386 tmp = RREG32(MC_ARB_RAMCFG); 2387 if (tmp & CHANSIZE_OVERRIDE) { 2388 chansize = 16; 2389 } else if (tmp & CHANSIZE_MASK) { 2390 chansize = 64; 2391 } else { 2392 chansize = 32; 2393 } 2394 tmp = RREG32(MC_SHARED_CHMAP); 2395 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 2396 case 0: 2397 default: 2398 numchan = 1; 2399 break; 2400 case 1: 2401 numchan = 2; 2402 break; 2403 case 2: 2404 numchan = 4; 2405 break; 2406 case 3: 2407 numchan = 8; 2408 break; 2409 case 4: 2410 numchan = 3; 2411 break; 2412 case 5: 2413 numchan = 6; 2414 break; 2415 case 6: 2416 numchan = 10; 2417 break; 2418 case 7: 2419 numchan = 12; 2420 break; 2421 case 8: 2422 numchan = 16; 2423 break; 2424 } 2425 rdev->mc.vram_width = numchan * chansize; 2426 /* Could aper size report 0 ? */ 2427 rdev->mc.aper_base = rdev->fb_aper_offset; 2428 rdev->mc.aper_size = rdev->fb_aper_size; 2429 /* size in MB on si */ 2430 tmp = RREG32(CONFIG_MEMSIZE); 2431 /* some boards may have garbage in the upper 16 bits */ 2432 if (tmp & 0xffff0000) { 2433 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); 2434 if (tmp & 0xffff) 2435 tmp &= 0xffff; 2436 } 2437 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL; 2438 rdev->mc.real_vram_size = rdev->mc.mc_vram_size; 2439 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2440 si_vram_gtt_location(rdev, &rdev->mc); 2441 radeon_update_bandwidth_info(rdev); 2442 2443 return 0; 2444 } 2445 2446 /* 2447 * GART 2448 */ 2449 void si_pcie_gart_tlb_flush(struct radeon_device *rdev) 2450 { 2451 /* flush hdp cache */ 2452 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 2453 2454 /* bits 0-15 are the VM contexts0-15 */ 2455 WREG32(VM_INVALIDATE_REQUEST, 1); 2456 } 2457 2458 static int si_pcie_gart_enable(struct radeon_device *rdev) 2459 { 2460 int r, i; 2461 2462 if (rdev->gart.robj == NULL) { 2463 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 2464 return -EINVAL; 2465 } 2466 r = radeon_gart_table_vram_pin(rdev); 2467 if (r) 2468 return r; 2469 radeon_gart_restore(rdev); 2470 /* Setup TLB control */ 2471 WREG32(MC_VM_MX_L1_TLB_CNTL, 2472 (0xA << 7) | 2473 ENABLE_L1_TLB | 2474 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 2475 ENABLE_ADVANCED_DRIVER_MODEL | 2476 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 2477 /* Setup L2 cache */ 2478 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 2479 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2480 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 2481 EFFECTIVE_L2_QUEUE_SIZE(7) | 2482 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 2483 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 2484 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 2485 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 2486 /* setup context0 */ 2487 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 2488 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 2489 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 2490 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 2491 (u32)(rdev->dummy_page.addr >> 12)); 2492 WREG32(VM_CONTEXT0_CNTL2, 0); 2493 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 2494 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); 2495 2496 WREG32(0x15D4, 0); 2497 WREG32(0x15D8, 0); 2498 WREG32(0x15DC, 0); 2499 2500 /* empty context1-15 */ 2501 /* set vm size, must be a multiple of 4 */ 2502 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 2503 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); 2504 /* Assign the pt base to something valid for now; the pts used for 2505 * the VMs are determined by the application and setup and assigned 2506 * on the fly in the vm part of radeon_gart.c 2507 */ 2508 for (i = 1; i < 16; i++) { 2509 if (i < 8) 2510 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 2511 rdev->gart.table_addr >> 12); 2512 else 2513 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), 2514 rdev->gart.table_addr >> 12); 2515 } 2516 2517 /* enable context1-15 */ 2518 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 2519 (u32)(rdev->dummy_page.addr >> 12)); 2520 WREG32(VM_CONTEXT1_CNTL2, 4); 2521 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 2522 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2523 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 2524 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2525 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 2526 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 2527 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 2528 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 2529 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 2530 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 2531 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 2532 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2533 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 2534 2535 si_pcie_gart_tlb_flush(rdev); 2536 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 2537 (unsigned)(rdev->mc.gtt_size >> 20), 2538 (unsigned long long)rdev->gart.table_addr); 2539 rdev->gart.ready = true; 2540 return 0; 2541 } 2542 2543 static void si_pcie_gart_disable(struct radeon_device *rdev) 2544 { 2545 /* Disable all tables */ 2546 WREG32(VM_CONTEXT0_CNTL, 0); 2547 WREG32(VM_CONTEXT1_CNTL, 0); 2548 /* Setup TLB control */ 2549 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | 2550 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 2551 /* Setup L2 cache */ 2552 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2553 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 2554 EFFECTIVE_L2_QUEUE_SIZE(7) | 2555 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 2556 WREG32(VM_L2_CNTL2, 0); 2557 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 2558 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 2559 radeon_gart_table_vram_unpin(rdev); 2560 } 2561 2562 static void si_pcie_gart_fini(struct radeon_device *rdev) 2563 { 2564 si_pcie_gart_disable(rdev); 2565 radeon_gart_table_vram_free(rdev); 2566 radeon_gart_fini(rdev); 2567 } 2568 2569 /* vm parser */ 2570 static bool si_vm_reg_valid(u32 reg) 2571 { 2572 /* context regs are fine */ 2573 if (reg >= 0x28000) 2574 return true; 2575 2576 /* check config regs */ 2577 switch (reg) { 2578 case GRBM_GFX_INDEX: 2579 case CP_STRMOUT_CNTL: 2580 case VGT_VTX_VECT_EJECT_REG: 2581 case VGT_CACHE_INVALIDATION: 2582 case VGT_ESGS_RING_SIZE: 2583 case VGT_GSVS_RING_SIZE: 2584 case VGT_GS_VERTEX_REUSE: 2585 case VGT_PRIMITIVE_TYPE: 2586 case VGT_INDEX_TYPE: 2587 case VGT_NUM_INDICES: 2588 case VGT_NUM_INSTANCES: 2589 case VGT_TF_RING_SIZE: 2590 case VGT_HS_OFFCHIP_PARAM: 2591 case VGT_TF_MEMORY_BASE: 2592 case PA_CL_ENHANCE: 2593 case PA_SU_LINE_STIPPLE_VALUE: 2594 case PA_SC_LINE_STIPPLE_STATE: 2595 case PA_SC_ENHANCE: 2596 case SQC_CACHES: 2597 case SPI_STATIC_THREAD_MGMT_1: 2598 case SPI_STATIC_THREAD_MGMT_2: 2599 case SPI_STATIC_THREAD_MGMT_3: 2600 case SPI_PS_MAX_WAVE_ID: 2601 case SPI_CONFIG_CNTL: 2602 case SPI_CONFIG_CNTL_1: 2603 case TA_CNTL_AUX: 2604 return true; 2605 default: 2606 DRM_ERROR("Invalid register 0x%x in CS\n", reg); 2607 return false; 2608 } 2609 } 2610 2611 static int si_vm_packet3_ce_check(struct radeon_device *rdev, 2612 u32 *ib, struct radeon_cs_packet *pkt) 2613 { 2614 switch (pkt->opcode) { 2615 case PACKET3_NOP: 2616 case PACKET3_SET_BASE: 2617 case PACKET3_SET_CE_DE_COUNTERS: 2618 case PACKET3_LOAD_CONST_RAM: 2619 case PACKET3_WRITE_CONST_RAM: 2620 case PACKET3_WRITE_CONST_RAM_OFFSET: 2621 case PACKET3_DUMP_CONST_RAM: 2622 case PACKET3_INCREMENT_CE_COUNTER: 2623 case PACKET3_WAIT_ON_DE_COUNTER: 2624 case PACKET3_CE_WRITE: 2625 break; 2626 default: 2627 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode); 2628 return -EINVAL; 2629 } 2630 return 0; 2631 } 2632 2633 static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx) 2634 { 2635 u32 start_reg, reg, i; 2636 u32 command = ib[idx + 4]; 2637 u32 info = ib[idx + 1]; 2638 u32 idx_value = ib[idx]; 2639 if (command & PACKET3_CP_DMA_CMD_SAS) { 2640 /* src address space is register */ 2641 if (((info & 0x60000000) >> 29) == 0) { 2642 start_reg = idx_value << 2; 2643 if (command & PACKET3_CP_DMA_CMD_SAIC) { 2644 reg = start_reg; 2645 if (!si_vm_reg_valid(reg)) { 2646 DRM_ERROR("CP DMA Bad SRC register\n"); 2647 return -EINVAL; 2648 } 2649 } else { 2650 for (i = 0; i < (command & 0x1fffff); i++) { 2651 reg = start_reg + (4 * i); 2652 if (!si_vm_reg_valid(reg)) { 2653 DRM_ERROR("CP DMA Bad SRC register\n"); 2654 return -EINVAL; 2655 } 2656 } 2657 } 2658 } 2659 } 2660 if (command & PACKET3_CP_DMA_CMD_DAS) { 2661 /* dst address space is register */ 2662 if (((info & 0x00300000) >> 20) == 0) { 2663 start_reg = ib[idx + 2]; 2664 if (command & PACKET3_CP_DMA_CMD_DAIC) { 2665 reg = start_reg; 2666 if (!si_vm_reg_valid(reg)) { 2667 DRM_ERROR("CP DMA Bad DST register\n"); 2668 return -EINVAL; 2669 } 2670 } else { 2671 for (i = 0; i < (command & 0x1fffff); i++) { 2672 reg = start_reg + (4 * i); 2673 if (!si_vm_reg_valid(reg)) { 2674 DRM_ERROR("CP DMA Bad DST register\n"); 2675 return -EINVAL; 2676 } 2677 } 2678 } 2679 } 2680 } 2681 return 0; 2682 } 2683 2684 static int si_vm_packet3_gfx_check(struct radeon_device *rdev, 2685 u32 *ib, struct radeon_cs_packet *pkt) 2686 { 2687 int r; 2688 u32 idx = pkt->idx + 1; 2689 u32 idx_value = ib[idx]; 2690 u32 start_reg, end_reg, reg, i; 2691 2692 switch (pkt->opcode) { 2693 case PACKET3_NOP: 2694 case PACKET3_SET_BASE: 2695 case PACKET3_CLEAR_STATE: 2696 case PACKET3_INDEX_BUFFER_SIZE: 2697 case PACKET3_DISPATCH_DIRECT: 2698 case PACKET3_DISPATCH_INDIRECT: 2699 case PACKET3_ALLOC_GDS: 2700 case PACKET3_WRITE_GDS_RAM: 2701 case PACKET3_ATOMIC_GDS: 2702 case PACKET3_ATOMIC: 2703 case PACKET3_OCCLUSION_QUERY: 2704 case PACKET3_SET_PREDICATION: 2705 case PACKET3_COND_EXEC: 2706 case PACKET3_PRED_EXEC: 2707 case PACKET3_DRAW_INDIRECT: 2708 case PACKET3_DRAW_INDEX_INDIRECT: 2709 case PACKET3_INDEX_BASE: 2710 case PACKET3_DRAW_INDEX_2: 2711 case PACKET3_CONTEXT_CONTROL: 2712 case PACKET3_INDEX_TYPE: 2713 case PACKET3_DRAW_INDIRECT_MULTI: 2714 case PACKET3_DRAW_INDEX_AUTO: 2715 case PACKET3_DRAW_INDEX_IMMD: 2716 case PACKET3_NUM_INSTANCES: 2717 case PACKET3_DRAW_INDEX_MULTI_AUTO: 2718 case PACKET3_STRMOUT_BUFFER_UPDATE: 2719 case PACKET3_DRAW_INDEX_OFFSET_2: 2720 case PACKET3_DRAW_INDEX_MULTI_ELEMENT: 2721 case PACKET3_DRAW_INDEX_INDIRECT_MULTI: 2722 case PACKET3_MPEG_INDEX: 2723 case PACKET3_WAIT_REG_MEM: 2724 case PACKET3_MEM_WRITE: 2725 case PACKET3_PFP_SYNC_ME: 2726 case PACKET3_SURFACE_SYNC: 2727 case PACKET3_EVENT_WRITE: 2728 case PACKET3_EVENT_WRITE_EOP: 2729 case PACKET3_EVENT_WRITE_EOS: 2730 case PACKET3_SET_CONTEXT_REG: 2731 case PACKET3_SET_CONTEXT_REG_INDIRECT: 2732 case PACKET3_SET_SH_REG: 2733 case PACKET3_SET_SH_REG_OFFSET: 2734 case PACKET3_INCREMENT_DE_COUNTER: 2735 case PACKET3_WAIT_ON_CE_COUNTER: 2736 case PACKET3_WAIT_ON_AVAIL_BUFFER: 2737 case PACKET3_ME_WRITE: 2738 break; 2739 case PACKET3_COPY_DATA: 2740 if ((idx_value & 0xf00) == 0) { 2741 reg = ib[idx + 3] * 4; 2742 if (!si_vm_reg_valid(reg)) 2743 return -EINVAL; 2744 } 2745 break; 2746 case PACKET3_WRITE_DATA: 2747 if ((idx_value & 0xf00) == 0) { 2748 start_reg = ib[idx + 1] * 4; 2749 if (idx_value & 0x10000) { 2750 if (!si_vm_reg_valid(start_reg)) 2751 return -EINVAL; 2752 } else { 2753 for (i = 0; i < (pkt->count - 2); i++) { 2754 reg = start_reg + (4 * i); 2755 if (!si_vm_reg_valid(reg)) 2756 return -EINVAL; 2757 } 2758 } 2759 } 2760 break; 2761 case PACKET3_COND_WRITE: 2762 if (idx_value & 0x100) { 2763 reg = ib[idx + 5] * 4; 2764 if (!si_vm_reg_valid(reg)) 2765 return -EINVAL; 2766 } 2767 break; 2768 case PACKET3_COPY_DW: 2769 if (idx_value & 0x2) { 2770 reg = ib[idx + 3] * 4; 2771 if (!si_vm_reg_valid(reg)) 2772 return -EINVAL; 2773 } 2774 break; 2775 case PACKET3_SET_CONFIG_REG: 2776 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; 2777 end_reg = 4 * pkt->count + start_reg - 4; 2778 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 2779 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2780 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2781 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2782 return -EINVAL; 2783 } 2784 for (i = 0; i < pkt->count; i++) { 2785 reg = start_reg + (4 * i); 2786 if (!si_vm_reg_valid(reg)) 2787 return -EINVAL; 2788 } 2789 break; 2790 case PACKET3_CP_DMA: 2791 r = si_vm_packet3_cp_dma_check(ib, idx); 2792 if (r) 2793 return r; 2794 break; 2795 default: 2796 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); 2797 return -EINVAL; 2798 } 2799 return 0; 2800 } 2801 2802 static int si_vm_packet3_compute_check(struct radeon_device *rdev, 2803 u32 *ib, struct radeon_cs_packet *pkt) 2804 { 2805 int r; 2806 u32 idx = pkt->idx + 1; 2807 u32 idx_value = ib[idx]; 2808 u32 start_reg, reg, i; 2809 2810 switch (pkt->opcode) { 2811 case PACKET3_NOP: 2812 case PACKET3_SET_BASE: 2813 case PACKET3_CLEAR_STATE: 2814 case PACKET3_DISPATCH_DIRECT: 2815 case PACKET3_DISPATCH_INDIRECT: 2816 case PACKET3_ALLOC_GDS: 2817 case PACKET3_WRITE_GDS_RAM: 2818 case PACKET3_ATOMIC_GDS: 2819 case PACKET3_ATOMIC: 2820 case PACKET3_OCCLUSION_QUERY: 2821 case PACKET3_SET_PREDICATION: 2822 case PACKET3_COND_EXEC: 2823 case PACKET3_PRED_EXEC: 2824 case PACKET3_CONTEXT_CONTROL: 2825 case PACKET3_STRMOUT_BUFFER_UPDATE: 2826 case PACKET3_WAIT_REG_MEM: 2827 case PACKET3_MEM_WRITE: 2828 case PACKET3_PFP_SYNC_ME: 2829 case PACKET3_SURFACE_SYNC: 2830 case PACKET3_EVENT_WRITE: 2831 case PACKET3_EVENT_WRITE_EOP: 2832 case PACKET3_EVENT_WRITE_EOS: 2833 case PACKET3_SET_CONTEXT_REG: 2834 case PACKET3_SET_CONTEXT_REG_INDIRECT: 2835 case PACKET3_SET_SH_REG: 2836 case PACKET3_SET_SH_REG_OFFSET: 2837 case PACKET3_INCREMENT_DE_COUNTER: 2838 case PACKET3_WAIT_ON_CE_COUNTER: 2839 case PACKET3_WAIT_ON_AVAIL_BUFFER: 2840 case PACKET3_ME_WRITE: 2841 break; 2842 case PACKET3_COPY_DATA: 2843 if ((idx_value & 0xf00) == 0) { 2844 reg = ib[idx + 3] * 4; 2845 if (!si_vm_reg_valid(reg)) 2846 return -EINVAL; 2847 } 2848 break; 2849 case PACKET3_WRITE_DATA: 2850 if ((idx_value & 0xf00) == 0) { 2851 start_reg = ib[idx + 1] * 4; 2852 if (idx_value & 0x10000) { 2853 if (!si_vm_reg_valid(start_reg)) 2854 return -EINVAL; 2855 } else { 2856 for (i = 0; i < (pkt->count - 2); i++) { 2857 reg = start_reg + (4 * i); 2858 if (!si_vm_reg_valid(reg)) 2859 return -EINVAL; 2860 } 2861 } 2862 } 2863 break; 2864 case PACKET3_COND_WRITE: 2865 if (idx_value & 0x100) { 2866 reg = ib[idx + 5] * 4; 2867 if (!si_vm_reg_valid(reg)) 2868 return -EINVAL; 2869 } 2870 break; 2871 case PACKET3_COPY_DW: 2872 if (idx_value & 0x2) { 2873 reg = ib[idx + 3] * 4; 2874 if (!si_vm_reg_valid(reg)) 2875 return -EINVAL; 2876 } 2877 break; 2878 case PACKET3_CP_DMA: 2879 r = si_vm_packet3_cp_dma_check(ib, idx); 2880 if (r) 2881 return r; 2882 break; 2883 default: 2884 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode); 2885 return -EINVAL; 2886 } 2887 return 0; 2888 } 2889 2890 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 2891 { 2892 int ret = 0; 2893 u32 idx = 0; 2894 struct radeon_cs_packet pkt; 2895 2896 do { 2897 pkt.idx = idx; 2898 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); 2899 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); 2900 pkt.one_reg_wr = 0; 2901 switch (pkt.type) { 2902 case PACKET_TYPE0: 2903 dev_err(rdev->dev, "Packet0 not allowed!\n"); 2904 ret = -EINVAL; 2905 break; 2906 case PACKET_TYPE2: 2907 idx += 1; 2908 break; 2909 case PACKET_TYPE3: 2910 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 2911 if (ib->is_const_ib) 2912 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); 2913 else { 2914 switch (ib->ring) { 2915 case RADEON_RING_TYPE_GFX_INDEX: 2916 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt); 2917 break; 2918 case CAYMAN_RING_TYPE_CP1_INDEX: 2919 case CAYMAN_RING_TYPE_CP2_INDEX: 2920 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt); 2921 break; 2922 default: 2923 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring); 2924 ret = -EINVAL; 2925 break; 2926 } 2927 } 2928 idx += pkt.count + 2; 2929 break; 2930 default: 2931 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); 2932 ret = -EINVAL; 2933 break; 2934 } 2935 if (ret) 2936 break; 2937 } while (idx < ib->length_dw); 2938 2939 return ret; 2940 } 2941 2942 /* 2943 * vm 2944 */ 2945 int si_vm_init(struct radeon_device *rdev) 2946 { 2947 /* number of VMs */ 2948 rdev->vm_manager.nvm = 16; 2949 /* base offset of vram pages */ 2950 rdev->vm_manager.vram_base_offset = 0; 2951 2952 return 0; 2953 } 2954 2955 void si_vm_fini(struct radeon_device *rdev) 2956 { 2957 } 2958 2959 /** 2960 * si_vm_set_page - update the page tables using the CP 2961 * 2962 * @rdev: radeon_device pointer 2963 * @pe: addr of the page entry 2964 * @addr: dst addr to write into pe 2965 * @count: number of page entries to update 2966 * @incr: increase next addr by incr bytes 2967 * @flags: access flags 2968 * 2969 * Update the page tables using the CP (cayman-si). 2970 */ 2971 void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, 2972 uint64_t addr, unsigned count, 2973 uint32_t incr, uint32_t flags) 2974 { 2975 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; 2976 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); 2977 uint64_t value; 2978 unsigned ndw; 2979 2980 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) { 2981 while (count) { 2982 ndw = 2 + count * 2; 2983 if (ndw > 0x3FFE) 2984 ndw = 0x3FFE; 2985 2986 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw)); 2987 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2988 WRITE_DATA_DST_SEL(1))); 2989 radeon_ring_write(ring, pe); 2990 radeon_ring_write(ring, upper_32_bits(pe)); 2991 for (; ndw > 2; ndw -= 2, --count, pe += 8) { 2992 if (flags & RADEON_VM_PAGE_SYSTEM) { 2993 value = radeon_vm_map_gart(rdev, addr); 2994 value &= 0xFFFFFFFFFFFFF000ULL; 2995 } else if (flags & RADEON_VM_PAGE_VALID) { 2996 value = addr; 2997 } else { 2998 value = 0; 2999 } 3000 addr += incr; 3001 value |= r600_flags; 3002 radeon_ring_write(ring, value); 3003 radeon_ring_write(ring, upper_32_bits(value)); 3004 } 3005 } 3006 } else { 3007 /* DMA */ 3008 if (flags & RADEON_VM_PAGE_SYSTEM) { 3009 while (count) { 3010 ndw = count * 2; 3011 if (ndw > 0xFFFFE) 3012 ndw = 0xFFFFE; 3013 3014 /* for non-physically contiguous pages (system) */ 3015 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw)); 3016 radeon_ring_write(ring, pe); 3017 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 3018 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 3019 if (flags & RADEON_VM_PAGE_SYSTEM) { 3020 value = radeon_vm_map_gart(rdev, addr); 3021 value &= 0xFFFFFFFFFFFFF000ULL; 3022 } else if (flags & RADEON_VM_PAGE_VALID) { 3023 value = addr; 3024 } else { 3025 value = 0; 3026 } 3027 addr += incr; 3028 value |= r600_flags; 3029 radeon_ring_write(ring, value); 3030 radeon_ring_write(ring, upper_32_bits(value)); 3031 } 3032 } 3033 } else { 3034 while (count) { 3035 ndw = count * 2; 3036 if (ndw > 0xFFFFE) 3037 ndw = 0xFFFFE; 3038 3039 if (flags & RADEON_VM_PAGE_VALID) 3040 value = addr; 3041 else 3042 value = 0; 3043 /* for physically contiguous pages (vram) */ 3044 radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw)); 3045 radeon_ring_write(ring, pe); /* dst addr */ 3046 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 3047 radeon_ring_write(ring, r600_flags); /* mask */ 3048 radeon_ring_write(ring, 0); 3049 radeon_ring_write(ring, value); /* value */ 3050 radeon_ring_write(ring, upper_32_bits(value)); 3051 radeon_ring_write(ring, incr); /* increment size */ 3052 radeon_ring_write(ring, 0); 3053 pe += ndw * 4; 3054 addr += (ndw / 2) * incr; 3055 count -= ndw / 2; 3056 } 3057 } 3058 } 3059 } 3060 3061 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 3062 { 3063 struct radeon_ring *ring = &rdev->ring[ridx]; 3064 3065 if (vm == NULL) 3066 return; 3067 3068 /* write new base address */ 3069 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3070 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3071 WRITE_DATA_DST_SEL(0))); 3072 3073 if (vm->id < 8) { 3074 radeon_ring_write(ring, 3075 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 3076 } else { 3077 radeon_ring_write(ring, 3078 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); 3079 } 3080 radeon_ring_write(ring, 0); 3081 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 3082 3083 /* flush hdp cache */ 3084 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3085 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3086 WRITE_DATA_DST_SEL(0))); 3087 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); 3088 radeon_ring_write(ring, 0); 3089 radeon_ring_write(ring, 0x1); 3090 3091 /* bits 0-15 are the VM contexts0-15 */ 3092 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3093 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3094 WRITE_DATA_DST_SEL(0))); 3095 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 3096 radeon_ring_write(ring, 0); 3097 radeon_ring_write(ring, 1 << vm->id); 3098 3099 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3100 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3101 radeon_ring_write(ring, 0x0); 3102 } 3103 3104 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 3105 { 3106 struct radeon_ring *ring = &rdev->ring[ridx]; 3107 3108 if (vm == NULL) 3109 return; 3110 3111 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3112 if (vm->id < 8) { 3113 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2)); 3114 } else { 3115 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2)); 3116 } 3117 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 3118 3119 /* flush hdp cache */ 3120 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3121 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); 3122 radeon_ring_write(ring, 1); 3123 3124 /* bits 0-7 are the VM contexts0-7 */ 3125 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3126 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); 3127 radeon_ring_write(ring, 1 << vm->id); 3128 } 3129 3130 /* 3131 * RLC 3132 */ 3133 void si_rlc_fini(struct radeon_device *rdev) 3134 { 3135 int r; 3136 3137 /* save restore block */ 3138 if (rdev->rlc.save_restore_obj) { 3139 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); 3140 if (unlikely(r != 0)) 3141 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); 3142 radeon_bo_unpin(rdev->rlc.save_restore_obj); 3143 radeon_bo_unreserve(rdev->rlc.save_restore_obj); 3144 3145 radeon_bo_unref(&rdev->rlc.save_restore_obj); 3146 rdev->rlc.save_restore_obj = NULL; 3147 } 3148 3149 /* clear state block */ 3150 if (rdev->rlc.clear_state_obj) { 3151 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); 3152 if (unlikely(r != 0)) 3153 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); 3154 radeon_bo_unpin(rdev->rlc.clear_state_obj); 3155 radeon_bo_unreserve(rdev->rlc.clear_state_obj); 3156 3157 radeon_bo_unref(&rdev->rlc.clear_state_obj); 3158 rdev->rlc.clear_state_obj = NULL; 3159 } 3160 } 3161 3162 int si_rlc_init(struct radeon_device *rdev) 3163 { 3164 int r; 3165 3166 /* save restore block */ 3167 if (rdev->rlc.save_restore_obj == NULL) { 3168 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 3169 RADEON_GEM_DOMAIN_VRAM, NULL, 3170 &rdev->rlc.save_restore_obj); 3171 if (r) { 3172 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); 3173 return r; 3174 } 3175 } 3176 3177 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); 3178 if (unlikely(r != 0)) { 3179 si_rlc_fini(rdev); 3180 return r; 3181 } 3182 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, 3183 &rdev->rlc.save_restore_gpu_addr); 3184 radeon_bo_unreserve(rdev->rlc.save_restore_obj); 3185 if (r) { 3186 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); 3187 si_rlc_fini(rdev); 3188 return r; 3189 } 3190 3191 /* clear state block */ 3192 if (rdev->rlc.clear_state_obj == NULL) { 3193 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 3194 RADEON_GEM_DOMAIN_VRAM, NULL, 3195 &rdev->rlc.clear_state_obj); 3196 if (r) { 3197 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); 3198 si_rlc_fini(rdev); 3199 return r; 3200 } 3201 } 3202 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); 3203 if (unlikely(r != 0)) { 3204 si_rlc_fini(rdev); 3205 return r; 3206 } 3207 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, 3208 &rdev->rlc.clear_state_gpu_addr); 3209 radeon_bo_unreserve(rdev->rlc.clear_state_obj); 3210 if (r) { 3211 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); 3212 si_rlc_fini(rdev); 3213 return r; 3214 } 3215 3216 return 0; 3217 } 3218 3219 static void si_rlc_stop(struct radeon_device *rdev) 3220 { 3221 WREG32(RLC_CNTL, 0); 3222 } 3223 3224 static void si_rlc_start(struct radeon_device *rdev) 3225 { 3226 WREG32(RLC_CNTL, RLC_ENABLE); 3227 } 3228 3229 static int si_rlc_resume(struct radeon_device *rdev) 3230 { 3231 u32 i; 3232 const __be32 *fw_data; 3233 3234 if (!rdev->rlc_fw) 3235 return -EINVAL; 3236 3237 si_rlc_stop(rdev); 3238 3239 WREG32(RLC_RL_BASE, 0); 3240 WREG32(RLC_RL_SIZE, 0); 3241 WREG32(RLC_LB_CNTL, 0); 3242 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); 3243 WREG32(RLC_LB_CNTR_INIT, 0); 3244 3245 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3246 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3247 3248 WREG32(RLC_MC_CNTL, 0); 3249 WREG32(RLC_UCODE_CNTL, 0); 3250 3251 fw_data = (const __be32 *)rdev->rlc_fw; 3252 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) { 3253 WREG32(RLC_UCODE_ADDR, i); 3254 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3255 } 3256 WREG32(RLC_UCODE_ADDR, 0); 3257 3258 si_rlc_start(rdev); 3259 3260 return 0; 3261 } 3262 3263 static void si_enable_interrupts(struct radeon_device *rdev) 3264 { 3265 u32 ih_cntl = RREG32(IH_CNTL); 3266 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3267 3268 ih_cntl |= ENABLE_INTR; 3269 ih_rb_cntl |= IH_RB_ENABLE; 3270 WREG32(IH_CNTL, ih_cntl); 3271 WREG32(IH_RB_CNTL, ih_rb_cntl); 3272 rdev->ih.enabled = true; 3273 } 3274 3275 static void si_disable_interrupts(struct radeon_device *rdev) 3276 { 3277 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3278 u32 ih_cntl = RREG32(IH_CNTL); 3279 3280 ih_rb_cntl &= ~IH_RB_ENABLE; 3281 ih_cntl &= ~ENABLE_INTR; 3282 WREG32(IH_RB_CNTL, ih_rb_cntl); 3283 WREG32(IH_CNTL, ih_cntl); 3284 /* set rptr, wptr to 0 */ 3285 WREG32(IH_RB_RPTR, 0); 3286 WREG32(IH_RB_WPTR, 0); 3287 rdev->ih.enabled = false; 3288 rdev->ih.rptr = 0; 3289 } 3290 3291 static void si_disable_interrupt_state(struct radeon_device *rdev) 3292 { 3293 u32 tmp; 3294 3295 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3296 WREG32(CP_INT_CNTL_RING1, 0); 3297 WREG32(CP_INT_CNTL_RING2, 0); 3298 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 3299 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); 3300 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 3301 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); 3302 WREG32(GRBM_INT_CNTL, 0); 3303 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3304 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3305 if (rdev->num_crtc >= 4) { 3306 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3307 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3308 } 3309 if (rdev->num_crtc >= 6) { 3310 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3311 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3312 } 3313 3314 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3315 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3316 if (rdev->num_crtc >= 4) { 3317 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3318 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3319 } 3320 if (rdev->num_crtc >= 6) { 3321 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3322 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3323 } 3324 3325 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3326 3327 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3328 WREG32(DC_HPD1_INT_CONTROL, tmp); 3329 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3330 WREG32(DC_HPD2_INT_CONTROL, tmp); 3331 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3332 WREG32(DC_HPD3_INT_CONTROL, tmp); 3333 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3334 WREG32(DC_HPD4_INT_CONTROL, tmp); 3335 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3336 WREG32(DC_HPD5_INT_CONTROL, tmp); 3337 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3338 WREG32(DC_HPD6_INT_CONTROL, tmp); 3339 3340 } 3341 3342 static int si_irq_init(struct radeon_device *rdev) 3343 { 3344 int ret = 0; 3345 int rb_bufsz; 3346 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3347 3348 /* allocate ring */ 3349 ret = r600_ih_ring_alloc(rdev); 3350 if (ret) 3351 return ret; 3352 3353 /* disable irqs */ 3354 si_disable_interrupts(rdev); 3355 3356 /* init rlc */ 3357 ret = si_rlc_resume(rdev); 3358 if (ret) { 3359 r600_ih_ring_fini(rdev); 3360 return ret; 3361 } 3362 3363 /* setup interrupt control */ 3364 /* set dummy read address to ring address */ 3365 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3366 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3367 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3368 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3369 */ 3370 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3371 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3372 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3373 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3374 3375 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3376 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3377 3378 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3379 IH_WPTR_OVERFLOW_CLEAR | 3380 (rb_bufsz << 1)); 3381 3382 if (rdev->wb.enabled) 3383 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3384 3385 /* set the writeback address whether it's enabled or not */ 3386 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3387 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3388 3389 WREG32(IH_RB_CNTL, ih_rb_cntl); 3390 3391 /* set rptr, wptr to 0 */ 3392 WREG32(IH_RB_RPTR, 0); 3393 WREG32(IH_RB_WPTR, 0); 3394 3395 /* Default settings for IH_CNTL (disabled at first) */ 3396 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); 3397 /* RPTR_REARM only works if msi's are enabled */ 3398 if (rdev->msi_enabled) 3399 ih_cntl |= RPTR_REARM; 3400 WREG32(IH_CNTL, ih_cntl); 3401 3402 /* force the active interrupt state to all disabled */ 3403 si_disable_interrupt_state(rdev); 3404 3405 #ifdef notyet 3406 pci_set_master(rdev->pdev); 3407 #endif 3408 3409 /* enable irqs */ 3410 si_enable_interrupts(rdev); 3411 3412 return ret; 3413 } 3414 3415 int si_irq_set(struct radeon_device *rdev) 3416 { 3417 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3418 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; 3419 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 3420 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 3421 u32 grbm_int_cntl = 0; 3422 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 3423 u32 dma_cntl, dma_cntl1; 3424 3425 if (!rdev->irq.installed) { 3426 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3427 return -EINVAL; 3428 } 3429 /* don't enable anything if the ih is disabled */ 3430 if (!rdev->ih.enabled) { 3431 si_disable_interrupts(rdev); 3432 /* force the active interrupt state to all disabled */ 3433 si_disable_interrupt_state(rdev); 3434 return 0; 3435 } 3436 3437 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3438 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3439 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3440 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3441 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3442 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3443 3444 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 3445 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 3446 3447 /* enable CP interrupts on all rings */ 3448 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3449 DRM_DEBUG("si_irq_set: sw int gfx\n"); 3450 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3451 } 3452 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { 3453 DRM_DEBUG("si_irq_set: sw int cp1\n"); 3454 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; 3455 } 3456 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { 3457 DRM_DEBUG("si_irq_set: sw int cp2\n"); 3458 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; 3459 } 3460 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3461 DRM_DEBUG("si_irq_set: sw int dma\n"); 3462 dma_cntl |= TRAP_ENABLE; 3463 } 3464 3465 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { 3466 DRM_DEBUG("si_irq_set: sw int dma1\n"); 3467 dma_cntl1 |= TRAP_ENABLE; 3468 } 3469 if (rdev->irq.crtc_vblank_int[0] || 3470 atomic_read(&rdev->irq.pflip[0])) { 3471 DRM_DEBUG("si_irq_set: vblank 0\n"); 3472 crtc1 |= VBLANK_INT_MASK; 3473 } 3474 if (rdev->irq.crtc_vblank_int[1] || 3475 atomic_read(&rdev->irq.pflip[1])) { 3476 DRM_DEBUG("si_irq_set: vblank 1\n"); 3477 crtc2 |= VBLANK_INT_MASK; 3478 } 3479 if (rdev->irq.crtc_vblank_int[2] || 3480 atomic_read(&rdev->irq.pflip[2])) { 3481 DRM_DEBUG("si_irq_set: vblank 2\n"); 3482 crtc3 |= VBLANK_INT_MASK; 3483 } 3484 if (rdev->irq.crtc_vblank_int[3] || 3485 atomic_read(&rdev->irq.pflip[3])) { 3486 DRM_DEBUG("si_irq_set: vblank 3\n"); 3487 crtc4 |= VBLANK_INT_MASK; 3488 } 3489 if (rdev->irq.crtc_vblank_int[4] || 3490 atomic_read(&rdev->irq.pflip[4])) { 3491 DRM_DEBUG("si_irq_set: vblank 4\n"); 3492 crtc5 |= VBLANK_INT_MASK; 3493 } 3494 if (rdev->irq.crtc_vblank_int[5] || 3495 atomic_read(&rdev->irq.pflip[5])) { 3496 DRM_DEBUG("si_irq_set: vblank 5\n"); 3497 crtc6 |= VBLANK_INT_MASK; 3498 } 3499 if (rdev->irq.hpd[0]) { 3500 DRM_DEBUG("si_irq_set: hpd 1\n"); 3501 hpd1 |= DC_HPDx_INT_EN; 3502 } 3503 if (rdev->irq.hpd[1]) { 3504 DRM_DEBUG("si_irq_set: hpd 2\n"); 3505 hpd2 |= DC_HPDx_INT_EN; 3506 } 3507 if (rdev->irq.hpd[2]) { 3508 DRM_DEBUG("si_irq_set: hpd 3\n"); 3509 hpd3 |= DC_HPDx_INT_EN; 3510 } 3511 if (rdev->irq.hpd[3]) { 3512 DRM_DEBUG("si_irq_set: hpd 4\n"); 3513 hpd4 |= DC_HPDx_INT_EN; 3514 } 3515 if (rdev->irq.hpd[4]) { 3516 DRM_DEBUG("si_irq_set: hpd 5\n"); 3517 hpd5 |= DC_HPDx_INT_EN; 3518 } 3519 if (rdev->irq.hpd[5]) { 3520 DRM_DEBUG("si_irq_set: hpd 6\n"); 3521 hpd6 |= DC_HPDx_INT_EN; 3522 } 3523 3524 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3525 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); 3526 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); 3527 3528 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); 3529 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); 3530 3531 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3532 3533 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 3534 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 3535 if (rdev->num_crtc >= 4) { 3536 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 3537 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 3538 } 3539 if (rdev->num_crtc >= 6) { 3540 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 3541 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 3542 } 3543 3544 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 3545 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 3546 if (rdev->num_crtc >= 4) { 3547 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 3548 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 3549 } 3550 if (rdev->num_crtc >= 6) { 3551 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 3552 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 3553 } 3554 3555 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3556 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3557 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3558 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3559 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3560 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3561 3562 return 0; 3563 } 3564 3565 static inline void si_irq_ack(struct radeon_device *rdev) 3566 { 3567 u32 tmp; 3568 3569 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3570 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3571 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 3572 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 3573 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 3574 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 3575 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 3576 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 3577 if (rdev->num_crtc >= 4) { 3578 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 3579 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 3580 } 3581 if (rdev->num_crtc >= 6) { 3582 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 3583 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 3584 } 3585 3586 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 3587 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3588 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 3589 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3590 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 3591 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 3592 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 3593 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 3594 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 3595 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 3596 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 3597 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 3598 3599 if (rdev->num_crtc >= 4) { 3600 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 3601 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3602 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 3603 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3604 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 3605 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 3606 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 3607 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 3608 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 3609 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 3610 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 3611 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 3612 } 3613 3614 if (rdev->num_crtc >= 6) { 3615 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 3616 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3617 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 3618 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3619 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 3620 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 3621 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 3622 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 3623 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 3624 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 3625 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 3626 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 3627 } 3628 3629 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 3630 tmp = RREG32(DC_HPD1_INT_CONTROL); 3631 tmp |= DC_HPDx_INT_ACK; 3632 WREG32(DC_HPD1_INT_CONTROL, tmp); 3633 } 3634 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 3635 tmp = RREG32(DC_HPD2_INT_CONTROL); 3636 tmp |= DC_HPDx_INT_ACK; 3637 WREG32(DC_HPD2_INT_CONTROL, tmp); 3638 } 3639 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 3640 tmp = RREG32(DC_HPD3_INT_CONTROL); 3641 tmp |= DC_HPDx_INT_ACK; 3642 WREG32(DC_HPD3_INT_CONTROL, tmp); 3643 } 3644 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 3645 tmp = RREG32(DC_HPD4_INT_CONTROL); 3646 tmp |= DC_HPDx_INT_ACK; 3647 WREG32(DC_HPD4_INT_CONTROL, tmp); 3648 } 3649 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 3650 tmp = RREG32(DC_HPD5_INT_CONTROL); 3651 tmp |= DC_HPDx_INT_ACK; 3652 WREG32(DC_HPD5_INT_CONTROL, tmp); 3653 } 3654 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 3655 tmp = RREG32(DC_HPD5_INT_CONTROL); 3656 tmp |= DC_HPDx_INT_ACK; 3657 WREG32(DC_HPD6_INT_CONTROL, tmp); 3658 } 3659 } 3660 3661 static void si_irq_disable(struct radeon_device *rdev) 3662 { 3663 si_disable_interrupts(rdev); 3664 /* Wait and acknowledge irq */ 3665 mdelay(1); 3666 si_irq_ack(rdev); 3667 si_disable_interrupt_state(rdev); 3668 } 3669 3670 static void si_irq_suspend(struct radeon_device *rdev) 3671 { 3672 si_irq_disable(rdev); 3673 si_rlc_stop(rdev); 3674 } 3675 3676 static void si_irq_fini(struct radeon_device *rdev) 3677 { 3678 si_irq_suspend(rdev); 3679 r600_ih_ring_fini(rdev); 3680 } 3681 3682 static inline u32 si_get_ih_wptr(struct radeon_device *rdev) 3683 { 3684 u32 wptr, tmp; 3685 3686 if (rdev->wb.enabled) 3687 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3688 else 3689 wptr = RREG32(IH_RB_WPTR); 3690 3691 if (wptr & RB_OVERFLOW) { 3692 /* When a ring buffer overflow happen start parsing interrupt 3693 * from the last not overwritten vector (wptr + 16). Hopefully 3694 * this should allow us to catchup. 3695 */ 3696 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3697 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3698 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3699 tmp = RREG32(IH_RB_CNTL); 3700 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3701 WREG32(IH_RB_CNTL, tmp); 3702 } 3703 return (wptr & rdev->ih.ptr_mask); 3704 } 3705 3706 /* SI IV Ring 3707 * Each IV ring entry is 128 bits: 3708 * [7:0] - interrupt source id 3709 * [31:8] - reserved 3710 * [59:32] - interrupt source data 3711 * [63:60] - reserved 3712 * [71:64] - RINGID 3713 * [79:72] - VMID 3714 * [127:80] - reserved 3715 */ 3716 int si_irq_process(struct radeon_device *rdev) 3717 { 3718 u32 wptr; 3719 u32 rptr; 3720 u32 src_id, src_data, ring_id; 3721 u32 ring_index; 3722 bool queue_hotplug = false; 3723 3724 if (!rdev->ih.enabled || rdev->shutdown) 3725 return IRQ_NONE; 3726 3727 wptr = si_get_ih_wptr(rdev); 3728 3729 if (wptr == rdev->ih.rptr) 3730 return IRQ_NONE; 3731 restart_ih: 3732 /* is somebody else already processing irqs? */ 3733 if (atomic_xchg(&rdev->ih.lock, 1)) 3734 return IRQ_NONE; 3735 3736 rptr = rdev->ih.rptr; 3737 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3738 3739 /* Order reading of wptr vs. reading of IH ring data */ 3740 rmb(); 3741 3742 /* display interrupts */ 3743 si_irq_ack(rdev); 3744 3745 while (rptr != wptr) { 3746 /* wptr/rptr are in bytes! */ 3747 ring_index = rptr / 4; 3748 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3749 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3750 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; 3751 3752 switch (src_id) { 3753 case 1: /* D1 vblank/vline */ 3754 switch (src_data) { 3755 case 0: /* D1 vblank */ 3756 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 3757 if (rdev->irq.crtc_vblank_int[0]) { 3758 drm_handle_vblank(rdev->ddev, 0); 3759 rdev->pm.vblank_sync = true; 3760 wake_up(&rdev->irq.vblank_queue); 3761 } 3762 if (atomic_read(&rdev->irq.pflip[0])) 3763 radeon_crtc_handle_flip(rdev, 0); 3764 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3765 DRM_DEBUG("IH: D1 vblank\n"); 3766 } 3767 break; 3768 case 1: /* D1 vline */ 3769 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 3770 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3771 DRM_DEBUG("IH: D1 vline\n"); 3772 } 3773 break; 3774 default: 3775 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3776 break; 3777 } 3778 break; 3779 case 2: /* D2 vblank/vline */ 3780 switch (src_data) { 3781 case 0: /* D2 vblank */ 3782 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 3783 if (rdev->irq.crtc_vblank_int[1]) { 3784 drm_handle_vblank(rdev->ddev, 1); 3785 rdev->pm.vblank_sync = true; 3786 wake_up(&rdev->irq.vblank_queue); 3787 } 3788 if (atomic_read(&rdev->irq.pflip[1])) 3789 radeon_crtc_handle_flip(rdev, 1); 3790 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 3791 DRM_DEBUG("IH: D2 vblank\n"); 3792 } 3793 break; 3794 case 1: /* D2 vline */ 3795 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 3796 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 3797 DRM_DEBUG("IH: D2 vline\n"); 3798 } 3799 break; 3800 default: 3801 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3802 break; 3803 } 3804 break; 3805 case 3: /* D3 vblank/vline */ 3806 switch (src_data) { 3807 case 0: /* D3 vblank */ 3808 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 3809 if (rdev->irq.crtc_vblank_int[2]) { 3810 drm_handle_vblank(rdev->ddev, 2); 3811 rdev->pm.vblank_sync = true; 3812 wake_up(&rdev->irq.vblank_queue); 3813 } 3814 if (atomic_read(&rdev->irq.pflip[2])) 3815 radeon_crtc_handle_flip(rdev, 2); 3816 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 3817 DRM_DEBUG("IH: D3 vblank\n"); 3818 } 3819 break; 3820 case 1: /* D3 vline */ 3821 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 3822 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 3823 DRM_DEBUG("IH: D3 vline\n"); 3824 } 3825 break; 3826 default: 3827 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3828 break; 3829 } 3830 break; 3831 case 4: /* D4 vblank/vline */ 3832 switch (src_data) { 3833 case 0: /* D4 vblank */ 3834 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 3835 if (rdev->irq.crtc_vblank_int[3]) { 3836 drm_handle_vblank(rdev->ddev, 3); 3837 rdev->pm.vblank_sync = true; 3838 wake_up(&rdev->irq.vblank_queue); 3839 } 3840 if (atomic_read(&rdev->irq.pflip[3])) 3841 radeon_crtc_handle_flip(rdev, 3); 3842 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 3843 DRM_DEBUG("IH: D4 vblank\n"); 3844 } 3845 break; 3846 case 1: /* D4 vline */ 3847 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 3848 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 3849 DRM_DEBUG("IH: D4 vline\n"); 3850 } 3851 break; 3852 default: 3853 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3854 break; 3855 } 3856 break; 3857 case 5: /* D5 vblank/vline */ 3858 switch (src_data) { 3859 case 0: /* D5 vblank */ 3860 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 3861 if (rdev->irq.crtc_vblank_int[4]) { 3862 drm_handle_vblank(rdev->ddev, 4); 3863 rdev->pm.vblank_sync = true; 3864 wake_up(&rdev->irq.vblank_queue); 3865 } 3866 if (atomic_read(&rdev->irq.pflip[4])) 3867 radeon_crtc_handle_flip(rdev, 4); 3868 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 3869 DRM_DEBUG("IH: D5 vblank\n"); 3870 } 3871 break; 3872 case 1: /* D5 vline */ 3873 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 3874 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 3875 DRM_DEBUG("IH: D5 vline\n"); 3876 } 3877 break; 3878 default: 3879 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3880 break; 3881 } 3882 break; 3883 case 6: /* D6 vblank/vline */ 3884 switch (src_data) { 3885 case 0: /* D6 vblank */ 3886 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 3887 if (rdev->irq.crtc_vblank_int[5]) { 3888 drm_handle_vblank(rdev->ddev, 5); 3889 rdev->pm.vblank_sync = true; 3890 wake_up(&rdev->irq.vblank_queue); 3891 } 3892 if (atomic_read(&rdev->irq.pflip[5])) 3893 radeon_crtc_handle_flip(rdev, 5); 3894 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 3895 DRM_DEBUG("IH: D6 vblank\n"); 3896 } 3897 break; 3898 case 1: /* D6 vline */ 3899 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 3900 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 3901 DRM_DEBUG("IH: D6 vline\n"); 3902 } 3903 break; 3904 default: 3905 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3906 break; 3907 } 3908 break; 3909 case 42: /* HPD hotplug */ 3910 switch (src_data) { 3911 case 0: 3912 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 3913 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 3914 queue_hotplug = true; 3915 DRM_DEBUG("IH: HPD1\n"); 3916 } 3917 break; 3918 case 1: 3919 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 3920 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 3921 queue_hotplug = true; 3922 DRM_DEBUG("IH: HPD2\n"); 3923 } 3924 break; 3925 case 2: 3926 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 3927 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 3928 queue_hotplug = true; 3929 DRM_DEBUG("IH: HPD3\n"); 3930 } 3931 break; 3932 case 3: 3933 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 3934 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 3935 queue_hotplug = true; 3936 DRM_DEBUG("IH: HPD4\n"); 3937 } 3938 break; 3939 case 4: 3940 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 3941 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 3942 queue_hotplug = true; 3943 DRM_DEBUG("IH: HPD5\n"); 3944 } 3945 break; 3946 case 5: 3947 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 3948 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 3949 queue_hotplug = true; 3950 DRM_DEBUG("IH: HPD6\n"); 3951 } 3952 break; 3953 default: 3954 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3955 break; 3956 } 3957 break; 3958 case 146: 3959 case 147: 3960 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); 3961 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 3962 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 3963 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 3964 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 3965 /* reset addr and status */ 3966 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); 3967 break; 3968 case 176: /* RINGID0 CP_INT */ 3969 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3970 break; 3971 case 177: /* RINGID1 CP_INT */ 3972 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 3973 break; 3974 case 178: /* RINGID2 CP_INT */ 3975 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 3976 break; 3977 case 181: /* CP EOP event */ 3978 DRM_DEBUG("IH: CP EOP\n"); 3979 switch (ring_id) { 3980 case 0: 3981 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3982 break; 3983 case 1: 3984 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 3985 break; 3986 case 2: 3987 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 3988 break; 3989 } 3990 break; 3991 case 224: /* DMA trap event */ 3992 DRM_DEBUG("IH: DMA trap\n"); 3993 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 3994 break; 3995 case 233: /* GUI IDLE */ 3996 DRM_DEBUG("IH: GUI idle\n"); 3997 break; 3998 case 244: /* DMA trap event */ 3999 DRM_DEBUG("IH: DMA1 trap\n"); 4000 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 4001 break; 4002 default: 4003 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4004 break; 4005 } 4006 4007 /* wptr/rptr are in bytes! */ 4008 rptr += 16; 4009 rptr &= rdev->ih.ptr_mask; 4010 } 4011 if (queue_hotplug) 4012 task_add(systq, &rdev->hotplug_task); 4013 rdev->ih.rptr = rptr; 4014 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4015 atomic_set(&rdev->ih.lock, 0); 4016 4017 /* make sure wptr hasn't changed while processing */ 4018 wptr = si_get_ih_wptr(rdev); 4019 if (wptr != rptr) 4020 goto restart_ih; 4021 4022 return IRQ_HANDLED; 4023 } 4024 4025 /** 4026 * si_copy_dma - copy pages using the DMA engine 4027 * 4028 * @rdev: radeon_device pointer 4029 * @src_offset: src GPU address 4030 * @dst_offset: dst GPU address 4031 * @num_gpu_pages: number of GPU pages to xfer 4032 * @fence: radeon fence object 4033 * 4034 * Copy GPU paging using the DMA engine (SI). 4035 * Used by the radeon ttm implementation to move pages if 4036 * registered as the asic copy callback. 4037 */ 4038 int si_copy_dma(struct radeon_device *rdev, 4039 uint64_t src_offset, uint64_t dst_offset, 4040 unsigned num_gpu_pages, 4041 struct radeon_fence **fence) 4042 { 4043 struct radeon_semaphore *sem = NULL; 4044 int ring_index = rdev->asic->copy.dma_ring_index; 4045 struct radeon_ring *ring = &rdev->ring[ring_index]; 4046 u32 size_in_bytes, cur_size_in_bytes; 4047 int i, num_loops; 4048 int r = 0; 4049 4050 r = radeon_semaphore_create(rdev, &sem); 4051 if (r) { 4052 DRM_ERROR("radeon: moving bo (%d).\n", r); 4053 return r; 4054 } 4055 4056 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 4057 num_loops = DIV_ROUND_UP(size_in_bytes, 0xfffff); 4058 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); 4059 if (r) { 4060 DRM_ERROR("radeon: moving bo (%d).\n", r); 4061 radeon_semaphore_free(rdev, &sem, NULL); 4062 return r; 4063 } 4064 4065 if (radeon_fence_need_sync(*fence, ring->idx)) { 4066 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 4067 ring->idx); 4068 radeon_fence_note_sync(*fence, ring->idx); 4069 } else { 4070 radeon_semaphore_free(rdev, &sem, NULL); 4071 } 4072 4073 for (i = 0; i < num_loops; i++) { 4074 cur_size_in_bytes = size_in_bytes; 4075 if (cur_size_in_bytes > 0xFFFFF) 4076 cur_size_in_bytes = 0xFFFFF; 4077 size_in_bytes -= cur_size_in_bytes; 4078 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); 4079 radeon_ring_write(ring, dst_offset & 0xffffffff); 4080 radeon_ring_write(ring, src_offset & 0xffffffff); 4081 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 4082 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); 4083 src_offset += cur_size_in_bytes; 4084 dst_offset += cur_size_in_bytes; 4085 } 4086 4087 r = radeon_fence_emit(rdev, fence, ring->idx); 4088 if (r) { 4089 radeon_ring_unlock_undo(rdev, ring); 4090 return r; 4091 } 4092 4093 radeon_ring_unlock_commit(rdev, ring); 4094 radeon_semaphore_free(rdev, &sem, *fence); 4095 4096 return r; 4097 } 4098 4099 /* 4100 * startup/shutdown callbacks 4101 */ 4102 static int si_startup(struct radeon_device *rdev) 4103 { 4104 struct radeon_ring *ring; 4105 int r; 4106 4107 si_mc_program(rdev); 4108 4109 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || 4110 !rdev->rlc_fw || !rdev->mc_fw) { 4111 r = si_init_microcode(rdev); 4112 if (r) { 4113 DRM_ERROR("Failed to load firmware!\n"); 4114 return r; 4115 } 4116 } 4117 4118 r = si_mc_load_microcode(rdev); 4119 if (r) { 4120 DRM_ERROR("Failed to load MC firmware!\n"); 4121 return r; 4122 } 4123 4124 r = r600_vram_scratch_init(rdev); 4125 if (r) 4126 return r; 4127 4128 r = si_pcie_gart_enable(rdev); 4129 if (r) 4130 return r; 4131 si_gpu_init(rdev); 4132 4133 #if 0 4134 r = evergreen_blit_init(rdev); 4135 if (r) { 4136 r600_blit_fini(rdev); 4137 rdev->asic->copy = NULL; 4138 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 4139 } 4140 #endif 4141 /* allocate rlc buffers */ 4142 r = si_rlc_init(rdev); 4143 if (r) { 4144 DRM_ERROR("Failed to init rlc BOs!\n"); 4145 return r; 4146 } 4147 4148 /* allocate wb buffer */ 4149 r = radeon_wb_init(rdev); 4150 if (r) 4151 return r; 4152 4153 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 4154 if (r) { 4155 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4156 return r; 4157 } 4158 4159 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 4160 if (r) { 4161 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4162 return r; 4163 } 4164 4165 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 4166 if (r) { 4167 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4168 return r; 4169 } 4170 4171 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 4172 if (r) { 4173 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 4174 return r; 4175 } 4176 4177 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 4178 if (r) { 4179 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 4180 return r; 4181 } 4182 4183 /* Enable IRQ */ 4184 if (!rdev->irq.installed) { 4185 r = radeon_irq_kms_init(rdev); 4186 if (r) 4187 return r; 4188 } 4189 4190 r = si_irq_init(rdev); 4191 if (r) { 4192 DRM_ERROR("radeon: IH init failed (%d).\n", r); 4193 radeon_irq_kms_fini(rdev); 4194 return r; 4195 } 4196 si_irq_set(rdev); 4197 4198 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4199 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 4200 CP_RB0_RPTR, CP_RB0_WPTR, 4201 0, 0xfffff, RADEON_CP_PACKET2); 4202 if (r) 4203 return r; 4204 4205 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 4206 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, 4207 CP_RB1_RPTR, CP_RB1_WPTR, 4208 0, 0xfffff, RADEON_CP_PACKET2); 4209 if (r) 4210 return r; 4211 4212 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 4213 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, 4214 CP_RB2_RPTR, CP_RB2_WPTR, 4215 0, 0xfffff, RADEON_CP_PACKET2); 4216 if (r) 4217 return r; 4218 4219 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 4220 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 4221 DMA_RB_RPTR + DMA0_REGISTER_OFFSET, 4222 DMA_RB_WPTR + DMA0_REGISTER_OFFSET, 4223 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 4224 if (r) 4225 return r; 4226 4227 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 4228 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 4229 DMA_RB_RPTR + DMA1_REGISTER_OFFSET, 4230 DMA_RB_WPTR + DMA1_REGISTER_OFFSET, 4231 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 4232 if (r) 4233 return r; 4234 4235 r = si_cp_load_microcode(rdev); 4236 if (r) 4237 return r; 4238 r = si_cp_resume(rdev); 4239 if (r) 4240 return r; 4241 4242 r = cayman_dma_resume(rdev); 4243 if (r) 4244 return r; 4245 4246 r = radeon_ib_pool_init(rdev); 4247 if (r) { 4248 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4249 return r; 4250 } 4251 4252 r = radeon_vm_manager_init(rdev); 4253 if (r) { 4254 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 4255 return r; 4256 } 4257 4258 return 0; 4259 } 4260 4261 int si_resume(struct radeon_device *rdev) 4262 { 4263 int r; 4264 4265 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 4266 * posting will perform necessary task to bring back GPU into good 4267 * shape. 4268 */ 4269 /* post card */ 4270 atom_asic_init(rdev->mode_info.atom_context); 4271 4272 rdev->accel_working = true; 4273 r = si_startup(rdev); 4274 if (r) { 4275 DRM_ERROR("si startup failed on resume\n"); 4276 rdev->accel_working = false; 4277 return r; 4278 } 4279 4280 return r; 4281 4282 } 4283 4284 int si_suspend(struct radeon_device *rdev) 4285 { 4286 radeon_vm_manager_fini(rdev); 4287 si_cp_enable(rdev, false); 4288 cayman_dma_stop(rdev); 4289 si_irq_suspend(rdev); 4290 radeon_wb_disable(rdev); 4291 si_pcie_gart_disable(rdev); 4292 return 0; 4293 } 4294 4295 /* Plan is to move initialization in that function and use 4296 * helper function so that radeon_device_init pretty much 4297 * do nothing more than calling asic specific function. This 4298 * should also allow to remove a bunch of callback function 4299 * like vram_info. 4300 */ 4301 int si_init(struct radeon_device *rdev) 4302 { 4303 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4304 int r; 4305 4306 /* Read BIOS */ 4307 if (!radeon_get_bios(rdev)) { 4308 if (ASIC_IS_AVIVO(rdev)) 4309 return -EINVAL; 4310 } 4311 /* Must be an ATOMBIOS */ 4312 if (!rdev->is_atom_bios) { 4313 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 4314 return -EINVAL; 4315 } 4316 r = radeon_atombios_init(rdev); 4317 if (r) 4318 return r; 4319 4320 /* Post card if necessary */ 4321 if (!radeon_card_posted(rdev)) { 4322 if (!rdev->bios) { 4323 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 4324 return -EINVAL; 4325 } 4326 DRM_INFO("GPU not posted. posting now...\n"); 4327 atom_asic_init(rdev->mode_info.atom_context); 4328 } 4329 /* Initialize scratch registers */ 4330 si_scratch_init(rdev); 4331 /* Initialize surface registers */ 4332 radeon_surface_init(rdev); 4333 /* Initialize clocks */ 4334 radeon_get_clock_info(rdev->ddev); 4335 4336 /* Fence driver */ 4337 r = radeon_fence_driver_init(rdev); 4338 if (r) 4339 return r; 4340 4341 /* initialize memory controller */ 4342 r = si_mc_init(rdev); 4343 if (r) 4344 return r; 4345 /* Memory manager */ 4346 r = radeon_bo_init(rdev); 4347 if (r) 4348 return r; 4349 4350 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4351 ring->ring_obj = NULL; 4352 r600_ring_init(rdev, ring, 1024 * 1024); 4353 4354 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 4355 ring->ring_obj = NULL; 4356 r600_ring_init(rdev, ring, 1024 * 1024); 4357 4358 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 4359 ring->ring_obj = NULL; 4360 r600_ring_init(rdev, ring, 1024 * 1024); 4361 4362 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 4363 ring->ring_obj = NULL; 4364 r600_ring_init(rdev, ring, 64 * 1024); 4365 4366 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 4367 ring->ring_obj = NULL; 4368 r600_ring_init(rdev, ring, 64 * 1024); 4369 4370 rdev->ih.ring_obj = NULL; 4371 r600_ih_ring_init(rdev, 64 * 1024); 4372 4373 r = r600_pcie_gart_init(rdev); 4374 if (r) 4375 return r; 4376 4377 rdev->accel_working = true; 4378 r = si_startup(rdev); 4379 if (r) { 4380 dev_err(rdev->dev, "disabling GPU acceleration\n"); 4381 si_cp_fini(rdev); 4382 cayman_dma_fini(rdev); 4383 si_irq_fini(rdev); 4384 si_rlc_fini(rdev); 4385 radeon_wb_fini(rdev); 4386 radeon_ib_pool_fini(rdev); 4387 radeon_vm_manager_fini(rdev); 4388 radeon_irq_kms_fini(rdev); 4389 si_pcie_gart_fini(rdev); 4390 rdev->accel_working = false; 4391 } 4392 4393 /* Don't start up if the MC ucode is missing. 4394 * The default clocks and voltages before the MC ucode 4395 * is loaded are not suffient for advanced operations. 4396 */ 4397 if (!rdev->mc_fw) { 4398 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 4399 return -EINVAL; 4400 } 4401 4402 return 0; 4403 } 4404 4405 void si_fini(struct radeon_device *rdev) 4406 { 4407 #if 0 4408 r600_blit_fini(rdev); 4409 #endif 4410 si_cp_fini(rdev); 4411 cayman_dma_fini(rdev); 4412 si_irq_fini(rdev); 4413 si_rlc_fini(rdev); 4414 radeon_wb_fini(rdev); 4415 radeon_vm_manager_fini(rdev); 4416 radeon_ib_pool_fini(rdev); 4417 radeon_irq_kms_fini(rdev); 4418 si_pcie_gart_fini(rdev); 4419 r600_vram_scratch_fini(rdev); 4420 radeon_gem_fini(rdev); 4421 radeon_fence_driver_fini(rdev); 4422 radeon_bo_fini(rdev); 4423 radeon_atombios_fini(rdev); 4424 kfree(rdev->bios); 4425 rdev->bios = NULL; 4426 } 4427 4428 /** 4429 * si_get_gpu_clock - return GPU clock counter snapshot 4430 * 4431 * @rdev: radeon_device pointer 4432 * 4433 * Fetches a GPU clock counter snapshot (SI). 4434 * Returns the 64 bit clock counter snapshot. 4435 */ 4436 uint64_t si_get_gpu_clock(struct radeon_device *rdev) 4437 { 4438 uint64_t clock; 4439 4440 mutex_lock(&rdev->gpu_clock_mutex); 4441 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4442 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4443 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4444 mutex_unlock(&rdev->gpu_clock_mutex); 4445 return clock; 4446 } 4447