1*391fd4d0Sdms /* $OpenBSD: gcu_reg.h,v 1.1 2009/11/25 13:28:13 dms Exp $ */ 2*391fd4d0Sdms 3*391fd4d0Sdms /* 4*391fd4d0Sdms * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. 5*391fd4d0Sdms * All rights reserved. 6*391fd4d0Sdms * 7*391fd4d0Sdms * Redistribution and use in source and binary forms, with or without 8*391fd4d0Sdms * modification, are permitted provided that the following conditions 9*391fd4d0Sdms * are met: 10*391fd4d0Sdms * 11*391fd4d0Sdms * * Redistributions of source code must retain the above copyright 12*391fd4d0Sdms * notice, this list of conditions and the following disclaimer. 13*391fd4d0Sdms * * Redistributions in binary form must reproduce the above copyright 14*391fd4d0Sdms * notice, this list of conditions and the following disclaimer in 15*391fd4d0Sdms * the documentation and/or other materials provided with the 16*391fd4d0Sdms * distribution. 17*391fd4d0Sdms * * Neither the name of Intel Corporation nor the names of its 18*391fd4d0Sdms * contributors may be used to endorse or promote products derived 19*391fd4d0Sdms * from this software without specific prior written permission. 20*391fd4d0Sdms * 21*391fd4d0Sdms * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22*391fd4d0Sdms * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23*391fd4d0Sdms * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24*391fd4d0Sdms * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25*391fd4d0Sdms * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26*391fd4d0Sdms * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27*391fd4d0Sdms * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28*391fd4d0Sdms * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29*391fd4d0Sdms * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30*391fd4d0Sdms * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31*391fd4d0Sdms * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32*391fd4d0Sdms * 33*391fd4d0Sdms * version: Embedded.B.1.0.3-146 34*391fd4d0Sdms */ 35*391fd4d0Sdms 36*391fd4d0Sdms /* 37*391fd4d0Sdms * gcu_reg.h 38*391fd4d0Sdms * Macros and constants related to the registers available on the GCU 39*391fd4d0Sdms */ 40*391fd4d0Sdms 41*391fd4d0Sdms #ifndef GCU_REG_H 42*391fd4d0Sdms #define GCU_REG_H 43*391fd4d0Sdms 44*391fd4d0Sdms /* Register Offsets within memory map register space */ 45*391fd4d0Sdms #define MDIO_STATUS_REG 0x00000010UL 46*391fd4d0Sdms #define MDIO_COMMAND_REG 0x00000014UL 47*391fd4d0Sdms 48*391fd4d0Sdms /* MDIO_STATUS_REG fields */ 49*391fd4d0Sdms #define MDIO_STATUS_STATUS_MASK 0x80000000UL /* bit 31 = 1 on error */ 50*391fd4d0Sdms #define MDIO_STATUS_READ_DATA_MASK 0x0000FFFFUL 51*391fd4d0Sdms 52*391fd4d0Sdms /* MDIO_COMMAND_REG fields */ 53*391fd4d0Sdms #define MDIO_COMMAND_GO_MASK 0x80000000UL /* bit 31 = 1 during read or 54*391fd4d0Sdms * write, 0 on completion */ 55*391fd4d0Sdms #define MDIO_COMMAND_OPER_MASK 0x04000000UL /* bit = 1 is a write */ 56*391fd4d0Sdms #define MDIO_COMMAND_PHY_ADDR_MASK 0x03E00000UL 57*391fd4d0Sdms #define MDIO_COMMAND_PHY_REG_MASK 0x001F0000UL 58*391fd4d0Sdms #define MDIO_COMMAND_WRITE_DATA_MASK 0x0000FFFFUL 59*391fd4d0Sdms 60*391fd4d0Sdms #define MDIO_COMMAND_GO_OFFSET 31 61*391fd4d0Sdms #define MDIO_COMMAND_OPER_OFFSET 26 62*391fd4d0Sdms #define MDIO_COMMAND_PHY_ADDR_OFFSET 21 63*391fd4d0Sdms #define MDIO_COMMAND_PHY_REG_OFFSET 16 64*391fd4d0Sdms #define MDIO_COMMAND_WRITE_DATA_OFFSET 0 65*391fd4d0Sdms 66*391fd4d0Sdms #define MDIO_COMMAND_PHY_ADDR_MAX 2 /* total phys supported by GCU */ 67*391fd4d0Sdms #define MDIO_COMMAND_PHY_REG_MAX 31 /* total registers available on 68*391fd4d0Sdms * the M88 Phy used on truxton */ 69*391fd4d0Sdms 70*391fd4d0Sdms #endif /* ifndef GCU_REG_H */ 71*391fd4d0Sdms 72