1 /* $OpenBSD: ichiic.c,v 1.24 2010/04/08 00:23:53 tedu Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB } 104 }; 105 106 int 107 ichiic_match(struct device *parent, void *match, void *aux) 108 { 109 return (pci_matchbyid(aux, ichiic_ids, 110 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 111 } 112 113 void 114 ichiic_attach(struct device *parent, struct device *self, void *aux) 115 { 116 struct ichiic_softc *sc = (struct ichiic_softc *)self; 117 struct pci_attach_args *pa = aux; 118 struct i2cbus_attach_args iba; 119 pcireg_t conf; 120 bus_size_t iosize; 121 pci_intr_handle_t ih; 122 const char *intrstr = NULL; 123 124 /* Read configuration */ 125 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 126 DPRINTF((": conf 0x%08x", conf)); 127 128 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 129 printf(": SMBus disabled\n"); 130 return; 131 } 132 133 /* Map I/O space */ 134 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 135 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 136 printf(": can't map i/o space\n"); 137 return; 138 } 139 140 sc->sc_poll = 1; 141 if (conf & ICH_SMB_HOSTC_SMIEN) { 142 /* No PCI IRQ */ 143 printf(": SMI"); 144 } else { 145 /* Install interrupt handler */ 146 if (pci_intr_map(pa, &ih) == 0) { 147 intrstr = pci_intr_string(pa->pa_pc, ih); 148 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 149 ichiic_intr, sc, sc->sc_dev.dv_xname); 150 if (sc->sc_ih != NULL) { 151 printf(": %s", intrstr); 152 sc->sc_poll = 0; 153 } 154 } 155 if (sc->sc_poll) 156 printf(": polling"); 157 } 158 159 printf("\n"); 160 161 /* Attach I2C bus */ 162 rw_init(&sc->sc_i2c_lock, "iiclk"); 163 sc->sc_i2c_tag.ic_cookie = sc; 164 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 165 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 166 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 167 168 bzero(&iba, sizeof(iba)); 169 iba.iba_name = "iic"; 170 iba.iba_tag = &sc->sc_i2c_tag; 171 config_found(self, &iba, iicbus_print); 172 173 return; 174 } 175 176 int 177 ichiic_i2c_acquire_bus(void *cookie, int flags) 178 { 179 struct ichiic_softc *sc = cookie; 180 181 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 182 return (0); 183 184 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 185 } 186 187 void 188 ichiic_i2c_release_bus(void *cookie, int flags) 189 { 190 struct ichiic_softc *sc = cookie; 191 192 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 193 return; 194 195 rw_exit(&sc->sc_i2c_lock); 196 } 197 198 int 199 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 200 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 201 { 202 struct ichiic_softc *sc = cookie; 203 u_int8_t *b; 204 u_int8_t ctl, st; 205 int retries; 206 207 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 208 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 209 len, flags)); 210 211 /* Wait for bus to be idle */ 212 for (retries = 100; retries > 0; retries--) { 213 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 214 if (!(st & ICH_SMB_HS_BUSY)) 215 break; 216 DELAY(ICHIIC_DELAY); 217 } 218 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 219 ICH_SMB_HS_BITS)); 220 if (st & ICH_SMB_HS_BUSY) 221 return (1); 222 223 if (cold || sc->sc_poll) 224 flags |= I2C_F_POLL; 225 226 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 227 return (1); 228 229 /* Setup transfer */ 230 sc->sc_i2c_xfer.op = op; 231 sc->sc_i2c_xfer.buf = buf; 232 sc->sc_i2c_xfer.len = len; 233 sc->sc_i2c_xfer.flags = flags; 234 sc->sc_i2c_xfer.error = 0; 235 236 /* Set slave address and transfer direction */ 237 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 238 ICH_SMB_TXSLVA_ADDR(addr) | 239 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 240 241 b = (void *)cmdbuf; 242 if (cmdlen > 0) 243 /* Set command byte */ 244 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 245 246 if (I2C_OP_WRITE_P(op)) { 247 /* Write data */ 248 b = buf; 249 if (len > 0) 250 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 251 ICH_SMB_HD0, b[0]); 252 if (len > 1) 253 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 254 ICH_SMB_HD1, b[1]); 255 } 256 257 /* Set SMBus command */ 258 if (len == 0) 259 ctl = ICH_SMB_HC_CMD_BYTE; 260 else if (len == 1) 261 ctl = ICH_SMB_HC_CMD_BDATA; 262 else if (len == 2) 263 ctl = ICH_SMB_HC_CMD_WDATA; 264 265 if ((flags & I2C_F_POLL) == 0) 266 ctl |= ICH_SMB_HC_INTREN; 267 268 /* Start transaction */ 269 ctl |= ICH_SMB_HC_START; 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 271 272 if (flags & I2C_F_POLL) { 273 /* Poll for completion */ 274 DELAY(ICHIIC_DELAY); 275 for (retries = 1000; retries > 0; retries--) { 276 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 277 ICH_SMB_HS); 278 if ((st & ICH_SMB_HS_BUSY) == 0) 279 break; 280 DELAY(ICHIIC_DELAY); 281 } 282 if (st & ICH_SMB_HS_BUSY) 283 goto timeout; 284 ichiic_intr(sc); 285 } else { 286 /* Wait for interrupt */ 287 if (tsleep(sc, PRIBIO, "iicexec", ICHIIC_TIMEOUT * hz)) 288 goto timeout; 289 } 290 291 if (sc->sc_i2c_xfer.error) 292 return (1); 293 294 return (0); 295 296 timeout: 297 /* 298 * Transfer timeout. Kill the transaction and clear status bits. 299 */ 300 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 301 ICH_SMB_HC_KILL); 302 DELAY(ICHIIC_DELAY); 303 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 304 if ((st & ICH_SMB_HS_FAILED) == 0) 305 printf("%s: abort failed, status 0x%b\n", 306 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 307 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 308 return (1); 309 } 310 311 int 312 ichiic_intr(void *arg) 313 { 314 struct ichiic_softc *sc = arg; 315 u_int8_t st; 316 u_int8_t *b; 317 size_t len; 318 319 /* Read status */ 320 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 321 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 322 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 323 ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0) 324 /* Interrupt was not for us */ 325 return (0); 326 327 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 328 ICH_SMB_HS_BITS)); 329 330 /* Clear status bits */ 331 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 332 333 /* Check for errors */ 334 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 335 sc->sc_i2c_xfer.error = 1; 336 goto done; 337 } 338 339 if (st & ICH_SMB_HS_INTR) { 340 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 341 goto done; 342 343 /* Read data */ 344 b = sc->sc_i2c_xfer.buf; 345 len = sc->sc_i2c_xfer.len; 346 if (len > 0) 347 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 348 ICH_SMB_HD0); 349 if (len > 1) 350 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 351 ICH_SMB_HD1); 352 } 353 354 done: 355 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 356 wakeup(sc); 357 return (1); 358 } 359