1 /* $OpenBSD: if_alcreg.h,v 1.5 2014/11/27 14:52:04 brad Exp $ */ 2 /*- 3 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 29 */ 30 31 #ifndef _IF_ALCREG_H 32 #define _IF_ALCREG_H 33 34 #define ALC_PCIR_BAR 0x10 35 36 #define ATHEROS_AR8152_B_V10 0xC0 37 #define ATHEROS_AR8152_B_V11 0xC1 38 39 /* 0x0000 - 0x02FF : PCIe configuration space */ 40 41 #define ALC_PEX_UNC_ERR_SEV 0x10C 42 #define PEX_UNC_ERR_SEV_TRN 0x00000001 43 #define PEX_UNC_ERR_SEV_DLP 0x00000010 44 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 45 #define PEX_UNC_ERR_SEV_FCP 0x00002000 46 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 47 #define PEX_UNC_ERR_SEV_CA 0x00008000 48 #define PEX_UNC_ERR_SEV_UC 0x00010000 49 #define PEX_UNC_ERR_SEV_ROV 0x00020000 50 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 51 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 52 #define PEX_UNC_ERR_SEV_UR 0x00100000 53 54 #define ALC_TWSI_CFG 0x218 55 #define TWSI_CFG_SW_LD_START 0x00000800 56 #define TWSI_CFG_HW_LD_START 0x00001000 57 #define TWSI_CFG_LD_EXIST 0x00400000 58 59 #define ALC_PCIE_PHYMISC 0x1000 60 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 61 62 #define ALC_PCIE_PHYMISC2 0x1004 63 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 64 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 65 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 66 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 67 68 #define ALC_TWSI_DEBUG 0x1108 69 #define TWSI_DEBUG_DEV_EXIST 0x20000000 70 71 #define ALC_EEPROM_CFG 0x12C0 72 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 73 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 74 #define EEPROM_CFG_ACK 0x40000000 75 #define EEPROM_CFG_RW 0x80000000 76 #define EEPROM_CFG_DATA_HI_SHIFT 0 77 #define EEPROM_CFG_ADDR_SHIFT 16 78 79 #define ALC_EEPROM_DATA_LO 0x12C4 80 81 #define ALC_OPT_CFG 0x12F0 82 #define OPT_CFG_CLK_ENB 0x00000002 83 84 #define ALC_PM_CFG 0x12F8 85 #define PM_CFG_SERDES_ENB 0x00000001 86 #define PM_CFG_RBER_ENB 0x00000002 87 #define PM_CFG_CLK_REQ_ENB 0x00000004 88 #define PM_CFG_ASPM_L1_ENB 0x00000008 89 #define PM_CFG_SERDES_L1_ENB 0x00000010 90 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 91 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 92 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 93 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 94 #define PM_CFG_ASPM_L0S_ENB 0x00001000 95 #define PM_CFG_CLK_SWH_L1 0x00002000 96 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 97 #define PM_CFG_PCIE_RECV 0x00008000 98 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 99 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 100 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 101 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 102 #define PM_CFG_SA_DLY_ENB 0x20000000 103 #define PM_CFG_MAC_ASPM_CHK 0x40000000 104 #define PM_CFG_HOTRST 0x80000000 105 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 106 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 107 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 108 #define PM_CFG_LCKDET_TIMER_SHIFT 24 109 110 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 111 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 112 #define PM_CFG_LCKDET_TIMER_DEFAULT 12 113 #define PM_CFG_PM_REQ_TIMER_DEFAULT 12 114 115 #define ALC_LTSSM_ID_CFG 0x12FC 116 #define LTSSM_ID_WRO_ENB 0x00001000 117 118 #define ALC_MASTER_CFG 0x1400 119 #define MASTER_RESET 0x00000001 120 #define MASTER_TEST_MODE_MASK 0x0000000C 121 #define MASTER_BERT_START 0x00000010 122 #define MASTER_OOB_DIS_OFF 0x00000040 123 #define MASTER_SA_TIMER_ENB 0x00000080 124 #define MASTER_MTIMER_ENB 0x00000100 125 #define MASTER_MANUAL_INTR_ENB 0x00000200 126 #define MASTER_IM_TX_TIMER_ENB 0x00000400 127 #define MASTER_IM_RX_TIMER_ENB 0x00000800 128 #define MASTER_CLK_SEL_DIS 0x00001000 129 #define MASTER_CLK_SWH_MODE 0x00002000 130 #define MASTER_INTR_RD_CLR 0x00004000 131 #define MASTER_CHIP_REV_MASK 0x00FF0000 132 #define MASTER_CHIP_ID_MASK 0x7F000000 133 #define MASTER_OTP_SEL 0x80000000 134 #define MASTER_TEST_MODE_SHIFT 2 135 #define MASTER_CHIP_REV_SHIFT 16 136 #define MASTER_CHIP_ID_SHIFT 24 137 138 /* Number of ticks per usec for AR813x/AR815x. */ 139 #define ALC_TICK_USECS 2 140 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 141 142 #define ALC_MANUAL_TIMER 0x1404 143 144 #define ALC_IM_TIMER 0x1408 145 #define IM_TIMER_TX_MASK 0x0000FFFF 146 #define IM_TIMER_RX_MASK 0xFFFF0000 147 #define IM_TIMER_TX_SHIFT 0 148 #define IM_TIMER_RX_SHIFT 16 149 #define ALC_IM_TIMER_MIN 0 150 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 151 /* 152 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 153 * interrupts in a second. 154 */ 155 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 156 /* 157 * alc(4) does not rely on Tx completion interrupts, so set it 158 * somewhat large value to reduce Tx completion interrupts. 159 */ 160 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 161 162 #define ALC_GPHY_CFG 0x140C /* 16bits */ 163 #define GPHY_CFG_EXT_RESET 0x0001 164 #define GPHY_CFG_RTL_MODE 0x0002 165 #define GPHY_CFG_LED_MODE 0x0004 166 #define GPHY_CFG_ANEG_NOW 0x0008 167 #define GPHY_CFG_RECV_ANEG 0x0010 168 #define GPHY_CFG_GATE_25M_ENB 0x0020 169 #define GPHY_CFG_LPW_EXIT 0x0040 170 #define GPHY_CFG_PHY_IDDQ 0x0080 171 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 172 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 173 #define GPHY_CFG_HIB_EN 0x0400 174 #define GPHY_CFG_HIB_PULSE 0x0800 175 #define GPHY_CFG_SEL_ANA_RESET 0x1000 176 #define GPHY_CFG_PHY_PLL_ON 0x2000 177 #define GPHY_CFG_PWDOWN_HW 0x4000 178 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 179 180 #define ALC_IDLE_STATUS 0x1410 181 #define IDLE_STATUS_RXMAC 0x00000001 182 #define IDLE_STATUS_TXMAC 0x00000002 183 #define IDLE_STATUS_RXQ 0x00000004 184 #define IDLE_STATUS_TXQ 0x00000008 185 #define IDLE_STATUS_DMARD 0x00000010 186 #define IDLE_STATUS_DMAWR 0x00000020 187 #define IDLE_STATUS_SMB 0x00000040 188 #define IDLE_STATUS_CMB 0x00000080 189 190 #define ALC_MDIO 0x1414 191 #define MDIO_DATA_MASK 0x0000FFFF 192 #define MDIO_REG_ADDR_MASK 0x001F0000 193 #define MDIO_OP_READ 0x00200000 194 #define MDIO_OP_WRITE 0x00000000 195 #define MDIO_SUP_PREAMBLE 0x00400000 196 #define MDIO_OP_EXECUTE 0x00800000 197 #define MDIO_CLK_25_4 0x00000000 198 #define MDIO_CLK_25_6 0x02000000 199 #define MDIO_CLK_25_8 0x03000000 200 #define MDIO_CLK_25_10 0x04000000 201 #define MDIO_CLK_25_14 0x05000000 202 #define MDIO_CLK_25_20 0x06000000 203 #define MDIO_CLK_25_28 0x07000000 204 #define MDIO_OP_BUSY 0x08000000 205 #define MDIO_AP_ENB 0x10000000 206 #define MDIO_DATA_SHIFT 0 207 #define MDIO_REG_ADDR_SHIFT 16 208 209 #define MDIO_REG_ADDR(x) \ 210 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 211 /* Default PHY address. */ 212 #define ALC_PHY_ADDR 0 213 214 #define ALC_PHY_STATUS 0x1418 215 #define PHY_STATUS_RECV_ENB 0x00000001 216 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 217 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 218 #define PHY_STATUS_LPW_STATE 0x80000000 219 #define PHY_STATIS_OE_PWSP_SHIFT 16 220 221 /* Packet memory BIST. */ 222 #define ALC_BIST0 0x141C 223 #define BIST0_ENB 0x00000001 224 #define BIST0_SRAM_FAIL 0x00000002 225 #define BIST0_FUSE_FLAG 0x00000004 226 227 /* PCIe retry buffer BIST. */ 228 #define ALC_BIST1 0x1420 229 #define BIST1_ENB 0x00000001 230 #define BIST1_SRAM_FAIL 0x00000002 231 #define BIST1_FUSE_FLAG 0x00000004 232 233 #define ALC_SERDES_LOCK 0x1424 234 #define SERDES_LOCK_DET 0x00000001 235 #define SERDES_LOCK_DET_ENB 0x00000002 236 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 237 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 238 239 #define ALC_MAC_CFG 0x1480 240 #define MAC_CFG_TX_ENB 0x00000001 241 #define MAC_CFG_RX_ENB 0x00000002 242 #define MAC_CFG_TX_FC 0x00000004 243 #define MAC_CFG_RX_FC 0x00000008 244 #define MAC_CFG_LOOP 0x00000010 245 #define MAC_CFG_FULL_DUPLEX 0x00000020 246 #define MAC_CFG_TX_CRC_ENB 0x00000040 247 #define MAC_CFG_TX_AUTO_PAD 0x00000080 248 #define MAC_CFG_TX_LENCHK 0x00000100 249 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 250 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 251 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 252 #define MAC_CFG_PROMISC 0x00008000 253 #define MAC_CFG_TX_PAUSE 0x00010000 254 #define MAC_CFG_SCNT 0x00020000 255 #define MAC_CFG_SYNC_RST_TX 0x00040000 256 #define MAC_CFG_SIM_RST_TX 0x00080000 257 #define MAC_CFG_SPEED_MASK 0x00300000 258 #define MAC_CFG_SPEED_10_100 0x00100000 259 #define MAC_CFG_SPEED_1000 0x00200000 260 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 261 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 262 #define MAC_CFG_RXCSUM_ENB 0x01000000 263 #define MAC_CFG_ALLMULTI 0x02000000 264 #define MAC_CFG_BCAST 0x04000000 265 #define MAC_CFG_DBG 0x08000000 266 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 267 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 268 #define MAC_CFG_SPEED_MODE_SW 0x40000000 269 #define MAC_CFG_PREAMBLE_SHIFT 10 270 #define MAC_CFG_PREAMBLE_DEFAULT 7 271 272 #define ALC_IPG_IFG_CFG 0x1484 273 #define IPG_IFG_IPGT_MASK 0x0000007F 274 #define IPG_IFG_MIFG_MASK 0x0000FF00 275 #define IPG_IFG_IPG1_MASK 0x007F0000 276 #define IPG_IFG_IPG2_MASK 0x7F000000 277 #define IPG_IFG_IPGT_SHIFT 0 278 #define IPG_IFG_IPGT_DEFAULT 0x60 279 #define IPG_IFG_MIFG_SHIFT 8 280 #define IPG_IFG_MIFG_DEFAULT 0x50 281 #define IPG_IFG_IPG1_SHIFT 16 282 #define IPG_IFG_IPG1_DEFAULT 0x40 283 #define IPG_IFG_IPG2_SHIFT 24 284 #define IPG_IFG_IPG2_DEFAULT 0x60 285 286 /* Station address. */ 287 #define ALC_PAR0 0x1488 288 #define ALC_PAR1 0x148C 289 290 /* 64bit multicast hash register. */ 291 #define ALC_MAR0 0x1490 292 #define ALC_MAR1 0x1494 293 294 /* half-duplex parameter configuration. */ 295 #define ALC_HDPX_CFG 0x1498 296 #define HDPX_CFG_LCOL_MASK 0x000003FF 297 #define HDPX_CFG_RETRY_MASK 0x0000F000 298 #define HDPX_CFG_EXC_DEF_EN 0x00010000 299 #define HDPX_CFG_NO_BACK_C 0x00020000 300 #define HDPX_CFG_NO_BACK_P 0x00040000 301 #define HDPX_CFG_ABEBE 0x00080000 302 #define HDPX_CFG_ABEBT_MASK 0x00F00000 303 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 304 #define HDPX_CFG_LCOL_SHIFT 0 305 #define HDPX_CFG_LCOL_DEFAULT 0x37 306 #define HDPX_CFG_RETRY_SHIFT 12 307 #define HDPX_CFG_RETRY_DEFAULT 0x0F 308 #define HDPX_CFG_ABEBT_SHIFT 20 309 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 310 #define HDPX_CFG_JAMIPG_SHIFT 24 311 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 312 313 #define ALC_FRAME_SIZE 0x149C 314 315 #define ALC_WOL_CFG 0x14A0 316 #define WOL_CFG_PATTERN 0x00000001 317 #define WOL_CFG_PATTERN_ENB 0x00000002 318 #define WOL_CFG_MAGIC 0x00000004 319 #define WOL_CFG_MAGIC_ENB 0x00000008 320 #define WOL_CFG_LINK_CHG 0x00000010 321 #define WOL_CFG_LINK_CHG_ENB 0x00000020 322 #define WOL_CFG_PATTERN_DET 0x00000100 323 #define WOL_CFG_MAGIC_DET 0x00000200 324 #define WOL_CFG_LINK_CHG_DET 0x00000400 325 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 326 #define WOL_CFG_PATTERN0 0x00010000 327 #define WOL_CFG_PATTERN1 0x00020000 328 #define WOL_CFG_PATTERN2 0x00040000 329 #define WOL_CFG_PATTERN3 0x00080000 330 #define WOL_CFG_PATTERN4 0x00100000 331 #define WOL_CFG_PATTERN5 0x00200000 332 #define WOL_CFG_PATTERN6 0x00400000 333 334 /* WOL pattern length. */ 335 #define ALC_PATTERN_CFG0 0x14A4 336 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 337 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 338 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 339 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 340 341 #define ALC_PATTERN_CFG1 0x14A8 342 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 343 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 344 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 345 346 /* RSS */ 347 #define ALC_RSS_KEY0 0x14B0 348 349 #define ALC_RSS_KEY1 0x14B4 350 351 #define ALC_RSS_KEY2 0x14B8 352 353 #define ALC_RSS_KEY3 0x14BC 354 355 #define ALC_RSS_KEY4 0x14C0 356 357 #define ALC_RSS_KEY5 0x14C4 358 359 #define ALC_RSS_KEY6 0x14C8 360 361 #define ALC_RSS_KEY7 0x14CC 362 363 #define ALC_RSS_KEY8 0x14D0 364 365 #define ALC_RSS_KEY9 0x14D4 366 367 #define ALC_RSS_IDT_TABLE0 0x14E0 368 369 #define ALC_RSS_IDT_TABLE1 0x14E4 370 371 #define ALC_RSS_IDT_TABLE2 0x14E8 372 373 #define ALC_RSS_IDT_TABLE3 0x14EC 374 375 #define ALC_RSS_IDT_TABLE4 0x14F0 376 377 #define ALC_RSS_IDT_TABLE5 0x14F4 378 379 #define ALC_RSS_IDT_TABLE6 0x14F8 380 381 #define ALC_RSS_IDT_TABLE7 0x14FC 382 383 #define ALC_SRAM_RD0_ADDR 0x1500 384 385 #define ALC_SRAM_RD1_ADDR 0x1504 386 387 #define ALC_SRAM_RD2_ADDR 0x1508 388 389 #define ALC_SRAM_RD3_ADDR 0x150C 390 391 #define RD_HEAD_ADDR_MASK 0x000003FF 392 #define RD_TAIL_ADDR_MASK 0x03FF0000 393 #define RD_HEAD_ADDR_SHIFT 0 394 #define RD_TAIL_ADDR_SHIFT 16 395 396 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 397 #define RD_NIC_LEN_MASK 0x000003FF 398 399 #define ALC_RD_NIC_LEN1 0x1514 400 401 #define ALC_SRAM_TD_ADDR 0x1518 402 #define TD_HEAD_ADDR_MASK 0x000003FF 403 #define TD_TAIL_ADDR_MASK 0x03FF0000 404 #define TD_HEAD_ADDR_SHIFT 0 405 #define TD_TAIL_ADDR_SHIFT 16 406 407 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 408 #define SRAM_TD_LEN_MASK 0x000003FF 409 410 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 411 412 #define ALC_SRAM_RX_FIFO_LEN 0x1524 413 414 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 415 416 #define ALC_SRAM_TX_FIFO_LEN 0x152C 417 418 #define ALC_SRAM_TCPH_ADDR 0x1530 419 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 420 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 421 #define SRAM_TCPH_ADDR_SHIFT 0 422 #define SRAM_PKTH_ADDR_SHIFT 16 423 424 #define ALC_DMA_BLOCK 0x1534 425 #define DMA_BLOCK_LOAD 0x00000001 426 427 #define ALC_RX_BASE_ADDR_HI 0x1540 428 429 #define ALC_TX_BASE_ADDR_HI 0x1544 430 431 #define ALC_SMB_BASE_ADDR_HI 0x1548 432 433 #define ALC_SMB_BASE_ADDR_LO 0x154C 434 435 #define ALC_RD0_HEAD_ADDR_LO 0x1550 436 437 #define ALC_RD1_HEAD_ADDR_LO 0x1554 438 439 #define ALC_RD2_HEAD_ADDR_LO 0x1558 440 441 #define ALC_RD3_HEAD_ADDR_LO 0x155C 442 443 #define ALC_RD_RING_CNT 0x1560 444 #define RD_RING_CNT_MASK 0x00000FFF 445 #define RD_RING_CNT_SHIFT 0 446 447 #define ALC_RX_BUF_SIZE 0x1564 448 #define RX_BUF_SIZE_MASK 0x0000FFFF 449 /* 450 * If larger buffer size than 1536 is specified the controller 451 * will be locked up. This is hardware limitation. 452 */ 453 #define RX_BUF_SIZE_MAX 1536 454 455 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 456 457 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 458 459 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 460 461 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 462 463 #define ALC_RRD_RING_CNT 0x1578 464 #define RRD_RING_CNT_MASK 0x00000FFF 465 #define RRD_RING_CNT_SHIFT 0 466 467 #define ALC_TDH_HEAD_ADDR_LO 0x157C 468 469 #define ALC_TDL_HEAD_ADDR_LO 0x1580 470 471 #define ALC_TD_RING_CNT 0x1584 472 #define TD_RING_CNT_MASK 0x0000FFFF 473 #define TD_RING_CNT_SHIFT 0 474 475 #define ALC_CMB_BASE_ADDR_LO 0x1588 476 477 #define ALC_TXQ_CFG 0x1590 478 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 479 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 480 #define TXQ_CFG_ENB 0x00000020 481 #define TXQ_CFG_ENHANCED_MODE 0x00000040 482 #define TXQ_CFG_8023_ENB 0x00000080 483 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 484 #define TXQ_CFG_TD_BURST_SHIFT 0 485 #define TXQ_CFG_TD_BURST_DEFAULT 5 486 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 487 488 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 489 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 490 #define TSO_OFFLOAD_THRESH_SHIFT 0 491 #define TSO_OFFLOAD_THRESH_UNIT 8 492 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 493 494 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 495 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 496 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 497 #define TXF_WATER_MARK_BURST_ENB 0x80000000 498 #define TXF_WATER_MARK_LO_SHIFT 0 499 #define TXF_WATER_MARK_HI_SHIFT 16 500 501 #define ALC_THROUGHPUT_MON 0x159C 502 #define THROUGHPUT_MON_RATE_MASK 0x00000003 503 #define THROUGHPUT_MON_ENB 0x00000080 504 #define THROUGHPUT_MON_RATE_SHIFT 0 505 506 #define ALC_RXQ_CFG 0x15A0 507 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 508 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 509 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 510 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 511 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 512 #define RXQ_CFG_QUEUE1_ENB 0x00000010 513 #define RXQ_CFG_QUEUE2_ENB 0x00000020 514 #define RXQ_CFG_QUEUE3_ENB 0x00000040 515 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 516 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 517 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 518 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 519 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 520 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 521 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 522 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 523 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 524 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 525 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 526 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 527 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 528 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 529 #define RXQ_CFG_QUEUE0_ENB 0x80000000 530 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 531 #define RXQ_CFG_RD_BURST_DEFAULT 8 532 #define RXQ_CFG_RD_BURST_SHIFT 20 533 #define RXQ_CFG_ENB \ 534 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 535 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 536 537 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 538 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 539 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 540 #define RX_RD_FREE_THRESH_HI_SHIFT 0 541 #define RX_RD_FREE_THRESH_LO_SHIFT 6 542 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 543 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 544 545 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 546 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 547 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 548 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 549 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 550 551 #define ALC_RD_DMA_CFG 0x15AC 552 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 553 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 554 #define RD_DMA_CFG_THRESH_SHIFT 0 555 #define RD_DMA_CFG_TIMER_SHIFT 16 556 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 557 #define RD_DMA_CFG_TIMER_DEFAULT 0 558 #define RD_DMA_CFG_TICK_USECS 8 559 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 560 561 #define ALC_RSS_HASH_VALUE 0x15B0 562 563 #define ALC_RSS_HASH_FLAG 0x15B4 564 565 #define ALC_RSS_CPU 0x15B8 566 567 #define ALC_DMA_CFG 0x15C0 568 #define DMA_CFG_IN_ORDER 0x00000001 569 #define DMA_CFG_ENH_ORDER 0x00000002 570 #define DMA_CFG_OUT_ORDER 0x00000004 571 #define DMA_CFG_RCB_64 0x00000000 572 #define DMA_CFG_RCB_128 0x00000008 573 #define DMA_CFG_RD_BURST_128 0x00000000 574 #define DMA_CFG_RD_BURST_256 0x00000010 575 #define DMA_CFG_RD_BURST_512 0x00000020 576 #define DMA_CFG_RD_BURST_1024 0x00000030 577 #define DMA_CFG_RD_BURST_2048 0x00000040 578 #define DMA_CFG_RD_BURST_4096 0x00000050 579 #define DMA_CFG_WR_BURST_128 0x00000000 580 #define DMA_CFG_WR_BURST_256 0x00000080 581 #define DMA_CFG_WR_BURST_512 0x00000100 582 #define DMA_CFG_WR_BURST_1024 0x00000180 583 #define DMA_CFG_WR_BURST_2048 0x00000200 584 #define DMA_CFG_WR_BURST_4096 0x00000280 585 #define DMA_CFG_RD_REQ_PRI 0x00000400 586 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 587 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 588 #define DMA_CFG_CMB_ENB 0x00100000 589 #define DMA_CFG_SMB_ENB 0x00200000 590 #define DMA_CFG_CMB_NOW 0x00400000 591 #define DMA_CFG_SMB_DIS 0x01000000 592 #define DMA_CFG_SMB_NOW 0x80000000 593 #define DMA_CFG_RD_BURST_MASK 0x07 594 #define DMA_CFG_RD_BURST_SHIFT 4 595 #define DMA_CFG_WR_BURST_MASK 0x07 596 #define DMA_CFG_WR_BURST_SHIFT 7 597 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 598 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 599 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 600 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 601 602 #define ALC_SMB_STAT_TIMER 0x15C4 603 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 604 #define SMB_STAT_TIMER_SHIFT 0 605 606 #define ALC_CMB_TD_THRESH 0x15C8 607 #define CMB_TD_THRESH_MASK 0x0000FFFF 608 #define CMB_TD_THRESH_SHIFT 0 609 610 #define ALC_CMB_TX_TIMER 0x15CC 611 #define CMB_TX_TIMER_MASK 0x0000FFFF 612 #define CMB_TX_TIMER_SHIFT 0 613 614 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 615 616 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 617 618 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 619 620 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 621 622 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 623 #define MBOX_RD_PROD_SHIFT 0 624 625 #define ALC_MBOX_TD_PROD_IDX 0x15F0 626 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 627 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 628 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 629 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 630 631 #define ALC_MBOX_TD_CONS_IDX 0x15F4 632 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 633 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 634 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 635 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 636 637 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 638 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 639 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 640 #define MBOX_RD0_CONS_IDX_SHIFT 0 641 #define MBOX_RD1_CONS_IDX_SHIFT 16 642 643 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 644 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 645 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 646 #define MBOX_RD2_CONS_IDX_SHIFT 0 647 #define MBOX_RD3_CONS_IDX_SHIFT 16 648 649 #define ALC_INTR_STATUS 0x1600 650 #define INTR_SMB 0x00000001 651 #define INTR_TIMER 0x00000002 652 #define INTR_MANUAL_TIMER 0x00000004 653 #define INTR_RX_FIFO_OFLOW 0x00000008 654 #define INTR_RD0_UNDERRUN 0x00000010 655 #define INTR_RD1_UNDERRUN 0x00000020 656 #define INTR_RD2_UNDERRUN 0x00000040 657 #define INTR_RD3_UNDERRUN 0x00000080 658 #define INTR_TX_FIFO_UNDERRUN 0x00000100 659 #define INTR_DMA_RD_TO_RST 0x00000200 660 #define INTR_DMA_WR_TO_RST 0x00000400 661 #define INTR_TX_CREDIT 0x00000800 662 #define INTR_GPHY 0x00001000 663 #define INTR_GPHY_LOW_PW 0x00002000 664 #define INTR_TXQ_TO_RST 0x00004000 665 #define INTR_TX_PKT 0x00008000 666 #define INTR_RX_PKT0 0x00010000 667 #define INTR_RX_PKT1 0x00020000 668 #define INTR_RX_PKT2 0x00040000 669 #define INTR_RX_PKT3 0x00080000 670 #define INTR_MAC_RX 0x00100000 671 #define INTR_MAC_TX 0x00200000 672 #define INTR_UNDERRUN 0x00400000 673 #define INTR_FRAME_ERROR 0x00800000 674 #define INTR_FRAME_OK 0x01000000 675 #define INTR_CSUM_ERROR 0x02000000 676 #define INTR_PHY_LINK_DOWN 0x04000000 677 #define INTR_DIS_INT 0x80000000 678 679 /* Interrupt Mask Register */ 680 #define ALC_INTR_MASK 0x1604 681 682 #ifdef notyet 683 #define INTR_RX_PKT \ 684 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 685 INTR_RX_PKT3) 686 #define INTR_RD_UNDERRUN \ 687 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 688 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 689 #else 690 #define INTR_RX_PKT INTR_RX_PKT0 691 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 692 #endif 693 694 #define ALC_INTRS \ 695 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 696 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 697 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 698 INTR_TX_FIFO_UNDERRUN) 699 700 #define ALC_INTR_RETRIG_TIMER 0x1608 701 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 702 #define INTR_RETRIG_TIMER_SHIFT 0 703 704 #define ALC_HDS_CFG 0x160C 705 #define HDS_CFG_ENB 0x00000001 706 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 707 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 708 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 709 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 710 711 /* AR813x/AR815x registers for MAC statistics */ 712 #define ALC_RX_MIB_BASE 0x1700 713 714 #define ALC_TX_MIB_BASE 0x1760 715 716 #define ALC_CLK_GATING_CFG 0x1814 717 #define CLK_GATING_DMAW_ENB 0x0001 718 #define CLK_GATING_DMAR_ENB 0x0002 719 #define CLK_GATING_TXQ_ENB 0x0004 720 #define CLK_GATING_RXQ_ENB 0x0008 721 #define CLK_GATING_TXMAC_ENB 0x0010 722 #define CLK_GATING_RXMAC_ENB 0x0020 723 724 #define ALC_DEBUG_DATA0 0x1900 725 726 #define ALC_DEBUG_DATA1 0x1904 727 728 #define ALC_MII_DBG_ADDR 0x1D 729 #define ALC_MII_DBG_DATA 0x1E 730 731 #define MII_ANA_CFG0 0x00 732 #define ANA_RESTART_CAL 0x0001 733 #define ANA_MANUL_SWICH_ON_MASK 0x001E 734 #define ANA_MAN_ENABLE 0x0020 735 #define ANA_SEL_HSP 0x0040 736 #define ANA_EN_HB 0x0080 737 #define ANA_EN_HBIAS 0x0100 738 #define ANA_OEN_125M 0x0200 739 #define ANA_EN_LCKDT 0x0400 740 #define ANA_LCKDT_PHY 0x0800 741 #define ANA_AFE_MODE 0x1000 742 #define ANA_VCO_SLOW 0x2000 743 #define ANA_VCO_FAST 0x4000 744 #define ANA_SEL_CLK125M_DSP 0x8000 745 #define ANA_MANUL_SWICH_ON_SHIFT 1 746 747 #define MII_ANA_CFG4 0x04 748 #define ANA_IECHO_ADJ_MASK 0x0F 749 #define ANA_IECHO_ADJ_3_MASK 0x000F 750 #define ANA_IECHO_ADJ_2_MASK 0x00F0 751 #define ANA_IECHO_ADJ_1_MASK 0x0F00 752 #define ANA_IECHO_ADJ_0_MASK 0xF000 753 #define ANA_IECHO_ADJ_3_SHIFT 0 754 #define ANA_IECHO_ADJ_2_SHIFT 4 755 #define ANA_IECHO_ADJ_1_SHIFT 8 756 #define ANA_IECHO_ADJ_0_SHIFT 12 757 758 #define MII_ANA_CFG5 0x05 759 #define ANA_SERDES_CDR_BW_MASK 0x0003 760 #define ANA_MS_PAD_DBG 0x0004 761 #define ANA_SPEEDUP_DBG 0x0008 762 #define ANA_SERDES_TH_LOS_MASK 0x0030 763 #define ANA_SERDES_EN_DEEM 0x0040 764 #define ANA_SERDES_TXELECIDLE 0x0080 765 #define ANA_SERDES_BEACON 0x0100 766 #define ANA_SERDES_HALFTXDR 0x0200 767 #define ANA_SERDES_SEL_HSP 0x0400 768 #define ANA_SERDES_EN_PLL 0x0800 769 #define ANA_SERDES_EN 0x1000 770 #define ANA_SERDES_EN_LCKDT 0x2000 771 #define ANA_SERDES_CDR_BW_SHIFT 0 772 #define ANA_SERDES_TH_LOS_SHIFT 4 773 774 #define MII_ANA_CFG11 0x0B 775 #define ANA_PS_HIB_EN 0x8000 776 777 #define MII_ANA_CFG18 0x12 778 #define ANA_TEST_MODE_10BT_01MASK 0x0003 779 #define ANA_LOOP_SEL_10BT 0x0004 780 #define ANA_RGMII_MODE_SW 0x0008 781 #define ANA_EN_LONGECABLE 0x0010 782 #define ANA_TEST_MODE_10BT_2 0x0020 783 #define ANA_EN_10BT_IDLE 0x0400 784 #define ANA_EN_MASK_TB 0x0800 785 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 786 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 787 #define ANA_TEST_MODE_10BT_01SHIFT 0 788 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 789 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 790 791 #define MII_ANA_CFG41 0x29 792 #define ANA_TOP_PS_EN 0x8000 793 794 #define MII_ANA_CFG54 0x36 795 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 796 #define ANA_DESERVED 0x0040 797 #define ANA_EN_LIT_CH 0x0080 798 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 799 #define ANA_BP_BAD_LINK_ACCUM 0x4000 800 #define ANA_BP_SMALL_BW 0x8000 801 #define ANA_LONG_CABLE_TH_100_SHIFT 0 802 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 803 804 /* Statistics counters collected by the MAC. */ 805 struct smb { 806 /* Rx stats. */ 807 uint32_t rx_frames; 808 uint32_t rx_bcast_frames; 809 uint32_t rx_mcast_frames; 810 uint32_t rx_pause_frames; 811 uint32_t rx_control_frames; 812 uint32_t rx_crcerrs; 813 uint32_t rx_lenerrs; 814 uint32_t rx_bytes; 815 uint32_t rx_runts; 816 uint32_t rx_fragments; 817 uint32_t rx_pkts_64; 818 uint32_t rx_pkts_65_127; 819 uint32_t rx_pkts_128_255; 820 uint32_t rx_pkts_256_511; 821 uint32_t rx_pkts_512_1023; 822 uint32_t rx_pkts_1024_1518; 823 uint32_t rx_pkts_1519_max; 824 uint32_t rx_pkts_truncated; 825 uint32_t rx_fifo_oflows; 826 uint32_t rx_rrs_errs; 827 uint32_t rx_alignerrs; 828 uint32_t rx_bcast_bytes; 829 uint32_t rx_mcast_bytes; 830 uint32_t rx_pkts_filtered; 831 /* Tx stats. */ 832 uint32_t tx_frames; 833 uint32_t tx_bcast_frames; 834 uint32_t tx_mcast_frames; 835 uint32_t tx_pause_frames; 836 uint32_t tx_excess_defer; 837 uint32_t tx_control_frames; 838 uint32_t tx_deferred; 839 uint32_t tx_bytes; 840 uint32_t tx_pkts_64; 841 uint32_t tx_pkts_65_127; 842 uint32_t tx_pkts_128_255; 843 uint32_t tx_pkts_256_511; 844 uint32_t tx_pkts_512_1023; 845 uint32_t tx_pkts_1024_1518; 846 uint32_t tx_pkts_1519_max; 847 uint32_t tx_single_colls; 848 uint32_t tx_multi_colls; 849 uint32_t tx_late_colls; 850 uint32_t tx_excess_colls; 851 uint32_t tx_underrun; 852 uint32_t tx_desc_underrun; 853 uint32_t tx_lenerrs; 854 uint32_t tx_pkts_truncated; 855 uint32_t tx_bcast_bytes; 856 uint32_t tx_mcast_bytes; 857 uint32_t updated; 858 }; 859 860 /* CMB(Coalesing message block) */ 861 struct cmb { 862 uint32_t cons; 863 }; 864 865 /* Rx free descriptor */ 866 struct rx_desc { 867 uint64_t addr; 868 }; 869 870 /* Rx return descriptor */ 871 struct rx_rdesc { 872 uint32_t rdinfo; 873 #define RRD_CSUM_MASK 0x0000FFFF 874 #define RRD_RD_CNT_MASK 0x000F0000 875 #define RRD_RD_IDX_MASK 0xFFF00000 876 #define RRD_CSUM_SHIFT 0 877 #define RRD_RD_CNT_SHIFT 16 878 #define RRD_RD_IDX_SHIFT 20 879 #define RRD_CSUM(x) \ 880 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 881 #define RRD_RD_CNT(x) \ 882 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 883 #define RRD_RD_IDX(x) \ 884 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 885 uint32_t rss; 886 uint32_t vtag; 887 #define RRD_VLAN_MASK 0x0000FFFF 888 #define RRD_HEAD_LEN_MASK 0x00FF0000 889 #define RRD_HDS_MASK 0x03000000 890 #define RRD_HDS_NONE 0x00000000 891 #define RRD_HDS_HEAD 0x01000000 892 #define RRD_HDS_DATA 0x02000000 893 #define RRD_CPU_MASK 0x0C000000 894 #define RRD_HASH_FLAG_MASK 0xF0000000 895 #define RRD_VLAN_SHIFT 0 896 #define RRD_HEAD_LEN_SHIFT 16 897 #define RRD_HDS_SHIFT 24 898 #define RRD_CPU_SHIFT 26 899 #define RRD_HASH_FLAG_SHIFT 28 900 #define RRD_VLAN(x) \ 901 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 902 #define RRD_HEAD_LEN(x) \ 903 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 904 #define RRD_CPU(x) \ 905 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 906 uint32_t status; 907 #define RRD_LEN_MASK 0x00003FFF 908 #define RRD_LEN_SHIFT 0 909 #define RRD_TCP_UDPCSUM_NOK 0x00004000 910 #define RRD_IPCSUM_NOK 0x00008000 911 #define RRD_VLAN_TAG 0x00010000 912 #define RRD_PROTO_MASK 0x000E0000 913 #define RRD_PROTO_IPV4 0x00020000 914 #define RRD_PROTO_IPV6 0x000C0000 915 #define RRD_ERR_SUM 0x00100000 916 #define RRD_ERR_CRC 0x00200000 917 #define RRD_ERR_ALIGN 0x00400000 918 #define RRD_ERR_TRUNC 0x00800000 919 #define RRD_ERR_RUNT 0x01000000 920 #define RRD_ERR_ICMP 0x02000000 921 #define RRD_BCAST 0x04000000 922 #define RRD_MCAST 0x08000000 923 #define RRD_SNAP_LLC 0x10000000 924 #define RRD_ETHER 0x00000000 925 #define RRD_FIFO_FULL 0x20000000 926 #define RRD_ERR_LENGTH 0x40000000 927 #define RRD_VALID 0x80000000 928 #define RRD_BYTES(x) \ 929 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 930 #define RRD_IPV4(x) \ 931 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 932 }; 933 934 /* Tx descriptor */ 935 struct tx_desc { 936 uint32_t len; 937 #define TD_BUFLEN_MASK 0x00003FFF 938 #define TD_VLAN_MASK 0xFFFF0000 939 #define TD_BUFLEN_SHIFT 0 940 #define TX_BYTES(x) \ 941 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 942 #define TD_VLAN_SHIFT 16 943 uint32_t flags; 944 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 945 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 946 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 947 #define TD_CUSTOM_CSUM 0x00000100 948 #define TD_IPCSUM 0x00000200 949 #define TD_TCPCSUM 0x00000400 950 #define TD_UDPCSUM 0x00000800 951 #define TD_TSO 0x00001000 952 #define TD_TSO_DESCV1 0x00000000 953 #define TD_TSO_DESCV2 0x00002000 954 #define TD_CON_VLAN_TAG 0x00004000 955 #define TD_INS_VLAN_TAG 0x00008000 956 #define TD_IPV4_DESCV2 0x00010000 957 #define TD_LLC_SNAP 0x00020000 958 #define TD_ETHERNET 0x00000000 959 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 960 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 961 #define TD_MSS_MASK 0x7FFC0000 962 #define TD_EOP 0x80000000 963 #define TD_L4HDR_OFFSET_SHIFT 0 964 #define TD_TCPHDR_OFFSET_SHIFT 0 965 #define TD_PLOAD_OFFSET_SHIFT 0 966 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 967 #define TD_MSS_SHIFT 18 968 uint64_t addr; 969 }; 970 971 #define ALC_TX_RING_CNT 256 972 #define ALC_TX_RING_ALIGN sizeof(struct tx_desc) 973 #define ALC_RX_RING_CNT 256 974 #define ALC_RX_RING_ALIGN sizeof(struct rx_desc) 975 #define ALC_RX_BUF_ALIGN 4 976 #define ALC_RR_RING_CNT ALC_RX_RING_CNT 977 #define ALC_RR_RING_ALIGN sizeof(struct rx_rdesc) 978 #define ALC_CMB_ALIGN 8 979 #define ALC_SMB_ALIGN 8 980 981 #define ALC_TSO_MAXSEGSIZE 4096 982 #define ALC_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 983 #define ALC_MAXTXSEGS 32 984 985 #define ALC_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF) 986 #define ALC_ADDR_HI(x) ((uint64_t) (x) >> 32) 987 988 #define ALC_DESC_INC(x, y) ((x) = ((x) + 1) % (y)) 989 990 /* Water mark to kick reclaiming Tx buffers. */ 991 #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) 992 993 #define ALC_MSI_MESSAGES 1 994 #define ALC_MSIX_MESSAGES 1 995 996 #define ALC_TX_RING_SZ \ 997 (sizeof(struct tx_desc) * ALC_TX_RING_CNT) 998 #define ALC_RX_RING_SZ \ 999 (sizeof(struct rx_desc) * ALC_RX_RING_CNT) 1000 #define ALC_RR_RING_SZ \ 1001 (sizeof(struct rx_rdesc) * ALC_RR_RING_CNT) 1002 #define ALC_CMB_SZ (sizeof(struct cmb)) 1003 #define ALC_SMB_SZ (sizeof(struct smb)) 1004 1005 #define ALC_PROC_MIN 16 1006 #define ALC_PROC_MAX (ALC_RX_RING_CNT - 1) 1007 #define ALC_PROC_DEFAULT (ALC_RX_RING_CNT / 4) 1008 1009 /* 1010 * The number of bits reserved for MSS in AR813x/AR815x controllers 1011 * are 13 bits. This limits the maximum interface MTU size in TSO 1012 * case(8191 + sizeof(struct ip) + sizeof(struct tcphdr)) as upper 1013 * stack should not generate TCP segments with MSS greater than the 1014 * limit. Also Atheros says that maximum MTU for TSO is 6KB. 1015 */ 1016 #define ALC_TSO_MTU (6 * 1024) 1017 1018 struct alc_rxdesc { 1019 struct mbuf *rx_m; 1020 bus_dmamap_t rx_dmamap; 1021 struct rx_desc *rx_desc; 1022 }; 1023 1024 struct alc_txdesc { 1025 struct mbuf *tx_m; 1026 bus_dmamap_t tx_dmamap; 1027 }; 1028 1029 struct alc_ring_data { 1030 struct tx_desc *alc_tx_ring; 1031 bus_dma_segment_t alc_tx_ring_seg; 1032 bus_addr_t alc_tx_ring_paddr; 1033 struct rx_desc *alc_rx_ring; 1034 bus_dma_segment_t alc_rx_ring_seg; 1035 bus_addr_t alc_rx_ring_paddr; 1036 struct rx_rdesc *alc_rr_ring; 1037 bus_dma_segment_t alc_rr_ring_seg; 1038 bus_addr_t alc_rr_ring_paddr; 1039 struct cmb *alc_cmb; 1040 bus_dma_segment_t alc_cmb_seg; 1041 bus_addr_t alc_cmb_paddr; 1042 struct smb *alc_smb; 1043 bus_dma_segment_t alc_smb_seg; 1044 bus_addr_t alc_smb_paddr; 1045 }; 1046 1047 struct alc_chain_data { 1048 struct alc_txdesc alc_txdesc[ALC_TX_RING_CNT]; 1049 struct alc_rxdesc alc_rxdesc[ALC_RX_RING_CNT]; 1050 bus_dmamap_t alc_tx_ring_map; 1051 bus_dma_segment_t alc_tx_ring_seg; 1052 bus_dmamap_t alc_rx_ring_map; 1053 bus_dma_segment_t alc_rx_ring_seg; 1054 bus_dmamap_t alc_rr_ring_map; 1055 bus_dma_segment_t alc_rr_ring_seg; 1056 bus_dmamap_t alc_rx_sparemap; 1057 bus_dmamap_t alc_cmb_map; 1058 bus_dma_segment_t alc_cmb_seg; 1059 bus_dmamap_t alc_smb_map; 1060 bus_dma_segment_t alc_smb_seg; 1061 1062 int alc_tx_prod; 1063 int alc_tx_cons; 1064 int alc_tx_cnt; 1065 int alc_rx_cons; 1066 int alc_rr_cons; 1067 int alc_rxlen; 1068 1069 struct mbuf *alc_rxhead; 1070 struct mbuf *alc_rxtail; 1071 struct mbuf *alc_rxprev_tail; 1072 }; 1073 1074 struct alc_hw_stats { 1075 /* Rx stats. */ 1076 uint32_t rx_frames; 1077 uint32_t rx_bcast_frames; 1078 uint32_t rx_mcast_frames; 1079 uint32_t rx_pause_frames; 1080 uint32_t rx_control_frames; 1081 uint32_t rx_crcerrs; 1082 uint32_t rx_lenerrs; 1083 uint64_t rx_bytes; 1084 uint32_t rx_runts; 1085 uint32_t rx_fragments; 1086 uint32_t rx_pkts_64; 1087 uint32_t rx_pkts_65_127; 1088 uint32_t rx_pkts_128_255; 1089 uint32_t rx_pkts_256_511; 1090 uint32_t rx_pkts_512_1023; 1091 uint32_t rx_pkts_1024_1518; 1092 uint32_t rx_pkts_1519_max; 1093 uint32_t rx_pkts_truncated; 1094 uint32_t rx_fifo_oflows; 1095 uint32_t rx_rrs_errs; 1096 uint32_t rx_alignerrs; 1097 uint64_t rx_bcast_bytes; 1098 uint64_t rx_mcast_bytes; 1099 uint32_t rx_pkts_filtered; 1100 /* Tx stats. */ 1101 uint32_t tx_frames; 1102 uint32_t tx_bcast_frames; 1103 uint32_t tx_mcast_frames; 1104 uint32_t tx_pause_frames; 1105 uint32_t tx_excess_defer; 1106 uint32_t tx_control_frames; 1107 uint32_t tx_deferred; 1108 uint64_t tx_bytes; 1109 uint32_t tx_pkts_64; 1110 uint32_t tx_pkts_65_127; 1111 uint32_t tx_pkts_128_255; 1112 uint32_t tx_pkts_256_511; 1113 uint32_t tx_pkts_512_1023; 1114 uint32_t tx_pkts_1024_1518; 1115 uint32_t tx_pkts_1519_max; 1116 uint32_t tx_single_colls; 1117 uint32_t tx_multi_colls; 1118 uint32_t tx_late_colls; 1119 uint32_t tx_excess_colls; 1120 uint32_t tx_underrun; 1121 uint32_t tx_desc_underrun; 1122 uint32_t tx_lenerrs; 1123 uint32_t tx_pkts_truncated; 1124 uint64_t tx_bcast_bytes; 1125 uint64_t tx_mcast_bytes; 1126 }; 1127 1128 /* 1129 * Software state per device. 1130 */ 1131 struct alc_softc { 1132 struct device sc_dev; 1133 struct arpcom sc_arpcom; 1134 1135 bus_space_tag_t sc_mem_bt; 1136 bus_space_handle_t sc_mem_bh; 1137 bus_size_t sc_mem_size; 1138 bus_dma_tag_t sc_dmat; 1139 pci_chipset_tag_t sc_pct; 1140 pcitag_t sc_pcitag; 1141 pci_vendor_id_t sc_product; 1142 1143 void *sc_irq_handle; 1144 1145 struct mii_data sc_miibus; 1146 int alc_rev; 1147 int alc_chip_rev; 1148 int alc_phyaddr; 1149 uint8_t alc_eaddr[ETHER_ADDR_LEN]; 1150 uint32_t alc_max_framelen; 1151 uint32_t alc_dma_rd_burst; 1152 uint32_t alc_dma_wr_burst; 1153 uint32_t alc_rcb; 1154 int alc_expcap; 1155 int alc_flags; 1156 #define ALC_FLAG_PCIE 0x0001 1157 #define ALC_FLAG_PCIX 0x0002 1158 #define ALC_FLAG_PM 0x0010 1159 #define ALC_FLAG_FASTETHER 0x0020 1160 #define ALC_FLAG_JUMBO 0x0040 1161 #define ALC_FLAG_ASPM_MON 0x0080 1162 #define ALC_FLAG_CMB_BUG 0x0100 1163 #define ALC_FLAG_SMB_BUG 0x0200 1164 #define ALC_FLAG_L0S 0x0400 1165 #define ALC_FLAG_L1S 0x0800 1166 #define ALC_FLAG_APS 0x1000 1167 #define ALC_FLAG_DETACH 0x4000 1168 #define ALC_FLAG_LINK 0x8000 1169 1170 struct timeout alc_tick_ch; 1171 struct alc_hw_stats alc_stats; 1172 struct alc_chain_data alc_cdata; 1173 struct alc_ring_data alc_rdata; 1174 int alc_int_rx_mod; 1175 int alc_int_tx_mod; 1176 int alc_buf_size; 1177 }; 1178 1179 /* Register access macros. */ 1180 #define CSR_WRITE_4(_sc, reg, val) \ 1181 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 1182 #define CSR_WRITE_2(_sc, reg, val) \ 1183 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 1184 #define CSR_WRITE_1(_sc, reg, val) \ 1185 bus_space_write_1((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 1186 #define CSR_READ_2(_sc, reg) \ 1187 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 1188 #define CSR_READ_4(_sc, reg) \ 1189 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 1190 1191 #define ALC_RXCHAIN_RESET(_sc) \ 1192 do { \ 1193 (_sc)->alc_cdata.alc_rxhead = NULL; \ 1194 (_sc)->alc_cdata.alc_rxtail = NULL; \ 1195 (_sc)->alc_cdata.alc_rxprev_tail = NULL; \ 1196 (_sc)->alc_cdata.alc_rxlen = 0; \ 1197 } while (0) 1198 1199 #define ALC_TX_TIMEOUT 5 1200 #define ALC_RESET_TIMEOUT 100 1201 #define ALC_TIMEOUT 1000 1202 #define ALC_PHY_TIMEOUT 1000 1203 1204 #endif /* _IF_ALCREG_H */ 1205