1 /* $OpenBSD: if_athn_pci.c,v 1.20 2019/04/23 01:17:09 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * PCI front-end for Atheros 802.11a/g/n chipsets. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/timeout.h> 33 #include <sys/device.h> 34 35 #include <machine/bus.h> 36 #include <machine/intr.h> 37 38 #include <net/if.h> 39 #include <net/if_media.h> 40 41 #include <netinet/in.h> 42 #include <netinet/if_ether.h> 43 44 #include <net80211/ieee80211_var.h> 45 #include <net80211/ieee80211_amrr.h> 46 #include <net80211/ieee80211_mira.h> 47 #include <net80211/ieee80211_radiotap.h> 48 49 #include <dev/ic/athnreg.h> 50 #include <dev/ic/athnvar.h> 51 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcidevs.h> 55 56 #define PCI_SUBSYSID_ATHEROS_COEX2WIRE 0x309b 57 #define PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA 0x30aa 58 #define PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA 0x30ab 59 60 struct athn_pci_softc { 61 struct athn_softc sc_sc; 62 63 /* PCI specific goo. */ 64 pci_chipset_tag_t sc_pc; 65 pcitag_t sc_tag; 66 void *sc_ih; 67 bus_space_tag_t sc_st; 68 bus_space_handle_t sc_sh; 69 bus_size_t sc_mapsize; 70 int sc_cap_off; 71 }; 72 73 int athn_pci_match(struct device *, void *, void *); 74 void athn_pci_attach(struct device *, struct device *, void *); 75 int athn_pci_detach(struct device *, int); 76 int athn_pci_activate(struct device *, int); 77 void athn_pci_wakeup(struct athn_pci_softc *); 78 uint32_t athn_pci_read(struct athn_softc *, uint32_t); 79 void athn_pci_write(struct athn_softc *, uint32_t, uint32_t); 80 void athn_pci_write_barrier(struct athn_softc *); 81 void athn_pci_disable_aspm(struct athn_softc *); 82 83 struct cfattach athn_pci_ca = { 84 sizeof (struct athn_pci_softc), 85 athn_pci_match, 86 athn_pci_attach, 87 athn_pci_detach, 88 athn_pci_activate 89 }; 90 91 static const struct pci_matchid athn_pci_devices[] = { 92 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 }, 93 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 }, 94 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 }, 95 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 }, 96 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 }, 97 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 }, 98 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 }, 99 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 }, 100 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 } 101 }; 102 103 int 104 athn_pci_match(struct device *parent, void *match, void *aux) 105 { 106 return (pci_matchbyid(aux, athn_pci_devices, 107 nitems(athn_pci_devices))); 108 } 109 110 void 111 athn_pci_attach(struct device *parent, struct device *self, void *aux) 112 { 113 struct athn_pci_softc *psc = (struct athn_pci_softc *)self; 114 struct athn_softc *sc = &psc->sc_sc; 115 struct pci_attach_args *pa = aux; 116 const char *intrstr; 117 pci_intr_handle_t ih; 118 pcireg_t memtype, reg; 119 pci_product_id_t subsysid; 120 int error; 121 122 sc->sc_dmat = pa->pa_dmat; 123 psc->sc_pc = pa->pa_pc; 124 psc->sc_tag = pa->pa_tag; 125 126 sc->ops.read = athn_pci_read; 127 sc->ops.write = athn_pci_write; 128 sc->ops.write_barrier = athn_pci_write_barrier; 129 130 /* 131 * Get the offset of the PCI Express Capability Structure in PCI 132 * Configuration Space (Linux hardcodes it as 0x60.) 133 */ 134 error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 135 &psc->sc_cap_off, NULL); 136 if (error != 0) { /* Found. */ 137 sc->sc_disable_aspm = athn_pci_disable_aspm; 138 sc->flags |= ATHN_FLAG_PCIE; 139 } 140 /* 141 * Clear device-specific "PCI retry timeout" register (41h) to prevent 142 * PCI Tx retries from interfering with C3 CPU state. 143 */ 144 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40); 145 if (reg & 0xff00) 146 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00); 147 148 /* 149 * Set the cache line size to a reasonable value if it is 0. 150 * Change latency timer; default value yields poor results. 151 */ 152 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 153 if (PCI_CACHELINE(reg) == 0) { 154 reg &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 155 reg |= 8 << PCI_CACHELINE_SHIFT; 156 } 157 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 158 reg |= 168 << PCI_LATTIMER_SHIFT; 159 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg); 160 161 /* Determine if bluetooth is also supported (combo chip.) */ 162 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 163 subsysid = PCI_PRODUCT(reg); 164 if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA || 165 subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA) 166 sc->flags |= ATHN_FLAG_BTCOEX3WIRE; 167 else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE) 168 sc->flags |= ATHN_FLAG_BTCOEX2WIRE; 169 170 /* Map control/status registers. */ 171 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 172 error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &psc->sc_st, 173 &psc->sc_sh, NULL, &psc->sc_mapsize, 0); 174 if (error != 0) { 175 printf(": can't map mem space\n"); 176 return; 177 } 178 179 if (pci_intr_map(pa, &ih) != 0) { 180 printf(": can't map interrupt\n"); 181 return; 182 } 183 intrstr = pci_intr_string(psc->sc_pc, ih); 184 psc->sc_ih = pci_intr_establish(psc->sc_pc, ih, IPL_NET, 185 athn_intr, sc, sc->sc_dev.dv_xname); 186 if (psc->sc_ih == NULL) { 187 printf(": can't establish interrupt"); 188 if (intrstr != NULL) 189 printf(" at %s", intrstr); 190 printf("\n"); 191 return; 192 } 193 printf(": %s\n", intrstr); 194 195 athn_attach(sc); 196 } 197 198 int 199 athn_pci_detach(struct device *self, int flags) 200 { 201 struct athn_pci_softc *psc = (struct athn_pci_softc *)self; 202 struct athn_softc *sc = &psc->sc_sc; 203 204 if (psc->sc_ih != NULL) { 205 athn_detach(sc); 206 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 207 } 208 if (psc->sc_mapsize > 0) 209 bus_space_unmap(psc->sc_st, psc->sc_sh, psc->sc_mapsize); 210 211 return (0); 212 } 213 214 int 215 athn_pci_activate(struct device *self, int act) 216 { 217 struct athn_pci_softc *psc = (struct athn_pci_softc *)self; 218 struct athn_softc *sc = &psc->sc_sc; 219 220 switch (act) { 221 case DVACT_SUSPEND: 222 athn_suspend(sc); 223 break; 224 case DVACT_WAKEUP: 225 athn_pci_wakeup(psc); 226 break; 227 } 228 229 return (0); 230 } 231 232 void 233 athn_pci_wakeup(struct athn_pci_softc *psc) 234 { 235 struct athn_softc *sc = &psc->sc_sc; 236 pcireg_t reg; 237 int s; 238 239 reg = pci_conf_read(psc->sc_pc, psc->sc_tag, 0x40); 240 if (reg & 0xff00) 241 pci_conf_write(psc->sc_pc, psc->sc_tag, 0x40, reg & ~0xff00); 242 243 s = splnet(); 244 athn_wakeup(sc); 245 splx(s); 246 } 247 248 uint32_t 249 athn_pci_read(struct athn_softc *sc, uint32_t addr) 250 { 251 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 252 253 return (bus_space_read_4(psc->sc_st, psc->sc_sh, addr)); 254 } 255 256 void 257 athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val) 258 { 259 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 260 261 bus_space_write_4(psc->sc_st, psc->sc_sh, addr, val); 262 } 263 264 void 265 athn_pci_write_barrier(struct athn_softc *sc) 266 { 267 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 268 269 bus_space_barrier(psc->sc_st, psc->sc_sh, 0, psc->sc_mapsize, 270 BUS_SPACE_BARRIER_WRITE); 271 } 272 273 void 274 athn_pci_disable_aspm(struct athn_softc *sc) 275 { 276 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 277 pcireg_t reg; 278 279 /* Disable PCIe Active State Power Management (ASPM). */ 280 reg = pci_conf_read(psc->sc_pc, psc->sc_tag, 281 psc->sc_cap_off + PCI_PCIE_LCSR); 282 reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1); 283 pci_conf_write(psc->sc_pc, psc->sc_tag, 284 psc->sc_cap_off + PCI_PCIE_LCSR, reg); 285 } 286