1 /* $OpenBSD: if_athn_pci.c,v 1.18 2015/11/24 17:11:39 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * PCI front-end for Atheros 802.11a/g/n chipsets. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/timeout.h> 33 #include <sys/device.h> 34 35 #include <machine/bus.h> 36 #include <machine/intr.h> 37 38 #include <net/if.h> 39 #include <net/if_media.h> 40 41 #include <netinet/in.h> 42 #include <netinet/if_ether.h> 43 44 #include <net80211/ieee80211_var.h> 45 #include <net80211/ieee80211_amrr.h> 46 #include <net80211/ieee80211_radiotap.h> 47 48 #include <dev/ic/athnreg.h> 49 #include <dev/ic/athnvar.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 55 #define PCI_SUBSYSID_ATHEROS_COEX2WIRE 0x309b 56 #define PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA 0x30aa 57 #define PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA 0x30ab 58 59 struct athn_pci_softc { 60 struct athn_softc sc_sc; 61 62 /* PCI specific goo. */ 63 pci_chipset_tag_t sc_pc; 64 pcitag_t sc_tag; 65 void *sc_ih; 66 bus_space_tag_t sc_st; 67 bus_space_handle_t sc_sh; 68 bus_size_t sc_mapsize; 69 int sc_cap_off; 70 }; 71 72 int athn_pci_match(struct device *, void *, void *); 73 void athn_pci_attach(struct device *, struct device *, void *); 74 int athn_pci_detach(struct device *, int); 75 int athn_pci_activate(struct device *, int); 76 void athn_pci_wakeup(struct athn_pci_softc *); 77 uint32_t athn_pci_read(struct athn_softc *, uint32_t); 78 void athn_pci_write(struct athn_softc *, uint32_t, uint32_t); 79 void athn_pci_write_barrier(struct athn_softc *); 80 void athn_pci_disable_aspm(struct athn_softc *); 81 82 struct cfattach athn_pci_ca = { 83 sizeof (struct athn_pci_softc), 84 athn_pci_match, 85 athn_pci_attach, 86 athn_pci_detach, 87 athn_pci_activate 88 }; 89 90 static const struct pci_matchid athn_pci_devices[] = { 91 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 }, 92 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 }, 93 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 }, 94 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 }, 95 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 }, 96 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 }, 97 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 }, 98 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 }, 99 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 } 100 }; 101 102 int 103 athn_pci_match(struct device *parent, void *match, void *aux) 104 { 105 return (pci_matchbyid(aux, athn_pci_devices, 106 nitems(athn_pci_devices))); 107 } 108 109 void 110 athn_pci_attach(struct device *parent, struct device *self, void *aux) 111 { 112 struct athn_pci_softc *psc = (struct athn_pci_softc *)self; 113 struct athn_softc *sc = &psc->sc_sc; 114 struct pci_attach_args *pa = aux; 115 const char *intrstr; 116 pci_intr_handle_t ih; 117 pcireg_t memtype, reg; 118 pci_product_id_t subsysid; 119 int error; 120 121 sc->sc_dmat = pa->pa_dmat; 122 psc->sc_pc = pa->pa_pc; 123 psc->sc_tag = pa->pa_tag; 124 125 sc->ops.read = athn_pci_read; 126 sc->ops.write = athn_pci_write; 127 sc->ops.write_barrier = athn_pci_write_barrier; 128 129 /* 130 * Get the offset of the PCI Express Capability Structure in PCI 131 * Configuration Space (Linux hardcodes it as 0x60.) 132 */ 133 error = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 134 &psc->sc_cap_off, NULL); 135 if (error != 0) { /* Found. */ 136 sc->sc_disable_aspm = athn_pci_disable_aspm; 137 sc->flags |= ATHN_FLAG_PCIE; 138 } 139 /* 140 * Noone knows why this shit is necessary but there are claims that 141 * not doing this may cause very frequent PCI FATAL interrupts from 142 * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483 143 */ 144 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40); 145 if (reg & 0xff00) 146 pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00); 147 148 /* Change latency timer; default value yields poor results. */ 149 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 150 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 151 reg |= 168 << PCI_LATTIMER_SHIFT; 152 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, reg); 153 154 /* Determine if bluetooth is also supported (combo chip.) */ 155 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 156 subsysid = PCI_PRODUCT(reg); 157 if (subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_SA || 158 subsysid == PCI_SUBSYSID_ATHEROS_COEX3WIRE_DA) 159 sc->flags |= ATHN_FLAG_BTCOEX3WIRE; 160 else if (subsysid == PCI_SUBSYSID_ATHEROS_COEX2WIRE) 161 sc->flags |= ATHN_FLAG_BTCOEX2WIRE; 162 163 /* Map control/status registers. */ 164 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); 165 error = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &psc->sc_st, 166 &psc->sc_sh, NULL, &psc->sc_mapsize, 0); 167 if (error != 0) { 168 printf(": can't map mem space\n"); 169 return; 170 } 171 172 if (pci_intr_map(pa, &ih) != 0) { 173 printf(": can't map interrupt\n"); 174 return; 175 } 176 intrstr = pci_intr_string(psc->sc_pc, ih); 177 psc->sc_ih = pci_intr_establish(psc->sc_pc, ih, IPL_NET, 178 athn_intr, sc, sc->sc_dev.dv_xname); 179 if (psc->sc_ih == NULL) { 180 printf(": can't establish interrupt"); 181 if (intrstr != NULL) 182 printf(" at %s", intrstr); 183 printf("\n"); 184 return; 185 } 186 printf(": %s\n", intrstr); 187 188 athn_attach(sc); 189 } 190 191 int 192 athn_pci_detach(struct device *self, int flags) 193 { 194 struct athn_pci_softc *psc = (struct athn_pci_softc *)self; 195 struct athn_softc *sc = &psc->sc_sc; 196 197 if (psc->sc_ih != NULL) { 198 athn_detach(sc); 199 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 200 } 201 if (psc->sc_mapsize > 0) 202 bus_space_unmap(psc->sc_st, psc->sc_sh, psc->sc_mapsize); 203 204 return (0); 205 } 206 207 int 208 athn_pci_activate(struct device *self, int act) 209 { 210 struct athn_pci_softc *psc = (struct athn_pci_softc *)self; 211 struct athn_softc *sc = &psc->sc_sc; 212 213 switch (act) { 214 case DVACT_SUSPEND: 215 athn_suspend(sc); 216 break; 217 case DVACT_WAKEUP: 218 athn_pci_wakeup(psc); 219 break; 220 } 221 222 return (0); 223 } 224 225 void 226 athn_pci_wakeup(struct athn_pci_softc *psc) 227 { 228 struct athn_softc *sc = &psc->sc_sc; 229 pcireg_t reg; 230 int s; 231 232 reg = pci_conf_read(psc->sc_pc, psc->sc_tag, 0x40); 233 if (reg & 0xff00) 234 pci_conf_write(psc->sc_pc, psc->sc_tag, 0x40, reg & ~0xff00); 235 236 s = splnet(); 237 athn_wakeup(sc); 238 splx(s); 239 } 240 241 uint32_t 242 athn_pci_read(struct athn_softc *sc, uint32_t addr) 243 { 244 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 245 246 return (bus_space_read_4(psc->sc_st, psc->sc_sh, addr)); 247 } 248 249 void 250 athn_pci_write(struct athn_softc *sc, uint32_t addr, uint32_t val) 251 { 252 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 253 254 bus_space_write_4(psc->sc_st, psc->sc_sh, addr, val); 255 } 256 257 void 258 athn_pci_write_barrier(struct athn_softc *sc) 259 { 260 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 261 262 bus_space_barrier(psc->sc_st, psc->sc_sh, 0, psc->sc_mapsize, 263 BUS_SPACE_BARRIER_WRITE); 264 } 265 266 void 267 athn_pci_disable_aspm(struct athn_softc *sc) 268 { 269 struct athn_pci_softc *psc = (struct athn_pci_softc *)sc; 270 pcireg_t reg; 271 272 /* Disable PCIe Active State Power Management (ASPM). */ 273 reg = pci_conf_read(psc->sc_pc, psc->sc_tag, 274 psc->sc_cap_off + PCI_PCIE_LCSR); 275 reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1); 276 pci_conf_write(psc->sc_pc, psc->sc_tag, 277 psc->sc_cap_off + PCI_PCIE_LCSR, reg); 278 } 279