1 /* $OpenBSD: if_bce.c,v 1.28 2009/08/13 14:24:47 jasper Exp $ */ 2 /* $NetBSD: if_bce.c,v 1.3 2003/09/29 01:53:02 mrg Exp $ */ 3 4 /* 5 * Copyright (c) 2003 Clifford Wright. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Broadcom BCM440x 10/100 ethernet (broadcom.com) 33 * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com) 34 * 35 * Cliff Wright cliff@snipe444.org 36 */ 37 38 #include "bpfilter.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/timeout.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 50 #include <net/if.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/ip.h> 59 #include <netinet/if_ether.h> 60 #endif 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcidevs.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/miidevs.h> 72 #include <dev/mii/brgphyreg.h> 73 74 #include <dev/pci/if_bcereg.h> 75 76 #include <uvm/uvm_extern.h> 77 78 /* transmit buffer max frags allowed */ 79 #define BCE_NTXFRAGS 16 80 81 /* ring descriptor */ 82 struct bce_dma_slot { 83 u_int32_t ctrl; 84 u_int32_t addr; 85 }; 86 #define CTRL_BC_MASK 0x1fff /* buffer byte count */ 87 #define CTRL_EOT 0x10000000 /* end of descriptor table */ 88 #define CTRL_IOC 0x20000000 /* interrupt on completion */ 89 #define CTRL_EOF 0x40000000 /* end of frame */ 90 #define CTRL_SOF 0x80000000 /* start of frame */ 91 92 /* Packet status is returned in a pre-packet header */ 93 struct rx_pph { 94 u_int16_t len; 95 u_int16_t flags; 96 u_int16_t pad[12]; 97 }; 98 99 #define BCE_PREPKT_HEADER_SIZE 30 100 101 /* packet status flags bits */ 102 #define RXF_NO 0x8 /* odd number of nibbles */ 103 #define RXF_RXER 0x4 /* receive symbol error */ 104 #define RXF_CRC 0x2 /* crc error */ 105 #define RXF_OV 0x1 /* fifo overflow */ 106 107 /* number of descriptors used in a ring */ 108 #define BCE_NRXDESC 128 109 #define BCE_NTXDESC 128 110 111 /* 112 * Mbuf pointers. We need these to keep track of the virtual addresses 113 * of our mbuf chains since we can only convert from physical to virtual, 114 * not the other way around. 115 */ 116 struct bce_chain_data { 117 struct mbuf *bce_tx_chain[BCE_NTXDESC]; 118 struct mbuf *bce_rx_chain[BCE_NRXDESC]; 119 bus_dmamap_t bce_tx_map[BCE_NTXDESC]; 120 bus_dmamap_t bce_rx_map[BCE_NRXDESC]; 121 }; 122 123 #define BCE_TIMEOUT 100 /* # 10us for mii read/write */ 124 125 struct bce_softc { 126 struct device bce_dev; 127 bus_space_tag_t bce_btag; 128 bus_space_handle_t bce_bhandle; 129 bus_dma_tag_t bce_dmatag; 130 struct arpcom bce_ac; /* interface info */ 131 void *bce_intrhand; 132 struct pci_attach_args bce_pa; 133 struct mii_data bce_mii; 134 u_int32_t bce_phy; /* eeprom indicated phy */ 135 struct bce_dma_slot *bce_rx_ring; /* receive ring */ 136 struct bce_dma_slot *bce_tx_ring; /* transmit ring */ 137 struct bce_chain_data bce_cdata; /* mbufs */ 138 bus_dmamap_t bce_ring_map; 139 u_int32_t bce_intmask; /* current intr mask */ 140 u_int32_t bce_rxin; /* last rx descriptor seen */ 141 u_int32_t bce_txin; /* last tx descriptor seen */ 142 int bce_txsfree; /* no. tx slots available */ 143 int bce_txsnext; /* next available tx slot */ 144 struct timeout bce_timeout; 145 }; 146 147 /* for ring descriptors */ 148 #define BCE_RXBUF_LEN (MCLBYTES - 4) 149 #define BCE_INIT_RXDESC(sc, x) \ 150 do { \ 151 struct bce_dma_slot *__bced = &sc->bce_rx_ring[x]; \ 152 \ 153 *mtod(sc->bce_cdata.bce_rx_chain[x], u_int32_t *) = 0; \ 154 __bced->addr = \ 155 htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr \ 156 + 0x40000000); \ 157 if (x != (BCE_NRXDESC - 1)) \ 158 __bced->ctrl = htole32(BCE_RXBUF_LEN); \ 159 else \ 160 __bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT); \ 161 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, \ 162 sizeof(struct bce_dma_slot) * x, \ 163 sizeof(struct bce_dma_slot), \ 164 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 165 } while (/* CONSTCOND */ 0) 166 167 int bce_probe(struct device *, void *, void *); 168 void bce_attach(struct device *, struct device *, void *); 169 int bce_ioctl(struct ifnet *, u_long, caddr_t); 170 void bce_start(struct ifnet *); 171 void bce_watchdog(struct ifnet *); 172 int bce_intr(void *); 173 void bce_rxintr(struct bce_softc *); 174 void bce_txintr(struct bce_softc *); 175 int bce_init(struct ifnet *); 176 void bce_add_mac(struct bce_softc *, u_int8_t *, unsigned long); 177 int bce_add_rxbuf(struct bce_softc *, int); 178 void bce_rxdrain(struct bce_softc *); 179 void bce_stop(struct ifnet *, int); 180 void bce_reset(struct bce_softc *); 181 void bce_set_filter(struct ifnet *); 182 int bce_mii_read(struct device *, int, int); 183 void bce_mii_write(struct device *, int, int, int); 184 void bce_statchg(struct device *); 185 int bce_mediachange(struct ifnet *); 186 void bce_mediastatus(struct ifnet *, struct ifmediareq *); 187 void bce_tick(void *); 188 189 #ifdef BCE_DEBUG 190 #define DPRINTF(x) do { \ 191 if (bcedebug) \ 192 printf x; \ 193 } while (/* CONSTCOND */ 0) 194 #define DPRINTFN(n,x) do { \ 195 if (bcedebug >= (n)) \ 196 printf x; \ 197 } while (/* CONSTCOND */ 0) 198 int bcedebug = 0; 199 #else 200 #define DPRINTF(x) 201 #define DPRINTFN(n,x) 202 #endif 203 204 struct cfattach bce_ca = { 205 sizeof(struct bce_softc), bce_probe, bce_attach 206 }; 207 struct cfdriver bce_cd = { 208 NULL, "bce", DV_IFNET 209 }; 210 211 const struct pci_matchid bce_devices[] = { 212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401 }, 213 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0 }, 214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B1 } 215 }; 216 217 int 218 bce_probe(struct device *parent, void *match, void *aux) 219 { 220 return (pci_matchbyid((struct pci_attach_args *)aux, bce_devices, 221 sizeof(bce_devices)/sizeof(bce_devices[0]))); 222 } 223 224 void 225 bce_attach(struct device *parent, struct device *self, void *aux) 226 { 227 struct bce_softc *sc = (struct bce_softc *) self; 228 struct pci_attach_args *pa = aux; 229 pci_chipset_tag_t pc = pa->pa_pc; 230 pci_intr_handle_t ih; 231 const char *intrstr = NULL; 232 caddr_t kva; 233 bus_dma_segment_t seg; 234 int rseg; 235 struct ifnet *ifp; 236 pcireg_t memtype; 237 bus_addr_t memaddr; 238 bus_size_t memsize; 239 int pmreg; 240 pcireg_t pmode; 241 int error; 242 int i; 243 244 sc->bce_pa = *pa; 245 sc->bce_dmatag = pa->pa_dmat; 246 247 /* 248 * Map control/status registers. 249 */ 250 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0); 251 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag, 252 &sc->bce_bhandle, &memaddr, &memsize, 0)) { 253 printf(": unable to find mem space\n"); 254 return; 255 } 256 257 /* Get it out of power save mode if needed. */ 258 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) { 259 pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3; 260 if (pmode == 3) { 261 /* 262 * The card has lost all configuration data in 263 * this state, so punt. 264 */ 265 printf(": unable to wake up from power state D3\n"); 266 return; 267 } 268 if (pmode != 0) { 269 printf(": waking up from power state D%d\n", 270 pmode); 271 pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0); 272 } 273 } 274 275 if (pci_intr_map(pa, &ih)) { 276 printf(": couldn't map interrupt\n"); 277 return; 278 } 279 280 intrstr = pci_intr_string(pc, ih); 281 sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc, 282 self->dv_xname); 283 if (sc->bce_intrhand == NULL) { 284 printf(": couldn't establish interrupt"); 285 if (intrstr != NULL) 286 printf(" at %s", intrstr); 287 printf("\n"); 288 return; 289 } 290 291 /* reset the chip */ 292 bce_reset(sc); 293 294 /* 295 * Allocate DMA-safe memory for ring descriptors. 296 * The receive, and transmit rings can not share the same 297 * 4k space, however both are allocated at once here. 298 */ 299 /* 300 * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but 301 * due to the limition above. ?? 302 */ 303 if ((error = bus_dmamem_alloc(sc->bce_dmatag, 304 2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE, 305 &seg, 1, &rseg, BUS_DMA_NOWAIT))) { 306 printf(": unable to alloc space for ring descriptors, " 307 "error = %d\n", error); 308 return; 309 } 310 311 /* map ring space to kernel */ 312 if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg, 313 2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) { 314 printf(": unable to map DMA buffers, error = %d\n", 315 error); 316 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 317 return; 318 } 319 320 /* create a dma map for the ring */ 321 if ((error = bus_dmamap_create(sc->bce_dmatag, 322 2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT, 323 &sc->bce_ring_map))) { 324 printf(": unable to create ring DMA map, error = %d\n", 325 error); 326 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 327 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 328 return; 329 } 330 331 /* connect the ring space to the dma map */ 332 if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva, 333 2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) { 334 printf(": unable to load ring DMA map\n"); 335 bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map); 336 bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE); 337 bus_dmamem_free(sc->bce_dmatag, &seg, rseg); 338 return; 339 } 340 341 /* save the ring space in softc */ 342 sc->bce_rx_ring = (struct bce_dma_slot *) kva; 343 sc->bce_tx_ring = (struct bce_dma_slot *) (kva + PAGE_SIZE); 344 345 /* Create the transmit buffer DMA maps. */ 346 for (i = 0; i < BCE_NTXDESC; i++) { 347 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 348 BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) { 349 printf(": unable to create tx DMA map, error = %d\n", 350 error); 351 } 352 sc->bce_cdata.bce_tx_chain[i] = NULL; 353 } 354 355 /* Create the receive buffer DMA maps. */ 356 for (i = 0; i < BCE_NRXDESC; i++) { 357 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) { 359 printf(": unable to create rx DMA map, error = %d\n", 360 error); 361 } 362 sc->bce_cdata.bce_rx_chain[i] = NULL; 363 } 364 365 /* Set up ifnet structure */ 366 ifp = &sc->bce_ac.ac_if; 367 strlcpy(ifp->if_xname, sc->bce_dev.dv_xname, IF_NAMESIZE); 368 ifp->if_softc = sc; 369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 370 ifp->if_ioctl = bce_ioctl; 371 ifp->if_start = bce_start; 372 ifp->if_watchdog = bce_watchdog; 373 ifp->if_init = bce_init; 374 IFQ_SET_READY(&ifp->if_snd); 375 376 ifp->if_capabilities = IFCAP_VLAN_MTU; 377 378 /* MAC address */ 379 sc->bce_ac.ac_enaddr[0] = 380 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET0); 381 sc->bce_ac.ac_enaddr[1] = 382 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET1); 383 sc->bce_ac.ac_enaddr[2] = 384 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET2); 385 sc->bce_ac.ac_enaddr[3] = 386 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET3); 387 sc->bce_ac.ac_enaddr[4] = 388 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET4); 389 sc->bce_ac.ac_enaddr[5] = 390 bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET5); 391 392 printf(": %s, address %s\n", intrstr, 393 ether_sprintf(sc->bce_ac.ac_enaddr)); 394 395 /* Initialize our media structures and probe the MII. */ 396 sc->bce_mii.mii_ifp = ifp; 397 sc->bce_mii.mii_readreg = bce_mii_read; 398 sc->bce_mii.mii_writereg = bce_mii_write; 399 sc->bce_mii.mii_statchg = bce_statchg; 400 ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange, 401 bce_mediastatus); 402 mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY, 403 MII_OFFSET_ANY, 0); 404 if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) { 405 ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 406 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE); 407 } else 408 ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO); 409 410 /* get the phy */ 411 sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle, 412 BCE_PHY) & 0x1f; 413 414 /* 415 * Enable activity led. 416 * XXX This should be in a phy driver, but not currently. 417 */ 418 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 419 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 420 421 /* enable traffic meter led mode */ 422 bce_mii_write((struct device *) sc, 1, 27, /* MAGIC */ 423 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 424 425 /* Attach the interface */ 426 if_attach(ifp); 427 ether_ifattach(ifp); 428 429 timeout_set(&sc->bce_timeout, bce_tick, sc); 430 } 431 432 /* handle media, and ethernet requests */ 433 int 434 bce_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 435 { 436 struct bce_softc *sc = ifp->if_softc; 437 struct ifaddr *ifa = (struct ifaddr *) data; 438 struct ifreq *ifr = (struct ifreq *) data; 439 int s, error = 0; 440 441 s = splnet(); 442 443 switch (cmd) { 444 case SIOCSIFADDR: 445 ifp->if_flags |= IFF_UP; 446 447 switch (ifa->ifa_addr->sa_family) { 448 #ifdef INET 449 case AF_INET: 450 bce_init(ifp); 451 arp_ifinit(&sc->bce_ac, ifa); 452 break; 453 #endif /* INET */ 454 default: 455 bce_init(ifp); 456 break; 457 } 458 break; 459 460 case SIOCSIFFLAGS: 461 if(ifp->if_flags & IFF_UP) 462 if(ifp->if_flags & IFF_RUNNING) 463 bce_set_filter(ifp); 464 else 465 bce_init(ifp); 466 else if(ifp->if_flags & IFF_RUNNING) 467 bce_stop(ifp, 0); 468 469 break; 470 471 case SIOCSIFMEDIA: 472 case SIOCGIFMEDIA: 473 error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd); 474 break; 475 476 default: 477 error = ether_ioctl(ifp, &sc->bce_ac, cmd, data); 478 } 479 480 if (error == ENETRESET) { 481 if (ifp->if_flags & IFF_RUNNING) 482 bce_set_filter(ifp); 483 error = 0; 484 } 485 486 if (error == 0) { 487 /* Try to get more packets going. */ 488 bce_start(ifp); 489 } 490 491 splx(s); 492 return error; 493 } 494 495 /* Start packet transmission on the interface. */ 496 void 497 bce_start(struct ifnet *ifp) 498 { 499 struct bce_softc *sc = ifp->if_softc; 500 struct mbuf *m0; 501 bus_dmamap_t dmamap; 502 int txstart; 503 int txsfree; 504 int newpkts = 0; 505 int error; 506 507 /* 508 * do not start another if currently transmitting, and more 509 * descriptors(tx slots) are needed for next packet. 510 */ 511 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 512 return; 513 514 /* determine number of descriptors available */ 515 if (sc->bce_txsnext >= sc->bce_txin) 516 txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext; 517 else 518 txsfree = sc->bce_txin - sc->bce_txsnext - 1; 519 520 /* 521 * Loop through the send queue, setting up transmit descriptors 522 * until we drain the queue, or use up all available transmit 523 * descriptors. 524 */ 525 while (txsfree > 0) { 526 int seg; 527 528 /* Grab a packet off the queue. */ 529 IFQ_POLL(&ifp->if_snd, m0); 530 if (m0 == NULL) 531 break; 532 533 /* get the transmit slot dma map */ 534 dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext]; 535 536 /* 537 * Load the DMA map. If this fails, the packet either 538 * didn't fit in the alloted number of segments, or we 539 * were short on resources. If the packet will not fit, 540 * it will be dropped. If short on resources, it will 541 * be tried again later. 542 */ 543 error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0, 544 BUS_DMA_WRITE | BUS_DMA_NOWAIT); 545 if (error == EFBIG) { 546 printf("%s: Tx packet consumes too many DMA segments, " 547 "dropping...\n", sc->bce_dev.dv_xname); 548 IFQ_DEQUEUE(&ifp->if_snd, m0); 549 m_freem(m0); 550 ifp->if_oerrors++; 551 continue; 552 } else if (error) { 553 /* short on resources, come back later */ 554 printf("%s: unable to load Tx buffer, error = %d\n", 555 sc->bce_dev.dv_xname, error); 556 break; 557 } 558 /* If not enough descriptors available, try again later */ 559 if (dmamap->dm_nsegs > txsfree) { 560 ifp->if_flags |= IFF_OACTIVE; 561 bus_dmamap_unload(sc->bce_dmatag, dmamap); 562 break; 563 } 564 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */ 565 566 /* So take it off the queue */ 567 IFQ_DEQUEUE(&ifp->if_snd, m0); 568 569 /* save the pointer so it can be freed later */ 570 sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0; 571 572 /* Sync the data DMA map. */ 573 bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize, 574 BUS_DMASYNC_PREWRITE); 575 576 /* Initialize the transmit descriptor(s). */ 577 txstart = sc->bce_txsnext; 578 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 579 u_int32_t ctrl; 580 581 ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK; 582 if (seg == 0) 583 ctrl |= CTRL_SOF; 584 if (seg == dmamap->dm_nsegs - 1) 585 ctrl |= CTRL_EOF; 586 if (sc->bce_txsnext == BCE_NTXDESC - 1) 587 ctrl |= CTRL_EOT; 588 ctrl |= CTRL_IOC; 589 sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl); 590 sc->bce_tx_ring[sc->bce_txsnext].addr = 591 htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */ 592 if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1) 593 sc->bce_txsnext = 0; 594 else 595 sc->bce_txsnext++; 596 txsfree--; 597 } 598 /* sync descriptors being used */ 599 bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map, 600 sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE, 601 sizeof(struct bce_dma_slot) * dmamap->dm_nsegs, 602 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 603 604 /* Give the packet to the chip. */ 605 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR, 606 sc->bce_txsnext * sizeof(struct bce_dma_slot)); 607 608 newpkts++; 609 610 #if NBPFILTER > 0 611 /* Pass the packet to any BPF listeners. */ 612 if (ifp->if_bpf) 613 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 614 #endif /* NBPFILTER > 0 */ 615 } 616 if (txsfree == 0) { 617 /* No more slots left; notify upper layer. */ 618 ifp->if_flags |= IFF_OACTIVE; 619 } 620 if (newpkts) { 621 /* Set a watchdog timer in case the chip flakes out. */ 622 ifp->if_timer = 5; 623 } 624 } 625 626 /* Watchdog timer handler. */ 627 void 628 bce_watchdog(struct ifnet *ifp) 629 { 630 struct bce_softc *sc = ifp->if_softc; 631 632 printf("%s: device timeout\n", sc->bce_dev.dv_xname); 633 ifp->if_oerrors++; 634 635 (void) bce_init(ifp); 636 637 /* Try to get more packets going. */ 638 bce_start(ifp); 639 } 640 641 int 642 bce_intr(void *xsc) 643 { 644 struct bce_softc *sc; 645 struct ifnet *ifp; 646 u_int32_t intstatus; 647 int wantinit; 648 int handled = 0; 649 650 sc = xsc; 651 ifp = &sc->bce_ac.ac_if; 652 653 654 for (wantinit = 0; wantinit == 0;) { 655 intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 656 BCE_INT_STS); 657 658 /* ignore if not ours, or unsolicited interrupts */ 659 intstatus &= sc->bce_intmask; 660 if (intstatus == 0) 661 break; 662 663 handled = 1; 664 665 /* Ack interrupt */ 666 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS, 667 intstatus); 668 669 /* Receive interrupts. */ 670 if (intstatus & I_RI) 671 bce_rxintr(sc); 672 /* Transmit interrupts. */ 673 if (intstatus & I_XI) 674 bce_txintr(sc); 675 /* Error interrupts */ 676 if (intstatus & ~(I_RI | I_XI)) { 677 if (intstatus & I_XU) 678 printf("%s: transmit fifo underflow\n", 679 sc->bce_dev.dv_xname); 680 if (intstatus & I_RO) { 681 printf("%s: receive fifo overflow\n", 682 sc->bce_dev.dv_xname); 683 ifp->if_ierrors++; 684 } 685 if (intstatus & I_RU) 686 printf("%s: receive descriptor underflow\n", 687 sc->bce_dev.dv_xname); 688 if (intstatus & I_DE) 689 printf("%s: descriptor protocol error\n", 690 sc->bce_dev.dv_xname); 691 if (intstatus & I_PD) 692 printf("%s: data error\n", 693 sc->bce_dev.dv_xname); 694 if (intstatus & I_PC) 695 printf("%s: descriptor error\n", 696 sc->bce_dev.dv_xname); 697 if (intstatus & I_TO) 698 printf("%s: general purpose timeout\n", 699 sc->bce_dev.dv_xname); 700 wantinit = 1; 701 } 702 } 703 704 if (handled) { 705 if (wantinit) 706 bce_init(ifp); 707 /* Try to get more packets going. */ 708 bce_start(ifp); 709 } 710 return (handled); 711 } 712 713 /* Receive interrupt handler */ 714 void 715 bce_rxintr(struct bce_softc *sc) 716 { 717 struct ifnet *ifp = &sc->bce_ac.ac_if; 718 struct rx_pph *pph; 719 struct mbuf *m; 720 int curr; 721 int len; 722 int i; 723 724 /* get pointer to active receive slot */ 725 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS) 726 & RS_CD_MASK; 727 curr = curr / sizeof(struct bce_dma_slot); 728 if (curr >= BCE_NRXDESC) 729 curr = BCE_NRXDESC - 1; 730 731 /* process packets up to but not current packet being worked on */ 732 for (i = sc->bce_rxin; i != curr; 733 i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) { 734 /* complete any post dma memory ops on packet */ 735 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0, 736 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 737 BUS_DMASYNC_POSTREAD); 738 739 /* 740 * If the packet had an error, simply recycle the buffer, 741 * resetting the len, and flags. 742 */ 743 pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *); 744 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) { 745 ifp->if_ierrors++; 746 pph->len = 0; 747 pph->flags = 0; 748 continue; 749 } 750 /* receive the packet */ 751 len = pph->len; 752 if (len == 0) 753 continue; /* no packet if empty */ 754 pph->len = 0; 755 pph->flags = 0; 756 /* bump past pre header to packet */ 757 sc->bce_cdata.bce_rx_chain[i]->m_data += 758 BCE_PREPKT_HEADER_SIZE; 759 760 /* 761 * The chip includes the CRC with every packet. Trim 762 * it off here. 763 */ 764 len -= ETHER_CRC_LEN; 765 766 /* 767 * If the packet is small enough to fit in a 768 * single header mbuf, allocate one and copy 769 * the data into it. This greatly reduces 770 * memory consumption when receiving lots 771 * of small packets. 772 * 773 * Otherwise, add a new buffer to the receive 774 * chain. If this fails, drop the packet and 775 * recycle the old buffer. 776 */ 777 if (len <= (MHLEN - 2)) { 778 MGETHDR(m, M_DONTWAIT, MT_DATA); 779 if (m == NULL) 780 goto dropit; 781 m->m_data += 2; 782 memcpy(mtod(m, caddr_t), 783 mtod(sc->bce_cdata.bce_rx_chain[i], caddr_t), len); 784 sc->bce_cdata.bce_rx_chain[i]->m_data -= 785 BCE_PREPKT_HEADER_SIZE; 786 } else { 787 m = sc->bce_cdata.bce_rx_chain[i]; 788 if (bce_add_rxbuf(sc, i) != 0) { 789 dropit: 790 ifp->if_ierrors++; 791 /* continue to use old buffer */ 792 sc->bce_cdata.bce_rx_chain[i]->m_data -= 793 BCE_PREPKT_HEADER_SIZE; 794 bus_dmamap_sync(sc->bce_dmatag, 795 sc->bce_cdata.bce_rx_map[i], 0, 796 sc->bce_cdata.bce_rx_map[i]->dm_mapsize, 797 BUS_DMASYNC_PREREAD); 798 continue; 799 } 800 } 801 802 m->m_pkthdr.rcvif = ifp; 803 m->m_pkthdr.len = m->m_len = len; 804 ifp->if_ipackets++; 805 806 #if NBPFILTER > 0 807 /* 808 * Pass this up to any BPF listeners, but only 809 * pass it up the stack if it's for us. 810 */ 811 if (ifp->if_bpf) 812 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 813 #endif /* NBPFILTER > 0 */ 814 815 /* Pass it on. */ 816 ether_input_mbuf(ifp, m); 817 818 /* re-check current in case it changed */ 819 curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 820 BCE_DMA_RXSTATUS) & RS_CD_MASK) / 821 sizeof(struct bce_dma_slot); 822 if (curr >= BCE_NRXDESC) 823 curr = BCE_NRXDESC - 1; 824 } 825 sc->bce_rxin = curr; 826 } 827 828 /* Transmit interrupt handler */ 829 void 830 bce_txintr(struct bce_softc *sc) 831 { 832 struct ifnet *ifp = &sc->bce_ac.ac_if; 833 int curr; 834 int i; 835 836 ifp->if_flags &= ~IFF_OACTIVE; 837 838 /* 839 * Go through the Tx list and free mbufs for those 840 * frames which have been transmitted. 841 */ 842 curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) & 843 RS_CD_MASK; 844 curr = curr / sizeof(struct bce_dma_slot); 845 if (curr >= BCE_NTXDESC) 846 curr = BCE_NTXDESC - 1; 847 for (i = sc->bce_txin; i != curr; 848 i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) { 849 /* do any post dma memory ops on transmit data */ 850 if (sc->bce_cdata.bce_tx_chain[i] == NULL) 851 continue; 852 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0, 853 sc->bce_cdata.bce_tx_map[i]->dm_mapsize, 854 BUS_DMASYNC_POSTWRITE); 855 bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]); 856 m_freem(sc->bce_cdata.bce_tx_chain[i]); 857 sc->bce_cdata.bce_tx_chain[i] = NULL; 858 ifp->if_opackets++; 859 } 860 sc->bce_txin = curr; 861 862 /* 863 * If there are no more pending transmissions, cancel the watchdog 864 * timer 865 */ 866 if (sc->bce_txsnext == sc->bce_txin) 867 ifp->if_timer = 0; 868 } 869 870 /* initialize the interface */ 871 int 872 bce_init(struct ifnet *ifp) 873 { 874 struct bce_softc *sc = ifp->if_softc; 875 u_int32_t reg_win; 876 int error; 877 int i; 878 879 /* Cancel any pending I/O. */ 880 bce_stop(ifp, 0); 881 882 /* enable pci inerrupts, bursts, and prefetch */ 883 884 /* remap the pci registers to the Sonics config registers */ 885 886 /* save the current map, so it can be restored */ 887 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 888 BCE_REG_WIN); 889 890 /* set register window to Sonics registers */ 891 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 892 BCE_SONICS_WIN); 893 894 /* enable SB to PCI interrupt */ 895 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 896 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) | 897 SBIV_ENET0); 898 899 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 900 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 901 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) | 902 SBTOPCI_PREF | SBTOPCI_BURST); 903 904 /* restore to ethernet register space */ 905 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 906 reg_win); 907 908 /* Reset the chip to a known state. */ 909 bce_reset(sc); 910 911 /* Initialize transmit descriptors */ 912 memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot)); 913 sc->bce_txsnext = 0; 914 sc->bce_txin = 0; 915 916 /* enable crc32 generation and set proper LED modes */ 917 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 918 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) | 919 BCE_EMC_CRC32_ENAB | BCE_EMC_LED); 920 921 /* reset or clear powerdown control bit */ 922 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL, 923 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) & 924 ~BCE_EMC_PDOWN); 925 926 /* setup DMA interrupt control */ 927 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24); /* MAGIC */ 928 929 /* setup packet filter */ 930 bce_set_filter(ifp); 931 932 /* set max frame length, account for possible VLAN tag */ 933 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX, 934 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 935 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX, 936 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 937 938 /* set tx watermark */ 939 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56); 940 941 /* enable transmit */ 942 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE); 943 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR, 944 sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000); /* MAGIC */ 945 946 /* 947 * Give the receive ring to the chip, and 948 * start the receive DMA engine. 949 */ 950 sc->bce_rxin = 0; 951 952 /* clear the rx descriptor ring */ 953 memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot)); 954 /* enable receive */ 955 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 956 BCE_PREPKT_HEADER_SIZE << 1 | XC_XE); 957 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR, 958 sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000); /* MAGIC */ 959 960 /* Initialize receive descriptors */ 961 for (i = 0; i < BCE_NRXDESC; i++) { 962 if (sc->bce_cdata.bce_rx_chain[i] == NULL) { 963 if ((error = bce_add_rxbuf(sc, i)) != 0) { 964 printf("%s: unable to allocate or map rx(%d) " 965 "mbuf, error = %d\n", sc->bce_dev.dv_xname, 966 i, error); 967 bce_rxdrain(sc); 968 return (error); 969 } 970 } else 971 BCE_INIT_RXDESC(sc, i); 972 } 973 974 /* Enable interrupts */ 975 sc->bce_intmask = 976 I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO; 977 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 978 sc->bce_intmask); 979 980 /* start the receive dma */ 981 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR, 982 BCE_NRXDESC * sizeof(struct bce_dma_slot)); 983 984 /* set media */ 985 mii_mediachg(&sc->bce_mii); 986 987 /* turn on the ethernet mac */ 988 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 989 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 990 BCE_ENET_CTL) | EC_EE); 991 992 /* start timer */ 993 timeout_add_sec(&sc->bce_timeout, 1); 994 995 /* mark as running, and no outputs active */ 996 ifp->if_flags |= IFF_RUNNING; 997 ifp->if_flags &= ~IFF_OACTIVE; 998 999 return 0; 1000 } 1001 1002 /* add a mac address to packet filter */ 1003 void 1004 bce_add_mac(struct bce_softc *sc, u_int8_t *mac, unsigned long idx) 1005 { 1006 int i; 1007 u_int32_t rval; 1008 1009 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW, 1010 mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]); 1011 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI, 1012 mac[0] << 8 | mac[1] | 0x10000); /* MAGIC */ 1013 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1014 idx << 16 | 8); /* MAGIC */ 1015 /* wait for write to complete */ 1016 for (i = 0; i < 100; i++) { 1017 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1018 BCE_FILT_CTL); 1019 if (!(rval & 0x80000000)) /* MAGIC */ 1020 break; 1021 delay(10); 1022 } 1023 if (i == 100) { 1024 printf("%s: timed out writing pkt filter ctl\n", 1025 sc->bce_dev.dv_xname); 1026 } 1027 } 1028 1029 /* Add a receive buffer to the indiciated descriptor. */ 1030 int 1031 bce_add_rxbuf(struct bce_softc *sc, int idx) 1032 { 1033 struct mbuf *m; 1034 int error; 1035 1036 MGETHDR(m, M_DONTWAIT, MT_DATA); 1037 if (m == NULL) 1038 return (ENOBUFS); 1039 1040 MCLGET(m, M_DONTWAIT); 1041 if ((m->m_flags & M_EXT) == 0) { 1042 m_freem(m); 1043 return (ENOBUFS); 1044 } 1045 if (sc->bce_cdata.bce_rx_chain[idx] != NULL) 1046 bus_dmamap_unload(sc->bce_dmatag, 1047 sc->bce_cdata.bce_rx_map[idx]); 1048 1049 sc->bce_cdata.bce_rx_chain[idx] = m; 1050 1051 error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 1052 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1053 BUS_DMA_READ | BUS_DMA_NOWAIT); 1054 if (error) 1055 return (error); 1056 1057 bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0, 1058 sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD); 1059 1060 BCE_INIT_RXDESC(sc, idx); 1061 1062 return (0); 1063 1064 } 1065 1066 /* Drain the receive queue. */ 1067 void 1068 bce_rxdrain(struct bce_softc *sc) 1069 { 1070 int i; 1071 1072 for (i = 0; i < BCE_NRXDESC; i++) { 1073 if (sc->bce_cdata.bce_rx_chain[i] != NULL) { 1074 bus_dmamap_unload(sc->bce_dmatag, 1075 sc->bce_cdata.bce_rx_map[i]); 1076 m_freem(sc->bce_cdata.bce_rx_chain[i]); 1077 sc->bce_cdata.bce_rx_chain[i] = NULL; 1078 } 1079 } 1080 } 1081 1082 /* Stop transmission on the interface */ 1083 void 1084 bce_stop(struct ifnet *ifp, int disable) 1085 { 1086 struct bce_softc *sc = ifp->if_softc; 1087 int i; 1088 u_int32_t val; 1089 1090 /* Stop the 1 second timer */ 1091 timeout_del(&sc->bce_timeout); 1092 1093 /* Mark the interface down and cancel the watchdog timer. */ 1094 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1095 ifp->if_timer = 0; 1096 1097 /* Down the MII. */ 1098 mii_down(&sc->bce_mii); 1099 1100 /* Disable interrupts. */ 1101 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0); 1102 sc->bce_intmask = 0; 1103 delay(10); 1104 1105 /* Disable emac */ 1106 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED); 1107 for (i = 0; i < 200; i++) { 1108 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1109 BCE_ENET_CTL); 1110 if (!(val & EC_ED)) 1111 break; 1112 delay(10); 1113 } 1114 1115 /* Stop the DMA */ 1116 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0); 1117 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1118 delay(10); 1119 1120 /* Release any queued transmit buffers. */ 1121 for (i = 0; i < BCE_NTXDESC; i++) { 1122 if (sc->bce_cdata.bce_tx_chain[i] != NULL) { 1123 bus_dmamap_unload(sc->bce_dmatag, 1124 sc->bce_cdata.bce_tx_map[i]); 1125 m_freem(sc->bce_cdata.bce_tx_chain[i]); 1126 sc->bce_cdata.bce_tx_chain[i] = NULL; 1127 } 1128 } 1129 1130 /* drain receive queue */ 1131 if (disable) 1132 bce_rxdrain(sc); 1133 } 1134 1135 /* reset the chip */ 1136 void 1137 bce_reset(struct bce_softc *sc) 1138 { 1139 u_int32_t val; 1140 u_int32_t sbval; 1141 int i; 1142 1143 /* if SB core is up */ 1144 sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1145 BCE_SBTMSTATELOW); 1146 if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) { 1147 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1148 0); 1149 1150 /* disable emac */ 1151 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1152 EC_ED); 1153 for (i = 0; i < 200; i++) { 1154 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1155 BCE_ENET_CTL); 1156 if (!(val & EC_ED)) 1157 break; 1158 delay(10); 1159 } 1160 if (i == 200) 1161 printf("%s: timed out disabling ethernet mac\n", 1162 sc->bce_dev.dv_xname); 1163 1164 /* reset the dma engines */ 1165 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0); 1166 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS); 1167 /* if error on receive, wait to go idle */ 1168 if (val & RS_ERROR) { 1169 for (i = 0; i < 100; i++) { 1170 val = bus_space_read_4(sc->bce_btag, 1171 sc->bce_bhandle, BCE_DMA_RXSTATUS); 1172 if (val & RS_DMA_IDLE) 1173 break; 1174 delay(10); 1175 } 1176 if (i == 100) 1177 printf("%s: receive dma did not go idle after" 1178 " error\n", sc->bce_dev.dv_xname); 1179 } 1180 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1181 BCE_DMA_RXSTATUS, 0); 1182 1183 /* reset ethernet mac */ 1184 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, 1185 EC_ES); 1186 for (i = 0; i < 200; i++) { 1187 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1188 BCE_ENET_CTL); 1189 if (!(val & EC_ES)) 1190 break; 1191 delay(10); 1192 } 1193 if (i == 200) 1194 printf("%s: timed out resetting ethernet mac\n", 1195 sc->bce_dev.dv_xname); 1196 } else { 1197 u_int32_t reg_win; 1198 1199 /* remap the pci registers to the Sonics config registers */ 1200 1201 /* save the current map, so it can be restored */ 1202 reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1203 BCE_REG_WIN); 1204 /* set register window to Sonics registers */ 1205 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, 1206 BCE_REG_WIN, BCE_SONICS_WIN); 1207 1208 /* enable SB to PCI interrupt */ 1209 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC, 1210 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1211 BCE_SBINTVEC) | 1212 SBIV_ENET0); 1213 1214 /* enable prefetch and bursts for sonics-to-pci translation 2 */ 1215 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2, 1216 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1217 BCE_SPCI_TR2) | 1218 SBTOPCI_PREF | SBTOPCI_BURST); 1219 1220 /* restore to ethernet register space */ 1221 pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN, 1222 reg_win); 1223 } 1224 1225 /* disable SB core if not in reset */ 1226 if (!(sbval & SBTML_RESET)) { 1227 1228 /* set the reject bit */ 1229 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1230 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK); 1231 for (i = 0; i < 200; i++) { 1232 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1233 BCE_SBTMSTATELOW); 1234 if (val & SBTML_REJ) 1235 break; 1236 delay(1); 1237 } 1238 if (i == 200) 1239 printf("%s: while resetting core, reject did not set\n", 1240 sc->bce_dev.dv_xname); 1241 /* wait until busy is clear */ 1242 for (i = 0; i < 200; i++) { 1243 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1244 BCE_SBTMSTATEHI); 1245 if (!(val & 0x4)) 1246 break; 1247 delay(1); 1248 } 1249 if (i == 200) 1250 printf("%s: while resetting core, busy did not clear\n", 1251 sc->bce_dev.dv_xname); 1252 /* set reset and reject while enabling the clocks */ 1253 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1254 BCE_SBTMSTATELOW, 1255 SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET); 1256 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1257 BCE_SBTMSTATELOW); 1258 delay(10); 1259 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1260 BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET); 1261 delay(1); 1262 } 1263 /* enable clock */ 1264 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1265 SBTML_FGC | SBTML_CLK | SBTML_RESET); 1266 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1267 delay(1); 1268 1269 /* clear any error bits that may be on */ 1270 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI); 1271 if (val & 1) 1272 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI, 1273 0); 1274 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE); 1275 if (val & SBIM_ERRORBITS) 1276 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE, 1277 val & ~SBIM_ERRORBITS); 1278 1279 /* clear reset and allow it to propagate throughout the core */ 1280 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1281 SBTML_FGC | SBTML_CLK); 1282 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1283 delay(1); 1284 1285 /* leave clock enabled */ 1286 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW, 1287 SBTML_CLK); 1288 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW); 1289 delay(1); 1290 1291 /* initialize MDC preamble, frequency */ 1292 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d); /* MAGIC */ 1293 1294 /* enable phy, differs for internal, and external */ 1295 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL); 1296 if (!(val & BCE_DC_IP)) { 1297 /* select external phy */ 1298 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP); 1299 } else if (val & BCE_DC_ER) { /* internal, clear reset bit if on */ 1300 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL, 1301 val & ~BCE_DC_ER); 1302 delay(100); 1303 } 1304 } 1305 1306 /* Set up the receive filter. */ 1307 void 1308 bce_set_filter(struct ifnet *ifp) 1309 { 1310 struct bce_softc *sc = ifp->if_softc; 1311 1312 if (ifp->if_flags & IFF_PROMISC) { 1313 ifp->if_flags |= IFF_ALLMULTI; 1314 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1315 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) 1316 | ERC_PE); 1317 } else { 1318 ifp->if_flags &= ~IFF_ALLMULTI; 1319 1320 /* turn off promiscuous */ 1321 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1322 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1323 BCE_RX_CTL) & ~ERC_PE); 1324 1325 /* enable/disable broadcast */ 1326 if (ifp->if_flags & IFF_BROADCAST) 1327 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1328 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1329 sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB); 1330 else 1331 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, 1332 BCE_RX_CTL, bus_space_read_4(sc->bce_btag, 1333 sc->bce_bhandle, BCE_RX_CTL) | ERC_DB); 1334 1335 /* disable the filter */ 1336 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1337 0); 1338 1339 /* add our own address */ 1340 bce_add_mac(sc, sc->bce_ac.ac_enaddr, 0); 1341 1342 /* for now accept all multicast */ 1343 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL, 1344 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) | 1345 ERC_AM); 1346 ifp->if_flags |= IFF_ALLMULTI; 1347 1348 /* enable the filter */ 1349 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL, 1350 bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1351 BCE_FILT_CTL) | 1); 1352 } 1353 } 1354 1355 /* Read a PHY register on the MII. */ 1356 int 1357 bce_mii_read(struct device *self, int phy, int reg) 1358 { 1359 struct bce_softc *sc = (struct bce_softc *) self; 1360 int i; 1361 u_int32_t val; 1362 1363 /* clear mii_int */ 1364 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR); 1365 1366 /* Read the PHY register */ 1367 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1368 (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1369 (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */ 1370 1371 for (i = 0; i < BCE_TIMEOUT; i++) { 1372 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS); 1373 if (val & BCE_MIINTR) 1374 break; 1375 delay(10); 1376 } 1377 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1378 if (i == BCE_TIMEOUT) { 1379 printf("%s: PHY read timed out reading phy %d, reg %d, val = " 1380 "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1381 return (0); 1382 } 1383 return (val & BCE_MICOMM_DATA); 1384 } 1385 1386 /* Write a PHY register on the MII */ 1387 void 1388 bce_mii_write(struct device *self, int phy, int reg, int val) 1389 { 1390 struct bce_softc *sc = (struct bce_softc *) self; 1391 int i; 1392 u_int32_t rval; 1393 1394 /* clear mii_int */ 1395 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, 1396 BCE_MIINTR); 1397 1398 /* Write the PHY register */ 1399 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM, 1400 (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) | /* MAGIC */ 1401 (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */ 1402 BCE_MIPHY(phy) | BCE_MIREG(reg)); 1403 1404 /* wait for write to complete */ 1405 for (i = 0; i < BCE_TIMEOUT; i++) { 1406 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, 1407 BCE_MI_STS); 1408 if (rval & BCE_MIINTR) 1409 break; 1410 delay(10); 1411 } 1412 rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM); 1413 if (i == BCE_TIMEOUT) { 1414 printf("%s: PHY timed out writing phy %d, reg %d, val " 1415 "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val); 1416 } 1417 } 1418 1419 /* sync hardware duplex mode to software state */ 1420 void 1421 bce_statchg(struct device *self) 1422 { 1423 struct bce_softc *sc = (struct bce_softc *) self; 1424 u_int32_t reg; 1425 1426 /* if needed, change register to match duplex mode */ 1427 reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL); 1428 if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD)) 1429 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1430 reg | EXC_FD); 1431 else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD) 1432 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL, 1433 reg & ~EXC_FD); 1434 1435 /* 1436 * Enable activity led. 1437 * XXX This should be in a phy driver, but not currently. 1438 */ 1439 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1440 bce_mii_read((struct device *) sc, 1, 26) & 0x7fff); /* MAGIC */ 1441 /* enable traffic meter led mode */ 1442 bce_mii_write((struct device *) sc, 1, 26, /* MAGIC */ 1443 bce_mii_read((struct device *) sc, 1, 27) | (1 << 6)); /* MAGIC */ 1444 } 1445 1446 /* Set hardware to newly-selected media */ 1447 int 1448 bce_mediachange(struct ifnet *ifp) 1449 { 1450 struct bce_softc *sc = ifp->if_softc; 1451 1452 if (ifp->if_flags & IFF_UP) 1453 mii_mediachg(&sc->bce_mii); 1454 return (0); 1455 } 1456 1457 /* Get the current interface media status */ 1458 void 1459 bce_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1460 { 1461 struct bce_softc *sc = ifp->if_softc; 1462 1463 mii_pollstat(&sc->bce_mii); 1464 ifmr->ifm_active = sc->bce_mii.mii_media_active; 1465 ifmr->ifm_status = sc->bce_mii.mii_media_status; 1466 } 1467 1468 /* One second timer, checks link status */ 1469 void 1470 bce_tick(void *v) 1471 { 1472 struct bce_softc *sc = v; 1473 int s; 1474 1475 s = splnet(); 1476 mii_tick(&sc->bce_mii); 1477 splx(s); 1478 1479 timeout_add_sec(&sc->bce_timeout, 1); 1480 } 1481