1 /* $OpenBSD: if_bge.c,v 1.388 2018/11/09 14:14:31 claudio Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bge.c,v 1.25 2002/11/14 23:54:49 sam Exp $ 36 */ 37 38 /* 39 * Broadcom BCM57xx/BCM590x family ethernet driver for OpenBSD. 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Engineer, Wind River Systems 43 */ 44 45 /* 46 * The Broadcom BCM5700 is based on technology originally developed by 47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 48 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 51 * frames, highly configurable RX filtering, and 16 RX and TX queues 52 * (which, along with RX filter rules, can be used for QOS applications). 53 * Other features, such as TCP segmentation, may be available as part 54 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 55 * firmware images can be stored in hardware and need not be compiled 56 * into the driver. 57 * 58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 59 * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus. 60 * 61 * The BCM5701 is a single-chip solution incorporating both the BCM5700 62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 63 * does not support external SSRAM. 64 * 65 * Broadcom also produces a variation of the BCM5700 under the "Altima" 66 * brand name, which is functionally similar but lacks PCI-X support. 67 * 68 * Without external SSRAM, you can only have at most 4 TX rings, 69 * and the use of the mini RX ring is disabled. This seems to imply 70 * that these features are simply not available on the BCM5701. As a 71 * result, this driver does not implement any support for the mini RX 72 * ring. 73 */ 74 75 #include "bpfilter.h" 76 #include "vlan.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/sockio.h> 81 #include <sys/mbuf.h> 82 #include <sys/malloc.h> 83 #include <sys/kernel.h> 84 #include <sys/device.h> 85 #include <sys/timeout.h> 86 #include <sys/socket.h> 87 #include <sys/atomic.h> 88 89 #include <net/if.h> 90 #include <net/if_media.h> 91 92 #include <netinet/in.h> 93 #include <netinet/if_ether.h> 94 95 #if NBPFILTER > 0 96 #include <net/bpf.h> 97 #endif 98 99 #ifdef __sparc64__ 100 #include <sparc64/autoconf.h> 101 #include <dev/ofw/openfirm.h> 102 #endif 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 108 #include <dev/mii/mii.h> 109 #include <dev/mii/miivar.h> 110 #include <dev/mii/miidevs.h> 111 #include <dev/mii/brgphyreg.h> 112 113 #include <dev/pci/if_bgereg.h> 114 115 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 116 117 const struct bge_revision * bge_lookup_rev(u_int32_t); 118 int bge_can_use_msi(struct bge_softc *); 119 int bge_probe(struct device *, void *, void *); 120 void bge_attach(struct device *, struct device *, void *); 121 int bge_detach(struct device *, int); 122 int bge_activate(struct device *, int); 123 124 struct cfattach bge_ca = { 125 sizeof(struct bge_softc), bge_probe, bge_attach, bge_detach, 126 bge_activate 127 }; 128 129 struct cfdriver bge_cd = { 130 NULL, "bge", DV_IFNET 131 }; 132 133 void bge_txeof(struct bge_softc *); 134 void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 135 void bge_rxeof(struct bge_softc *); 136 137 void bge_tick(void *); 138 void bge_stats_update(struct bge_softc *); 139 void bge_stats_update_regs(struct bge_softc *); 140 int bge_cksum_pad(struct mbuf *); 141 int bge_encap(struct bge_softc *, struct mbuf *, int *); 142 int bge_compact_dma_runt(struct mbuf *); 143 144 int bge_intr(void *); 145 void bge_start(struct ifqueue *); 146 int bge_ioctl(struct ifnet *, u_long, caddr_t); 147 int bge_rxrinfo(struct bge_softc *, struct if_rxrinfo *); 148 void bge_init(void *); 149 void bge_stop_block(struct bge_softc *, bus_size_t, u_int32_t); 150 void bge_stop(struct bge_softc *, int); 151 void bge_watchdog(struct ifnet *); 152 int bge_ifmedia_upd(struct ifnet *); 153 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 154 155 u_int8_t bge_nvram_getbyte(struct bge_softc *, int, u_int8_t *); 156 int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 157 u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *); 158 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 159 160 void bge_iff(struct bge_softc *); 161 162 int bge_newbuf_jumbo(struct bge_softc *, int); 163 int bge_init_rx_ring_jumbo(struct bge_softc *); 164 void bge_fill_rx_ring_jumbo(struct bge_softc *); 165 void bge_free_rx_ring_jumbo(struct bge_softc *); 166 167 int bge_newbuf(struct bge_softc *, int); 168 int bge_init_rx_ring_std(struct bge_softc *); 169 void bge_rxtick(void *); 170 void bge_fill_rx_ring_std(struct bge_softc *); 171 void bge_free_rx_ring_std(struct bge_softc *); 172 173 void bge_free_tx_ring(struct bge_softc *); 174 int bge_init_tx_ring(struct bge_softc *); 175 176 void bge_chipinit(struct bge_softc *); 177 int bge_blockinit(struct bge_softc *); 178 u_int32_t bge_dma_swap_options(struct bge_softc *); 179 int bge_phy_addr(struct bge_softc *); 180 181 u_int32_t bge_readmem_ind(struct bge_softc *, int); 182 void bge_writemem_ind(struct bge_softc *, int, int); 183 void bge_writereg_ind(struct bge_softc *, int, int); 184 void bge_writembx(struct bge_softc *, int, int); 185 186 int bge_miibus_readreg(struct device *, int, int); 187 void bge_miibus_writereg(struct device *, int, int, int); 188 void bge_miibus_statchg(struct device *); 189 190 #define BGE_RESET_SHUTDOWN 0 191 #define BGE_RESET_START 1 192 #define BGE_RESET_SUSPEND 2 193 void bge_sig_post_reset(struct bge_softc *, int); 194 void bge_sig_legacy(struct bge_softc *, int); 195 void bge_sig_pre_reset(struct bge_softc *, int); 196 void bge_stop_fw(struct bge_softc *, int); 197 void bge_reset(struct bge_softc *); 198 void bge_link_upd(struct bge_softc *); 199 200 void bge_ape_lock_init(struct bge_softc *); 201 void bge_ape_read_fw_ver(struct bge_softc *); 202 int bge_ape_lock(struct bge_softc *, int); 203 void bge_ape_unlock(struct bge_softc *, int); 204 void bge_ape_send_event(struct bge_softc *, uint32_t); 205 void bge_ape_driver_state_change(struct bge_softc *, int); 206 207 #ifdef BGE_DEBUG 208 #define DPRINTF(x) do { if (bgedebug) printf x; } while (0) 209 #define DPRINTFN(n,x) do { if (bgedebug >= (n)) printf x; } while (0) 210 int bgedebug = 0; 211 #else 212 #define DPRINTF(x) 213 #define DPRINTFN(n,x) 214 #endif 215 216 /* 217 * Various supported device vendors/types and their names. Note: the 218 * spec seems to indicate that the hardware still has Alteon's vendor 219 * ID burned into it, though it will always be overridden by the vendor 220 * ID in the EEPROM. Just to be safe, we cover all possibilities. 221 */ 222 const struct pci_matchid bge_devices[] = { 223 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700 }, 224 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701 }, 225 226 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000 }, 227 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001 }, 228 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1003 }, 229 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100 }, 230 231 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701 }, 232 233 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700 }, 234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701 }, 235 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702 }, 236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT }, 237 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X }, 238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703 }, 239 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703_ALT }, 240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X }, 241 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C }, 242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S }, 243 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT }, 244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705 }, 245 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F }, 246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K }, 247 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M }, 248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT }, 249 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714 }, 250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S }, 251 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715 }, 252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S }, 253 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717 }, 254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C }, 255 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718 }, 256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719 }, 257 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720 }, 258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721 }, 259 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722 }, 260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723 }, 261 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725 }, 262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727 }, 263 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751 }, 264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F }, 265 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M }, 266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752 }, 267 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M }, 268 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753 }, 269 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F }, 270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M }, 271 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754 }, 272 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M }, 273 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755 }, 274 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M }, 275 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756 }, 276 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761 }, 277 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E }, 278 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S }, 279 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE }, 280 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762 }, 281 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764 }, 282 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780 }, 283 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S }, 284 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781 }, 285 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782 }, 286 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784 }, 287 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F }, 288 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G }, 289 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786 }, 290 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787 }, 291 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F }, 292 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M }, 293 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788 }, 294 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789 }, 295 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901 }, 296 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2 }, 297 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M }, 298 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906 }, 299 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M }, 300 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760 }, 301 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761 }, 302 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762 }, 303 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57764 }, 304 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765 }, 305 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766 }, 306 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57767 }, 307 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780 }, 308 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781 }, 309 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782 }, 310 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785 }, 311 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786 }, 312 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57787 }, 313 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788 }, 314 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790 }, 315 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791 }, 316 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795 }, 317 318 { PCI_VENDOR_FUJITSU, PCI_PRODUCT_FUJITSU_PW008GE4 }, 319 { PCI_VENDOR_FUJITSU, PCI_PRODUCT_FUJITSU_PW008GE5 }, 320 { PCI_VENDOR_FUJITSU, PCI_PRODUCT_FUJITSU_PP250_450_LAN }, 321 322 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9D21 }, 323 324 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996 } 325 }; 326 327 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_JUMBO_CAPABLE) 328 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_5700_FAMILY) 329 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_5705_PLUS) 330 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_5714_FAMILY) 331 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_575X_PLUS) 332 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_5755_PLUS) 333 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_5717_PLUS) 334 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_57765_PLUS) 335 336 static const struct bge_revision { 337 u_int32_t br_chipid; 338 const char *br_name; 339 } bge_revisions[] = { 340 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 341 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 342 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 343 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 344 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 345 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 346 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 347 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 348 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 349 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 350 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 351 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 352 /* the 5702 and 5703 share the same ASIC ID */ 353 { BGE_CHIPID_BCM5703_A0, "BCM5702/5703 A0" }, 354 { BGE_CHIPID_BCM5703_A1, "BCM5702/5703 A1" }, 355 { BGE_CHIPID_BCM5703_A2, "BCM5702/5703 A2" }, 356 { BGE_CHIPID_BCM5703_A3, "BCM5702/5703 A3" }, 357 { BGE_CHIPID_BCM5703_B0, "BCM5702/5703 B0" }, 358 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 359 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 360 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 361 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 362 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 363 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 364 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 365 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 366 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 367 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 368 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 369 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 370 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 371 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 372 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 373 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 374 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 375 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 376 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 377 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 378 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 379 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 380 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 381 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 382 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 383 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 384 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 385 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 386 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 387 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 388 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 389 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 390 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 391 { BGE_CHIPID_BCM5755_C0, "BCM5755 C0" }, 392 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 393 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 394 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 395 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 396 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 397 /* the 5754 and 5787 share the same ASIC ID */ 398 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 399 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 400 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 401 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 402 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 403 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 404 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 405 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 406 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 407 408 { 0, NULL } 409 }; 410 411 /* 412 * Some defaults for major revisions, so that newer steppings 413 * that we don't know about have a shot at working. 414 */ 415 static const struct bge_revision bge_majorrevs[] = { 416 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 417 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 418 /* 5702 and 5703 share the same ASIC ID */ 419 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 420 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 421 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 422 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 423 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 424 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 425 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 426 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 427 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 428 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 429 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 430 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 431 /* 5754 and 5787 share the same ASIC ID */ 432 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 433 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 434 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 435 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 436 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 437 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 438 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 439 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 440 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 441 442 { 0, NULL } 443 }; 444 445 u_int32_t 446 bge_readmem_ind(struct bge_softc *sc, int off) 447 { 448 struct pci_attach_args *pa = &(sc->bge_pa); 449 u_int32_t val; 450 451 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 452 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 453 return (0); 454 455 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 456 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA); 457 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, 0); 458 return (val); 459 } 460 461 void 462 bge_writemem_ind(struct bge_softc *sc, int off, int val) 463 { 464 struct pci_attach_args *pa = &(sc->bge_pa); 465 466 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 467 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 468 return; 469 470 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 471 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 472 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, 0); 473 } 474 475 void 476 bge_writereg_ind(struct bge_softc *sc, int off, int val) 477 { 478 struct pci_attach_args *pa = &(sc->bge_pa); 479 480 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 481 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 482 } 483 484 void 485 bge_writembx(struct bge_softc *sc, int off, int val) 486 { 487 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 488 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 489 490 CSR_WRITE_4(sc, off, val); 491 } 492 493 /* 494 * Clear all stale locks and select the lock for this driver instance. 495 */ 496 void 497 bge_ape_lock_init(struct bge_softc *sc) 498 { 499 struct pci_attach_args *pa = &(sc->bge_pa); 500 uint32_t bit, regbase; 501 int i; 502 503 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 504 regbase = BGE_APE_LOCK_GRANT; 505 else 506 regbase = BGE_APE_PER_LOCK_GRANT; 507 508 /* Clear any stale locks. */ 509 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 510 switch (i) { 511 case BGE_APE_LOCK_PHY0: 512 case BGE_APE_LOCK_PHY1: 513 case BGE_APE_LOCK_PHY2: 514 case BGE_APE_LOCK_PHY3: 515 bit = BGE_APE_LOCK_GRANT_DRIVER0; 516 break; 517 default: 518 if (pa->pa_function == 0) 519 bit = BGE_APE_LOCK_GRANT_DRIVER0; 520 else 521 bit = (1 << pa->pa_function); 522 } 523 APE_WRITE_4(sc, regbase + 4 * i, bit); 524 } 525 526 /* Select the PHY lock based on the device's function number. */ 527 switch (pa->pa_function) { 528 case 0: 529 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 530 break; 531 case 1: 532 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 533 break; 534 case 2: 535 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 536 break; 537 case 3: 538 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 539 break; 540 default: 541 printf("%s: PHY lock not supported on function %d\n", 542 sc->bge_dev.dv_xname, pa->pa_function); 543 break; 544 } 545 } 546 547 /* 548 * Check for APE firmware, set flags, and print version info. 549 */ 550 void 551 bge_ape_read_fw_ver(struct bge_softc *sc) 552 { 553 const char *fwtype; 554 uint32_t apedata, features; 555 556 /* Check for a valid APE signature in shared memory. */ 557 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 558 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 559 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 560 return; 561 } 562 563 /* Check if APE firmware is running. */ 564 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 565 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 566 printf("%s: APE signature found but FW status not ready! " 567 "0x%08x\n", sc->bge_dev.dv_xname, apedata); 568 return; 569 } 570 571 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 572 573 /* Fetch the APE firwmare type and version. */ 574 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 575 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 576 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 577 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 578 fwtype = "NCSI"; 579 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 580 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 581 fwtype = "DASH"; 582 } else 583 fwtype = "UNKN"; 584 585 /* Print the APE firmware version. */ 586 printf(", APE firmware %s %d.%d.%d.%d", fwtype, 587 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 588 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 589 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 590 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 591 } 592 593 int 594 bge_ape_lock(struct bge_softc *sc, int locknum) 595 { 596 struct pci_attach_args *pa = &(sc->bge_pa); 597 uint32_t bit, gnt, req, status; 598 int i, off; 599 600 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 601 return (0); 602 603 /* Lock request/grant registers have different bases. */ 604 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) { 605 req = BGE_APE_LOCK_REQ; 606 gnt = BGE_APE_LOCK_GRANT; 607 } else { 608 req = BGE_APE_PER_LOCK_REQ; 609 gnt = BGE_APE_PER_LOCK_GRANT; 610 } 611 612 off = 4 * locknum; 613 614 switch (locknum) { 615 case BGE_APE_LOCK_GPIO: 616 /* Lock required when using GPIO. */ 617 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 618 return (0); 619 if (pa->pa_function == 0) 620 bit = BGE_APE_LOCK_REQ_DRIVER0; 621 else 622 bit = (1 << pa->pa_function); 623 break; 624 case BGE_APE_LOCK_GRC: 625 /* Lock required to reset the device. */ 626 if (pa->pa_function == 0) 627 bit = BGE_APE_LOCK_REQ_DRIVER0; 628 else 629 bit = (1 << pa->pa_function); 630 break; 631 case BGE_APE_LOCK_MEM: 632 /* Lock required when accessing certain APE memory. */ 633 if (pa->pa_function == 0) 634 bit = BGE_APE_LOCK_REQ_DRIVER0; 635 else 636 bit = (1 << pa->pa_function); 637 break; 638 case BGE_APE_LOCK_PHY0: 639 case BGE_APE_LOCK_PHY1: 640 case BGE_APE_LOCK_PHY2: 641 case BGE_APE_LOCK_PHY3: 642 /* Lock required when accessing PHYs. */ 643 bit = BGE_APE_LOCK_REQ_DRIVER0; 644 break; 645 default: 646 return (EINVAL); 647 } 648 649 /* Request a lock. */ 650 APE_WRITE_4(sc, req + off, bit); 651 652 /* Wait up to 1 second to acquire lock. */ 653 for (i = 0; i < 20000; i++) { 654 status = APE_READ_4(sc, gnt + off); 655 if (status == bit) 656 break; 657 DELAY(50); 658 } 659 660 /* Handle any errors. */ 661 if (status != bit) { 662 printf("%s: APE lock %d request failed! " 663 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 664 sc->bge_dev.dv_xname, 665 locknum, req + off, bit & 0xFFFF, gnt + off, 666 status & 0xFFFF); 667 /* Revoke the lock request. */ 668 APE_WRITE_4(sc, gnt + off, bit); 669 return (EBUSY); 670 } 671 672 return (0); 673 } 674 675 void 676 bge_ape_unlock(struct bge_softc *sc, int locknum) 677 { 678 struct pci_attach_args *pa = &(sc->bge_pa); 679 uint32_t bit, gnt; 680 int off; 681 682 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 683 return; 684 685 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 686 gnt = BGE_APE_LOCK_GRANT; 687 else 688 gnt = BGE_APE_PER_LOCK_GRANT; 689 690 off = 4 * locknum; 691 692 switch (locknum) { 693 case BGE_APE_LOCK_GPIO: 694 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 695 return; 696 if (pa->pa_function == 0) 697 bit = BGE_APE_LOCK_GRANT_DRIVER0; 698 else 699 bit = (1 << pa->pa_function); 700 break; 701 case BGE_APE_LOCK_GRC: 702 if (pa->pa_function == 0) 703 bit = BGE_APE_LOCK_GRANT_DRIVER0; 704 else 705 bit = (1 << pa->pa_function); 706 break; 707 case BGE_APE_LOCK_MEM: 708 if (pa->pa_function == 0) 709 bit = BGE_APE_LOCK_GRANT_DRIVER0; 710 else 711 bit = (1 << pa->pa_function); 712 break; 713 case BGE_APE_LOCK_PHY0: 714 case BGE_APE_LOCK_PHY1: 715 case BGE_APE_LOCK_PHY2: 716 case BGE_APE_LOCK_PHY3: 717 bit = BGE_APE_LOCK_GRANT_DRIVER0; 718 break; 719 default: 720 return; 721 } 722 723 APE_WRITE_4(sc, gnt + off, bit); 724 } 725 726 /* 727 * Send an event to the APE firmware. 728 */ 729 void 730 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 731 { 732 uint32_t apedata; 733 int i; 734 735 /* NCSI does not support APE events. */ 736 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 737 return; 738 739 /* Wait up to 1ms for APE to service previous event. */ 740 for (i = 10; i > 0; i--) { 741 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 742 break; 743 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 744 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 745 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 746 BGE_APE_EVENT_STATUS_EVENT_PENDING); 747 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 748 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 749 break; 750 } 751 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 752 DELAY(100); 753 } 754 if (i == 0) { 755 printf("%s: APE event 0x%08x send timed out\n", 756 sc->bge_dev.dv_xname, event); 757 } 758 } 759 760 void 761 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 762 { 763 uint32_t apedata, event; 764 765 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 766 return; 767 768 switch (kind) { 769 case BGE_RESET_START: 770 /* If this is the first load, clear the load counter. */ 771 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 772 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 773 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 774 else { 775 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 776 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 777 } 778 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 779 BGE_APE_HOST_SEG_SIG_MAGIC); 780 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 781 BGE_APE_HOST_SEG_LEN_MAGIC); 782 783 /* Add some version info if bge(4) supports it. */ 784 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 785 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 786 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 787 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 788 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 789 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 790 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 791 BGE_APE_HOST_DRVR_STATE_START); 792 event = BGE_APE_EVENT_STATUS_STATE_START; 793 break; 794 case BGE_RESET_SHUTDOWN: 795 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 796 BGE_APE_HOST_DRVR_STATE_UNLOAD); 797 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 798 break; 799 case BGE_RESET_SUSPEND: 800 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 801 break; 802 default: 803 return; 804 } 805 806 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 807 BGE_APE_EVENT_STATUS_STATE_CHNGE); 808 } 809 810 811 u_int8_t 812 bge_nvram_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 813 { 814 u_int32_t access, byte = 0; 815 int i; 816 817 /* Lock. */ 818 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 819 for (i = 0; i < 8000; i++) { 820 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 821 break; 822 DELAY(20); 823 } 824 if (i == 8000) 825 return (1); 826 827 /* Enable access. */ 828 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 829 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 830 831 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 832 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 833 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 834 DELAY(10); 835 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 836 DELAY(10); 837 break; 838 } 839 } 840 841 if (i == BGE_TIMEOUT * 10) { 842 printf("%s: nvram read timed out\n", sc->bge_dev.dv_xname); 843 return (1); 844 } 845 846 /* Get result. */ 847 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 848 849 *dest = (swap32(byte) >> ((addr % 4) * 8)) & 0xFF; 850 851 /* Disable access. */ 852 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 853 854 /* Unlock. */ 855 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 856 CSR_READ_4(sc, BGE_NVRAM_SWARB); 857 858 return (0); 859 } 860 861 /* 862 * Read a sequence of bytes from NVRAM. 863 */ 864 865 int 866 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 867 { 868 int err = 0, i; 869 u_int8_t byte = 0; 870 871 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) 872 return (1); 873 874 for (i = 0; i < cnt; i++) { 875 err = bge_nvram_getbyte(sc, off + i, &byte); 876 if (err) 877 break; 878 *(dest + i) = byte; 879 } 880 881 return (err ? 1 : 0); 882 } 883 884 /* 885 * Read a byte of data stored in the EEPROM at address 'addr.' The 886 * BCM570x supports both the traditional bitbang interface and an 887 * auto access interface for reading the EEPROM. We use the auto 888 * access method. 889 */ 890 u_int8_t 891 bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest) 892 { 893 int i; 894 u_int32_t byte = 0; 895 896 /* 897 * Enable use of auto EEPROM access so we can avoid 898 * having to use the bitbang method. 899 */ 900 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 901 902 /* Reset the EEPROM, load the clock period. */ 903 CSR_WRITE_4(sc, BGE_EE_ADDR, 904 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 905 DELAY(20); 906 907 /* Issue the read EEPROM command. */ 908 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 909 910 /* Wait for completion */ 911 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 912 DELAY(10); 913 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 914 break; 915 } 916 917 if (i == BGE_TIMEOUT * 10) { 918 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 919 return (1); 920 } 921 922 /* Get result. */ 923 byte = CSR_READ_4(sc, BGE_EE_DATA); 924 925 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 926 927 return (0); 928 } 929 930 /* 931 * Read a sequence of bytes from the EEPROM. 932 */ 933 int 934 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 935 { 936 int i, error = 0; 937 u_int8_t byte = 0; 938 939 for (i = 0; i < cnt; i++) { 940 error = bge_eeprom_getbyte(sc, off + i, &byte); 941 if (error) 942 break; 943 *(dest + i) = byte; 944 } 945 946 return (error ? 1 : 0); 947 } 948 949 int 950 bge_miibus_readreg(struct device *dev, int phy, int reg) 951 { 952 struct bge_softc *sc = (struct bge_softc *)dev; 953 u_int32_t val, autopoll; 954 int i; 955 956 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 957 return (0); 958 959 /* Reading with autopolling on may trigger PCI errors */ 960 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 961 if (autopoll & BGE_MIMODE_AUTOPOLL) { 962 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 963 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 964 DELAY(80); 965 } 966 967 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 968 BGE_MIPHY(phy)|BGE_MIREG(reg)); 969 CSR_READ_4(sc, BGE_MI_COMM); /* force write */ 970 971 for (i = 0; i < 200; i++) { 972 delay(1); 973 val = CSR_READ_4(sc, BGE_MI_COMM); 974 if (!(val & BGE_MICOMM_BUSY)) 975 break; 976 delay(10); 977 } 978 979 if (i == 200) { 980 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 981 val = 0; 982 goto done; 983 } 984 985 val = CSR_READ_4(sc, BGE_MI_COMM); 986 987 done: 988 if (autopoll & BGE_MIMODE_AUTOPOLL) { 989 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 990 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 991 DELAY(80); 992 } 993 994 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 995 996 if (val & BGE_MICOMM_READFAIL) 997 return (0); 998 999 return (val & 0xFFFF); 1000 } 1001 1002 void 1003 bge_miibus_writereg(struct device *dev, int phy, int reg, int val) 1004 { 1005 struct bge_softc *sc = (struct bge_softc *)dev; 1006 u_int32_t autopoll; 1007 int i; 1008 1009 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906 && 1010 (reg == MII_100T2CR || reg == BRGPHY_MII_AUXCTL)) 1011 return; 1012 1013 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1014 return; 1015 1016 /* Reading with autopolling on may trigger PCI errors */ 1017 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 1018 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1019 DELAY(40); 1020 BGE_STS_CLRBIT(sc, BGE_STS_AUTOPOLL); 1021 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1022 DELAY(40); /* 40 usec is supposed to be adequate */ 1023 } 1024 1025 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 1026 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 1027 CSR_READ_4(sc, BGE_MI_COMM); /* force write */ 1028 1029 for (i = 0; i < 200; i++) { 1030 delay(1); 1031 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 1032 break; 1033 delay(10); 1034 } 1035 1036 if (autopoll & BGE_MIMODE_AUTOPOLL) { 1037 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 1038 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 1039 DELAY(40); 1040 } 1041 1042 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1043 1044 if (i == 200) { 1045 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 1046 } 1047 } 1048 1049 void 1050 bge_miibus_statchg(struct device *dev) 1051 { 1052 struct bge_softc *sc = (struct bge_softc *)dev; 1053 struct mii_data *mii = &sc->bge_mii; 1054 u_int32_t mac_mode, rx_mode, tx_mode; 1055 1056 /* 1057 * Get flow control negotiation result. 1058 */ 1059 if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO && 1060 (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) 1061 sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK; 1062 1063 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 1064 mii->mii_media_status & IFM_ACTIVE && 1065 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1066 BGE_STS_SETBIT(sc, BGE_STS_LINK); 1067 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 1068 (!(mii->mii_media_status & IFM_ACTIVE) || 1069 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 1070 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 1071 1072 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 1073 return; 1074 1075 /* Set the port mode (MII/GMII) to match the link speed. */ 1076 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1077 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1078 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1079 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1080 1081 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1082 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1083 mac_mode |= BGE_PORTMODE_GMII; 1084 else 1085 mac_mode |= BGE_PORTMODE_MII; 1086 1087 /* Set MAC flow control behavior to match link flow control settings. */ 1088 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1089 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1090 if (mii->mii_media_active & IFM_FDX) { 1091 if (sc->bge_flowflags & IFM_ETH_TXPAUSE) 1092 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1093 if (sc->bge_flowflags & IFM_ETH_RXPAUSE) 1094 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1095 } else 1096 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1097 1098 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1099 DELAY(40); 1100 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1101 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1102 } 1103 1104 /* 1105 * Intialize a standard receive ring descriptor. 1106 */ 1107 int 1108 bge_newbuf(struct bge_softc *sc, int i) 1109 { 1110 bus_dmamap_t dmap = sc->bge_cdata.bge_rx_std_map[i]; 1111 struct bge_rx_bd *r = &sc->bge_rdata->bge_rx_std_ring[i]; 1112 struct mbuf *m; 1113 int error; 1114 1115 m = MCLGETI(NULL, M_DONTWAIT, NULL, sc->bge_rx_std_len); 1116 if (!m) 1117 return (ENOBUFS); 1118 m->m_len = m->m_pkthdr.len = sc->bge_rx_std_len; 1119 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1120 m_adj(m, ETHER_ALIGN); 1121 1122 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmap, m, 1123 BUS_DMA_READ|BUS_DMA_NOWAIT); 1124 if (error) { 1125 m_freem(m); 1126 return (ENOBUFS); 1127 } 1128 1129 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, dmap->dm_mapsize, 1130 BUS_DMASYNC_PREREAD); 1131 sc->bge_cdata.bge_rx_std_chain[i] = m; 1132 1133 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1134 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1135 i * sizeof (struct bge_rx_bd), 1136 sizeof (struct bge_rx_bd), 1137 BUS_DMASYNC_POSTWRITE); 1138 1139 BGE_HOSTADDR(r->bge_addr, dmap->dm_segs[0].ds_addr); 1140 r->bge_flags = BGE_RXBDFLAG_END; 1141 r->bge_len = m->m_len; 1142 r->bge_idx = i; 1143 1144 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1145 offsetof(struct bge_ring_data, bge_rx_std_ring) + 1146 i * sizeof (struct bge_rx_bd), 1147 sizeof (struct bge_rx_bd), 1148 BUS_DMASYNC_PREWRITE); 1149 1150 return (0); 1151 } 1152 1153 /* 1154 * Initialize a Jumbo receive ring descriptor. 1155 */ 1156 int 1157 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1158 { 1159 bus_dmamap_t dmap = sc->bge_cdata.bge_rx_jumbo_map[i]; 1160 struct bge_ext_rx_bd *r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 1161 struct mbuf *m; 1162 int error; 1163 1164 m = MCLGETI(NULL, M_DONTWAIT, NULL, BGE_JLEN); 1165 if (!m) 1166 return (ENOBUFS); 1167 m->m_len = m->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 1168 if (!(sc->bge_flags & BGE_RX_ALIGNBUG)) 1169 m_adj(m, ETHER_ALIGN); 1170 1171 error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmap, m, 1172 BUS_DMA_READ|BUS_DMA_NOWAIT); 1173 if (error) { 1174 m_freem(m); 1175 return (ENOBUFS); 1176 } 1177 1178 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, dmap->dm_mapsize, 1179 BUS_DMASYNC_PREREAD); 1180 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1181 1182 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1183 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1184 i * sizeof (struct bge_ext_rx_bd), 1185 sizeof (struct bge_ext_rx_bd), 1186 BUS_DMASYNC_POSTWRITE); 1187 1188 /* 1189 * Fill in the extended RX buffer descriptor. 1190 */ 1191 r->bge_bd.bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1192 r->bge_bd.bge_idx = i; 1193 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1194 switch (dmap->dm_nsegs) { 1195 case 4: 1196 BGE_HOSTADDR(r->bge_addr3, dmap->dm_segs[3].ds_addr); 1197 r->bge_len3 = dmap->dm_segs[3].ds_len; 1198 /* FALLTHROUGH */ 1199 case 3: 1200 BGE_HOSTADDR(r->bge_addr2, dmap->dm_segs[2].ds_addr); 1201 r->bge_len2 = dmap->dm_segs[2].ds_len; 1202 /* FALLTHROUGH */ 1203 case 2: 1204 BGE_HOSTADDR(r->bge_addr1, dmap->dm_segs[1].ds_addr); 1205 r->bge_len1 = dmap->dm_segs[1].ds_len; 1206 /* FALLTHROUGH */ 1207 case 1: 1208 BGE_HOSTADDR(r->bge_bd.bge_addr, dmap->dm_segs[0].ds_addr); 1209 r->bge_bd.bge_len = dmap->dm_segs[0].ds_len; 1210 break; 1211 default: 1212 panic("%s: %d segments", __func__, dmap->dm_nsegs); 1213 } 1214 1215 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 1216 offsetof(struct bge_ring_data, bge_rx_jumbo_ring) + 1217 i * sizeof (struct bge_ext_rx_bd), 1218 sizeof (struct bge_ext_rx_bd), 1219 BUS_DMASYNC_PREWRITE); 1220 1221 return (0); 1222 } 1223 1224 int 1225 bge_init_rx_ring_std(struct bge_softc *sc) 1226 { 1227 int i; 1228 1229 if (ISSET(sc->bge_flags, BGE_RXRING_VALID)) 1230 return (0); 1231 1232 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1233 if (bus_dmamap_create(sc->bge_dmatag, sc->bge_rx_std_len, 1, 1234 sc->bge_rx_std_len, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1235 &sc->bge_cdata.bge_rx_std_map[i]) != 0) { 1236 printf("%s: unable to create dmamap for slot %d\n", 1237 sc->bge_dev.dv_xname, i); 1238 goto uncreate; 1239 } 1240 bzero(&sc->bge_rdata->bge_rx_std_ring[i], 1241 sizeof(struct bge_rx_bd)); 1242 } 1243 1244 sc->bge_std = BGE_STD_RX_RING_CNT - 1; 1245 1246 /* lwm must be greater than the replenish threshold */ 1247 if_rxr_init(&sc->bge_std_ring, 17, BGE_STD_RX_RING_CNT); 1248 bge_fill_rx_ring_std(sc); 1249 1250 SET(sc->bge_flags, BGE_RXRING_VALID); 1251 1252 return (0); 1253 1254 uncreate: 1255 while (--i) { 1256 bus_dmamap_destroy(sc->bge_dmatag, 1257 sc->bge_cdata.bge_rx_std_map[i]); 1258 } 1259 return (1); 1260 } 1261 1262 /* 1263 * When the refill timeout for a ring is active, that ring is so empty 1264 * that no more packets can be received on it, so the interrupt handler 1265 * will not attempt to refill it, meaning we don't need to protect against 1266 * interrupts here. 1267 */ 1268 1269 void 1270 bge_rxtick(void *arg) 1271 { 1272 struct bge_softc *sc = arg; 1273 1274 if (ISSET(sc->bge_flags, BGE_RXRING_VALID) && 1275 if_rxr_inuse(&sc->bge_std_ring) <= 8) 1276 bge_fill_rx_ring_std(sc); 1277 } 1278 1279 void 1280 bge_rxtick_jumbo(void *arg) 1281 { 1282 struct bge_softc *sc = arg; 1283 1284 if (ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID) && 1285 if_rxr_inuse(&sc->bge_jumbo_ring) <= 8) 1286 bge_fill_rx_ring_jumbo(sc); 1287 } 1288 1289 void 1290 bge_fill_rx_ring_std(struct bge_softc *sc) 1291 { 1292 int i; 1293 int post = 0; 1294 u_int slots; 1295 1296 i = sc->bge_std; 1297 for (slots = if_rxr_get(&sc->bge_std_ring, BGE_STD_RX_RING_CNT); 1298 slots > 0; slots--) { 1299 BGE_INC(i, BGE_STD_RX_RING_CNT); 1300 1301 if (bge_newbuf(sc, i) != 0) 1302 break; 1303 1304 sc->bge_std = i; 1305 post = 1; 1306 } 1307 if_rxr_put(&sc->bge_std_ring, slots); 1308 1309 if (post) 1310 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1311 1312 /* 1313 * bge always needs more than 8 packets on the ring. if we cant do 1314 * that now, then try again later. 1315 */ 1316 if (if_rxr_inuse(&sc->bge_std_ring) <= 8) 1317 timeout_add(&sc->bge_rxtimeout, 1); 1318 } 1319 1320 void 1321 bge_free_rx_ring_std(struct bge_softc *sc) 1322 { 1323 bus_dmamap_t dmap; 1324 struct mbuf *m; 1325 int i; 1326 1327 if (!ISSET(sc->bge_flags, BGE_RXRING_VALID)) 1328 return; 1329 1330 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1331 dmap = sc->bge_cdata.bge_rx_std_map[i]; 1332 m = sc->bge_cdata.bge_rx_std_chain[i]; 1333 if (m != NULL) { 1334 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, 1335 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1336 bus_dmamap_unload(sc->bge_dmatag, dmap); 1337 m_freem(m); 1338 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1339 } 1340 bus_dmamap_destroy(sc->bge_dmatag, dmap); 1341 sc->bge_cdata.bge_rx_std_map[i] = NULL; 1342 bzero(&sc->bge_rdata->bge_rx_std_ring[i], 1343 sizeof(struct bge_rx_bd)); 1344 } 1345 1346 CLR(sc->bge_flags, BGE_RXRING_VALID); 1347 } 1348 1349 int 1350 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1351 { 1352 volatile struct bge_rcb *rcb; 1353 int i; 1354 1355 if (ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)) 1356 return (0); 1357 1358 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1359 if (bus_dmamap_create(sc->bge_dmatag, BGE_JLEN, 4, BGE_JLEN, 0, 1360 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1361 &sc->bge_cdata.bge_rx_jumbo_map[i]) != 0) { 1362 printf("%s: unable to create dmamap for slot %d\n", 1363 sc->bge_dev.dv_xname, i); 1364 goto uncreate; 1365 } 1366 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i], 1367 sizeof(struct bge_ext_rx_bd)); 1368 } 1369 1370 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1; 1371 1372 /* lwm must be greater than the replenish threshold */ 1373 if_rxr_init(&sc->bge_jumbo_ring, 17, BGE_JUMBO_RX_RING_CNT); 1374 bge_fill_rx_ring_jumbo(sc); 1375 1376 SET(sc->bge_flags, BGE_JUMBO_RXRING_VALID); 1377 1378 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1379 rcb->bge_maxlen_flags = 1380 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1381 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1382 1383 return (0); 1384 1385 uncreate: 1386 while (--i) { 1387 bus_dmamap_destroy(sc->bge_dmatag, 1388 sc->bge_cdata.bge_rx_jumbo_map[i]); 1389 } 1390 return (1); 1391 } 1392 1393 void 1394 bge_fill_rx_ring_jumbo(struct bge_softc *sc) 1395 { 1396 int i; 1397 int post = 0; 1398 u_int slots; 1399 1400 i = sc->bge_jumbo; 1401 for (slots = if_rxr_get(&sc->bge_jumbo_ring, BGE_JUMBO_RX_RING_CNT); 1402 slots > 0; slots--) { 1403 BGE_INC(i, BGE_JUMBO_RX_RING_CNT); 1404 1405 if (bge_newbuf_jumbo(sc, i) != 0) 1406 break; 1407 1408 sc->bge_jumbo = i; 1409 post = 1; 1410 } 1411 if_rxr_put(&sc->bge_jumbo_ring, slots); 1412 1413 if (post) 1414 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1415 1416 /* 1417 * bge always needs more than 8 packets on the ring. if we cant do 1418 * that now, then try again later. 1419 */ 1420 if (if_rxr_inuse(&sc->bge_jumbo_ring) <= 8) 1421 timeout_add(&sc->bge_rxtimeout_jumbo, 1); 1422 } 1423 1424 void 1425 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1426 { 1427 bus_dmamap_t dmap; 1428 struct mbuf *m; 1429 int i; 1430 1431 if (!ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)) 1432 return; 1433 1434 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1435 dmap = sc->bge_cdata.bge_rx_jumbo_map[i]; 1436 m = sc->bge_cdata.bge_rx_jumbo_chain[i]; 1437 if (m != NULL) { 1438 bus_dmamap_sync(sc->bge_dmatag, dmap, 0, 1439 dmap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1440 bus_dmamap_unload(sc->bge_dmatag, dmap); 1441 m_freem(m); 1442 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1443 } 1444 bus_dmamap_destroy(sc->bge_dmatag, dmap); 1445 sc->bge_cdata.bge_rx_jumbo_map[i] = NULL; 1446 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i], 1447 sizeof(struct bge_ext_rx_bd)); 1448 } 1449 1450 CLR(sc->bge_flags, BGE_JUMBO_RXRING_VALID); 1451 } 1452 1453 void 1454 bge_free_tx_ring(struct bge_softc *sc) 1455 { 1456 int i; 1457 1458 if (!(sc->bge_flags & BGE_TXRING_VALID)) 1459 return; 1460 1461 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1462 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1463 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1464 sc->bge_cdata.bge_tx_chain[i] = NULL; 1465 sc->bge_cdata.bge_tx_map[i] = NULL; 1466 } 1467 bzero(&sc->bge_rdata->bge_tx_ring[i], 1468 sizeof(struct bge_tx_bd)); 1469 1470 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_txdma[i]); 1471 } 1472 1473 sc->bge_flags &= ~BGE_TXRING_VALID; 1474 } 1475 1476 int 1477 bge_init_tx_ring(struct bge_softc *sc) 1478 { 1479 int i; 1480 bus_size_t txsegsz, txmaxsegsz; 1481 1482 if (sc->bge_flags & BGE_TXRING_VALID) 1483 return (0); 1484 1485 sc->bge_txcnt = 0; 1486 sc->bge_tx_saved_considx = 0; 1487 1488 /* Initialize transmit producer index for host-memory send ring. */ 1489 sc->bge_tx_prodidx = 0; 1490 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1491 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1492 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1493 1494 /* NIC-memory send ring not used; initialize to zero. */ 1495 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1496 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 1497 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1498 1499 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1500 txsegsz = 4096; 1501 txmaxsegsz = BGE_JLEN; 1502 } else { 1503 txsegsz = MCLBYTES; 1504 txmaxsegsz = MCLBYTES; 1505 } 1506 1507 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1508 if (bus_dmamap_create(sc->bge_dmatag, txmaxsegsz, 1509 BGE_NTXSEG, txsegsz, 0, BUS_DMA_NOWAIT, &sc->bge_txdma[i])) 1510 return (ENOBUFS); 1511 } 1512 1513 sc->bge_flags |= BGE_TXRING_VALID; 1514 1515 return (0); 1516 } 1517 1518 void 1519 bge_iff(struct bge_softc *sc) 1520 { 1521 struct arpcom *ac = &sc->arpcom; 1522 struct ifnet *ifp = &ac->ac_if; 1523 struct ether_multi *enm; 1524 struct ether_multistep step; 1525 u_int8_t hashes[16]; 1526 u_int32_t h, rxmode; 1527 1528 /* First, zot all the existing filters. */ 1529 rxmode = CSR_READ_4(sc, BGE_RX_MODE) & ~BGE_RXMODE_RX_PROMISC; 1530 ifp->if_flags &= ~IFF_ALLMULTI; 1531 memset(hashes, 0x00, sizeof(hashes)); 1532 1533 if (ifp->if_flags & IFF_PROMISC) { 1534 ifp->if_flags |= IFF_ALLMULTI; 1535 rxmode |= BGE_RXMODE_RX_PROMISC; 1536 } else if (ac->ac_multirangecnt > 0) { 1537 ifp->if_flags |= IFF_ALLMULTI; 1538 memset(hashes, 0xff, sizeof(hashes)); 1539 } else { 1540 ETHER_FIRST_MULTI(step, ac, enm); 1541 while (enm != NULL) { 1542 h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1543 1544 setbit(hashes, h & 0x7F); 1545 1546 ETHER_NEXT_MULTI(step, enm); 1547 } 1548 } 1549 1550 bus_space_write_raw_region_4(sc->bge_btag, sc->bge_bhandle, BGE_MAR0, 1551 hashes, sizeof(hashes)); 1552 CSR_WRITE_4(sc, BGE_RX_MODE, rxmode); 1553 } 1554 1555 void 1556 bge_sig_pre_reset(struct bge_softc *sc, int type) 1557 { 1558 /* no bge_asf_mode. */ 1559 1560 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1561 bge_ape_driver_state_change(sc, type); 1562 } 1563 1564 void 1565 bge_sig_post_reset(struct bge_softc *sc, int type) 1566 { 1567 /* no bge_asf_mode. */ 1568 1569 if (type == BGE_RESET_SHUTDOWN) 1570 bge_ape_driver_state_change(sc, type); 1571 } 1572 1573 void 1574 bge_sig_legacy(struct bge_softc *sc, int type) 1575 { 1576 /* no bge_asf_mode. */ 1577 } 1578 1579 void 1580 bge_stop_fw(struct bge_softc *sc, int type) 1581 { 1582 /* no bge_asf_mode. */ 1583 } 1584 1585 u_int32_t 1586 bge_dma_swap_options(struct bge_softc *sc) 1587 { 1588 u_int32_t dma_options = BGE_DMA_SWAP_OPTIONS; 1589 1590 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 1591 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1592 BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE | 1593 BGE_MODECTL_HTX2B_ENABLE; 1594 } 1595 1596 return (dma_options); 1597 } 1598 1599 int 1600 bge_phy_addr(struct bge_softc *sc) 1601 { 1602 struct pci_attach_args *pa = &(sc->bge_pa); 1603 int phy_addr = 1; 1604 1605 switch (BGE_ASICREV(sc->bge_chipid)) { 1606 case BGE_ASICREV_BCM5717: 1607 case BGE_ASICREV_BCM5719: 1608 case BGE_ASICREV_BCM5720: 1609 phy_addr = pa->pa_function; 1610 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 1611 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) & 1612 BGE_SGDIGSTS_IS_SERDES) ? 8 : 1; 1613 } else { 1614 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 1615 BGE_CPMU_PHY_STRAP_IS_SERDES) ? 8 : 1; 1616 } 1617 } 1618 1619 return (phy_addr); 1620 } 1621 1622 /* 1623 * Do endian, PCI and DMA initialization. 1624 */ 1625 void 1626 bge_chipinit(struct bge_softc *sc) 1627 { 1628 struct pci_attach_args *pa = &(sc->bge_pa); 1629 u_int32_t dma_rw_ctl, misc_ctl, mode_ctl; 1630 int i; 1631 1632 /* Set endianness before we access any non-PCI registers. */ 1633 misc_ctl = BGE_INIT; 1634 if (sc->bge_flags & BGE_TAGGED_STATUS) 1635 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1636 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1637 misc_ctl); 1638 1639 /* 1640 * Clear the MAC statistics block in the NIC's 1641 * internal memory. 1642 */ 1643 for (i = BGE_STATS_BLOCK; 1644 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1645 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1646 1647 for (i = BGE_STATUS_BLOCK; 1648 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1649 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 1650 1651 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57765 || 1652 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57766) { 1653 /* 1654 * For the 57766 and non Ax versions of 57765, bootcode 1655 * needs to setup the PCIE Fast Training Sequence (FTS) 1656 * value to prevent transmit hangs. 1657 */ 1658 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_57765_AX) { 1659 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1660 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1661 BGE_CPMU_PADRNG_CTL_RDIV2); 1662 } 1663 } 1664 1665 /* 1666 * Set up the PCI DMA control register. 1667 */ 1668 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1669 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1670 1671 if (sc->bge_flags & BGE_PCIE) { 1672 if (sc->bge_mps >= 256) 1673 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1674 else 1675 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1676 } else if (sc->bge_flags & BGE_PCIX) { 1677 /* PCI-X bus */ 1678 if (BGE_IS_5714_FAMILY(sc)) { 1679 /* 256 bytes for read and write. */ 1680 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1681 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1682 1683 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780) 1684 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1685 else 1686 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1687 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1688 /* 1536 bytes for read, 384 bytes for write. */ 1689 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1690 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1691 } else { 1692 /* 384 bytes for read and write. */ 1693 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1694 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1695 (0x0F); 1696 } 1697 1698 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1699 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 1700 u_int32_t tmp; 1701 1702 /* Set ONEDMA_ATONCE for hardware workaround. */ 1703 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1704 if (tmp == 6 || tmp == 7) 1705 dma_rw_ctl |= 1706 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1707 1708 /* Set PCI-X DMA write workaround. */ 1709 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1710 } 1711 } else { 1712 /* Conventional PCI bus: 256 bytes for read and write. */ 1713 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1714 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1715 1716 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5705 && 1717 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5750) 1718 dma_rw_ctl |= 0x0F; 1719 } 1720 1721 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 1722 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) 1723 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1724 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1725 1726 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 || 1727 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1728 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1729 1730 if (BGE_IS_5717_PLUS(sc)) { 1731 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1732 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1733 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1734 1735 /* 1736 * Enable HW workaround for controllers that misinterpret 1737 * a status tag update and leave interrupts permanently 1738 * disabled. 1739 */ 1740 if (!BGE_IS_57765_PLUS(sc) && 1741 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 1742 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762) 1743 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1744 } 1745 1746 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl); 1747 1748 /* 1749 * Set up general mode register. 1750 */ 1751 mode_ctl = bge_dma_swap_options(sc); 1752 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 1753 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 1754 /* Retain Host-2-BMC settings written by APE firmware. */ 1755 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1756 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1757 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1758 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1759 } 1760 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1761 BGE_MODECTL_TX_NO_PHDR_CSUM; 1762 1763 /* 1764 * BCM5701 B5 have a bug causing data corruption when using 1765 * 64-bit DMA reads, which can be terminated early and then 1766 * completed later as 32-bit accesses, in combination with 1767 * certain bridges. 1768 */ 1769 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 1770 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1771 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1772 1773 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1774 1775 /* 1776 * Disable memory write invalidate. Apparently it is not supported 1777 * properly by these devices. 1778 */ 1779 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 1780 PCI_COMMAND_INVALIDATE_ENABLE); 1781 1782 #ifdef __brokenalpha__ 1783 /* 1784 * Must ensure that we do not cross an 8K (bytes) boundary 1785 * for DMA reads. Our highest limit is 1K bytes. This is a 1786 * restriction on some ALPHA platforms with early revision 1787 * 21174 PCI chipsets, such as the AlphaPC 164lx 1788 */ 1789 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1790 BGE_PCI_READ_BNDRY_1024); 1791 #endif 1792 1793 /* Set the timer prescaler (always 66MHz) */ 1794 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1795 1796 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1797 DELAY(40); /* XXX */ 1798 1799 /* Put PHY into ready state */ 1800 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1801 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1802 DELAY(40); 1803 } 1804 } 1805 1806 int 1807 bge_blockinit(struct bge_softc *sc) 1808 { 1809 volatile struct bge_rcb *rcb; 1810 vaddr_t rcb_addr; 1811 bge_hostaddr taddr; 1812 u_int32_t dmactl, rdmareg, mimode, val; 1813 int i, limit; 1814 1815 /* 1816 * Initialize the memory window pointer register so that 1817 * we can access the first 32K of internal NIC RAM. This will 1818 * allow us to set up the TX send ring RCBs and the RX return 1819 * ring RCBs, plus other things which live in NIC memory. 1820 */ 1821 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1822 1823 /* Configure mbuf memory pool */ 1824 if (!BGE_IS_5705_PLUS(sc)) { 1825 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1826 BGE_BUFFPOOL_1); 1827 1828 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 1829 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1830 else 1831 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1832 1833 /* Configure DMA resource pool */ 1834 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1835 BGE_DMA_DESCRIPTORS); 1836 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1837 } 1838 1839 /* Configure mbuf pool watermarks */ 1840 /* new Broadcom docs strongly recommend these: */ 1841 if (BGE_IS_5717_PLUS(sc)) { 1842 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1843 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1844 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1845 } else if (BGE_IS_5705_PLUS(sc)) { 1846 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1847 1848 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 1849 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1850 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1851 } else { 1852 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1853 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1854 } 1855 } else { 1856 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1857 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1858 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1859 } 1860 1861 /* Configure DMA resource watermarks */ 1862 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1863 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1864 1865 /* Enable buffer manager */ 1866 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1867 /* 1868 * Change the arbitration algorithm of TXMBUF read request to 1869 * round-robin instead of priority based for BCM5719. When 1870 * TXFIFO is almost empty, RDMA will hold its request until 1871 * TXFIFO is not almost empty. 1872 */ 1873 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 1874 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 1875 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 1876 1877 /* Poll for buffer manager start indication */ 1878 for (i = 0; i < 2000; i++) { 1879 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1880 break; 1881 DELAY(10); 1882 } 1883 1884 if (i == 2000) { 1885 printf("%s: buffer manager failed to start\n", 1886 sc->bge_dev.dv_xname); 1887 return (ENXIO); 1888 } 1889 1890 /* Enable flow-through queues */ 1891 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1892 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1893 1894 /* Wait until queue initialization is complete */ 1895 for (i = 0; i < 2000; i++) { 1896 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1897 break; 1898 DELAY(10); 1899 } 1900 1901 if (i == 2000) { 1902 printf("%s: flow-through queue init failed\n", 1903 sc->bge_dev.dv_xname); 1904 return (ENXIO); 1905 } 1906 1907 /* 1908 * Summary of rings supported by the controller: 1909 * 1910 * Standard Receive Producer Ring 1911 * - This ring is used to feed receive buffers for "standard" 1912 * sized frames (typically 1536 bytes) to the controller. 1913 * 1914 * Jumbo Receive Producer Ring 1915 * - This ring is used to feed receive buffers for jumbo sized 1916 * frames (i.e. anything bigger than the "standard" frames) 1917 * to the controller. 1918 * 1919 * Mini Receive Producer Ring 1920 * - This ring is used to feed receive buffers for "mini" 1921 * sized frames to the controller. 1922 * - This feature required external memory for the controller 1923 * but was never used in a production system. Should always 1924 * be disabled. 1925 * 1926 * Receive Return Ring 1927 * - After the controller has placed an incoming frame into a 1928 * receive buffer that buffer is moved into a receive return 1929 * ring. The driver is then responsible to passing the 1930 * buffer up to the stack. Many versions of the controller 1931 * support multiple RR rings. 1932 * 1933 * Send Ring 1934 * - This ring is used for outgoing frames. Many versions of 1935 * the controller support multiple send rings. 1936 */ 1937 1938 /* Initialize the standard RX ring control block */ 1939 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1940 BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring)); 1941 if (BGE_IS_5717_PLUS(sc)) { 1942 /* 1943 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 1944 * Bits 15-2 : Maximum RX frame size 1945 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 1946 * Bit 0 : Reserved 1947 */ 1948 rcb->bge_maxlen_flags = 1949 BGE_RCB_MAXLEN_FLAGS(512, ETHER_MAX_DIX_LEN << 2); 1950 } else if (BGE_IS_5705_PLUS(sc)) { 1951 /* 1952 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1953 * Bits 15-2 : Reserved (should be 0) 1954 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1955 * Bit 0 : Reserved 1956 */ 1957 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1958 } else { 1959 /* 1960 * Ring size is always XXX entries 1961 * Bits 31-16: Maximum RX frame size 1962 * Bits 15-2 : Reserved (should be 0) 1963 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1964 * Bit 0 : Reserved 1965 */ 1966 rcb->bge_maxlen_flags = 1967 BGE_RCB_MAXLEN_FLAGS(ETHER_MAX_DIX_LEN, 0); 1968 } 1969 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1970 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 1971 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 1972 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 1973 else 1974 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1975 /* Write the standard receive producer ring control block. */ 1976 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1977 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1978 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1979 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1980 1981 /* Reset the standard receive producer ring producer index. */ 1982 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1983 1984 /* 1985 * Initialize the Jumbo RX ring control block 1986 * We set the 'ring disabled' bit in the flags 1987 * field until we're actually ready to start 1988 * using this ring (i.e. once we set the MTU 1989 * high enough to require it). 1990 */ 1991 if (sc->bge_flags & BGE_JUMBO_RING) { 1992 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1993 BGE_HOSTADDR(rcb->bge_hostaddr, 1994 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring)); 1995 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1996 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1997 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 1998 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 1999 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2000 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2001 else 2002 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2003 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2004 rcb->bge_hostaddr.bge_addr_hi); 2005 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2006 rcb->bge_hostaddr.bge_addr_lo); 2007 /* Program the jumbo receive producer ring RCB parameters. */ 2008 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2009 rcb->bge_maxlen_flags); 2010 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2011 /* Reset the jumbo receive producer ring producer index. */ 2012 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2013 } 2014 2015 /* Disable the mini receive producer ring RCB. */ 2016 if (BGE_IS_5700_FAMILY(sc)) { 2017 /* Set up dummy disabled mini ring RCB */ 2018 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 2019 rcb->bge_maxlen_flags = 2020 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2021 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2022 rcb->bge_maxlen_flags); 2023 /* Reset the mini receive producer ring producer index. */ 2024 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2025 2026 /* XXX why? */ 2027 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 2028 offsetof(struct bge_ring_data, bge_info), 2029 sizeof (struct bge_gib), 2030 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2031 } 2032 2033 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2034 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 2035 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2036 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2037 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2038 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2039 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2040 } 2041 /* 2042 * The BD ring replenish thresholds control how often the 2043 * hardware fetches new BD's from the producer rings in host 2044 * memory. Setting the value too low on a busy system can 2045 * starve the hardware and recue the throughpout. 2046 * 2047 * Set the BD ring replenish thresholds. The recommended 2048 * values are 1/8th the number of descriptors allocated to 2049 * each ring, but since we try to avoid filling the entire 2050 * ring we set these to the minimal value of 8. This needs to 2051 * be done on several of the supported chip revisions anyway, 2052 * to work around HW bugs. 2053 */ 2054 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8); 2055 if (sc->bge_flags & BGE_JUMBO_RING) 2056 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8); 2057 2058 if (BGE_IS_5717_PLUS(sc)) { 2059 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4); 2060 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4); 2061 } 2062 2063 /* 2064 * Disable all send rings by setting the 'ring disabled' bit 2065 * in the flags field of all the TX send ring control blocks, 2066 * located in NIC memory. 2067 */ 2068 if (BGE_IS_5700_FAMILY(sc)) { 2069 /* 5700 to 5704 had 16 send rings. */ 2070 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2071 } else if (BGE_IS_57765_PLUS(sc) || 2072 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2073 limit = 2; 2074 else if (BGE_IS_5717_PLUS(sc)) 2075 limit = 4; 2076 else 2077 limit = 1; 2078 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2079 for (i = 0; i < limit; i++) { 2080 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2081 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2082 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2083 rcb_addr += sizeof(struct bge_rcb); 2084 } 2085 2086 /* Configure send ring RCB 0 (we use only the first ring) */ 2087 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2088 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 2089 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2090 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2091 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2092 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2093 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2094 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, BGE_SEND_RING_5717); 2095 else 2096 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 2097 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2098 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2099 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2100 2101 /* 2102 * Disable all receive return rings by setting the 2103 * 'ring diabled' bit in the flags field of all the receive 2104 * return ring control blocks, located in NIC memory. 2105 */ 2106 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717 || 2107 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2108 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2109 /* Should be 17, use 16 until we get an SRAM map. */ 2110 limit = 16; 2111 } else if (BGE_IS_5700_FAMILY(sc)) 2112 limit = BGE_RX_RINGS_MAX; 2113 else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2114 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762 || 2115 BGE_IS_57765_PLUS(sc)) 2116 limit = 4; 2117 else 2118 limit = 1; 2119 /* Disable all receive return rings */ 2120 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2121 for (i = 0; i < limit; i++) { 2122 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 2123 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 2124 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2125 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 2126 BGE_RCB_FLAG_RING_DISABLED)); 2127 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 2128 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2129 (i * (sizeof(u_int64_t))), 0); 2130 rcb_addr += sizeof(struct bge_rcb); 2131 } 2132 2133 /* 2134 * Set up receive return ring 0. Note that the NIC address 2135 * for RX return rings is 0x0. The return rings live entirely 2136 * within the host, so the nicaddr field in the RCB isn't used. 2137 */ 2138 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2139 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 2140 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2141 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2142 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 2143 RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags, 2144 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2145 2146 /* Set random backoff seed for TX */ 2147 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2148 (sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 2149 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 2150 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) & 2151 BGE_TX_BACKOFF_SEED_MASK); 2152 2153 /* Set inter-packet gap */ 2154 val = 0x2620; 2155 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2156 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2157 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2158 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2159 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2160 2161 /* 2162 * Specify which ring to use for packets that don't match 2163 * any RX rules. 2164 */ 2165 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2166 2167 /* 2168 * Configure number of RX lists. One interrupt distribution 2169 * list, sixteen active lists, one bad frames class. 2170 */ 2171 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2172 2173 /* Inialize RX list placement stats mask. */ 2174 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007BFFFF); 2175 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2176 2177 /* Disable host coalescing until we get it set up */ 2178 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2179 2180 /* Poll to make sure it's shut down. */ 2181 for (i = 0; i < 2000; i++) { 2182 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2183 break; 2184 DELAY(10); 2185 } 2186 2187 if (i == 2000) { 2188 printf("%s: host coalescing engine failed to idle\n", 2189 sc->bge_dev.dv_xname); 2190 return (ENXIO); 2191 } 2192 2193 /* Set up host coalescing defaults */ 2194 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2195 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2196 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2197 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2198 if (!(BGE_IS_5705_PLUS(sc))) { 2199 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2200 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2201 } 2202 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 2203 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 2204 2205 /* Set up address of statistics block */ 2206 if (!(BGE_IS_5705_PLUS(sc))) { 2207 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 2208 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi); 2209 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo); 2210 2211 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2212 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2213 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2214 } 2215 2216 /* Set up address of status block */ 2217 BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block)); 2218 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi); 2219 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo); 2220 2221 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 2222 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 2223 2224 /* Set up status block size. */ 2225 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 && 2226 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2227 val = BGE_STATBLKSZ_FULL; 2228 bzero(&sc->bge_rdata->bge_status_block, BGE_STATUS_BLK_SZ); 2229 } else { 2230 val = BGE_STATBLKSZ_32BYTE; 2231 bzero(&sc->bge_rdata->bge_status_block, 32); 2232 } 2233 2234 /* Turn on host coalescing state machine */ 2235 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2236 2237 /* Turn on RX BD completion state machine and enable attentions */ 2238 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2239 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 2240 2241 /* Turn on RX list placement state machine */ 2242 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2243 2244 /* Turn on RX list selector state machine. */ 2245 if (!(BGE_IS_5705_PLUS(sc))) 2246 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2247 2248 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2249 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2250 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2251 BGE_MACMODE_FRMHDR_DMA_ENB; 2252 2253 if (sc->bge_flags & BGE_FIBER_TBI) 2254 val |= BGE_PORTMODE_TBI; 2255 else if (sc->bge_flags & BGE_FIBER_MII) 2256 val |= BGE_PORTMODE_GMII; 2257 else 2258 val |= BGE_PORTMODE_MII; 2259 2260 /* Allow APE to send/receive frames. */ 2261 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2262 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2263 2264 /* Turn on DMA, clear stats */ 2265 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2266 DELAY(40); 2267 2268 /* Set misc. local control, enable interrupts on attentions */ 2269 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2270 2271 #ifdef notdef 2272 /* Assert GPIO pins for PHY reset */ 2273 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 2274 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 2275 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 2276 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 2277 #endif 2278 2279 /* Turn on DMA completion state machine */ 2280 if (!(BGE_IS_5705_PLUS(sc))) 2281 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2282 2283 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; 2284 2285 /* Enable host coalescing bug fix. */ 2286 if (BGE_IS_5755_PLUS(sc)) 2287 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2288 2289 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785) 2290 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2291 2292 /* Turn on write DMA state machine */ 2293 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2294 DELAY(40); 2295 2296 val = BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS; 2297 2298 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5717) 2299 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2300 2301 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2302 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2303 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2304 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2305 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2306 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2307 2308 if (sc->bge_flags & BGE_PCIE) 2309 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2310 2311 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 2312 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2313 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2314 BGE_RDMAMODE_H2BNC_VLAN_DET; 2315 /* 2316 * Allow multiple outstanding read requests from 2317 * non-LSO read DMA engine. 2318 */ 2319 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2320 } 2321 2322 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2323 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2324 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2325 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780 || 2326 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2327 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 2328 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2329 else 2330 rdmareg = BGE_RDMA_RSRVCTRL; 2331 dmactl = CSR_READ_4(sc, rdmareg); 2332 /* 2333 * Adjust tx margin to prevent TX data corruption and 2334 * fix internal FIFO overflow. 2335 */ 2336 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2337 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2338 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2339 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2340 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2341 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2342 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2343 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2344 } 2345 /* 2346 * Enable fix for read DMA FIFO overruns. 2347 * The fix is to limit the number of RX BDs 2348 * the hardware would fetch at a fime. 2349 */ 2350 CSR_WRITE_4(sc, rdmareg, dmactl | 2351 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2352 } 2353 2354 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) { 2355 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2356 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2357 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2358 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2359 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2360 /* 2361 * Allow 4KB burst length reads for non-LSO frames. 2362 * Enable 512B burst length reads for buffer descriptors. 2363 */ 2364 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2365 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2366 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2367 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2368 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 2369 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2370 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2371 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2372 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2373 } 2374 2375 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2376 DELAY(40); 2377 2378 if (sc->bge_flags & BGE_RDMA_BUG) { 2379 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2380 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2381 if ((val & 0xFFFF) > ETHER_MAX_LEN) 2382 break; 2383 if (((val >> 16) & 0xFFFF) > ETHER_MAX_LEN) 2384 break; 2385 } 2386 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2387 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2388 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 2389 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2390 else 2391 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2392 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2393 } 2394 } 2395 2396 /* Turn on RX data completion state machine */ 2397 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2398 2399 /* Turn on RX BD initiator state machine */ 2400 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2401 2402 /* Turn on RX data and RX BD initiator state machine */ 2403 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2404 2405 /* Turn on Mbuf cluster free state machine */ 2406 if (!BGE_IS_5705_PLUS(sc)) 2407 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2408 2409 /* Turn on send BD completion state machine */ 2410 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2411 2412 /* Turn on send data completion state machine */ 2413 val = BGE_SDCMODE_ENABLE; 2414 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761) 2415 val |= BGE_SDCMODE_CDELAY; 2416 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2417 2418 /* Turn on send data initiator state machine */ 2419 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2420 2421 /* Turn on send BD initiator state machine */ 2422 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2423 2424 /* Turn on send BD selector state machine */ 2425 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2426 2427 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007BFFFF); 2428 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2429 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 2430 2431 /* ack/clear link change events */ 2432 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2433 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2434 BGE_MACSTAT_LINK_CHANGED); 2435 2436 /* Enable PHY auto polling (for MII/GMII only) */ 2437 if (sc->bge_flags & BGE_FIBER_TBI) { 2438 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2439 } else { 2440 if ((sc->bge_flags & BGE_CPMU_PRESENT) != 0) 2441 mimode = BGE_MIMODE_500KHZ_CONST; 2442 else 2443 mimode = BGE_MIMODE_BASE; 2444 if (BGE_IS_5700_FAMILY(sc) || 2445 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705) { 2446 mimode |= BGE_MIMODE_AUTOPOLL; 2447 BGE_STS_SETBIT(sc, BGE_STS_AUTOPOLL); 2448 } 2449 mimode |= BGE_MIMODE_PHYADDR(sc->bge_phy_addr); 2450 CSR_WRITE_4(sc, BGE_MI_MODE, mimode); 2451 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) 2452 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2453 BGE_EVTENB_MI_INTERRUPT); 2454 } 2455 2456 /* 2457 * Clear any pending link state attention. 2458 * Otherwise some link state change events may be lost until attention 2459 * is cleared by bge_intr() -> bge_link_upd() sequence. 2460 * It's not necessary on newer BCM chips - perhaps enabling link 2461 * state change attentions implies clearing pending attention. 2462 */ 2463 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2464 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2465 BGE_MACSTAT_LINK_CHANGED); 2466 2467 /* Enable link state change attentions. */ 2468 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2469 2470 return (0); 2471 } 2472 2473 const struct bge_revision * 2474 bge_lookup_rev(u_int32_t chipid) 2475 { 2476 const struct bge_revision *br; 2477 2478 for (br = bge_revisions; br->br_name != NULL; br++) { 2479 if (br->br_chipid == chipid) 2480 return (br); 2481 } 2482 2483 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2484 if (br->br_chipid == BGE_ASICREV(chipid)) 2485 return (br); 2486 } 2487 2488 return (NULL); 2489 } 2490 2491 int 2492 bge_can_use_msi(struct bge_softc *sc) 2493 { 2494 int can_use_msi = 0; 2495 2496 switch (BGE_ASICREV(sc->bge_chipid)) { 2497 case BGE_ASICREV_BCM5714_A0: 2498 case BGE_ASICREV_BCM5714: 2499 /* 2500 * Apparently, MSI doesn't work when these chips are 2501 * configured in single-port mode. 2502 */ 2503 break; 2504 case BGE_ASICREV_BCM5750: 2505 if (BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_AX && 2506 BGE_CHIPREV(sc->bge_chipid) != BGE_CHIPREV_5750_BX) 2507 can_use_msi = 1; 2508 break; 2509 default: 2510 if (BGE_IS_575X_PLUS(sc)) 2511 can_use_msi = 1; 2512 } 2513 2514 return (can_use_msi); 2515 } 2516 2517 /* 2518 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2519 * against our list and return its name if we find a match. Note 2520 * that since the Broadcom controller contains VPD support, we 2521 * can get the device name string from the controller itself instead 2522 * of the compiled-in string. This is a little slow, but it guarantees 2523 * we'll always announce the right product name. 2524 */ 2525 int 2526 bge_probe(struct device *parent, void *match, void *aux) 2527 { 2528 return (pci_matchbyid(aux, bge_devices, nitems(bge_devices))); 2529 } 2530 2531 void 2532 bge_attach(struct device *parent, struct device *self, void *aux) 2533 { 2534 struct bge_softc *sc = (struct bge_softc *)self; 2535 struct pci_attach_args *pa = aux; 2536 pci_chipset_tag_t pc = pa->pa_pc; 2537 const struct bge_revision *br; 2538 pcireg_t pm_ctl, memtype, subid, reg; 2539 pci_intr_handle_t ih; 2540 const char *intrstr = NULL; 2541 int gotenaddr = 0; 2542 u_int32_t hwcfg = 0; 2543 u_int32_t mac_addr = 0; 2544 u_int32_t misccfg; 2545 struct ifnet *ifp; 2546 caddr_t kva; 2547 #ifdef __sparc64__ 2548 char name[32]; 2549 #endif 2550 2551 sc->bge_pa = *pa; 2552 2553 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 2554 2555 /* 2556 * Map control/status registers. 2557 */ 2558 DPRINTFN(5, ("Map control/status regs\n")); 2559 2560 DPRINTFN(5, ("pci_mapreg_map\n")); 2561 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0); 2562 if (pci_mapreg_map(pa, BGE_PCI_BAR0, memtype, 0, &sc->bge_btag, 2563 &sc->bge_bhandle, NULL, &sc->bge_bsize, 0)) { 2564 printf(": can't find mem space\n"); 2565 return; 2566 } 2567 2568 /* 2569 * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?) 2570 * can clobber the chip's PCI config-space power control registers, 2571 * leaving the card in D3 powersave state. 2572 * We do not have memory-mapped registers in this state, 2573 * so force device into D0 state before starting initialization. 2574 */ 2575 pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD); 2576 pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3); 2577 pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */ 2578 pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl); 2579 DELAY(1000); /* 27 usec is allegedly sufficent */ 2580 2581 /* 2582 * Save ASIC rev. 2583 */ 2584 sc->bge_chipid = 2585 (pci_conf_read(pc, pa->pa_tag, BGE_PCI_MISC_CTL) 2586 >> BGE_PCIMISCCTL_ASICREV_SHIFT); 2587 2588 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2589 switch (PCI_PRODUCT(pa->pa_id)) { 2590 case PCI_PRODUCT_BROADCOM_BCM5717: 2591 case PCI_PRODUCT_BROADCOM_BCM5718: 2592 case PCI_PRODUCT_BROADCOM_BCM5719: 2593 case PCI_PRODUCT_BROADCOM_BCM5720: 2594 case PCI_PRODUCT_BROADCOM_BCM5725: 2595 case PCI_PRODUCT_BROADCOM_BCM5727: 2596 case PCI_PRODUCT_BROADCOM_BCM5762: 2597 case PCI_PRODUCT_BROADCOM_BCM57764: 2598 case PCI_PRODUCT_BROADCOM_BCM57767: 2599 case PCI_PRODUCT_BROADCOM_BCM57787: 2600 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2601 BGE_PCI_GEN2_PRODID_ASICREV); 2602 break; 2603 case PCI_PRODUCT_BROADCOM_BCM57761: 2604 case PCI_PRODUCT_BROADCOM_BCM57762: 2605 case PCI_PRODUCT_BROADCOM_BCM57765: 2606 case PCI_PRODUCT_BROADCOM_BCM57766: 2607 case PCI_PRODUCT_BROADCOM_BCM57781: 2608 case PCI_PRODUCT_BROADCOM_BCM57782: 2609 case PCI_PRODUCT_BROADCOM_BCM57785: 2610 case PCI_PRODUCT_BROADCOM_BCM57786: 2611 case PCI_PRODUCT_BROADCOM_BCM57791: 2612 case PCI_PRODUCT_BROADCOM_BCM57795: 2613 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2614 BGE_PCI_GEN15_PRODID_ASICREV); 2615 break; 2616 default: 2617 sc->bge_chipid = pci_conf_read(pc, pa->pa_tag, 2618 BGE_PCI_PRODID_ASICREV); 2619 break; 2620 } 2621 } 2622 2623 sc->bge_phy_addr = bge_phy_addr(sc); 2624 2625 printf(", "); 2626 br = bge_lookup_rev(sc->bge_chipid); 2627 if (br == NULL) 2628 printf("unknown ASIC (0x%x)", sc->bge_chipid); 2629 else 2630 printf("%s (0x%x)", br->br_name, sc->bge_chipid); 2631 2632 /* 2633 * PCI Express or PCI-X controller check. 2634 */ 2635 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 2636 &sc->bge_expcap, NULL) != 0) { 2637 /* Extract supported maximum payload size. */ 2638 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, sc->bge_expcap + 2639 PCI_PCIE_DCAP); 2640 sc->bge_mps = 128 << (reg & 0x7); 2641 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2642 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 2643 sc->bge_expmrq = (fls(2048) - 8) << 12; 2644 else 2645 sc->bge_expmrq = (fls(4096) - 8) << 12; 2646 /* Disable PCIe Active State Power Management (ASPM). */ 2647 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, 2648 sc->bge_expcap + PCI_PCIE_LCSR); 2649 reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1); 2650 pci_conf_write(pa->pa_pc, pa->pa_tag, 2651 sc->bge_expcap + PCI_PCIE_LCSR, reg); 2652 sc->bge_flags |= BGE_PCIE; 2653 } else { 2654 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) & 2655 BGE_PCISTATE_PCI_BUSMODE) == 0) 2656 sc->bge_flags |= BGE_PCIX; 2657 } 2658 2659 /* 2660 * SEEPROM check. 2661 */ 2662 #ifdef __sparc64__ 2663 /* 2664 * Onboard interfaces on UltraSPARC systems generally don't 2665 * have a SEEPROM fitted. These interfaces, and cards that 2666 * have FCode, are named "network" by the PROM, whereas cards 2667 * without FCode show up as "ethernet". Since we don't really 2668 * need the information from the SEEPROM on cards that have 2669 * FCode it's fine to pretend they don't have one. 2670 */ 2671 if (OF_getprop(PCITAG_NODE(pa->pa_tag), "name", name, 2672 sizeof(name)) > 0 && strcmp(name, "network") == 0) 2673 sc->bge_flags |= BGE_NO_EEPROM; 2674 #endif 2675 2676 /* Save chipset family. */ 2677 switch (BGE_ASICREV(sc->bge_chipid)) { 2678 case BGE_ASICREV_BCM5762: 2679 case BGE_ASICREV_BCM57765: 2680 case BGE_ASICREV_BCM57766: 2681 sc->bge_flags |= BGE_57765_PLUS; 2682 /* FALLTHROUGH */ 2683 case BGE_ASICREV_BCM5717: 2684 case BGE_ASICREV_BCM5719: 2685 case BGE_ASICREV_BCM5720: 2686 sc->bge_flags |= BGE_5717_PLUS | BGE_5755_PLUS | BGE_575X_PLUS | 2687 BGE_5705_PLUS | BGE_JUMBO_CAPABLE | BGE_JUMBO_RING | 2688 BGE_JUMBO_FRAME; 2689 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 || 2690 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) { 2691 /* 2692 * Enable work around for DMA engine miscalculation 2693 * of TXMBUF available space. 2694 */ 2695 sc->bge_flags |= BGE_RDMA_BUG; 2696 2697 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719 && 2698 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2699 /* Jumbo frame on BCM5719 A0 does not work. */ 2700 sc->bge_flags &= ~(BGE_JUMBO_CAPABLE | 2701 BGE_JUMBO_RING | BGE_JUMBO_FRAME); 2702 } 2703 } 2704 break; 2705 case BGE_ASICREV_BCM5755: 2706 case BGE_ASICREV_BCM5761: 2707 case BGE_ASICREV_BCM5784: 2708 case BGE_ASICREV_BCM5785: 2709 case BGE_ASICREV_BCM5787: 2710 case BGE_ASICREV_BCM57780: 2711 sc->bge_flags |= BGE_5755_PLUS | BGE_575X_PLUS | BGE_5705_PLUS; 2712 break; 2713 case BGE_ASICREV_BCM5700: 2714 case BGE_ASICREV_BCM5701: 2715 case BGE_ASICREV_BCM5703: 2716 case BGE_ASICREV_BCM5704: 2717 sc->bge_flags |= BGE_5700_FAMILY | BGE_JUMBO_CAPABLE | BGE_JUMBO_RING; 2718 break; 2719 case BGE_ASICREV_BCM5714_A0: 2720 case BGE_ASICREV_BCM5780: 2721 case BGE_ASICREV_BCM5714: 2722 sc->bge_flags |= BGE_5714_FAMILY | BGE_JUMBO_CAPABLE | BGE_JUMBO_STD; 2723 /* FALLTHROUGH */ 2724 case BGE_ASICREV_BCM5750: 2725 case BGE_ASICREV_BCM5752: 2726 case BGE_ASICREV_BCM5906: 2727 sc->bge_flags |= BGE_575X_PLUS; 2728 /* FALLTHROUGH */ 2729 case BGE_ASICREV_BCM5705: 2730 sc->bge_flags |= BGE_5705_PLUS; 2731 break; 2732 } 2733 2734 if (sc->bge_flags & BGE_JUMBO_STD) 2735 sc->bge_rx_std_len = BGE_JLEN; 2736 else 2737 sc->bge_rx_std_len = MCLBYTES; 2738 2739 /* 2740 * When using the BCM5701 in PCI-X mode, data corruption has 2741 * been observed in the first few bytes of some received packets. 2742 * Aligning the packet buffer in memory eliminates the corruption. 2743 * Unfortunately, this misaligns the packet payloads. On platforms 2744 * which do not support unaligned accesses, we will realign the 2745 * payloads by copying the received packets. 2746 */ 2747 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 && 2748 sc->bge_flags & BGE_PCIX) 2749 sc->bge_flags |= BGE_RX_ALIGNBUG; 2750 2751 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2752 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) && 2753 PCI_VENDOR(subid) == DELL_VENDORID) 2754 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 2755 2756 misccfg = CSR_READ_4(sc, BGE_MISC_CFG); 2757 misccfg &= BGE_MISCCFG_BOARD_ID_MASK; 2758 2759 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2760 (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2761 misccfg == BGE_MISCCFG_BOARD_ID_5788M)) 2762 sc->bge_flags |= BGE_IS_5788; 2763 2764 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 && 2765 (misccfg == 0x4000 || misccfg == 0x8000)) || 2766 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2767 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2768 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 || 2769 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 || 2770 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) || 2771 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 2772 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F || 2773 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F || 2774 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) || 2775 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57790 || 2776 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57791 || 2777 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM57795 || 2778 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2779 sc->bge_phy_flags |= BGE_PHY_10_100_ONLY; 2780 2781 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 2782 (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 && 2783 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2784 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2785 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2786 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 2787 2788 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2789 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2790 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 2791 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX || 2792 BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX) 2793 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 2794 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2795 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 2796 2797 if ((BGE_IS_5705_PLUS(sc)) && 2798 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906 && 2799 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 2800 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM57780 && 2801 !BGE_IS_5717_PLUS(sc)) { 2802 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 || 2803 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2804 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2805 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) { 2806 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 && 2807 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756) 2808 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 2809 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M) 2810 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 2811 } else 2812 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 2813 } 2814 2815 /* Identify chips with APE processor. */ 2816 switch (BGE_ASICREV(sc->bge_chipid)) { 2817 case BGE_ASICREV_BCM5717: 2818 case BGE_ASICREV_BCM5719: 2819 case BGE_ASICREV_BCM5720: 2820 case BGE_ASICREV_BCM5761: 2821 case BGE_ASICREV_BCM5762: 2822 sc->bge_flags |= BGE_APE; 2823 break; 2824 } 2825 2826 /* Chips with APE need BAR2 access for APE registers/memory. */ 2827 if ((sc->bge_flags & BGE_APE) != 0) { 2828 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR2); 2829 if (pci_mapreg_map(pa, BGE_PCI_BAR2, memtype, 0, 2830 &sc->bge_apetag, &sc->bge_apehandle, NULL, 2831 &sc->bge_apesize, 0)) { 2832 printf(": couldn't map BAR2 memory\n"); 2833 goto fail_1; 2834 } 2835 2836 /* Enable APE register/memory access by host driver. */ 2837 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 2838 reg |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 2839 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 2840 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 2841 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, reg); 2842 2843 bge_ape_lock_init(sc); 2844 bge_ape_read_fw_ver(sc); 2845 } 2846 2847 /* Identify the chips that use an CPMU. */ 2848 if (BGE_IS_5717_PLUS(sc) || 2849 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 || 2850 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5761 || 2851 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 || 2852 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780) 2853 sc->bge_flags |= BGE_CPMU_PRESENT; 2854 2855 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, 2856 &sc->bge_msicap, NULL)) { 2857 if (bge_can_use_msi(sc) == 0) 2858 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 2859 } 2860 2861 DPRINTFN(5, ("pci_intr_map\n")); 2862 if (pci_intr_map_msi(pa, &ih) == 0) 2863 sc->bge_flags |= BGE_MSI; 2864 else if (pci_intr_map(pa, &ih)) { 2865 printf(": couldn't map interrupt\n"); 2866 goto fail_1; 2867 } 2868 2869 /* 2870 * All controllers except BCM5700 supports tagged status but 2871 * we use tagged status only for MSI case on BCM5717. Otherwise 2872 * MSI on BCM5717 does not work. 2873 */ 2874 if (BGE_IS_5717_PLUS(sc) && sc->bge_flags & BGE_MSI) 2875 sc->bge_flags |= BGE_TAGGED_STATUS; 2876 2877 DPRINTFN(5, ("pci_intr_string\n")); 2878 intrstr = pci_intr_string(pc, ih); 2879 2880 /* Try to reset the chip. */ 2881 DPRINTFN(5, ("bge_reset\n")); 2882 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 2883 bge_reset(sc); 2884 2885 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 2886 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 2887 2888 bge_chipinit(sc); 2889 2890 #ifdef __sparc64__ 2891 if (!gotenaddr) { 2892 if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address", 2893 sc->arpcom.ac_enaddr, ETHER_ADDR_LEN) == ETHER_ADDR_LEN) 2894 gotenaddr = 1; 2895 } 2896 #endif 2897 2898 /* 2899 * Get station address from the EEPROM. 2900 */ 2901 if (!gotenaddr) { 2902 mac_addr = bge_readmem_ind(sc, 0x0c14); 2903 if ((mac_addr >> 16) == 0x484b) { 2904 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 2905 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 2906 mac_addr = bge_readmem_ind(sc, 0x0c18); 2907 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 2908 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 2909 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 2910 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 2911 gotenaddr = 1; 2912 } 2913 } 2914 if (!gotenaddr) { 2915 int mac_offset = BGE_EE_MAC_OFFSET; 2916 2917 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 2918 mac_offset = BGE_EE_MAC_OFFSET_5906; 2919 2920 if (bge_read_nvram(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2921 mac_offset + 2, ETHER_ADDR_LEN) == 0) 2922 gotenaddr = 1; 2923 } 2924 if (!gotenaddr && (!(sc->bge_flags & BGE_NO_EEPROM))) { 2925 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2926 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN) == 0) 2927 gotenaddr = 1; 2928 } 2929 2930 #ifdef __sparc64__ 2931 if (!gotenaddr) { 2932 extern void myetheraddr(u_char *); 2933 2934 myetheraddr(sc->arpcom.ac_enaddr); 2935 gotenaddr = 1; 2936 } 2937 #endif 2938 2939 if (!gotenaddr) { 2940 printf(": failed to read station address\n"); 2941 goto fail_2; 2942 } 2943 2944 /* Allocate the general information block and ring buffers. */ 2945 sc->bge_dmatag = pa->pa_dmat; 2946 DPRINTFN(5, ("bus_dmamem_alloc\n")); 2947 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 2948 PAGE_SIZE, 0, &sc->bge_ring_seg, 1, &sc->bge_ring_nseg, 2949 BUS_DMA_NOWAIT)) { 2950 printf(": can't alloc rx buffers\n"); 2951 goto fail_2; 2952 } 2953 DPRINTFN(5, ("bus_dmamem_map\n")); 2954 if (bus_dmamem_map(sc->bge_dmatag, &sc->bge_ring_seg, 2955 sc->bge_ring_nseg, sizeof(struct bge_ring_data), &kva, 2956 BUS_DMA_NOWAIT)) { 2957 printf(": can't map dma buffers (%lu bytes)\n", 2958 sizeof(struct bge_ring_data)); 2959 goto fail_3; 2960 } 2961 DPRINTFN(5, ("bus_dmamem_create\n")); 2962 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 2963 sizeof(struct bge_ring_data), 0, 2964 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 2965 printf(": can't create dma map\n"); 2966 goto fail_4; 2967 } 2968 DPRINTFN(5, ("bus_dmamem_load\n")); 2969 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 2970 sizeof(struct bge_ring_data), NULL, 2971 BUS_DMA_NOWAIT)) { 2972 goto fail_5; 2973 } 2974 2975 DPRINTFN(5, ("bzero\n")); 2976 sc->bge_rdata = (struct bge_ring_data *)kva; 2977 2978 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 2979 2980 /* Set default tuneable values. */ 2981 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2982 sc->bge_rx_coal_ticks = 150; 2983 sc->bge_rx_max_coal_bds = 64; 2984 sc->bge_tx_coal_ticks = 300; 2985 sc->bge_tx_max_coal_bds = 400; 2986 2987 /* 5705 limits RX return ring to 512 entries. */ 2988 if (BGE_IS_5700_FAMILY(sc) || BGE_IS_5717_PLUS(sc)) 2989 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2990 else 2991 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2992 2993 /* Set up ifnet structure */ 2994 ifp = &sc->arpcom.ac_if; 2995 ifp->if_softc = sc; 2996 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2997 ifp->if_xflags = IFXF_MPSAFE; 2998 ifp->if_ioctl = bge_ioctl; 2999 ifp->if_qstart = bge_start; 3000 ifp->if_watchdog = bge_watchdog; 3001 IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1); 3002 3003 DPRINTFN(5, ("bcopy\n")); 3004 bcopy(sc->bge_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 3005 3006 ifp->if_capabilities = IFCAP_VLAN_MTU; 3007 3008 #if NVLAN > 0 3009 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 3010 #endif 3011 3012 /* 3013 * 5700 B0 chips do not support checksumming correctly due 3014 * to hardware bugs. 3015 * 3016 * It seems all controllers have a bug that can generate UDP 3017 * datagrams with a checksum value 0 when TX UDP checksum 3018 * offloading is enabled. Generating UDP checksum value 0 is 3019 * a violation of RFC 768. 3020 */ 3021 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) 3022 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4; 3023 3024 if (BGE_IS_JUMBO_CAPABLE(sc)) 3025 ifp->if_hardmtu = BGE_JUMBO_MTU; 3026 3027 /* 3028 * Do MII setup. 3029 */ 3030 DPRINTFN(5, ("mii setup\n")); 3031 sc->bge_mii.mii_ifp = ifp; 3032 sc->bge_mii.mii_readreg = bge_miibus_readreg; 3033 sc->bge_mii.mii_writereg = bge_miibus_writereg; 3034 sc->bge_mii.mii_statchg = bge_miibus_statchg; 3035 3036 /* 3037 * Figure out what sort of media we have by checking the hardware 3038 * config word in the first 32K of internal NIC memory, or fall back to 3039 * examining the EEPROM if necessary. Note: on some BCM5700 cards, 3040 * this value seems to be unset. If that's the case, we have to rely on 3041 * identifying the NIC by its PCI subsystem ID, as we do below for the 3042 * SysKonnect SK-9D41. 3043 */ 3044 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 3045 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 3046 else if (!(sc->bge_flags & BGE_NO_EEPROM)) { 3047 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3048 sizeof(hwcfg))) { 3049 printf(": failed to read media type\n"); 3050 goto fail_6; 3051 } 3052 hwcfg = ntohl(hwcfg); 3053 } 3054 3055 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3056 if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41 || 3057 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3058 if (BGE_IS_5700_FAMILY(sc)) 3059 sc->bge_flags |= BGE_FIBER_TBI; 3060 else 3061 sc->bge_flags |= BGE_FIBER_MII; 3062 } 3063 3064 /* Take advantage of single-shot MSI. */ 3065 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_MSI) 3066 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3067 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3068 3069 /* Hookup IRQ last. */ 3070 DPRINTFN(5, ("pci_intr_establish\n")); 3071 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, 3072 bge_intr, sc, sc->bge_dev.dv_xname); 3073 if (sc->bge_intrhand == NULL) { 3074 printf(": couldn't establish interrupt"); 3075 if (intrstr != NULL) 3076 printf(" at %s", intrstr); 3077 printf("\n"); 3078 goto fail_6; 3079 } 3080 3081 /* 3082 * A Broadcom chip was detected. Inform the world. 3083 */ 3084 printf(": %s, address %s\n", intrstr, 3085 ether_sprintf(sc->arpcom.ac_enaddr)); 3086 3087 if (sc->bge_flags & BGE_FIBER_TBI) { 3088 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3089 bge_ifmedia_sts); 3090 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 3091 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX, 3092 0, NULL); 3093 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 3094 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 3095 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3096 } else { 3097 int mii_flags; 3098 3099 /* 3100 * Do transceiver setup. 3101 */ 3102 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 3103 bge_ifmedia_sts); 3104 mii_flags = MIIF_DOPAUSE; 3105 if (sc->bge_flags & BGE_FIBER_MII) 3106 mii_flags |= MIIF_HAVEFIBER; 3107 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 3108 sc->bge_phy_addr, MII_OFFSET_ANY, mii_flags); 3109 3110 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 3111 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 3112 ifmedia_add(&sc->bge_mii.mii_media, 3113 IFM_ETHER|IFM_MANUAL, 0, NULL); 3114 ifmedia_set(&sc->bge_mii.mii_media, 3115 IFM_ETHER|IFM_MANUAL); 3116 } else 3117 ifmedia_set(&sc->bge_mii.mii_media, 3118 IFM_ETHER|IFM_AUTO); 3119 } 3120 3121 /* 3122 * Call MI attach routine. 3123 */ 3124 if_attach(ifp); 3125 ether_ifattach(ifp); 3126 3127 timeout_set(&sc->bge_timeout, bge_tick, sc); 3128 timeout_set(&sc->bge_rxtimeout, bge_rxtick, sc); 3129 timeout_set(&sc->bge_rxtimeout_jumbo, bge_rxtick_jumbo, sc); 3130 return; 3131 3132 fail_6: 3133 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3134 3135 fail_5: 3136 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3137 3138 fail_4: 3139 bus_dmamem_unmap(sc->bge_dmatag, (caddr_t)sc->bge_rdata, 3140 sizeof(struct bge_ring_data)); 3141 3142 fail_3: 3143 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_nseg); 3144 3145 fail_2: 3146 if ((sc->bge_flags & BGE_APE) != 0) 3147 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3148 sc->bge_apesize); 3149 3150 fail_1: 3151 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3152 } 3153 3154 int 3155 bge_detach(struct device *self, int flags) 3156 { 3157 struct bge_softc *sc = (struct bge_softc *)self; 3158 struct ifnet *ifp = &sc->arpcom.ac_if; 3159 3160 if (sc->bge_intrhand) 3161 pci_intr_disestablish(sc->bge_pa.pa_pc, sc->bge_intrhand); 3162 3163 bge_stop(sc, 1); 3164 3165 /* Detach any PHYs we might have. */ 3166 if (LIST_FIRST(&sc->bge_mii.mii_phys) != NULL) 3167 mii_detach(&sc->bge_mii, MII_PHY_ANY, MII_OFFSET_ANY); 3168 3169 /* Delete any remaining media. */ 3170 ifmedia_delete_instance(&sc->bge_mii.mii_media, IFM_INST_ANY); 3171 3172 ether_ifdetach(ifp); 3173 if_detach(ifp); 3174 3175 bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map); 3176 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 3177 bus_dmamem_unmap(sc->bge_dmatag, (caddr_t)sc->bge_rdata, 3178 sizeof(struct bge_ring_data)); 3179 bus_dmamem_free(sc->bge_dmatag, &sc->bge_ring_seg, sc->bge_ring_nseg); 3180 3181 if ((sc->bge_flags & BGE_APE) != 0) 3182 bus_space_unmap(sc->bge_apetag, sc->bge_apehandle, 3183 sc->bge_apesize); 3184 3185 bus_space_unmap(sc->bge_btag, sc->bge_bhandle, sc->bge_bsize); 3186 return (0); 3187 } 3188 3189 int 3190 bge_activate(struct device *self, int act) 3191 { 3192 struct bge_softc *sc = (struct bge_softc *)self; 3193 struct ifnet *ifp = &sc->arpcom.ac_if; 3194 int rv = 0; 3195 3196 switch (act) { 3197 case DVACT_SUSPEND: 3198 rv = config_activate_children(self, act); 3199 if (ifp->if_flags & IFF_RUNNING) 3200 bge_stop(sc, 0); 3201 break; 3202 case DVACT_RESUME: 3203 if (ifp->if_flags & IFF_UP) 3204 bge_init(sc); 3205 break; 3206 default: 3207 rv = config_activate_children(self, act); 3208 break; 3209 } 3210 return (rv); 3211 } 3212 3213 void 3214 bge_reset(struct bge_softc *sc) 3215 { 3216 struct pci_attach_args *pa = &sc->bge_pa; 3217 pcireg_t cachesize, command, devctl; 3218 u_int32_t reset, mac_mode, mac_mode_mask, val; 3219 void (*write_op)(struct bge_softc *, int, int); 3220 int i; 3221 3222 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3223 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3224 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3225 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3226 3227 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3228 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906) { 3229 if (sc->bge_flags & BGE_PCIE) 3230 write_op = bge_writembx; 3231 else 3232 write_op = bge_writemem_ind; 3233 } else 3234 write_op = bge_writereg_ind; 3235 3236 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5700 && 3237 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5701) { 3238 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 3239 for (i = 0; i < 8000; i++) { 3240 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 3241 BGE_NVRAMSWARB_GNT1) 3242 break; 3243 DELAY(20); 3244 } 3245 if (i == 8000) 3246 printf("%s: nvram lock timed out\n", 3247 sc->bge_dev.dv_xname); 3248 } 3249 /* Take APE lock when performing reset. */ 3250 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3251 3252 /* Save some important PCI state. */ 3253 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 3254 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 3255 3256 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 3257 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3258 BGE_PCIMISCCTL_ENDIAN_WORDSWAP | BGE_PCIMISCCTL_PCISTATE_RW); 3259 3260 /* Disable fastboot on controllers that support it. */ 3261 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 || 3262 BGE_IS_5755_PLUS(sc)) 3263 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0); 3264 3265 /* 3266 * Write the magic number to SRAM at offset 0xB50. 3267 * When firmware finishes its initialization it will 3268 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 3269 */ 3270 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3271 3272 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3273 3274 if (sc->bge_flags & BGE_PCIE) { 3275 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785 && 3276 !BGE_IS_5717_PLUS(sc)) { 3277 if (CSR_READ_4(sc, 0x7e2c) == 0x60) { 3278 /* PCI Express 1.0 system */ 3279 CSR_WRITE_4(sc, 0x7e2c, 0x20); 3280 } 3281 } 3282 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3283 /* 3284 * Prevent PCI Express link training 3285 * during global reset. 3286 */ 3287 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); 3288 reset |= (1<<29); 3289 } 3290 } 3291 3292 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3293 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3294 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3295 val | BGE_VCPU_STATUS_DRV_RESET); 3296 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3297 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3298 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3299 3300 sc->bge_flags |= BGE_NO_EEPROM; 3301 } 3302 3303 /* 3304 * Set GPHY Power Down Override to leave GPHY 3305 * powered up in D0 uninitialized. 3306 */ 3307 if (BGE_IS_5705_PLUS(sc) && 3308 (sc->bge_flags & BGE_CPMU_PRESENT) == 0) 3309 reset |= BGE_MISCCFG_KEEP_GPHY_POWER; 3310 3311 /* Issue global reset */ 3312 write_op(sc, BGE_MISC_CFG, reset); 3313 3314 if (sc->bge_flags & BGE_PCIE) 3315 DELAY(100 * 1000); 3316 else 3317 DELAY(1000); 3318 3319 if (sc->bge_flags & BGE_PCIE) { 3320 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3321 pcireg_t v; 3322 3323 DELAY(500000); /* wait for link training to complete */ 3324 v = pci_conf_read(pa->pa_pc, pa->pa_tag, 0xc4); 3325 pci_conf_write(pa->pa_pc, pa->pa_tag, 0xc4, v | (1<<15)); 3326 } 3327 3328 devctl = pci_conf_read(pa->pa_pc, pa->pa_tag, sc->bge_expcap + 3329 PCI_PCIE_DCSR); 3330 /* Clear enable no snoop and disable relaxed ordering. */ 3331 devctl &= ~(PCI_PCIE_DCSR_ERO | PCI_PCIE_DCSR_ENS); 3332 /* Set PCI Express max payload size. */ 3333 devctl = (devctl & ~PCI_PCIE_DCSR_MPS) | sc->bge_expmrq; 3334 /* Clear error status. */ 3335 devctl |= PCI_PCIE_DCSR_CEE | PCI_PCIE_DCSR_NFE | 3336 PCI_PCIE_DCSR_FEE | PCI_PCIE_DCSR_URE; 3337 pci_conf_write(pa->pa_pc, pa->pa_tag, sc->bge_expcap + 3338 PCI_PCIE_DCSR, devctl); 3339 } 3340 3341 /* Reset some of the PCI state that got zapped by reset */ 3342 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 3343 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3344 BGE_PCIMISCCTL_ENDIAN_WORDSWAP | BGE_PCIMISCCTL_PCISTATE_RW); 3345 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 3346 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 3347 (sc->bge_flags & BGE_PCIX) != 0) 3348 val |= BGE_PCISTATE_RETRY_SAME_DMA; 3349 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3350 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3351 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3352 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3353 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE, val); 3354 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 3355 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 3356 3357 /* Re-enable MSI, if necessary, and enable memory arbiter. */ 3358 if (BGE_IS_5714_FAMILY(sc)) { 3359 /* This chip disables MSI on reset. */ 3360 if (sc->bge_flags & BGE_MSI) { 3361 val = pci_conf_read(pa->pa_pc, pa->pa_tag, 3362 sc->bge_msicap + PCI_MSI_MC); 3363 pci_conf_write(pa->pa_pc, pa->pa_tag, 3364 sc->bge_msicap + PCI_MSI_MC, 3365 val | PCI_MSI_MC_MSIE); 3366 val = CSR_READ_4(sc, BGE_MSI_MODE); 3367 CSR_WRITE_4(sc, BGE_MSI_MODE, 3368 val | BGE_MSIMODE_ENABLE); 3369 } 3370 val = CSR_READ_4(sc, BGE_MARB_MODE); 3371 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3372 } else 3373 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3374 3375 /* Fix up byte swapping */ 3376 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 3377 3378 val = CSR_READ_4(sc, BGE_MAC_MODE); 3379 val = (val & ~mac_mode_mask) | mac_mode; 3380 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 3381 DELAY(40); 3382 3383 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 3384 3385 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) { 3386 for (i = 0; i < BGE_TIMEOUT; i++) { 3387 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3388 if (val & BGE_VCPU_STATUS_INIT_DONE) 3389 break; 3390 DELAY(100); 3391 } 3392 3393 if (i >= BGE_TIMEOUT) 3394 printf("%s: reset timed out\n", sc->bge_dev.dv_xname); 3395 } else { 3396 /* 3397 * Poll until we see 1's complement of the magic number. 3398 * This indicates that the firmware initialization 3399 * is complete. We expect this to fail if no SEEPROM 3400 * is fitted. 3401 */ 3402 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 3403 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3404 if (val == ~BGE_MAGIC_NUMBER) 3405 break; 3406 DELAY(10); 3407 } 3408 3409 if ((i >= BGE_TIMEOUT * 10) && 3410 (!(sc->bge_flags & BGE_NO_EEPROM))) 3411 printf("%s: firmware handshake timed out\n", 3412 sc->bge_dev.dv_xname); 3413 /* BCM57765 A0 needs additional time before accessing. */ 3414 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 3415 DELAY(10 * 1000); /* XXX */ 3416 } 3417 3418 /* 3419 * The 5704 in TBI mode apparently needs some special 3420 * adjustment to ensure the SERDES drive level is set 3421 * to 1.2V. 3422 */ 3423 if (sc->bge_flags & BGE_FIBER_TBI && 3424 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 3425 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3426 val = (val & ~0xFFF) | 0x880; 3427 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3428 } 3429 3430 if (sc->bge_flags & BGE_PCIE && 3431 !BGE_IS_5717_PLUS(sc) && 3432 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3433 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5785) { 3434 /* Enable Data FIFO protection. */ 3435 val = CSR_READ_4(sc, 0x7c00); 3436 CSR_WRITE_4(sc, 0x7c00, val | (1<<25)); 3437 } 3438 3439 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720) 3440 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 3441 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 3442 } 3443 3444 /* 3445 * Frame reception handling. This is called if there's a frame 3446 * on the receive return list. 3447 * 3448 * Note: we have to be able to handle two possibilities here: 3449 * 1) the frame is from the jumbo receive ring 3450 * 2) the frame is from the standard receive ring 3451 */ 3452 3453 void 3454 bge_rxeof(struct bge_softc *sc) 3455 { 3456 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 3457 struct ifnet *ifp; 3458 uint16_t rx_prod, rx_cons; 3459 int stdcnt = 0, jumbocnt = 0; 3460 bus_dmamap_t dmamap; 3461 bus_addr_t offset, toff; 3462 bus_size_t tlen; 3463 int tosync; 3464 3465 rx_cons = sc->bge_rx_saved_considx; 3466 rx_prod = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx; 3467 3468 /* Nothing to do */ 3469 if (rx_cons == rx_prod) 3470 return; 3471 3472 ifp = &sc->arpcom.ac_if; 3473 3474 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3475 offsetof(struct bge_ring_data, bge_status_block), 3476 sizeof (struct bge_status_block), 3477 BUS_DMASYNC_POSTREAD); 3478 3479 offset = offsetof(struct bge_ring_data, bge_rx_return_ring); 3480 tosync = rx_prod - rx_cons; 3481 3482 toff = offset + (rx_cons * sizeof (struct bge_rx_bd)); 3483 3484 if (tosync < 0) { 3485 tlen = (sc->bge_return_ring_cnt - rx_cons) * 3486 sizeof (struct bge_rx_bd); 3487 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3488 toff, tlen, BUS_DMASYNC_POSTREAD); 3489 tosync = -tosync; 3490 } 3491 3492 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3493 offset, tosync * sizeof (struct bge_rx_bd), 3494 BUS_DMASYNC_POSTREAD); 3495 3496 while (rx_cons != rx_prod) { 3497 struct bge_rx_bd *cur_rx; 3498 u_int32_t rxidx; 3499 struct mbuf *m = NULL; 3500 3501 cur_rx = &sc->bge_rdata->bge_rx_return_ring[rx_cons]; 3502 3503 rxidx = cur_rx->bge_idx; 3504 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3505 3506 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3507 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3508 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 3509 3510 jumbocnt++; 3511 3512 dmamap = sc->bge_cdata.bge_rx_jumbo_map[rxidx]; 3513 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3514 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3515 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3516 3517 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3518 m_freem(m); 3519 continue; 3520 } 3521 } else { 3522 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3523 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 3524 3525 stdcnt++; 3526 3527 dmamap = sc->bge_cdata.bge_rx_std_map[rxidx]; 3528 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3529 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3530 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3531 3532 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3533 m_freem(m); 3534 continue; 3535 } 3536 } 3537 3538 #ifdef __STRICT_ALIGNMENT 3539 /* 3540 * The i386 allows unaligned accesses, but for other 3541 * platforms we must make sure the payload is aligned. 3542 */ 3543 if (sc->bge_flags & BGE_RX_ALIGNBUG) { 3544 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3545 cur_rx->bge_len); 3546 m->m_data += ETHER_ALIGN; 3547 } 3548 #endif 3549 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3550 3551 bge_rxcsum(sc, cur_rx, m); 3552 3553 #if NVLAN > 0 3554 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING && 3555 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3556 m->m_pkthdr.ether_vtag = cur_rx->bge_vlan_tag; 3557 m->m_flags |= M_VLANTAG; 3558 } 3559 #endif 3560 3561 ml_enqueue(&ml, m); 3562 } 3563 3564 sc->bge_rx_saved_considx = rx_cons; 3565 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3566 if (stdcnt) { 3567 if_rxr_put(&sc->bge_std_ring, stdcnt); 3568 bge_fill_rx_ring_std(sc); 3569 } 3570 if (jumbocnt) { 3571 if_rxr_put(&sc->bge_jumbo_ring, jumbocnt); 3572 bge_fill_rx_ring_jumbo(sc); 3573 } 3574 3575 if_input(ifp, &ml); 3576 } 3577 3578 void 3579 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 3580 { 3581 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3582 /* 3583 * 5700 B0 chips do not support checksumming correctly due 3584 * to hardware bugs. 3585 */ 3586 return; 3587 } else if (BGE_IS_5717_PLUS(sc)) { 3588 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 3589 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM && 3590 (cur_rx->bge_error_flag & 3591 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 3592 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 3593 3594 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 3595 m->m_pkthdr.csum_flags |= 3596 M_TCP_CSUM_IN_OK|M_UDP_CSUM_IN_OK; 3597 } 3598 } 3599 } else { 3600 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM && 3601 cur_rx->bge_ip_csum == 0xFFFF) 3602 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 3603 3604 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3605 m->m_pkthdr.len >= ETHER_MIN_NOPAD && 3606 cur_rx->bge_tcp_udp_csum == 0xFFFF) { 3607 m->m_pkthdr.csum_flags |= 3608 M_TCP_CSUM_IN_OK|M_UDP_CSUM_IN_OK; 3609 } 3610 } 3611 } 3612 3613 void 3614 bge_txeof(struct bge_softc *sc) 3615 { 3616 struct bge_tx_bd *cur_tx = NULL; 3617 struct ifnet *ifp; 3618 bus_dmamap_t dmamap; 3619 bus_addr_t offset, toff; 3620 bus_size_t tlen; 3621 int tosync, freed, txcnt; 3622 u_int32_t cons, newcons; 3623 struct mbuf *m; 3624 3625 /* Nothing to do */ 3626 cons = sc->bge_tx_saved_considx; 3627 newcons = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx; 3628 if (cons == newcons) 3629 return; 3630 3631 ifp = &sc->arpcom.ac_if; 3632 3633 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3634 offsetof(struct bge_ring_data, bge_status_block), 3635 sizeof (struct bge_status_block), 3636 BUS_DMASYNC_POSTREAD); 3637 3638 offset = offsetof(struct bge_ring_data, bge_tx_ring); 3639 tosync = newcons - cons; 3640 3641 toff = offset + (cons * sizeof (struct bge_tx_bd)); 3642 3643 if (tosync < 0) { 3644 tlen = (BGE_TX_RING_CNT - cons) * sizeof (struct bge_tx_bd); 3645 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3646 toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3647 tosync = -tosync; 3648 } 3649 3650 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3651 offset, tosync * sizeof (struct bge_tx_bd), 3652 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3653 3654 /* 3655 * Go through our tx ring and free mbufs for those 3656 * frames that have been sent. 3657 */ 3658 freed = 0; 3659 while (cons != newcons) { 3660 cur_tx = &sc->bge_rdata->bge_tx_ring[cons]; 3661 m = sc->bge_cdata.bge_tx_chain[cons]; 3662 if (m != NULL) { 3663 dmamap = sc->bge_cdata.bge_tx_map[cons]; 3664 3665 sc->bge_cdata.bge_tx_chain[cons] = NULL; 3666 sc->bge_cdata.bge_tx_map[cons] = NULL; 3667 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, 3668 dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 3669 bus_dmamap_unload(sc->bge_dmatag, dmamap); 3670 3671 m_freem(m); 3672 } 3673 freed++; 3674 BGE_INC(cons, BGE_TX_RING_CNT); 3675 } 3676 3677 txcnt = atomic_sub_int_nv(&sc->bge_txcnt, freed); 3678 3679 sc->bge_tx_saved_considx = cons; 3680 3681 if (ifq_is_oactive(&ifp->if_snd)) 3682 ifq_restart(&ifp->if_snd); 3683 else if (txcnt == 0) 3684 ifp->if_timer = 0; 3685 } 3686 3687 int 3688 bge_intr(void *xsc) 3689 { 3690 struct bge_softc *sc; 3691 struct ifnet *ifp; 3692 u_int32_t statusword, statustag; 3693 3694 sc = xsc; 3695 ifp = &sc->arpcom.ac_if; 3696 3697 /* read status word from status block */ 3698 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3699 offsetof(struct bge_ring_data, bge_status_block), 3700 sizeof (struct bge_status_block), 3701 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3702 3703 statusword = sc->bge_rdata->bge_status_block.bge_status; 3704 statustag = sc->bge_rdata->bge_status_block.bge_status_tag << 24; 3705 3706 if (sc->bge_flags & BGE_TAGGED_STATUS) { 3707 if (sc->bge_lasttag == statustag && 3708 (CSR_READ_4(sc, BGE_PCI_PCISTATE) & 3709 BGE_PCISTATE_INTR_NOT_ACTIVE)) 3710 return (0); 3711 sc->bge_lasttag = statustag; 3712 } else { 3713 if (!(statusword & BGE_STATFLAG_UPDATED) && 3714 (CSR_READ_4(sc, BGE_PCI_PCISTATE) & 3715 BGE_PCISTATE_INTR_NOT_ACTIVE)) 3716 return (0); 3717 /* Ack interrupt and stop others from occurring. */ 3718 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 3719 statustag = 0; 3720 } 3721 3722 /* clear status word */ 3723 sc->bge_rdata->bge_status_block.bge_status = 0; 3724 3725 bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map, 3726 offsetof(struct bge_ring_data, bge_status_block), 3727 sizeof (struct bge_status_block), 3728 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3729 3730 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 3731 statusword & BGE_STATFLAG_LINKSTATE_CHANGED || 3732 BGE_STS_BIT(sc, BGE_STS_LINK_EVT)) { 3733 KERNEL_LOCK(); 3734 bge_link_upd(sc); 3735 KERNEL_UNLOCK(); 3736 } 3737 3738 /* Re-enable interrupts. */ 3739 bge_writembx(sc, BGE_MBX_IRQ0_LO, statustag); 3740 3741 if (ifp->if_flags & IFF_RUNNING) { 3742 /* Check RX return ring producer/consumer */ 3743 bge_rxeof(sc); 3744 3745 /* Check TX ring producer/consumer */ 3746 bge_txeof(sc); 3747 } 3748 3749 return (1); 3750 } 3751 3752 void 3753 bge_tick(void *xsc) 3754 { 3755 struct bge_softc *sc = xsc; 3756 struct mii_data *mii = &sc->bge_mii; 3757 int s; 3758 3759 s = splnet(); 3760 3761 if (BGE_IS_5705_PLUS(sc)) 3762 bge_stats_update_regs(sc); 3763 else 3764 bge_stats_update(sc); 3765 3766 if (sc->bge_flags & BGE_FIBER_TBI) { 3767 /* 3768 * Since in TBI mode auto-polling can't be used we should poll 3769 * link status manually. Here we register pending link event 3770 * and trigger interrupt. 3771 */ 3772 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 3773 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3774 } else { 3775 /* 3776 * Do not touch PHY if we have link up. This could break 3777 * IPMI/ASF mode or produce extra input errors. 3778 * (extra input errors was reported for bcm5701 & bcm5704). 3779 */ 3780 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) 3781 mii_tick(mii); 3782 } 3783 3784 timeout_add_sec(&sc->bge_timeout, 1); 3785 3786 splx(s); 3787 } 3788 3789 void 3790 bge_stats_update_regs(struct bge_softc *sc) 3791 { 3792 struct ifnet *ifp = &sc->arpcom.ac_if; 3793 3794 sc->bge_tx_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3795 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3796 3797 sc->bge_rx_overruns += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3798 3799 /* 3800 * XXX 3801 * Unlike other controllers, the BGE_RXLP_LOCSTAT_IFIN_DROPS counter 3802 * of the BCM5717, BCM5718, BCM5762, BCM5719 A0 and BCM5720 A0 3803 * controllers includes the number of unwanted multicast frames. 3804 * This comes from a silicon bug and known workaround to get rough 3805 * (not exact) counter is to enable interrupt on MBUF low watermark 3806 * attention. This can be accomplished by setting BGE_HCCMODE_ATTN 3807 * bit of BGE_HDD_MODE, BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE 3808 * and BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. However 3809 * that change would generate more interrupts and there are still 3810 * possibilities of losing multiple frames during 3811 * BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. Given that 3812 * the workaround still would not get correct counter I don't think 3813 * it's worth to implement it. So ignore reading the counter on 3814 * controllers that have the silicon bug. 3815 */ 3816 if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5717 && 3817 BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5762 && 3818 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 3819 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 3820 sc->bge_rx_discards += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3821 3822 sc->bge_rx_inerrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3823 3824 ifp->if_collisions = sc->bge_tx_collisions; 3825 ifp->if_ierrors = sc->bge_rx_discards + sc->bge_rx_inerrors; 3826 3827 if (sc->bge_flags & BGE_RDMA_BUG) { 3828 u_int32_t val, ucast, mcast, bcast; 3829 3830 ucast = CSR_READ_4(sc, BGE_MAC_STATS + 3831 offsetof(struct bge_mac_stats_regs, ifHCOutUcastPkts)); 3832 mcast = CSR_READ_4(sc, BGE_MAC_STATS + 3833 offsetof(struct bge_mac_stats_regs, ifHCOutMulticastPkts)); 3834 bcast = CSR_READ_4(sc, BGE_MAC_STATS + 3835 offsetof(struct bge_mac_stats_regs, ifHCOutBroadcastPkts)); 3836 3837 /* 3838 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 3839 * frames, it's safe to disable workaround for DMA engine's 3840 * miscalculation of TXMBUF space. 3841 */ 3842 if (ucast + mcast + bcast > BGE_NUM_RDMA_CHANNELS) { 3843 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 3844 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5719) 3845 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 3846 else 3847 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 3848 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 3849 sc->bge_flags &= ~BGE_RDMA_BUG; 3850 } 3851 } 3852 } 3853 3854 void 3855 bge_stats_update(struct bge_softc *sc) 3856 { 3857 struct ifnet *ifp = &sc->arpcom.ac_if; 3858 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3859 u_int32_t cnt; 3860 3861 #define READ_STAT(sc, stats, stat) \ 3862 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3863 3864 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3865 ifp->if_collisions += (u_int32_t)(cnt - sc->bge_tx_collisions); 3866 sc->bge_tx_collisions = cnt; 3867 3868 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 3869 sc->bge_rx_overruns = cnt; 3870 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 3871 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrors); 3872 sc->bge_rx_inerrors = cnt; 3873 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3874 ifp->if_ierrors += (u_int32_t)(cnt - sc->bge_rx_discards); 3875 sc->bge_rx_discards = cnt; 3876 3877 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3878 ifp->if_oerrors += (u_int32_t)(cnt - sc->bge_tx_discards); 3879 sc->bge_tx_discards = cnt; 3880 3881 #undef READ_STAT 3882 } 3883 3884 /* 3885 * Compact outbound packets to avoid bug with DMA segments less than 8 bytes. 3886 */ 3887 int 3888 bge_compact_dma_runt(struct mbuf *pkt) 3889 { 3890 struct mbuf *m, *prev, *n = NULL; 3891 int totlen, newprevlen; 3892 3893 prev = NULL; 3894 totlen = 0; 3895 3896 for (m = pkt; m != NULL; prev = m,m = m->m_next) { 3897 int mlen = m->m_len; 3898 int shortfall = 8 - mlen ; 3899 3900 totlen += mlen; 3901 if (mlen == 0) 3902 continue; 3903 if (mlen >= 8) 3904 continue; 3905 3906 /* If we get here, mbuf data is too small for DMA engine. 3907 * Try to fix by shuffling data to prev or next in chain. 3908 * If that fails, do a compacting deep-copy of the whole chain. 3909 */ 3910 3911 /* Internal frag. If fits in prev, copy it there. */ 3912 if (prev && m_trailingspace(prev) >= m->m_len) { 3913 bcopy(m->m_data, prev->m_data+prev->m_len, mlen); 3914 prev->m_len += mlen; 3915 m->m_len = 0; 3916 /* XXX stitch chain */ 3917 prev->m_next = m_free(m); 3918 m = prev; 3919 continue; 3920 } else if (m->m_next != NULL && 3921 m_trailingspace(m) >= shortfall && 3922 m->m_next->m_len >= (8 + shortfall)) { 3923 /* m is writable and have enough data in next, pull up. */ 3924 3925 bcopy(m->m_next->m_data, m->m_data+m->m_len, shortfall); 3926 m->m_len += shortfall; 3927 m->m_next->m_len -= shortfall; 3928 m->m_next->m_data += shortfall; 3929 } else if (m->m_next == NULL || 1) { 3930 /* Got a runt at the very end of the packet. 3931 * borrow data from the tail of the preceding mbuf and 3932 * update its length in-place. (The original data is still 3933 * valid, so we can do this even if prev is not writable.) 3934 */ 3935 3936 /* if we'd make prev a runt, just move all of its data. */ 3937 #ifdef DEBUG 3938 KASSERT(prev != NULL /*, ("runt but null PREV")*/); 3939 KASSERT(prev->m_len >= 8 /*, ("runt prev")*/); 3940 #endif 3941 if ((prev->m_len - shortfall) < 8) 3942 shortfall = prev->m_len; 3943 3944 newprevlen = prev->m_len - shortfall; 3945 3946 MGET(n, M_NOWAIT, MT_DATA); 3947 if (n == NULL) 3948 return (ENOBUFS); 3949 KASSERT(m->m_len + shortfall < MLEN 3950 /*, 3951 ("runt %d +prev %d too big\n", m->m_len, shortfall)*/); 3952 3953 /* first copy the data we're stealing from prev */ 3954 bcopy(prev->m_data + newprevlen, n->m_data, shortfall); 3955 3956 /* update prev->m_len accordingly */ 3957 prev->m_len -= shortfall; 3958 3959 /* copy data from runt m */ 3960 bcopy(m->m_data, n->m_data + shortfall, m->m_len); 3961 3962 /* n holds what we stole from prev, plus m */ 3963 n->m_len = shortfall + m->m_len; 3964 3965 /* stitch n into chain and free m */ 3966 n->m_next = m->m_next; 3967 prev->m_next = n; 3968 /* KASSERT(m->m_next == NULL); */ 3969 m->m_next = NULL; 3970 m_free(m); 3971 m = n; /* for continuing loop */ 3972 } 3973 } 3974 return (0); 3975 } 3976 3977 /* 3978 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3979 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3980 * but when such padded frames employ the bge IP/TCP checksum offload, 3981 * the hardware checksum assist gives incorrect results (possibly 3982 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3983 * If we pad such runts with zeros, the onboard checksum comes out correct. 3984 */ 3985 int 3986 bge_cksum_pad(struct mbuf *m) 3987 { 3988 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3989 struct mbuf *last; 3990 3991 /* If there's only the packet-header and we can pad there, use it. */ 3992 if (m->m_pkthdr.len == m->m_len && m_trailingspace(m) >= padlen) { 3993 last = m; 3994 } else { 3995 /* 3996 * Walk packet chain to find last mbuf. We will either 3997 * pad there, or append a new mbuf and pad it. 3998 */ 3999 for (last = m; last->m_next != NULL; last = last->m_next); 4000 if (m_trailingspace(last) < padlen) { 4001 /* Allocate new empty mbuf, pad it. Compact later. */ 4002 struct mbuf *n; 4003 4004 MGET(n, M_DONTWAIT, MT_DATA); 4005 if (n == NULL) 4006 return (ENOBUFS); 4007 n->m_len = 0; 4008 last->m_next = n; 4009 last = n; 4010 } 4011 } 4012 4013 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 4014 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 4015 last->m_len += padlen; 4016 m->m_pkthdr.len += padlen; 4017 4018 return (0); 4019 } 4020 4021 /* 4022 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4023 * pointers to descriptors. 4024 */ 4025 int 4026 bge_encap(struct bge_softc *sc, struct mbuf *m, int *txinc) 4027 { 4028 struct bge_tx_bd *f = NULL; 4029 u_int32_t frag, cur; 4030 u_int16_t csum_flags = 0; 4031 bus_dmamap_t dmamap; 4032 int i = 0; 4033 4034 cur = frag = (sc->bge_tx_prodidx + *txinc) % BGE_TX_RING_CNT; 4035 4036 if (m->m_pkthdr.csum_flags) { 4037 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 4038 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4039 if (m->m_pkthdr.csum_flags & 4040 (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT)) { 4041 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4042 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 4043 bge_cksum_pad(m) != 0) 4044 return (ENOBUFS); 4045 } 4046 } 4047 4048 if (sc->bge_flags & BGE_JUMBO_FRAME && 4049 m->m_pkthdr.len > ETHER_MAX_LEN) 4050 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 4051 4052 if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)) 4053 goto doit; 4054 4055 /* 4056 * bcm5700 Revision B silicon cannot handle DMA descriptors with 4057 * less than eight bytes. If we encounter a teeny mbuf 4058 * at the end of a chain, we can pad. Otherwise, copy. 4059 */ 4060 if (bge_compact_dma_runt(m) != 0) 4061 return (ENOBUFS); 4062 4063 doit: 4064 dmamap = sc->bge_txdma[cur]; 4065 4066 /* 4067 * Start packing the mbufs in this chain into 4068 * the fragment pointers. Stop when we run out 4069 * of fragments or hit the end of the mbuf chain. 4070 */ 4071 switch (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m, 4072 BUS_DMA_NOWAIT)) { 4073 case 0: 4074 break; 4075 case EFBIG: 4076 if (m_defrag(m, M_DONTWAIT) == 0 && 4077 bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m, 4078 BUS_DMA_NOWAIT) == 0) 4079 break; 4080 4081 /* FALLTHROUGH */ 4082 default: 4083 return (ENOBUFS); 4084 } 4085 4086 for (i = 0; i < dmamap->dm_nsegs; i++) { 4087 f = &sc->bge_rdata->bge_tx_ring[frag]; 4088 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 4089 break; 4090 BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr); 4091 f->bge_len = dmamap->dm_segs[i].ds_len; 4092 f->bge_flags = csum_flags; 4093 f->bge_vlan_tag = 0; 4094 #if NVLAN > 0 4095 if (m->m_flags & M_VLANTAG) { 4096 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 4097 f->bge_vlan_tag = m->m_pkthdr.ether_vtag; 4098 } 4099 #endif 4100 cur = frag; 4101 BGE_INC(frag, BGE_TX_RING_CNT); 4102 } 4103 4104 if (i < dmamap->dm_nsegs) 4105 goto fail_unload; 4106 4107 if (frag == sc->bge_tx_saved_considx) 4108 goto fail_unload; 4109 4110 bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize, 4111 BUS_DMASYNC_PREWRITE); 4112 4113 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 4114 sc->bge_cdata.bge_tx_chain[cur] = m; 4115 sc->bge_cdata.bge_tx_map[cur] = dmamap; 4116 4117 *txinc += dmamap->dm_nsegs; 4118 4119 return (0); 4120 4121 fail_unload: 4122 bus_dmamap_unload(sc->bge_dmatag, dmamap); 4123 4124 return (ENOBUFS); 4125 } 4126 4127 /* 4128 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4129 * to the mbuf data regions directly in the transmit descriptors. 4130 */ 4131 void 4132 bge_start(struct ifqueue *ifq) 4133 { 4134 struct ifnet *ifp = ifq->ifq_if; 4135 struct bge_softc *sc = ifp->if_softc; 4136 struct mbuf *m; 4137 int txinc; 4138 4139 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4140 ifq_purge(ifq); 4141 return; 4142 } 4143 4144 txinc = 0; 4145 while (1) { 4146 /* Check if we have enough free send BDs. */ 4147 if (sc->bge_txcnt + txinc + BGE_NTXSEG + 16 >= 4148 BGE_TX_RING_CNT) { 4149 ifq_set_oactive(ifq); 4150 break; 4151 } 4152 4153 m = ifq_dequeue(ifq); 4154 if (m == NULL) 4155 break; 4156 4157 if (bge_encap(sc, m, &txinc) != 0) { 4158 m_freem(m); 4159 continue; 4160 } 4161 4162 #if NBPFILTER > 0 4163 if (ifp->if_bpf) 4164 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_OUT); 4165 #endif 4166 } 4167 4168 if (txinc != 0) { 4169 /* Transmit */ 4170 sc->bge_tx_prodidx = (sc->bge_tx_prodidx + txinc) % 4171 BGE_TX_RING_CNT; 4172 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 4173 if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX) 4174 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, 4175 sc->bge_tx_prodidx); 4176 4177 atomic_add_int(&sc->bge_txcnt, txinc); 4178 4179 /* 4180 * Set a timeout in case the chip goes out to lunch. 4181 */ 4182 ifp->if_timer = 5; 4183 } 4184 } 4185 4186 void 4187 bge_init(void *xsc) 4188 { 4189 struct bge_softc *sc = xsc; 4190 struct ifnet *ifp; 4191 u_int16_t *m; 4192 u_int32_t mode; 4193 int s; 4194 4195 s = splnet(); 4196 4197 ifp = &sc->arpcom.ac_if; 4198 4199 /* Cancel pending I/O and flush buffers. */ 4200 bge_stop(sc, 0); 4201 bge_sig_pre_reset(sc, BGE_RESET_START); 4202 bge_reset(sc); 4203 bge_sig_legacy(sc, BGE_RESET_START); 4204 bge_sig_post_reset(sc, BGE_RESET_START); 4205 4206 bge_chipinit(sc); 4207 4208 /* 4209 * Init the various state machines, ring 4210 * control blocks and firmware. 4211 */ 4212 if (bge_blockinit(sc)) { 4213 printf("%s: initialization failure\n", sc->bge_dev.dv_xname); 4214 splx(s); 4215 return; 4216 } 4217 4218 /* Specify MRU. */ 4219 if (BGE_IS_JUMBO_CAPABLE(sc)) 4220 CSR_WRITE_4(sc, BGE_RX_MTU, 4221 BGE_JUMBO_FRAMELEN + ETHER_VLAN_ENCAP_LEN); 4222 else 4223 CSR_WRITE_4(sc, BGE_RX_MTU, 4224 ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 4225 4226 /* Load our MAC address. */ 4227 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 4228 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4229 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4230 4231 if (!(ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) { 4232 /* Disable hardware decapsulation of VLAN frames. */ 4233 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 4234 } 4235 4236 /* Program promiscuous mode and multicast filters. */ 4237 bge_iff(sc); 4238 4239 /* Init RX ring. */ 4240 bge_init_rx_ring_std(sc); 4241 4242 /* 4243 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4244 * memory to ensure that the chip has in fact read the first 4245 * entry of the ring. 4246 */ 4247 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4248 u_int32_t v, i; 4249 for (i = 0; i < 10; i++) { 4250 DELAY(20); 4251 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4252 if (v == (MCLBYTES - ETHER_ALIGN)) 4253 break; 4254 } 4255 if (i == 10) 4256 printf("%s: 5705 A0 chip failed to load RX ring\n", 4257 sc->bge_dev.dv_xname); 4258 } 4259 4260 /* Init Jumbo RX ring. */ 4261 if (sc->bge_flags & BGE_JUMBO_RING) 4262 bge_init_rx_ring_jumbo(sc); 4263 4264 /* Init our RX return ring index */ 4265 sc->bge_rx_saved_considx = 0; 4266 4267 /* Init our RX/TX stat counters. */ 4268 sc->bge_tx_collisions = 0; 4269 sc->bge_rx_discards = 0; 4270 sc->bge_rx_inerrors = 0; 4271 sc->bge_rx_overruns = 0; 4272 sc->bge_tx_discards = 0; 4273 4274 /* Init TX ring. */ 4275 bge_init_tx_ring(sc); 4276 4277 /* Enable TX MAC state machine lockup fix. */ 4278 mode = CSR_READ_4(sc, BGE_TX_MODE); 4279 if (BGE_IS_5755_PLUS(sc) || 4280 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) 4281 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 4282 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5720 || 4283 BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) { 4284 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 4285 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 4286 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 4287 } 4288 4289 /* Turn on transmitter */ 4290 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 4291 DELAY(100); 4292 4293 mode = CSR_READ_4(sc, BGE_RX_MODE); 4294 if (BGE_IS_5755_PLUS(sc)) 4295 mode |= BGE_RXMODE_IPV6_ENABLE; 4296 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5762) 4297 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 4298 4299 /* Turn on receiver */ 4300 CSR_WRITE_4(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 4301 DELAY(10); 4302 4303 /* 4304 * Set the number of good frames to receive after RX MBUF 4305 * Low Watermark has been reached. After the RX MAC receives 4306 * this number of frames, it will drop subsequent incoming 4307 * frames until the MBUF High Watermark is reached. 4308 */ 4309 if (BGE_IS_57765_PLUS(sc)) 4310 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 4311 else 4312 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4313 4314 /* Tell firmware we're alive. */ 4315 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4316 4317 /* Enable host interrupts. */ 4318 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4319 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4320 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4321 4322 bge_ifmedia_upd(ifp); 4323 4324 ifp->if_flags |= IFF_RUNNING; 4325 ifq_clr_oactive(&ifp->if_snd); 4326 4327 splx(s); 4328 4329 timeout_add_sec(&sc->bge_timeout, 1); 4330 } 4331 4332 /* 4333 * Set media options. 4334 */ 4335 int 4336 bge_ifmedia_upd(struct ifnet *ifp) 4337 { 4338 struct bge_softc *sc = ifp->if_softc; 4339 struct mii_data *mii = &sc->bge_mii; 4340 struct ifmedia *ifm = &sc->bge_ifmedia; 4341 4342 /* If this is a 1000baseX NIC, enable the TBI port. */ 4343 if (sc->bge_flags & BGE_FIBER_TBI) { 4344 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4345 return (EINVAL); 4346 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4347 case IFM_AUTO: 4348 /* 4349 * The BCM5704 ASIC appears to have a special 4350 * mechanism for programming the autoneg 4351 * advertisement registers in TBI mode. 4352 */ 4353 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) { 4354 u_int32_t sgdig; 4355 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4356 if (sgdig & BGE_SGDIGSTS_DONE) { 4357 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4358 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4359 sgdig |= BGE_SGDIGCFG_AUTO | 4360 BGE_SGDIGCFG_PAUSE_CAP | 4361 BGE_SGDIGCFG_ASYM_PAUSE; 4362 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4363 sgdig | BGE_SGDIGCFG_SEND); 4364 DELAY(5); 4365 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4366 } 4367 } 4368 break; 4369 case IFM_1000_SX: 4370 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4371 BGE_CLRBIT(sc, BGE_MAC_MODE, 4372 BGE_MACMODE_HALF_DUPLEX); 4373 } else { 4374 BGE_SETBIT(sc, BGE_MAC_MODE, 4375 BGE_MACMODE_HALF_DUPLEX); 4376 } 4377 DELAY(40); 4378 break; 4379 default: 4380 return (EINVAL); 4381 } 4382 /* XXX 802.3x flow control for 1000BASE-SX */ 4383 return (0); 4384 } 4385 4386 BGE_STS_SETBIT(sc, BGE_STS_LINK_EVT); 4387 if (mii->mii_instance) { 4388 struct mii_softc *miisc; 4389 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4390 mii_phy_reset(miisc); 4391 } 4392 mii_mediachg(mii); 4393 4394 /* 4395 * Force an interrupt so that we will call bge_link_upd 4396 * if needed and clear any pending link state attention. 4397 * Without this we are not getting any further interrupts 4398 * for link state changes and thus will not UP the link and 4399 * not be able to send in bge_start. The only way to get 4400 * things working was to receive a packet and get a RX intr. 4401 */ 4402 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 || 4403 sc->bge_flags & BGE_IS_5788) 4404 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4405 else 4406 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4407 4408 return (0); 4409 } 4410 4411 /* 4412 * Report current media status. 4413 */ 4414 void 4415 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4416 { 4417 struct bge_softc *sc = ifp->if_softc; 4418 struct mii_data *mii = &sc->bge_mii; 4419 4420 if (sc->bge_flags & BGE_FIBER_TBI) { 4421 ifmr->ifm_status = IFM_AVALID; 4422 ifmr->ifm_active = IFM_ETHER; 4423 if (CSR_READ_4(sc, BGE_MAC_STS) & 4424 BGE_MACSTAT_TBI_PCS_SYNCHED) { 4425 ifmr->ifm_status |= IFM_ACTIVE; 4426 } else { 4427 ifmr->ifm_active |= IFM_NONE; 4428 return; 4429 } 4430 ifmr->ifm_active |= IFM_1000_SX; 4431 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4432 ifmr->ifm_active |= IFM_HDX; 4433 else 4434 ifmr->ifm_active |= IFM_FDX; 4435 return; 4436 } 4437 4438 mii_pollstat(mii); 4439 ifmr->ifm_status = mii->mii_media_status; 4440 ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) | 4441 sc->bge_flowflags; 4442 } 4443 4444 int 4445 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4446 { 4447 struct bge_softc *sc = ifp->if_softc; 4448 struct ifreq *ifr = (struct ifreq *) data; 4449 int s, error = 0; 4450 struct mii_data *mii; 4451 4452 s = splnet(); 4453 4454 switch(command) { 4455 case SIOCSIFADDR: 4456 ifp->if_flags |= IFF_UP; 4457 if (!(ifp->if_flags & IFF_RUNNING)) 4458 bge_init(sc); 4459 break; 4460 4461 case SIOCSIFFLAGS: 4462 if (ifp->if_flags & IFF_UP) { 4463 if (ifp->if_flags & IFF_RUNNING) 4464 error = ENETRESET; 4465 else 4466 bge_init(sc); 4467 } else { 4468 if (ifp->if_flags & IFF_RUNNING) 4469 bge_stop(sc, 0); 4470 } 4471 break; 4472 4473 case SIOCSIFMEDIA: 4474 /* XXX Flow control is not supported for 1000BASE-SX */ 4475 if (sc->bge_flags & BGE_FIBER_TBI) { 4476 ifr->ifr_media &= ~IFM_ETH_FMASK; 4477 sc->bge_flowflags = 0; 4478 } 4479 4480 /* Flow control requires full-duplex mode. */ 4481 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO || 4482 (ifr->ifr_media & IFM_FDX) == 0) { 4483 ifr->ifr_media &= ~IFM_ETH_FMASK; 4484 } 4485 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) { 4486 if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) { 4487 /* We can do both TXPAUSE and RXPAUSE. */ 4488 ifr->ifr_media |= 4489 IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE; 4490 } 4491 sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK; 4492 } 4493 /* FALLTHROUGH */ 4494 case SIOCGIFMEDIA: 4495 if (sc->bge_flags & BGE_FIBER_TBI) { 4496 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 4497 command); 4498 } else { 4499 mii = &sc->bge_mii; 4500 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 4501 command); 4502 } 4503 break; 4504 4505 case SIOCGIFRXR: 4506 error = bge_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); 4507 break; 4508 4509 default: 4510 error = ether_ioctl(ifp, &sc->arpcom, command, data); 4511 } 4512 4513 if (error == ENETRESET) { 4514 if (ifp->if_flags & IFF_RUNNING) 4515 bge_iff(sc); 4516 error = 0; 4517 } 4518 4519 splx(s); 4520 return (error); 4521 } 4522 4523 int 4524 bge_rxrinfo(struct bge_softc *sc, struct if_rxrinfo *ifri) 4525 { 4526 struct if_rxring_info ifr[2]; 4527 u_int n = 0; 4528 4529 memset(ifr, 0, sizeof(ifr)); 4530 4531 if (ISSET(sc->bge_flags, BGE_RXRING_VALID)) { 4532 ifr[n].ifr_size = sc->bge_rx_std_len; 4533 strlcpy(ifr[n].ifr_name, "std", sizeof(ifr[n].ifr_name)); 4534 ifr[n].ifr_info = sc->bge_std_ring; 4535 4536 n++; 4537 } 4538 4539 if (ISSET(sc->bge_flags, BGE_JUMBO_RXRING_VALID)) { 4540 ifr[n].ifr_size = BGE_JLEN; 4541 strlcpy(ifr[n].ifr_name, "jumbo", sizeof(ifr[n].ifr_name)); 4542 ifr[n].ifr_info = sc->bge_jumbo_ring; 4543 4544 n++; 4545 } 4546 4547 return (if_rxr_info_ioctl(ifri, n, ifr)); 4548 } 4549 4550 void 4551 bge_watchdog(struct ifnet *ifp) 4552 { 4553 struct bge_softc *sc; 4554 4555 sc = ifp->if_softc; 4556 4557 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 4558 4559 bge_init(sc); 4560 4561 ifp->if_oerrors++; 4562 } 4563 4564 void 4565 bge_stop_block(struct bge_softc *sc, bus_size_t reg, u_int32_t bit) 4566 { 4567 int i; 4568 4569 BGE_CLRBIT(sc, reg, bit); 4570 4571 for (i = 0; i < BGE_TIMEOUT; i++) { 4572 if ((CSR_READ_4(sc, reg) & bit) == 0) 4573 return; 4574 delay(100); 4575 } 4576 4577 DPRINTFN(5, ("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n", 4578 sc->bge_dev.dv_xname, (u_long) reg, bit)); 4579 } 4580 4581 /* 4582 * Stop the adapter and free any mbufs allocated to the 4583 * RX and TX lists. 4584 */ 4585 void 4586 bge_stop(struct bge_softc *sc, int softonly) 4587 { 4588 struct ifnet *ifp = &sc->arpcom.ac_if; 4589 struct ifmedia_entry *ifm; 4590 struct mii_data *mii; 4591 int mtmp, itmp; 4592 4593 timeout_del(&sc->bge_timeout); 4594 timeout_del(&sc->bge_rxtimeout); 4595 timeout_del(&sc->bge_rxtimeout_jumbo); 4596 4597 ifp->if_flags &= ~IFF_RUNNING; 4598 ifp->if_timer = 0; 4599 4600 if (!softonly) { 4601 /* 4602 * Tell firmware we're shutting down. 4603 */ 4604 /* bge_stop_fw(sc); */ 4605 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 4606 4607 /* 4608 * Disable all of the receiver blocks 4609 */ 4610 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4611 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4612 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4613 if (BGE_IS_5700_FAMILY(sc)) 4614 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4615 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4616 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4617 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4618 4619 /* 4620 * Disable all of the transmit blocks 4621 */ 4622 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4623 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4624 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4625 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4626 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4627 if (BGE_IS_5700_FAMILY(sc)) 4628 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4629 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4630 4631 /* 4632 * Shut down all of the memory managers and related 4633 * state machines. 4634 */ 4635 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4636 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4637 if (BGE_IS_5700_FAMILY(sc)) 4638 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4639 4640 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4641 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4642 4643 if (!BGE_IS_5705_PLUS(sc)) { 4644 bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4645 bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4646 } 4647 4648 bge_reset(sc); 4649 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 4650 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 4651 4652 /* 4653 * Tell firmware we're shutting down. 4654 */ 4655 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4656 } 4657 4658 intr_barrier(sc->bge_intrhand); 4659 ifq_barrier(&ifp->if_snd); 4660 4661 ifq_clr_oactive(&ifp->if_snd); 4662 4663 /* Free the RX lists. */ 4664 bge_free_rx_ring_std(sc); 4665 4666 /* Free jumbo RX list. */ 4667 if (sc->bge_flags & BGE_JUMBO_RING) 4668 bge_free_rx_ring_jumbo(sc); 4669 4670 /* Free TX buffers. */ 4671 bge_free_tx_ring(sc); 4672 4673 /* 4674 * Isolate/power down the PHY, but leave the media selection 4675 * unchanged so that things will be put back to normal when 4676 * we bring the interface back up. 4677 */ 4678 if (!(sc->bge_flags & BGE_FIBER_TBI)) { 4679 mii = &sc->bge_mii; 4680 itmp = ifp->if_flags; 4681 ifp->if_flags |= IFF_UP; 4682 ifm = mii->mii_media.ifm_cur; 4683 mtmp = ifm->ifm_media; 4684 ifm->ifm_media = IFM_ETHER|IFM_NONE; 4685 mii_mediachg(mii); 4686 ifm->ifm_media = mtmp; 4687 ifp->if_flags = itmp; 4688 } 4689 4690 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4691 4692 if (!softonly) { 4693 /* Clear MAC's link state (PHY may still have link UP). */ 4694 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4695 } 4696 } 4697 4698 void 4699 bge_link_upd(struct bge_softc *sc) 4700 { 4701 struct ifnet *ifp = &sc->arpcom.ac_if; 4702 struct mii_data *mii = &sc->bge_mii; 4703 u_int32_t status; 4704 int link; 4705 4706 /* Clear 'pending link event' flag */ 4707 BGE_STS_CLRBIT(sc, BGE_STS_LINK_EVT); 4708 4709 /* 4710 * Process link state changes. 4711 * Grrr. The link status word in the status block does 4712 * not work correctly on the BCM5700 rev AX and BX chips, 4713 * according to all available information. Hence, we have 4714 * to enable MII interrupts in order to properly obtain 4715 * async link changes. Unfortunately, this also means that 4716 * we have to read the MAC status register to detect link 4717 * changes, thereby adding an additional register access to 4718 * the interrupt handler. 4719 * 4720 */ 4721 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) { 4722 status = CSR_READ_4(sc, BGE_MAC_STS); 4723 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4724 mii_pollstat(mii); 4725 4726 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4727 mii->mii_media_status & IFM_ACTIVE && 4728 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4729 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4730 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4731 (!(mii->mii_media_status & IFM_ACTIVE) || 4732 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4733 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4734 4735 /* Clear the interrupt */ 4736 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4737 BGE_EVTENB_MI_INTERRUPT); 4738 bge_miibus_readreg(&sc->bge_dev, sc->bge_phy_addr, 4739 BRGPHY_MII_ISR); 4740 bge_miibus_writereg(&sc->bge_dev, sc->bge_phy_addr, 4741 BRGPHY_MII_IMR, BRGPHY_INTRS); 4742 } 4743 return; 4744 } 4745 4746 if (sc->bge_flags & BGE_FIBER_TBI) { 4747 status = CSR_READ_4(sc, BGE_MAC_STS); 4748 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4749 if (!BGE_STS_BIT(sc, BGE_STS_LINK)) { 4750 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4751 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) 4752 BGE_CLRBIT(sc, BGE_MAC_MODE, 4753 BGE_MACMODE_TBI_SEND_CFGS); 4754 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4755 status = CSR_READ_4(sc, BGE_MAC_MODE); 4756 link = (status & BGE_MACMODE_HALF_DUPLEX) ? 4757 LINK_STATE_HALF_DUPLEX : 4758 LINK_STATE_FULL_DUPLEX; 4759 ifp->if_baudrate = IF_Gbps(1); 4760 if (ifp->if_link_state != link) { 4761 ifp->if_link_state = link; 4762 if_link_state_change(ifp); 4763 } 4764 } 4765 } else if (BGE_STS_BIT(sc, BGE_STS_LINK)) { 4766 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4767 link = LINK_STATE_DOWN; 4768 ifp->if_baudrate = 0; 4769 if (ifp->if_link_state != link) { 4770 ifp->if_link_state = link; 4771 if_link_state_change(ifp); 4772 } 4773 } 4774 } else if (BGE_STS_BIT(sc, BGE_STS_AUTOPOLL)) { 4775 /* 4776 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4777 * in status word always set. Workaround this bug by reading 4778 * PHY link status directly. 4779 */ 4780 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)? 4781 BGE_STS_LINK : 0; 4782 4783 if (BGE_STS_BIT(sc, BGE_STS_LINK) != link) { 4784 mii_pollstat(mii); 4785 4786 if (!BGE_STS_BIT(sc, BGE_STS_LINK) && 4787 mii->mii_media_status & IFM_ACTIVE && 4788 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4789 BGE_STS_SETBIT(sc, BGE_STS_LINK); 4790 else if (BGE_STS_BIT(sc, BGE_STS_LINK) && 4791 (!(mii->mii_media_status & IFM_ACTIVE) || 4792 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) 4793 BGE_STS_CLRBIT(sc, BGE_STS_LINK); 4794 } 4795 } else { 4796 /* 4797 * For controllers that call mii_tick, we have to poll 4798 * link status. 4799 */ 4800 mii_pollstat(mii); 4801 } 4802 4803 /* Clear the attention */ 4804 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 4805 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 4806 BGE_MACSTAT_LINK_CHANGED); 4807 } 4808