1 /* $OpenBSD: if_bge.c,v 1.6 2002/02/15 20:45:31 nordin Exp $ */ 2 /* 3 * Copyright (c) 2001 Wind River Systems 4 * Copyright (c) 1997, 1998, 1999, 2001 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.2 2001/09/28 18:56:57 wpaul Exp $ 35 */ 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * Written by Bill Paul <wpaul@windriver.com> 41 * Senior Engineer, Wind River Systems 42 */ 43 44 /* 45 * The Broadcom BCM5700 is based on technology originally developed by 46 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 47 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 48 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 49 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 50 * frames, highly configurable RX filtering, and 16 RX and TX queues 51 * (which, along with RX filter rules, can be used for QOS applications). 52 * Other features, such as TCP segmentation, may be available as part 53 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 54 * firmware images can be stored in hardware and need not be compiled 55 * into the driver. 56 * 57 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 58 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 59 * 60 * The BCM5701 is a single-chip solution incorporating both the BCM5700 61 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5700 62 * does not support external SSRAM. 63 * 64 * Broadcom also produces a variation of the BCM5700 under the "Altima" 65 * brand name, which is functionally similar but lacks PCI-X support. 66 * 67 * Without external SSRAM, you can only have at most 4 TX rings, 68 * and the use of the mini RX ring is disabled. This seems to imply 69 * that these features are simply not available on the BCM5701. As a 70 * result, this driver does not implement any support for the mini RX 71 * ring. 72 */ 73 74 #include "bpfilter.h" 75 #include "vlan.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/sockio.h> 80 #include <sys/mbuf.h> 81 #include <sys/malloc.h> 82 #include <sys/kernel.h> 83 #include <sys/device.h> 84 #include <sys/socket.h> 85 86 #include <net/if.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #ifdef INET 91 #include <netinet/in.h> 92 #include <netinet/in_systm.h> 93 #include <netinet/in_var.h> 94 #include <netinet/ip.h> 95 #include <netinet/if_ether.h> 96 #endif 97 98 #if NVLAN > 0 99 #include <net/if_types.h> 100 #include <net/if_vlan_var.h> 101 #endif 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #endif 106 107 #include <dev/pci/pcireg.h> 108 #include <dev/pci/pcivar.h> 109 #include <dev/pci/pcidevs.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 #include <dev/mii/miidevs.h> 114 #include <dev/mii/brgphyreg.h> 115 116 #include <dev/pci/if_bgereg.h> 117 118 /* #define BGE_CHECKSUM */ 119 120 int bge_probe __P((struct device *, void *, void *)); 121 void bge_attach __P((struct device *, struct device *, void *)); 122 void bge_release_resources __P((struct bge_softc *)); 123 void bge_txeof __P((struct bge_softc *)); 124 void bge_rxeof __P((struct bge_softc *)); 125 126 void bge_tick __P((void *)); 127 void bge_stats_update __P((struct bge_softc *)); 128 int bge_encap __P((struct bge_softc *, struct mbuf *, u_int32_t *)); 129 130 int bge_intr __P((void *)); 131 void bge_start __P((struct ifnet *)); 132 int bge_ioctl __P((struct ifnet *, u_long, caddr_t)); 133 void bge_init __P((void *)); 134 void bge_stop __P((struct bge_softc *)); 135 void bge_watchdog __P((struct ifnet *)); 136 void bge_shutdown __P((void *)); 137 int bge_ifmedia_upd __P((struct ifnet *)); 138 void bge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 139 140 u_int8_t bge_eeprom_getbyte __P((struct bge_softc *, 141 int, u_int8_t *)); 142 int bge_read_eeprom __P((struct bge_softc *, caddr_t, int, int)); 143 144 u_int32_t bge_crc __P((struct bge_softc *, caddr_t)); 145 void bge_setmulti __P((struct bge_softc *)); 146 147 void bge_handle_events __P((struct bge_softc *)); 148 int bge_alloc_jumbo_mem __P((struct bge_softc *)); 149 void bge_free_jumbo_mem __P((struct bge_softc *)); 150 void *bge_jalloc __P((struct bge_softc *)); 151 void bge_jfree __P((caddr_t, u_int, void *)); 152 int bge_newbuf_std __P((struct bge_softc *, int, struct mbuf *)); 153 int bge_newbuf_jumbo __P((struct bge_softc *, int, struct mbuf *)); 154 int bge_init_rx_ring_std __P((struct bge_softc *)); 155 void bge_free_rx_ring_std __P((struct bge_softc *)); 156 int bge_init_rx_ring_jumbo __P((struct bge_softc *)); 157 void bge_free_rx_ring_jumbo __P((struct bge_softc *)); 158 void bge_free_tx_ring __P((struct bge_softc *)); 159 int bge_init_tx_ring __P((struct bge_softc *)); 160 161 int bge_chipinit __P((struct bge_softc *)); 162 int bge_blockinit __P((struct bge_softc *)); 163 164 u_int8_t bge_vpd_readbyte __P((struct bge_softc *, int)); 165 void bge_vpd_read_res __P((struct bge_softc *, struct vpd_res *, int)); 166 void bge_vpd_read __P((struct bge_softc *)); 167 168 u_int32_t bge_readmem_ind __P((struct bge_softc *, int)); 169 void bge_writemem_ind __P((struct bge_softc *, int, int)); 170 #ifdef notdef 171 u_int32_t bge_readreg_ind __P((struct bge_softc *, int)); 172 #endif 173 void bge_writereg_ind __P((struct bge_softc *, int, int)); 174 175 int bge_miibus_readreg __P((struct device *, int, int)); 176 void bge_miibus_writereg __P((struct device *, int, int, int)); 177 void bge_miibus_statchg __P((struct device *)); 178 179 void bge_reset __P((struct bge_softc *)); 180 void bge_phy_hack __P((struct bge_softc *)); 181 182 #define BGE_DEBUG 183 #ifdef BGE_DEBUG 184 #define DPRINTF(x) if (bgedebug) printf x 185 #define DPRINTFN(n,x) if (bgedebug >= (n)) printf x 186 int bgedebug = 0; 187 #else 188 #define DPRINTF(x) 189 #define DPRINTFN(n,x) 190 #endif 191 192 u_int32_t 193 bge_readmem_ind(sc, off) 194 struct bge_softc *sc; 195 int off; 196 { 197 struct pci_attach_args *pa = &(sc->bge_pa); 198 199 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 200 return (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA)); 201 } 202 203 void 204 bge_writemem_ind(sc, off, val) 205 struct bge_softc *sc; 206 int off, val; 207 { 208 struct pci_attach_args *pa = &(sc->bge_pa); 209 210 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off); 211 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val); 212 } 213 214 #ifdef notdef 215 u_int32_t 216 bge_readreg_ind(sc, off) 217 struct bge_softc *sc; 218 int off; 219 { 220 struct pci_attach_args *pa = &(sc->bge_pa); 221 222 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 223 return(pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA)); 224 } 225 #endif 226 227 void 228 bge_writereg_ind(sc, off, val) 229 struct bge_softc *sc; 230 int off, val; 231 { 232 struct pci_attach_args *pa = &(sc->bge_pa); 233 234 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off); 235 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val); 236 } 237 238 u_int8_t 239 bge_vpd_readbyte(sc, addr) 240 struct bge_softc *sc; 241 int addr; 242 { 243 int i; 244 u_int32_t val; 245 struct pci_attach_args *pa = &(sc->bge_pa); 246 247 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR, addr); 248 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 249 DELAY(10); 250 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_ADDR) & 251 BGE_VPD_FLAG) 252 break; 253 } 254 255 if (i == BGE_TIMEOUT) { 256 printf("%s: VPD read timed out\n", sc->bge_dev.dv_xname); 257 return(0); 258 } 259 260 val = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_VPD_DATA); 261 262 return((val >> ((addr % 4) * 8)) & 0xFF); 263 } 264 265 void 266 bge_vpd_read_res(sc, res, addr) 267 struct bge_softc *sc; 268 struct vpd_res *res; 269 int addr; 270 { 271 int i; 272 u_int8_t *ptr; 273 274 ptr = (u_int8_t *)res; 275 for (i = 0; i < sizeof(struct vpd_res); i++) 276 ptr[i] = bge_vpd_readbyte(sc, i + addr); 277 } 278 279 void 280 bge_vpd_read(sc) 281 struct bge_softc *sc; 282 { 283 int pos = 0, i; 284 struct vpd_res res; 285 286 if (sc->bge_vpd_prodname != NULL) 287 free(sc->bge_vpd_prodname, M_DEVBUF); 288 if (sc->bge_vpd_readonly != NULL) 289 free(sc->bge_vpd_readonly, M_DEVBUF); 290 sc->bge_vpd_prodname = NULL; 291 sc->bge_vpd_readonly = NULL; 292 293 bge_vpd_read_res(sc, &res, pos); 294 295 if (res.vr_id != VPD_RES_ID) { 296 printf("%s: bad VPD resource id: expected %x got %x\n", 297 sc->bge_dev.dv_xname, VPD_RES_ID, res.vr_id); 298 return; 299 } 300 301 pos += sizeof(res); 302 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 303 if (sc->bge_vpd_prodname == NULL) 304 panic("bge_vpd_read"); 305 for (i = 0; i < res.vr_len; i++) 306 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 307 sc->bge_vpd_prodname[i] = '\0'; 308 pos += i; 309 310 bge_vpd_read_res(sc, &res, pos); 311 312 if (res.vr_id != VPD_RES_READ) { 313 printf("%s: bad VPD resource id: expected %x got %x\n", 314 sc->bge_dev.dv_xname, VPD_RES_READ, res.vr_id); 315 return; 316 } 317 318 pos += sizeof(res); 319 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 320 if (sc->bge_vpd_readonly == NULL) 321 panic("bge_vpd_read"); 322 for (i = 0; i < res.vr_len + 1; i++) 323 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 324 } 325 326 /* 327 * Read a byte of data stored in the EEPROM at address 'addr.' The 328 * BCM570x supports both the traditional bitbang interface and an 329 * auto access interface for reading the EEPROM. We use the auto 330 * access method. 331 */ 332 u_int8_t 333 bge_eeprom_getbyte(sc, addr, dest) 334 struct bge_softc *sc; 335 int addr; 336 u_int8_t *dest; 337 { 338 int i; 339 u_int32_t byte = 0; 340 341 /* 342 * Enable use of auto EEPROM access so we can avoid 343 * having to use the bitbang method. 344 */ 345 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 346 347 /* Reset the EEPROM, load the clock period. */ 348 CSR_WRITE_4(sc, BGE_EE_ADDR, 349 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 350 DELAY(20); 351 352 /* Issue the read EEPROM command. */ 353 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 354 355 /* Wait for completion */ 356 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 357 DELAY(10); 358 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 359 break; 360 } 361 362 if (i == BGE_TIMEOUT) { 363 printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname); 364 return(0); 365 } 366 367 /* Get result. */ 368 byte = CSR_READ_4(sc, BGE_EE_DATA); 369 370 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 371 372 return(0); 373 } 374 375 /* 376 * Read a sequence of bytes from the EEPROM. 377 */ 378 int 379 bge_read_eeprom(sc, dest, off, cnt) 380 struct bge_softc *sc; 381 caddr_t dest; 382 int off; 383 int cnt; 384 { 385 int err = 0, i; 386 u_int8_t byte = 0; 387 388 for (i = 0; i < cnt; i++) { 389 err = bge_eeprom_getbyte(sc, off + i, &byte); 390 if (err) 391 break; 392 *(dest + i) = byte; 393 } 394 395 return(err ? 1 : 0); 396 } 397 398 int 399 bge_miibus_readreg(dev, phy, reg) 400 struct device *dev; 401 int phy, reg; 402 { 403 struct bge_softc *sc = (struct bge_softc *)dev; 404 struct ifnet *ifp; 405 u_int32_t val; 406 int i; 407 408 ifp = &sc->arpcom.ac_if; 409 410 if (ifp->if_flags & IFF_RUNNING) 411 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 412 413 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 414 BGE_MIPHY(phy)|BGE_MIREG(reg)); 415 416 for (i = 0; i < BGE_TIMEOUT; i++) { 417 val = CSR_READ_4(sc, BGE_MI_COMM); 418 if (!(val & BGE_MICOMM_BUSY)) 419 break; 420 } 421 422 if (i == BGE_TIMEOUT) { 423 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 424 return(0); 425 } 426 427 val = CSR_READ_4(sc, BGE_MI_COMM); 428 429 if (ifp->if_flags & IFF_RUNNING) 430 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 431 432 if (val & BGE_MICOMM_READFAIL) 433 return(0); 434 435 return(val & 0xFFFF); 436 } 437 438 void 439 bge_miibus_writereg(dev, phy, reg, val) 440 struct device *dev; 441 int phy, reg, val; 442 { 443 struct bge_softc *sc = (struct bge_softc *)dev; 444 int i; 445 446 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 447 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 448 449 for (i = 0; i < BGE_TIMEOUT; i++) { 450 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 451 break; 452 } 453 454 if (i == BGE_TIMEOUT) { 455 printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname); 456 } 457 } 458 459 void 460 bge_miibus_statchg(dev) 461 struct device *dev; 462 { 463 struct bge_softc *sc = (struct bge_softc *)dev; 464 struct mii_data *mii = &sc->bge_mii; 465 466 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 467 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 468 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 469 } else { 470 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 471 } 472 473 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 474 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 475 } else { 476 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 477 } 478 479 bge_phy_hack(sc); 480 } 481 482 /* 483 * Handle events that have triggered interrupts. 484 */ 485 void 486 bge_handle_events(sc) 487 struct bge_softc *sc; 488 { 489 490 return; 491 } 492 493 /* 494 * Memory management for jumbo frames. 495 */ 496 497 int 498 bge_alloc_jumbo_mem(sc) 499 struct bge_softc *sc; 500 { 501 caddr_t ptr, kva; 502 bus_dma_segment_t seg; 503 int i, rseg; 504 struct bge_jpool_entry *entry; 505 506 /* Grab a big chunk o' storage. */ 507 if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0, 508 &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 509 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 510 return (ENOBUFS); 511 } 512 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva, 513 BUS_DMA_NOWAIT)) { 514 printf("%s: can't map dma buffers (%d bytes)\n", 515 sc->bge_dev.dv_xname, BGE_JMEM); 516 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 517 return (ENOBUFS); 518 } 519 if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0, 520 BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) { 521 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 522 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 523 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 524 return (ENOBUFS); 525 } 526 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map, 527 kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) { 528 printf("%s: can't load dma map\n", sc->bge_dev.dv_xname); 529 bus_dmamap_destroy(sc->bge_dmatag, 530 sc->bge_cdata.bge_rx_jumbo_map); 531 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 532 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 533 return (ENOBUFS); 534 } 535 sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva; 536 DPRINTFN(1,("bge_jumbo_buf = 0x%08X\n", sc->bge_cdata.bge_jumbo_buf)); 537 538 LIST_INIT(&sc->bge_jfree_listhead); 539 LIST_INIT(&sc->bge_jinuse_listhead); 540 541 /* 542 * Now divide it up into 9K pieces and save the addresses 543 * in an array. 544 */ 545 ptr = sc->bge_cdata.bge_jumbo_buf; 546 for (i = 0; i < BGE_JSLOTS; i++) { 547 sc->bge_cdata.bge_jslots[i] = ptr; 548 ptr += BGE_JLEN; 549 entry = malloc(sizeof(struct bge_jpool_entry), 550 M_DEVBUF, M_NOWAIT); 551 if (entry == NULL) { 552 bus_dmamap_unload(sc->bge_dmatag, 553 sc->bge_cdata.bge_rx_jumbo_map); 554 bus_dmamap_destroy(sc->bge_dmatag, 555 sc->bge_cdata.bge_rx_jumbo_map); 556 bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM); 557 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 558 sc->bge_cdata.bge_jumbo_buf = NULL; 559 printf("%s: no memory for jumbo buffer queue!\n", 560 sc->bge_dev.dv_xname); 561 return(ENOBUFS); 562 } 563 entry->slot = i; 564 LIST_INSERT_HEAD(&sc->bge_jfree_listhead, 565 entry, jpool_entries); 566 } 567 568 return(0); 569 } 570 571 /* 572 * Allocate a jumbo buffer. 573 */ 574 void * 575 bge_jalloc(sc) 576 struct bge_softc *sc; 577 { 578 struct bge_jpool_entry *entry; 579 580 entry = LIST_FIRST(&sc->bge_jfree_listhead); 581 582 if (entry == NULL) { 583 printf("%s: no free jumbo buffers\n", sc->bge_dev.dv_xname); 584 return(NULL); 585 } 586 587 LIST_REMOVE(entry, jpool_entries); 588 LIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 589 return(sc->bge_cdata.bge_jslots[entry->slot]); 590 } 591 592 /* 593 * Release a jumbo buffer. 594 */ 595 void 596 bge_jfree(buf, size, arg) 597 caddr_t buf; 598 u_int size; 599 void *arg; 600 { 601 struct bge_jpool_entry *entry; 602 struct bge_softc *sc; 603 int i; 604 605 /* Extract the softc struct pointer. */ 606 sc = (struct bge_softc *)arg; 607 608 if (sc == NULL) 609 panic("bge_jfree: can't find softc pointer!"); 610 611 /* calculate the slot this buffer belongs to */ 612 613 i = ((vm_offset_t)buf 614 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 615 616 if ((i < 0) || (i >= BGE_JSLOTS)) 617 panic("bge_jfree: asked to free buffer that we don't manage!"); 618 619 entry = LIST_FIRST(&sc->bge_jinuse_listhead); 620 if (entry == NULL) 621 panic("bge_jfree: buffer not in use!"); 622 entry->slot = i; 623 LIST_REMOVE(entry, jpool_entries); 624 LIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 625 } 626 627 628 /* 629 * Intialize a standard receive ring descriptor. 630 */ 631 int 632 bge_newbuf_std(sc, i, m) 633 struct bge_softc *sc; 634 int i; 635 struct mbuf *m; 636 { 637 struct mbuf *m_new = NULL; 638 struct bge_rx_bd *r; 639 bus_dmamap_t rxmap = sc->bge_cdata.bge_rx_std_map[i]; 640 641 if (m == NULL) { 642 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 643 if (m_new == NULL) { 644 printf("%s: mbuf allocation failed " 645 "-- packet dropped!\n", sc->bge_dev.dv_xname); 646 return(ENOBUFS); 647 } 648 649 MCLGET(m_new, M_DONTWAIT); 650 if (!(m_new->m_flags & M_EXT)) { 651 printf("%s: cluster allocation failed " 652 "-- packet dropped!\n", sc->bge_dev.dv_xname); 653 m_freem(m_new); 654 return(ENOBUFS); 655 } 656 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 657 } else { 658 m_new = m; 659 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 660 m_new->m_data = m_new->m_ext.ext_buf; 661 } 662 663 if (bus_dmamap_load_mbuf(sc->bge_dmatag, rxmap, m_new, BUS_DMA_NOWAIT)) 664 return(ENOBUFS); 665 666 m_adj(m_new, ETHER_ALIGN); 667 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 668 r = &sc->bge_rdata->bge_rx_std_ring[i]; 669 BGE_HOSTADDR(r->bge_addr) = rxmap->dm_segs[0].ds_addr + ETHER_ALIGN; 670 r->bge_flags = BGE_RXBDFLAG_END; 671 r->bge_len = m_new->m_len; 672 r->bge_idx = i; 673 674 return(0); 675 } 676 677 /* 678 * Initialize a jumbo receive ring descriptor. This allocates 679 * a jumbo buffer from the pool managed internally by the driver. 680 */ 681 int 682 bge_newbuf_jumbo(sc, i, m) 683 struct bge_softc *sc; 684 int i; 685 struct mbuf *m; 686 { 687 struct mbuf *m_new = NULL; 688 struct bge_rx_bd *r; 689 690 if (m == NULL) { 691 caddr_t *buf = NULL; 692 693 /* Allocate the mbuf. */ 694 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 695 if (m_new == NULL) { 696 printf("%s: mbuf allocation failed " 697 "-- packet dropped!\n", sc->bge_dev.dv_xname); 698 return(ENOBUFS); 699 } 700 701 /* Allocate the jumbo buffer */ 702 buf = bge_jalloc(sc); 703 if (buf == NULL) { 704 m_freem(m_new); 705 printf("%s: jumbo allocation failed " 706 "-- packet dropped!\n", sc->bge_dev.dv_xname); 707 return(ENOBUFS); 708 } 709 710 /* Attach the buffer to the mbuf. */ 711 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 712 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, 0, bge_jfree, sc); 713 } else { 714 m_new = m; 715 m_new->m_data = m_new->m_ext.ext_buf; 716 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 717 } 718 719 m_adj(m_new, ETHER_ALIGN); 720 /* Set up the descriptor. */ 721 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 722 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 723 BGE_HOSTADDR(r->bge_addr) = 724 BGE_JUMBO_DMA_ADDR(sc, m_new) + ETHER_ALIGN; 725 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 726 r->bge_len = m_new->m_len; 727 r->bge_idx = i; 728 729 return(0); 730 } 731 732 /* 733 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 734 * that's 1MB or memory, which is a lot. For now, we fill only the first 735 * 256 ring entries and hope that our CPU is fast enough to keep up with 736 * the NIC. 737 */ 738 int 739 bge_init_rx_ring_std(sc) 740 struct bge_softc *sc; 741 { 742 int i; 743 744 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 745 if (bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1, MCLBYTES, 746 0, BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_std_map[i])) 747 return(ENOBUFS); 748 } 749 750 for (i = 0; i < BGE_SSLOTS; i++) { 751 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 752 return(ENOBUFS); 753 } 754 755 sc->bge_std = i - 1; 756 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 757 758 return(0); 759 } 760 761 void 762 bge_free_rx_ring_std(sc) 763 struct bge_softc *sc; 764 { 765 int i; 766 767 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 768 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 769 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 770 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 771 bus_dmamap_unload(sc->bge_dmatag, 772 sc->bge_cdata.bge_rx_std_map[i]); 773 } 774 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 775 sizeof(struct bge_rx_bd)); 776 } 777 } 778 779 int 780 bge_init_rx_ring_jumbo(sc) 781 struct bge_softc *sc; 782 { 783 int i; 784 struct bge_rcb *rcb; 785 struct bge_rcb_opaque *rcbo; 786 787 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 788 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 789 return(ENOBUFS); 790 }; 791 792 sc->bge_jumbo = i - 1; 793 794 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 795 rcbo = (struct bge_rcb_opaque *)rcb; 796 rcb->bge_flags = 0; 797 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 798 799 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 800 801 return(0); 802 } 803 804 void 805 bge_free_rx_ring_jumbo(sc) 806 struct bge_softc *sc; 807 { 808 int i; 809 810 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 811 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 812 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 813 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 814 } 815 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 816 sizeof(struct bge_rx_bd)); 817 } 818 } 819 820 void 821 bge_free_tx_ring(sc) 822 struct bge_softc *sc; 823 { 824 int i; 825 826 if (sc->bge_rdata->bge_tx_ring == NULL) 827 return; 828 829 for (i = 0; i < BGE_TX_RING_CNT; i++) { 830 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 831 m_freem(sc->bge_cdata.bge_tx_chain[i]); 832 sc->bge_cdata.bge_tx_chain[i] = NULL; 833 bus_dmamap_unload(sc->bge_dmatag, 834 sc->bge_cdata.bge_tx_map[i]); 835 } 836 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 837 sizeof(struct bge_tx_bd)); 838 } 839 } 840 841 int 842 bge_init_tx_ring(sc) 843 struct bge_softc *sc; 844 { 845 int i; 846 847 sc->bge_txcnt = 0; 848 sc->bge_tx_saved_considx = 0; 849 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 850 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 851 852 for (i = 0; i < BGE_TX_RING_CNT; i++) { 853 if (bus_dmamap_create(sc->bge_dmatag, MCLBYTES, BGE_NTXSEG, 854 MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->bge_cdata.bge_tx_map[i])) 855 return(ENOBUFS); 856 } 857 858 return(0); 859 } 860 861 #define BGE_POLY 0xEDB88320 862 863 u_int32_t 864 bge_crc(sc, addr) 865 struct bge_softc *sc; 866 caddr_t addr; 867 { 868 u_int32_t idx, bit, data, crc; 869 870 /* Compute CRC for the address value. */ 871 crc = 0xFFFFFFFF; /* initial value */ 872 873 for (idx = 0; idx < 6; idx++) { 874 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 875 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 876 } 877 878 return(crc & 0x7F); 879 } 880 881 void 882 bge_setmulti(sc) 883 struct bge_softc *sc; 884 { 885 struct arpcom *ac = &sc->arpcom; 886 struct ifnet *ifp = &ac->ac_if; 887 struct ether_multi *enm; 888 struct ether_multistep step; 889 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 890 u_int32_t h; 891 int i; 892 893 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 894 for (i = 0; i < 4; i++) 895 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 896 return; 897 } 898 899 /* First, zot all the existing filters. */ 900 for (i = 0; i < 4; i++) 901 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 902 903 /* Now program new ones. */ 904 ETHER_FIRST_MULTI(step, ac, enm); 905 while (enm != NULL) { 906 h = bge_crc(sc, LLADDR((struct sockaddr_dl *)enm->enm_addrlo)); 907 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 908 ETHER_NEXT_MULTI(step, enm); 909 } 910 911 for (i = 0; i < 4; i++) 912 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 913 } 914 915 /* 916 * Do endian, PCI and DMA initialization. Also check the on-board ROM 917 * self-test results. 918 */ 919 int 920 bge_chipinit(sc) 921 struct bge_softc *sc; 922 { 923 u_int32_t cachesize; 924 int i; 925 struct pci_attach_args *pa = &(sc->bge_pa); 926 927 #ifdef BGE_CHECKSUM 928 sc->arpcom.ac_if.if_capabilities = 929 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 930 #endif 931 932 /* Set endianness before we access any non-PCI registers. */ 933 #if BYTE_ORDER == BIG_ENDIAN 934 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 935 BGE_BIGENDIAN_INIT); 936 #else 937 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 938 BGE_LITTLEENDIAN_INIT); 939 #endif 940 941 /* 942 * Check the 'ROM failed' bit on the RX CPU to see if 943 * self-tests passed. 944 */ 945 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 946 printf("%s: RX CPU self-diagnostics failed!\n", 947 sc->bge_dev.dv_xname); 948 return(ENODEV); 949 } 950 951 /* Clear the MAC control register */ 952 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 953 954 /* 955 * Clear the MAC statistics block in the NIC's 956 * internal memory. 957 */ 958 for (i = BGE_STATS_BLOCK; 959 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 960 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 961 962 for (i = BGE_STATUS_BLOCK; 963 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 964 BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0); 965 966 /* Set up the PCI DMA control register. */ 967 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 968 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F); 969 970 /* 971 * Set up general mode register. 972 */ 973 #ifndef BGE_CHECKSUM 974 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 975 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 976 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 977 BGE_MODECTL_NO_RX_CRC); 978 #else 979 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 980 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 981 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 982 BGE_MODECTL_NO_RX_CRC 983 /* |BGE_MODECTL_TX_NO_PHDR_CSUM| */ 984 /* BGE_MODECTL_RX_NO_PHDR_CSUM */ 985 ); 986 #endif 987 988 /* Get cache line size. */ 989 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 990 991 /* 992 * Avoid violating PCI spec on certain chip revs. 993 */ 994 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD) & 995 PCIM_CMD_MWIEN) { 996 switch(cachesize) { 997 case 1: 998 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 999 BGE_PCI_WRITE_BNDRY_16BYTES); 1000 break; 1001 case 2: 1002 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1003 BGE_PCI_WRITE_BNDRY_32BYTES); 1004 break; 1005 case 4: 1006 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1007 BGE_PCI_WRITE_BNDRY_64BYTES); 1008 break; 1009 case 8: 1010 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1011 BGE_PCI_WRITE_BNDRY_128BYTES); 1012 break; 1013 case 16: 1014 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1015 BGE_PCI_WRITE_BNDRY_256BYTES); 1016 break; 1017 case 32: 1018 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1019 BGE_PCI_WRITE_BNDRY_512BYTES); 1020 break; 1021 case 64: 1022 PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, 1023 BGE_PCI_WRITE_BNDRY_1024BYTES); 1024 break; 1025 default: 1026 /* Disable PCI memory write and invalidate. */ 1027 #if 0 1028 if (bootverbose) 1029 printf("%s: cache line size %d not " 1030 "supported; disabling PCI MWI\n", 1031 sc->bge_dev.dv_xname, cachesize); 1032 #endif 1033 PCI_CLRBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, 1034 PCIM_CMD_MWIEN); 1035 break; 1036 } 1037 } 1038 1039 #ifdef __brokenalpha__ 1040 /* 1041 * Must insure that we do not cross an 8K (bytes) boundary 1042 * for DMA reads. Our highest limit is 1K bytes. This is a 1043 * restriction on some ALPHA platforms with early revision 1044 * 21174 PCI chipsets, such as the AlphaPC 164lx 1045 */ 1046 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1047 #endif 1048 1049 /* Set the timer prescaler (always 66Mhz) */ 1050 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1051 1052 return(0); 1053 } 1054 1055 int 1056 bge_blockinit(sc) 1057 struct bge_softc *sc; 1058 { 1059 struct bge_rcb *rcb; 1060 struct bge_rcb_opaque *rcbo; 1061 vm_offset_t rcb_addr; 1062 int i; 1063 1064 /* 1065 * Initialize the memory window pointer register so that 1066 * we can access the first 32K of internal NIC RAM. This will 1067 * allow us to set up the TX send ring RCBs and the RX return 1068 * ring RCBs, plus other things which live in NIC memory. 1069 */ 1070 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1071 1072 /* Configure mbuf memory pool */ 1073 if (sc->bge_extram) { 1074 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1075 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1076 } else { 1077 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1078 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1079 } 1080 1081 /* Configure DMA resource pool */ 1082 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1083 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1084 1085 /* Configure mbuf pool watermarks */ 1086 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1087 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1088 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1089 1090 /* Configure DMA resource watermarks */ 1091 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1092 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1093 1094 /* Enable buffer manager */ 1095 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1096 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1097 1098 /* Poll for buffer manager start indication */ 1099 for (i = 0; i < BGE_TIMEOUT; i++) { 1100 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1101 break; 1102 DELAY(10); 1103 } 1104 1105 if (i == BGE_TIMEOUT) { 1106 printf("%s: buffer manager failed to start\n", 1107 sc->bge_dev.dv_xname); 1108 return(ENXIO); 1109 } 1110 1111 /* Enable flow-through queues */ 1112 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1113 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1114 1115 /* Wait until queue initialization is complete */ 1116 for (i = 0; i < BGE_TIMEOUT; i++) { 1117 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1118 break; 1119 DELAY(10); 1120 } 1121 1122 if (i == BGE_TIMEOUT) { 1123 printf("%s: flow-through queue init failed\n", 1124 sc->bge_dev.dv_xname); 1125 return(ENXIO); 1126 } 1127 1128 /* Initialize the standard RX ring control block */ 1129 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1130 BGE_HOSTADDR(rcb->bge_hostaddr) = 1131 BGE_RING_DMA_ADDR(sc, bge_rx_std_ring); 1132 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1133 if (sc->bge_extram) 1134 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1135 else 1136 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1137 rcb->bge_flags = 0; 1138 rcbo = (struct bge_rcb_opaque *)rcb; 1139 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1140 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1141 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1142 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1143 1144 /* 1145 * Initialize the jumbo RX ring control block 1146 * We set the 'ring disabled' bit in the flags 1147 * field until we're actually ready to start 1148 * using this ring (i.e. once we set the MTU 1149 * high enough to require it). 1150 */ 1151 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1152 BGE_HOSTADDR(rcb->bge_hostaddr) = 1153 BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring); 1154 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1155 if (sc->bge_extram) 1156 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1157 else 1158 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1159 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1160 1161 rcbo = (struct bge_rcb_opaque *)rcb; 1162 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1163 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1164 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1165 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1166 1167 /* Set up dummy disabled mini ring RCB */ 1168 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1169 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1170 rcbo = (struct bge_rcb_opaque *)rcb; 1171 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1172 1173 /* 1174 * Set the BD ring replentish thresholds. The recommended 1175 * values are 1/8th the number of descriptors allocated to 1176 * each ring. 1177 */ 1178 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1179 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1180 1181 /* 1182 * Disable all unused send rings by setting the 'ring disabled' 1183 * bit in the flags field of all the TX send ring control blocks. 1184 * These are located in NIC memory. 1185 */ 1186 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1187 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1188 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1189 BGE_RCB_FLAG_RING_DISABLED); 1190 RCB_WRITE_2(sc, rcb_addr, bge_max_len, 0); 1191 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1192 rcb_addr += sizeof(struct bge_rcb); 1193 } 1194 1195 /* Configure TX RCB 0 (we use only the first ring) */ 1196 rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1197 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1198 RCB_WRITE_4(sc, rcb_addr, BGE_HOSTADDR(bge_hostaddr), 1199 BGE_RING_DMA_ADDR(sc, bge_tx_ring)); 1200 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 1201 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1202 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_TX_RING_CNT); 1203 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1204 1205 /* Disable all unused RX return rings */ 1206 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1207 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1208 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1209 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0); 1210 RCB_WRITE_2(sc, rcb_addr, bge_flags, 1211 BGE_RCB_FLAG_RING_DISABLED); 1212 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1213 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0); 1214 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1215 (i * (sizeof(u_int64_t))), 0); 1216 rcb_addr += sizeof(struct bge_rcb); 1217 } 1218 1219 /* Initialize RX ring indexes */ 1220 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1221 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1222 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1223 1224 /* 1225 * Set up RX return ring 0 1226 * Note that the NIC address for RX return rings is 0x00000000. 1227 * The return rings live entirely within the host, so the 1228 * nicaddr field in the RCB isn't used. 1229 */ 1230 rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1231 RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0); 1232 RCB_WRITE_4(sc, rcb_addr, BGE_HOSTADDR(bge_hostaddr), 1233 BGE_RING_DMA_ADDR(sc, bge_rx_return_ring)); 1234 RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000); 1235 RCB_WRITE_2(sc, rcb_addr, bge_max_len, BGE_RETURN_RING_CNT); 1236 RCB_WRITE_2(sc, rcb_addr, bge_flags, 0); 1237 1238 /* Set random backoff seed for TX */ 1239 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1240 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1241 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1242 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1243 BGE_TX_BACKOFF_SEED_MASK); 1244 1245 /* Set inter-packet gap */ 1246 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1247 1248 /* 1249 * Specify which ring to use for packets that don't match 1250 * any RX rules. 1251 */ 1252 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1253 1254 /* 1255 * Configure number of RX lists. One interrupt distribution 1256 * list, sixteen active lists, one bad frames class. 1257 */ 1258 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1259 1260 /* Inialize RX list placement stats mask. */ 1261 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1262 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1263 1264 /* Disable host coalescing until we get it set up */ 1265 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1266 1267 /* Poll to make sure it's shut down. */ 1268 for (i = 0; i < BGE_TIMEOUT; i++) { 1269 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1270 break; 1271 DELAY(10); 1272 } 1273 1274 if (i == BGE_TIMEOUT) { 1275 printf("%s: host coalescing engine failed to idle\n", 1276 sc->bge_dev.dv_xname); 1277 return(ENXIO); 1278 } 1279 1280 /* Set up host coalescing defaults */ 1281 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1282 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1283 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1284 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1285 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1286 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1287 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1288 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1289 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1290 1291 /* Set up address of statistics block */ 1292 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1293 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1294 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1295 BGE_RING_DMA_ADDR(sc, bge_info.bge_stats)); 1296 1297 /* Set up address of status block */ 1298 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1299 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1300 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1301 BGE_RING_DMA_ADDR(sc, bge_status_block)); 1302 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1303 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1304 1305 /* Turn on host coalescing state machine */ 1306 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1307 1308 /* Turn on RX BD completion state machine and enable attentions */ 1309 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1310 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1311 1312 /* Turn on RX list placement state machine */ 1313 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1314 1315 /* Turn on RX list selector state machine. */ 1316 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1317 1318 /* Turn on DMA, clear stats */ 1319 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1320 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1321 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1322 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1323 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1324 1325 /* Set misc. local control, enable interrupts on attentions */ 1326 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1327 1328 #ifdef notdef 1329 /* Assert GPIO pins for PHY reset */ 1330 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1331 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1332 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1333 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1334 #endif 1335 1336 /* Turn on DMA completion state machine */ 1337 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1338 1339 /* Turn on write DMA state machine */ 1340 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1341 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1342 1343 /* Turn on read DMA state machine */ 1344 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1345 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1346 1347 /* Turn on RX data completion state machine */ 1348 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1349 1350 /* Turn on RX BD initiator state machine */ 1351 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1352 1353 /* Turn on RX data and RX BD initiator state machine */ 1354 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1355 1356 /* Turn on Mbuf cluster free state machine */ 1357 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1358 1359 /* Turn on send BD completion state machine */ 1360 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1361 1362 /* Turn on send data completion state machine */ 1363 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1364 1365 /* Turn on send data initiator state machine */ 1366 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1367 1368 /* Turn on send BD initiator state machine */ 1369 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1370 1371 /* Turn on send BD selector state machine */ 1372 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1373 1374 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1375 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1376 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1377 1378 /* init LED register */ 1379 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1380 1381 /* ack/clear link change events */ 1382 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1383 BGE_MACSTAT_CFG_CHANGED); 1384 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1385 1386 /* Enable PHY auto polling (for MII/GMII only) */ 1387 if (sc->bge_tbi) { 1388 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1389 } else 1390 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1391 1392 /* Enable link state change attentions. */ 1393 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1394 1395 return(0); 1396 } 1397 1398 /* 1399 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1400 * against our list and return its name if we find a match. Note 1401 * that since the Broadcom controller contains VPD support, we 1402 * can get the device name string from the controller itself instead 1403 * of the compiled-in string. This is a little slow, but it guarantees 1404 * we'll always announce the right product name. 1405 */ 1406 int 1407 bge_probe(parent, match, aux) 1408 struct device *parent; 1409 void *match; 1410 void *aux; 1411 { 1412 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 1413 1414 /* 1415 * Various supported device vendors/types and their 1416 * names. Note: the spec seems to indicate that the hardware 1417 * still has Alteon's vendor ID burned into it, though it will 1418 * always be overriden by the vendor ID in the EEPROM. Just to 1419 * be safe, we cover all possibilities. 1420 */ 1421 1422 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON && 1423 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_BCM5700 || 1424 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_BCM5701)) 1425 return (1); 1426 1427 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM && 1428 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5700 || 1429 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5701)) 1430 return (1); 1431 1432 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SCHNEIDERKOCH && 1433 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SCHNEIDERKOCH_SK9D21) 1434 return (1); 1435 1436 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3COM && 1437 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3COM_3C996) 1438 return (1); 1439 1440 return (0); 1441 } 1442 1443 void 1444 bge_attach(parent, self, aux) 1445 struct device *parent, *self; 1446 void *aux; 1447 { 1448 struct bge_softc *sc = (struct bge_softc *)self; 1449 struct pci_attach_args *pa = aux; 1450 pci_chipset_tag_t pc = pa->pa_pc; 1451 pci_intr_handle_t ih; 1452 const char *intrstr = NULL; 1453 bus_addr_t iobase; 1454 bus_size_t iosize; 1455 bus_dma_segment_t seg; 1456 int s, rseg; 1457 u_int32_t command; 1458 struct ifnet *ifp; 1459 int unit, error = 0; 1460 caddr_t kva; 1461 1462 s = splimp(); 1463 1464 sc->bge_pa = *pa; 1465 1466 /* 1467 * Map control/status registers. 1468 */ 1469 DPRINTFN(5, ("Map control/status regs\n")); 1470 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1471 command |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE; 1472 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 1473 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 1474 1475 if (!(command & PCI_COMMAND_MEM_ENABLE)) { 1476 printf("%s: failed to enable memory mapping!\n", 1477 sc->bge_dev.dv_xname); 1478 error = ENXIO; 1479 goto fail; 1480 } 1481 1482 DPRINTFN(5, ("pci_mem_find\n")); 1483 if (pci_mem_find(pc, pa->pa_tag, BGE_PCI_BAR0, &iobase, 1484 &iosize, NULL)) { 1485 printf(": can't find mem space\n"); 1486 goto fail; 1487 } 1488 1489 DPRINTFN(5, ("bus_space_map\n")); 1490 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->bge_bhandle)) { 1491 printf(": can't map mem space\n"); 1492 goto fail; 1493 } 1494 1495 sc->bge_btag = pa->pa_memt; 1496 1497 DPRINTFN(5, ("pci_intr_map\n")); 1498 if (pci_intr_map(pa, &ih)) { 1499 printf(": couldn't map interrupt\n"); 1500 goto fail; 1501 } 1502 1503 DPRINTFN(5, ("pci_intr_string\n")); 1504 intrstr = pci_intr_string(pc, ih); 1505 1506 DPRINTFN(5, ("pci_intr_establish\n")); 1507 sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc, 1508 sc->bge_dev.dv_xname); 1509 1510 if (sc->bge_intrhand == NULL) { 1511 printf(": couldn't establish interrupt"); 1512 if (intrstr != NULL) 1513 printf(" at %s", intrstr); 1514 printf("\n"); 1515 goto fail; 1516 } 1517 printf(": %s", intrstr); 1518 1519 /* Try to reset the chip. */ 1520 DPRINTFN(5, ("bge_reset\n")); 1521 bge_reset(sc); 1522 1523 if (bge_chipinit(sc)) { 1524 printf("%s: chip initializatino failed\n", 1525 sc->bge_dev.dv_xname); 1526 bge_release_resources(sc); 1527 error = ENXIO; 1528 goto fail; 1529 } 1530 1531 /* 1532 * Get station address from the EEPROM. 1533 */ 1534 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1535 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1536 printf("bge%d: failed to read station address\n", unit); 1537 bge_release_resources(sc); 1538 error = ENXIO; 1539 goto fail; 1540 } 1541 1542 /* 1543 * A Broadcom chip was detected. Inform the world. 1544 */ 1545 printf(": Ethernet address: %s\n", 1546 ether_sprintf(sc->arpcom.ac_enaddr)); 1547 1548 /* Allocate the general information block and ring buffers. */ 1549 sc->bge_dmatag = pa->pa_dmat; 1550 DPRINTFN(5, ("bus_dmamem_alloc\n")); 1551 if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data), 1552 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) { 1553 printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname); 1554 goto fail; 1555 } 1556 DPRINTFN(5, ("bus_dmamem_map\n")); 1557 if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, 1558 sizeof(struct bge_ring_data), &kva, 1559 BUS_DMA_NOWAIT)) { 1560 printf("%s: can't map dma buffers (%d bytes)\n", 1561 sc->bge_dev.dv_xname, sizeof(struct bge_ring_data)); 1562 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1563 goto fail; 1564 } 1565 DPRINTFN(5, ("bus_dmamem_create\n")); 1566 if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1, 1567 sizeof(struct bge_ring_data), 0, 1568 BUS_DMA_NOWAIT, &sc->bge_ring_map)) { 1569 printf("%s: can't create dma map\n", sc->bge_dev.dv_xname); 1570 bus_dmamem_unmap(sc->bge_dmatag, kva, 1571 sizeof(struct bge_ring_data)); 1572 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1573 goto fail; 1574 } 1575 DPRINTFN(5, ("bus_dmamem_load\n")); 1576 if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva, 1577 sizeof(struct bge_ring_data), NULL, 1578 BUS_DMA_NOWAIT)) { 1579 bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map); 1580 bus_dmamem_unmap(sc->bge_dmatag, kva, 1581 sizeof(struct bge_ring_data)); 1582 bus_dmamem_free(sc->bge_dmatag, &seg, rseg); 1583 goto fail; 1584 } 1585 1586 DPRINTFN(5, ("bzero\n")); 1587 sc->bge_rdata = (struct bge_ring_data *)kva; 1588 1589 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1590 1591 /* Try to allocate memory for jumbo buffers. */ 1592 if (bge_alloc_jumbo_mem(sc)) { 1593 printf("%s: jumbo buffer allocation failed\n", 1594 sc->bge_dev.dv_xname); 1595 error = ENXIO; 1596 goto fail; 1597 } 1598 1599 /* Set default tuneable values. */ 1600 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1601 sc->bge_rx_coal_ticks = 150; 1602 sc->bge_tx_coal_ticks = 150; 1603 sc->bge_rx_max_coal_bds = 64; 1604 sc->bge_tx_max_coal_bds = 128; 1605 1606 /* Set up ifnet structure */ 1607 ifp = &sc->arpcom.ac_if; 1608 ifp->if_softc = sc; 1609 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1610 ifp->if_ioctl = bge_ioctl; 1611 ifp->if_output = ether_output; 1612 ifp->if_start = bge_start; 1613 ifp->if_watchdog = bge_watchdog; 1614 ifp->if_baudrate = 1000000000; 1615 ifp->if_mtu = ETHERMTU; 1616 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1617 DPRINTFN(5, ("bcopy\n")); 1618 bcopy(sc->bge_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 1619 1620 /* 1621 * Do MII setup. 1622 */ 1623 DPRINTFN(5, ("mii setup\n")); 1624 sc->bge_mii.mii_ifp = ifp; 1625 sc->bge_mii.mii_readreg = bge_miibus_readreg; 1626 sc->bge_mii.mii_writereg = bge_miibus_writereg; 1627 sc->bge_mii.mii_statchg = bge_miibus_statchg; 1628 1629 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1630 if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_SUBSYS) >> 16) == 1631 SK_SUBSYSID_9D41) 1632 sc->bge_tbi = 1; 1633 1634 /* 1635 * Do transceiver setup. 1636 */ 1637 ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd, 1638 bge_ifmedia_sts); 1639 mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff, 1640 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1641 1642 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) { 1643 printf("%s: no PHY found!\n", sc->bge_dev.dv_xname); 1644 ifmedia_add(&sc->bge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 1645 0, NULL); 1646 ifmedia_set(&sc->bge_mii.mii_media, IFM_ETHER|IFM_MANUAL); 1647 } else 1648 ifmedia_set(&sc->bge_mii.mii_media, IFM_ETHER|IFM_AUTO); 1649 1650 /* 1651 * Call MI attach routine. 1652 */ 1653 DPRINTFN(5, ("if_attach\n")); 1654 if_attach(ifp); 1655 DPRINTFN(5, ("ether_ifattach\n")); 1656 ether_ifattach(ifp); 1657 DPRINTFN(5, ("timeout_set\n")); 1658 timeout_set(&sc->bge_timeout, bge_tick, sc); 1659 fail: 1660 splx(s); 1661 } 1662 1663 void 1664 bge_release_resources(sc) 1665 struct bge_softc *sc; 1666 { 1667 if (sc->bge_vpd_prodname != NULL) 1668 free(sc->bge_vpd_prodname, M_DEVBUF); 1669 1670 if (sc->bge_vpd_readonly != NULL) 1671 free(sc->bge_vpd_readonly, M_DEVBUF); 1672 1673 #ifdef fake 1674 if (sc->bge_intrhand != NULL) 1675 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1676 1677 if (sc->bge_irq != NULL) 1678 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1679 1680 if (sc->bge_res != NULL) 1681 bus_release_resource(dev, SYS_RES_MEMORY, 1682 BGE_PCI_BAR0, sc->bge_res); 1683 1684 if (sc->bge_rdata != NULL) 1685 contigfree(sc->bge_rdata, 1686 sizeof(struct bge_ring_data), M_DEVBUF); 1687 #endif 1688 } 1689 1690 void 1691 bge_reset(sc) 1692 struct bge_softc *sc; 1693 { 1694 struct pci_attach_args *pa = &sc->bge_pa; 1695 u_int32_t cachesize, command, pcistate; 1696 int i, val = 0; 1697 1698 /* Save some important PCI state. */ 1699 cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ); 1700 command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD); 1701 pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE); 1702 1703 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1704 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1705 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW); 1706 1707 /* Issue global reset */ 1708 bge_writereg_ind(sc, BGE_MISC_CFG, 1709 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1710 1711 DELAY(1000); 1712 1713 /* Reset some of the PCI state that got zapped by reset */ 1714 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL, 1715 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1716 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW); 1717 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize); 1718 pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command); 1719 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1720 1721 /* 1722 * Prevent PXE restart: write a magic number to the 1723 * general communications memory at 0xB50. 1724 */ 1725 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1726 /* 1727 * Poll the value location we just wrote until 1728 * we see the 1's complement of the magic number. 1729 * This indicates that the firmware initialization 1730 * is complete. 1731 */ 1732 for (i = 0; i < BGE_TIMEOUT; i++) { 1733 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1734 if (val == ~BGE_MAGIC_NUMBER) 1735 break; 1736 DELAY(10); 1737 } 1738 1739 if (i == BGE_TIMEOUT) { 1740 printf("%s: firmware handshake timed out\n", 1741 sc->bge_dev.dv_xname); 1742 return; 1743 } 1744 1745 /* 1746 * XXX Wait for the value of the PCISTATE register to 1747 * return to its original pre-reset state. This is a 1748 * fairly good indicator of reset completion. If we don't 1749 * wait for the reset to fully complete, trying to read 1750 * from the device's non-PCI registers may yield garbage 1751 * results. 1752 */ 1753 for (i = 0; i < BGE_TIMEOUT; i++) { 1754 if (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) == 1755 pcistate) 1756 break; 1757 DELAY(10); 1758 } 1759 1760 /* Enable memory arbiter. */ 1761 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1762 1763 /* Fix up byte swapping */ 1764 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1765 BGE_MODECTL_BYTESWAP_DATA); 1766 1767 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1768 1769 DELAY(10000); 1770 } 1771 1772 /* 1773 * Frame reception handling. This is called if there's a frame 1774 * on the receive return list. 1775 * 1776 * Note: we have to be able to handle two possibilities here: 1777 * 1) the frame is from the jumbo recieve ring 1778 * 2) the frame is from the standard receive ring 1779 */ 1780 1781 void 1782 bge_rxeof(sc) 1783 struct bge_softc *sc; 1784 { 1785 struct ifnet *ifp; 1786 int stdcnt = 0, jumbocnt = 0; 1787 1788 ifp = &sc->arpcom.ac_if; 1789 1790 while(sc->bge_rx_saved_considx != 1791 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1792 struct bge_rx_bd *cur_rx; 1793 u_int32_t rxidx; 1794 struct mbuf *m = NULL; 1795 #if NVLAN > 0 1796 u_int16_t vlan_tag = 0; 1797 int have_tag = 0; 1798 #endif 1799 #ifdef BGE_CHECKSUM 1800 int sumflags = 0; 1801 #endif 1802 1803 cur_rx = &sc->bge_rdata-> 1804 bge_rx_return_ring[sc->bge_rx_saved_considx]; 1805 1806 rxidx = cur_rx->bge_idx; 1807 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1808 1809 #if NVLAN > 0 1810 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1811 have_tag = 1; 1812 vlan_tag = cur_rx->bge_vlan_tag; 1813 } 1814 #endif 1815 1816 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1817 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1818 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1819 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1820 jumbocnt++; 1821 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1822 ifp->if_ierrors++; 1823 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1824 continue; 1825 } 1826 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 1827 NULL)== ENOBUFS) { 1828 ifp->if_ierrors++; 1829 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1830 continue; 1831 } 1832 } else { 1833 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1834 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1835 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1836 bus_dmamap_unload(sc->bge_dmatag, 1837 sc->bge_cdata.bge_rx_std_map[rxidx]); 1838 stdcnt++; 1839 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1840 ifp->if_ierrors++; 1841 bge_newbuf_std(sc, sc->bge_std, m); 1842 continue; 1843 } 1844 if (bge_newbuf_std(sc, sc->bge_std, 1845 NULL) == ENOBUFS) { 1846 ifp->if_ierrors++; 1847 bge_newbuf_std(sc, sc->bge_std, m); 1848 continue; 1849 } 1850 } 1851 1852 ifp->if_ipackets++; 1853 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1854 m->m_pkthdr.rcvif = ifp; 1855 1856 #if NBPFILTER > 0 1857 /* 1858 * Handle BPF listeners. Let the BPF user see the packet. 1859 */ 1860 if (ifp->if_bpf) 1861 bpf_mtap(ifp->if_bpf, m); 1862 #endif 1863 1864 #ifdef BGE_CHECKSUM 1865 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1866 sumflags |= M_IPV4_CSUM_IN_OK; 1867 else 1868 sumflags |= M_IPV4_CSUM_IN_BAD; 1869 #if 0 1870 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1871 m->m_pkthdr.csum_data = 1872 cur_rx->bge_tcp_udp_csum; 1873 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1874 } 1875 #endif 1876 m->m_pkthdr.csum = sumflags; 1877 sumflags = 0; 1878 #endif 1879 1880 #if NVLAN > 0 1881 /* 1882 * If we received a packet with a vlan tag, pass it 1883 * to vlan_input() instead of ether_input(). 1884 */ 1885 if (have_tag) { 1886 vlan_input_tag(m, vlan_tag); 1887 have_tag = vlan_tag = 0; 1888 continue; 1889 } 1890 #endif 1891 ether_input_mbuf(ifp, m); 1892 } 1893 1894 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1895 if (stdcnt) 1896 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1897 if (jumbocnt) 1898 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1899 } 1900 1901 void 1902 bge_txeof(sc) 1903 struct bge_softc *sc; 1904 { 1905 struct bge_tx_bd *cur_tx = NULL; 1906 struct ifnet *ifp; 1907 1908 ifp = &sc->arpcom.ac_if; 1909 1910 /* 1911 * Go through our tx ring and free mbufs for those 1912 * frames that have been sent. 1913 */ 1914 while (sc->bge_tx_saved_considx != 1915 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1916 u_int32_t idx = 0; 1917 1918 idx = sc->bge_tx_saved_considx; 1919 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1920 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1921 ifp->if_opackets++; 1922 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1923 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1924 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1925 bus_dmamap_unload(sc->bge_dmatag, 1926 sc->bge_cdata.bge_tx_map[idx]); 1927 } 1928 sc->bge_txcnt--; 1929 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1930 ifp->if_timer = 0; 1931 } 1932 1933 if (cur_tx != NULL) 1934 ifp->if_flags &= ~IFF_OACTIVE; 1935 } 1936 1937 int 1938 bge_intr(xsc) 1939 void *xsc; 1940 { 1941 struct bge_softc *sc; 1942 struct ifnet *ifp; 1943 1944 sc = xsc; 1945 ifp = &sc->arpcom.ac_if; 1946 1947 #ifdef notdef 1948 /* Avoid this for now -- checking this register is expensive. */ 1949 /* Make sure this is really our interrupt. */ 1950 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 1951 return (0); 1952 #endif 1953 /* Ack interrupt and stop others from occuring. */ 1954 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 1955 1956 /* Process link state changes. */ 1957 if (sc->bge_rdata->bge_status_block.bge_status & 1958 BGE_STATFLAG_LINKSTATE_CHANGED) { 1959 sc->bge_link = 0; 1960 timeout_del(&sc->bge_timeout); 1961 bge_tick(sc); 1962 /* ack the event to clear/reset it */ 1963 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1964 BGE_MACSTAT_CFG_CHANGED); 1965 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1966 } 1967 1968 if (ifp->if_flags & IFF_RUNNING) { 1969 /* Check RX return ring producer/consumer */ 1970 bge_rxeof(sc); 1971 1972 /* Check TX ring producer/consumer */ 1973 bge_txeof(sc); 1974 } 1975 1976 bge_handle_events(sc); 1977 1978 /* Re-enable interrupts. */ 1979 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 1980 1981 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 1982 bge_start(ifp); 1983 1984 return (1); 1985 } 1986 1987 void 1988 bge_tick(xsc) 1989 void *xsc; 1990 { 1991 struct bge_softc *sc = xsc; 1992 struct mii_data *mii = &sc->bge_mii; 1993 struct ifmedia *ifm = NULL; 1994 struct ifnet *ifp = &sc->arpcom.ac_if; 1995 int s; 1996 1997 s = splimp(); 1998 1999 bge_stats_update(sc); 2000 timeout_add(&sc->bge_timeout, hz); 2001 if (sc->bge_link) { 2002 splx(s); 2003 return; 2004 } 2005 2006 if (sc->bge_tbi) { 2007 ifm = &sc->bge_ifmedia; 2008 if (CSR_READ_4(sc, BGE_MAC_STS) & 2009 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2010 sc->bge_link++; 2011 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2012 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2013 if (ifp->if_snd.ifq_head != NULL) 2014 bge_start(ifp); 2015 } 2016 splx(s); 2017 return; 2018 } 2019 2020 mii_tick(mii); 2021 2022 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2023 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2024 sc->bge_link++; 2025 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 2026 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2027 printf("%s: gigabit link up\n", sc->bge_dev.dv_xname); 2028 if (ifp->if_snd.ifq_head != NULL) 2029 bge_start(ifp); 2030 } 2031 2032 splx(s); 2033 } 2034 2035 void 2036 bge_stats_update(sc) 2037 struct bge_softc *sc; 2038 { 2039 struct ifnet *ifp = &sc->arpcom.ac_if; 2040 bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 2041 2042 #define READ_STAT(sc, stats, stat) \ 2043 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 2044 2045 ifp->if_collisions += 2046 (READ_STAT(sc, stats, dot3StatsSingleCollisionFrames.bge_addr_lo) + 2047 READ_STAT(sc, stats, dot3StatsMultipleCollisionFrames.bge_addr_lo) + 2048 READ_STAT(sc, stats, dot3StatsExcessiveCollisions.bge_addr_lo) + 2049 READ_STAT(sc, stats, dot3StatsLateCollisions.bge_addr_lo)) - 2050 ifp->if_collisions; 2051 2052 #undef READ_STAT 2053 2054 #ifdef notdef 2055 ifp->if_collisions += 2056 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2057 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2058 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2059 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2060 ifp->if_collisions; 2061 #endif 2062 } 2063 2064 /* 2065 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2066 * pointers to descriptors. 2067 */ 2068 int 2069 bge_encap(sc, m_head, txidx) 2070 struct bge_softc *sc; 2071 struct mbuf *m_head; 2072 u_int32_t *txidx; 2073 { 2074 struct bge_tx_bd *f = NULL; 2075 struct mbuf *m; 2076 u_int32_t frag, cur, cnt = 0; 2077 u_int16_t csum_flags = 0; 2078 bus_dmamap_t txmap; 2079 int i = 0; 2080 #if NVLAN > 0 2081 struct ifvlan *ifv = NULL; 2082 2083 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2084 m_head->m_pkthdr.rcvif != NULL) 2085 ifv = m_head->m_pkthdr.rcvif->if_softc; 2086 #endif 2087 2088 m = m_head; 2089 cur = frag = *txidx; 2090 2091 #ifdef BGE_CHECKSUM 2092 if (m_head->m_pkthdr.csum) { 2093 if (m_head->m_pkthdr.csum & M_IPV4_CSUM_OUT) 2094 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2095 if (m_head->m_pkthdr.csum & (M_TCPV4_CSUM_OUT | 2096 M_UDPV4_CSUM_OUT)) 2097 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2098 #ifdef fake 2099 if (m_head->m_flags & M_LASTFRAG) 2100 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2101 else if (m_head->m_flags & M_FRAG) 2102 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2103 #endif 2104 } 2105 #endif 2106 2107 /* 2108 * Start packing the mbufs in this chain into 2109 * the fragment pointers. Stop when we run out 2110 * of fragments or hit the end of the mbuf chain. 2111 */ 2112 txmap = sc->bge_cdata.bge_tx_map[frag]; 2113 if (bus_dmamap_load_mbuf(sc->bge_dmatag, txmap, m, 2114 BUS_DMA_NOWAIT)) 2115 return(ENOBUFS); 2116 2117 for (m = m_head; m != NULL; m = m->m_next) { 2118 if (m->m_len != 0) { 2119 f = &sc->bge_rdata->bge_tx_ring[frag]; 2120 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2121 break; 2122 BGE_HOSTADDR(f->bge_addr) = 2123 txmap->dm_segs[i++].ds_addr; 2124 f->bge_len = m->m_len; 2125 f->bge_flags = csum_flags; 2126 #if NVLAN > 0 2127 if (ifv != NULL) { 2128 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2129 f->bge_vlan_tag = ifv->ifv_tag; 2130 } else { 2131 f->bge_vlan_tag = 0; 2132 } 2133 #endif 2134 /* 2135 * Sanity check: avoid coming within 16 descriptors 2136 * of the end of the ring. 2137 */ 2138 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2139 return(ENOBUFS); 2140 cur = frag; 2141 BGE_INC(frag, BGE_TX_RING_CNT); 2142 cnt++; 2143 } 2144 } 2145 2146 if (m != NULL) 2147 return(ENOBUFS); 2148 2149 if (frag == sc->bge_tx_saved_considx) 2150 return(ENOBUFS); 2151 2152 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2153 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2154 sc->bge_txcnt += cnt; 2155 2156 *txidx = frag; 2157 2158 return(0); 2159 } 2160 2161 /* 2162 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2163 * to the mbuf data regions directly in the transmit descriptors. 2164 */ 2165 void 2166 bge_start(ifp) 2167 struct ifnet *ifp; 2168 { 2169 struct bge_softc *sc; 2170 struct mbuf *m_head = NULL; 2171 u_int32_t prodidx = 0; 2172 2173 sc = ifp->if_softc; 2174 2175 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2176 return; 2177 2178 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2179 2180 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2181 IF_DEQUEUE(&ifp->if_snd, m_head); 2182 if (m_head == NULL) 2183 break; 2184 2185 /* 2186 * XXX 2187 * safety overkill. If this is a fragmented packet chain 2188 * with delayed TCP/UDP checksums, then only encapsulate 2189 * it if we have enough descriptors to handle the entire 2190 * chain at once. 2191 * (paranoia -- may not actually be needed) 2192 */ 2193 #ifdef fake 2194 if (m_head->m_flags & M_FIRSTFRAG && 2195 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2196 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2197 m_head->m_pkthdr.csum_data + 16) { 2198 IF_PREPEND(&ifp->if_snd, m_head); 2199 ifp->if_flags |= IFF_OACTIVE; 2200 break; 2201 } 2202 } 2203 #endif 2204 2205 /* 2206 * Pack the data into the transmit ring. If we 2207 * don't have room, set the OACTIVE flag and wait 2208 * for the NIC to drain the ring. 2209 */ 2210 if (bge_encap(sc, m_head, &prodidx)) { 2211 IF_PREPEND(&ifp->if_snd, m_head); 2212 ifp->if_flags |= IFF_OACTIVE; 2213 break; 2214 } 2215 2216 /* 2217 * If there's a BPF listener, bounce a copy of this frame 2218 * to him. 2219 */ 2220 if (ifp->if_bpf) 2221 bpf_mtap(ifp->if_bpf, m_head); 2222 } 2223 2224 /* Transmit */ 2225 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2226 2227 /* 2228 * Set a timeout in case the chip goes out to lunch. 2229 */ 2230 ifp->if_timer = 5; 2231 } 2232 2233 /* 2234 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2235 * program its internal DSP. Failing to do this can result in 2236 * massive packet loss at 1Gb speeds. 2237 */ 2238 void 2239 bge_phy_hack(sc) 2240 struct bge_softc *sc; 2241 { 2242 struct bge_bcom_hack bhack[] = { 2243 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2244 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2245 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2246 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2247 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2248 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2249 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2250 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2251 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2252 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2253 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2254 { 0, 0 } }; 2255 u_int16_t vid, did; 2256 int i; 2257 2258 vid = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR1); 2259 did = bge_miibus_readreg(&sc->bge_dev, 1, MII_PHYIDR2); 2260 2261 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2262 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2263 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2264 i = 0; 2265 while (bhack[i].reg) { 2266 bge_miibus_writereg(&sc->bge_dev, 1, bhack[i].reg, 2267 bhack[i].val); 2268 i++; 2269 } 2270 } 2271 } 2272 2273 void 2274 bge_init(xsc) 2275 void *xsc; 2276 { 2277 struct bge_softc *sc = xsc; 2278 struct ifnet *ifp; 2279 u_int16_t *m; 2280 int s; 2281 2282 s = splimp(); 2283 2284 ifp = &sc->arpcom.ac_if; 2285 2286 if (ifp->if_flags & IFF_RUNNING) 2287 return; 2288 2289 /* Cancel pending I/O and flush buffers. */ 2290 bge_stop(sc); 2291 bge_reset(sc); 2292 bge_chipinit(sc); 2293 2294 /* 2295 * Init the various state machines, ring 2296 * control blocks and firmware. 2297 */ 2298 if (bge_blockinit(sc)) { 2299 printf("%s: initialization failure\n", sc->bge_dev.dv_xname); 2300 splx(s); 2301 return; 2302 } 2303 2304 ifp = &sc->arpcom.ac_if; 2305 2306 /* Specify MTU. */ 2307 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2308 ETHER_HDR_LEN + ETHER_CRC_LEN); 2309 2310 /* Load our MAC address. */ 2311 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2312 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2313 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2314 2315 /* Enable or disable promiscuous mode as needed. */ 2316 if (ifp->if_flags & IFF_PROMISC) { 2317 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2318 } else { 2319 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2320 } 2321 2322 /* Program multicast filter. */ 2323 bge_setmulti(sc); 2324 2325 /* Init RX ring. */ 2326 bge_init_rx_ring_std(sc); 2327 2328 /* Init jumbo RX ring. */ 2329 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2330 bge_init_rx_ring_jumbo(sc); 2331 2332 /* Init our RX return ring index */ 2333 sc->bge_rx_saved_considx = 0; 2334 2335 /* Init TX ring. */ 2336 bge_init_tx_ring(sc); 2337 2338 /* Turn on transmitter */ 2339 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2340 2341 /* Turn on receiver */ 2342 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2343 2344 /* Tell firmware we're alive. */ 2345 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2346 2347 /* Enable host interrupts. */ 2348 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2349 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2350 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2351 2352 bge_ifmedia_upd(ifp); 2353 2354 ifp->if_flags |= IFF_RUNNING; 2355 ifp->if_flags &= ~IFF_OACTIVE; 2356 2357 splx(s); 2358 2359 timeout_add(&sc->bge_timeout, hz); 2360 } 2361 2362 /* 2363 * Set media options. 2364 */ 2365 int 2366 bge_ifmedia_upd(ifp) 2367 struct ifnet *ifp; 2368 { 2369 struct bge_softc *sc = ifp->if_softc; 2370 struct mii_data *mii = &sc->bge_mii; 2371 struct ifmedia *ifm = &sc->bge_ifmedia; 2372 2373 /* If this is a 1000baseX NIC, enable the TBI port. */ 2374 if (sc->bge_tbi) { 2375 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2376 return(EINVAL); 2377 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2378 case IFM_AUTO: 2379 break; 2380 case IFM_1000_SX: 2381 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2382 BGE_CLRBIT(sc, BGE_MAC_MODE, 2383 BGE_MACMODE_HALF_DUPLEX); 2384 } else { 2385 BGE_SETBIT(sc, BGE_MAC_MODE, 2386 BGE_MACMODE_HALF_DUPLEX); 2387 } 2388 break; 2389 default: 2390 return(EINVAL); 2391 } 2392 return(0); 2393 } 2394 2395 sc->bge_link = 0; 2396 if (mii->mii_instance) { 2397 struct mii_softc *miisc; 2398 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2399 miisc = LIST_NEXT(miisc, mii_list)) 2400 mii_phy_reset(miisc); 2401 } 2402 bge_phy_hack(sc); 2403 mii_mediachg(mii); 2404 2405 return(0); 2406 } 2407 2408 /* 2409 * Report current media status. 2410 */ 2411 void 2412 bge_ifmedia_sts(ifp, ifmr) 2413 struct ifnet *ifp; 2414 struct ifmediareq *ifmr; 2415 { 2416 struct bge_softc *sc = ifp->if_softc; 2417 struct mii_data *mii = &sc->bge_mii; 2418 2419 if (sc->bge_tbi) { 2420 ifmr->ifm_status = IFM_AVALID; 2421 ifmr->ifm_active = IFM_ETHER; 2422 if (CSR_READ_4(sc, BGE_MAC_STS) & 2423 BGE_MACSTAT_TBI_PCS_SYNCHED) 2424 ifmr->ifm_status |= IFM_ACTIVE; 2425 ifmr->ifm_active |= IFM_1000_SX; 2426 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2427 ifmr->ifm_active |= IFM_HDX; 2428 else 2429 ifmr->ifm_active |= IFM_FDX; 2430 return; 2431 } 2432 2433 mii_pollstat(mii); 2434 ifmr->ifm_active = mii->mii_media_active; 2435 ifmr->ifm_status = mii->mii_media_status; 2436 } 2437 2438 int 2439 bge_ioctl(ifp, command, data) 2440 struct ifnet *ifp; 2441 u_long command; 2442 caddr_t data; 2443 { 2444 struct bge_softc *sc = ifp->if_softc; 2445 struct ifreq *ifr = (struct ifreq *) data; 2446 struct ifaddr *ifa = (struct ifaddr *)data; 2447 int s, error = 0; 2448 struct mii_data *mii; 2449 2450 s = splimp(); 2451 2452 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 2453 splx(s); 2454 return (error); 2455 } 2456 2457 switch(command) { 2458 case SIOCSIFADDR: 2459 ifp->if_flags |= IFF_UP; 2460 switch (ifa->ifa_addr->sa_family) { 2461 #ifdef INET 2462 case AF_INET: 2463 bge_init(sc); 2464 arp_ifinit(&sc->arpcom, ifa); 2465 break; 2466 #endif /* INET */ 2467 default: 2468 bge_init(sc); 2469 break; 2470 } 2471 break; 2472 case SIOCSIFMTU: 2473 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2474 error = EINVAL; 2475 else 2476 ifp->if_mtu = ifr->ifr_mtu; 2477 break; 2478 case SIOCSIFFLAGS: 2479 if (ifp->if_flags & IFF_UP) { 2480 /* 2481 * If only the state of the PROMISC flag changed, 2482 * then just use the 'set promisc mode' command 2483 * instead of reinitializing the entire NIC. Doing 2484 * a full re-init means reloading the firmware and 2485 * waiting for it to start up, which may take a 2486 * second or two. 2487 */ 2488 if (ifp->if_flags & IFF_RUNNING && 2489 ifp->if_flags & IFF_PROMISC && 2490 !(sc->bge_if_flags & IFF_PROMISC)) { 2491 BGE_SETBIT(sc, BGE_RX_MODE, 2492 BGE_RXMODE_RX_PROMISC); 2493 } else if (ifp->if_flags & IFF_RUNNING && 2494 !(ifp->if_flags & IFF_PROMISC) && 2495 sc->bge_if_flags & IFF_PROMISC) { 2496 BGE_CLRBIT(sc, BGE_RX_MODE, 2497 BGE_RXMODE_RX_PROMISC); 2498 } else 2499 bge_init(sc); 2500 } else { 2501 if (ifp->if_flags & IFF_RUNNING) { 2502 bge_stop(sc); 2503 } 2504 } 2505 sc->bge_if_flags = ifp->if_flags; 2506 error = 0; 2507 break; 2508 case SIOCADDMULTI: 2509 case SIOCDELMULTI: 2510 if (ifp->if_flags & IFF_RUNNING) { 2511 bge_setmulti(sc); 2512 error = 0; 2513 } 2514 break; 2515 case SIOCSIFMEDIA: 2516 case SIOCGIFMEDIA: 2517 if (sc->bge_tbi) { 2518 error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia, 2519 command); 2520 } else { 2521 mii = &sc->bge_mii; 2522 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2523 command); 2524 } 2525 error = 0; 2526 break; 2527 default: 2528 error = EINVAL; 2529 break; 2530 } 2531 2532 splx(s); 2533 2534 return(error); 2535 } 2536 2537 void 2538 bge_watchdog(ifp) 2539 struct ifnet *ifp; 2540 { 2541 struct bge_softc *sc; 2542 2543 sc = ifp->if_softc; 2544 2545 printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname); 2546 2547 ifp->if_flags &= ~IFF_RUNNING; 2548 bge_init(sc); 2549 2550 ifp->if_oerrors++; 2551 } 2552 2553 /* 2554 * Stop the adapter and free any mbufs allocated to the 2555 * RX and TX lists. 2556 */ 2557 void 2558 bge_stop(sc) 2559 struct bge_softc *sc; 2560 { 2561 struct ifnet *ifp = &sc->arpcom.ac_if; 2562 struct ifmedia_entry *ifm; 2563 struct mii_data *mii; 2564 int mtmp, itmp; 2565 2566 timeout_del(&sc->bge_timeout); 2567 2568 /* 2569 * Disable all of the receiver blocks 2570 */ 2571 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2572 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2573 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2574 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2575 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2576 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2577 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2578 2579 /* 2580 * Disable all of the transmit blocks 2581 */ 2582 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2583 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2584 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2585 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2586 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2587 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2588 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2589 2590 /* 2591 * Shut down all of the memory managers and related 2592 * state machines. 2593 */ 2594 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2595 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2596 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2597 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2598 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2599 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2600 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2601 2602 /* Disable host interrupts. */ 2603 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2604 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2605 2606 /* 2607 * Tell firmware we're shutting down. 2608 */ 2609 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2610 2611 /* Free the RX lists. */ 2612 bge_free_rx_ring_std(sc); 2613 2614 /* Free jumbo RX list. */ 2615 bge_free_rx_ring_jumbo(sc); 2616 2617 /* Free TX buffers. */ 2618 bge_free_tx_ring(sc); 2619 2620 /* 2621 * Isolate/power down the PHY, but leave the media selection 2622 * unchanged so that things will be put back to normal when 2623 * we bring the interface back up. 2624 */ 2625 if (!sc->bge_tbi) { 2626 mii = &sc->bge_mii; 2627 itmp = ifp->if_flags; 2628 ifp->if_flags |= IFF_UP; 2629 ifm = mii->mii_media.ifm_cur; 2630 mtmp = ifm->ifm_media; 2631 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2632 mii_mediachg(mii); 2633 ifm->ifm_media = mtmp; 2634 ifp->if_flags = itmp; 2635 } 2636 2637 sc->bge_link = 0; 2638 2639 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2640 2641 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2642 } 2643 2644 /* 2645 * Stop all chip I/O so that the kernel's probe routines don't 2646 * get confused by errant DMAs when rebooting. 2647 */ 2648 void 2649 bge_shutdown(xsc) 2650 void *xsc; 2651 { 2652 struct bge_softc *sc = (struct bge_softc *)xsc; 2653 2654 bge_stop(sc); 2655 bge_reset(sc); 2656 } 2657 2658 struct cfattach bge_ca = { 2659 sizeof(struct bge_softc), bge_probe, bge_attach 2660 }; 2661 2662 struct cfdriver bge_cd = { 2663 0, "bge", DV_IFNET 2664 }; 2665