1 /* $OpenBSD: if_bgereg.h,v 1.104 2011/02/15 19:49:47 robert Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD: if_bgereg.h,v 1.11 2002/11/14 23:54:50 sam Exp $ 36 */ 37 38 /* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66 #define BGE_PAGE_ZERO 0x00000000 67 #define BGE_PAGE_ZERO_END 0x000000FF 68 #define BGE_SEND_RING_RCB 0x00000100 69 #define BGE_SEND_RING_RCB_END 0x000001FF 70 #define BGE_RX_RETURN_RING_RCB 0x00000200 71 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72 #define BGE_STATS_BLOCK 0x00000300 73 #define BGE_STATS_BLOCK_END 0x00000AFF 74 #define BGE_STATUS_BLOCK 0x00000B00 75 #define BGE_STATUS_BLOCK_END 0x00000B4F 76 #define BGE_SOFTWARE_GENCOMM 0x00000B50 77 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 78 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 79 #define BGE_SOFTWARE_GENCOMM_VER 0x00000B5C 80 #define BGE_VER_SHIFT 16 81 #define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 82 #define BGE_FW_PAUSE 0x00000002 83 #define BGE_SOFTWARE_GENCOMM_NICCFG2 0x00000D38 84 #define BGE_SOFTWARE_GENCOMM_NICCFG3 0x00000D3C 85 #define BGE_SOFTWARE_GENCOMM_NICCFG4 0x00000D60 86 #define BGE_NICCFG4_GMII_MODE 0x00000002 87 #define BGE_NICCFG4_RGMII_STD_IBND_DISABLE 0x00000004 88 #define BGE_NICCFG4_RGMII_EXT_IBND_RX_EN 0x00000008 89 #define BGE_NICCFG4_RGMII_EXT_IBND_TX_EN 0x00000010 90 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 91 #define BGE_UNMAPPED 0x00001000 92 #define BGE_UNMAPPED_END 0x00001FFF 93 #define BGE_DMA_DESCRIPTORS 0x00002000 94 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 95 #define BGE_SEND_RING_1_TO_4 0x00004000 96 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 97 98 /* Mappings for internal memory configuration */ 99 #define BGE_STD_RX_RINGS 0x00006000 100 #define BGE_STD_RX_RINGS_END 0x00006FFF 101 #define BGE_JUMBO_RX_RINGS 0x00007000 102 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 103 #define BGE_BUFFPOOL_1 0x00008000 104 #define BGE_BUFFPOOL_1_END 0x0000FFFF 105 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 106 #define BGE_BUFFPOOL_2_END 0x00017FFF 107 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 108 #define BGE_BUFFPOOL_3_END 0x0001FFFF 109 110 /* Mappings for external SSRAM configurations */ 111 #define BGE_SEND_RING_5_TO_6 0x00006000 112 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 113 #define BGE_SEND_RING_7_TO_8 0x00007000 114 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 115 #define BGE_SEND_RING_9_TO_16 0x00008000 116 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 117 #define BGE_EXT_STD_RX_RINGS 0x0000C000 118 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 119 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 120 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 121 #define BGE_MINI_RX_RINGS 0x0000E000 122 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 123 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 124 #define BGE_AVAIL_REGION1_END 0x00017FFF 125 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 126 #define BGE_AVAIL_REGION2_END 0x0001FFFF 127 #define BGE_EXT_SSRAM 0x00020000 128 #define BGE_EXT_SSRAM_END 0x000FFFFF 129 130 131 /* 132 * BCM570x register offsets. These are memory mapped registers 133 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 134 * Each register must be accessed using 32 bit operations. 135 * 136 * All registers are accessed through a 32K shared memory block. 137 * The first group of registers are actually copies of the PCI 138 * configuration space registers. 139 */ 140 141 /* 142 * PCI registers defined in the PCI 2.2 spec. 143 */ 144 #define BGE_PCI_VID 0x00 145 #define BGE_PCI_DID 0x02 146 #define BGE_PCI_CMD 0x04 147 #define BGE_PCI_STS 0x06 148 #define BGE_PCI_REV 0x08 149 #define BGE_PCI_CLASS 0x09 150 #define BGE_PCI_CACHESZ 0x0C 151 #define BGE_PCI_LATTIMER 0x0D 152 #define BGE_PCI_HDRTYPE 0x0E 153 #define BGE_PCI_BIST 0x0F 154 #define BGE_PCI_BAR0 0x10 155 #define BGE_PCI_BAR1 0x14 156 #define BGE_PCI_SUBSYS 0x2C 157 #define BGE_PCI_SUBVID 0x2E 158 #define BGE_PCI_ROMBASE 0x30 159 #define BGE_PCI_CAPPTR 0x34 160 #define BGE_PCI_INTLINE 0x3C 161 #define BGE_PCI_INTPIN 0x3D 162 #define BGE_PCI_MINGNT 0x3E 163 #define BGE_PCI_MAXLAT 0x3F 164 #define BGE_PCI_PCIXCAP 0x40 165 #define BGE_PCI_NEXTPTR_PM 0x41 166 #define BGE_PCI_PCIX_CMD 0x42 167 #define BGE_PCI_PCIX_STS 0x44 168 #define BGE_PCI_PWRMGMT_CAPID 0x48 169 #define BGE_PCI_NEXTPTR_VPD 0x49 170 #define BGE_PCI_PWRMGMT_CAPS 0x4A 171 #define BGE_PCI_PWRMGMT_CMD 0x4C 172 #define BGE_PCI_PWRMGMT_STS 0x4D 173 #define BGE_PCI_PWRMGMT_DATA 0x4F 174 #define BGE_PCI_VPD_CAPID 0x50 175 #define BGE_PCI_NEXTPTR_MSI 0x51 176 #define BGE_PCI_VPD_ADDR 0x52 177 #define BGE_PCI_VPD_DATA 0x54 178 #define BGE_PCI_MSI_CAPID 0x58 179 #define BGE_PCI_NEXTPTR_NONE 0x59 180 #define BGE_PCI_MSI_CTL 0x5A 181 #define BGE_PCI_MSI_ADDR_HI 0x5C 182 #define BGE_PCI_MSI_ADDR_LO 0x60 183 #define BGE_PCI_MSI_DATA 0x64 184 185 /* PCI MSI. ??? */ 186 #define BGE_PCIE_CAPID_REG 0xD0 187 #define BGE_PCIE_CAPID 0x10 188 189 /* 190 * PCI registers specific to the BCM570x family. 191 */ 192 #define BGE_PCI_MISC_CTL 0x68 193 #define BGE_PCI_DMA_RW_CTL 0x6C 194 #define BGE_PCI_PCISTATE 0x70 195 #define BGE_PCI_CLKCTL 0x74 196 #define BGE_PCI_REG_BASEADDR 0x78 197 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 198 #define BGE_PCI_REG_DATA 0x80 199 #define BGE_PCI_MEMWIN_DATA 0x84 200 #define BGE_PCI_MODECTL 0x88 201 #define BGE_PCI_MISC_CFG 0x8C 202 #define BGE_PCI_MISC_LOCALCTL 0x90 203 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 204 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 205 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 206 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 207 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 208 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 209 #define BGE_PCI_ISR_MBX_HI 0xB0 210 #define BGE_PCI_ISR_MBX_LO 0xB4 211 #define BGE_PCI_PRODID_ASICREV 0xBC 212 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 213 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 214 215 /* XXX: 216 * Used in PCI-Express code for 575x chips. 217 * Should be replaced with checking for a PCI config-space 218 * capability for PCI-Express, and PCI-Express standard 219 * offsets into that capability block. 220 */ 221 #define BGE_PCI_CONF_DEV_CTRL 0xD8 222 #define BGE_PCI_CONF_DEV_STUS 0xDA 223 224 /* PCI Misc. Host control register */ 225 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 226 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 227 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 228 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 229 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 230 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 231 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 232 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 233 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 234 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16 235 236 #if BYTE_ORDER == LITTLE_ENDIAN 237 #define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME| \ 239 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 240 #else 241 #define BGE_DMA_SWAP_OPTIONS \ 242 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 243 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 244 #endif 245 246 #define BGE_INIT \ 247 (BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 248 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 249 250 #define BGE_CHIPID_BCM5700_A0 0x7000 251 #define BGE_CHIPID_BCM5700_A1 0x7001 252 #define BGE_CHIPID_BCM5700_B0 0x7100 253 #define BGE_CHIPID_BCM5700_B1 0x7101 254 #define BGE_CHIPID_BCM5700_B2 0x7102 255 #define BGE_CHIPID_BCM5700_B3 0x7103 256 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104 257 #define BGE_CHIPID_BCM5700_C0 0x7200 258 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 259 #define BGE_CHIPID_BCM5701_B0 0x0100 260 #define BGE_CHIPID_BCM5701_B2 0x0102 261 #define BGE_CHIPID_BCM5701_B5 0x0105 262 #define BGE_CHIPID_BCM5703_A0 0x1000 263 #define BGE_CHIPID_BCM5703_A1 0x1001 264 #define BGE_CHIPID_BCM5703_A2 0x1002 265 #define BGE_CHIPID_BCM5703_A3 0x1003 266 #define BGE_CHIPID_BCM5703_B0 0x1100 267 #define BGE_CHIPID_BCM5704_A0 0x2000 268 #define BGE_CHIPID_BCM5704_A1 0x2001 269 #define BGE_CHIPID_BCM5704_A2 0x2002 270 #define BGE_CHIPID_BCM5704_A3 0x2003 271 #define BGE_CHIPID_BCM5704_B0 0x2100 272 #define BGE_CHIPID_BCM5705_A0 0x3000 273 #define BGE_CHIPID_BCM5705_A1 0x3001 274 #define BGE_CHIPID_BCM5705_A2 0x3002 275 #define BGE_CHIPID_BCM5705_A3 0x3003 276 #define BGE_CHIPID_BCM5750_A0 0x4000 277 #define BGE_CHIPID_BCM5750_A1 0x4001 278 #define BGE_CHIPID_BCM5750_A3 0x4003 279 #define BGE_CHIPID_BCM5750_B0 0x4010 280 #define BGE_CHIPID_BCM5750_B1 0x4101 281 #define BGE_CHIPID_BCM5750_C0 0x4200 282 #define BGE_CHIPID_BCM5750_C1 0x4201 283 #define BGE_CHIPID_BCM5750_C2 0x4202 284 #define BGE_CHIPID_BCM5714_A0 0x5000 285 #define BGE_CHIPID_BCM5761_A0 0x5761000 286 #define BGE_CHIPID_BCM5761_A1 0x5761100 287 #define BGE_CHIPID_BCM5784_A0 0x5784000 288 #define BGE_CHIPID_BCM5784_A1 0x5784100 289 #define BGE_CHIPID_BCM5752_A0 0x6000 290 #define BGE_CHIPID_BCM5752_A1 0x6001 291 #define BGE_CHIPID_BCM5752_A2 0x6002 292 #define BGE_CHIPID_BCM5714_B0 0x8000 293 #define BGE_CHIPID_BCM5714_B3 0x8003 294 #define BGE_CHIPID_BCM5715_A0 0x9000 295 #define BGE_CHIPID_BCM5715_A1 0x9001 296 #define BGE_CHIPID_BCM5715_A3 0x9003 297 #define BGE_CHIPID_BCM5755_A0 0xa000 298 #define BGE_CHIPID_BCM5755_A1 0xa001 299 #define BGE_CHIPID_BCM5755_A2 0xa002 300 #define BGE_CHIPID_BCM5755_C0 0xa200 301 #define BGE_CHIPID_BCM5787_A0 0xb000 302 #define BGE_CHIPID_BCM5787_A1 0xb001 303 #define BGE_CHIPID_BCM5787_A2 0xb002 304 #define BGE_CHIPID_BCM5906_A0 0xc000 305 #define BGE_CHIPID_BCM5906_A1 0xc001 306 #define BGE_CHIPID_BCM5906_A2 0xc002 307 #define BGE_CHIPID_BCM57780_A0 0x57780000 308 #define BGE_CHIPID_BCM57780_A1 0x57780001 309 310 /* shorthand one */ 311 #define BGE_ASICREV(x) ((x) >> 12) 312 #define BGE_ASICREV_BCM5700 0x07 313 #define BGE_ASICREV_BCM5701 0x00 314 #define BGE_ASICREV_BCM5703 0x01 315 #define BGE_ASICREV_BCM5704 0x02 316 #define BGE_ASICREV_BCM5705 0x03 317 #define BGE_ASICREV_BCM5750 0x04 318 #define BGE_ASICREV_BCM5714_A0 0x05 /* 5714, 5715 */ 319 #define BGE_ASICREV_BCM5752 0x06 320 #define BGE_ASICREV_BCM5780 0x08 321 #define BGE_ASICREV_BCM5714 0x09 /* 5714, 5715 */ 322 #define BGE_ASICREV_BCM5755 0x0a 323 #define BGE_ASICREV_BCM5787 0x0b 324 #define BGE_ASICREV_BCM5906 0x0c 325 #define BGE_ASICREV_USE_PRODID_REG 0x0f 326 #define BGE_ASICREV_BCM5761 0x5761 327 #define BGE_ASICREV_BCM5784 0x5784 328 #define BGE_ASICREV_BCM5785 0x5785 329 #define BGE_ASICREV_BCM57780 0x57780 330 #define BGE_ASICREV_BCM5717 0x5717 331 #define BGE_ASICREV_BCM57765 0x57785 332 333 /* chip revisions */ 334 #define BGE_CHIPREV(x) ((x) >> 8) 335 #define BGE_CHIPREV_5700_AX 0x70 336 #define BGE_CHIPREV_5700_BX 0x71 337 #define BGE_CHIPREV_5700_CX 0x72 338 #define BGE_CHIPREV_5701_AX 0x00 339 #define BGE_CHIPREV_5703_AX 0x10 340 #define BGE_CHIPREV_5704_AX 0x20 341 #define BGE_CHIPREV_5704_BX 0x21 342 #define BGE_CHIPREV_5750_AX 0x40 343 #define BGE_CHIPREV_5750_BX 0x41 344 #define BGE_CHIPREV_5761_AX 0x57611 345 #define BGE_CHIPREV_5784_AX 0x57841 346 347 /* PCI DMA Read/Write Control register */ 348 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 349 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 350 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 351 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 352 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 353 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 354 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 355 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 356 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 357 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 358 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 359 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 360 361 #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 362 #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 363 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 364 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 365 366 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 367 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 368 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 369 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 370 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 371 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 372 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 373 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 374 375 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 376 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 377 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 378 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 379 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 380 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 381 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 382 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 383 384 /* 385 * PCI state register -- note, this register is read only 386 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 387 * register is set. 388 */ 389 #define BGE_PCISTATE_FORCE_RESET 0x00000001 390 #define BGE_PCISTATE_INTR_NOT_ACTIVE 0x00000002 391 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 392 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 393 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 394 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 395 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 396 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 397 #define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 398 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 399 400 /* 401 * The following bits in PCI state register are reserved. 402 * If we check that the register values reverts on reset, 403 * do not check these bits. On some 5704C (rev A3) and some 404 * Altima chips, these bits do not revert until much later 405 * in the bge driver's bge_reset() chip-reset state machine. 406 */ 407 #define BGE_PCISTATE_RESERVED ((1 << 12) + (1 <<7)) 408 409 /* 410 * PCI Clock Control register -- note, this register is read only 411 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 412 * register is set. 413 */ 414 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 415 #define BGE_PCICLOCKCTL_M66EN 0x00000080 416 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 417 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 418 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 419 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 420 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 421 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 422 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 423 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 424 425 /* 426 * High priority mailbox registers 427 * Each mailbox is 64-bits wide, though we only use the 428 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 429 * first. The NIC will load the mailbox after the lower 32 bit word 430 * has been updated. 431 */ 432 #define BGE_MBX_IRQ0_HI 0x0200 433 #define BGE_MBX_IRQ0_LO 0x0204 434 #define BGE_MBX_IRQ1_HI 0x0208 435 #define BGE_MBX_IRQ1_LO 0x020C 436 #define BGE_MBX_IRQ2_HI 0x0210 437 #define BGE_MBX_IRQ2_LO 0x0214 438 #define BGE_MBX_IRQ3_HI 0x0218 439 #define BGE_MBX_IRQ3_LO 0x021C 440 #define BGE_MBX_GEN0_HI 0x0220 441 #define BGE_MBX_GEN0_LO 0x0224 442 #define BGE_MBX_GEN1_HI 0x0228 443 #define BGE_MBX_GEN1_LO 0x022C 444 #define BGE_MBX_GEN2_HI 0x0230 445 #define BGE_MBX_GEN2_LO 0x0234 446 #define BGE_MBX_GEN3_HI 0x0228 447 #define BGE_MBX_GEN3_LO 0x022C 448 #define BGE_MBX_GEN4_HI 0x0240 449 #define BGE_MBX_GEN4_LO 0x0244 450 #define BGE_MBX_GEN5_HI 0x0248 451 #define BGE_MBX_GEN5_LO 0x024C 452 #define BGE_MBX_GEN6_HI 0x0250 453 #define BGE_MBX_GEN6_LO 0x0254 454 #define BGE_MBX_GEN7_HI 0x0258 455 #define BGE_MBX_GEN7_LO 0x025C 456 #define BGE_MBX_RELOAD_STATS_HI 0x0260 457 #define BGE_MBX_RELOAD_STATS_LO 0x0264 458 #define BGE_MBX_RX_STD_PROD_HI 0x0268 459 #define BGE_MBX_RX_STD_PROD_LO 0x026C 460 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 461 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 462 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 463 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 464 #define BGE_MBX_RX_CONS0_HI 0x0280 465 #define BGE_MBX_RX_CONS0_LO 0x0284 466 #define BGE_MBX_RX_CONS1_HI 0x0288 467 #define BGE_MBX_RX_CONS1_LO 0x028C 468 #define BGE_MBX_RX_CONS2_HI 0x0290 469 #define BGE_MBX_RX_CONS2_LO 0x0294 470 #define BGE_MBX_RX_CONS3_HI 0x0298 471 #define BGE_MBX_RX_CONS3_LO 0x029C 472 #define BGE_MBX_RX_CONS4_HI 0x02A0 473 #define BGE_MBX_RX_CONS4_LO 0x02A4 474 #define BGE_MBX_RX_CONS5_HI 0x02A8 475 #define BGE_MBX_RX_CONS5_LO 0x02AC 476 #define BGE_MBX_RX_CONS6_HI 0x02B0 477 #define BGE_MBX_RX_CONS6_LO 0x02B4 478 #define BGE_MBX_RX_CONS7_HI 0x02B8 479 #define BGE_MBX_RX_CONS7_LO 0x02BC 480 #define BGE_MBX_RX_CONS8_HI 0x02C0 481 #define BGE_MBX_RX_CONS8_LO 0x02C4 482 #define BGE_MBX_RX_CONS9_HI 0x02C8 483 #define BGE_MBX_RX_CONS9_LO 0x02CC 484 #define BGE_MBX_RX_CONS10_HI 0x02D0 485 #define BGE_MBX_RX_CONS10_LO 0x02D4 486 #define BGE_MBX_RX_CONS11_HI 0x02D8 487 #define BGE_MBX_RX_CONS11_LO 0x02DC 488 #define BGE_MBX_RX_CONS12_HI 0x02E0 489 #define BGE_MBX_RX_CONS12_LO 0x02E4 490 #define BGE_MBX_RX_CONS13_HI 0x02E8 491 #define BGE_MBX_RX_CONS13_LO 0x02EC 492 #define BGE_MBX_RX_CONS14_HI 0x02F0 493 #define BGE_MBX_RX_CONS14_LO 0x02F4 494 #define BGE_MBX_RX_CONS15_HI 0x02F8 495 #define BGE_MBX_RX_CONS15_LO 0x02FC 496 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 497 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 498 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 499 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 500 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 501 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 502 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 503 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 504 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 505 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 506 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 507 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 508 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 509 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 510 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 511 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 512 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 513 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 514 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 515 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 516 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 517 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 518 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 519 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 520 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 521 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 522 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 523 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 524 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 525 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 526 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 527 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 528 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 529 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 530 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 531 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 532 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 533 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 534 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 535 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 536 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 537 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 538 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 539 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 540 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 541 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 542 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 543 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 544 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 545 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 546 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 547 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 548 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 549 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 550 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 551 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 552 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 553 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 554 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 555 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 556 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 557 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 558 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 559 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 560 561 #define BGE_TX_RINGS_MAX 4 562 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 563 #define BGE_RX_RINGS_MAX 16 564 565 /* Ethernet MAC control registers */ 566 #define BGE_MAC_MODE 0x0400 567 #define BGE_MAC_STS 0x0404 568 #define BGE_MAC_EVT_ENB 0x0408 569 #define BGE_MAC_LED_CTL 0x040C 570 #define BGE_MAC_ADDR1_LO 0x0410 571 #define BGE_MAC_ADDR1_HI 0x0414 572 #define BGE_MAC_ADDR2_LO 0x0418 573 #define BGE_MAC_ADDR2_HI 0x041C 574 #define BGE_MAC_ADDR3_LO 0x0420 575 #define BGE_MAC_ADDR3_HI 0x0424 576 #define BGE_MAC_ADDR4_LO 0x0428 577 #define BGE_MAC_ADDR4_HI 0x042C 578 #define BGE_WOL_PATPTR 0x0430 579 #define BGE_WOL_PATCFG 0x0434 580 #define BGE_TX_RANDOM_BACKOFF 0x0438 581 #define BGE_RX_MTU 0x043C 582 #define BGE_GBIT_PCS_TEST 0x0440 583 #define BGE_TX_TBI_AUTONEG 0x0444 584 #define BGE_RX_TBI_AUTONEG 0x0448 585 #define BGE_MI_COMM 0x044C 586 #define BGE_MI_STS 0x0450 587 #define BGE_MI_MODE 0x0454 588 #define BGE_AUTOPOLL_STS 0x0458 589 #define BGE_TX_MODE 0x045C 590 #define BGE_TX_STS 0x0460 591 #define BGE_TX_LENGTHS 0x0464 592 #define BGE_RX_MODE 0x0468 593 #define BGE_RX_STS 0x046C 594 #define BGE_MAR0 0x0470 595 #define BGE_MAR1 0x0474 596 #define BGE_MAR2 0x0478 597 #define BGE_MAR3 0x047C 598 #define BGE_RX_BD_RULES_CTL0 0x0480 599 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 600 #define BGE_RX_BD_RULES_CTL1 0x0488 601 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 602 #define BGE_RX_BD_RULES_CTL2 0x0490 603 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 604 #define BGE_RX_BD_RULES_CTL3 0x0498 605 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 606 #define BGE_RX_BD_RULES_CTL4 0x04A0 607 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 608 #define BGE_RX_BD_RULES_CTL5 0x04A8 609 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 610 #define BGE_RX_BD_RULES_CTL6 0x04B0 611 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 612 #define BGE_RX_BD_RULES_CTL7 0x04B8 613 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 614 #define BGE_RX_BD_RULES_CTL8 0x04C0 615 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 616 #define BGE_RX_BD_RULES_CTL9 0x04C8 617 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 618 #define BGE_RX_BD_RULES_CTL10 0x04D0 619 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 620 #define BGE_RX_BD_RULES_CTL11 0x04D8 621 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 622 #define BGE_RX_BD_RULES_CTL12 0x04E0 623 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 624 #define BGE_RX_BD_RULES_CTL13 0x04E8 625 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 626 #define BGE_RX_BD_RULES_CTL14 0x04F0 627 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 628 #define BGE_RX_BD_RULES_CTL15 0x04F8 629 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 630 #define BGE_RX_RULES_CFG 0x0500 631 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 632 #define BGE_SERDES_CFG 0x0590 633 #define BGE_SERDES_STS 0x0594 634 #define BGE_PHYCFG1 0x05A0 635 #define BGE_PHYCFG2 0x05A4 636 #define BGE_EXT_RGMII_MODE 0x05A8 637 #define BGE_SGDIG_CFG 0x05B0 638 #define BGE_SGDIG_STS 0x05B4 639 #define BGE_MAC_STATS 0x0800 640 641 /* Ethernet MAC Mode register */ 642 #define BGE_MACMODE_RESET 0x00000001 643 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 644 #define BGE_MACMODE_PORTMODE 0x0000000C 645 #define BGE_MACMODE_LOOPBACK 0x00000010 646 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 647 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 648 #define BGE_MACMODE_MAX_DEFER 0x00000200 649 #define BGE_MACMODE_LINK_POLARITY 0x00000400 650 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 651 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 652 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 653 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 654 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 655 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 656 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 657 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 658 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 659 #define BGE_MACMODE_MIP_ENB 0x00100000 660 #define BGE_MACMODE_TXDMA_ENB 0x00200000 661 #define BGE_MACMODE_RXDMA_ENB 0x00400000 662 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 663 664 #define BGE_PORTMODE_NONE 0x00000000 665 #define BGE_PORTMODE_MII 0x00000004 666 #define BGE_PORTMODE_GMII 0x00000008 667 #define BGE_PORTMODE_TBI 0x0000000C 668 669 /* MAC Status register */ 670 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 671 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 672 #define BGE_MACSTAT_RX_CFG 0x00000004 673 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 674 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 675 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 676 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 677 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 678 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 679 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 680 #define BGE_MACSTAT_ODI_ERROR 0x02000000 681 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 682 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 683 684 /* MAC Event Enable Register */ 685 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 686 #define BGE_EVTENB_LINK_CHANGED 0x00001000 687 #define BGE_EVTENB_MI_COMPLETE 0x00400000 688 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 689 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 690 #define BGE_EVTENB_ODI_ERROR 0x02000000 691 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 692 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 693 694 /* LED Control Register */ 695 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 696 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 697 #define BGE_LEDCTL_100MBPS_LED 0x00000004 698 #define BGE_LEDCTL_10MBPS_LED 0x00000008 699 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 700 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 701 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 702 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 703 #define BGE_LEDCTL_100MBPS_STS 0x00000100 704 #define BGE_LEDCTL_10MBPS_STS 0x00000200 705 #define BGE_LEDCTL_TRADLED_STS 0x00000400 706 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 707 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 708 709 /* TX backoff seed register */ 710 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 711 712 /* Autopoll status register */ 713 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 714 715 /* Transmit MAC mode register */ 716 #define BGE_TXMODE_RESET 0x00000001 717 #define BGE_TXMODE_ENABLE 0x00000002 718 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 719 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 720 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 721 722 /* Transmit MAC status register */ 723 #define BGE_TXSTAT_RX_XOFFED 0x00000001 724 #define BGE_TXSTAT_SENT_XOFF 0x00000002 725 #define BGE_TXSTAT_SENT_XON 0x00000004 726 #define BGE_TXSTAT_LINK_UP 0x00000008 727 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 728 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 729 730 /* Transmit MAC lengths register */ 731 #define BGE_TXLEN_SLOTTIME 0x000000FF 732 #define BGE_TXLEN_IPG 0x00000F00 733 #define BGE_TXLEN_CRS 0x00003000 734 735 /* Receive MAC mode register */ 736 #define BGE_RXMODE_RESET 0x00000001 737 #define BGE_RXMODE_ENABLE 0x00000002 738 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 739 #define BGE_RXMODE_RX_GIANTS 0x00000020 740 #define BGE_RXMODE_RX_RUNTS 0x00000040 741 #define BGE_RXMODE_8022_LENCHECK 0x00000080 742 #define BGE_RXMODE_RX_PROMISC 0x00000100 743 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 744 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 745 #define BGE_RXMODE_RX_IPV6_CSUM_ENABLE 0x01000000 746 747 /* Receive MAC status register */ 748 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 749 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 750 #define BGE_RXSTAT_RCVD_XON 0x00000004 751 752 /* Receive Rules Control register */ 753 #define BGE_RXRULECTL_OFFSET 0x000000FF 754 #define BGE_RXRULECTL_CLASS 0x00001F00 755 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 756 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 757 #define BGE_RXRULECTL_MAP 0x01000000 758 #define BGE_RXRULECTL_DISCARD 0x02000000 759 #define BGE_RXRULECTL_MASK 0x04000000 760 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 761 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 762 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 763 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 764 765 /* Receive Rules Mask register */ 766 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 767 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 768 769 /* SERDES configuration register */ 770 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 771 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 772 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 773 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 774 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 775 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 776 #define BGE_SERDESCFG_TXMODE 0x00001000 777 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 778 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 779 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 780 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 781 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 782 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 783 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125MHz clock */ 784 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 785 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 786 787 /* SERDES status register */ 788 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 789 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 790 791 /* PHYCFG1 config */ 792 #define BGE_PHYCFG1_RGMII_INT 0x00000001 793 #define BGE_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 794 #define BGE_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 795 #define BGE_PHYCFG1_TXC_DRV 0x20000000 796 797 /* PHYCFG2 config */ 798 #define BGE_PHYCFG2_INBAND_ENABLE 0x00000001 799 #define BGE_PHYCFG2_EMODE_MASK_MASK 0x000001c0 800 #define BGE_PHYCFG2_EMODE_MASK_AC131 0x000000c0 801 #define BGE_PHYCFG2_EMODE_MASK_50610 0x00000100 802 #define BGE_PHYCFG2_EMODE_MASK_RT8211 0x00000000 803 #define BGE_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 804 #define BGE_PHYCFG2_EMODE_COMP_MASK 0x00000e00 805 #define BGE_PHYCFG2_EMODE_COMP_AC131 0x00000600 806 #define BGE_PHYCFG2_EMODE_COMP_50610 0x00000400 807 #define BGE_PHYCFG2_EMODE_COMP_RT8211 0x00000800 808 #define BGE_PHYCFG2_EMODE_COMP_RT8201 0x00000000 809 #define BGE_PHYCFG2_FMODE_MASK_MASK 0x00007000 810 #define BGE_PHYCFG2_FMODE_MASK_AC131 0x00006000 811 #define BGE_PHYCFG2_FMODE_MASK_50610 0x00004000 812 #define BGE_PHYCFG2_FMODE_MASK_RT8211 0x00000000 813 #define BGE_PHYCFG2_FMODE_MASK_RT8201 0x00007000 814 #define BGE_PHYCFG2_FMODE_COMP_MASK 0x00038000 815 #define BGE_PHYCFG2_FMODE_COMP_AC131 0x00030000 816 #define BGE_PHYCFG2_FMODE_COMP_50610 0x00008000 817 #define BGE_PHYCFG2_FMODE_COMP_RT8211 0x00038000 818 #define BGE_PHYCFG2_FMODE_COMP_RT8201 0x00000000 819 #define BGE_PHYCFG2_GMODE_MASK_MASK 0x001c0000 820 #define BGE_PHYCFG2_GMODE_MASK_AC131 0x001c0000 821 #define BGE_PHYCFG2_GMODE_MASK_50610 0x00100000 822 #define BGE_PHYCFG2_GMODE_MASK_RT8211 0x00000000 823 #define BGE_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 824 #define BGE_PHYCFG2_GMODE_COMP_MASK 0x00e00000 825 #define BGE_PHYCFG2_GMODE_COMP_AC131 0x00e00000 826 #define BGE_PHYCFG2_GMODE_COMP_50610 0x00000000 827 #define BGE_PHYCFG2_GMODE_COMP_RT8211 0x00200000 828 #define BGE_PHYCFG2_GMODE_COMP_RT8201 0x00000000 829 #define BGE_PHYCFG2_ACT_MASK_MASK 0x03000000 830 #define BGE_PHYCFG2_ACT_MASK_AC131 0x03000000 831 #define BGE_PHYCFG2_ACT_MASK_50610 0x01000000 832 #define BGE_PHYCFG2_ACT_MASK_RT8211 0x03000000 833 #define BGE_PHYCFG2_ACT_MASK_RT8201 0x01000000 834 #define BGE_PHYCFG2_ACT_COMP_MASK 0x0c000000 835 #define BGE_PHYCFG2_ACT_COMP_AC131 0x00000000 836 #define BGE_PHYCFG2_ACT_COMP_50610 0x00000000 837 #define BGE_PHYCFG2_ACT_COMP_RT8211 0x00000000 838 #define BGE_PHYCFG2_ACT_COMP_RT8201 0x08000000 839 #define BGE_PHYCFG2_QUAL_MASK_MASK 0x30000000 840 #define BGE_PHYCFG2_QUAL_MASK_AC131 0x30000000 841 #define BGE_PHYCFG2_QUAL_MASK_50610 0x30000000 842 #define BGE_PHYCFG2_QUAL_MASK_RT8211 0x30000000 843 #define BGE_PHYCFG2_QUAL_MASK_RT8201 0x30000000 844 #define BGE_PHYCFG2_QUAL_COMP_MASK 0xc0000000 845 #define BGE_PHYCFG2_QUAL_COMP_AC131 0x00000000 846 #define BGE_PHYCFG2_QUAL_COMP_50610 0x00000000 847 #define BGE_PHYCFG2_QUAL_COMP_RT8211 0x00000000 848 #define BGE_PHYCFG2_QUAL_COMP_RT8201 0x00000000 849 #define BGE_PHYCFG2_50610_LED_MODES \ 850 (BGE_PHYCFG2_EMODE_MASK_50610 | \ 851 BGE_PHYCFG2_EMODE_COMP_50610 | \ 852 BGE_PHYCFG2_FMODE_MASK_50610 | \ 853 BGE_PHYCFG2_FMODE_COMP_50610 | \ 854 BGE_PHYCFG2_GMODE_MASK_50610 | \ 855 BGE_PHYCFG2_GMODE_COMP_50610 | \ 856 BGE_PHYCFG2_ACT_MASK_50610 | \ 857 BGE_PHYCFG2_ACT_COMP_50610 | \ 858 BGE_PHYCFG2_QUAL_MASK_50610 | \ 859 BGE_PHYCFG2_QUAL_COMP_50610) 860 #define BGE_PHYCFG2_AC131_LED_MODES \ 861 (BGE_PHYCFG2_EMODE_MASK_AC131 | \ 862 BGE_PHYCFG2_EMODE_COMP_AC131 | \ 863 BGE_PHYCFG2_FMODE_MASK_AC131 | \ 864 BGE_PHYCFG2_FMODE_COMP_AC131 | \ 865 BGE_PHYCFG2_GMODE_MASK_AC131 | \ 866 BGE_PHYCFG2_GMODE_COMP_AC131 | \ 867 BGE_PHYCFG2_ACT_MASK_AC131 | \ 868 BGE_PHYCFG2_ACT_COMP_AC131 | \ 869 BGE_PHYCFG2_QUAL_MASK_AC131 | \ 870 BGE_PHYCFG2_QUAL_COMP_AC131) 871 #define BGE_PHYCFG2_RTL8211C_LED_MODES \ 872 (BGE_PHYCFG2_EMODE_MASK_RT8211 | \ 873 BGE_PHYCFG2_EMODE_COMP_RT8211 | \ 874 BGE_PHYCFG2_FMODE_MASK_RT8211 | \ 875 BGE_PHYCFG2_FMODE_COMP_RT8211 | \ 876 BGE_PHYCFG2_GMODE_MASK_RT8211 | \ 877 BGE_PHYCFG2_GMODE_COMP_RT8211 | \ 878 BGE_PHYCFG2_ACT_MASK_RT8211 | \ 879 BGE_PHYCFG2_ACT_COMP_RT8211 | \ 880 BGE_PHYCFG2_QUAL_MASK_RT8211 | \ 881 BGE_PHYCFG2_QUAL_COMP_RT8211) 882 #define BGE_PHYCFG2_RTL8201E_LED_MODES \ 883 (BGE_PHYCFG2_EMODE_MASK_RT8201 | \ 884 BGE_PHYCFG2_EMODE_COMP_RT8201 | \ 885 BGE_PHYCFG2_FMODE_MASK_RT8201 | \ 886 BGE_PHYCFG2_FMODE_COMP_RT8201 | \ 887 BGE_PHYCFG2_GMODE_MASK_RT8201 | \ 888 BGE_PHYCFG2_GMODE_COMP_RT8201 | \ 889 BGE_PHYCFG2_ACT_MASK_RT8201 | \ 890 BGE_PHYCFG2_ACT_COMP_RT8201 | \ 891 BGE_PHYCFG2_QUAL_MASK_RT8201 | \ 892 BGE_PHYCFG2_QUAL_COMP_RT8201) 893 894 /* EXT_RGMII_MODE config */ 895 #define BGE_RGMII_MODE_TX_ENABLE 0x00000001 896 #define BGE_RGMII_MODE_TX_LOWPWR 0x00000002 897 #define BGE_RGMII_MODE_TX_RESET 0x00000004 898 #define BGE_RGMII_MODE_RX_INT_B 0x00000100 899 #define BGE_RGMII_MODE_RX_QUALITY 0x00000200 900 #define BGE_RGMII_MODE_RX_ACTIVITY 0x00000400 901 #define BGE_RGMII_MODE_RX_ENG_DET 0x00000800 902 903 /* SGDIG config (not documented) */ 904 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 905 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 906 #define BGE_SGDIGCFG_SEND 0x40000000 907 #define BGE_SGDIGCFG_AUTO 0x80000000 908 909 /* SGDIG status (not documented) */ 910 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 911 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 912 #define BGE_SGDIGSTS_DONE 0x00000002 913 914 /* MI communication register */ 915 #define BGE_MICOMM_DATA 0x0000FFFF 916 #define BGE_MICOMM_REG 0x001F0000 917 #define BGE_MICOMM_PHY 0x03E00000 918 #define BGE_MICOMM_CMD 0x0C000000 919 #define BGE_MICOMM_READFAIL 0x10000000 920 #define BGE_MICOMM_BUSY 0x20000000 921 922 #define BGE_MIREG(x) ((x & 0x1F) << 16) 923 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 924 #define BGE_MICMD_WRITE 0x04000000 925 #define BGE_MICMD_READ 0x08000000 926 927 /* MI status register */ 928 #define BGE_MISTS_LINK 0x00000001 929 #define BGE_MISTS_10MBPS 0x00000002 930 931 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 932 #define BGE_MIMODE_AUTOPOLL 0x00000010 933 #define BGE_MIMODE_500KHZ_CONST 0x00008000 934 #define BGE_MIMODE_CLKCNT 0x001F0000 935 #define BGE_MIMODE_BASE 0x000C0000 936 937 /* 938 * Send data initiator control registers. 939 */ 940 #define BGE_SDI_MODE 0x0C00 941 #define BGE_SDI_STATUS 0x0C04 942 #define BGE_SDI_STATS_CTL 0x0C08 943 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 944 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 945 #define BGE_ISO_PKT_TX 0x0C20 946 #define BGE_LOCSTATS_COS0 0x0C80 947 #define BGE_LOCSTATS_COS1 0x0C84 948 #define BGE_LOCSTATS_COS2 0x0C88 949 #define BGE_LOCSTATS_COS3 0x0C8C 950 #define BGE_LOCSTATS_COS4 0x0C90 951 #define BGE_LOCSTATS_COS5 0x0C84 952 #define BGE_LOCSTATS_COS6 0x0C98 953 #define BGE_LOCSTATS_COS7 0x0C9C 954 #define BGE_LOCSTATS_COS8 0x0CA0 955 #define BGE_LOCSTATS_COS9 0x0CA4 956 #define BGE_LOCSTATS_COS10 0x0CA8 957 #define BGE_LOCSTATS_COS11 0x0CAC 958 #define BGE_LOCSTATS_COS12 0x0CB0 959 #define BGE_LOCSTATS_COS13 0x0CB4 960 #define BGE_LOCSTATS_COS14 0x0CB8 961 #define BGE_LOCSTATS_COS15 0x0CBC 962 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 963 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 964 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 965 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 966 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 967 #define BGE_LOCSTATS_IRQS 0x0CD4 968 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 969 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 970 971 /* Send Data Initiator mode register */ 972 #define BGE_SDIMODE_RESET 0x00000001 973 #define BGE_SDIMODE_ENABLE 0x00000002 974 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 975 976 /* Send Data Initiator stats register */ 977 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 978 979 /* Send Data Initiator stats control register */ 980 #define BGE_SDISTATSCTL_ENABLE 0x00000001 981 #define BGE_SDISTATSCTL_FASTER 0x00000002 982 #define BGE_SDISTATSCTL_CLEAR 0x00000004 983 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 984 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 985 986 /* 987 * Send Data Completion Control registers 988 */ 989 #define BGE_SDC_MODE 0x1000 990 #define BGE_SDC_STATUS 0x1004 991 992 /* Send Data completion mode register */ 993 #define BGE_SDCMODE_RESET 0x00000001 994 #define BGE_SDCMODE_ENABLE 0x00000002 995 #define BGE_SDCMODE_ATTN 0x00000004 996 #define BGE_SDCMODE_CDELAY 0x00000010 997 998 /* Send Data completion status register */ 999 #define BGE_SDCSTAT_ATTN 0x00000004 1000 1001 /* 1002 * Send BD Ring Selector Control registers 1003 */ 1004 #define BGE_SRS_MODE 0x1400 1005 #define BGE_SRS_STATUS 0x1404 1006 #define BGE_SRS_HWDIAG 0x1408 1007 #define BGE_SRS_LOC_NIC_CONS0 0x1440 1008 #define BGE_SRS_LOC_NIC_CONS1 0x1444 1009 #define BGE_SRS_LOC_NIC_CONS2 0x1448 1010 #define BGE_SRS_LOC_NIC_CONS3 0x144C 1011 #define BGE_SRS_LOC_NIC_CONS4 0x1450 1012 #define BGE_SRS_LOC_NIC_CONS5 0x1454 1013 #define BGE_SRS_LOC_NIC_CONS6 0x1458 1014 #define BGE_SRS_LOC_NIC_CONS7 0x145C 1015 #define BGE_SRS_LOC_NIC_CONS8 0x1460 1016 #define BGE_SRS_LOC_NIC_CONS9 0x1464 1017 #define BGE_SRS_LOC_NIC_CONS10 0x1468 1018 #define BGE_SRS_LOC_NIC_CONS11 0x146C 1019 #define BGE_SRS_LOC_NIC_CONS12 0x1470 1020 #define BGE_SRS_LOC_NIC_CONS13 0x1474 1021 #define BGE_SRS_LOC_NIC_CONS14 0x1478 1022 #define BGE_SRS_LOC_NIC_CONS15 0x147C 1023 1024 /* Send BD Ring Selector Mode register */ 1025 #define BGE_SRSMODE_RESET 0x00000001 1026 #define BGE_SRSMODE_ENABLE 0x00000002 1027 #define BGE_SRSMODE_ATTN 0x00000004 1028 1029 /* Send BD Ring Selector Status register */ 1030 #define BGE_SRSSTAT_ERROR 0x00000004 1031 1032 /* Send BD Ring Selector HW Diagnostics register */ 1033 #define BGE_SRSHWDIAG_STATE 0x0000000F 1034 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1035 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1036 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1037 1038 /* 1039 * Send BD Initiator Selector Control registers 1040 */ 1041 #define BGE_SBDI_MODE 0x1800 1042 #define BGE_SBDI_STATUS 0x1804 1043 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 1044 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 1045 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 1046 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 1047 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 1048 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 1049 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 1050 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 1051 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 1052 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 1053 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 1054 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 1055 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 1056 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 1057 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 1058 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 1059 1060 /* Send BD Initiator Mode register */ 1061 #define BGE_SBDIMODE_RESET 0x00000001 1062 #define BGE_SBDIMODE_ENABLE 0x00000002 1063 #define BGE_SBDIMODE_ATTN 0x00000004 1064 1065 /* Send BD Initiator Status register */ 1066 #define BGE_SBDISTAT_ERROR 0x00000004 1067 1068 /* 1069 * Send BD Completion Control registers 1070 */ 1071 #define BGE_SBDC_MODE 0x1C00 1072 #define BGE_SBDC_STATUS 0x1C04 1073 1074 /* Send BD Completion Control Mode register */ 1075 #define BGE_SBDCMODE_RESET 0x00000001 1076 #define BGE_SBDCMODE_ENABLE 0x00000002 1077 #define BGE_SBDCMODE_ATTN 0x00000004 1078 1079 /* Send BD Completion Control Status register */ 1080 #define BGE_SBDCSTAT_ATTN 0x00000004 1081 1082 /* 1083 * Receive List Placement Control registers 1084 */ 1085 #define BGE_RXLP_MODE 0x2000 1086 #define BGE_RXLP_STATUS 0x2004 1087 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 1088 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1089 #define BGE_RXLP_CFG 0x2010 1090 #define BGE_RXLP_STATS_CTL 0x2014 1091 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1092 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1093 #define BGE_RXLP_HEAD0 0x2100 1094 #define BGE_RXLP_TAIL0 0x2104 1095 #define BGE_RXLP_COUNT0 0x2108 1096 #define BGE_RXLP_HEAD1 0x2110 1097 #define BGE_RXLP_TAIL1 0x2114 1098 #define BGE_RXLP_COUNT1 0x2118 1099 #define BGE_RXLP_HEAD2 0x2120 1100 #define BGE_RXLP_TAIL2 0x2124 1101 #define BGE_RXLP_COUNT2 0x2128 1102 #define BGE_RXLP_HEAD3 0x2130 1103 #define BGE_RXLP_TAIL3 0x2134 1104 #define BGE_RXLP_COUNT3 0x2138 1105 #define BGE_RXLP_HEAD4 0x2140 1106 #define BGE_RXLP_TAIL4 0x2144 1107 #define BGE_RXLP_COUNT4 0x2148 1108 #define BGE_RXLP_HEAD5 0x2150 1109 #define BGE_RXLP_TAIL5 0x2154 1110 #define BGE_RXLP_COUNT5 0x2158 1111 #define BGE_RXLP_HEAD6 0x2160 1112 #define BGE_RXLP_TAIL6 0x2164 1113 #define BGE_RXLP_COUNT6 0x2168 1114 #define BGE_RXLP_HEAD7 0x2170 1115 #define BGE_RXLP_TAIL7 0x2174 1116 #define BGE_RXLP_COUNT7 0x2178 1117 #define BGE_RXLP_HEAD8 0x2180 1118 #define BGE_RXLP_TAIL8 0x2184 1119 #define BGE_RXLP_COUNT8 0x2188 1120 #define BGE_RXLP_HEAD9 0x2190 1121 #define BGE_RXLP_TAIL9 0x2194 1122 #define BGE_RXLP_COUNT9 0x2198 1123 #define BGE_RXLP_HEAD10 0x21A0 1124 #define BGE_RXLP_TAIL10 0x21A4 1125 #define BGE_RXLP_COUNT10 0x21A8 1126 #define BGE_RXLP_HEAD11 0x21B0 1127 #define BGE_RXLP_TAIL11 0x21B4 1128 #define BGE_RXLP_COUNT11 0x21B8 1129 #define BGE_RXLP_HEAD12 0x21C0 1130 #define BGE_RXLP_TAIL12 0x21C4 1131 #define BGE_RXLP_COUNT12 0x21C8 1132 #define BGE_RXLP_HEAD13 0x21D0 1133 #define BGE_RXLP_TAIL13 0x21D4 1134 #define BGE_RXLP_COUNT13 0x21D8 1135 #define BGE_RXLP_HEAD14 0x21E0 1136 #define BGE_RXLP_TAIL14 0x21E4 1137 #define BGE_RXLP_COUNT14 0x21E8 1138 #define BGE_RXLP_HEAD15 0x21F0 1139 #define BGE_RXLP_TAIL15 0x21F4 1140 #define BGE_RXLP_COUNT15 0x21F8 1141 #define BGE_RXLP_LOCSTAT_COS0 0x2200 1142 #define BGE_RXLP_LOCSTAT_COS1 0x2204 1143 #define BGE_RXLP_LOCSTAT_COS2 0x2208 1144 #define BGE_RXLP_LOCSTAT_COS3 0x220C 1145 #define BGE_RXLP_LOCSTAT_COS4 0x2210 1146 #define BGE_RXLP_LOCSTAT_COS5 0x2214 1147 #define BGE_RXLP_LOCSTAT_COS6 0x2218 1148 #define BGE_RXLP_LOCSTAT_COS7 0x221C 1149 #define BGE_RXLP_LOCSTAT_COS8 0x2220 1150 #define BGE_RXLP_LOCSTAT_COS9 0x2224 1151 #define BGE_RXLP_LOCSTAT_COS10 0x2228 1152 #define BGE_RXLP_LOCSTAT_COS11 0x222C 1153 #define BGE_RXLP_LOCSTAT_COS12 0x2230 1154 #define BGE_RXLP_LOCSTAT_COS13 0x2234 1155 #define BGE_RXLP_LOCSTAT_COS14 0x2238 1156 #define BGE_RXLP_LOCSTAT_COS15 0x223C 1157 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1158 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1159 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1160 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1161 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1162 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1163 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1164 1165 1166 /* Receive List Placement mode register */ 1167 #define BGE_RXLPMODE_RESET 0x00000001 1168 #define BGE_RXLPMODE_ENABLE 0x00000002 1169 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1170 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1171 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1172 1173 /* Receive List Placement Status register */ 1174 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1175 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1176 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1177 1178 /* 1179 * Receive Data and Receive BD Initiator Control Registers 1180 */ 1181 #define BGE_RDBDI_MODE 0x2400 1182 #define BGE_RDBDI_STATUS 0x2404 1183 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1184 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1185 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1186 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1187 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1188 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1189 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1190 #define BGE_RX_STD_RCB_NICADDR 0x245C 1191 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1192 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1193 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1194 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1195 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1196 #define BGE_RDBDI_STD_RX_CONS 0x2474 1197 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1198 #define BGE_RDBDI_RETURN_PROD0 0x2480 1199 #define BGE_RDBDI_RETURN_PROD1 0x2484 1200 #define BGE_RDBDI_RETURN_PROD2 0x2488 1201 #define BGE_RDBDI_RETURN_PROD3 0x248C 1202 #define BGE_RDBDI_RETURN_PROD4 0x2490 1203 #define BGE_RDBDI_RETURN_PROD5 0x2494 1204 #define BGE_RDBDI_RETURN_PROD6 0x2498 1205 #define BGE_RDBDI_RETURN_PROD7 0x249C 1206 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1207 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1208 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1209 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1210 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1211 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1212 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1213 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1214 #define BGE_RDBDI_HWDIAG 0x24C0 1215 1216 1217 /* Receive Data and Receive BD Initiator Mode register */ 1218 #define BGE_RDBDIMODE_RESET 0x00000001 1219 #define BGE_RDBDIMODE_ENABLE 0x00000002 1220 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1221 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1222 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1223 1224 /* Receive Data and Receive BD Initiator Status register */ 1225 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1226 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1227 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1228 1229 1230 /* 1231 * Receive Data Completion Control registers 1232 */ 1233 #define BGE_RDC_MODE 0x2800 1234 1235 /* Receive Data Completion Mode register */ 1236 #define BGE_RDCMODE_RESET 0x00000001 1237 #define BGE_RDCMODE_ENABLE 0x00000002 1238 #define BGE_RDCMODE_ATTN 0x00000004 1239 1240 /* 1241 * Receive BD Initiator Control registers 1242 */ 1243 #define BGE_RBDI_MODE 0x2C00 1244 #define BGE_RBDI_STATUS 0x2C04 1245 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1246 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1247 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1248 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1249 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1250 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1251 1252 #define BGE_STD_REPL_LWM 0x2D00 1253 #define BGE_JUMBO_REPL_LWM 0x2D04 1254 1255 /* Receive BD Initiator Mode register */ 1256 #define BGE_RBDIMODE_RESET 0x00000001 1257 #define BGE_RBDIMODE_ENABLE 0x00000002 1258 #define BGE_RBDIMODE_ATTN 0x00000004 1259 1260 /* Receive BD Initiator Status register */ 1261 #define BGE_RBDISTAT_ATTN 0x00000004 1262 1263 /* 1264 * Receive BD Completion Control registers 1265 */ 1266 #define BGE_RBDC_MODE 0x3000 1267 #define BGE_RBDC_STATUS 0x3004 1268 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1269 #define BGE_RBDC_STD_BD_PROD 0x300C 1270 #define BGE_RBDC_MINI_BD_PROD 0x3010 1271 1272 /* Receive BD completion mode register */ 1273 #define BGE_RBDCMODE_RESET 0x00000001 1274 #define BGE_RBDCMODE_ENABLE 0x00000002 1275 #define BGE_RBDCMODE_ATTN 0x00000004 1276 1277 /* Receive BD completion status register */ 1278 #define BGE_RBDCSTAT_ERROR 0x00000004 1279 1280 /* 1281 * Receive List Selector Control registers 1282 */ 1283 #define BGE_RXLS_MODE 0x3400 1284 #define BGE_RXLS_STATUS 0x3404 1285 1286 /* Receive List Selector Mode register */ 1287 #define BGE_RXLSMODE_RESET 0x00000001 1288 #define BGE_RXLSMODE_ENABLE 0x00000002 1289 #define BGE_RXLSMODE_ATTN 0x00000004 1290 1291 /* Receive List Selector Status register */ 1292 #define BGE_RXLSSTAT_ERROR 0x00000004 1293 1294 /* 1295 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1296 */ 1297 #define BGE_MBCF_MODE 0x3800 1298 #define BGE_MBCF_STATUS 0x3804 1299 1300 /* Mbuf Cluster Free mode register */ 1301 #define BGE_MBCFMODE_RESET 0x00000001 1302 #define BGE_MBCFMODE_ENABLE 0x00000002 1303 #define BGE_MBCFMODE_ATTN 0x00000004 1304 1305 /* Mbuf Cluster Free status register */ 1306 #define BGE_MBCFSTAT_ERROR 0x00000004 1307 1308 /* 1309 * Host Coalescing Control registers 1310 */ 1311 #define BGE_HCC_MODE 0x3C00 1312 #define BGE_HCC_STATUS 0x3C04 1313 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1314 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1315 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1316 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1317 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1318 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1319 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1320 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1321 #define BGE_HCC_STATS_TICKS 0x3C28 1322 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1323 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1324 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1325 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1326 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1327 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1328 #define BGE_FLOW_ATTN 0x3C48 1329 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1330 #define BGE_HCC_STD_BD_CONS 0x3C54 1331 #define BGE_HCC_MINI_BD_CONS 0x3C58 1332 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1333 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1334 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1335 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1336 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1337 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1338 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1339 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1340 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1341 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1342 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1343 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1344 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1345 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1346 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1347 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1348 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1349 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1350 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1351 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1352 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1353 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1354 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1355 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1356 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1357 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1358 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1359 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1360 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1361 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1362 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1363 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1364 1365 1366 /* Host coalescing mode register */ 1367 #define BGE_HCCMODE_RESET 0x00000001 1368 #define BGE_HCCMODE_ENABLE 0x00000002 1369 #define BGE_HCCMODE_ATTN 0x00000004 1370 #define BGE_HCCMODE_COAL_NOW 0x00000008 1371 #define BGE_HCCMODE_MSI_BITS 0x00000070 1372 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1373 1374 #define BGE_STATBLKSZ_FULL 0x00000000 1375 #define BGE_STATBLKSZ_64BYTE 0x00000080 1376 #define BGE_STATBLKSZ_32BYTE 0x00000100 1377 1378 /* Host coalescing status register */ 1379 #define BGE_HCCSTAT_ERROR 0x00000004 1380 1381 /* Flow attention register */ 1382 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1383 #define BGE_FLOWATTN_MEMARB 0x00000080 1384 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1385 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1386 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1387 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1388 #define BGE_FLOWATTN_RDBDI 0x00080000 1389 #define BGE_FLOWATTN_RXLS 0x00100000 1390 #define BGE_FLOWATTN_RXLP 0x00200000 1391 #define BGE_FLOWATTN_RBDC 0x00400000 1392 #define BGE_FLOWATTN_RBDI 0x00800000 1393 #define BGE_FLOWATTN_SDC 0x08000000 1394 #define BGE_FLOWATTN_SDI 0x10000000 1395 #define BGE_FLOWATTN_SRS 0x20000000 1396 #define BGE_FLOWATTN_SBDC 0x40000000 1397 #define BGE_FLOWATTN_SBDI 0x80000000 1398 1399 /* 1400 * Memory arbiter registers 1401 */ 1402 #define BGE_MARB_MODE 0x4000 1403 #define BGE_MARB_STATUS 0x4004 1404 #define BGE_MARB_TRAPADDR_HI 0x4008 1405 #define BGE_MARB_TRAPADDR_LO 0x400C 1406 1407 /* Memory arbiter mode register */ 1408 #define BGE_MARBMODE_RESET 0x00000001 1409 #define BGE_MARBMODE_ENABLE 0x00000002 1410 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1411 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1412 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1413 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1414 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1415 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1416 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1417 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1418 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1419 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1420 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1421 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1422 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1423 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1424 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1425 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1426 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1427 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1428 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1429 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1430 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1431 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1432 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1433 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1434 1435 /* Memory arbiter status register */ 1436 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1437 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1438 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1439 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1440 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1441 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1442 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1443 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1444 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1445 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1446 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1447 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1448 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1449 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1450 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1451 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1452 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1453 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1454 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1455 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1456 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1457 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1458 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1459 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1460 1461 /* 1462 * Buffer manager control registers 1463 */ 1464 #define BGE_BMAN_MODE 0x4400 1465 #define BGE_BMAN_STATUS 0x4404 1466 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1467 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1468 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1469 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1470 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1471 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1472 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1473 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1474 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1475 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1476 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1477 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1478 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1479 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1480 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1481 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1482 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1483 #define BGE_BMAN_HWDIAG_1 0x444C 1484 #define BGE_BMAN_HWDIAG_2 0x4450 1485 #define BGE_BMAN_HWDIAG_3 0x4454 1486 1487 /* Buffer manager mode register */ 1488 #define BGE_BMANMODE_RESET 0x00000001 1489 #define BGE_BMANMODE_ENABLE 0x00000002 1490 #define BGE_BMANMODE_ATTN 0x00000004 1491 #define BGE_BMANMODE_TESTMODE 0x00000008 1492 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1493 1494 /* Buffer manager status register */ 1495 #define BGE_BMANSTAT_ERRO 0x00000004 1496 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1497 1498 1499 /* 1500 * Read DMA Control registers 1501 */ 1502 #define BGE_RDMA_MODE 0x4800 1503 #define BGE_RDMA_STATUS 0x4804 1504 1505 /* Read DMA mode register */ 1506 #define BGE_RDMAMODE_RESET 0x00000001 1507 #define BGE_RDMAMODE_ENABLE 0x00000002 1508 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1509 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1510 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1511 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1512 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1513 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1514 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1515 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1516 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1517 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1518 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1519 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1520 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1521 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1522 #define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1523 1524 /* Read DMA status register */ 1525 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1526 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1527 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1528 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1529 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1530 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1531 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1532 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1533 1534 /* 1535 * Write DMA control registers 1536 */ 1537 #define BGE_WDMA_MODE 0x4C00 1538 #define BGE_WDMA_STATUS 0x4C04 1539 1540 /* Write DMA mode register */ 1541 #define BGE_WDMAMODE_RESET 0x00000001 1542 #define BGE_WDMAMODE_ENABLE 0x00000002 1543 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1544 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1545 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1546 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1547 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1548 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1549 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1550 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1551 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1552 #define BGE_WDMAMODE_RX_ACCEL 0x00000400 1553 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1554 #define BGE_WDMAMODE_BURST_ALL_DATA 0xc0000000 1555 1556 /* Write DMA status register */ 1557 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1558 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1559 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1560 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1561 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1562 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1563 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1564 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1565 1566 1567 /* 1568 * RX CPU registers 1569 */ 1570 #define BGE_RXCPU_MODE 0x5000 1571 #define BGE_RXCPU_STATUS 0x5004 1572 #define BGE_RXCPU_PC 0x501C 1573 1574 /* RX CPU mode register */ 1575 #define BGE_RXCPUMODE_RESET 0x00000001 1576 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1577 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1578 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1579 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1580 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1581 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1582 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1583 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1584 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1585 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1586 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1587 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1588 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1589 1590 /* RX CPU status register */ 1591 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1592 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1593 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1594 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1595 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1596 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1597 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1598 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1599 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1600 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1601 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1602 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1603 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1604 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1605 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1606 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1607 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1608 1609 1610 /* 1611 * V? CPU registers 1612 */ 1613 #define BGE_VCPU_STATUS 0x5100 1614 #define BGE_VCPU_EXT_CTRL 0x6890 1615 1616 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1617 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1618 1619 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1620 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1621 1622 1623 /* 1624 * TX CPU registers 1625 */ 1626 #define BGE_TXCPU_MODE 0x5400 1627 #define BGE_TXCPU_STATUS 0x5404 1628 #define BGE_TXCPU_PC 0x541C 1629 1630 /* TX CPU mode register */ 1631 #define BGE_TXCPUMODE_RESET 0x00000001 1632 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1633 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1634 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1635 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1636 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1637 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1638 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1639 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1640 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1641 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1642 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1643 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1644 1645 /* TX CPU status register */ 1646 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1647 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1648 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1649 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1650 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1651 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1652 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1653 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1654 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1655 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1656 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1657 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1658 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1659 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1660 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1661 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1662 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1663 1664 1665 /* 1666 * Low priority mailbox registers 1667 */ 1668 #define BGE_LPMBX_IRQ0_HI 0x5800 1669 #define BGE_LPMBX_IRQ0_LO 0x5804 1670 #define BGE_LPMBX_IRQ1_HI 0x5808 1671 #define BGE_LPMBX_IRQ1_LO 0x580C 1672 #define BGE_LPMBX_IRQ2_HI 0x5810 1673 #define BGE_LPMBX_IRQ2_LO 0x5814 1674 #define BGE_LPMBX_IRQ3_HI 0x5818 1675 #define BGE_LPMBX_IRQ3_LO 0x581C 1676 #define BGE_LPMBX_GEN0_HI 0x5820 1677 #define BGE_LPMBX_GEN0_LO 0x5824 1678 #define BGE_LPMBX_GEN1_HI 0x5828 1679 #define BGE_LPMBX_GEN1_LO 0x582C 1680 #define BGE_LPMBX_GEN2_HI 0x5830 1681 #define BGE_LPMBX_GEN2_LO 0x5834 1682 #define BGE_LPMBX_GEN3_HI 0x5828 1683 #define BGE_LPMBX_GEN3_LO 0x582C 1684 #define BGE_LPMBX_GEN4_HI 0x5840 1685 #define BGE_LPMBX_GEN4_LO 0x5844 1686 #define BGE_LPMBX_GEN5_HI 0x5848 1687 #define BGE_LPMBX_GEN5_LO 0x584C 1688 #define BGE_LPMBX_GEN6_HI 0x5850 1689 #define BGE_LPMBX_GEN6_LO 0x5854 1690 #define BGE_LPMBX_GEN7_HI 0x5858 1691 #define BGE_LPMBX_GEN7_LO 0x585C 1692 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1693 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1694 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1695 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1696 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1697 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1698 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1699 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1700 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1701 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1702 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1703 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1704 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1705 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1706 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1707 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1708 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1709 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1710 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1711 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1712 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1713 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1714 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1715 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1716 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1717 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1718 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1719 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1720 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1721 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1722 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1723 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1724 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1725 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1726 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1727 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1728 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1729 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1730 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1731 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1732 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1733 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1734 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1735 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1736 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1737 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1738 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1739 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1740 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1741 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1742 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1743 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1744 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1745 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1746 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1747 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1748 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1749 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1750 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1751 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1752 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1753 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1754 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1755 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1756 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1757 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1758 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1759 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1760 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1761 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1762 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1763 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1764 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1765 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1766 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1767 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1768 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1769 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1770 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1771 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1772 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1773 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1774 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1775 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1776 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1777 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1778 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1779 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1780 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1781 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1782 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1783 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1784 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1785 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1786 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1787 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1788 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1789 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1790 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1791 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1792 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1793 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1794 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1795 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1796 1797 /* 1798 * Flow throw Queue reset register 1799 */ 1800 #define BGE_FTQ_RESET 0x5C00 1801 1802 #define BGE_FTQRESET_DMAREAD 0x00000002 1803 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1804 #define BGE_FTQRESET_DMADONE 0x00000010 1805 #define BGE_FTQRESET_SBDC 0x00000020 1806 #define BGE_FTQRESET_SDI 0x00000040 1807 #define BGE_FTQRESET_WDMA 0x00000080 1808 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1809 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1810 #define BGE_FTQRESET_SDC 0x00000400 1811 #define BGE_FTQRESET_HCC 0x00000800 1812 #define BGE_FTQRESET_TXFIFO 0x00001000 1813 #define BGE_FTQRESET_MBC 0x00002000 1814 #define BGE_FTQRESET_RBDC 0x00004000 1815 #define BGE_FTQRESET_RXLP 0x00008000 1816 #define BGE_FTQRESET_RDBDI 0x00010000 1817 #define BGE_FTQRESET_RDC 0x00020000 1818 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1819 1820 /* 1821 * Message Signaled Interrupt registers 1822 */ 1823 #define BGE_MSI_MODE 0x6000 1824 #define BGE_MSI_STATUS 0x6004 1825 #define BGE_MSI_FIFOACCESS 0x6008 1826 1827 /* MSI mode register */ 1828 #define BGE_MSIMODE_RESET 0x00000001 1829 #define BGE_MSIMODE_ENABLE 0x00000002 1830 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1831 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1832 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1833 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1834 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1835 1836 /* MSI status register */ 1837 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1838 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1839 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1840 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1841 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1842 1843 1844 /* 1845 * DMA Completion registers 1846 */ 1847 #define BGE_DMAC_MODE 0x6400 1848 1849 /* DMA Completion mode register */ 1850 #define BGE_DMACMODE_RESET 0x00000001 1851 #define BGE_DMACMODE_ENABLE 0x00000002 1852 1853 1854 /* 1855 * General control registers. 1856 */ 1857 #define BGE_MODE_CTL 0x6800 1858 #define BGE_MISC_CFG 0x6804 1859 #define BGE_MISC_LOCAL_CTL 0x6808 1860 #define BGE_CPU_EVENT 0x6810 1861 #define BGE_EE_ADDR 0x6838 1862 #define BGE_EE_DATA 0x683C 1863 #define BGE_EE_CTL 0x6840 1864 #define BGE_MDI_CTL 0x6844 1865 #define BGE_EE_DELAY 0x6848 1866 1867 #define BGE_FASTBOOT_PC 0x6894 1868 1869 /* 1870 * NVRAM Control registers 1871 */ 1872 1873 #define BGE_NVRAM_CMD 0x7000 1874 #define BGE_NVRAM_STAT 0x7004 1875 #define BGE_NVRAM_WRDATA 0x7008 1876 #define BGE_NVRAM_ADDR 0x700c 1877 #define BGE_NVRAM_RDDATA 0x7010 1878 #define BGE_NVRAM_CFG1 0x7014 1879 #define BGE_NVRAM_CFG2 0x7018 1880 #define BGE_NVRAM_CFG3 0x701c 1881 #define BGE_NVRAM_SWARB 0x7020 1882 #define BGE_NVRAM_ACCESS 0x7024 1883 #define BGE_NVRAM_WRITE1 0x7028 1884 1885 1886 #define BGE_NVRAMCMD_RESET 0x00000001 1887 #define BGE_NVRAMCMD_DONE 0x00000008 1888 #define BGE_NVRAMCMD_START 0x00000010 1889 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1890 #define BGE_NVRAMCMD_ERASE 0x00000040 1891 #define BGE_NVRAMCMD_FIRST 0x00000080 1892 #define BGE_NVRAMCMD_LAST 0x00000100 1893 1894 #define BGE_NVRAM_READCMD \ 1895 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1896 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1897 #define BGE_NVRAM_WRITECMD \ 1898 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1899 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1900 1901 #define BGE_NVRAMSWARB_SET0 0x00000001 1902 #define BGE_NVRAMSWARB_SET1 0x00000002 1903 #define BGE_NVRAMSWARB_SET2 0x00000003 1904 #define BGE_NVRAMSWARB_SET3 0x00000004 1905 #define BGE_NVRAMSWARB_CLR0 0x00000010 1906 #define BGE_NVRAMSWARB_CLR1 0x00000020 1907 #define BGE_NVRAMSWARB_CLR2 0x00000040 1908 #define BGE_NVRAMSWARB_CLR3 0x00000080 1909 #define BGE_NVRAMSWARB_GNT0 0x00000100 1910 #define BGE_NVRAMSWARB_GNT1 0x00000200 1911 #define BGE_NVRAMSWARB_GNT2 0x00000400 1912 #define BGE_NVRAMSWARB_GNT3 0x00000800 1913 #define BGE_NVRAMSWARB_REQ0 0x00001000 1914 #define BGE_NVRAMSWARB_REQ1 0x00002000 1915 #define BGE_NVRAMSWARB_REQ2 0x00004000 1916 #define BGE_NVRAMSWARB_REQ3 0x00008000 1917 1918 #define BGE_NVRAMACC_ENABLE 0x00000001 1919 #define BGE_NVRAMACC_WRENABLE 0x00000002 1920 1921 /* 1922 * TLP Control Register 1923 * Applicable to BCM5721 and BCM5751 only 1924 */ 1925 #define BGE_TLP_CONTROL_REG 0x7c00 1926 #define BGE_TLP_DATA_FIFO_PROTECT 0x02000000 1927 1928 /* 1929 * PHY Test Control Register 1930 * Applicable to BCM5721 and BCM5751 only 1931 */ 1932 #define BGE_PHY_TEST_CTRL_REG 0x7e2c 1933 #define BGE_PHY_PCIE_SCRAM_MODE 0x0020 1934 #define BGE_PHY_PCIE_LTASS_MODE 0x0040 1935 1936 /* Mode control register */ 1937 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1938 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1939 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1940 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1941 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1942 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1943 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1944 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1945 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1946 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1947 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1948 #define BGE_MODECTL_STACKUP 0x00010000 1949 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1950 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1951 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1952 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1953 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1954 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1955 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1956 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1957 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1958 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1959 1960 /* Misc. config register */ 1961 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1962 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1963 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1964 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1965 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000 1966 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1967 #define BGE_MISCCFG_KEEP_GPHY_POWER 0x04000000 1968 1969 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1970 1971 /* Misc. Local Control */ 1972 #define BGE_MLC_INTR_STATE 0x00000001 1973 #define BGE_MLC_INTR_CLR 0x00000002 1974 #define BGE_MLC_INTR_SET 0x00000004 1975 #define BGE_MLC_INTR_ONATTN 0x00000008 1976 #define BGE_MLC_MISCIO_IN0 0x00000100 1977 #define BGE_MLC_MISCIO_IN1 0x00000200 1978 #define BGE_MLC_MISCIO_IN2 0x00000400 1979 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1980 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1981 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1982 #define BGE_MLC_MISCIO_OUT0 0x00004000 1983 #define BGE_MLC_MISCIO_OUT1 0x00008000 1984 #define BGE_MLC_MISCIO_OUT2 0x00010000 1985 #define BGE_MLC_EXTRAM_ENB 0x00020000 1986 #define BGE_MLC_SRAM_SIZE 0x001C0000 1987 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1988 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1989 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1990 #define BGE_MLC_AUTO_EEPROM 0x01000000 1991 1992 #define BGE_SSRAMSIZE_256KB 0x00000000 1993 #define BGE_SSRAMSIZE_512KB 0x00040000 1994 #define BGE_SSRAMSIZE_1MB 0x00080000 1995 #define BGE_SSRAMSIZE_2MB 0x000C0000 1996 #define BGE_SSRAMSIZE_4MB 0x00100000 1997 #define BGE_SSRAMSIZE_8MB 0x00140000 1998 #define BGE_SSRAMSIZE_16M 0x00180000 1999 2000 /* EEPROM address register */ 2001 #define BGE_EEADDR_ADDRESS 0x0000FFFC 2002 #define BGE_EEADDR_HALFCLK 0x01FF0000 2003 #define BGE_EEADDR_START 0x02000000 2004 #define BGE_EEADDR_DEVID 0x1C000000 2005 #define BGE_EEADDR_RESET 0x20000000 2006 #define BGE_EEADDR_DONE 0x40000000 2007 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2008 2009 #define BGE_EEDEVID(x) ((x & 7) << 26) 2010 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2011 #define BGE_HALFCLK_384SCL 0x60 2012 #define BGE_EE_READCMD \ 2013 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2014 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2015 #define BGE_EE_WRCMD \ 2016 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2017 BGE_EEADDR_START|BGE_EEADDR_DONE) 2018 2019 /* EEPROM Control register */ 2020 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2021 #define BGE_EECTL_CLKOUT 0x00000002 2022 #define BGE_EECTL_CLKIN 0x00000004 2023 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2024 #define BGE_EECTL_DATAOUT 0x00000010 2025 #define BGE_EECTL_DATAIN 0x00000020 2026 2027 /* MDI (MII/GMII) access register */ 2028 #define BGE_MDI_DATA 0x00000001 2029 #define BGE_MDI_DIR 0x00000002 2030 #define BGE_MDI_SEL 0x00000004 2031 #define BGE_MDI_CLK 0x00000008 2032 2033 #define BGE_MEMWIN_START 0x00008000 2034 #define BGE_MEMWIN_END 0x0000FFFF 2035 2036 2037 #define BGE_MEMWIN_READ(pc, tag, x, val) \ 2038 do { \ 2039 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2040 (0xFFFF0000 & x)); \ 2041 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2042 } while(0) 2043 2044 #define BGE_MEMWIN_WRITE(pc, tag, x, val) \ 2045 do { \ 2046 pci_conf_write(pc, tag, BGE_PCI_MEMWIN_BASEADDR, \ 2047 (0xFFFF0000 & x)); \ 2048 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2049 } while(0) 2050 2051 /* 2052 * This magic number is written to the firmware mailbox at 0xb50 2053 * before a software reset is issued. After the internal firmware 2054 * has completed its initialization it will write the opposite of 2055 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 2056 * driver to synchronize with the firmware. 2057 */ 2058 #define BGE_MAGIC_NUMBER 0x4B657654 2059 2060 typedef struct { 2061 u_int32_t bge_addr_hi; 2062 u_int32_t bge_addr_lo; 2063 } bge_hostaddr; 2064 #define BGE_HOSTADDR(x,y) \ 2065 do { \ 2066 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 2067 if (sizeof(bus_addr_t) == 8) \ 2068 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 2069 else \ 2070 (x).bge_addr_hi = 0; \ 2071 } while(0) 2072 2073 /* Ring control block structure */ 2074 struct bge_rcb { 2075 bge_hostaddr bge_hostaddr; 2076 u_int32_t bge_maxlen_flags; 2077 u_int32_t bge_nicaddr; 2078 }; 2079 2080 #define RCB_WRITE_4(sc, rcb, offset, val) \ 2081 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 2082 rcb + offsetof(struct bge_rcb, offset), val) 2083 2084 #define RCB_WRITE_2(sc, rcb, offset, val) \ 2085 bus_space_write_2(sc->bge_btag, sc->bge_bhandle, \ 2086 rcb + offsetof(struct bge_rcb, offset), val) 2087 2088 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2089 2090 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2091 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 2092 2093 struct bge_tx_bd { 2094 bge_hostaddr bge_addr; 2095 #if BYTE_ORDER == LITTLE_ENDIAN 2096 u_int16_t bge_flags; 2097 u_int16_t bge_len; 2098 u_int16_t bge_vlan_tag; 2099 u_int16_t bge_rsvd; 2100 #else 2101 u_int16_t bge_len; 2102 u_int16_t bge_flags; 2103 u_int16_t bge_rsvd; 2104 u_int16_t bge_vlan_tag; 2105 #endif 2106 }; 2107 2108 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2109 #define BGE_TXBDFLAG_IP_CSUM 0x0002 2110 #define BGE_TXBDFLAG_END 0x0004 2111 #define BGE_TXBDFLAG_IP_FRAG 0x0008 2112 #define BGE_TXBDFLAG_JMB_PKT 0x0008 2113 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2114 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 2115 #define BGE_TXBDFLAG_COAL_NOW 0x0080 2116 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2117 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2118 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2119 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2120 #define BGE_TXBDFLAG_NO_CRC 0x8000 2121 2122 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 2123 BGE_SEND_RING_1_TO_4 + \ 2124 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2125 2126 struct bge_rx_bd { 2127 bge_hostaddr bge_addr; 2128 #if BYTE_ORDER == LITTLE_ENDIAN 2129 u_int16_t bge_len; 2130 u_int16_t bge_idx; 2131 u_int16_t bge_flags; 2132 u_int16_t bge_type; 2133 u_int16_t bge_tcp_udp_csum; 2134 u_int16_t bge_ip_csum; 2135 u_int16_t bge_vlan_tag; 2136 u_int16_t bge_error_flag; 2137 #else 2138 u_int16_t bge_idx; 2139 u_int16_t bge_len; 2140 u_int16_t bge_type; 2141 u_int16_t bge_flags; 2142 u_int16_t bge_ip_csum; 2143 u_int16_t bge_tcp_udp_csum; 2144 u_int16_t bge_error_flag; 2145 u_int16_t bge_vlan_tag; 2146 #endif 2147 u_int32_t bge_rsvd; 2148 u_int32_t bge_opaque; 2149 }; 2150 2151 struct bge_ext_rx_bd { 2152 bge_hostaddr bge_addr1; 2153 bge_hostaddr bge_addr2; 2154 bge_hostaddr bge_addr3; 2155 #if BYTE_ORDER == LITTLE_ENDIAN 2156 u_int16_t bge_len2; 2157 u_int16_t bge_len1; 2158 u_int16_t bge_rsvd; 2159 u_int16_t bge_len3; 2160 #else 2161 u_int16_t bge_len1; 2162 u_int16_t bge_len2; 2163 u_int16_t bge_len3; 2164 u_int16_t bge_rsvd; 2165 #endif 2166 struct bge_rx_bd bge_bd; 2167 }; 2168 2169 #define BGE_RXBDFLAG_END 0x0004 2170 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 2171 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 2172 #define BGE_RXBDFLAG_ERROR 0x0400 2173 #define BGE_RXBDFLAG_MINI_RING 0x0800 2174 #define BGE_RXBDFLAG_IP_CSUM 0x1000 2175 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2176 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2177 2178 #define BGE_RXERRFLAG_BAD_CRC 0x0001 2179 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 2180 #define BGE_RXERRFLAG_LINK_LOST 0x0004 2181 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2182 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 2183 #define BGE_RXERRFLAG_RUNT 0x0020 2184 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2185 #define BGE_RXERRFLAG_GIANT 0x0080 2186 2187 struct bge_sts_idx { 2188 #if BYTE_ORDER == LITTLE_ENDIAN 2189 u_int16_t bge_rx_prod_idx; 2190 u_int16_t bge_tx_cons_idx; 2191 #else 2192 u_int16_t bge_tx_cons_idx; 2193 u_int16_t bge_rx_prod_idx; 2194 #endif 2195 }; 2196 2197 struct bge_status_block { 2198 u_int32_t bge_status; 2199 u_int32_t bge_rsvd0; 2200 #if BYTE_ORDER == LITTLE_ENDIAN 2201 u_int16_t bge_rx_jumbo_cons_idx; 2202 u_int16_t bge_rx_std_cons_idx; 2203 u_int16_t bge_rx_mini_cons_idx; 2204 u_int16_t bge_rsvd1; 2205 #else 2206 u_int16_t bge_rx_std_cons_idx; 2207 u_int16_t bge_rx_jumbo_cons_idx; 2208 u_int16_t bge_rsvd1; 2209 u_int16_t bge_rx_mini_cons_idx; 2210 #endif 2211 struct bge_sts_idx bge_idx[16]; 2212 }; 2213 2214 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2215 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2216 2217 #define BGE_STATFLAG_UPDATED 0x00000001 2218 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2219 #define BGE_STATFLAG_ERROR 0x00000004 2220 2221 /* 2222 * SysKonnect Subsystem IDs 2223 */ 2224 #define SK_SUBSYSID_9D41 0x4441 2225 2226 /* 2227 * Dell PCI vendor ID 2228 */ 2229 #define DELL_VENDORID 0x1028 2230 2231 /* 2232 * Offset of MAC address inside EEPROM. 2233 */ 2234 #define BGE_EE_MAC_OFFSET 0x7C 2235 #define BGE_EE_MAC_OFFSET_5906 0x10 2236 #define BGE_EE_HWCFG_OFFSET 0xC8 2237 2238 #define BGE_HWCFG_VOLTAGE 0x00000003 2239 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2240 #define BGE_HWCFG_MEDIA 0x00000030 2241 #define BGE_HWCFG_ASF 0x00000080 2242 2243 #define BGE_VOLTAGE_1POINT3 0x00000000 2244 #define BGE_VOLTAGE_1POINT8 0x00000001 2245 2246 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2247 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2248 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2249 2250 #define BGE_MEDIA_UNSPEC 0x00000000 2251 #define BGE_MEDIA_COPPER 0x00000010 2252 #define BGE_MEDIA_FIBER 0x00000020 2253 2254 #define BGE_TICKS_PER_SEC 1000000 2255 2256 /* 2257 * Ring size constants. 2258 */ 2259 #define BGE_EVENT_RING_CNT 256 2260 #define BGE_CMD_RING_CNT 64 2261 #define BGE_STD_RX_RING_CNT 512 2262 #define BGE_JUMBO_RX_RING_CNT 256 2263 #define BGE_MINI_RX_RING_CNT 1024 2264 #define BGE_RETURN_RING_CNT 1024 2265 2266 /* 5705 has smaller return ring size */ 2267 #define BGE_RETURN_RING_CNT_5705 512 2268 2269 /* 2270 * Possible TX ring sizes. 2271 */ 2272 #define BGE_TX_RING_CNT_128 128 2273 #define BGE_TX_RING_BASE_128 0x3800 2274 2275 #define BGE_TX_RING_CNT_256 256 2276 #define BGE_TX_RING_BASE_256 0x3000 2277 2278 #define BGE_TX_RING_CNT_512 512 2279 #define BGE_TX_RING_BASE_512 0x2000 2280 2281 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2282 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2283 2284 /* 2285 * Tigon III statistics counters. 2286 */ 2287 /* Statistics maintained MAC Receive block. */ 2288 struct bge_rx_mac_stats { 2289 bge_hostaddr ifHCInOctets; 2290 bge_hostaddr Reserved1; 2291 bge_hostaddr etherStatsFragments; 2292 bge_hostaddr ifHCInUcastPkts; 2293 bge_hostaddr ifHCInMulticastPkts; 2294 bge_hostaddr ifHCInBroadcastPkts; 2295 bge_hostaddr dot3StatsFCSErrors; 2296 bge_hostaddr dot3StatsAlignmentErrors; 2297 bge_hostaddr xonPauseFramesReceived; 2298 bge_hostaddr xoffPauseFramesReceived; 2299 bge_hostaddr macControlFramesReceived; 2300 bge_hostaddr xoffStateEntered; 2301 bge_hostaddr dot3StatsFramesTooLong; 2302 bge_hostaddr etherStatsJabbers; 2303 bge_hostaddr etherStatsUndersizePkts; 2304 bge_hostaddr inRangeLengthError; 2305 bge_hostaddr outRangeLengthError; 2306 bge_hostaddr etherStatsPkts64Octets; 2307 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2308 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2309 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2310 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2311 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2312 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2313 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2314 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2315 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2316 }; 2317 2318 /* Statistics maintained MAC Transmit block. */ 2319 struct bge_tx_mac_stats { 2320 bge_hostaddr ifHCOutOctets; 2321 bge_hostaddr Reserved2; 2322 bge_hostaddr etherStatsCollisions; 2323 bge_hostaddr outXonSent; 2324 bge_hostaddr outXoffSent; 2325 bge_hostaddr flowControlDone; 2326 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2327 bge_hostaddr dot3StatsSingleCollisionFrames; 2328 bge_hostaddr dot3StatsMultipleCollisionFrames; 2329 bge_hostaddr dot3StatsDeferredTransmissions; 2330 bge_hostaddr Reserved3; 2331 bge_hostaddr dot3StatsExcessiveCollisions; 2332 bge_hostaddr dot3StatsLateCollisions; 2333 bge_hostaddr dot3Collided2Times; 2334 bge_hostaddr dot3Collided3Times; 2335 bge_hostaddr dot3Collided4Times; 2336 bge_hostaddr dot3Collided5Times; 2337 bge_hostaddr dot3Collided6Times; 2338 bge_hostaddr dot3Collided7Times; 2339 bge_hostaddr dot3Collided8Times; 2340 bge_hostaddr dot3Collided9Times; 2341 bge_hostaddr dot3Collided10Times; 2342 bge_hostaddr dot3Collided11Times; 2343 bge_hostaddr dot3Collided12Times; 2344 bge_hostaddr dot3Collided13Times; 2345 bge_hostaddr dot3Collided14Times; 2346 bge_hostaddr dot3Collided15Times; 2347 bge_hostaddr ifHCOutUcastPkts; 2348 bge_hostaddr ifHCOutMulticastPkts; 2349 bge_hostaddr ifHCOutBroadcastPkts; 2350 bge_hostaddr dot3StatsCarrierSenseErrors; 2351 bge_hostaddr ifOutDiscards; 2352 bge_hostaddr ifOutErrors; 2353 }; 2354 2355 /* Stats counters access through registers */ 2356 struct bge_mac_stats_regs { 2357 u_int32_t ifHCOutOctets; 2358 u_int32_t Reserved0; 2359 u_int32_t etherStatsCollisions; 2360 u_int32_t outXonSent; 2361 u_int32_t outXoffSent; 2362 u_int32_t Reserved1; 2363 u_int32_t dot3StatsInternalMacTransmitErrors; 2364 u_int32_t dot3StatsSingleCollisionFrames; 2365 u_int32_t dot3StatsMultipleCollisionFrames; 2366 u_int32_t dot3StatsDeferredTransmissions; 2367 u_int32_t Reserved2; 2368 u_int32_t dot3StatsExcessiveCollisions; 2369 u_int32_t dot3StatsLateCollisions; 2370 u_int32_t Reserved3[14]; 2371 u_int32_t ifHCOutUcastPkts; 2372 u_int32_t ifHCOutMulticastPkts; 2373 u_int32_t ifHCOutBroadcastPkts; 2374 u_int32_t Reserved4[2]; 2375 u_int32_t ifHCInOctets; 2376 u_int32_t Reserved5; 2377 u_int32_t etherStatsFragments; 2378 u_int32_t ifHCInUcastPkts; 2379 u_int32_t ifHCInMulticastPkts; 2380 u_int32_t ifHCInBroadcastPkts; 2381 u_int32_t dot3StatsFCSErrors; 2382 u_int32_t dot3StatsAlignmentErrors; 2383 u_int32_t xonPauseFramesReceived; 2384 u_int32_t xoffPauseFramesReceived; 2385 u_int32_t macControlFramesReceived; 2386 u_int32_t xoffStateEntered; 2387 u_int32_t dot3StatsFramesTooLong; 2388 u_int32_t etherStatsJabbers; 2389 u_int32_t etherStatsUndersizePkts; 2390 }; 2391 2392 struct bge_stats { 2393 u_int8_t Reserved0[256]; 2394 2395 /* Statistics maintained by Receive MAC. */ 2396 struct bge_rx_mac_stats rxstats; 2397 2398 bge_hostaddr Unused1[37]; 2399 2400 /* Statistics maintained by Transmit MAC. */ 2401 struct bge_tx_mac_stats txstats; 2402 2403 bge_hostaddr Unused2[31]; 2404 2405 /* Statistics maintained by Receive List Placement. */ 2406 bge_hostaddr COSIfHCInPkts[16]; 2407 bge_hostaddr COSFramesDroppedDueToFilters; 2408 bge_hostaddr nicDmaWriteQueueFull; 2409 bge_hostaddr nicDmaWriteHighPriQueueFull; 2410 bge_hostaddr nicNoMoreRxBDs; 2411 bge_hostaddr ifInDiscards; 2412 bge_hostaddr ifInErrors; 2413 bge_hostaddr nicRecvThresholdHit; 2414 2415 bge_hostaddr Unused3[9]; 2416 2417 /* Statistics maintained by Send Data Initiator. */ 2418 bge_hostaddr COSIfHCOutPkts[16]; 2419 bge_hostaddr nicDmaReadQueueFull; 2420 bge_hostaddr nicDmaReadHighPriQueueFull; 2421 bge_hostaddr nicSendDataCompQueueFull; 2422 2423 /* Statistics maintained by Host Coalescing. */ 2424 bge_hostaddr nicRingSetSendProdIndex; 2425 bge_hostaddr nicRingStatusUpdate; 2426 bge_hostaddr nicInterrupts; 2427 bge_hostaddr nicAvoidedInterrupts; 2428 bge_hostaddr nicSendThresholdHit; 2429 2430 u_int8_t Reserved4[320]; 2431 }; 2432 2433 /* 2434 * Tigon general information block. This resides in host memory 2435 * and contains the status counters, ring control blocks and 2436 * producer pointers. 2437 */ 2438 2439 struct bge_gib { 2440 struct bge_stats bge_stats; 2441 struct bge_rcb bge_tx_rcb[16]; 2442 struct bge_rcb bge_std_rx_rcb; 2443 struct bge_rcb bge_jumbo_rx_rcb; 2444 struct bge_rcb bge_mini_rx_rcb; 2445 struct bge_rcb bge_return_rcb; 2446 }; 2447 2448 /* 2449 * NOTE! On the Alpha, we have an alignment constraint. 2450 * The first thing in the packet is a 14-byte Ethernet header. 2451 * This means that the packet is misaligned. To compensate, 2452 * we actually offset the data 2 bytes into the cluster. This 2453 * alignes the packet after the Ethernet header at a 32-bit 2454 * boundary. 2455 */ 2456 2457 #define BGE_JUMBO_FRAMELEN 9022 2458 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 2459 #define BGE_PAGE_SIZE PAGE_SIZE 2460 2461 /* 2462 * Other utility macros. 2463 */ 2464 #define BGE_INC(x, y) (x) = (x + 1) % y 2465 2466 /* 2467 * Vital product data and structures. 2468 */ 2469 #define BGE_VPD_FLAG 0x8000 2470 2471 #define VPD_RES_ID 0x82 /* ID string */ 2472 #define VPD_RES_READ 0x90 /* start of read only area */ 2473 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2474 #define VPD_RES_END 0x78 /* end tag */ 2475 2476 /* 2477 * Register access macros. The Tigon always uses memory mapped register 2478 * accesses and all registers must be accessed with 32 bit operations. 2479 */ 2480 2481 #define CSR_WRITE_4(sc, reg, val) \ 2482 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2483 2484 #define CSR_READ_4(sc, reg) \ 2485 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2486 2487 #define BGE_SETBIT(sc, reg, x) \ 2488 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2489 #define BGE_CLRBIT(sc, reg, x) \ 2490 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2491 2492 #define PCI_SETBIT(pc, tag, reg, x) \ 2493 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 2494 #define PCI_CLRBIT(pc, tag, reg, x) \ 2495 pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 2496 2497 /* 2498 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2499 * values are tuneable. They control the actual amount of buffers 2500 * allocated for the standard, mini and jumbo receive rings. 2501 */ 2502 2503 #define BGE_SSLOTS 256 2504 #define BGE_MSLOTS 256 2505 #define BGE_JSLOTS 384 2506 2507 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2508 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2509 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2510 2511 /* 2512 * Ring structures. Most of these reside in host memory and we tell 2513 * the NIC where they are via the ring control blocks. The exceptions 2514 * are the tx and command rings, which live in NIC memory and which 2515 * we access via the shared memory window. 2516 */ 2517 struct bge_ring_data { 2518 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2519 struct bge_ext_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2520 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2521 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2522 struct bge_status_block bge_status_block; 2523 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2524 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2525 struct bge_gib bge_info; 2526 }; 2527 2528 #define BGE_RING_DMA_ADDR(sc, offset) \ 2529 ((sc)->bge_ring_map->dm_segs[0].ds_addr + \ 2530 offsetof(struct bge_ring_data, offset)) 2531 2532 /* 2533 * Number of DMA segments in a TxCB. Note that this is carefully 2534 * chosen to make the total struct size an even power of two. It's 2535 * critical that no TxCB be split across a page boundary since 2536 * no attempt is made to allocate physically contiguous memory. 2537 * 2538 */ 2539 #ifdef __LP64__ 2540 #define BGE_NTXSEG 30 2541 #else 2542 #define BGE_NTXSEG 31 2543 #endif 2544 2545 /* 2546 * Mbuf pointers. We need these to keep track of the virtual addresses 2547 * of our mbuf chains since we can only convert from physical to virtual, 2548 * not the other way around. 2549 */ 2550 struct bge_chain_data { 2551 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2552 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2553 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2554 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2555 bus_dmamap_t bge_tx_map[BGE_TX_RING_CNT]; 2556 bus_dmamap_t bge_rx_std_map[BGE_STD_RX_RING_CNT]; 2557 bus_dmamap_t bge_rx_jumbo_map[BGE_JUMBO_RX_RING_CNT]; 2558 }; 2559 2560 struct bge_type { 2561 u_int16_t bge_vid; 2562 u_int16_t bge_did; 2563 char *bge_name; 2564 }; 2565 2566 #define BGE_TIMEOUT 100000 2567 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2568 2569 struct txdmamap_pool_entry { 2570 bus_dmamap_t dmamap; 2571 SLIST_ENTRY(txdmamap_pool_entry) link; 2572 }; 2573 2574 #define ASF_ENABLE 1 2575 #define ASF_NEW_HANDSHAKE 2 2576 #define ASF_STACKUP 4 2577 2578 struct bge_softc { 2579 struct device bge_dev; 2580 struct arpcom arpcom; /* interface info */ 2581 bus_space_handle_t bge_bhandle; 2582 bus_space_tag_t bge_btag; 2583 void *bge_intrhand; 2584 struct pci_attach_args bge_pa; 2585 struct mii_data bge_mii; 2586 struct ifmedia bge_ifmedia; /* media info */ 2587 u_int32_t bge_flags; 2588 #define BGE_TXRING_VALID 0x00000001 2589 #define BGE_RXRING_VALID 0x00000002 2590 #define BGE_JUMBO_RXRING_VALID 0x00000004 2591 #define BGE_RX_ALIGNBUG 0x00000008 2592 #define BGE_NO_3LED 0x00000010 2593 #define BGE_PCIX 0x00000020 2594 #define BGE_PCIE 0x00000040 2595 #define BGE_ASF_MODE 0x00000080 2596 #define BGE_NO_EEPROM 0x00000100 2597 #define BGE_JUMBO_CAPABLE 0x00000200 2598 #define BGE_10_100_ONLY 0x00000400 2599 #define BGE_PHY_FIBER_TBI 0x00000800 2600 #define BGE_PHY_FIBER_MII 0x00001000 2601 #define BGE_PHY_CRC_BUG 0x00002000 2602 #define BGE_PHY_ADC_BUG 0x00004000 2603 #define BGE_PHY_5704_A0_BUG 0x00008000 2604 #define BGE_PHY_JITTER_BUG 0x00010000 2605 #define BGE_PHY_BER_BUG 0x00020000 2606 #define BGE_PHY_ADJUST_TRIM 0x00040000 2607 #define BGE_NO_ETH_WIRE_SPEED 0x00080000 2608 #define BGE_IS_5788 0x00100000 2609 #define BGE_5705_PLUS 0x00200000 2610 #define BGE_5750_PLUS 0x00400000 2611 #define BGE_5755_PLUS 0x00800000 2612 #define BGE_5714_FAMILY 0x01000000 2613 #define BGE_5700_FAMILY 0x02000000 2614 2615 bus_dma_tag_t bge_dmatag; 2616 u_int32_t bge_chipid; 2617 struct bge_ring_data *bge_rdata; /* rings */ 2618 struct bge_chain_data bge_cdata; /* mbufs */ 2619 bus_dmamap_t bge_ring_map; 2620 u_int16_t bge_tx_saved_considx; 2621 u_int16_t bge_rx_saved_considx; 2622 u_int16_t bge_ev_saved_considx; 2623 u_int16_t bge_return_ring_cnt; 2624 u_int32_t bge_tx_prodidx; 2625 u_int16_t bge_std; /* current std ring head */ 2626 int bge_std_cnt; 2627 u_int16_t bge_jumbo; /* current jumo ring head */ 2628 int bge_jumbo_cnt; 2629 u_int32_t bge_stat_ticks; 2630 u_int32_t bge_rx_coal_ticks; 2631 u_int32_t bge_tx_coal_ticks; 2632 u_int32_t bge_rx_max_coal_bds; 2633 u_int32_t bge_tx_max_coal_bds; 2634 u_int32_t bge_tx_buf_ratio; 2635 u_int32_t bge_sts; 2636 #define BGE_STS_LINK 0x00000001 /* MAC link status */ 2637 #define BGE_STS_LINK_EVT 0x00000002 /* pending link event */ 2638 #define BGE_STS_AUTOPOLL 0x00000004 /* PHY auto-polling */ 2639 #define BGE_STS_BIT(sc, x) ((sc)->bge_sts & (x)) 2640 #define BGE_STS_SETBIT(sc, x) ((sc)->bge_sts |= (x)) 2641 #define BGE_STS_CLRBIT(sc, x) ((sc)->bge_sts &= ~(x)) 2642 int bge_flowflags; 2643 int bge_txcnt; 2644 struct timeout bge_timeout; 2645 struct timeout bge_rxtimeout; 2646 u_int32_t bge_rx_discards; 2647 u_int32_t bge_tx_discards; 2648 u_int32_t bge_rx_inerrors; 2649 u_int32_t bge_rx_overruns; 2650 u_int32_t bge_tx_collisions; 2651 SLIST_HEAD(, txdmamap_pool_entry) txdma_list; 2652 struct txdmamap_pool_entry *txdma[BGE_TX_RING_CNT]; 2653 }; 2654