1 /* $OpenBSD: if_casvar.h,v 1.7 2010/09/20 07:40:38 deraadt Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2007 Mark Kettenis. 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 #ifndef _IF_CASVAR_H 34 #define _IF_CASVAR_H 35 36 #include <sys/queue.h> 37 #include <sys/timeout.h> 38 39 /* 40 * Misc. definitions for Sun Cassini ethernet controllers. 41 */ 42 43 /* 44 * Preferred page size. Cassini has a configurable page size, but 45 * needs at least 8k to handle jumbo frames. This happens to be the 46 * default anyway. 47 */ 48 #define CAS_PAGE_SIZE 8192 49 50 /* 51 * Transmit descriptor ring size. This is arbitrary, but allocate 52 * enough descriptors for 64 pending transmissions and 16 segments 53 * per packet. 54 */ 55 #define CAS_NTXSEGS 16 56 57 #define CAS_TXQUEUELEN 64 58 #define CAS_NTXDESC (CAS_TXQUEUELEN * CAS_NTXSEGS) 59 #define CAS_NTXDESC_MASK (CAS_NTXDESC - 1) 60 #define CAS_NEXTTX(x) ((x + 1) & CAS_NTXDESC_MASK) 61 62 struct cas_sxd { 63 struct mbuf *sd_mbuf; 64 bus_dmamap_t sd_map; 65 }; 66 67 /* 68 * Receive descriptor ring size. We have one Rx buffer per incoming 69 * packet, so this logic is a little simpler. 70 */ 71 #define CAS_NRXDESC 128 72 #define CAS_NRXDESC_MASK (CAS_NRXDESC - 1) 73 74 /* 75 * Receive completion ring size. 76 */ 77 #define CAS_NRXCOMP 256 78 #define CAS_NRXCOMP_MASK (CAS_NRXCOMP - 1) 79 #define CAS_NEXTRX(x) ((x + 1) & CAS_NRXCOMP_MASK) 80 81 /* 82 * Control structures are DMA'd to the Cassini chip. We allocate them in 83 * a single clump that maps to a single DMA segment to make several things 84 * easier. 85 */ 86 struct cas_control_data { 87 /* 88 * The transmit descriptors. 89 */ 90 struct cas_desc ccd_txdescs[CAS_NTXDESC]; 91 92 /* 93 * The receive completions. 94 */ 95 struct cas_comp ccd_rxcomps[CAS_NRXCOMP]; 96 97 /* 98 * The receive descriptors. 99 */ 100 struct cas_desc ccd_rxdescs[CAS_NRXDESC]; 101 char ccd_unused[CAS_PAGE_SIZE - CAS_NRXDESC * 16]; 102 struct cas_desc ccd_rxdescs2[CAS_NRXDESC]; 103 }; 104 105 #define CAS_CDOFF(x) offsetof(struct cas_control_data, x) 106 #define CAS_CDTXOFF(x) CAS_CDOFF(ccd_txdescs[(x)]) 107 #define CAS_CDRXOFF(x) CAS_CDOFF(ccd_rxdescs[(x)]) 108 #define CAS_CDRXOFF2(x) CAS_CDOFF(ccd_rxdescs2[(x)]) 109 #define CAS_CDRXCOFF(x) CAS_CDOFF(ccd_rxcomps[(x)]) 110 111 /* 112 * Software state for receive jobs. 113 */ 114 struct cas_rxsoft { 115 bus_dmamap_t rxs_dmamap; /* our DMA map */ 116 bus_dma_segment_t rxs_dmaseg; /* our DMA segment */ 117 caddr_t rxs_kva; 118 }; 119 120 /* 121 * Software state per device. 122 */ 123 struct cas_softc { 124 struct device sc_dev; /* generic device information */ 125 struct arpcom sc_arpcom; /* ethernet common data */ 126 struct mii_data sc_mii; /* MII media control */ 127 #define sc_media sc_mii.mii_media/* shorthand */ 128 struct timeout sc_tick_ch; /* tick callout */ 129 130 bus_space_tag_t sc_memt; 131 bus_space_handle_t sc_memh; 132 void *sc_ih; 133 134 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 135 bus_dmamap_t sc_dmamap; /* bus dma handle */ 136 int sc_burst; /* DVMA burst size in effect */ 137 int sc_phys[2]; /* MII instance -> PHY map */ 138 139 int sc_mif_config; /* Selected MII reg setting */ 140 141 /* 142 * Ring buffer DMA stuff. 143 */ 144 bus_dma_segment_t sc_cdseg; /* control data memory */ 145 int sc_cdnseg; /* number of segments */ 146 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 147 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 148 149 /* 150 * Software state for transmit and receive descriptors. 151 */ 152 struct cas_sxd sc_txd[CAS_NTXDESC]; 153 u_int32_t sc_tx_cnt, sc_tx_prod, sc_tx_cons; 154 155 struct cas_rxsoft sc_rxsoft[CAS_NRXDESC]; 156 struct cas_rxsoft sc_rxsoft2[CAS_NRXDESC]; 157 158 /* 159 * Control data structures. 160 */ 161 struct cas_control_data *sc_control_data; 162 #define sc_txdescs sc_control_data->ccd_txdescs 163 #define sc_rxdescs sc_control_data->ccd_rxdescs 164 #define sc_rxdescs2 sc_control_data->ccd_rxdescs2 165 #define sc_rxcomps sc_control_data->ccd_rxcomps 166 167 int sc_rxptr; /* next ready RX descriptor/descsoft */ 168 int sc_rxfifosize; 169 int sc_rxdptr; 170 171 int sc_rev; 172 int sc_inited; 173 int sc_debug; 174 }; 175 176 /* 177 * This maccro determines whether we have a Cassini+. 178 */ 179 #define CAS_PLUS(sc) (sc->sc_rev > 0x10) 180 181 #define CAS_DMA_READ(v) letoh64(v) 182 #define CAS_DMA_WRITE(v) htole64(v) 183 184 #define CAS_CDTXADDR(sc, x) ((sc)->sc_cddma + CAS_CDTXOFF((x))) 185 #define CAS_CDRXADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXOFF((x))) 186 #define CAS_CDRXADDR2(sc, x) ((sc)->sc_cddma + CAS_CDRXOFF2((x))) 187 #define CAS_CDRXCADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXCOFF((x))) 188 189 #define CAS_CDTXSYNC(sc, x, n, ops) \ 190 do { \ 191 int __x, __n; \ 192 \ 193 __x = (x); \ 194 __n = (n); \ 195 \ 196 /* If it will wrap around, sync to the end of the ring. */ \ 197 if ((__x + __n) > CAS_NTXDESC) { \ 198 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 199 CAS_CDTXOFF(__x), sizeof(struct cas_desc) * \ 200 (CAS_NTXDESC - __x), (ops)); \ 201 __n -= (CAS_NTXDESC - __x); \ 202 __x = 0; \ 203 } \ 204 \ 205 /* Now sync whatever is left. */ \ 206 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 207 CAS_CDTXOFF(__x), sizeof(struct cas_desc) * __n, (ops)); \ 208 } while (0) 209 210 #define CAS_CDRXSYNC(sc, x, ops) \ 211 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 212 CAS_CDRXOFF((x)), sizeof(struct cas_desc), (ops)) 213 214 #define CAS_CDRXCSYNC(sc, x, ops) \ 215 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 216 CAS_CDRXCOFF((x)), sizeof(struct cas_desc), (ops)) 217 218 #define CAS_INIT_RXDESC(sc, d, s) \ 219 do { \ 220 struct cas_rxsoft *__rxs = &sc->sc_rxsoft[(s)]; \ 221 struct cas_desc *__rxd = &sc->sc_rxdescs[(d)]; \ 222 \ 223 __rxd->cd_addr = \ 224 CAS_DMA_WRITE(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 225 __rxd->cd_flags = \ 226 CAS_DMA_WRITE((s)); \ 227 CAS_CDRXSYNC((sc), (d), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 228 } while (0) 229 230 #endif 231