1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.93 2017/03/19 11:09:26 jsg Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 48 #include <net/if.h> 49 #include <net/if_media.h> 50 51 #include <netinet/in.h> 52 #include <netinet/if_ether.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <dev/pci/if_em_hw.h> 60 #include <dev/pci/if_em_soc.h> 61 62 #include <dev/mii/rgephyreg.h> 63 64 #define STATIC 65 66 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 67 static void em_swfw_sync_release(struct em_hw *, uint16_t); 68 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 69 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 70 static int32_t em_get_software_semaphore(struct em_hw *); 71 static void em_release_software_semaphore(struct em_hw *); 72 73 static int32_t em_check_downshift(struct em_hw *); 74 static void em_clear_vfta(struct em_hw *); 75 void em_clear_vfta_i350(struct em_hw *); 76 static int32_t em_commit_shadow_ram(struct em_hw *); 77 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 78 static int32_t em_config_fc_after_link_up(struct em_hw *); 79 static int32_t em_match_gig_phy(struct em_hw *); 80 static int32_t em_detect_gig_phy(struct em_hw *); 81 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 82 static int32_t em_get_auto_rd_done(struct em_hw *); 83 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 84 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 85 static int32_t em_get_phy_cfg_done(struct em_hw *); 86 static int32_t em_get_software_flag(struct em_hw *); 87 static int32_t em_ich8_cycle_init(struct em_hw *); 88 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 89 static int32_t em_id_led_init(struct em_hw *); 90 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 91 uint32_t); 92 static int32_t em_init_lcd_from_nvm(struct em_hw *); 93 static int32_t em_phy_no_cable_workaround(struct em_hw *); 94 static void em_init_rx_addrs(struct em_hw *); 95 static void em_initialize_hardware_bits(struct em_hw *); 96 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 97 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 98 static int32_t em_mng_enable_host_if(struct em_hw *); 99 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 100 uint16_t *); 101 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 102 uint16_t *data); 103 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 104 static void em_put_hw_eeprom_semaphore(struct em_hw *); 105 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 106 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 107 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 108 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 109 static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *); 110 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 111 uint16_t *); 112 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 113 uint16_t); 114 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 115 uint16_t *); 116 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 117 uint16_t *); 118 static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, 119 uint16_t *); 120 static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); 121 static void em_release_software_flag(struct em_hw *); 122 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 123 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 124 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 125 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 126 static void em_set_pci_express_master_disable(struct em_hw *); 127 static int32_t em_wait_autoneg(struct em_hw *); 128 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 129 static int32_t em_set_phy_type(struct em_hw *); 130 static void em_phy_init_script(struct em_hw *); 131 static int32_t em_setup_copper_link(struct em_hw *); 132 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 133 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 134 static int32_t em_phy_force_speed_duplex(struct em_hw *); 135 static int32_t em_config_mac_to_phy(struct em_hw *); 136 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 137 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 138 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 139 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 140 static int32_t em_phy_reset_dsp(struct em_hw *); 141 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 142 uint16_t *); 143 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 144 uint16_t *); 145 static int32_t em_spi_eeprom_ready(struct em_hw *); 146 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 147 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 148 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 149 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 150 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 151 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 152 static int32_t em_acquire_eeprom(struct em_hw *); 153 static void em_release_eeprom(struct em_hw *); 154 static void em_standby_eeprom(struct em_hw *); 155 static int32_t em_set_vco_speed(struct em_hw *); 156 static int32_t em_polarity_reversal_workaround(struct em_hw *); 157 static int32_t em_set_phy_mode(struct em_hw *); 158 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 159 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 160 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 161 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 162 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 163 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 164 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 165 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 166 int32_t em_link_stall_workaround_hv(struct em_hw *); 167 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 168 int32_t em_k1_workaround_lv(struct em_hw *); 169 int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); 170 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 171 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 172 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 173 uint16_t *, boolean_t); 174 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 175 uint16_t *, boolean_t); 176 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 177 boolean_t); 178 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 179 void em_power_up_serdes_link_82575(struct em_hw *); 180 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 181 uint16_t *); 182 int32_t em_set_eee_i350(struct em_hw *); 183 int32_t em_set_eee_pchlan(struct em_hw *); 184 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 185 int32_t em_initialize_M88E1512_phy(struct em_hw *); 186 187 /* IGP cable length table */ 188 static const uint16_t 189 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 190 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 191 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 192 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 193 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 194 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 195 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 196 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 197 110, 198 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 199 120}; 200 201 static const uint16_t 202 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 203 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 204 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 205 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 206 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 207 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 208 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 209 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 210 121, 124}; 211 212 /****************************************************************************** 213 * Set the phy type member in the hw struct. 214 * 215 * hw - Struct containing variables accessed by shared code 216 *****************************************************************************/ 217 STATIC int32_t 218 em_set_phy_type(struct em_hw *hw) 219 { 220 DEBUGFUNC("em_set_phy_type"); 221 222 if (hw->mac_type == em_undefined) 223 return -E1000_ERR_PHY_TYPE; 224 225 switch (hw->phy_id) { 226 case M88E1000_E_PHY_ID: 227 case M88E1000_I_PHY_ID: 228 case M88E1011_I_PHY_ID: 229 case M88E1111_I_PHY_ID: 230 case M88E1112_E_PHY_ID: 231 case M88E1543_E_PHY_ID: 232 case M88E1512_E_PHY_ID: 233 case I210_I_PHY_ID: 234 case I347AT4_E_PHY_ID: 235 hw->phy_type = em_phy_m88; 236 break; 237 case IGP01E1000_I_PHY_ID: 238 if (hw->mac_type == em_82541 || 239 hw->mac_type == em_82541_rev_2 || 240 hw->mac_type == em_82547 || 241 hw->mac_type == em_82547_rev_2) { 242 hw->phy_type = em_phy_igp; 243 break; 244 } 245 case IGP03E1000_E_PHY_ID: 246 case IGP04E1000_E_PHY_ID: 247 hw->phy_type = em_phy_igp_3; 248 break; 249 case IFE_E_PHY_ID: 250 case IFE_PLUS_E_PHY_ID: 251 case IFE_C_E_PHY_ID: 252 hw->phy_type = em_phy_ife; 253 break; 254 case M88E1141_E_PHY_ID: 255 hw->phy_type = em_phy_oem; 256 break; 257 case I82577_E_PHY_ID: 258 hw->phy_type = em_phy_82577; 259 break; 260 case I82578_E_PHY_ID: 261 hw->phy_type = em_phy_82578; 262 break; 263 case I82579_E_PHY_ID: 264 hw->phy_type = em_phy_82579; 265 break; 266 case I217_E_PHY_ID: 267 hw->phy_type = em_phy_i217; 268 break; 269 case I82580_I_PHY_ID: 270 case I350_I_PHY_ID: 271 hw->phy_type = em_phy_82580; 272 break; 273 case RTL8211_E_PHY_ID: 274 hw->phy_type = em_phy_rtl8211; 275 break; 276 case BME1000_E_PHY_ID: 277 if (hw->phy_revision == 1) { 278 hw->phy_type = em_phy_bm; 279 break; 280 } 281 /* FALLTHROUGH */ 282 case GG82563_E_PHY_ID: 283 if (hw->mac_type == em_80003es2lan) { 284 hw->phy_type = em_phy_gg82563; 285 break; 286 } 287 /* FALLTHROUGH */ 288 default: 289 /* Should never have loaded on this device */ 290 hw->phy_type = em_phy_undefined; 291 return -E1000_ERR_PHY_TYPE; 292 } 293 294 return E1000_SUCCESS; 295 } 296 297 /****************************************************************************** 298 * IGP phy init script - initializes the GbE PHY 299 * 300 * hw - Struct containing variables accessed by shared code 301 *****************************************************************************/ 302 static void 303 em_phy_init_script(struct em_hw *hw) 304 { 305 uint16_t phy_saved_data; 306 DEBUGFUNC("em_phy_init_script"); 307 308 if (hw->phy_init_script) { 309 msec_delay(20); 310 /* 311 * Save off the current value of register 0x2F5B to be 312 * restored at the end of this routine. 313 */ 314 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 315 316 /* Disabled the PHY transmitter */ 317 em_write_phy_reg(hw, 0x2F5B, 0x0003); 318 msec_delay(20); 319 em_write_phy_reg(hw, 0x0000, 0x0140); 320 msec_delay(5); 321 322 switch (hw->mac_type) { 323 case em_82541: 324 case em_82547: 325 em_write_phy_reg(hw, 0x1F95, 0x0001); 326 em_write_phy_reg(hw, 0x1F71, 0xBD21); 327 em_write_phy_reg(hw, 0x1F79, 0x0018); 328 em_write_phy_reg(hw, 0x1F30, 0x1600); 329 em_write_phy_reg(hw, 0x1F31, 0x0014); 330 em_write_phy_reg(hw, 0x1F32, 0x161C); 331 em_write_phy_reg(hw, 0x1F94, 0x0003); 332 em_write_phy_reg(hw, 0x1F96, 0x003F); 333 em_write_phy_reg(hw, 0x2010, 0x0008); 334 break; 335 case em_82541_rev_2: 336 case em_82547_rev_2: 337 em_write_phy_reg(hw, 0x1F73, 0x0099); 338 break; 339 default: 340 break; 341 } 342 343 em_write_phy_reg(hw, 0x0000, 0x3300); 344 msec_delay(20); 345 346 /* Now enable the transmitter */ 347 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 348 349 if (hw->mac_type == em_82547) { 350 uint16_t fused, fine, coarse; 351 /* Move to analog registers page */ 352 em_read_phy_reg(hw, 353 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 354 355 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 356 em_read_phy_reg(hw, 357 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 358 359 fine = fused & 360 IGP01E1000_ANALOG_FUSE_FINE_MASK; 361 coarse = fused & 362 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 363 364 if (coarse > 365 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 366 coarse -= 367 IGP01E1000_ANALOG_FUSE_COARSE_10; 368 fine -= 369 IGP01E1000_ANALOG_FUSE_FINE_1; 370 } else if (coarse == 371 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 372 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 373 374 fused = (fused & 375 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 376 (fine & 377 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 378 (coarse & 379 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 380 381 em_write_phy_reg(hw, 382 IGP01E1000_ANALOG_FUSE_CONTROL, 383 fused); 384 385 em_write_phy_reg(hw, 386 IGP01E1000_ANALOG_FUSE_BYPASS, 387 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 388 } 389 } 390 } 391 } 392 393 /****************************************************************************** 394 * Set the mac type member in the hw struct. 395 * 396 * hw - Struct containing variables accessed by shared code 397 *****************************************************************************/ 398 int32_t 399 em_set_mac_type(struct em_hw *hw) 400 { 401 DEBUGFUNC("em_set_mac_type"); 402 403 switch (hw->device_id) { 404 case E1000_DEV_ID_82542: 405 switch (hw->revision_id) { 406 case E1000_82542_2_0_REV_ID: 407 hw->mac_type = em_82542_rev2_0; 408 break; 409 case E1000_82542_2_1_REV_ID: 410 hw->mac_type = em_82542_rev2_1; 411 break; 412 default: 413 /* Invalid 82542 revision ID */ 414 return -E1000_ERR_MAC_TYPE; 415 } 416 break; 417 case E1000_DEV_ID_82543GC_FIBER: 418 case E1000_DEV_ID_82543GC_COPPER: 419 hw->mac_type = em_82543; 420 break; 421 case E1000_DEV_ID_82544EI_COPPER: 422 case E1000_DEV_ID_82544EI_FIBER: 423 case E1000_DEV_ID_82544GC_COPPER: 424 case E1000_DEV_ID_82544GC_LOM: 425 hw->mac_type = em_82544; 426 break; 427 case E1000_DEV_ID_82540EM: 428 case E1000_DEV_ID_82540EM_LOM: 429 case E1000_DEV_ID_82540EP: 430 case E1000_DEV_ID_82540EP_LOM: 431 case E1000_DEV_ID_82540EP_LP: 432 hw->mac_type = em_82540; 433 break; 434 case E1000_DEV_ID_82545EM_COPPER: 435 case E1000_DEV_ID_82545EM_FIBER: 436 hw->mac_type = em_82545; 437 break; 438 case E1000_DEV_ID_82545GM_COPPER: 439 case E1000_DEV_ID_82545GM_FIBER: 440 case E1000_DEV_ID_82545GM_SERDES: 441 hw->mac_type = em_82545_rev_3; 442 break; 443 case E1000_DEV_ID_82546EB_COPPER: 444 case E1000_DEV_ID_82546EB_FIBER: 445 case E1000_DEV_ID_82546EB_QUAD_COPPER: 446 hw->mac_type = em_82546; 447 break; 448 case E1000_DEV_ID_82546GB_COPPER: 449 case E1000_DEV_ID_82546GB_FIBER: 450 case E1000_DEV_ID_82546GB_SERDES: 451 case E1000_DEV_ID_82546GB_PCIE: 452 case E1000_DEV_ID_82546GB_QUAD_COPPER: 453 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 454 case E1000_DEV_ID_82546GB_2: 455 hw->mac_type = em_82546_rev_3; 456 break; 457 case E1000_DEV_ID_82541EI: 458 case E1000_DEV_ID_82541EI_MOBILE: 459 case E1000_DEV_ID_82541ER_LOM: 460 hw->mac_type = em_82541; 461 break; 462 case E1000_DEV_ID_82541ER: 463 case E1000_DEV_ID_82541GI: 464 case E1000_DEV_ID_82541GI_LF: 465 case E1000_DEV_ID_82541GI_MOBILE: 466 hw->mac_type = em_82541_rev_2; 467 break; 468 case E1000_DEV_ID_82547EI: 469 case E1000_DEV_ID_82547EI_MOBILE: 470 hw->mac_type = em_82547; 471 break; 472 case E1000_DEV_ID_82547GI: 473 hw->mac_type = em_82547_rev_2; 474 break; 475 case E1000_DEV_ID_82571EB_AF: 476 case E1000_DEV_ID_82571EB_AT: 477 case E1000_DEV_ID_82571EB_COPPER: 478 case E1000_DEV_ID_82571EB_FIBER: 479 case E1000_DEV_ID_82571EB_SERDES: 480 case E1000_DEV_ID_82571EB_QUAD_COPPER: 481 case E1000_DEV_ID_82571EB_QUAD_FIBER: 482 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 483 case E1000_DEV_ID_82571EB_SERDES_DUAL: 484 case E1000_DEV_ID_82571EB_SERDES_QUAD: 485 case E1000_DEV_ID_82571PT_QUAD_COPPER: 486 hw->mac_type = em_82571; 487 break; 488 case E1000_DEV_ID_82572EI_COPPER: 489 case E1000_DEV_ID_82572EI_FIBER: 490 case E1000_DEV_ID_82572EI_SERDES: 491 case E1000_DEV_ID_82572EI: 492 hw->mac_type = em_82572; 493 break; 494 case E1000_DEV_ID_82573E: 495 case E1000_DEV_ID_82573E_IAMT: 496 case E1000_DEV_ID_82573E_PM: 497 case E1000_DEV_ID_82573L: 498 case E1000_DEV_ID_82573L_PL_1: 499 case E1000_DEV_ID_82573L_PL_2: 500 case E1000_DEV_ID_82573V_PM: 501 hw->mac_type = em_82573; 502 break; 503 case E1000_DEV_ID_82574L: 504 case E1000_DEV_ID_82574LA: 505 case E1000_DEV_ID_82583V: 506 hw->mac_type = em_82574; 507 break; 508 case E1000_DEV_ID_82575EB_PT: 509 case E1000_DEV_ID_82575EB_PF: 510 case E1000_DEV_ID_82575GB_QP: 511 case E1000_DEV_ID_82575GB_QP_PM: 512 case E1000_DEV_ID_82576: 513 case E1000_DEV_ID_82576_FIBER: 514 case E1000_DEV_ID_82576_SERDES: 515 case E1000_DEV_ID_82576_QUAD_COPPER: 516 case E1000_DEV_ID_82576_QUAD_CU_ET2: 517 case E1000_DEV_ID_82576_NS: 518 case E1000_DEV_ID_82576_NS_SERDES: 519 case E1000_DEV_ID_82576_SERDES_QUAD: 520 hw->mac_type = em_82575; 521 hw->initialize_hw_bits_disable = 1; 522 break; 523 case E1000_DEV_ID_82580_COPPER: 524 case E1000_DEV_ID_82580_FIBER: 525 case E1000_DEV_ID_82580_QUAD_FIBER: 526 case E1000_DEV_ID_82580_SERDES: 527 case E1000_DEV_ID_82580_SGMII: 528 case E1000_DEV_ID_82580_COPPER_DUAL: 529 case E1000_DEV_ID_DH89XXCC_SGMII: 530 case E1000_DEV_ID_DH89XXCC_SERDES: 531 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 532 case E1000_DEV_ID_DH89XXCC_SFP: 533 hw->mac_type = em_82580; 534 hw->initialize_hw_bits_disable = 1; 535 break; 536 case E1000_DEV_ID_I210_COPPER: 537 case E1000_DEV_ID_I210_FIBER: 538 case E1000_DEV_ID_I210_SERDES: 539 case E1000_DEV_ID_I210_SGMII: 540 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 541 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 542 case E1000_DEV_ID_I211_COPPER: 543 hw->mac_type = em_i210; 544 hw->initialize_hw_bits_disable = 1; 545 hw->eee_enable = 1; 546 break; 547 case E1000_DEV_ID_I350_COPPER: 548 case E1000_DEV_ID_I350_FIBER: 549 case E1000_DEV_ID_I350_SERDES: 550 case E1000_DEV_ID_I350_SGMII: 551 case E1000_DEV_ID_I350_DA4: 552 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 553 case E1000_DEV_ID_I354_SGMII: 554 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 555 hw->mac_type = em_i350; 556 hw->initialize_hw_bits_disable = 1; 557 hw->eee_enable = 1; 558 break; 559 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 560 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 561 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 562 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 563 hw->mac_type = em_80003es2lan; 564 break; 565 case E1000_DEV_ID_ICH8_IFE: 566 case E1000_DEV_ID_ICH8_IFE_G: 567 case E1000_DEV_ID_ICH8_IFE_GT: 568 case E1000_DEV_ID_ICH8_IGP_AMT: 569 case E1000_DEV_ID_ICH8_IGP_C: 570 case E1000_DEV_ID_ICH8_IGP_M: 571 case E1000_DEV_ID_ICH8_IGP_M_AMT: 572 case E1000_DEV_ID_ICH8_82567V_3: 573 hw->mac_type = em_ich8lan; 574 break; 575 case E1000_DEV_ID_ICH9_BM: 576 case E1000_DEV_ID_ICH9_IFE: 577 case E1000_DEV_ID_ICH9_IFE_G: 578 case E1000_DEV_ID_ICH9_IFE_GT: 579 case E1000_DEV_ID_ICH9_IGP_AMT: 580 case E1000_DEV_ID_ICH9_IGP_C: 581 case E1000_DEV_ID_ICH9_IGP_M: 582 case E1000_DEV_ID_ICH9_IGP_M_AMT: 583 case E1000_DEV_ID_ICH9_IGP_M_V: 584 case E1000_DEV_ID_ICH10_R_BM_LF: 585 case E1000_DEV_ID_ICH10_R_BM_LM: 586 case E1000_DEV_ID_ICH10_R_BM_V: 587 hw->mac_type = em_ich9lan; 588 break; 589 case E1000_DEV_ID_ICH10_D_BM_LF: 590 case E1000_DEV_ID_ICH10_D_BM_LM: 591 hw->mac_type = em_ich10lan; 592 break; 593 case E1000_DEV_ID_PCH_M_HV_LC: 594 case E1000_DEV_ID_PCH_M_HV_LM: 595 case E1000_DEV_ID_PCH_D_HV_DC: 596 case E1000_DEV_ID_PCH_D_HV_DM: 597 hw->mac_type = em_pchlan; 598 hw->eee_enable = 1; 599 break; 600 case E1000_DEV_ID_PCH2_LV_LM: 601 case E1000_DEV_ID_PCH2_LV_V: 602 hw->mac_type = em_pch2lan; 603 break; 604 case E1000_DEV_ID_PCH_LPT_I217_LM: 605 case E1000_DEV_ID_PCH_LPT_I217_V: 606 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 607 case E1000_DEV_ID_PCH_LPTLP_I218_V: 608 case E1000_DEV_ID_PCH_I218_LM2: 609 case E1000_DEV_ID_PCH_I218_V2: 610 case E1000_DEV_ID_PCH_I218_LM3: 611 case E1000_DEV_ID_PCH_I218_V3: 612 hw->mac_type = em_pch_lpt; 613 break; 614 case E1000_DEV_ID_PCH_SPT_I219_LM: 615 case E1000_DEV_ID_PCH_SPT_I219_V: 616 case E1000_DEV_ID_PCH_SPT_I219_LM2: 617 case E1000_DEV_ID_PCH_SPT_I219_V2: 618 case E1000_DEV_ID_PCH_LBG_I219_LM3: 619 case E1000_DEV_ID_PCH_SPT_I219_LM4: 620 case E1000_DEV_ID_PCH_SPT_I219_V4: 621 case E1000_DEV_ID_PCH_SPT_I219_LM5: 622 case E1000_DEV_ID_PCH_SPT_I219_V5: 623 hw->mac_type = em_pch_spt; 624 break; 625 case E1000_DEV_ID_EP80579_LAN_1: 626 hw->mac_type = em_icp_xxxx; 627 hw->icp_xxxx_port_num = 0; 628 break; 629 case E1000_DEV_ID_EP80579_LAN_2: 630 case E1000_DEV_ID_EP80579_LAN_4: 631 hw->mac_type = em_icp_xxxx; 632 hw->icp_xxxx_port_num = 1; 633 break; 634 case E1000_DEV_ID_EP80579_LAN_3: 635 case E1000_DEV_ID_EP80579_LAN_5: 636 hw->mac_type = em_icp_xxxx; 637 hw->icp_xxxx_port_num = 2; 638 break; 639 case E1000_DEV_ID_EP80579_LAN_6: 640 hw->mac_type = em_icp_xxxx; 641 hw->icp_xxxx_port_num = 3; 642 break; 643 default: 644 /* Should never have loaded on this device */ 645 return -E1000_ERR_MAC_TYPE; 646 } 647 648 switch (hw->mac_type) { 649 case em_ich8lan: 650 case em_ich9lan: 651 case em_ich10lan: 652 case em_pchlan: 653 case em_pch2lan: 654 case em_pch_lpt: 655 case em_pch_spt: 656 hw->swfwhw_semaphore_present = TRUE; 657 hw->asf_firmware_present = TRUE; 658 break; 659 case em_80003es2lan: 660 case em_82575: 661 case em_82580: 662 case em_i210: 663 case em_i350: 664 hw->swfw_sync_present = TRUE; 665 /* FALLTHROUGH */ 666 case em_82571: 667 case em_82572: 668 case em_82573: 669 case em_82574: 670 hw->eeprom_semaphore_present = TRUE; 671 /* FALLTHROUGH */ 672 case em_82541: 673 case em_82547: 674 case em_82541_rev_2: 675 case em_82547_rev_2: 676 hw->asf_firmware_present = TRUE; 677 break; 678 default: 679 break; 680 } 681 682 return E1000_SUCCESS; 683 } 684 /***************************************************************************** 685 * Set media type and TBI compatibility. 686 * 687 * hw - Struct containing variables accessed by shared code 688 * **************************************************************************/ 689 void 690 em_set_media_type(struct em_hw *hw) 691 { 692 uint32_t status, ctrl_ext; 693 DEBUGFUNC("em_set_media_type"); 694 695 if (hw->mac_type != em_82543) { 696 /* tbi_compatibility is only valid on 82543 */ 697 hw->tbi_compatibility_en = FALSE; 698 } 699 700 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 701 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 702 hw->media_type = em_media_type_copper; 703 704 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 705 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 706 case E1000_CTRL_EXT_LINK_MODE_SGMII: 707 ctrl_ext |= E1000_CTRL_I2C_ENA; 708 break; 709 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 710 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 711 hw->media_type = em_media_type_internal_serdes; 712 ctrl_ext |= E1000_CTRL_I2C_ENA; 713 break; 714 default: 715 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 716 break; 717 } 718 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 719 return; 720 } 721 722 switch (hw->device_id) { 723 case E1000_DEV_ID_82545GM_SERDES: 724 case E1000_DEV_ID_82546GB_SERDES: 725 case E1000_DEV_ID_82571EB_SERDES: 726 case E1000_DEV_ID_82571EB_SERDES_DUAL: 727 case E1000_DEV_ID_82571EB_SERDES_QUAD: 728 case E1000_DEV_ID_82572EI_SERDES: 729 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 730 hw->media_type = em_media_type_internal_serdes; 731 break; 732 case E1000_DEV_ID_EP80579_LAN_1: 733 case E1000_DEV_ID_EP80579_LAN_2: 734 case E1000_DEV_ID_EP80579_LAN_3: 735 case E1000_DEV_ID_EP80579_LAN_4: 736 case E1000_DEV_ID_EP80579_LAN_5: 737 case E1000_DEV_ID_EP80579_LAN_6: 738 hw->media_type = em_media_type_copper; 739 break; 740 default: 741 switch (hw->mac_type) { 742 case em_82542_rev2_0: 743 case em_82542_rev2_1: 744 hw->media_type = em_media_type_fiber; 745 break; 746 case em_ich8lan: 747 case em_ich9lan: 748 case em_ich10lan: 749 case em_pchlan: 750 case em_pch2lan: 751 case em_pch_lpt: 752 case em_pch_spt: 753 case em_82573: 754 case em_82574: 755 /* 756 * The STATUS_TBIMODE bit is reserved or reused for 757 * the this device. 758 */ 759 hw->media_type = em_media_type_copper; 760 break; 761 default: 762 status = E1000_READ_REG(hw, STATUS); 763 if (status & E1000_STATUS_TBIMODE) { 764 hw->media_type = em_media_type_fiber; 765 /* tbi_compatibility not valid on fiber */ 766 hw->tbi_compatibility_en = FALSE; 767 } else { 768 hw->media_type = em_media_type_copper; 769 } 770 break; 771 } 772 } 773 } 774 /****************************************************************************** 775 * Reset the transmit and receive units; mask and clear all interrupts. 776 * 777 * hw - Struct containing variables accessed by shared code 778 *****************************************************************************/ 779 int32_t 780 em_reset_hw(struct em_hw *hw) 781 { 782 uint32_t ctrl; 783 uint32_t ctrl_ext; 784 uint32_t icr; 785 uint32_t manc; 786 uint32_t led_ctrl; 787 uint32_t timeout; 788 uint32_t extcnf_ctrl; 789 int32_t ret_val; 790 DEBUGFUNC("em_reset_hw"); 791 792 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 793 if (hw->mac_type == em_82542_rev2_0) { 794 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 795 em_pci_clear_mwi(hw); 796 } 797 if (hw->bus_type == em_bus_type_pci_express) { 798 /* 799 * Prevent the PCI-E bus from sticking if there is no TLP 800 * connection on the last TLP read/write transaction when MAC 801 * is reset. 802 */ 803 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 804 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 805 } 806 } 807 808 /* Set the completion timeout for 82575 chips */ 809 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 810 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 811 ret_val = em_set_pciex_completion_timeout(hw); 812 if (ret_val) { 813 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 814 } 815 } 816 817 /* Clear interrupt mask to stop board from generating interrupts */ 818 DEBUGOUT("Masking off all interrupts\n"); 819 E1000_WRITE_REG(hw, IMC, 0xffffffff); 820 /* 821 * Disable the Transmit and Receive units. Then delay to allow any 822 * pending transactions to complete before we hit the MAC with the 823 * global reset. 824 */ 825 E1000_WRITE_REG(hw, RCTL, 0); 826 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 827 E1000_WRITE_FLUSH(hw); 828 /* 829 * The tbi_compatibility_on Flag must be cleared when Rctl is 830 * cleared. 831 */ 832 hw->tbi_compatibility_on = FALSE; 833 /* 834 * Delay to allow any outstanding PCI transactions to complete before 835 * resetting the device 836 */ 837 msec_delay(10); 838 839 ctrl = E1000_READ_REG(hw, CTRL); 840 841 /* Must reset the PHY before resetting the MAC */ 842 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 843 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 844 msec_delay(5); 845 } 846 /* 847 * Must acquire the MDIO ownership before MAC reset. Ownership 848 * defaults to firmware after a reset. 849 */ 850 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 851 timeout = 10; 852 853 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 854 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 855 856 do { 857 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 858 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 859 860 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 861 break; 862 else 863 extcnf_ctrl |= 864 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 865 866 msec_delay(2); 867 timeout--; 868 } while (timeout); 869 } 870 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 871 if (hw->mac_type == em_ich8lan) { 872 /* Set Tx and Rx buffer allocation to 8k apiece. */ 873 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 874 /* Set Packet Buffer Size to 16k. */ 875 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 876 } 877 /* 878 * Issue a global reset to the MAC. This will reset the chip's 879 * transmit, receive, DMA, and link units. It will not effect the 880 * current PCI configuration. The global reset bit is self- 881 * clearing, and should clear within a microsecond. 882 */ 883 DEBUGOUT("Issuing a global reset to MAC\n"); 884 885 switch (hw->mac_type) { 886 case em_82544: 887 case em_82540: 888 case em_82545: 889 case em_82546: 890 case em_82541: 891 case em_82541_rev_2: 892 /* 893 * These controllers can't ack the 64-bit write when issuing 894 * the reset, so use IO-mapping as a workaround to issue the 895 * reset 896 */ 897 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 898 break; 899 case em_82545_rev_3: 900 case em_82546_rev_3: 901 /* Reset is performed on a shadow of the control register */ 902 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 903 break; 904 case em_ich8lan: 905 case em_ich9lan: 906 case em_ich10lan: 907 case em_pchlan: 908 case em_pch2lan: 909 case em_pch_lpt: 910 case em_pch_spt: 911 if (!hw->phy_reset_disable && 912 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 913 /* 914 * PHY HW reset requires MAC CORE reset at the same 915 * time to make sure the interface between MAC and 916 * the external PHY is reset. 917 */ 918 ctrl |= E1000_CTRL_PHY_RST; 919 /* 920 * Gate automatic PHY configuration by hardware on 921 * non-managed 82579 922 */ 923 if ((hw->mac_type == em_pch2lan) && 924 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 925 em_gate_hw_phy_config_ich8lan(hw, TRUE); 926 } 927 } 928 em_get_software_flag(hw); 929 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 930 msec_delay(5); 931 932 /* Ungate automatic PHY configuration on non-managed 82579 */ 933 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 934 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 935 msec_delay(10); 936 em_gate_hw_phy_config_ich8lan(hw, FALSE); 937 } 938 break; 939 default: 940 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 941 break; 942 } 943 944 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 945 if (hw->mac_type == em_pchlan) { 946 ret_val = em_hv_phy_workarounds_ich8lan(hw); 947 if (ret_val) 948 return ret_val; 949 } 950 else if (hw->mac_type == em_pch2lan) { 951 ret_val = em_lv_phy_workarounds_ich8lan(hw); 952 if (ret_val) 953 return ret_val; 954 } 955 } 956 957 /* 958 * After MAC reset, force reload of EEPROM to restore power-on 959 * settings to device. Later controllers reload the EEPROM 960 * automatically, so just wait for reload to complete. 961 */ 962 switch (hw->mac_type) { 963 case em_82542_rev2_0: 964 case em_82542_rev2_1: 965 case em_82543: 966 case em_82544: 967 /* Wait for reset to complete */ 968 usec_delay(10); 969 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 970 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 971 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 972 E1000_WRITE_FLUSH(hw); 973 /* Wait for EEPROM reload */ 974 msec_delay(2); 975 break; 976 case em_82541: 977 case em_82541_rev_2: 978 case em_82547: 979 case em_82547_rev_2: 980 /* Wait for EEPROM reload */ 981 msec_delay(20); 982 break; 983 case em_82573: 984 case em_82574: 985 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 986 usec_delay(10); 987 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 988 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 989 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 990 E1000_WRITE_FLUSH(hw); 991 } 992 /* FALLTHROUGH */ 993 994 /* Auto read done will delay 5ms or poll based on mac type */ 995 ret_val = em_get_auto_rd_done(hw); 996 if (ret_val) 997 return ret_val; 998 break; 999 default: 1000 /* Wait for EEPROM reload (it happens automatically) */ 1001 msec_delay(5); 1002 break; 1003 } 1004 1005 /* Disable HW ARPs on ASF enabled adapters */ 1006 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 1007 hw->mac_type != em_icp_xxxx) { 1008 manc = E1000_READ_REG(hw, MANC); 1009 manc &= ~(E1000_MANC_ARP_EN); 1010 E1000_WRITE_REG(hw, MANC, manc); 1011 } 1012 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 1013 em_phy_init_script(hw); 1014 1015 /* Configure activity LED after PHY reset */ 1016 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1017 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1018 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1019 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1020 } 1021 1022 /* 1023 * For PCH, this write will make sure that any noise 1024 * will be detected as a CRC error and be dropped rather than show up 1025 * as a bad packet to the DMA engine. 1026 */ 1027 if (hw->mac_type == em_pchlan) 1028 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 1029 1030 /* Clear interrupt mask to stop board from generating interrupts */ 1031 DEBUGOUT("Masking off all interrupts\n"); 1032 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1033 1034 /* Clear any pending interrupt events. */ 1035 icr = E1000_READ_REG(hw, ICR); 1036 1037 /* If MWI was previously enabled, reenable it. */ 1038 if (hw->mac_type == em_82542_rev2_0) { 1039 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1040 em_pci_set_mwi(hw); 1041 } 1042 if (IS_ICH8(hw->mac_type)) { 1043 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1044 kab |= E1000_KABGTXD_BGSQLBIAS; 1045 E1000_WRITE_REG(hw, KABGTXD, kab); 1046 } 1047 1048 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1049 uint32_t mdicnfg; 1050 uint16_t nvm_data; 1051 1052 /* clear global device reset status bit */ 1053 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1054 1055 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1056 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1057 &nvm_data); 1058 1059 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1060 if (nvm_data & NVM_WORD24_EXT_MDIO) 1061 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1062 if (nvm_data & NVM_WORD24_COM_MDIO) 1063 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1064 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1065 } 1066 1067 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1068 em_set_eee_i350(hw); 1069 1070 return E1000_SUCCESS; 1071 } 1072 1073 /****************************************************************************** 1074 * 1075 * Initialize a number of hardware-dependent bits 1076 * 1077 * hw: Struct containing variables accessed by shared code 1078 * 1079 *****************************************************************************/ 1080 STATIC void 1081 em_initialize_hardware_bits(struct em_hw *hw) 1082 { 1083 DEBUGFUNC("em_initialize_hardware_bits"); 1084 1085 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1086 /* Settings common to all silicon */ 1087 uint32_t reg_ctrl, reg_ctrl_ext; 1088 uint32_t reg_tarc0, reg_tarc1; 1089 uint32_t reg_tctl; 1090 uint32_t reg_txdctl, reg_txdctl1; 1091 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1092 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1093 * 27 */ 1094 1095 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1096 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1097 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1098 1099 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1100 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1101 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1102 1103 switch (hw->mac_type) { 1104 case em_82571: 1105 case em_82572: 1106 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1107 reg_tctl = E1000_READ_REG(hw, TCTL); 1108 1109 /* Set the phy Tx compatible mode bits */ 1110 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1111 1112 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1113 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1114 1115 if (reg_tctl & E1000_TCTL_MULR) 1116 /* Clear bit 28 if MULR is 1b */ 1117 reg_tarc1 &= ~0x10000000; 1118 else 1119 /* Set bit 28 if MULR is 0b */ 1120 reg_tarc1 |= 0x10000000; 1121 1122 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1123 break; 1124 case em_82573: 1125 case em_82574: 1126 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1127 reg_ctrl = E1000_READ_REG(hw, CTRL); 1128 1129 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1130 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1131 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1132 1133 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1134 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1135 break; 1136 case em_80003es2lan: 1137 if ((hw->media_type == em_media_type_fiber) || 1138 (hw->media_type == em_media_type_internal_serdes)) { 1139 /* Clear bit 20 */ 1140 reg_tarc0 &= ~0x00100000; 1141 } 1142 reg_tctl = E1000_READ_REG(hw, TCTL); 1143 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1144 if (reg_tctl & E1000_TCTL_MULR) 1145 /* Clear bit 28 if MULR is 1b */ 1146 reg_tarc1 &= ~0x10000000; 1147 else 1148 /* Set bit 28 if MULR is 0b */ 1149 reg_tarc1 |= 0x10000000; 1150 1151 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1152 break; 1153 case em_ich8lan: 1154 case em_ich9lan: 1155 case em_ich10lan: 1156 case em_pchlan: 1157 case em_pch2lan: 1158 case em_pch_lpt: 1159 case em_pch_spt: 1160 if (hw->mac_type == em_ich8lan) 1161 /* Set TARC0 bits 29 and 28 */ 1162 reg_tarc0 |= 0x30000000; 1163 1164 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1165 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1166 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1167 if (hw->mac_type >= em_pchlan) 1168 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1169 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1170 1171 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1172 * 24, 26, 27 */ 1173 1174 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1175 reg_tctl = E1000_READ_REG(hw, TCTL); 1176 1177 if (reg_tctl & E1000_TCTL_MULR) 1178 /* Clear bit 28 if MULR is 1b */ 1179 reg_tarc1 &= ~0x10000000; 1180 else 1181 /* Set bit 28 if MULR is 0b */ 1182 reg_tarc1 |= 0x10000000; 1183 1184 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1185 * 30 */ 1186 1187 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1188 break; 1189 default: 1190 break; 1191 } 1192 1193 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1194 } 1195 } 1196 1197 /****************************************************************************** 1198 * Performs basic configuration of the adapter. 1199 * 1200 * hw - Struct containing variables accessed by shared code 1201 * 1202 * Assumes that the controller has previously been reset and is in a 1203 * post-reset uninitialized state. Initializes the receive address registers, 1204 * multicast table, and VLAN filter table. Calls routines to setup link 1205 * configuration and flow control settings. Clears all on-chip counters. Leaves 1206 * the transmit and receive units disabled and uninitialized. 1207 *****************************************************************************/ 1208 int32_t 1209 em_init_hw(struct em_hw *hw) 1210 { 1211 uint32_t ctrl; 1212 uint32_t i; 1213 int32_t ret_val; 1214 uint16_t pcix_cmd_word; 1215 uint16_t pcix_stat_hi_word; 1216 uint16_t cmd_mmrbc; 1217 uint16_t stat_mmrbc; 1218 uint32_t mta_size; 1219 uint32_t reg_data; 1220 uint32_t ctrl_ext; 1221 uint32_t snoop; 1222 uint32_t fwsm; 1223 DEBUGFUNC("em_init_hw"); 1224 1225 /* force full DMA clock frequency for ICH8 */ 1226 if (hw->mac_type == em_ich8lan) { 1227 reg_data = E1000_READ_REG(hw, STATUS); 1228 reg_data &= ~0x80000000; 1229 E1000_WRITE_REG(hw, STATUS, reg_data); 1230 } 1231 1232 if (hw->mac_type == em_pchlan || 1233 hw->mac_type == em_pch2lan || 1234 hw->mac_type == em_pch_lpt || 1235 hw->mac_type == em_pch_spt) { 1236 /* 1237 * The MAC-PHY interconnect may still be in SMBus mode 1238 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1239 * the interconnect to PCIe mode, but only if there is no 1240 * firmware present otherwise firmware will have done it. 1241 */ 1242 fwsm = E1000_READ_REG(hw, FWSM); 1243 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1244 ctrl = E1000_READ_REG(hw, CTRL); 1245 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1246 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1247 E1000_WRITE_REG(hw, CTRL, ctrl); 1248 usec_delay(10); 1249 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1250 E1000_WRITE_REG(hw, CTRL, ctrl); 1251 msec_delay(50); 1252 } 1253 1254 /* Gate automatic PHY configuration on non-managed 82579 */ 1255 if (hw->mac_type == em_pch2lan) 1256 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1257 1258 /* 1259 * Reset the PHY before any acccess to it. Doing so, 1260 * ensures that the PHY is in a known good state before 1261 * we read/write PHY registers. The generic reset is 1262 * sufficient here, because we haven't determined 1263 * the PHY type yet. 1264 */ 1265 em_phy_reset(hw); 1266 1267 /* Ungate automatic PHY configuration on non-managed 82579 */ 1268 if (hw->mac_type == em_pch2lan && 1269 (fwsm & E1000_FWSM_FW_VALID) == 0) 1270 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1271 1272 /* Set MDIO slow mode before any other MDIO access */ 1273 ret_val = em_set_mdio_slow_mode_hv(hw); 1274 if (ret_val) 1275 return ret_val; 1276 } 1277 1278 /* Initialize Identification LED */ 1279 ret_val = em_id_led_init(hw); 1280 if (ret_val) { 1281 DEBUGOUT("Error Initializing Identification LED\n"); 1282 return ret_val; 1283 } 1284 /* Set the media type and TBI compatibility */ 1285 em_set_media_type(hw); 1286 1287 /* Must be called after em_set_media_type because media_type is used */ 1288 em_initialize_hardware_bits(hw); 1289 1290 /* Disabling VLAN filtering. */ 1291 DEBUGOUT("Initializing the IEEE VLAN\n"); 1292 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1293 if (!IS_ICH8(hw->mac_type)) { 1294 if (hw->mac_type < em_82545_rev_3) 1295 E1000_WRITE_REG(hw, VET, 0); 1296 if (hw->mac_type == em_i350) 1297 em_clear_vfta_i350(hw); 1298 else 1299 em_clear_vfta(hw); 1300 } 1301 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1302 if (hw->mac_type == em_82542_rev2_0) { 1303 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1304 em_pci_clear_mwi(hw); 1305 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1306 E1000_WRITE_FLUSH(hw); 1307 msec_delay(5); 1308 } 1309 /* 1310 * Setup the receive address. This involves initializing all of the 1311 * Receive Address Registers (RARs 0 - 15). 1312 */ 1313 em_init_rx_addrs(hw); 1314 1315 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1316 if (hw->mac_type == em_82542_rev2_0) { 1317 E1000_WRITE_REG(hw, RCTL, 0); 1318 E1000_WRITE_FLUSH(hw); 1319 msec_delay(1); 1320 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1321 em_pci_set_mwi(hw); 1322 } 1323 /* Zero out the Multicast HASH table */ 1324 DEBUGOUT("Zeroing the MTA\n"); 1325 mta_size = E1000_MC_TBL_SIZE; 1326 if (IS_ICH8(hw->mac_type)) 1327 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1328 for (i = 0; i < mta_size; i++) { 1329 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1330 /* 1331 * use write flush to prevent Memory Write Block (MWB) from 1332 * occuring when accessing our register space 1333 */ 1334 E1000_WRITE_FLUSH(hw); 1335 } 1336 /* 1337 * Set the PCI priority bit correctly in the CTRL register. This 1338 * determines if the adapter gives priority to receives, or if it 1339 * gives equal priority to transmits and receives. Valid only on 1340 * 82542 and 82543 silicon. 1341 */ 1342 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1343 ctrl = E1000_READ_REG(hw, CTRL); 1344 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1345 } 1346 switch (hw->mac_type) { 1347 case em_82545_rev_3: 1348 case em_82546_rev_3: 1349 break; 1350 default: 1351 /* 1352 * Workaround for PCI-X problem when BIOS sets MMRBC 1353 * incorrectly. 1354 */ 1355 if (hw->bus_type == em_bus_type_pcix) { 1356 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1357 &pcix_cmd_word); 1358 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1359 &pcix_stat_hi_word); 1360 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1361 >> PCIX_COMMAND_MMRBC_SHIFT; 1362 stat_mmrbc = (pcix_stat_hi_word & 1363 PCIX_STATUS_HI_MMRBC_MASK) >> 1364 PCIX_STATUS_HI_MMRBC_SHIFT; 1365 1366 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1367 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1368 if (cmd_mmrbc > stat_mmrbc) { 1369 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1370 pcix_cmd_word |= stat_mmrbc << 1371 PCIX_COMMAND_MMRBC_SHIFT; 1372 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1373 &pcix_cmd_word); 1374 } 1375 } 1376 break; 1377 } 1378 1379 /* More time needed for PHY to initialize */ 1380 if (IS_ICH8(hw->mac_type)) 1381 msec_delay(15); 1382 1383 /* 1384 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1385 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1386 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1387 */ 1388 if (hw->phy_type == em_phy_82578) { 1389 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1390 (uint16_t *)®_data); 1391 ret_val = em_phy_reset(hw); 1392 if (ret_val) 1393 return ret_val; 1394 } 1395 1396 /* Call a subroutine to configure the link and setup flow control. */ 1397 ret_val = em_setup_link(hw); 1398 1399 /* Set the transmit descriptor write-back policy */ 1400 if (hw->mac_type > em_82544) { 1401 ctrl = E1000_READ_REG(hw, TXDCTL); 1402 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1403 E1000_TXDCTL_FULL_TX_DESC_WB; 1404 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1405 } 1406 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1407 em_enable_tx_pkt_filtering(hw); 1408 } 1409 switch (hw->mac_type) { 1410 default: 1411 break; 1412 case em_80003es2lan: 1413 /* Enable retransmit on late collisions */ 1414 reg_data = E1000_READ_REG(hw, TCTL); 1415 reg_data |= E1000_TCTL_RTLC; 1416 E1000_WRITE_REG(hw, TCTL, reg_data); 1417 1418 /* Configure Gigabit Carry Extend Padding */ 1419 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1420 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1421 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1422 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1423 1424 /* Configure Transmit Inter-Packet Gap */ 1425 reg_data = E1000_READ_REG(hw, TIPG); 1426 reg_data &= ~E1000_TIPG_IPGT_MASK; 1427 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1428 E1000_WRITE_REG(hw, TIPG, reg_data); 1429 1430 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1431 reg_data &= ~0x00100000; 1432 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1433 /* FALLTHROUGH */ 1434 case em_82571: 1435 case em_82572: 1436 case em_82575: 1437 case em_82580: 1438 case em_i210: 1439 case em_i350: 1440 case em_ich8lan: 1441 case em_ich9lan: 1442 case em_ich10lan: 1443 case em_pchlan: 1444 case em_pch2lan: 1445 case em_pch_lpt: 1446 case em_pch_spt: 1447 ctrl = E1000_READ_REG(hw, TXDCTL1); 1448 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1449 E1000_TXDCTL_FULL_TX_DESC_WB; 1450 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1451 break; 1452 } 1453 1454 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1455 uint32_t gcr = E1000_READ_REG(hw, GCR); 1456 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1457 E1000_WRITE_REG(hw, GCR, gcr); 1458 } 1459 /* 1460 * Clear all of the statistics registers (clear on read). It is 1461 * important that we do this after we have tried to establish link 1462 * because the symbol error count will increment wildly if there is 1463 * no link. 1464 */ 1465 em_clear_hw_cntrs(hw); 1466 /* 1467 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1468 * after reset. 1469 */ 1470 if (IS_ICH8(hw->mac_type)) { 1471 if (hw->mac_type == em_ich8lan) 1472 snoop = PCI_EX_82566_SNOOP_ALL; 1473 else 1474 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1475 1476 em_set_pci_ex_no_snoop(hw, snoop); 1477 } 1478 1479 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1480 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1481 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1482 /* 1483 * Relaxed ordering must be disabled to avoid a parity error 1484 * crash in a PCI slot. 1485 */ 1486 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1487 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1488 } 1489 return ret_val; 1490 } 1491 1492 /****************************************************************************** 1493 * Adjust SERDES output amplitude based on EEPROM setting. 1494 * 1495 * hw - Struct containing variables accessed by shared code. 1496 *****************************************************************************/ 1497 static int32_t 1498 em_adjust_serdes_amplitude(struct em_hw *hw) 1499 { 1500 uint16_t eeprom_data; 1501 int32_t ret_val; 1502 DEBUGFUNC("em_adjust_serdes_amplitude"); 1503 1504 if (hw->media_type != em_media_type_internal_serdes || 1505 hw->mac_type >= em_82575) 1506 return E1000_SUCCESS; 1507 1508 switch (hw->mac_type) { 1509 case em_82545_rev_3: 1510 case em_82546_rev_3: 1511 break; 1512 default: 1513 return E1000_SUCCESS; 1514 } 1515 1516 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1517 if (ret_val) { 1518 return ret_val; 1519 } 1520 if (eeprom_data != EEPROM_RESERVED_WORD) { 1521 /* Adjust SERDES output amplitude only. */ 1522 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1523 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1524 eeprom_data); 1525 if (ret_val) 1526 return ret_val; 1527 } 1528 return E1000_SUCCESS; 1529 } 1530 1531 /****************************************************************************** 1532 * Configures flow control and link settings. 1533 * 1534 * hw - Struct containing variables accessed by shared code 1535 * 1536 * Determines which flow control settings to use. Calls the appropriate media- 1537 * specific link configuration function. Configures the flow control settings. 1538 * Assuming the adapter has a valid link partner, a valid link should be 1539 * established. Assumes the hardware has previously been reset and the 1540 * transmitter and receiver are not enabled. 1541 *****************************************************************************/ 1542 int32_t 1543 em_setup_link(struct em_hw *hw) 1544 { 1545 uint32_t ctrl_ext; 1546 int32_t ret_val; 1547 uint16_t eeprom_data; 1548 uint16_t eeprom_control2_reg_offset; 1549 DEBUGFUNC("em_setup_link"); 1550 1551 eeprom_control2_reg_offset = 1552 (hw->mac_type != em_icp_xxxx) 1553 ? EEPROM_INIT_CONTROL2_REG 1554 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1555 /* 1556 * In the case of the phy reset being blocked, we already have a 1557 * link. We do not have to set it up again. 1558 */ 1559 if (em_check_phy_reset_block(hw)) 1560 return E1000_SUCCESS; 1561 /* 1562 * Read and store word 0x0F of the EEPROM. This word contains bits 1563 * that determine the hardware's default PAUSE (flow control) mode, a 1564 * bit that determines whether the HW defaults to enabling or 1565 * disabling auto-negotiation, and the direction of the SW defined 1566 * pins. If there is no SW over-ride of the flow control setting, 1567 * then the variable hw->fc will be initialized based on a value in 1568 * the EEPROM. 1569 */ 1570 if (hw->fc == E1000_FC_DEFAULT) { 1571 switch (hw->mac_type) { 1572 case em_ich8lan: 1573 case em_ich9lan: 1574 case em_ich10lan: 1575 case em_pchlan: 1576 case em_pch2lan: 1577 case em_pch_lpt: 1578 case em_pch_spt: 1579 case em_82573: 1580 case em_82574: 1581 hw->fc = E1000_FC_FULL; 1582 break; 1583 default: 1584 ret_val = em_read_eeprom(hw, 1585 eeprom_control2_reg_offset, 1, &eeprom_data); 1586 if (ret_val) { 1587 DEBUGOUT("EEPROM Read Error\n"); 1588 return -E1000_ERR_EEPROM; 1589 } 1590 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1591 hw->fc = E1000_FC_NONE; 1592 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1593 EEPROM_WORD0F_ASM_DIR) 1594 hw->fc = E1000_FC_TX_PAUSE; 1595 else 1596 hw->fc = E1000_FC_FULL; 1597 break; 1598 } 1599 } 1600 /* 1601 * We want to save off the original Flow Control configuration just 1602 * in case we get disconnected and then reconnected into a different 1603 * hub or switch with different Flow Control capabilities. 1604 */ 1605 if (hw->mac_type == em_82542_rev2_0) 1606 hw->fc &= (~E1000_FC_TX_PAUSE); 1607 1608 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1609 hw->fc &= (~E1000_FC_RX_PAUSE); 1610 1611 hw->original_fc = hw->fc; 1612 1613 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1614 /* 1615 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1616 * polarity value for the SW controlled pins, and setup the Extended 1617 * Device Control reg with that info. This is needed because one of 1618 * the SW controlled pins is used for signal detection. So this 1619 * should be done before em_setup_pcs_link() or em_phy_setup() is 1620 * called. 1621 */ 1622 if (hw->mac_type == em_82543) { 1623 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1624 1, &eeprom_data); 1625 if (ret_val) { 1626 DEBUGOUT("EEPROM Read Error\n"); 1627 return -E1000_ERR_EEPROM; 1628 } 1629 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1630 SWDPIO__EXT_SHIFT); 1631 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1632 } 1633 /* Make sure we have a valid PHY */ 1634 ret_val = em_detect_gig_phy(hw); 1635 if (ret_val) { 1636 DEBUGOUT("Error, did not detect valid phy.\n"); 1637 if (hw->mac_type == em_icp_xxxx) 1638 return E1000_DEFER_INIT; 1639 else 1640 return ret_val; 1641 } 1642 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1643 1644 /* Call the necessary subroutine to configure the link. */ 1645 switch (hw->media_type) { 1646 case em_media_type_copper: 1647 case em_media_type_oem: 1648 ret_val = em_setup_copper_link(hw); 1649 break; 1650 default: 1651 ret_val = em_setup_fiber_serdes_link(hw); 1652 break; 1653 } 1654 /* 1655 * Initialize the flow control address, type, and PAUSE timer 1656 * registers to their default values. This is done even if flow 1657 * control is disabled, because it does not hurt anything to 1658 * initialize these registers. 1659 */ 1660 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1661 ); 1662 1663 /* 1664 * FCAL/H and FCT are hardcoded to standard values in 1665 * em_ich8lan / em_ich9lan / em_ich10lan. 1666 */ 1667 if (!IS_ICH8(hw->mac_type)) { 1668 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1669 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1670 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1671 } 1672 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1673 1674 if (hw->phy_type == em_phy_82577 || 1675 hw->phy_type == em_phy_82578 || 1676 hw->phy_type == em_phy_82579 || 1677 hw->phy_type == em_phy_i217) { 1678 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1679 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1680 hw->fc_pause_time); 1681 } 1682 1683 /* 1684 * Set the flow control receive threshold registers. Normally, these 1685 * registers will be set to a default threshold that may be adjusted 1686 * later by the driver's runtime code. However, if the ability to 1687 * transmit pause frames in not enabled, then these registers will be 1688 * set to 0. 1689 */ 1690 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1691 E1000_WRITE_REG(hw, FCRTL, 0); 1692 E1000_WRITE_REG(hw, FCRTH, 0); 1693 } else { 1694 /* 1695 * We need to set up the Receive Threshold high and low water 1696 * marks as well as (optionally) enabling the transmission of 1697 * XON frames. 1698 */ 1699 if (hw->fc_send_xon) { 1700 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1701 | E1000_FCRTL_XONE)); 1702 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1703 } else { 1704 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1705 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1706 } 1707 } 1708 return ret_val; 1709 } 1710 1711 void 1712 em_power_up_serdes_link_82575(struct em_hw *hw) 1713 { 1714 uint32_t reg; 1715 1716 /* Enable PCS to turn on link */ 1717 reg = E1000_READ_REG(hw, PCS_CFG0); 1718 reg |= E1000_PCS_CFG_PCS_EN; 1719 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1720 1721 /* Power up the laser */ 1722 reg = E1000_READ_REG(hw, CTRL_EXT); 1723 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1724 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1725 1726 /* flush the write to verify completion */ 1727 E1000_WRITE_FLUSH(hw); 1728 delay(5); 1729 } 1730 1731 /****************************************************************************** 1732 * Sets up link for a fiber based or serdes based adapter 1733 * 1734 * hw - Struct containing variables accessed by shared code 1735 * 1736 * Manipulates Physical Coding Sublayer functions in order to configure 1737 * link. Assumes the hardware has been previously reset and the transmitter 1738 * and receiver are not enabled. 1739 *****************************************************************************/ 1740 static int32_t 1741 em_setup_fiber_serdes_link(struct em_hw *hw) 1742 { 1743 uint32_t ctrl, ctrl_ext, reg; 1744 uint32_t status; 1745 uint32_t txcw = 0; 1746 uint32_t i; 1747 uint32_t signal = 0; 1748 int32_t ret_val; 1749 DEBUGFUNC("em_setup_fiber_serdes_link"); 1750 /* 1751 * On 82571 and 82572 Fiber connections, SerDes loopback mode 1752 * persists until explicitly turned off or a power cycle is 1753 * performed. A read to the register does not indicate its status. 1754 * Therefore, we ensure loopback mode is disabled during 1755 * initialization. 1756 */ 1757 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 1758 hw->mac_type >= em_82575) 1759 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1760 1761 if (hw->mac_type >= em_82575) 1762 em_power_up_serdes_link_82575(hw); 1763 1764 /* 1765 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 1766 * the optics detect a signal. On older adapters, it will be cleared 1767 * when there is a signal. This applies to fiber media only. If 1768 * we're on serdes media, adjust the output amplitude to value set in 1769 * the EEPROM. 1770 */ 1771 ctrl = E1000_READ_REG(hw, CTRL); 1772 if (hw->media_type == em_media_type_fiber) 1773 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 1774 1775 ret_val = em_adjust_serdes_amplitude(hw); 1776 if (ret_val) 1777 return ret_val; 1778 1779 /* Take the link out of reset */ 1780 ctrl &= ~(E1000_CTRL_LRST); 1781 1782 if (hw->mac_type >= em_82575) { 1783 /* set both sw defined pins on 82575/82576*/ 1784 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1785 1786 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1787 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1788 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1789 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1790 /* the backplane is always connected */ 1791 reg = E1000_READ_REG(hw, PCS_LCTL); 1792 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1793 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1794 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1795 DEBUGOUT("Configuring Forced Link\n"); 1796 E1000_WRITE_REG(hw, PCS_LCTL, reg); 1797 em_force_mac_fc(hw); 1798 hw->autoneg_failed = 0; 1799 return E1000_SUCCESS; 1800 break; 1801 default: 1802 /* Set switch control to serdes energy detect */ 1803 reg = E1000_READ_REG(hw, CONNSW); 1804 reg |= E1000_CONNSW_ENRGSRC; 1805 E1000_WRITE_REG(hw, CONNSW, reg); 1806 break; 1807 } 1808 } 1809 1810 /* Adjust VCO speed to improve BER performance */ 1811 ret_val = em_set_vco_speed(hw); 1812 if (ret_val) 1813 return ret_val; 1814 1815 em_config_collision_dist(hw); 1816 /* 1817 * Check for a software override of the flow control settings, and 1818 * setup the device accordingly. If auto-negotiation is enabled, 1819 * then software will have to set the "PAUSE" bits to the correct 1820 * value in the Tranmsit Config Word Register (TXCW) and re-start 1821 * auto-negotiation. However, if auto-negotiation is disabled, then 1822 * software will have to manually configure the two flow control 1823 * enable bits in the CTRL register. 1824 * 1825 * The possible values of the "fc" parameter are: 0: Flow control is 1826 * completely disabled 1: Rx flow control is enabled (we can receive 1827 * pause frames, but not send pause frames). 2: Tx flow control is 1828 * enabled (we can send pause frames but we do not support receiving 1829 * pause frames). 3: Both Rx and TX flow control (symmetric) are 1830 * enabled. 1831 */ 1832 switch (hw->fc) { 1833 case E1000_FC_NONE: 1834 /* 1835 * Flow control is completely disabled by a software 1836 * over-ride. 1837 */ 1838 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1839 break; 1840 case E1000_FC_RX_PAUSE: 1841 /* 1842 * RX Flow control is enabled and TX Flow control is disabled 1843 * by a software over-ride. Since there really isn't a way to 1844 * advertise that we are capable of RX Pause ONLY, we will 1845 * advertise that we support both symmetric and asymmetric RX 1846 * PAUSE. Later, we will disable the adapter's ability to 1847 * send PAUSE frames. 1848 */ 1849 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1850 E1000_TXCW_PAUSE_MASK); 1851 break; 1852 case E1000_FC_TX_PAUSE: 1853 /* 1854 * TX Flow control is enabled, and RX Flow control is 1855 * disabled, by a software over-ride. 1856 */ 1857 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1858 break; 1859 case E1000_FC_FULL: 1860 /* 1861 * Flow control (both RX and TX) is enabled by a software 1862 * over-ride. 1863 */ 1864 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1865 E1000_TXCW_PAUSE_MASK); 1866 break; 1867 default: 1868 DEBUGOUT("Flow control param set incorrectly\n"); 1869 return -E1000_ERR_CONFIG; 1870 break; 1871 } 1872 /* 1873 * Since auto-negotiation is enabled, take the link out of reset (the 1874 * link will be in reset, because we previously reset the chip). This 1875 * will restart auto-negotiation. If auto-neogtiation is successful 1876 * then the link-up status bit will be set and the flow control 1877 * enable bits (RFCE and TFCE) will be set according to their 1878 * negotiated value. 1879 */ 1880 DEBUGOUT("Auto-negotiation enabled\n"); 1881 1882 E1000_WRITE_REG(hw, TXCW, txcw); 1883 E1000_WRITE_REG(hw, CTRL, ctrl); 1884 E1000_WRITE_FLUSH(hw); 1885 1886 hw->txcw = txcw; 1887 msec_delay(1); 1888 /* 1889 * If we have a signal (the cable is plugged in) then poll for a 1890 * "Link-Up" indication in the Device Status Register. Time-out if a 1891 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 1892 * should complete in less than 500 milliseconds even if the other 1893 * end is doing it in SW). For internal serdes, we just assume a 1894 * signal is present, then poll. 1895 */ 1896 if (hw->media_type == em_media_type_internal_serdes || 1897 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1898 DEBUGOUT("Looking for Link\n"); 1899 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1900 msec_delay(10); 1901 status = E1000_READ_REG(hw, STATUS); 1902 if (status & E1000_STATUS_LU) 1903 break; 1904 } 1905 if (i == (LINK_UP_TIMEOUT / 10)) { 1906 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1907 hw->autoneg_failed = 1; 1908 /* 1909 * AutoNeg failed to achieve a link, so we'll call 1910 * em_check_for_link. This routine will force the 1911 * link up if we detect a signal. This will allow us 1912 * to communicate with non-autonegotiating link 1913 * partners. 1914 */ 1915 ret_val = em_check_for_link(hw); 1916 if (ret_val) { 1917 DEBUGOUT("Error while checking for link\n"); 1918 return ret_val; 1919 } 1920 hw->autoneg_failed = 0; 1921 } else { 1922 hw->autoneg_failed = 0; 1923 DEBUGOUT("Valid Link Found\n"); 1924 } 1925 } else { 1926 DEBUGOUT("No Signal Detected\n"); 1927 } 1928 return E1000_SUCCESS; 1929 } 1930 1931 /****************************************************************************** 1932 * Make sure we have a valid PHY and change PHY mode before link setup. 1933 * 1934 * hw - Struct containing variables accessed by shared code 1935 *****************************************************************************/ 1936 static int32_t 1937 em_copper_link_preconfig(struct em_hw *hw) 1938 { 1939 uint32_t ctrl; 1940 int32_t ret_val; 1941 uint16_t phy_data; 1942 DEBUGFUNC("em_copper_link_preconfig"); 1943 1944 ctrl = E1000_READ_REG(hw, CTRL); 1945 /* 1946 * With 82543, we need to force speed and duplex on the MAC equal to 1947 * what the PHY speed and duplex configuration is. In addition, we 1948 * need to perform a hardware reset on the PHY to take it out of 1949 * reset. 1950 */ 1951 if (hw->mac_type > em_82543) { 1952 ctrl |= E1000_CTRL_SLU; 1953 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1954 E1000_WRITE_REG(hw, CTRL, ctrl); 1955 } else { 1956 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 1957 E1000_CTRL_SLU); 1958 E1000_WRITE_REG(hw, CTRL, ctrl); 1959 ret_val = em_phy_hw_reset(hw); 1960 if (ret_val) 1961 return ret_val; 1962 } 1963 1964 /* Set PHY to class A mode (if necessary) */ 1965 ret_val = em_set_phy_mode(hw); 1966 if (ret_val) 1967 return ret_val; 1968 1969 if ((hw->mac_type == em_82545_rev_3) || 1970 (hw->mac_type == em_82546_rev_3)) { 1971 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1972 &phy_data); 1973 phy_data |= 0x00000008; 1974 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1975 phy_data); 1976 } 1977 if (hw->mac_type <= em_82543 || 1978 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 1979 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 1980 hw->phy_reset_disable = FALSE; 1981 1982 return E1000_SUCCESS; 1983 } 1984 1985 /****************************************************************************** 1986 * Copper link setup for em_phy_igp series. 1987 * 1988 * hw - Struct containing variables accessed by shared code 1989 *****************************************************************************/ 1990 static int32_t 1991 em_copper_link_igp_setup(struct em_hw *hw) 1992 { 1993 uint32_t led_ctrl; 1994 int32_t ret_val; 1995 uint16_t phy_data; 1996 DEBUGFUNC("em_copper_link_igp_setup"); 1997 1998 if (hw->phy_reset_disable) 1999 return E1000_SUCCESS; 2000 2001 ret_val = em_phy_reset(hw); 2002 if (ret_val) { 2003 DEBUGOUT("Error Resetting the PHY\n"); 2004 return ret_val; 2005 } 2006 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2007 msec_delay(15); 2008 if (hw->mac_type != em_ich8lan && 2009 hw->mac_type != em_ich9lan && 2010 hw->mac_type != em_ich10lan) { 2011 /* Configure activity LED after PHY reset */ 2012 led_ctrl = E1000_READ_REG(hw, LEDCTL); 2013 led_ctrl &= IGP_ACTIVITY_LED_MASK; 2014 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 2015 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 2016 } 2017 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 2018 if (hw->phy_type == em_phy_igp) { 2019 /* disable lplu d3 during driver init */ 2020 ret_val = em_set_d3_lplu_state(hw, FALSE); 2021 if (ret_val) { 2022 DEBUGOUT("Error Disabling LPLU D3\n"); 2023 return ret_val; 2024 } 2025 } 2026 /* disable lplu d0 during driver init */ 2027 if (hw->mac_type == em_pchlan || 2028 hw->mac_type == em_pch2lan || 2029 hw->mac_type == em_pch_lpt || 2030 hw->mac_type == em_pch_spt) 2031 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2032 else 2033 ret_val = em_set_d0_lplu_state(hw, FALSE); 2034 if (ret_val) { 2035 DEBUGOUT("Error Disabling LPLU D0\n"); 2036 return ret_val; 2037 } 2038 /* Configure mdi-mdix settings */ 2039 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2040 if (ret_val) 2041 return ret_val; 2042 2043 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2044 hw->dsp_config_state = em_dsp_config_disabled; 2045 /* Force MDI for earlier revs of the IGP PHY */ 2046 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2047 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2048 hw->mdix = 1; 2049 2050 } else { 2051 hw->dsp_config_state = em_dsp_config_enabled; 2052 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2053 2054 switch (hw->mdix) { 2055 case 1: 2056 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2057 break; 2058 case 2: 2059 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2060 break; 2061 case 0: 2062 default: 2063 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2064 break; 2065 } 2066 } 2067 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2068 if (ret_val) 2069 return ret_val; 2070 2071 /* set auto-master slave resolution settings */ 2072 if (hw->autoneg) { 2073 em_ms_type phy_ms_setting = hw->master_slave; 2074 if (hw->ffe_config_state == em_ffe_config_active) 2075 hw->ffe_config_state = em_ffe_config_enabled; 2076 2077 if (hw->dsp_config_state == em_dsp_config_activated) 2078 hw->dsp_config_state = em_dsp_config_enabled; 2079 /* 2080 * when autonegotiation advertisement is only 1000Mbps then 2081 * we should disable SmartSpeed and enable Auto MasterSlave 2082 * resolution as hardware default. 2083 */ 2084 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2085 /* Disable SmartSpeed */ 2086 ret_val = em_read_phy_reg(hw, 2087 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2088 if (ret_val) 2089 return ret_val; 2090 2091 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2092 ret_val = em_write_phy_reg(hw, 2093 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2094 if (ret_val) 2095 return ret_val; 2096 /* Set auto Master/Slave resolution process */ 2097 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2098 &phy_data); 2099 if (ret_val) 2100 return ret_val; 2101 2102 phy_data &= ~CR_1000T_MS_ENABLE; 2103 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2104 phy_data); 2105 if (ret_val) 2106 return ret_val; 2107 } 2108 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2109 if (ret_val) 2110 return ret_val; 2111 2112 /* load defaults for future use */ 2113 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2114 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2115 em_ms_force_slave) : em_ms_auto; 2116 2117 switch (phy_ms_setting) { 2118 case em_ms_force_master: 2119 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2120 break; 2121 case em_ms_force_slave: 2122 phy_data |= CR_1000T_MS_ENABLE; 2123 phy_data &= ~(CR_1000T_MS_VALUE); 2124 break; 2125 case em_ms_auto: 2126 phy_data &= ~CR_1000T_MS_ENABLE; 2127 break; 2128 default: 2129 break; 2130 } 2131 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2132 if (ret_val) 2133 return ret_val; 2134 } 2135 return E1000_SUCCESS; 2136 } 2137 2138 /****************************************************************************** 2139 * Copper link setup for em_phy_gg82563 series. 2140 * 2141 * hw - Struct containing variables accessed by shared code 2142 *****************************************************************************/ 2143 static int32_t 2144 em_copper_link_ggp_setup(struct em_hw *hw) 2145 { 2146 int32_t ret_val; 2147 uint16_t phy_data; 2148 uint32_t reg_data; 2149 DEBUGFUNC("em_copper_link_ggp_setup"); 2150 2151 if (!hw->phy_reset_disable) { 2152 2153 /* Enable CRS on TX for half-duplex operation. */ 2154 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2155 &phy_data); 2156 if (ret_val) 2157 return ret_val; 2158 2159 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2160 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2161 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2162 2163 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2164 phy_data); 2165 if (ret_val) 2166 return ret_val; 2167 /* 2168 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2169 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2170 * (MDI-X for 10/100Base-T modes) 2171 */ 2172 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2173 &phy_data); 2174 2175 if (ret_val) 2176 return ret_val; 2177 2178 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2179 2180 switch (hw->mdix) { 2181 case 1: 2182 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2183 break; 2184 case 2: 2185 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2186 break; 2187 case 0: 2188 default: 2189 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2190 break; 2191 } 2192 /* 2193 * Options: disable_polarity_correction = 0 (default) 2194 * Automatic Correction for Reversed Cable Polarity 0 - 2195 * Disabled 1 - Enabled 2196 */ 2197 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2198 if (hw->disable_polarity_correction == 1) 2199 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2200 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2201 phy_data); 2202 2203 if (ret_val) 2204 return ret_val; 2205 2206 /* SW Reset the PHY so all changes take effect */ 2207 ret_val = em_phy_reset(hw); 2208 if (ret_val) { 2209 DEBUGOUT("Error Resetting the PHY\n"); 2210 return ret_val; 2211 } 2212 } /* phy_reset_disable */ 2213 if (hw->mac_type == em_80003es2lan) { 2214 /* Bypass RX and TX FIFO's */ 2215 ret_val = em_write_kmrn_reg(hw, 2216 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2217 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2218 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2219 if (ret_val) 2220 return ret_val; 2221 2222 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2223 &phy_data); 2224 if (ret_val) 2225 return ret_val; 2226 2227 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2228 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2229 phy_data); 2230 2231 if (ret_val) 2232 return ret_val; 2233 2234 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2235 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2236 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2237 2238 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2239 &phy_data); 2240 if (ret_val) 2241 return ret_val; 2242 /* 2243 * Do not init these registers when the HW is in IAMT mode, 2244 * since the firmware will have already initialized them. We 2245 * only initialize them if the HW is not in IAMT mode. 2246 */ 2247 if (em_check_mng_mode(hw) == FALSE) { 2248 /* Enable Electrical Idle on the PHY */ 2249 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2250 ret_val = em_write_phy_reg(hw, 2251 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2252 if (ret_val) 2253 return ret_val; 2254 2255 ret_val = em_read_phy_reg(hw, 2256 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2257 if (ret_val) 2258 return ret_val; 2259 2260 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2261 ret_val = em_write_phy_reg(hw, 2262 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2263 2264 if (ret_val) 2265 return ret_val; 2266 } 2267 /* 2268 * Workaround: Disable padding in Kumeran interface in the 2269 * MAC and in the PHY to avoid CRC errors. 2270 */ 2271 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2272 &phy_data); 2273 if (ret_val) 2274 return ret_val; 2275 phy_data |= GG82563_ICR_DIS_PADDING; 2276 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2277 phy_data); 2278 if (ret_val) 2279 return ret_val; 2280 } 2281 return E1000_SUCCESS; 2282 } 2283 2284 /****************************************************************************** 2285 * Copper link setup for em_phy_m88 series. 2286 * 2287 * hw - Struct containing variables accessed by shared code 2288 *****************************************************************************/ 2289 static int32_t 2290 em_copper_link_mgp_setup(struct em_hw *hw) 2291 { 2292 int32_t ret_val; 2293 uint16_t phy_data; 2294 DEBUGFUNC("em_copper_link_mgp_setup"); 2295 2296 if (hw->phy_reset_disable) 2297 return E1000_SUCCESS; 2298 2299 /* disable lplu d0 during driver init */ 2300 if (hw->mac_type == em_pchlan || 2301 hw->mac_type == em_pch2lan || 2302 hw->mac_type == em_pch_lpt || 2303 hw->mac_type == em_pch_spt) 2304 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2305 2306 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2307 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2308 if (ret_val) 2309 return ret_val; 2310 2311 if (hw->phy_id == M88E1141_E_PHY_ID) { 2312 phy_data |= 0x00000008; 2313 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2314 phy_data); 2315 if (ret_val) 2316 return ret_val; 2317 2318 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2319 &phy_data); 2320 if (ret_val) 2321 return ret_val; 2322 2323 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2324 2325 } 2326 /* For BM PHY this bit is downshift enable */ 2327 else if (hw->phy_type != em_phy_bm) 2328 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2329 /* 2330 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2331 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2332 * 10/100Base-T modes) 2333 */ 2334 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2335 2336 switch (hw->mdix) { 2337 case 1: 2338 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2339 break; 2340 case 2: 2341 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2342 break; 2343 case 3: 2344 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2345 break; 2346 case 0: 2347 default: 2348 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2349 break; 2350 } 2351 /* 2352 * Options: disable_polarity_correction = 0 (default) Automatic 2353 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2354 */ 2355 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2356 if (hw->disable_polarity_correction == 1) 2357 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2358 2359 /* Enable downshift on BM (disabled by default) */ 2360 if (hw->phy_type == em_phy_bm) 2361 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2362 2363 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2364 if (ret_val) 2365 return ret_val; 2366 2367 if (((hw->phy_type == em_phy_m88) && 2368 (hw->phy_revision < M88E1011_I_REV_4) && 2369 (hw->phy_id != BME1000_E_PHY_ID)) || 2370 (hw->phy_type == em_phy_oem)) { 2371 /* 2372 * Force TX_CLK in the Extended PHY Specific Control Register 2373 * to 25MHz clock. 2374 */ 2375 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2376 &phy_data); 2377 if (ret_val) 2378 return ret_val; 2379 2380 if (hw->phy_type == em_phy_oem) { 2381 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2382 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2383 } 2384 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2385 2386 if ((hw->phy_revision == E1000_REVISION_2) && 2387 (hw->phy_id == M88E1111_I_PHY_ID)) { 2388 /* Vidalia Phy, set the downshift counter to 5x */ 2389 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2390 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2391 ret_val = em_write_phy_reg(hw, 2392 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2393 if (ret_val) 2394 return ret_val; 2395 } else { 2396 /* Configure Master and Slave downshift values */ 2397 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2398 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2399 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2400 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2401 ret_val = em_write_phy_reg(hw, 2402 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2403 if (ret_val) 2404 return ret_val; 2405 } 2406 } 2407 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2408 /* 2409 * Set PHY page 0, register 29 to 0x0003 2410 * The next two writes are supposed to lower BER for gig 2411 * conection 2412 */ 2413 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2414 if (ret_val) 2415 return ret_val; 2416 2417 /* Set PHY page 0, register 30 to 0x0000 */ 2418 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2419 if (ret_val) 2420 return ret_val; 2421 } 2422 if (hw->phy_type == em_phy_82578) { 2423 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2424 &phy_data); 2425 if (ret_val) 2426 return ret_val; 2427 2428 /* 82578 PHY - set the downshift count to 1x. */ 2429 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2430 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2431 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2432 phy_data); 2433 if (ret_val) 2434 return ret_val; 2435 } 2436 /* SW Reset the PHY so all changes take effect */ 2437 ret_val = em_phy_reset(hw); 2438 if (ret_val) { 2439 DEBUGOUT("Error Resetting the PHY\n"); 2440 return ret_val; 2441 } 2442 return E1000_SUCCESS; 2443 } 2444 2445 /****************************************************************************** 2446 * Copper link setup for em_phy_82577 series. 2447 * 2448 * hw - Struct containing variables accessed by shared code 2449 *****************************************************************************/ 2450 static int32_t 2451 em_copper_link_82577_setup(struct em_hw *hw) 2452 { 2453 int32_t ret_val; 2454 uint16_t phy_data; 2455 uint32_t led_ctl; 2456 DEBUGFUNC("em_copper_link_82577_setup"); 2457 2458 if (hw->phy_reset_disable) 2459 return E1000_SUCCESS; 2460 2461 /* Enable CRS on TX for half-duplex operation. */ 2462 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2463 if (ret_val) 2464 return ret_val; 2465 2466 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2467 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2468 2469 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2470 if (ret_val) 2471 return ret_val; 2472 2473 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2474 msec_delay(15); 2475 led_ctl = hw->ledctl_mode1; 2476 2477 /* disable lplu d0 during driver init */ 2478 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2479 if (ret_val) { 2480 DEBUGOUT("Error Disabling LPLU D0\n"); 2481 return ret_val; 2482 } 2483 2484 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2485 2486 return E1000_SUCCESS; 2487 } 2488 2489 static int32_t 2490 em_copper_link_82580_setup(struct em_hw *hw) 2491 { 2492 int32_t ret_val; 2493 uint16_t phy_data; 2494 2495 if (hw->phy_reset_disable) 2496 return E1000_SUCCESS; 2497 2498 ret_val = em_phy_reset(hw); 2499 if (ret_val) 2500 goto out; 2501 2502 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2503 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2504 if (ret_val) 2505 goto out; 2506 2507 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2508 I82580_CFG_ENABLE_DOWNSHIFT; 2509 2510 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2511 2512 out: 2513 return ret_val; 2514 } 2515 2516 static int32_t 2517 em_copper_link_rtl8211_setup(struct em_hw *hw) 2518 { 2519 int32_t ret_val; 2520 uint16_t phy_data; 2521 2522 DEBUGFUNC("em_copper_link_rtl8211_setup: begin"); 2523 2524 if (!hw) { 2525 return -1; 2526 } 2527 /* SW Reset the PHY so all changes take effect */ 2528 em_phy_hw_reset(hw); 2529 2530 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2531 phy_data = 0; 2532 2533 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 2534 if (ret_val) { 2535 printf("Unable to read RGEPHY_CR register\n"); 2536 return ret_val; 2537 } 2538 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id, 2539 hw->phy_addr, phy_data); 2540 phy_data |= RGEPHY_CR_ASSERT_CRS; 2541 2542 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 2543 if (ret_val) { 2544 printf("Unable to write RGEPHY_CR register\n"); 2545 return ret_val; 2546 } 2547 2548 phy_data = 0; /* LED Control Register 0x18 */ 2549 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC, &phy_data); 2550 if (ret_val) { 2551 printf("Unable to read RGEPHY_LC register\n"); 2552 return ret_val; 2553 } 2554 2555 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */ 2556 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2557 if (ret_val) { 2558 printf("Unable to write RGEPHY_LC register\n"); 2559 return ret_val; 2560 } 2561 /* LED Control and Definition Register 0x11, PHY spec status reg */ 2562 phy_data = 0; 2563 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2564 if (ret_val) { 2565 printf("Unable to read RGEPHY_SR register\n"); 2566 return ret_val; 2567 } 2568 2569 phy_data |= 0x0010; /* LED active Low */ 2570 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR, phy_data); 2571 if (ret_val) { 2572 printf("Unable to write RGEPHY_SR register\n"); 2573 return ret_val; 2574 } 2575 2576 phy_data = 0; 2577 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR, &phy_data); 2578 if (ret_val) { 2579 printf("Unable to read RGEPHY_SR register\n"); 2580 return ret_val; 2581 } 2582 2583 /* Switch to Page2 */ 2584 phy_data = RGEPHY_PS_PAGE_2; 2585 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2586 if (ret_val) { 2587 printf("Unable to write PHY RGEPHY_PS register\n"); 2588 return ret_val; 2589 } 2590 2591 phy_data = 0x0000; 2592 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2593 if (ret_val) { 2594 printf("Unable to write RGEPHY_LC_P2 register\n"); 2595 return ret_val; 2596 } 2597 usec_delay(5); 2598 2599 2600 /* LED Configuration Control Reg for setting for 0x1A Register */ 2601 phy_data = 0; 2602 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2603 if (ret_val) { 2604 printf("Unable to read RGEPHY_LC_P2 register\n"); 2605 return ret_val; 2606 } 2607 2608 phy_data &= 0xF000; 2609 phy_data |= 0x0F24; 2610 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P2, phy_data); 2611 if (ret_val) { 2612 printf("Unable to write RGEPHY_LC_P2 register\n"); 2613 return ret_val; 2614 } 2615 phy_data = 0; 2616 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P2, &phy_data); 2617 if (ret_val) { 2618 printf("Unable to read RGEPHY_LC_P2 register\n"); 2619 return ret_val; 2620 } 2621 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data); 2622 2623 2624 /* After setting Page2, go back to Page 0 */ 2625 phy_data = 0; 2626 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS, phy_data); 2627 if (ret_val) { 2628 printf("Unable to write PHY RGEPHY_PS register\n"); 2629 return ret_val; 2630 } 2631 2632 /* pulse streching= 42-84ms, blink rate=84mm */ 2633 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | 2634 RGEPHY_LC_DUPLEX | RGEPHY_LC_RX; 2635 2636 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); 2637 if (ret_val) { 2638 printf("Unable to write RGEPHY_LC register\n"); 2639 return ret_val; 2640 } 2641 return E1000_SUCCESS; 2642 } 2643 2644 /****************************************************************************** 2645 * Setup auto-negotiation and flow control advertisements, 2646 * and then perform auto-negotiation. 2647 * 2648 * hw - Struct containing variables accessed by shared code 2649 *****************************************************************************/ 2650 int32_t 2651 em_copper_link_autoneg(struct em_hw *hw) 2652 { 2653 int32_t ret_val; 2654 uint16_t phy_data; 2655 DEBUGFUNC("em_copper_link_autoneg"); 2656 /* 2657 * Perform some bounds checking on the hw->autoneg_advertised 2658 * parameter. If this variable is zero, then set it to the default. 2659 */ 2660 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2661 /* 2662 * If autoneg_advertised is zero, we assume it was not defaulted by 2663 * the calling code so we set to advertise full capability. 2664 */ 2665 if (hw->autoneg_advertised == 0) 2666 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2667 2668 /* IFE phy only supports 10/100 */ 2669 if (hw->phy_type == em_phy_ife) 2670 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2671 2672 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2673 ret_val = em_phy_setup_autoneg(hw); 2674 if (ret_val) { 2675 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2676 return ret_val; 2677 } 2678 DEBUGOUT("Restarting Auto-Neg\n"); 2679 /* 2680 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2681 * the Auto Neg Restart bit in the PHY control register. 2682 */ 2683 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2684 if (ret_val) 2685 return ret_val; 2686 2687 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2688 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2689 if (ret_val) 2690 return ret_val; 2691 /* 2692 * Does the user want to wait for Auto-Neg to complete here, or check 2693 * at a later time (for example, callback routine). 2694 */ 2695 if (hw->wait_autoneg_complete) { 2696 ret_val = em_wait_autoneg(hw); 2697 if (ret_val) { 2698 DEBUGOUT("Error while waiting for autoneg to complete\n" 2699 ); 2700 return ret_val; 2701 } 2702 } 2703 hw->get_link_status = TRUE; 2704 2705 return E1000_SUCCESS; 2706 } 2707 2708 /****************************************************************************** 2709 * Config the MAC and the PHY after link is up. 2710 * 1) Set up the MAC to the current PHY speed/duplex 2711 * if we are on 82543. If we 2712 * are on newer silicon, we only need to configure 2713 * collision distance in the Transmit Control Register. 2714 * 2) Set up flow control on the MAC to that established with 2715 * the link partner. 2716 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2717 * 2718 * hw - Struct containing variables accessed by shared code 2719 *****************************************************************************/ 2720 int32_t 2721 em_copper_link_postconfig(struct em_hw *hw) 2722 { 2723 int32_t ret_val; 2724 DEBUGFUNC("em_copper_link_postconfig"); 2725 2726 if (hw->mac_type >= em_82544 && 2727 hw->mac_type != em_icp_xxxx) { 2728 em_config_collision_dist(hw); 2729 } else { 2730 ret_val = em_config_mac_to_phy(hw); 2731 if (ret_val) { 2732 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2733 return ret_val; 2734 } 2735 } 2736 ret_val = em_config_fc_after_link_up(hw); 2737 if (ret_val) { 2738 DEBUGOUT("Error Configuring Flow Control\n"); 2739 return ret_val; 2740 } 2741 /* Config DSP to improve Giga link quality */ 2742 if (hw->phy_type == em_phy_igp) { 2743 ret_val = em_config_dsp_after_link_change(hw, TRUE); 2744 if (ret_val) { 2745 DEBUGOUT("Error Configuring DSP after link up\n"); 2746 return ret_val; 2747 } 2748 } 2749 return E1000_SUCCESS; 2750 } 2751 2752 /****************************************************************************** 2753 * Detects which PHY is present and setup the speed and duplex 2754 * 2755 * hw - Struct containing variables accessed by shared code 2756 *****************************************************************************/ 2757 static int32_t 2758 em_setup_copper_link(struct em_hw *hw) 2759 { 2760 int32_t ret_val; 2761 uint16_t i; 2762 uint16_t phy_data; 2763 uint16_t reg_data; 2764 DEBUGFUNC("em_setup_copper_link"); 2765 2766 switch (hw->mac_type) { 2767 case em_80003es2lan: 2768 case em_ich8lan: 2769 case em_ich9lan: 2770 case em_ich10lan: 2771 case em_pchlan: 2772 case em_pch2lan: 2773 case em_pch_lpt: 2774 case em_pch_spt: 2775 /* 2776 * Set the mac to wait the maximum time between each 2777 * iteration and increase the max iterations when polling the 2778 * phy; this fixes erroneous timeouts at 10Mbps. 2779 */ 2780 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2781 if (ret_val) 2782 return ret_val; 2783 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 2784 ®_data); 2785 if (ret_val) 2786 return ret_val; 2787 reg_data |= 0x3F; 2788 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 2789 reg_data); 2790 if (ret_val) 2791 return ret_val; 2792 default: 2793 break; 2794 } 2795 2796 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2797 ret_val = em_copper_link_preconfig(hw); 2798 if (ret_val) 2799 return ret_val; 2800 2801 switch (hw->mac_type) { 2802 case em_80003es2lan: 2803 /* Kumeran registers are written-only */ 2804 reg_data = 2805 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2806 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2807 ret_val = em_write_kmrn_reg(hw, 2808 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2809 if (ret_val) 2810 return ret_val; 2811 break; 2812 default: 2813 break; 2814 } 2815 2816 if (hw->phy_type == em_phy_igp || 2817 hw->phy_type == em_phy_igp_3 || 2818 hw->phy_type == em_phy_igp_2) { 2819 ret_val = em_copper_link_igp_setup(hw); 2820 if (ret_val) 2821 return ret_val; 2822 } else if (hw->phy_type == em_phy_m88 || 2823 hw->phy_type == em_phy_bm || 2824 hw->phy_type == em_phy_oem || 2825 hw->phy_type == em_phy_82578) { 2826 ret_val = em_copper_link_mgp_setup(hw); 2827 if (ret_val) 2828 return ret_val; 2829 } else if (hw->phy_type == em_phy_gg82563) { 2830 ret_val = em_copper_link_ggp_setup(hw); 2831 if (ret_val) 2832 return ret_val; 2833 } else if (hw->phy_type == em_phy_82577 || 2834 hw->phy_type == em_phy_82579 || 2835 hw->phy_type == em_phy_i217) { 2836 ret_val = em_copper_link_82577_setup(hw); 2837 if (ret_val) 2838 return ret_val; 2839 } else if (hw->phy_type == em_phy_82580) { 2840 ret_val = em_copper_link_82580_setup(hw); 2841 if (ret_val) 2842 return ret_val; 2843 } else if (hw->phy_type == em_phy_rtl8211) { 2844 ret_val = em_copper_link_rtl8211_setup(hw); 2845 if (ret_val) 2846 return ret_val; 2847 } 2848 if (hw->autoneg) { 2849 /* 2850 * Setup autoneg and flow control advertisement and perform 2851 * autonegotiation 2852 */ 2853 ret_val = em_copper_link_autoneg(hw); 2854 if (ret_val) 2855 return ret_val; 2856 } else { 2857 /* 2858 * PHY will be set to 10H, 10F, 100H,or 100F depending on 2859 * value from forced_speed_duplex. 2860 */ 2861 DEBUGOUT("Forcing speed and duplex\n"); 2862 ret_val = em_phy_force_speed_duplex(hw); 2863 if (ret_val) { 2864 DEBUGOUT("Error Forcing Speed and Duplex\n"); 2865 return ret_val; 2866 } 2867 } 2868 /* 2869 * Check link status. Wait up to 100 microseconds for link to become 2870 * valid. 2871 */ 2872 for (i = 0; i < 10; i++) { 2873 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2874 if (ret_val) 2875 return ret_val; 2876 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2877 if (ret_val) 2878 return ret_val; 2879 2880 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 2881 2882 if (phy_data & MII_SR_LINK_STATUS) { 2883 /* Config the MAC and PHY after link is up */ 2884 ret_val = em_copper_link_postconfig(hw); 2885 if (ret_val) 2886 return ret_val; 2887 2888 DEBUGOUT("Valid link established!!!\n"); 2889 return E1000_SUCCESS; 2890 } 2891 usec_delay(10); 2892 } 2893 2894 DEBUGOUT("Unable to establish link!!!\n"); 2895 return E1000_SUCCESS; 2896 } 2897 2898 /****************************************************************************** 2899 * Configure the MAC-to-PHY interface for 10/100Mbps 2900 * 2901 * hw - Struct containing variables accessed by shared code 2902 *****************************************************************************/ 2903 static int32_t 2904 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 2905 { 2906 int32_t ret_val = E1000_SUCCESS; 2907 uint32_t tipg; 2908 uint16_t reg_data; 2909 DEBUGFUNC("em_configure_kmrn_for_10_100"); 2910 2911 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 2912 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2913 reg_data); 2914 if (ret_val) 2915 return ret_val; 2916 2917 /* Configure Transmit Inter-Packet Gap */ 2918 tipg = E1000_READ_REG(hw, TIPG); 2919 tipg &= ~E1000_TIPG_IPGT_MASK; 2920 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2921 E1000_WRITE_REG(hw, TIPG, tipg); 2922 2923 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2924 2925 if (ret_val) 2926 return ret_val; 2927 2928 if (duplex == HALF_DUPLEX) 2929 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 2930 else 2931 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2932 2933 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2934 2935 return ret_val; 2936 } 2937 2938 static int32_t 2939 em_configure_kmrn_for_1000(struct em_hw *hw) 2940 { 2941 int32_t ret_val = E1000_SUCCESS; 2942 uint16_t reg_data; 2943 uint32_t tipg; 2944 DEBUGFUNC("em_configure_kmrn_for_1000"); 2945 2946 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 2947 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2948 reg_data); 2949 if (ret_val) 2950 return ret_val; 2951 2952 /* Configure Transmit Inter-Packet Gap */ 2953 tipg = E1000_READ_REG(hw, TIPG); 2954 tipg &= ~E1000_TIPG_IPGT_MASK; 2955 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2956 E1000_WRITE_REG(hw, TIPG, tipg); 2957 2958 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2959 2960 if (ret_val) 2961 return ret_val; 2962 2963 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2964 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2965 2966 return ret_val; 2967 } 2968 2969 /****************************************************************************** 2970 * Configures PHY autoneg and flow control advertisement settings 2971 * 2972 * hw - Struct containing variables accessed by shared code 2973 *****************************************************************************/ 2974 int32_t 2975 em_phy_setup_autoneg(struct em_hw *hw) 2976 { 2977 int32_t ret_val; 2978 uint16_t mii_autoneg_adv_reg; 2979 uint16_t mii_1000t_ctrl_reg; 2980 DEBUGFUNC("em_phy_setup_autoneg"); 2981 2982 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2983 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2984 if (ret_val) 2985 return ret_val; 2986 2987 if (hw->phy_type != em_phy_ife) { 2988 /* Read the MII 1000Base-T Control Register (Address 9). */ 2989 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2990 &mii_1000t_ctrl_reg); 2991 if (ret_val) 2992 return ret_val; 2993 } else 2994 mii_1000t_ctrl_reg = 0; 2995 /* 2996 * Need to parse both autoneg_advertised and fc and set up the 2997 * appropriate PHY registers. First we will parse for 2998 * autoneg_advertised software override. Since we can advertise a 2999 * plethora of combinations, we need to check each bit individually. 3000 */ 3001 /* 3002 * First we clear all the 10/100 mb speed bits in the Auto-Neg 3003 * Advertisement Register (Address 4) and the 1000 mb speed bits in 3004 * the 1000Base-T Control Register (Address 9). 3005 */ 3006 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 3007 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 3008 3009 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 3010 3011 /* Do we want to advertise 10 Mb Half Duplex? */ 3012 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 3013 DEBUGOUT("Advertise 10mb Half duplex\n"); 3014 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 3015 } 3016 /* Do we want to advertise 10 Mb Full Duplex? */ 3017 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 3018 DEBUGOUT("Advertise 10mb Full duplex\n"); 3019 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 3020 } 3021 /* Do we want to advertise 100 Mb Half Duplex? */ 3022 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 3023 DEBUGOUT("Advertise 100mb Half duplex\n"); 3024 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 3025 } 3026 /* Do we want to advertise 100 Mb Full Duplex? */ 3027 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 3028 DEBUGOUT("Advertise 100mb Full duplex\n"); 3029 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 3030 } 3031 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 3032 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 3033 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 3034 " denied!\n"); 3035 } 3036 /* Do we want to advertise 1000 Mb Full Duplex? */ 3037 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 3038 DEBUGOUT("Advertise 1000mb Full duplex\n"); 3039 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 3040 if (hw->phy_type == em_phy_ife) { 3041 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 3042 " not supported.\n"); 3043 } 3044 } 3045 /* 3046 * Check for a software override of the flow control settings, and 3047 * setup the PHY advertisement registers accordingly. If 3048 * auto-negotiation is enabled, then software will have to set the 3049 * "PAUSE" bits to the correct value in the Auto-Negotiation 3050 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 3051 * auto-negotiation. 3052 * 3053 * The possible values of the "fc" parameter are: 0: Flow control is 3054 * completely disabled 1: Rx flow control is enabled (we can receive 3055 * pause frames but not send pause frames). 2: Tx flow control is 3056 * enabled (we can send pause frames but we do not support receiving 3057 * pause frames). 3: Both Rx and TX flow control (symmetric) are 3058 * enabled. other: No software override. The flow control 3059 * configuration in the EEPROM is used. 3060 */ 3061 switch (hw->fc) { 3062 case E1000_FC_NONE: /* 0 */ 3063 /* 3064 * Flow control (RX & TX) is completely disabled by a 3065 * software over-ride. 3066 */ 3067 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3068 break; 3069 case E1000_FC_RX_PAUSE:/* 1 */ 3070 /* 3071 * RX Flow control is enabled, and TX Flow control is 3072 * disabled, by a software over-ride. 3073 */ 3074 /* 3075 * Since there really isn't a way to advertise that we are 3076 * capable of RX Pause ONLY, we will advertise that we 3077 * support both symmetric and asymmetric RX PAUSE. Later (in 3078 * em_config_fc_after_link_up) we will disable the hw's 3079 * ability to send PAUSE frames. 3080 */ 3081 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3082 break; 3083 case E1000_FC_TX_PAUSE:/* 2 */ 3084 /* 3085 * TX Flow control is enabled, and RX Flow control is 3086 * disabled, by a software over-ride. 3087 */ 3088 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 3089 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 3090 break; 3091 case E1000_FC_FULL: /* 3 */ 3092 /* 3093 * Flow control (both RX and TX) is enabled by a software 3094 * over-ride. 3095 */ 3096 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 3097 break; 3098 default: 3099 DEBUGOUT("Flow control param set incorrectly\n"); 3100 return -E1000_ERR_CONFIG; 3101 } 3102 3103 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 3104 if (ret_val) 3105 return ret_val; 3106 3107 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 3108 3109 if (hw->phy_type != em_phy_ife) { 3110 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 3111 mii_1000t_ctrl_reg); 3112 if (ret_val) 3113 return ret_val; 3114 } 3115 return E1000_SUCCESS; 3116 } 3117 /****************************************************************************** 3118 * Force PHY speed and duplex settings to hw->forced_speed_duplex 3119 * 3120 * hw - Struct containing variables accessed by shared code 3121 *****************************************************************************/ 3122 static int32_t 3123 em_phy_force_speed_duplex(struct em_hw *hw) 3124 { 3125 uint32_t ctrl; 3126 int32_t ret_val; 3127 uint16_t mii_ctrl_reg; 3128 uint16_t mii_status_reg; 3129 uint16_t phy_data; 3130 uint16_t i; 3131 DEBUGFUNC("em_phy_force_speed_duplex"); 3132 3133 /* Turn off Flow control if we are forcing speed and duplex. */ 3134 hw->fc = E1000_FC_NONE; 3135 3136 DEBUGOUT1("hw->fc = %d\n", hw->fc); 3137 3138 /* Read the Device Control Register. */ 3139 ctrl = E1000_READ_REG(hw, CTRL); 3140 3141 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 3142 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3143 ctrl &= ~(DEVICE_SPEED_MASK); 3144 3145 /* Clear the Auto Speed Detect Enable bit. */ 3146 ctrl &= ~E1000_CTRL_ASDE; 3147 3148 /* Read the MII Control Register. */ 3149 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 3150 if (ret_val) 3151 return ret_val; 3152 3153 /* We need to disable autoneg in order to force link and duplex. */ 3154 3155 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 3156 3157 /* Are we forcing Full or Half Duplex? */ 3158 if (hw->forced_speed_duplex == em_100_full || 3159 hw->forced_speed_duplex == em_10_full) { 3160 /* 3161 * We want to force full duplex so we SET the full duplex 3162 * bits in the Device and MII Control Registers. 3163 */ 3164 ctrl |= E1000_CTRL_FD; 3165 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 3166 DEBUGOUT("Full Duplex\n"); 3167 } else { 3168 /* 3169 * We want to force half duplex so we CLEAR the full duplex 3170 * bits in the Device and MII Control Registers. 3171 */ 3172 ctrl &= ~E1000_CTRL_FD; 3173 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3174 DEBUGOUT("Half Duplex\n"); 3175 } 3176 3177 /* Are we forcing 100Mbps??? */ 3178 if (hw->forced_speed_duplex == em_100_full || 3179 hw->forced_speed_duplex == em_100_half) { 3180 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3181 ctrl |= E1000_CTRL_SPD_100; 3182 mii_ctrl_reg |= MII_CR_SPEED_100; 3183 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3184 DEBUGOUT("Forcing 100mb "); 3185 } else { 3186 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3187 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3188 mii_ctrl_reg |= MII_CR_SPEED_10; 3189 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3190 DEBUGOUT("Forcing 10mb "); 3191 } 3192 3193 em_config_collision_dist(hw); 3194 3195 /* Write the configured values back to the Device Control Reg. */ 3196 E1000_WRITE_REG(hw, CTRL, ctrl); 3197 3198 if ((hw->phy_type == em_phy_m88) || 3199 (hw->phy_type == em_phy_gg82563) || 3200 (hw->phy_type == em_phy_bm) || 3201 (hw->phy_type == em_phy_oem || 3202 (hw->phy_type == em_phy_82578))) { 3203 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3204 &phy_data); 3205 if (ret_val) 3206 return ret_val; 3207 /* 3208 * Clear Auto-Crossover to force MDI manually. M88E1000 3209 * requires MDI forced whenever speed are duplex are forced. 3210 */ 3211 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3212 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3213 phy_data); 3214 if (ret_val) 3215 return ret_val; 3216 3217 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3218 3219 /* Need to reset the PHY or these changes will be ignored */ 3220 mii_ctrl_reg |= MII_CR_RESET; 3221 3222 } 3223 else if (hw->phy_type == em_phy_rtl8211) { 3224 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3225 if(ret_val) { 3226 printf("Unable to read RGEPHY_CR register\n" 3227 ); 3228 return ret_val; 3229 } 3230 3231 /* 3232 * Clear Auto-Crossover to force MDI manually. RTL8211 requires 3233 * MDI forced whenever speed are duplex are forced. 3234 */ 3235 3236 phy_data |= RGEPHY_CR_MDI_MASK; // enable MDIX 3237 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3238 if(ret_val) { 3239 printf("Unable to write RGEPHY_CR register\n"); 3240 return ret_val; 3241 } 3242 mii_ctrl_reg |= MII_CR_RESET; 3243 3244 } 3245 /* Disable MDI-X support for 10/100 */ 3246 else if (hw->phy_type == em_phy_ife) { 3247 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3248 if (ret_val) 3249 return ret_val; 3250 3251 phy_data &= ~IFE_PMC_AUTO_MDIX; 3252 phy_data &= ~IFE_PMC_FORCE_MDIX; 3253 3254 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3255 if (ret_val) 3256 return ret_val; 3257 } else { 3258 /* 3259 * Clear Auto-Crossover to force MDI manually. IGP requires 3260 * MDI forced whenever speed or duplex are forced. 3261 */ 3262 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3263 &phy_data); 3264 if (ret_val) 3265 return ret_val; 3266 3267 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3268 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3269 3270 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3271 phy_data); 3272 if (ret_val) 3273 return ret_val; 3274 } 3275 3276 /* Write back the modified PHY MII control register. */ 3277 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3278 if (ret_val) 3279 return ret_val; 3280 3281 usec_delay(1); 3282 /* 3283 * The wait_autoneg_complete flag may be a little misleading here. 3284 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3285 * But we do want to delay for a period while forcing only so we 3286 * don't generate false No Link messages. So we will wait here only 3287 * if the user has set wait_autoneg_complete to 1, which is the 3288 * default. 3289 */ 3290 if (hw->wait_autoneg_complete) { 3291 /* We will wait for autoneg to complete. */ 3292 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3293 mii_status_reg = 0; 3294 /* 3295 * We will wait for autoneg to complete or 4.5 seconds to 3296 * expire. 3297 */ 3298 for (i = PHY_FORCE_TIME; i > 0; i--) { 3299 /* 3300 * Read the MII Status Register and wait for Auto-Neg 3301 * Complete bit to be set. 3302 */ 3303 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3304 &mii_status_reg); 3305 if (ret_val) 3306 return ret_val; 3307 3308 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3309 &mii_status_reg); 3310 if (ret_val) 3311 return ret_val; 3312 3313 if (mii_status_reg & MII_SR_LINK_STATUS) 3314 break; 3315 msec_delay(100); 3316 } 3317 if ((i == 0) && 3318 ((hw->phy_type == em_phy_m88) || 3319 (hw->phy_type == em_phy_gg82563) || 3320 (hw->phy_type == em_phy_bm))) { 3321 /* 3322 * We didn't get link. Reset the DSP and wait again 3323 * for link. 3324 */ 3325 ret_val = em_phy_reset_dsp(hw); 3326 if (ret_val) { 3327 DEBUGOUT("Error Resetting PHY DSP\n"); 3328 return ret_val; 3329 } 3330 } 3331 /* 3332 * This loop will early-out if the link condition has been 3333 * met. 3334 */ 3335 for (i = PHY_FORCE_TIME; i > 0; i--) { 3336 if (mii_status_reg & MII_SR_LINK_STATUS) 3337 break; 3338 msec_delay(100); 3339 /* 3340 * Read the MII Status Register and wait for Auto-Neg 3341 * Complete bit to be set. 3342 */ 3343 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3344 &mii_status_reg); 3345 if (ret_val) 3346 return ret_val; 3347 3348 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3349 &mii_status_reg); 3350 if (ret_val) 3351 return ret_val; 3352 } 3353 } 3354 if (hw->phy_type == em_phy_m88 || 3355 hw->phy_type == em_phy_bm || 3356 hw->phy_type == em_phy_oem) { 3357 /* 3358 * Because we reset the PHY above, we need to re-force TX_CLK 3359 * in the Extended PHY Specific Control Register to 25MHz 3360 * clock. This value defaults back to a 2.5MHz clock when 3361 * the PHY is reset. 3362 */ 3363 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3364 &phy_data); 3365 if (ret_val) 3366 return ret_val; 3367 3368 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3369 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3370 phy_data); 3371 if (ret_val) 3372 return ret_val; 3373 /* 3374 * In addition, because of the s/w reset above, we need to 3375 * enable CRS on TX. This must be set for both full and half 3376 * duplex operation. 3377 */ 3378 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3379 &phy_data); 3380 if (ret_val) 3381 return ret_val; 3382 3383 if (hw->phy_id == M88E1141_E_PHY_ID) 3384 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3385 else 3386 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3387 3388 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3389 phy_data); 3390 if (ret_val) 3391 return ret_val; 3392 3393 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3394 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3395 hw->forced_speed_duplex == em_10_half)) { 3396 ret_val = em_polarity_reversal_workaround(hw); 3397 if (ret_val) 3398 return ret_val; 3399 } 3400 } else if (hw->phy_type == em_phy_rtl8211) { 3401 /* 3402 * In addition, because of the s/w reset above, we need to enable 3403 * CRX on TX. This must be set for both full and half duplex 3404 * operation. 3405 */ 3406 3407 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR, &phy_data); 3408 if(ret_val) { 3409 printf("Unable to read RGEPHY_CR register\n"); 3410 return ret_val; 3411 } 3412 3413 phy_data &= ~RGEPHY_CR_ASSERT_CRS; 3414 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR, phy_data); 3415 if(ret_val) { 3416 printf("Unable to write RGEPHY_CR register\n"); 3417 return ret_val; 3418 } 3419 } else if (hw->phy_type == em_phy_gg82563) { 3420 /* 3421 * The TX_CLK of the Extended PHY Specific Control Register 3422 * defaults to 2.5MHz on a reset. We need to re-force it 3423 * back to 25MHz, if we're not in a forced 10/duplex 3424 * configuration. 3425 */ 3426 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3427 &phy_data); 3428 if (ret_val) 3429 return ret_val; 3430 3431 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3432 if ((hw->forced_speed_duplex == em_10_full) || 3433 (hw->forced_speed_duplex == em_10_half)) 3434 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3435 else 3436 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3437 3438 /* Also due to the reset, we need to enable CRS on Tx. */ 3439 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3440 3441 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3442 phy_data); 3443 if (ret_val) 3444 return ret_val; 3445 } 3446 return E1000_SUCCESS; 3447 } 3448 3449 /****************************************************************************** 3450 * Sets the collision distance in the Transmit Control register 3451 * 3452 * hw - Struct containing variables accessed by shared code 3453 * 3454 * Link should have been established previously. Reads the speed and duplex 3455 * information from the Device Status register. 3456 *****************************************************************************/ 3457 void 3458 em_config_collision_dist(struct em_hw *hw) 3459 { 3460 uint32_t tctl, coll_dist; 3461 DEBUGFUNC("em_config_collision_dist"); 3462 3463 if (hw->mac_type < em_82543) 3464 coll_dist = E1000_COLLISION_DISTANCE_82542; 3465 else 3466 coll_dist = E1000_COLLISION_DISTANCE; 3467 3468 tctl = E1000_READ_REG(hw, TCTL); 3469 3470 tctl &= ~E1000_TCTL_COLD; 3471 tctl |= coll_dist << E1000_COLD_SHIFT; 3472 3473 E1000_WRITE_REG(hw, TCTL, tctl); 3474 E1000_WRITE_FLUSH(hw); 3475 } 3476 3477 /****************************************************************************** 3478 * Sets MAC speed and duplex settings to reflect the those in the PHY 3479 * 3480 * hw - Struct containing variables accessed by shared code 3481 * mii_reg - data to write to the MII control register 3482 * 3483 * The contents of the PHY register containing the needed information need to 3484 * be passed in. 3485 *****************************************************************************/ 3486 static int32_t 3487 em_config_mac_to_phy(struct em_hw *hw) 3488 { 3489 uint32_t ctrl; 3490 int32_t ret_val; 3491 uint16_t phy_data; 3492 DEBUGFUNC("em_config_mac_to_phy"); 3493 /* 3494 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3495 * speed/duplex configuration. 3496 */ 3497 if (hw->mac_type >= em_82544 3498 && hw->mac_type != em_icp_xxxx) 3499 return E1000_SUCCESS; 3500 /* 3501 * Read the Device Control Register and set the bits to Force Speed 3502 * and Duplex. 3503 */ 3504 ctrl = E1000_READ_REG(hw, CTRL); 3505 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3506 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3507 /* 3508 * Set up duplex in the Device Control and Transmit Control registers 3509 * depending on negotiated values. 3510 */ 3511 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3512 if (ret_val) 3513 return ret_val; 3514 3515 if (phy_data & M88E1000_PSSR_DPLX) 3516 ctrl |= E1000_CTRL_FD; 3517 else 3518 ctrl &= ~E1000_CTRL_FD; 3519 3520 em_config_collision_dist(hw); 3521 /* 3522 * Set up speed in the Device Control register depending on 3523 * negotiated values. 3524 */ 3525 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3526 ctrl |= E1000_CTRL_SPD_1000; 3527 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3528 ctrl |= E1000_CTRL_SPD_100; 3529 3530 /* Write the configured values back to the Device Control Reg. */ 3531 E1000_WRITE_REG(hw, CTRL, ctrl); 3532 return E1000_SUCCESS; 3533 } 3534 3535 /****************************************************************************** 3536 * Forces the MAC's flow control settings. 3537 * 3538 * hw - Struct containing variables accessed by shared code 3539 * 3540 * Sets the TFCE and RFCE bits in the device control register to reflect 3541 * the adapter settings. TFCE and RFCE need to be explicitly set by 3542 * software when a Copper PHY is used because autonegotiation is managed 3543 * by the PHY rather than the MAC. Software must also configure these 3544 * bits when link is forced on a fiber connection. 3545 *****************************************************************************/ 3546 int32_t 3547 em_force_mac_fc(struct em_hw *hw) 3548 { 3549 uint32_t ctrl; 3550 DEBUGFUNC("em_force_mac_fc"); 3551 3552 /* Get the current configuration of the Device Control Register */ 3553 ctrl = E1000_READ_REG(hw, CTRL); 3554 /* 3555 * Because we didn't get link via the internal auto-negotiation 3556 * mechanism (we either forced link or we got link via PHY auto-neg), 3557 * we have to manually enable/disable transmit an receive flow 3558 * control. 3559 * 3560 * The "Case" statement below enables/disable flow control according to 3561 * the "hw->fc" parameter. 3562 * 3563 * The possible values of the "fc" parameter are: 0: Flow control is 3564 * completely disabled 1: Rx flow control is enabled (we can receive 3565 * pause frames but not send pause frames). 2: Tx flow control is 3566 * enabled (we can send pause frames frames but we do not receive 3567 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3568 * enabled. other: No other values should be possible at this point. 3569 */ 3570 3571 switch (hw->fc) { 3572 case E1000_FC_NONE: 3573 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3574 break; 3575 case E1000_FC_RX_PAUSE: 3576 ctrl &= (~E1000_CTRL_TFCE); 3577 ctrl |= E1000_CTRL_RFCE; 3578 break; 3579 case E1000_FC_TX_PAUSE: 3580 ctrl &= (~E1000_CTRL_RFCE); 3581 ctrl |= E1000_CTRL_TFCE; 3582 break; 3583 case E1000_FC_FULL: 3584 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3585 break; 3586 default: 3587 DEBUGOUT("Flow control param set incorrectly\n"); 3588 return -E1000_ERR_CONFIG; 3589 } 3590 3591 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3592 if (hw->mac_type == em_82542_rev2_0) 3593 ctrl &= (~E1000_CTRL_TFCE); 3594 3595 E1000_WRITE_REG(hw, CTRL, ctrl); 3596 return E1000_SUCCESS; 3597 } 3598 /****************************************************************************** 3599 * Configures flow control settings after link is established 3600 * 3601 * hw - Struct containing variables accessed by shared code 3602 * 3603 * Should be called immediately after a valid link has been established. 3604 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3605 * and autonegotiation is enabled, the MAC flow control settings will be set 3606 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3607 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3608 *****************************************************************************/ 3609 STATIC int32_t 3610 em_config_fc_after_link_up(struct em_hw *hw) 3611 { 3612 int32_t ret_val; 3613 uint16_t mii_status_reg; 3614 uint16_t mii_nway_adv_reg; 3615 uint16_t mii_nway_lp_ability_reg; 3616 uint16_t speed; 3617 uint16_t duplex; 3618 DEBUGFUNC("em_config_fc_after_link_up"); 3619 /* 3620 * Check for the case where we have fiber media and auto-neg failed 3621 * so we had to force link. In this case, we need to force the 3622 * configuration of the MAC to match the "fc" parameter. 3623 */ 3624 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3625 || ((hw->media_type == em_media_type_internal_serdes) && 3626 (hw->autoneg_failed)) || 3627 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3628 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3629 ret_val = em_force_mac_fc(hw); 3630 if (ret_val) { 3631 DEBUGOUT("Error forcing flow control settings\n"); 3632 return ret_val; 3633 } 3634 } 3635 /* 3636 * Check for the case where we have copper media and auto-neg is 3637 * enabled. In this case, we need to check and see if Auto-Neg has 3638 * completed, and if so, how the PHY and link partner has flow 3639 * control configured. 3640 */ 3641 if ((hw->media_type == em_media_type_copper || 3642 (hw->media_type == em_media_type_oem)) && 3643 hw->autoneg) { 3644 /* 3645 * Read the MII Status Register and check to see if AutoNeg 3646 * has completed. We read this twice because this reg has 3647 * some "sticky" (latched) bits. 3648 */ 3649 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3650 if (ret_val) 3651 return ret_val; 3652 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3653 if (ret_val) 3654 return ret_val; 3655 3656 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3657 /* 3658 * The AutoNeg process has completed, so we now need 3659 * to read both the Auto Negotiation Advertisement 3660 * Register (Address 4) and the Auto_Negotiation Base 3661 * Page Ability Register (Address 5) to determine how 3662 * flow control was negotiated. 3663 */ 3664 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3665 &mii_nway_adv_reg); 3666 if (ret_val) 3667 return ret_val; 3668 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3669 &mii_nway_lp_ability_reg); 3670 if (ret_val) 3671 return ret_val; 3672 /* 3673 * Two bits in the Auto Negotiation Advertisement 3674 * Register (Address 4) and two bits in the Auto 3675 * Negotiation Base Page Ability Register (Address 5) 3676 * determine flow control for both the PHY and the 3677 * link partner. The following table, taken out of 3678 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3679 * describes these PAUSE resolution bits and how flow 3680 * control is determined based upon these settings. 3681 * NOTE: DC = Don't Care 3682 * 3683 * LOCAL DEVICE | LINK PARTNER | 3684 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3685 * -------|---------|-------|---------|--------------- 3686 * 0 | 0 | DC | DC | em_fc_none 3687 * 0 | 1 | 0 | DC | em_fc_none 3688 * 0 | 1 | 1 | 0 | em_fc_none 3689 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3690 * 1 | 0 | 0 | DC | em_fc_none 3691 * 1 | DC | 1 | DC | em_fc_full 3692 * 1 | 1 | 0 | 0 | em_fc_none 3693 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3694 * 3695 */ 3696 /* 3697 * Are both PAUSE bits set to 1? If so, this implies 3698 * Symmetric Flow Control is enabled at both ends. 3699 * The ASM_DIR bits are irrelevant per the spec. 3700 * 3701 * For Symmetric Flow Control: 3702 * 3703 * LOCAL DEVICE | LINK PARTNER 3704 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3705 * -------|---------|-------|---------|--------------- 3706 * 1 | DC | 1 | DC | em_fc_full 3707 * 3708 */ 3709 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3710 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3711 /* 3712 * Now we need to check if the user selected 3713 * RX ONLY of pause frames. In this case, we 3714 * had to advertise FULL flow control because 3715 * we could not advertise RX ONLY. Hence, we 3716 * must now check to see if we need to turn 3717 * OFF the TRANSMISSION of PAUSE frames. 3718 */ 3719 if (hw->original_fc == E1000_FC_FULL) { 3720 hw->fc = E1000_FC_FULL; 3721 DEBUGOUT("Flow Control = FULL.\n"); 3722 } else { 3723 hw->fc = E1000_FC_RX_PAUSE; 3724 DEBUGOUT("Flow Control = RX PAUSE" 3725 " frames only.\n"); 3726 } 3727 } 3728 /* 3729 * For receiving PAUSE frames ONLY. 3730 * 3731 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3732 * PAUSE | ASM_DIR | Result 3733 * -------|---------|-------|---------|--------------- 3734 * ----- 0 | 1 | 1 | 1 | 3735 * em_fc_tx_pause 3736 * 3737 */ 3738 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3739 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3740 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3741 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3742 hw->fc = E1000_FC_TX_PAUSE; 3743 DEBUGOUT("Flow Control = TX PAUSE frames only." 3744 "\n"); 3745 } 3746 /* 3747 * For transmitting PAUSE frames ONLY. 3748 * 3749 * LOCAL DEVICE | LINK PARTNER 3750 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3751 * -------|---------|-------|---------|--------------- 3752 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3753 * 3754 */ 3755 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3756 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3757 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3758 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3759 hw->fc = E1000_FC_RX_PAUSE; 3760 DEBUGOUT("Flow Control = RX PAUSE frames only." 3761 "\n"); 3762 } 3763 /* 3764 * Per the IEEE spec, at this point flow control 3765 * should be disabled. However, we want to consider 3766 * that we could be connected to a legacy switch that 3767 * doesn't advertise desired flow control, but can be 3768 * forced on the link partner. So if we advertised 3769 * no flow control, that is what we will resolve to. 3770 * If we advertised some kind of receive capability 3771 * (Rx Pause Only or Full Flow Control) and the link 3772 * partner advertised none, we will configure 3773 * ourselves to enable Rx Flow Control only. We can 3774 * do this safely for two reasons: If the link 3775 * partner really didn't want flow control enabled, 3776 * and we enable Rx, no harm done since we won't be 3777 * receiving any PAUSE frames anyway. If the intent 3778 * on the link partner was to have flow control 3779 * enabled, then by us enabling RX only, we can at 3780 * least receive pause frames and process them. This 3781 * is a good idea because in most cases, since we are 3782 * predominantly a server NIC, more times than not we 3783 * will be asked to delay transmission of packets 3784 * than asking our link partner to pause transmission 3785 * of frames. 3786 */ 3787 else if ((hw->original_fc == E1000_FC_NONE || 3788 hw->original_fc == E1000_FC_TX_PAUSE) || 3789 hw->fc_strict_ieee) { 3790 hw->fc = E1000_FC_NONE; 3791 DEBUGOUT("Flow Control = NONE.\n"); 3792 } else { 3793 hw->fc = E1000_FC_RX_PAUSE; 3794 DEBUGOUT("Flow Control = RX PAUSE frames only." 3795 "\n"); 3796 } 3797 /* 3798 * Now we need to do one last check... If we auto- 3799 * negotiated to HALF DUPLEX, flow control should not 3800 * be enabled per IEEE 802.3 spec. 3801 */ 3802 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3803 if (ret_val) { 3804 DEBUGOUT("Error getting link speed and duplex" 3805 "\n"); 3806 return ret_val; 3807 } 3808 if (duplex == HALF_DUPLEX) 3809 hw->fc = E1000_FC_NONE; 3810 /* 3811 * Now we call a subroutine to actually force the MAC 3812 * controller to use the correct flow control 3813 * settings. 3814 */ 3815 ret_val = em_force_mac_fc(hw); 3816 if (ret_val) { 3817 DEBUGOUT("Error forcing flow control settings" 3818 "\n"); 3819 return ret_val; 3820 } 3821 } else { 3822 DEBUGOUT("Copper PHY and Auto Neg has not completed." 3823 "\n"); 3824 } 3825 } 3826 return E1000_SUCCESS; 3827 } 3828 /****************************************************************************** 3829 * Checks to see if the link status of the hardware has changed. 3830 * 3831 * hw - Struct containing variables accessed by shared code 3832 * 3833 * Called by any function that needs to check the link status of the adapter. 3834 *****************************************************************************/ 3835 int32_t 3836 em_check_for_link(struct em_hw *hw) 3837 { 3838 uint32_t rxcw = 0; 3839 uint32_t ctrl; 3840 uint32_t status; 3841 uint32_t rctl; 3842 uint32_t icr; 3843 uint32_t signal = 0; 3844 int32_t ret_val; 3845 uint16_t phy_data; 3846 DEBUGFUNC("em_check_for_link"); 3847 uint16_t speed, duplex; 3848 3849 if (hw->mac_type >= em_82575 && 3850 hw->media_type != em_media_type_copper) { 3851 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 3852 &duplex); 3853 hw->get_link_status = hw->serdes_link_down; 3854 3855 return (ret_val); 3856 } 3857 3858 ctrl = E1000_READ_REG(hw, CTRL); 3859 status = E1000_READ_REG(hw, STATUS); 3860 /* 3861 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 3862 * be set when the optics detect a signal. On older adapters, it will 3863 * be cleared when there is a signal. This applies to fiber media 3864 * only. 3865 */ 3866 if ((hw->media_type == em_media_type_fiber) || 3867 (hw->media_type == em_media_type_internal_serdes)) { 3868 rxcw = E1000_READ_REG(hw, RXCW); 3869 3870 if (hw->media_type == em_media_type_fiber) { 3871 signal = (hw->mac_type > em_82544) ? 3872 E1000_CTRL_SWDPIN1 : 0; 3873 if (status & E1000_STATUS_LU) 3874 hw->get_link_status = FALSE; 3875 } 3876 } 3877 /* 3878 * If we have a copper PHY then we only want to go out to the PHY 3879 * registers to see if Auto-Neg has completed and/or if our link 3880 * status has changed. The get_link_status flag will be set if we 3881 * receive a Link Status Change interrupt or we have Rx Sequence 3882 * Errors. 3883 */ 3884 if ((hw->media_type == em_media_type_copper || 3885 (hw->media_type == em_media_type_oem)) && 3886 hw->get_link_status) { 3887 /* 3888 * First we want to see if the MII Status Register reports 3889 * link. If so, then we want to get the current speed/duplex 3890 * of the PHY. Read the register twice since the link bit is 3891 * sticky. 3892 */ 3893 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3894 if (ret_val) 3895 return ret_val; 3896 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3897 if (ret_val) 3898 return ret_val; 3899 3900 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3901 3902 if (hw->mac_type == em_pchlan) { 3903 ret_val = em_k1_gig_workaround_hv(hw, 3904 hw->icp_xxxx_is_link_up); 3905 if (ret_val) 3906 return ret_val; 3907 } 3908 3909 if (phy_data & MII_SR_LINK_STATUS) { 3910 hw->get_link_status = FALSE; 3911 3912 if (hw->phy_type == em_phy_82578) { 3913 ret_val = em_link_stall_workaround_hv(hw); 3914 if (ret_val) 3915 return ret_val; 3916 } 3917 3918 if (hw->mac_type == em_pch2lan) { 3919 ret_val = em_k1_workaround_lv(hw); 3920 if (ret_val) 3921 return ret_val; 3922 } 3923 /* Work-around I218 hang issue */ 3924 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 3925 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 3926 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 3927 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 3928 ret_val = em_k1_workaround_lpt_lp(hw, 3929 hw->icp_xxxx_is_link_up); 3930 if (ret_val) 3931 return ret_val; 3932 } 3933 3934 /* 3935 * Check if there was DownShift, must be checked 3936 * immediately after link-up 3937 */ 3938 em_check_downshift(hw); 3939 3940 /* Enable/Disable EEE after link up */ 3941 if (hw->mac_type == em_pch2lan || 3942 hw->mac_type == em_pch_lpt || 3943 hw->mac_type == em_pch_spt) { 3944 ret_val = em_set_eee_pchlan(hw); 3945 if (ret_val) 3946 return ret_val; 3947 } 3948 3949 /* 3950 * If we are on 82544 or 82543 silicon and 3951 * speed/duplex are forced to 10H or 10F, then we 3952 * will implement the polarity reversal workaround. 3953 * We disable interrupts first, and upon returning, 3954 * place the devices interrupt state to its previous 3955 * value except for the link status change interrupt 3956 * which will happen due to the execution of this 3957 * workaround. 3958 */ 3959 if ((hw->mac_type == em_82544 || 3960 hw->mac_type == em_82543) && (!hw->autoneg) && 3961 (hw->forced_speed_duplex == em_10_full || 3962 hw->forced_speed_duplex == em_10_half)) { 3963 E1000_WRITE_REG(hw, IMC, 0xffffffff); 3964 ret_val = em_polarity_reversal_workaround(hw); 3965 icr = E1000_READ_REG(hw, ICR); 3966 E1000_WRITE_REG(hw, ICS, 3967 (icr & ~E1000_ICS_LSC)); 3968 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 3969 } 3970 } else { 3971 /* No link detected */ 3972 em_config_dsp_after_link_change(hw, FALSE); 3973 return 0; 3974 } 3975 /* 3976 * If we are forcing speed/duplex, then we simply return 3977 * since we have already determined whether we have link or 3978 * not. 3979 */ 3980 if (!hw->autoneg) 3981 return -E1000_ERR_CONFIG; 3982 3983 /* optimize the dsp settings for the igp phy */ 3984 em_config_dsp_after_link_change(hw, TRUE); 3985 /* 3986 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 3987 * have Si on board that is 82544 or newer, Auto Speed 3988 * Detection takes care of MAC speed/duplex configuration. 3989 * So we only need to configure Collision Distance in the 3990 * MAC. Otherwise, we need to force speed/duplex on the MAC 3991 * to the current PHY speed/duplex settings. 3992 */ 3993 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) { 3994 em_config_collision_dist(hw); 3995 } else { 3996 ret_val = em_config_mac_to_phy(hw); 3997 if (ret_val) { 3998 DEBUGOUT("Error configuring MAC to PHY" 3999 " settings\n"); 4000 return ret_val; 4001 } 4002 } 4003 /* 4004 * Configure Flow Control now that Auto-Neg has completed. 4005 * First, we need to restore the desired flow control 4006 * settings because we may have had to re-autoneg with a 4007 * different link partner. 4008 */ 4009 ret_val = em_config_fc_after_link_up(hw); 4010 if (ret_val) { 4011 DEBUGOUT("Error configuring flow control\n"); 4012 return ret_val; 4013 } 4014 /* 4015 * At this point we know that we are on copper and we have 4016 * auto-negotiated link. These are conditions for checking 4017 * the link partner capability register. We use the link 4018 * speed to determine if TBI compatibility needs to be turned 4019 * on or off. If the link is not at gigabit speed, then TBI 4020 * compatibility is not needed. If we are at gigabit speed, 4021 * we turn on TBI compatibility. 4022 */ 4023 if (hw->tbi_compatibility_en) { 4024 uint16_t speed, duplex; 4025 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 4026 if (ret_val) { 4027 DEBUGOUT("Error getting link speed and duplex" 4028 "\n"); 4029 return ret_val; 4030 } 4031 if (speed != SPEED_1000) { 4032 /* 4033 * If link speed is not set to gigabit speed, 4034 * we do not need to enable TBI 4035 * compatibility. 4036 */ 4037 if (hw->tbi_compatibility_on) { 4038 /* 4039 * If we previously were in the mode, 4040 * turn it off. 4041 */ 4042 rctl = E1000_READ_REG(hw, RCTL); 4043 rctl &= ~E1000_RCTL_SBP; 4044 E1000_WRITE_REG(hw, RCTL, rctl); 4045 hw->tbi_compatibility_on = FALSE; 4046 } 4047 } else { 4048 /* 4049 * If TBI compatibility is was previously 4050 * off, turn it on. For compatibility with a 4051 * TBI link partner, we will store bad 4052 * packets. Some frames have an additional 4053 * byte on the end and will look like CRC 4054 * errors to to the hardware. 4055 */ 4056 if (!hw->tbi_compatibility_on) { 4057 hw->tbi_compatibility_on = TRUE; 4058 rctl = E1000_READ_REG(hw, RCTL); 4059 rctl |= E1000_RCTL_SBP; 4060 E1000_WRITE_REG(hw, RCTL, rctl); 4061 } 4062 } 4063 } 4064 } 4065 /* 4066 * If we don't have link (auto-negotiation failed or link partner 4067 * cannot auto-negotiate), the cable is plugged in (we have signal), 4068 * and our link partner is not trying to auto-negotiate with us (we 4069 * are receiving idles or data), we need to force link up. We also 4070 * need to give auto-negotiation time to complete, in case the cable 4071 * was just plugged in. The autoneg_failed flag does this. 4072 */ 4073 else if ((((hw->media_type == em_media_type_fiber) && 4074 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 4075 (hw->media_type == em_media_type_internal_serdes)) && 4076 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 4077 if (hw->autoneg_failed == 0) { 4078 hw->autoneg_failed = 1; 4079 return 0; 4080 } 4081 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 4082 4083 /* Disable auto-negotiation in the TXCW register */ 4084 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 4085 4086 /* Force link-up and also force full-duplex. */ 4087 ctrl = E1000_READ_REG(hw, CTRL); 4088 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 4089 E1000_WRITE_REG(hw, CTRL, ctrl); 4090 4091 /* Configure Flow Control after forcing link up. */ 4092 ret_val = em_config_fc_after_link_up(hw); 4093 if (ret_val) { 4094 DEBUGOUT("Error configuring flow control\n"); 4095 return ret_val; 4096 } 4097 } 4098 /* 4099 * If we are forcing link and we are receiving /C/ ordered sets, 4100 * re-enable auto-negotiation in the TXCW register and disable forced 4101 * link in the Device Control register in an attempt to 4102 * auto-negotiate with our link partner. 4103 */ 4104 else if (((hw->media_type == em_media_type_fiber) || 4105 (hw->media_type == em_media_type_internal_serdes)) && 4106 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 4107 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 4108 E1000_WRITE_REG(hw, TXCW, hw->txcw); 4109 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 4110 4111 hw->serdes_link_down = FALSE; 4112 } 4113 /* 4114 * If we force link for non-auto-negotiation switch, check link 4115 * status based on MAC synchronization for internal serdes media 4116 * type. 4117 */ 4118 else if ((hw->media_type == em_media_type_internal_serdes) && 4119 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4120 /* SYNCH bit and IV bit are sticky. */ 4121 usec_delay(10); 4122 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 4123 if (!(rxcw & E1000_RXCW_IV)) { 4124 hw->serdes_link_down = FALSE; 4125 DEBUGOUT("SERDES: Link is up.\n"); 4126 } 4127 } else { 4128 hw->serdes_link_down = TRUE; 4129 DEBUGOUT("SERDES: Link is down.\n"); 4130 } 4131 } 4132 if ((hw->media_type == em_media_type_internal_serdes) && 4133 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 4134 hw->serdes_link_down = !(E1000_STATUS_LU & 4135 E1000_READ_REG(hw, STATUS)); 4136 } 4137 return E1000_SUCCESS; 4138 } 4139 4140 int32_t 4141 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 4142 uint16_t *duplex) 4143 { 4144 uint32_t pcs; 4145 4146 hw->serdes_link_down = TRUE; 4147 *speed = 0; 4148 *duplex = 0; 4149 4150 /* 4151 * Read the PCS Status register for link state. For non-copper mode, 4152 * the status register is not accurate. The PCS status register is 4153 * used instead. 4154 */ 4155 pcs = E1000_READ_REG(hw, PCS_LSTAT); 4156 4157 /* 4158 * The link up bit determines when link is up on autoneg. The sync ok 4159 * gets set once both sides sync up and agree upon link. Stable link 4160 * can be determined by checking for both link up and link sync ok 4161 */ 4162 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 4163 hw->serdes_link_down = FALSE; 4164 4165 /* Detect and store PCS speed */ 4166 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 4167 *speed = SPEED_1000; 4168 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 4169 *speed = SPEED_100; 4170 } else { 4171 *speed = SPEED_10; 4172 } 4173 4174 /* Detect and store PCS duplex */ 4175 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 4176 *duplex = FULL_DUPLEX; 4177 } else { 4178 *duplex = HALF_DUPLEX; 4179 } 4180 } 4181 4182 return (0); 4183 } 4184 4185 4186 /****************************************************************************** 4187 * Detects the current speed and duplex settings of the hardware. 4188 * 4189 * hw - Struct containing variables accessed by shared code 4190 * speed - Speed of the connection 4191 * duplex - Duplex setting of the connection 4192 *****************************************************************************/ 4193 int32_t 4194 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 4195 { 4196 uint32_t status; 4197 int32_t ret_val; 4198 uint16_t phy_data; 4199 DEBUGFUNC("em_get_speed_and_duplex"); 4200 4201 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 4202 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 4203 4204 if (hw->mac_type >= em_82543) { 4205 status = E1000_READ_REG(hw, STATUS); 4206 if (status & E1000_STATUS_SPEED_1000) { 4207 *speed = SPEED_1000; 4208 DEBUGOUT("1000 Mbs, "); 4209 } else if (status & E1000_STATUS_SPEED_100) { 4210 *speed = SPEED_100; 4211 DEBUGOUT("100 Mbs, "); 4212 } else { 4213 *speed = SPEED_10; 4214 DEBUGOUT("10 Mbs, "); 4215 } 4216 4217 if (status & E1000_STATUS_FD) { 4218 *duplex = FULL_DUPLEX; 4219 DEBUGOUT("Full Duplex\n"); 4220 } else { 4221 *duplex = HALF_DUPLEX; 4222 DEBUGOUT(" Half Duplex\n"); 4223 } 4224 } else { 4225 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4226 *speed = SPEED_1000; 4227 *duplex = FULL_DUPLEX; 4228 } 4229 /* 4230 * IGP01 PHY may advertise full duplex operation after speed 4231 * downgrade even if it is operating at half duplex. Here we set the 4232 * duplex settings to match the duplex in the link partner's 4233 * capabilities. 4234 */ 4235 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4236 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4237 if (ret_val) 4238 return ret_val; 4239 4240 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4241 *duplex = HALF_DUPLEX; 4242 else { 4243 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4244 &phy_data); 4245 if (ret_val) 4246 return ret_val; 4247 if ((*speed == SPEED_100 && 4248 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4249 (*speed == SPEED_10 && 4250 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4251 *duplex = HALF_DUPLEX; 4252 } 4253 } 4254 if ((hw->mac_type == em_80003es2lan) && 4255 (hw->media_type == em_media_type_copper)) { 4256 if (*speed == SPEED_1000) 4257 ret_val = em_configure_kmrn_for_1000(hw); 4258 else 4259 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4260 if (ret_val) 4261 return ret_val; 4262 } 4263 if ((hw->mac_type == em_ich8lan) && 4264 (hw->phy_type == em_phy_igp_3) && 4265 (*speed == SPEED_1000)) { 4266 ret_val = em_kumeran_lock_loss_workaround(hw); 4267 if (ret_val) 4268 return ret_val; 4269 } 4270 return E1000_SUCCESS; 4271 } 4272 4273 /****************************************************************************** 4274 * Blocks until autoneg completes or times out (~4.5 seconds) 4275 * 4276 * hw - Struct containing variables accessed by shared code 4277 *****************************************************************************/ 4278 STATIC int32_t 4279 em_wait_autoneg(struct em_hw *hw) 4280 { 4281 int32_t ret_val; 4282 uint16_t i; 4283 uint16_t phy_data; 4284 DEBUGFUNC("em_wait_autoneg"); 4285 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4286 4287 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4288 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4289 /* 4290 * Read the MII Status Register and wait for Auto-Neg 4291 * Complete bit to be set. 4292 */ 4293 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4294 if (ret_val) 4295 return ret_val; 4296 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4297 if (ret_val) 4298 return ret_val; 4299 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4300 return E1000_SUCCESS; 4301 } 4302 msec_delay(100); 4303 } 4304 return E1000_SUCCESS; 4305 } 4306 4307 /****************************************************************************** 4308 * Raises the Management Data Clock 4309 * 4310 * hw - Struct containing variables accessed by shared code 4311 * ctrl - Device control register's current value 4312 *****************************************************************************/ 4313 static void 4314 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4315 { 4316 /* 4317 * Raise the clock input to the Management Data Clock (by setting the 4318 * MDC bit), and then delay 10 microseconds. 4319 */ 4320 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4321 E1000_WRITE_FLUSH(hw); 4322 usec_delay(10); 4323 } 4324 4325 /****************************************************************************** 4326 * Lowers the Management Data Clock 4327 * 4328 * hw - Struct containing variables accessed by shared code 4329 * ctrl - Device control register's current value 4330 *****************************************************************************/ 4331 static void 4332 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4333 { 4334 /* 4335 * Lower the clock input to the Management Data Clock (by clearing 4336 * the MDC bit), and then delay 10 microseconds. 4337 */ 4338 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4339 E1000_WRITE_FLUSH(hw); 4340 usec_delay(10); 4341 } 4342 4343 /****************************************************************************** 4344 * Shifts data bits out to the PHY 4345 * 4346 * hw - Struct containing variables accessed by shared code 4347 * data - Data to send out to the PHY 4348 * count - Number of bits to shift out 4349 * 4350 * Bits are shifted out in MSB to LSB order. 4351 *****************************************************************************/ 4352 static void 4353 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4354 { 4355 uint32_t ctrl; 4356 uint32_t mask; 4357 /* 4358 * We need to shift "count" number of bits out to the PHY. So, the 4359 * value in the "data" parameter will be shifted out to the PHY one 4360 * bit at a time. In order to do this, "data" must be broken down 4361 * into bits. 4362 */ 4363 mask = 0x01; 4364 mask <<= (count - 1); 4365 4366 ctrl = E1000_READ_REG(hw, CTRL); 4367 4368 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4369 * pins. 4370 */ 4371 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4372 4373 while (mask) { 4374 /* 4375 * A "1" is shifted out to the PHY by setting the MDIO bit to 4376 * "1" and then raising and lowering the Management Data 4377 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4378 * bit to "0" and then raising and lowering the clock. 4379 */ 4380 if (data & mask) 4381 ctrl |= E1000_CTRL_MDIO; 4382 else 4383 ctrl &= ~E1000_CTRL_MDIO; 4384 4385 E1000_WRITE_REG(hw, CTRL, ctrl); 4386 E1000_WRITE_FLUSH(hw); 4387 4388 usec_delay(10); 4389 4390 em_raise_mdi_clk(hw, &ctrl); 4391 em_lower_mdi_clk(hw, &ctrl); 4392 4393 mask = mask >> 1; 4394 } 4395 } 4396 4397 /****************************************************************************** 4398 * Shifts data bits in from the PHY 4399 * 4400 * hw - Struct containing variables accessed by shared code 4401 * 4402 * Bits are shifted in in MSB to LSB order. 4403 *****************************************************************************/ 4404 static uint16_t 4405 em_shift_in_mdi_bits(struct em_hw *hw) 4406 { 4407 uint32_t ctrl; 4408 uint16_t data = 0; 4409 uint8_t i; 4410 /* 4411 * In order to read a register from the PHY, we need to shift in a 4412 * total of 18 bits from the PHY. The first two bit (turnaround) 4413 * times are used to avoid contention on the MDIO pin when a read 4414 * operation is performed. These two bits are ignored by us and 4415 * thrown away. Bits are "shifted in" by raising the input to the 4416 * Management Data Clock (setting the MDC bit), and then reading the 4417 * value of the MDIO bit. 4418 */ 4419 ctrl = E1000_READ_REG(hw, CTRL); 4420 /* 4421 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4422 * input. 4423 */ 4424 ctrl &= ~E1000_CTRL_MDIO_DIR; 4425 ctrl &= ~E1000_CTRL_MDIO; 4426 4427 E1000_WRITE_REG(hw, CTRL, ctrl); 4428 E1000_WRITE_FLUSH(hw); 4429 /* 4430 * Raise and Lower the clock before reading in the data. This 4431 * accounts for the turnaround bits. The first clock occurred when we 4432 * clocked out the last bit of the Register Address. 4433 */ 4434 em_raise_mdi_clk(hw, &ctrl); 4435 em_lower_mdi_clk(hw, &ctrl); 4436 4437 for (data = 0, i = 0; i < 16; i++) { 4438 data = data << 1; 4439 em_raise_mdi_clk(hw, &ctrl); 4440 ctrl = E1000_READ_REG(hw, CTRL); 4441 /* Check to see if we shifted in a "1". */ 4442 if (ctrl & E1000_CTRL_MDIO) 4443 data |= 1; 4444 em_lower_mdi_clk(hw, &ctrl); 4445 } 4446 4447 em_raise_mdi_clk(hw, &ctrl); 4448 em_lower_mdi_clk(hw, &ctrl); 4449 4450 return data; 4451 } 4452 4453 STATIC int32_t 4454 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4455 { 4456 uint32_t swfw_sync = 0; 4457 uint32_t swmask = mask; 4458 uint32_t fwmask = mask << 16; 4459 int32_t timeout = 200; 4460 DEBUGFUNC("em_swfw_sync_acquire"); 4461 4462 if (hw->swfwhw_semaphore_present) 4463 return em_get_software_flag(hw); 4464 4465 if (!hw->swfw_sync_present) 4466 return em_get_hw_eeprom_semaphore(hw); 4467 4468 while (timeout) { 4469 if (em_get_hw_eeprom_semaphore(hw)) 4470 return -E1000_ERR_SWFW_SYNC; 4471 4472 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4473 if (!(swfw_sync & (fwmask | swmask))) { 4474 break; 4475 } 4476 /* 4477 * firmware currently using resource (fwmask) 4478 * or other software thread currently using resource (swmask) 4479 */ 4480 em_put_hw_eeprom_semaphore(hw); 4481 msec_delay_irq(5); 4482 timeout--; 4483 } 4484 4485 if (!timeout) { 4486 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4487 "\n"); 4488 return -E1000_ERR_SWFW_SYNC; 4489 } 4490 swfw_sync |= swmask; 4491 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4492 4493 em_put_hw_eeprom_semaphore(hw); 4494 return E1000_SUCCESS; 4495 } 4496 4497 STATIC void 4498 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4499 { 4500 uint32_t swfw_sync; 4501 uint32_t swmask = mask; 4502 DEBUGFUNC("em_swfw_sync_release"); 4503 4504 if (hw->swfwhw_semaphore_present) { 4505 em_release_software_flag(hw); 4506 return; 4507 } 4508 if (!hw->swfw_sync_present) { 4509 em_put_hw_eeprom_semaphore(hw); 4510 return; 4511 } 4512 /* 4513 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4514 */ 4515 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4516 /* empty */ 4517 4518 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4519 swfw_sync &= ~swmask; 4520 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4521 4522 em_put_hw_eeprom_semaphore(hw); 4523 } 4524 4525 /**************************************************************************** 4526 * Read BM PHY wakeup register. It works as such: 4527 * 1) Set page 769, register 17, bit 2 = 1 4528 * 2) Set page to 800 for host (801 if we were manageability) 4529 * 3) Write the address using the address opcode (0x11) 4530 * 4) Read or write the data using the data opcode (0x12) 4531 * 5) Restore 769_17.2 to its original value 4532 ****************************************************************************/ 4533 int32_t 4534 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4535 uint16_t *phy_data, boolean_t read) 4536 { 4537 int32_t ret_val; 4538 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4539 uint16_t phy_reg = 0; 4540 4541 /* All operations in this function are phy address 1 */ 4542 hw->phy_addr = 1; 4543 4544 /* Set page 769 */ 4545 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4546 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4547 4548 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4549 if (ret_val) 4550 goto out; 4551 4552 /* First clear bit 4 to avoid a power state change */ 4553 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4554 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4555 if (ret_val) 4556 goto out; 4557 4558 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4559 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4560 phy_reg | BM_WUC_ENABLE_BIT); 4561 if (ret_val) 4562 goto out; 4563 4564 /* Select page 800 */ 4565 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4566 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4567 4568 /* Write the page 800 offset value using opcode 0x11 */ 4569 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4570 if (ret_val) 4571 goto out; 4572 4573 if (read) 4574 /* Read the page 800 value using opcode 0x12 */ 4575 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4576 phy_data); 4577 else 4578 /* Write the page 800 value using opcode 0x12 */ 4579 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4580 *phy_data); 4581 4582 if (ret_val) 4583 goto out; 4584 4585 /* 4586 * Restore 769_17.2 to its original value 4587 * Set page 769 4588 */ 4589 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4590 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4591 4592 /* Clear 769_17.2 */ 4593 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4594 if (ret_val) 4595 goto out; 4596 4597 out: 4598 return ret_val; 4599 } 4600 4601 /*************************************************************************** 4602 * Read HV PHY vendor specific high registers 4603 ***************************************************************************/ 4604 int32_t 4605 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4606 uint16_t *phy_data, boolean_t read) 4607 { 4608 int32_t ret_val; 4609 uint32_t addr_reg = 0; 4610 uint32_t data_reg = 0; 4611 4612 /* This takes care of the difference with desktop vs mobile phy */ 4613 addr_reg = (hw->phy_type == em_phy_82578) ? 4614 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4615 data_reg = addr_reg + 1; 4616 4617 /* All operations in this function are phy address 2 */ 4618 hw->phy_addr = 2; 4619 4620 /* masking with 0x3F to remove the page from offset */ 4621 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4622 if (ret_val) { 4623 printf("Could not write PHY the HV address register\n"); 4624 goto out; 4625 } 4626 4627 /* Read or write the data value next */ 4628 if (read) 4629 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4630 else 4631 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4632 4633 if (ret_val) { 4634 printf("Could not read data value from HV data register\n"); 4635 goto out; 4636 } 4637 4638 out: 4639 return ret_val; 4640 } 4641 4642 /****************************************************************************** 4643 * Reads or writes the value from a PHY register, if the value is on a specific 4644 * non zero page, sets the page first. 4645 * hw - Struct containing variables accessed by shared code 4646 * reg_addr - address of the PHY register to read 4647 *****************************************************************************/ 4648 int32_t 4649 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4650 boolean_t read) 4651 { 4652 uint32_t ret_val; 4653 uint16_t swfw; 4654 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4655 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4656 4657 DEBUGFUNC("em_access_phy_reg_hv"); 4658 4659 swfw = E1000_SWFW_PHY0_SM; 4660 4661 if (em_swfw_sync_acquire(hw, swfw)) 4662 return -E1000_ERR_SWFW_SYNC; 4663 4664 if (page == BM_WUC_PAGE) { 4665 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4666 phy_data, read); 4667 goto release; 4668 } 4669 4670 if (page >= HV_INTC_FC_PAGE_START) 4671 hw->phy_addr = 1; 4672 else 4673 hw->phy_addr = 2; 4674 4675 if (page == HV_INTC_FC_PAGE_START) 4676 page = 0; 4677 4678 /* 4679 * Workaround MDIO accesses being disabled after entering IEEE Power 4680 * Down (whenever bit 11 of the PHY Control register is set) 4681 */ 4682 if (!read && 4683 (hw->phy_type == em_phy_82578) && 4684 (hw->phy_revision >= 1) && 4685 (hw->phy_addr == 2) && 4686 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4687 (*phy_data & (1 << 11))) { 4688 uint16_t data2 = 0x7EFF; 4689 4690 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4691 &data2, FALSE); 4692 if (ret_val) 4693 return ret_val; 4694 } 4695 4696 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4697 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4698 (page << PHY_PAGE_SHIFT)); 4699 if (ret_val) 4700 return ret_val; 4701 } 4702 if (read) 4703 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4704 phy_data); 4705 else 4706 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4707 *phy_data); 4708 release: 4709 em_swfw_sync_release(hw, swfw); 4710 return ret_val; 4711 } 4712 4713 /****************************************************************************** 4714 * Reads the value from a PHY register, if the value is on a specific non zero 4715 * page, sets the page first. 4716 * hw - Struct containing variables accessed by shared code 4717 * reg_addr - address of the PHY register to read 4718 *****************************************************************************/ 4719 int32_t 4720 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4721 { 4722 uint32_t ret_val; 4723 uint16_t swfw; 4724 DEBUGFUNC("em_read_phy_reg"); 4725 4726 if (hw->mac_type == em_pchlan || 4727 hw->mac_type == em_pch2lan || 4728 hw->mac_type == em_pch_lpt || 4729 hw->mac_type == em_pch_spt) 4730 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4731 4732 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) && 4733 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4734 swfw = E1000_SWFW_PHY1_SM; 4735 } else { 4736 swfw = E1000_SWFW_PHY0_SM; 4737 } 4738 if (em_swfw_sync_acquire(hw, swfw)) 4739 return -E1000_ERR_SWFW_SYNC; 4740 4741 if ((hw->phy_type == em_phy_igp || 4742 hw->phy_type == em_phy_igp_3 || 4743 hw->phy_type == em_phy_igp_2) && 4744 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4745 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4746 (uint16_t) reg_addr); 4747 if (ret_val) { 4748 em_swfw_sync_release(hw, swfw); 4749 return ret_val; 4750 } 4751 } else if (hw->phy_type == em_phy_gg82563) { 4752 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4753 (hw->mac_type == em_80003es2lan)) { 4754 /* Select Configuration Page */ 4755 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4756 GG82563_MIN_ALT_REG) { 4757 ret_val = em_write_phy_reg_ex(hw, 4758 GG82563_PHY_PAGE_SELECT, 4759 (uint16_t) ((uint16_t) reg_addr >> 4760 GG82563_PAGE_SHIFT)); 4761 } else { 4762 /* 4763 * Use Alternative Page Select register to 4764 * access registers 30 and 31 4765 */ 4766 ret_val = em_write_phy_reg_ex(hw, 4767 GG82563_PHY_PAGE_SELECT_ALT, 4768 (uint16_t) ((uint16_t) reg_addr >> 4769 GG82563_PAGE_SHIFT)); 4770 } 4771 4772 if (ret_val) { 4773 em_swfw_sync_release(hw, swfw); 4774 return ret_val; 4775 } 4776 } 4777 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4778 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4779 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4780 (uint16_t) ((uint16_t) reg_addr >> 4781 PHY_PAGE_SHIFT)); 4782 if (ret_val) 4783 return ret_val; 4784 } 4785 } 4786 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4787 phy_data); 4788 4789 em_swfw_sync_release(hw, swfw); 4790 return ret_val; 4791 } 4792 4793 STATIC int32_t 4794 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4795 { 4796 uint32_t i; 4797 uint32_t mdic = 0; 4798 DEBUGFUNC("em_read_phy_reg_ex"); 4799 4800 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4801 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4802 return -E1000_ERR_PARAM; 4803 } 4804 if (hw->mac_type == em_icp_xxxx) { 4805 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 4806 reg_addr); 4807 return E1000_SUCCESS; 4808 } 4809 if (hw->mac_type > em_82543) { 4810 /* 4811 * Set up Op-code, Phy Address, and register address in the 4812 * MDI Control register. The MAC will take care of 4813 * interfacing with the PHY to retrieve the desired data. 4814 */ 4815 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4816 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4817 (E1000_MDIC_OP_READ)); 4818 4819 E1000_WRITE_REG(hw, MDIC, mdic); 4820 4821 /* 4822 * Poll the ready bit to see if the MDI read completed 4823 * Increasing the time out as testing showed failures with 4824 * the lower time out (from FreeBSD driver) 4825 */ 4826 for (i = 0; i < 1960; i++) { 4827 usec_delay(50); 4828 mdic = E1000_READ_REG(hw, MDIC); 4829 if (mdic & E1000_MDIC_READY) 4830 break; 4831 } 4832 if (!(mdic & E1000_MDIC_READY)) { 4833 DEBUGOUT("MDI Read did not complete\n"); 4834 return -E1000_ERR_PHY; 4835 } 4836 if (mdic & E1000_MDIC_ERROR) { 4837 DEBUGOUT("MDI Error\n"); 4838 return -E1000_ERR_PHY; 4839 } 4840 *phy_data = (uint16_t) mdic; 4841 4842 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt) 4843 usec_delay(100); 4844 } else { 4845 /* 4846 * We must first send a preamble through the MDIO pin to 4847 * signal the beginning of an MII instruction. This is done 4848 * by sending 32 consecutive "1" bits. 4849 */ 4850 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4851 /* 4852 * Now combine the next few fields that are required for a 4853 * read operation. We use this method instead of calling the 4854 * em_shift_out_mdi_bits routine five different times. The 4855 * format of a MII read instruction consists of a shift out 4856 * of 14 bits and is defined as follows: <Preamble><SOF><Op 4857 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 4858 * bits. This first two bits shifted in are TurnAround bits 4859 * used to avoid contention on the MDIO pin when a READ 4860 * operation is performed. These two bits are thrown away 4861 * followed by a shift in of 16 bits which contains the 4862 * desired data. 4863 */ 4864 mdic = ((reg_addr) | (hw->phy_addr << 5) | 4865 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4866 4867 em_shift_out_mdi_bits(hw, mdic, 14); 4868 /* 4869 * Now that we've shifted out the read command to the MII, we 4870 * need to "shift in" the 16-bit value (18 total bits) of the 4871 * requested PHY register address. 4872 */ 4873 *phy_data = em_shift_in_mdi_bits(hw); 4874 } 4875 return E1000_SUCCESS; 4876 } 4877 4878 /****************************************************************************** 4879 * Writes a value to a PHY register 4880 * 4881 * hw - Struct containing variables accessed by shared code 4882 * reg_addr - address of the PHY register to write 4883 * data - data to write to the PHY 4884 *****************************************************************************/ 4885 int32_t 4886 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4887 { 4888 uint32_t ret_val; 4889 DEBUGFUNC("em_write_phy_reg"); 4890 4891 if (hw->mac_type == em_pchlan || 4892 hw->mac_type == em_pch2lan || 4893 hw->mac_type == em_pch_lpt || 4894 hw->mac_type == em_pch_spt) 4895 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 4896 4897 if (em_swfw_sync_acquire(hw, hw->swfw)) 4898 return -E1000_ERR_SWFW_SYNC; 4899 4900 if ((hw->phy_type == em_phy_igp || 4901 hw->phy_type == em_phy_igp_3 || 4902 hw->phy_type == em_phy_igp_2) && 4903 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4904 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4905 (uint16_t) reg_addr); 4906 if (ret_val) { 4907 em_swfw_sync_release(hw, hw->swfw); 4908 return ret_val; 4909 } 4910 } else if (hw->phy_type == em_phy_gg82563) { 4911 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4912 (hw->mac_type == em_80003es2lan)) { 4913 /* Select Configuration Page */ 4914 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4915 GG82563_MIN_ALT_REG) { 4916 ret_val = em_write_phy_reg_ex(hw, 4917 GG82563_PHY_PAGE_SELECT, 4918 (uint16_t) ((uint16_t) reg_addr >> 4919 GG82563_PAGE_SHIFT)); 4920 } else { 4921 /* 4922 * Use Alternative Page Select register to 4923 * access registers 30 and 31 4924 */ 4925 ret_val = em_write_phy_reg_ex(hw, 4926 GG82563_PHY_PAGE_SELECT_ALT, 4927 (uint16_t) ((uint16_t) reg_addr >> 4928 GG82563_PAGE_SHIFT)); 4929 } 4930 4931 if (ret_val) { 4932 em_swfw_sync_release(hw, hw->swfw); 4933 return ret_val; 4934 } 4935 } 4936 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4937 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4938 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4939 (uint16_t) ((uint16_t) reg_addr >> 4940 PHY_PAGE_SHIFT)); 4941 if (ret_val) 4942 return ret_val; 4943 } 4944 } 4945 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4946 phy_data); 4947 4948 em_swfw_sync_release(hw, hw->swfw); 4949 return ret_val; 4950 } 4951 4952 STATIC int32_t 4953 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4954 { 4955 uint32_t i; 4956 uint32_t mdic = 0; 4957 DEBUGFUNC("em_write_phy_reg_ex"); 4958 4959 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4960 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4961 return -E1000_ERR_PARAM; 4962 } 4963 if (hw->mac_type == em_icp_xxxx) { 4964 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 4965 reg_addr, phy_data); 4966 return E1000_SUCCESS; 4967 } 4968 if (hw->mac_type > em_82543) { 4969 /* 4970 * Set up Op-code, Phy Address, register address, and data 4971 * intended for the PHY register in the MDI Control register. 4972 * The MAC will take care of interfacing with the PHY to send 4973 * the desired data. 4974 */ 4975 mdic = (((uint32_t) phy_data) | 4976 (reg_addr << E1000_MDIC_REG_SHIFT) | 4977 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4978 (E1000_MDIC_OP_WRITE)); 4979 4980 E1000_WRITE_REG(hw, MDIC, mdic); 4981 4982 /* Poll the ready bit to see if the MDI read completed */ 4983 for (i = 0; i < 641; i++) { 4984 usec_delay(5); 4985 mdic = E1000_READ_REG(hw, MDIC); 4986 if (mdic & E1000_MDIC_READY) 4987 break; 4988 } 4989 if (!(mdic & E1000_MDIC_READY)) { 4990 DEBUGOUT("MDI Write did not complete\n"); 4991 return -E1000_ERR_PHY; 4992 } 4993 4994 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt) 4995 usec_delay(100); 4996 } else { 4997 /* 4998 * We'll need to use the SW defined pins to shift the write 4999 * command out to the PHY. We first send a preamble to the 5000 * PHY to signal the beginning of the MII instruction. This 5001 * is done by sending 32 consecutive "1" bits. 5002 */ 5003 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 5004 /* 5005 * Now combine the remaining required fields that will 5006 * indicate a write operation. We use this method instead of 5007 * calling the em_shift_out_mdi_bits routine for each field 5008 * in the command. The format of a MII write instruction is 5009 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 5010 * Addr><Turnaround><Data>. 5011 */ 5012 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 5013 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 5014 (PHY_SOF << 14)); 5015 mdic <<= 16; 5016 mdic |= (uint32_t) phy_data; 5017 5018 em_shift_out_mdi_bits(hw, mdic, 32); 5019 } 5020 5021 return E1000_SUCCESS; 5022 } 5023 5024 STATIC int32_t 5025 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 5026 { 5027 uint32_t reg_val; 5028 DEBUGFUNC("em_read_kmrn_reg"); 5029 5030 if (em_swfw_sync_acquire(hw, hw->swfw)) 5031 return -E1000_ERR_SWFW_SYNC; 5032 5033 /* Write register address */ 5034 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5035 E1000_KUMCTRLSTA_OFFSET) | 5036 E1000_KUMCTRLSTA_REN; 5037 5038 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5039 usec_delay(2); 5040 5041 /* Read the data returned */ 5042 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 5043 *data = (uint16_t) reg_val; 5044 5045 em_swfw_sync_release(hw, hw->swfw); 5046 return E1000_SUCCESS; 5047 } 5048 5049 STATIC int32_t 5050 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 5051 { 5052 uint32_t reg_val; 5053 DEBUGFUNC("em_write_kmrn_reg"); 5054 5055 if (em_swfw_sync_acquire(hw, hw->swfw)) 5056 return -E1000_ERR_SWFW_SYNC; 5057 5058 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 5059 E1000_KUMCTRLSTA_OFFSET) | data; 5060 5061 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 5062 usec_delay(2); 5063 5064 em_swfw_sync_release(hw, hw->swfw); 5065 return E1000_SUCCESS; 5066 } 5067 5068 /****************************************************************************** 5069 * Returns the PHY to the power-on reset state 5070 * 5071 * hw - Struct containing variables accessed by shared code 5072 *****************************************************************************/ 5073 int32_t 5074 em_phy_hw_reset(struct em_hw *hw) 5075 { 5076 uint32_t ctrl, ctrl_ext; 5077 uint32_t led_ctrl; 5078 int32_t ret_val; 5079 DEBUGFUNC("em_phy_hw_reset"); 5080 /* 5081 * In the case of the phy reset being blocked, it's not an error, we 5082 * simply return success without performing the reset. 5083 */ 5084 ret_val = em_check_phy_reset_block(hw); 5085 if (ret_val) 5086 return E1000_SUCCESS; 5087 5088 DEBUGOUT("Resetting Phy...\n"); 5089 5090 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 5091 if (em_swfw_sync_acquire(hw, hw->swfw)) { 5092 DEBUGOUT("Unable to acquire swfw sync\n"); 5093 return -E1000_ERR_SWFW_SYNC; 5094 } 5095 /* 5096 * Read the device control register and assert the 5097 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 5098 * pre-em_82571 hardware, we delay for 10ms between the 5099 * assert and deassert. For em_82571 hardware and later, we 5100 * instead delay for 50us between and 10ms after the 5101 * deassertion. 5102 */ 5103 ctrl = E1000_READ_REG(hw, CTRL); 5104 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 5105 E1000_WRITE_FLUSH(hw); 5106 5107 if (hw->mac_type < em_82571) 5108 msec_delay(10); 5109 else 5110 usec_delay(100); 5111 5112 E1000_WRITE_REG(hw, CTRL, ctrl); 5113 E1000_WRITE_FLUSH(hw); 5114 5115 if (hw->mac_type >= em_82571) 5116 msec_delay_irq(10); 5117 em_swfw_sync_release(hw, hw->swfw); 5118 /* 5119 * the M88E1141_E_PHY_ID might need reset here, but nothing 5120 * proves it 5121 */ 5122 } else { 5123 /* 5124 * Read the Extended Device Control Register, assert the 5125 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 5126 * out of reset. 5127 */ 5128 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 5129 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 5130 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 5131 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5132 E1000_WRITE_FLUSH(hw); 5133 msec_delay(10); 5134 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 5135 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 5136 E1000_WRITE_FLUSH(hw); 5137 } 5138 usec_delay(150); 5139 5140 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 5141 /* Configure activity LED after PHY reset */ 5142 led_ctrl = E1000_READ_REG(hw, LEDCTL); 5143 led_ctrl &= IGP_ACTIVITY_LED_MASK; 5144 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 5145 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 5146 } 5147 /* Wait for FW to finish PHY configuration. */ 5148 ret_val = em_get_phy_cfg_done(hw); 5149 if (ret_val != E1000_SUCCESS) 5150 return ret_val; 5151 em_release_software_semaphore(hw); 5152 5153 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 5154 ret_val = em_init_lcd_from_nvm(hw); 5155 5156 return ret_val; 5157 } 5158 5159 /***************************************************************************** 5160 * SW-based LCD Configuration. 5161 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 5162 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 5163 * in NVM determines whether HW should configure LPLU and Gbe Disable. 5164 *****************************************************************************/ 5165 int32_t 5166 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 5167 { 5168 int32_t ret_val = E1000_SUCCESS; 5169 uint32_t mac_reg; 5170 uint16_t oem_reg; 5171 uint16_t swfw = E1000_SWFW_PHY0_SM; 5172 5173 if (hw->mac_type < em_pchlan) 5174 return ret_val; 5175 5176 ret_val = em_swfw_sync_acquire(hw, swfw); 5177 if (ret_val) 5178 return ret_val; 5179 5180 if (hw->mac_type == em_pchlan) { 5181 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 5182 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 5183 goto out; 5184 } 5185 5186 mac_reg = E1000_READ_REG(hw, FEXTNVM); 5187 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 5188 goto out; 5189 5190 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 5191 5192 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 5193 if (ret_val) 5194 goto out; 5195 5196 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 5197 5198 if (d0_state) { 5199 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 5200 oem_reg |= HV_OEM_BITS_GBE_DIS; 5201 5202 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 5203 oem_reg |= HV_OEM_BITS_LPLU; 5204 /* Restart auto-neg to activate the bits */ 5205 if (!em_check_phy_reset_block(hw)) 5206 oem_reg |= HV_OEM_BITS_RESTART_AN; 5207 5208 } else { 5209 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 5210 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 5211 oem_reg |= HV_OEM_BITS_GBE_DIS; 5212 5213 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 5214 E1000_PHY_CTRL_NOND0A_LPLU)) 5215 oem_reg |= HV_OEM_BITS_LPLU; 5216 } 5217 5218 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 5219 5220 out: 5221 em_swfw_sync_release(hw, swfw); 5222 5223 return ret_val; 5224 } 5225 5226 5227 /****************************************************************************** 5228 * Resets the PHY 5229 * 5230 * hw - Struct containing variables accessed by shared code 5231 * 5232 * Sets bit 15 of the MII Control regiser 5233 *****************************************************************************/ 5234 int32_t 5235 em_phy_reset(struct em_hw *hw) 5236 { 5237 int32_t ret_val; 5238 uint16_t phy_data; 5239 DEBUGFUNC("em_phy_reset"); 5240 /* 5241 * In the case of the phy reset being blocked, it's not an error, we 5242 * simply return success without performing the reset. 5243 */ 5244 ret_val = em_check_phy_reset_block(hw); 5245 if (ret_val) 5246 return E1000_SUCCESS; 5247 5248 switch (hw->phy_type) { 5249 case em_phy_igp: 5250 case em_phy_igp_2: 5251 case em_phy_igp_3: 5252 case em_phy_ife: 5253 ret_val = em_phy_hw_reset(hw); 5254 if (ret_val) 5255 return ret_val; 5256 break; 5257 default: 5258 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5259 if (ret_val) 5260 return ret_val; 5261 5262 phy_data |= MII_CR_RESET; 5263 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5264 if (ret_val) 5265 return ret_val; 5266 5267 usec_delay(1); 5268 break; 5269 } 5270 5271 /* Allow time for h/w to get to a quiescent state after reset */ 5272 msec_delay(10); 5273 5274 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5275 em_phy_init_script(hw); 5276 5277 if (hw->mac_type == em_pchlan) { 5278 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5279 if (ret_val) 5280 return ret_val; 5281 } else if (hw->mac_type == em_pch2lan) { 5282 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5283 if (ret_val) 5284 return ret_val; 5285 } 5286 5287 if (hw->mac_type >= em_pchlan) { 5288 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5289 if (ret_val) 5290 return ret_val; 5291 } 5292 5293 /* Ungate automatic PHY configuration on non-managed 82579 */ 5294 if ((hw->mac_type == em_pch2lan) && 5295 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5296 msec_delay(10); 5297 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5298 } 5299 5300 if (hw->phy_id == M88E1512_E_PHY_ID) { 5301 ret_val = em_initialize_M88E1512_phy(hw); 5302 if (ret_val) 5303 return ret_val; 5304 } 5305 5306 return E1000_SUCCESS; 5307 } 5308 5309 /****************************************************************************** 5310 * Work-around for 82566 Kumeran PCS lock loss: 5311 * On link status change (i.e. PCI reset, speed change) and link is up and 5312 * speed is gigabit- 5313 * 0) if workaround is optionally disabled do nothing 5314 * 1) wait 1ms for Kumeran link to come up 5315 * 2) check Kumeran Diagnostic register PCS lock loss bit 5316 * 3) if not set the link is locked (all is good), otherwise... 5317 * 4) reset the PHY 5318 * 5) repeat up to 10 times 5319 * Note: this is only called for IGP3 copper when speed is 1gb. 5320 * 5321 * hw - struct containing variables accessed by shared code 5322 *****************************************************************************/ 5323 STATIC int32_t 5324 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5325 { 5326 int32_t ret_val; 5327 int32_t reg; 5328 int32_t cnt; 5329 uint16_t phy_data; 5330 if (hw->kmrn_lock_loss_workaround_disabled) 5331 return E1000_SUCCESS; 5332 /* 5333 * Make sure link is up before proceeding. If not just return. 5334 * Attempting this while link is negotiating fouled up link stability 5335 */ 5336 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5337 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5338 5339 if (phy_data & MII_SR_LINK_STATUS) { 5340 for (cnt = 0; cnt < 10; cnt++) { 5341 /* read once to clear */ 5342 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5343 &phy_data); 5344 if (ret_val) 5345 return ret_val; 5346 /* and again to get new status */ 5347 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5348 if (ret_val) 5349 return ret_val; 5350 5351 /* check for PCS lock */ 5352 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5353 return E1000_SUCCESS; 5354 5355 /* Issue PHY reset */ 5356 em_phy_hw_reset(hw); 5357 msec_delay_irq(5); 5358 } 5359 /* Disable GigE link negotiation */ 5360 reg = E1000_READ_REG(hw, PHY_CTRL); 5361 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5362 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5363 5364 /* unable to acquire PCS lock */ 5365 return E1000_ERR_PHY; 5366 } 5367 return E1000_SUCCESS; 5368 } 5369 5370 /****************************************************************************** 5371 * Reads and matches the expected PHY address for known PHY IDs 5372 * 5373 * hw - Struct containing variables accessed by shared code 5374 *****************************************************************************/ 5375 STATIC int32_t 5376 em_match_gig_phy(struct em_hw *hw) 5377 { 5378 int32_t phy_init_status, ret_val; 5379 uint16_t phy_id_high, phy_id_low; 5380 boolean_t match = FALSE; 5381 DEBUGFUNC("em_match_gig_phy"); 5382 5383 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5384 if (ret_val) 5385 return ret_val; 5386 5387 hw->phy_id = (uint32_t) (phy_id_high << 16); 5388 usec_delay(20); 5389 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5390 if (ret_val) 5391 return ret_val; 5392 5393 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5394 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5395 5396 switch (hw->mac_type) { 5397 case em_82543: 5398 if (hw->phy_id == M88E1000_E_PHY_ID) 5399 match = TRUE; 5400 break; 5401 case em_82544: 5402 if (hw->phy_id == M88E1000_I_PHY_ID) 5403 match = TRUE; 5404 break; 5405 case em_82540: 5406 case em_82545: 5407 case em_82545_rev_3: 5408 case em_82546: 5409 case em_82546_rev_3: 5410 if (hw->phy_id == M88E1011_I_PHY_ID) 5411 match = TRUE; 5412 break; 5413 case em_82541: 5414 case em_82541_rev_2: 5415 case em_82547: 5416 case em_82547_rev_2: 5417 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5418 match = TRUE; 5419 break; 5420 case em_82573: 5421 if (hw->phy_id == M88E1111_I_PHY_ID) 5422 match = TRUE; 5423 break; 5424 case em_82574: 5425 if (hw->phy_id == BME1000_E_PHY_ID) 5426 match = TRUE; 5427 break; 5428 case em_82575: 5429 if (hw->phy_id == M88E1000_E_PHY_ID) 5430 match = TRUE; 5431 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5432 match = TRUE; 5433 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5434 match = TRUE; 5435 break; 5436 case em_82580: 5437 case em_i210: 5438 case em_i350: 5439 if (hw->phy_id == I82580_I_PHY_ID || 5440 hw->phy_id == I210_I_PHY_ID || 5441 hw->phy_id == I347AT4_E_PHY_ID || 5442 hw->phy_id == I350_I_PHY_ID || 5443 hw->phy_id == M88E1112_E_PHY_ID || 5444 hw->phy_id == M88E1543_E_PHY_ID || 5445 hw->phy_id == M88E1512_E_PHY_ID) { 5446 uint32_t mdic; 5447 5448 mdic = EM_READ_REG(hw, E1000_MDICNFG); 5449 mdic &= E1000_MDICNFG_PHY_MASK; 5450 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 5451 DEBUGOUT1("MDICNFG PHY ADDR %d", 5452 mdic >> E1000_MDICNFG_PHY_SHIFT); 5453 match = TRUE; 5454 } 5455 break; 5456 case em_80003es2lan: 5457 if (hw->phy_id == GG82563_E_PHY_ID) 5458 match = TRUE; 5459 break; 5460 case em_ich8lan: 5461 case em_ich9lan: 5462 case em_ich10lan: 5463 case em_pchlan: 5464 case em_pch2lan: 5465 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5466 match = TRUE; 5467 if (hw->phy_id == IFE_E_PHY_ID) 5468 match = TRUE; 5469 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5470 match = TRUE; 5471 if (hw->phy_id == IFE_C_E_PHY_ID) 5472 match = TRUE; 5473 if (hw->phy_id == BME1000_E_PHY_ID) 5474 match = TRUE; 5475 if (hw->phy_id == I82577_E_PHY_ID) 5476 match = TRUE; 5477 if (hw->phy_id == I82578_E_PHY_ID) 5478 match = TRUE; 5479 if (hw->phy_id == I82579_E_PHY_ID) 5480 match = TRUE; 5481 break; 5482 case em_pch_lpt: 5483 case em_pch_spt: 5484 if (hw->phy_id == I217_E_PHY_ID) 5485 match = TRUE; 5486 break; 5487 case em_icp_xxxx: 5488 if (hw->phy_id == M88E1141_E_PHY_ID) 5489 match = TRUE; 5490 if (hw->phy_id == RTL8211_E_PHY_ID) 5491 match = TRUE; 5492 break; 5493 default: 5494 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5495 return -E1000_ERR_CONFIG; 5496 } 5497 phy_init_status = em_set_phy_type(hw); 5498 5499 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5500 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5501 return E1000_SUCCESS; 5502 } 5503 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5504 return -E1000_ERR_PHY; 5505 } 5506 5507 /****************************************************************************** 5508 * Probes the expected PHY address for known PHY IDs 5509 * 5510 * hw - Struct containing variables accessed by shared code 5511 *****************************************************************************/ 5512 STATIC int32_t 5513 em_detect_gig_phy(struct em_hw *hw) 5514 { 5515 int32_t ret_val; 5516 DEBUGFUNC("em_detect_gig_phy"); 5517 5518 if (hw->phy_id != 0) 5519 return E1000_SUCCESS; 5520 5521 /* default phy address, most phys reside here, but not all (ICH10) */ 5522 if (hw->mac_type != em_icp_xxxx) 5523 hw->phy_addr = 1; 5524 else 5525 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5526 5527 /* 5528 * The 82571 firmware may still be configuring the PHY. In this 5529 * case, we cannot access the PHY until the configuration is done. 5530 * So we explicitly set the PHY values. 5531 */ 5532 if (hw->mac_type == em_82571 || 5533 hw->mac_type == em_82572) { 5534 hw->phy_id = IGP01E1000_I_PHY_ID; 5535 hw->phy_type = em_phy_igp_2; 5536 return E1000_SUCCESS; 5537 } 5538 5539 /* 5540 * Some of the fiber cards dont have a phy, so we must exit cleanly 5541 * here 5542 */ 5543 if ((hw->media_type == em_media_type_fiber) && 5544 (hw->mac_type == em_82542_rev2_0 || 5545 hw->mac_type == em_82542_rev2_1 || 5546 hw->mac_type == em_82543 || 5547 hw->mac_type == em_82573 || 5548 hw->mac_type == em_82574 || 5549 hw->mac_type == em_80003es2lan)) { 5550 hw->phy_type = em_phy_undefined; 5551 return E1000_SUCCESS; 5552 } 5553 5554 if ((hw->media_type == em_media_type_internal_serdes || 5555 hw->media_type == em_media_type_fiber) && 5556 hw->mac_type >= em_82575) { 5557 hw->phy_type = em_phy_undefined; 5558 return E1000_SUCCESS; 5559 } 5560 5561 /* 5562 * Up to 82543 (incl), we need reset the phy, or it might not get 5563 * detected 5564 */ 5565 if (hw->mac_type <= em_82543) { 5566 ret_val = em_phy_hw_reset(hw); 5567 if (ret_val) 5568 return ret_val; 5569 } 5570 /* 5571 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5572 * work- around that forces PHY page 0 to be set or the reads fail. 5573 * The rest of the code in this routine uses em_read_phy_reg to read 5574 * the PHY ID. So for ESB-2 we need to have this set so our reads 5575 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5576 * routines below will figure this out as well. 5577 */ 5578 if (hw->mac_type == em_80003es2lan) 5579 hw->phy_type = em_phy_gg82563; 5580 5581 /* Power on SGMII phy if it is disabled */ 5582 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 5583 hw->mac_type == em_i350) { 5584 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 5585 EM_WRITE_REG(hw, E1000_CTRL_EXT, 5586 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 5587 delay(300); 5588 } 5589 5590 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5591 for (hw->phy_addr = 1; (hw->phy_addr < 4); hw->phy_addr++) { 5592 ret_val = em_match_gig_phy(hw); 5593 if (ret_val == E1000_SUCCESS) 5594 return E1000_SUCCESS; 5595 } 5596 return -E1000_ERR_PHY; 5597 } 5598 5599 /****************************************************************************** 5600 * Resets the PHY's DSP 5601 * 5602 * hw - Struct containing variables accessed by shared code 5603 *****************************************************************************/ 5604 static int32_t 5605 em_phy_reset_dsp(struct em_hw *hw) 5606 { 5607 int32_t ret_val; 5608 DEBUGFUNC("em_phy_reset_dsp"); 5609 5610 do { 5611 if (hw->phy_type != em_phy_gg82563) { 5612 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5613 if (ret_val) 5614 break; 5615 } 5616 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5617 if (ret_val) 5618 break; 5619 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5620 if (ret_val) 5621 break; 5622 ret_val = E1000_SUCCESS; 5623 } while (0); 5624 5625 return ret_val; 5626 } 5627 5628 /****************************************************************************** 5629 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5630 * is configured. Additionally, if this is ICH8, the flash controller GbE 5631 * registers must be mapped, or this will crash. 5632 * 5633 * hw - Struct containing variables accessed by shared code 5634 *****************************************************************************/ 5635 int32_t 5636 em_init_eeprom_params(struct em_hw *hw) 5637 { 5638 struct em_eeprom_info *eeprom = &hw->eeprom; 5639 uint32_t eecd = E1000_READ_REG(hw, EECD); 5640 int32_t ret_val = E1000_SUCCESS; 5641 uint16_t eeprom_size; 5642 DEBUGFUNC("em_init_eeprom_params"); 5643 5644 switch (hw->mac_type) { 5645 case em_82542_rev2_0: 5646 case em_82542_rev2_1: 5647 case em_82543: 5648 case em_82544: 5649 eeprom->type = em_eeprom_microwire; 5650 eeprom->word_size = 64; 5651 eeprom->opcode_bits = 3; 5652 eeprom->address_bits = 6; 5653 eeprom->delay_usec = 50; 5654 eeprom->use_eerd = FALSE; 5655 eeprom->use_eewr = FALSE; 5656 break; 5657 case em_82540: 5658 case em_82545: 5659 case em_82545_rev_3: 5660 case em_icp_xxxx: 5661 case em_82546: 5662 case em_82546_rev_3: 5663 eeprom->type = em_eeprom_microwire; 5664 eeprom->opcode_bits = 3; 5665 eeprom->delay_usec = 50; 5666 if (eecd & E1000_EECD_SIZE) { 5667 eeprom->word_size = 256; 5668 eeprom->address_bits = 8; 5669 } else { 5670 eeprom->word_size = 64; 5671 eeprom->address_bits = 6; 5672 } 5673 eeprom->use_eerd = FALSE; 5674 eeprom->use_eewr = FALSE; 5675 break; 5676 case em_82541: 5677 case em_82541_rev_2: 5678 case em_82547: 5679 case em_82547_rev_2: 5680 if (eecd & E1000_EECD_TYPE) { 5681 eeprom->type = em_eeprom_spi; 5682 eeprom->opcode_bits = 8; 5683 eeprom->delay_usec = 1; 5684 if (eecd & E1000_EECD_ADDR_BITS) { 5685 eeprom->page_size = 32; 5686 eeprom->address_bits = 16; 5687 } else { 5688 eeprom->page_size = 8; 5689 eeprom->address_bits = 8; 5690 } 5691 } else { 5692 eeprom->type = em_eeprom_microwire; 5693 eeprom->opcode_bits = 3; 5694 eeprom->delay_usec = 50; 5695 if (eecd & E1000_EECD_ADDR_BITS) { 5696 eeprom->word_size = 256; 5697 eeprom->address_bits = 8; 5698 } else { 5699 eeprom->word_size = 64; 5700 eeprom->address_bits = 6; 5701 } 5702 } 5703 eeprom->use_eerd = FALSE; 5704 eeprom->use_eewr = FALSE; 5705 break; 5706 case em_82571: 5707 case em_82572: 5708 eeprom->type = em_eeprom_spi; 5709 eeprom->opcode_bits = 8; 5710 eeprom->delay_usec = 1; 5711 if (eecd & E1000_EECD_ADDR_BITS) { 5712 eeprom->page_size = 32; 5713 eeprom->address_bits = 16; 5714 } else { 5715 eeprom->page_size = 8; 5716 eeprom->address_bits = 8; 5717 } 5718 eeprom->use_eerd = FALSE; 5719 eeprom->use_eewr = FALSE; 5720 break; 5721 case em_82573: 5722 case em_82574: 5723 case em_82575: 5724 case em_82580: 5725 case em_i210: 5726 case em_i350: 5727 eeprom->type = em_eeprom_spi; 5728 eeprom->opcode_bits = 8; 5729 eeprom->delay_usec = 1; 5730 if (eecd & E1000_EECD_ADDR_BITS) { 5731 eeprom->page_size = 32; 5732 eeprom->address_bits = 16; 5733 } else { 5734 eeprom->page_size = 8; 5735 eeprom->address_bits = 8; 5736 } 5737 eeprom->use_eerd = TRUE; 5738 eeprom->use_eewr = TRUE; 5739 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 5740 eeprom->type = em_eeprom_flash; 5741 eeprom->word_size = 2048; 5742 /* 5743 * Ensure that the Autonomous FLASH update bit is 5744 * cleared due to Flash update issue on parts which 5745 * use a FLASH for NVM. 5746 */ 5747 eecd &= ~E1000_EECD_AUPDEN; 5748 E1000_WRITE_REG(hw, EECD, eecd); 5749 } 5750 if (em_get_flash_presence_i210(hw) == FALSE) { 5751 eeprom->type = em_eeprom_invm; 5752 eeprom->word_size = INVM_SIZE; 5753 eeprom->use_eerd = FALSE; 5754 eeprom->use_eewr = FALSE; 5755 } 5756 break; 5757 case em_80003es2lan: 5758 eeprom->type = em_eeprom_spi; 5759 eeprom->opcode_bits = 8; 5760 eeprom->delay_usec = 1; 5761 if (eecd & E1000_EECD_ADDR_BITS) { 5762 eeprom->page_size = 32; 5763 eeprom->address_bits = 16; 5764 } else { 5765 eeprom->page_size = 8; 5766 eeprom->address_bits = 8; 5767 } 5768 eeprom->use_eerd = TRUE; 5769 eeprom->use_eewr = FALSE; 5770 break; 5771 case em_ich8lan: 5772 case em_ich9lan: 5773 case em_ich10lan: 5774 case em_pchlan: 5775 case em_pch2lan: 5776 case em_pch_lpt: 5777 { 5778 int32_t i = 0; 5779 uint32_t flash_size = 5780 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 5781 eeprom->type = em_eeprom_ich8; 5782 eeprom->use_eerd = FALSE; 5783 eeprom->use_eewr = FALSE; 5784 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 5785 /* 5786 * Zero the shadow RAM structure. But don't load it 5787 * from NVM so as to save time for driver init 5788 */ 5789 if (hw->eeprom_shadow_ram != NULL) { 5790 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5791 hw->eeprom_shadow_ram[i].modified = 5792 FALSE; 5793 hw->eeprom_shadow_ram[i].eeprom_word = 5794 0xFFFF; 5795 } 5796 } 5797 hw->flash_base_addr = (flash_size & 5798 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 5799 5800 hw->flash_bank_size = ((flash_size >> 16) & 5801 ICH_GFPREG_BASE_MASK) + 1; 5802 hw->flash_bank_size -= (flash_size & 5803 ICH_GFPREG_BASE_MASK); 5804 5805 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 5806 5807 hw->flash_bank_size /= 2 * sizeof(uint16_t); 5808 5809 break; 5810 } 5811 case em_pch_spt: 5812 { 5813 int32_t i = 0; 5814 uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */); 5815 5816 eeprom->type = em_eeprom_ich8; 5817 eeprom->use_eerd = FALSE; 5818 eeprom->use_eewr = FALSE; 5819 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 5820 /* 5821 * Zero the shadow RAM structure. But don't load it 5822 * from NVM so as to save time for driver init 5823 */ 5824 if (hw->eeprom_shadow_ram != NULL) { 5825 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5826 hw->eeprom_shadow_ram[i].modified = 5827 FALSE; 5828 hw->eeprom_shadow_ram[i].eeprom_word = 5829 0xFFFF; 5830 } 5831 } 5832 hw->flash_base_addr = 0; 5833 flash_size = ((flash_size >> 1) & 0x1f) + 1; 5834 flash_size *= 4096; 5835 hw->flash_bank_size = flash_size / 4; 5836 } 5837 break; 5838 default: 5839 break; 5840 } 5841 5842 if (eeprom->type == em_eeprom_spi) { 5843 /* 5844 * eeprom_size will be an enum [0..8] that maps to eeprom 5845 * sizes 128B to 32KB (incremented by powers of 2). 5846 */ 5847 if (hw->mac_type <= em_82547_rev_2) { 5848 /* Set to default value for initial eeprom read. */ 5849 eeprom->word_size = 64; 5850 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 5851 &eeprom_size); 5852 if (ret_val) 5853 return ret_val; 5854 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 5855 EEPROM_SIZE_SHIFT; 5856 /* 5857 * 256B eeprom size was not supported in earlier 5858 * hardware, so we bump eeprom_size up one to ensure 5859 * that "1" (which maps to 256B) is never the result 5860 * used in the shifting logic below. 5861 */ 5862 if (eeprom_size) 5863 eeprom_size++; 5864 } else { 5865 eeprom_size = (uint16_t) ( 5866 (eecd & E1000_EECD_SIZE_EX_MASK) >> 5867 E1000_EECD_SIZE_EX_SHIFT); 5868 } 5869 5870 /* EEPROM access above 16k is unsupported */ 5871 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 5872 EEPROM_WORD_SIZE_SHIFT_MAX) { 5873 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 5874 } else { 5875 eeprom->word_size = 1 << 5876 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 5877 } 5878 } 5879 return ret_val; 5880 } 5881 5882 /****************************************************************************** 5883 * Raises the EEPROM's clock input. 5884 * 5885 * hw - Struct containing variables accessed by shared code 5886 * eecd - EECD's current value 5887 *****************************************************************************/ 5888 static void 5889 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 5890 { 5891 /* 5892 * Raise the clock input to the EEPROM (by setting the SK bit), and 5893 * then wait <delay> microseconds. 5894 */ 5895 *eecd = *eecd | E1000_EECD_SK; 5896 E1000_WRITE_REG(hw, EECD, *eecd); 5897 E1000_WRITE_FLUSH(hw); 5898 usec_delay(hw->eeprom.delay_usec); 5899 } 5900 5901 /****************************************************************************** 5902 * Lowers the EEPROM's clock input. 5903 * 5904 * hw - Struct containing variables accessed by shared code 5905 * eecd - EECD's current value 5906 *****************************************************************************/ 5907 static void 5908 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 5909 { 5910 /* 5911 * Lower the clock input to the EEPROM (by clearing the SK bit), and 5912 * then wait 50 microseconds. 5913 */ 5914 *eecd = *eecd & ~E1000_EECD_SK; 5915 E1000_WRITE_REG(hw, EECD, *eecd); 5916 E1000_WRITE_FLUSH(hw); 5917 usec_delay(hw->eeprom.delay_usec); 5918 } 5919 5920 /****************************************************************************** 5921 * Shift data bits out to the EEPROM. 5922 * 5923 * hw - Struct containing variables accessed by shared code 5924 * data - data to send to the EEPROM 5925 * count - number of bits to shift out 5926 *****************************************************************************/ 5927 static void 5928 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 5929 { 5930 struct em_eeprom_info *eeprom = &hw->eeprom; 5931 uint32_t eecd; 5932 uint32_t mask; 5933 /* 5934 * We need to shift "count" bits out to the EEPROM. So, value in the 5935 * "data" parameter will be shifted out to the EEPROM one bit at a 5936 * time. In order to do this, "data" must be broken down into bits. 5937 */ 5938 mask = 0x01 << (count - 1); 5939 eecd = E1000_READ_REG(hw, EECD); 5940 if (eeprom->type == em_eeprom_microwire) { 5941 eecd &= ~E1000_EECD_DO; 5942 } else if (eeprom->type == em_eeprom_spi) { 5943 eecd |= E1000_EECD_DO; 5944 } 5945 do { 5946 /* 5947 * A "1" is shifted out to the EEPROM by setting bit "DI" to 5948 * a "1", and then raising and then lowering the clock (the 5949 * SK bit controls the clock input to the EEPROM). A "0" is 5950 * shifted out to the EEPROM by setting "DI" to "0" and then 5951 * raising and then lowering the clock. 5952 */ 5953 eecd &= ~E1000_EECD_DI; 5954 5955 if (data & mask) 5956 eecd |= E1000_EECD_DI; 5957 5958 E1000_WRITE_REG(hw, EECD, eecd); 5959 E1000_WRITE_FLUSH(hw); 5960 5961 usec_delay(eeprom->delay_usec); 5962 5963 em_raise_ee_clk(hw, &eecd); 5964 em_lower_ee_clk(hw, &eecd); 5965 5966 mask = mask >> 1; 5967 5968 } while (mask); 5969 5970 /* We leave the "DI" bit set to "0" when we leave this routine. */ 5971 eecd &= ~E1000_EECD_DI; 5972 E1000_WRITE_REG(hw, EECD, eecd); 5973 } 5974 5975 /****************************************************************************** 5976 * Shift data bits in from the EEPROM 5977 * 5978 * hw - Struct containing variables accessed by shared code 5979 *****************************************************************************/ 5980 static uint16_t 5981 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 5982 { 5983 uint32_t eecd; 5984 uint32_t i; 5985 uint16_t data; 5986 /* 5987 * In order to read a register from the EEPROM, we need to shift 5988 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 5989 * the clock input to the EEPROM (setting the SK bit), and then 5990 * reading the value of the "DO" bit. During this "shifting in" 5991 * process the "DI" bit should always be clear. 5992 */ 5993 5994 eecd = E1000_READ_REG(hw, EECD); 5995 5996 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 5997 data = 0; 5998 5999 for (i = 0; i < count; i++) { 6000 data = data << 1; 6001 em_raise_ee_clk(hw, &eecd); 6002 6003 eecd = E1000_READ_REG(hw, EECD); 6004 6005 eecd &= ~(E1000_EECD_DI); 6006 if (eecd & E1000_EECD_DO) 6007 data |= 1; 6008 6009 em_lower_ee_clk(hw, &eecd); 6010 } 6011 6012 return data; 6013 } 6014 /****************************************************************************** 6015 * Prepares EEPROM for access 6016 * 6017 * hw - Struct containing variables accessed by shared code 6018 * 6019 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 6020 * function should be called before issuing a command to the EEPROM. 6021 *****************************************************************************/ 6022 static int32_t 6023 em_acquire_eeprom(struct em_hw *hw) 6024 { 6025 struct em_eeprom_info *eeprom = &hw->eeprom; 6026 uint32_t eecd, i = 0; 6027 DEBUGFUNC("em_acquire_eeprom"); 6028 6029 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6030 return -E1000_ERR_SWFW_SYNC; 6031 eecd = E1000_READ_REG(hw, EECD); 6032 6033 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 6034 /* Request EEPROM Access */ 6035 if (hw->mac_type > em_82544) { 6036 eecd |= E1000_EECD_REQ; 6037 E1000_WRITE_REG(hw, EECD, eecd); 6038 eecd = E1000_READ_REG(hw, EECD); 6039 while ((!(eecd & E1000_EECD_GNT)) && 6040 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 6041 i++; 6042 usec_delay(5); 6043 eecd = E1000_READ_REG(hw, EECD); 6044 } 6045 if (!(eecd & E1000_EECD_GNT)) { 6046 eecd &= ~E1000_EECD_REQ; 6047 E1000_WRITE_REG(hw, EECD, eecd); 6048 DEBUGOUT("Could not acquire EEPROM grant\n"); 6049 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6050 return -E1000_ERR_EEPROM; 6051 } 6052 } 6053 } 6054 6055 /* Setup EEPROM for Read/Write */ 6056 if (eeprom->type == em_eeprom_microwire) { 6057 /* Clear SK and DI */ 6058 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 6059 E1000_WRITE_REG(hw, EECD, eecd); 6060 6061 /* Set CS */ 6062 eecd |= E1000_EECD_CS; 6063 E1000_WRITE_REG(hw, EECD, eecd); 6064 } else if (eeprom->type == em_eeprom_spi) { 6065 /* Clear SK and CS */ 6066 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6067 E1000_WRITE_REG(hw, EECD, eecd); 6068 usec_delay(1); 6069 } 6070 return E1000_SUCCESS; 6071 } 6072 6073 /****************************************************************************** 6074 * Returns EEPROM to a "standby" state 6075 * 6076 * hw - Struct containing variables accessed by shared code 6077 *****************************************************************************/ 6078 static void 6079 em_standby_eeprom(struct em_hw *hw) 6080 { 6081 struct em_eeprom_info *eeprom = &hw->eeprom; 6082 uint32_t eecd; 6083 eecd = E1000_READ_REG(hw, EECD); 6084 6085 if (eeprom->type == em_eeprom_microwire) { 6086 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 6087 E1000_WRITE_REG(hw, EECD, eecd); 6088 E1000_WRITE_FLUSH(hw); 6089 usec_delay(eeprom->delay_usec); 6090 6091 /* Clock high */ 6092 eecd |= E1000_EECD_SK; 6093 E1000_WRITE_REG(hw, EECD, eecd); 6094 E1000_WRITE_FLUSH(hw); 6095 usec_delay(eeprom->delay_usec); 6096 6097 /* Select EEPROM */ 6098 eecd |= E1000_EECD_CS; 6099 E1000_WRITE_REG(hw, EECD, eecd); 6100 E1000_WRITE_FLUSH(hw); 6101 usec_delay(eeprom->delay_usec); 6102 6103 /* Clock low */ 6104 eecd &= ~E1000_EECD_SK; 6105 E1000_WRITE_REG(hw, EECD, eecd); 6106 E1000_WRITE_FLUSH(hw); 6107 usec_delay(eeprom->delay_usec); 6108 } else if (eeprom->type == em_eeprom_spi) { 6109 /* Toggle CS to flush commands */ 6110 eecd |= E1000_EECD_CS; 6111 E1000_WRITE_REG(hw, EECD, eecd); 6112 E1000_WRITE_FLUSH(hw); 6113 usec_delay(eeprom->delay_usec); 6114 eecd &= ~E1000_EECD_CS; 6115 E1000_WRITE_REG(hw, EECD, eecd); 6116 E1000_WRITE_FLUSH(hw); 6117 usec_delay(eeprom->delay_usec); 6118 } 6119 } 6120 6121 /****************************************************************************** 6122 * Terminates a command by inverting the EEPROM's chip select pin 6123 * 6124 * hw - Struct containing variables accessed by shared code 6125 *****************************************************************************/ 6126 static void 6127 em_release_eeprom(struct em_hw *hw) 6128 { 6129 uint32_t eecd; 6130 DEBUGFUNC("em_release_eeprom"); 6131 6132 eecd = E1000_READ_REG(hw, EECD); 6133 6134 if (hw->eeprom.type == em_eeprom_spi) { 6135 eecd |= E1000_EECD_CS; /* Pull CS high */ 6136 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 6137 6138 E1000_WRITE_REG(hw, EECD, eecd); 6139 6140 usec_delay(hw->eeprom.delay_usec); 6141 } else if (hw->eeprom.type == em_eeprom_microwire) { 6142 /* cleanup eeprom */ 6143 6144 /* CS on Microwire is active-high */ 6145 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 6146 6147 E1000_WRITE_REG(hw, EECD, eecd); 6148 6149 /* Rising edge of clock */ 6150 eecd |= E1000_EECD_SK; 6151 E1000_WRITE_REG(hw, EECD, eecd); 6152 E1000_WRITE_FLUSH(hw); 6153 usec_delay(hw->eeprom.delay_usec); 6154 6155 /* Falling edge of clock */ 6156 eecd &= ~E1000_EECD_SK; 6157 E1000_WRITE_REG(hw, EECD, eecd); 6158 E1000_WRITE_FLUSH(hw); 6159 usec_delay(hw->eeprom.delay_usec); 6160 } 6161 /* Stop requesting EEPROM access */ 6162 if (hw->mac_type > em_82544) { 6163 eecd &= ~E1000_EECD_REQ; 6164 E1000_WRITE_REG(hw, EECD, eecd); 6165 } 6166 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6167 } 6168 6169 /****************************************************************************** 6170 * Reads a 16 bit word from the EEPROM. 6171 * 6172 * hw - Struct containing variables accessed by shared code 6173 *****************************************************************************/ 6174 STATIC int32_t 6175 em_spi_eeprom_ready(struct em_hw *hw) 6176 { 6177 uint16_t retry_count = 0; 6178 uint8_t spi_stat_reg; 6179 DEBUGFUNC("em_spi_eeprom_ready"); 6180 /* 6181 * Read "Status Register" repeatedly until the LSB is cleared. The 6182 * EEPROM will signal that the command has been completed by clearing 6183 * bit 0 of the internal status register. If it's not cleared within 6184 * 5 milliseconds, then error out. 6185 */ 6186 retry_count = 0; 6187 do { 6188 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 6189 hw->eeprom.opcode_bits); 6190 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 6191 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 6192 break; 6193 6194 usec_delay(5); 6195 retry_count += 5; 6196 6197 em_standby_eeprom(hw); 6198 } while (retry_count < EEPROM_MAX_RETRY_SPI); 6199 /* 6200 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 6201 * only 0-5mSec on 5V devices) 6202 */ 6203 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 6204 DEBUGOUT("SPI EEPROM Status error\n"); 6205 return -E1000_ERR_EEPROM; 6206 } 6207 return E1000_SUCCESS; 6208 } 6209 6210 /****************************************************************************** 6211 * Reads a 16 bit word from the EEPROM. 6212 * 6213 * hw - Struct containing variables accessed by shared code 6214 * offset - offset of word in the EEPROM to read 6215 * data - word read from the EEPROM 6216 * words - number of words to read 6217 *****************************************************************************/ 6218 int32_t 6219 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6220 uint16_t *data) 6221 { 6222 struct em_eeprom_info *eeprom = &hw->eeprom; 6223 uint32_t i = 0; 6224 DEBUGFUNC("em_read_eeprom"); 6225 6226 /* If eeprom is not yet detected, do so now */ 6227 if (eeprom->word_size == 0) 6228 em_init_eeprom_params(hw); 6229 /* 6230 * A check for invalid values: offset too large, too many words, and 6231 * not enough words. 6232 */ 6233 if ((offset >= eeprom->word_size) || 6234 (words > eeprom->word_size - offset) || 6235 (words == 0)) { 6236 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 6237 " size = %d\n", offset, eeprom->word_size); 6238 return -E1000_ERR_EEPROM; 6239 } 6240 /* 6241 * EEPROM's that don't use EERD to read require us to bit-bang the 6242 * SPI directly. In this case, we need to acquire the EEPROM so that 6243 * FW or other port software does not interrupt. 6244 */ 6245 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 6246 em_get_flash_presence_i210(hw) == TRUE && 6247 hw->eeprom.use_eerd == FALSE) { 6248 /* Prepare the EEPROM for bit-bang reading */ 6249 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6250 return -E1000_ERR_EEPROM; 6251 } 6252 /* Eerd register EEPROM access requires no eeprom aquire/release */ 6253 if (eeprom->use_eerd == TRUE) 6254 return em_read_eeprom_eerd(hw, offset, words, data); 6255 6256 /* ICH EEPROM access is done via the ICH flash controller */ 6257 if (eeprom->type == em_eeprom_ich8) 6258 return em_read_eeprom_ich8(hw, offset, words, data); 6259 6260 /* Some i210/i211 have a special OTP chip */ 6261 if (eeprom->type == em_eeprom_invm) 6262 return em_read_invm_i210(hw, offset, words, data); 6263 6264 /* 6265 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 6266 * acquired the EEPROM at this point, so any returns should relase it 6267 */ 6268 if (eeprom->type == em_eeprom_spi) { 6269 uint16_t word_in; 6270 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6271 if (em_spi_eeprom_ready(hw)) { 6272 em_release_eeprom(hw); 6273 return -E1000_ERR_EEPROM; 6274 } 6275 em_standby_eeprom(hw); 6276 /* 6277 * Some SPI eeproms use the 8th address bit embedded in the 6278 * opcode 6279 */ 6280 if ((eeprom->address_bits == 8) && (offset >= 128)) 6281 read_opcode |= EEPROM_A8_OPCODE_SPI; 6282 6283 /* Send the READ command (opcode + addr) */ 6284 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6285 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6286 eeprom->address_bits); 6287 /* 6288 * Read the data. The address of the eeprom internally 6289 * increments with each byte (spi) being read, saving on the 6290 * overhead of eeprom setup and tear-down. The address 6291 * counter will roll over if reading beyond the size of the 6292 * eeprom, thus allowing the entire memory to be read 6293 * starting from any offset. 6294 */ 6295 for (i = 0; i < words; i++) { 6296 word_in = em_shift_in_ee_bits(hw, 16); 6297 data[i] = (word_in >> 8) | (word_in << 8); 6298 } 6299 } else if (eeprom->type == em_eeprom_microwire) { 6300 for (i = 0; i < words; i++) { 6301 /* Send the READ command (opcode + addr) */ 6302 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6303 eeprom->opcode_bits); 6304 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6305 eeprom->address_bits); 6306 /* 6307 * Read the data. For microwire, each word requires 6308 * the overhead of eeprom setup and tear-down. 6309 */ 6310 data[i] = em_shift_in_ee_bits(hw, 16); 6311 em_standby_eeprom(hw); 6312 } 6313 } 6314 /* End this read operation */ 6315 em_release_eeprom(hw); 6316 6317 return E1000_SUCCESS; 6318 } 6319 6320 /****************************************************************************** 6321 * Reads a 16 bit word from the EEPROM using the EERD register. 6322 * 6323 * hw - Struct containing variables accessed by shared code 6324 * offset - offset of word in the EEPROM to read 6325 * data - word read from the EEPROM 6326 * words - number of words to read 6327 *****************************************************************************/ 6328 STATIC int32_t 6329 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6330 uint16_t *data) 6331 { 6332 uint32_t i, eerd = 0; 6333 int32_t error = 0; 6334 for (i = 0; i < words; i++) { 6335 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6336 E1000_EEPROM_RW_REG_START; 6337 6338 E1000_WRITE_REG(hw, EERD, eerd); 6339 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6340 6341 if (error) { 6342 break; 6343 } 6344 data[i] = (E1000_READ_REG(hw, EERD) >> 6345 E1000_EEPROM_RW_REG_DATA); 6346 6347 } 6348 6349 return error; 6350 } 6351 6352 /****************************************************************************** 6353 * Writes a 16 bit word from the EEPROM using the EEWR register. 6354 * 6355 * hw - Struct containing variables accessed by shared code 6356 * offset - offset of word in the EEPROM to read 6357 * data - word read from the EEPROM 6358 * words - number of words to read 6359 *****************************************************************************/ 6360 STATIC int32_t 6361 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6362 uint16_t *data) 6363 { 6364 uint32_t register_value = 0; 6365 uint32_t i = 0; 6366 int32_t error = 0; 6367 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6368 return -E1000_ERR_SWFW_SYNC; 6369 6370 for (i = 0; i < words; i++) { 6371 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6372 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6373 E1000_EEPROM_RW_REG_START; 6374 6375 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6376 if (error) { 6377 break; 6378 } 6379 E1000_WRITE_REG(hw, EEWR, register_value); 6380 6381 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6382 6383 if (error) { 6384 break; 6385 } 6386 } 6387 6388 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6389 return error; 6390 } 6391 6392 /****************************************************************************** 6393 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6394 * 6395 * hw - Struct containing variables accessed by shared code 6396 *****************************************************************************/ 6397 STATIC int32_t 6398 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6399 { 6400 uint32_t attempts = 100000; 6401 uint32_t i, reg = 0; 6402 int32_t done = E1000_ERR_EEPROM; 6403 for (i = 0; i < attempts; i++) { 6404 if (eerd == E1000_EEPROM_POLL_READ) 6405 reg = E1000_READ_REG(hw, EERD); 6406 else 6407 reg = E1000_READ_REG(hw, EEWR); 6408 6409 if (reg & E1000_EEPROM_RW_REG_DONE) { 6410 done = E1000_SUCCESS; 6411 break; 6412 } 6413 usec_delay(5); 6414 } 6415 6416 return done; 6417 } 6418 6419 /****************************************************************************** 6420 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6421 * 6422 * hw - Struct containing variables accessed by shared code 6423 *****************************************************************************/ 6424 STATIC boolean_t 6425 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6426 { 6427 uint32_t eecd = 0; 6428 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6429 6430 if (IS_ICH8(hw->mac_type)) 6431 return FALSE; 6432 6433 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6434 eecd = E1000_READ_REG(hw, EECD); 6435 6436 /* Isolate bits 15 & 16 */ 6437 eecd = ((eecd >> 15) & 0x03); 6438 6439 /* If both bits are set, device is Flash type */ 6440 if (eecd == 0x03) { 6441 return FALSE; 6442 } 6443 } 6444 return TRUE; 6445 } 6446 6447 /****************************************************************************** 6448 * Check if flash device is detected. 6449 * 6450 * hw - Struct containing variables accessed by shared code 6451 *****************************************************************************/ 6452 boolean_t 6453 em_get_flash_presence_i210(struct em_hw *hw) 6454 { 6455 uint32_t eecd; 6456 DEBUGFUNC("em_get_flash_presence_i210"); 6457 6458 if (hw->mac_type != em_i210) 6459 return TRUE; 6460 6461 eecd = E1000_READ_REG(hw, EECD); 6462 6463 if (eecd & E1000_EECD_FLUPD) 6464 return TRUE; 6465 6466 return FALSE; 6467 } 6468 6469 /****************************************************************************** 6470 * Verifies that the EEPROM has a valid checksum 6471 * 6472 * hw - Struct containing variables accessed by shared code 6473 * 6474 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6475 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6476 * valid. 6477 *****************************************************************************/ 6478 int32_t 6479 em_validate_eeprom_checksum(struct em_hw *hw) 6480 { 6481 uint16_t checksum = 0; 6482 uint16_t i, eeprom_data; 6483 uint16_t checksum_reg; 6484 DEBUGFUNC("em_validate_eeprom_checksum"); 6485 6486 checksum_reg = hw->mac_type != em_icp_xxxx ? 6487 EEPROM_CHECKSUM_REG : 6488 EEPROM_CHECKSUM_REG_ICP_xxxx; 6489 6490 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6491 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6492 /* 6493 * Check bit 4 of word 10h. If it is 0, firmware is done 6494 * updating 10h-12h. Checksum may need to be fixed. 6495 */ 6496 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6497 if ((eeprom_data & 0x10) == 0) { 6498 /* 6499 * Read 0x23 and check bit 15. This bit is a 1 when 6500 * the checksum has already been fixed. If the 6501 * checksum is still wrong and this bit is a 1, we 6502 * need to return bad checksum. Otherwise, we need 6503 * to set this bit to a 1 and update the checksum. 6504 */ 6505 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6506 if ((eeprom_data & 0x8000) == 0) { 6507 eeprom_data |= 0x8000; 6508 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6509 em_update_eeprom_checksum(hw); 6510 } 6511 } 6512 } 6513 if (IS_ICH8(hw->mac_type)) { 6514 uint16_t word; 6515 uint16_t valid_csum_mask; 6516 6517 /* 6518 * Drivers must allocate the shadow ram structure for the 6519 * EEPROM checksum to be updated. Otherwise, this bit as 6520 * well as the checksum must both be set correctly for this 6521 * validation to pass. 6522 */ 6523 switch (hw->mac_type) { 6524 case em_pch_lpt: 6525 case em_pch_spt: 6526 word = EEPROM_COMPAT; 6527 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 6528 break; 6529 default: 6530 word = EEPROM_FUTURE_INIT_WORD1; 6531 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 6532 break; 6533 } 6534 em_read_eeprom(hw, word, 1, &eeprom_data); 6535 if ((eeprom_data & valid_csum_mask) == 0) { 6536 eeprom_data |= valid_csum_mask; 6537 em_write_eeprom(hw, word, 1, &eeprom_data); 6538 em_update_eeprom_checksum(hw); 6539 } 6540 } 6541 for (i = 0; i < (checksum_reg + 1); i++) { 6542 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6543 DEBUGOUT("EEPROM Read Error\n"); 6544 return -E1000_ERR_EEPROM; 6545 } 6546 checksum += eeprom_data; 6547 } 6548 6549 if (checksum == (uint16_t) EEPROM_SUM) 6550 return E1000_SUCCESS; 6551 else { 6552 DEBUGOUT("EEPROM Checksum Invalid\n"); 6553 return -E1000_ERR_EEPROM; 6554 } 6555 } 6556 6557 /****************************************************************************** 6558 * Calculates the EEPROM checksum and writes it to the EEPROM 6559 * 6560 * hw - Struct containing variables accessed by shared code 6561 * 6562 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6563 * Writes the difference to word offset 63 of the EEPROM. 6564 *****************************************************************************/ 6565 int32_t 6566 em_update_eeprom_checksum(struct em_hw *hw) 6567 { 6568 uint32_t ctrl_ext; 6569 uint16_t checksum = 0; 6570 uint16_t i, eeprom_data; 6571 DEBUGFUNC("em_update_eeprom_checksum"); 6572 6573 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6574 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6575 DEBUGOUT("EEPROM Read Error\n"); 6576 return -E1000_ERR_EEPROM; 6577 } 6578 checksum += eeprom_data; 6579 } 6580 checksum = (uint16_t) EEPROM_SUM - checksum; 6581 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6582 DEBUGOUT("EEPROM Write Error\n"); 6583 return -E1000_ERR_EEPROM; 6584 } else if (hw->eeprom.type == em_eeprom_flash) { 6585 em_commit_shadow_ram(hw); 6586 } else if (hw->eeprom.type == em_eeprom_ich8) { 6587 em_commit_shadow_ram(hw); 6588 /* 6589 * Reload the EEPROM, or else modifications will not appear 6590 * until after next adapter reset. 6591 */ 6592 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6593 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6594 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6595 msec_delay(10); 6596 } 6597 return E1000_SUCCESS; 6598 } 6599 6600 /****************************************************************************** 6601 * Parent function for writing words to the different EEPROM types. 6602 * 6603 * hw - Struct containing variables accessed by shared code 6604 * offset - offset within the EEPROM to be written to 6605 * words - number of words to write 6606 * data - 16 bit word to be written to the EEPROM 6607 * 6608 * If em_update_eeprom_checksum is not called after this function, the 6609 * EEPROM will most likely contain an invalid checksum. 6610 *****************************************************************************/ 6611 int32_t 6612 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6613 uint16_t *data) 6614 { 6615 struct em_eeprom_info *eeprom = &hw->eeprom; 6616 int32_t status = 0; 6617 DEBUGFUNC("em_write_eeprom"); 6618 6619 /* If eeprom is not yet detected, do so now */ 6620 if (eeprom->word_size == 0) 6621 em_init_eeprom_params(hw); 6622 /* 6623 * A check for invalid values: offset too large, too many words, and 6624 * not enough words. 6625 */ 6626 if ((offset >= eeprom->word_size) || 6627 (words > eeprom->word_size - offset) || 6628 (words == 0)) { 6629 DEBUGOUT("\"words\" parameter out of bounds\n"); 6630 return -E1000_ERR_EEPROM; 6631 } 6632 /* 82573/4 writes only through eewr */ 6633 if (eeprom->use_eewr == TRUE) 6634 return em_write_eeprom_eewr(hw, offset, words, data); 6635 6636 if (eeprom->type == em_eeprom_ich8) 6637 return em_write_eeprom_ich8(hw, offset, words, data); 6638 6639 /* Prepare the EEPROM for writing */ 6640 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6641 return -E1000_ERR_EEPROM; 6642 6643 if (eeprom->type == em_eeprom_microwire) { 6644 status = em_write_eeprom_microwire(hw, offset, words, data); 6645 } else { 6646 status = em_write_eeprom_spi(hw, offset, words, data); 6647 msec_delay(10); 6648 } 6649 6650 /* Done with writing */ 6651 em_release_eeprom(hw); 6652 6653 return status; 6654 } 6655 6656 /****************************************************************************** 6657 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6658 * 6659 * hw - Struct containing variables accessed by shared code 6660 * offset - offset within the EEPROM to be written to 6661 * words - number of words to write 6662 * data - pointer to array of 8 bit words to be written to the EEPROM 6663 * 6664 *****************************************************************************/ 6665 STATIC int32_t 6666 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6667 uint16_t *data) 6668 { 6669 struct em_eeprom_info *eeprom = &hw->eeprom; 6670 uint16_t widx = 0; 6671 DEBUGFUNC("em_write_eeprom_spi"); 6672 6673 while (widx < words) { 6674 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6675 if (em_spi_eeprom_ready(hw)) 6676 return -E1000_ERR_EEPROM; 6677 6678 em_standby_eeprom(hw); 6679 6680 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6681 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6682 eeprom->opcode_bits); 6683 6684 em_standby_eeprom(hw); 6685 /* 6686 * Some SPI eeproms use the 8th address bit embedded in the 6687 * opcode 6688 */ 6689 if ((eeprom->address_bits == 8) && (offset >= 128)) 6690 write_opcode |= EEPROM_A8_OPCODE_SPI; 6691 6692 /* Send the Write command (8-bit opcode + addr) */ 6693 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6694 6695 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6696 eeprom->address_bits); 6697 6698 /* Send the data */ 6699 /* 6700 * Loop to allow for up to whole page write (32 bytes) of 6701 * eeprom 6702 */ 6703 while (widx < words) { 6704 uint16_t word_out = data[widx]; 6705 word_out = (word_out >> 8) | (word_out << 8); 6706 em_shift_out_ee_bits(hw, word_out, 16); 6707 widx++; 6708 /* 6709 * Some larger eeprom sizes are capable of a 32-byte 6710 * PAGE WRITE operation, while the smaller eeproms 6711 * are capable of an 8-byte PAGE WRITE operation. 6712 * Break the inner loop to pass new address 6713 */ 6714 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6715 em_standby_eeprom(hw); 6716 break; 6717 } 6718 } 6719 } 6720 6721 return E1000_SUCCESS; 6722 } 6723 6724 /****************************************************************************** 6725 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 6726 * 6727 * hw - Struct containing variables accessed by shared code 6728 * offset - offset within the EEPROM to be written to 6729 * words - number of words to write 6730 * data - pointer to array of 16 bit words to be written to the EEPROM 6731 * 6732 *****************************************************************************/ 6733 STATIC int32_t 6734 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 6735 uint16_t *data) 6736 { 6737 struct em_eeprom_info *eeprom = &hw->eeprom; 6738 uint32_t eecd; 6739 uint16_t words_written = 0; 6740 uint16_t i = 0; 6741 DEBUGFUNC("em_write_eeprom_microwire"); 6742 /* 6743 * Send the write enable command to the EEPROM (3-bit opcode plus 6744 * 6/8-bit dummy address beginning with 11). It's less work to 6745 * include the 11 of the dummy address as part of the opcode than it 6746 * is to shift it over the correct number of bits for the address. 6747 * This puts the EEPROM into write/erase mode. 6748 */ 6749 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 6750 (uint16_t) (eeprom->opcode_bits + 2)); 6751 6752 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6753 6754 /* Prepare the EEPROM */ 6755 em_standby_eeprom(hw); 6756 6757 while (words_written < words) { 6758 /* Send the Write command (3-bit opcode + addr) */ 6759 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 6760 eeprom->opcode_bits); 6761 6762 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 6763 eeprom->address_bits); 6764 6765 /* Send the data */ 6766 em_shift_out_ee_bits(hw, data[words_written], 16); 6767 /* 6768 * Toggle the CS line. This in effect tells the EEPROM to 6769 * execute the previous command. 6770 */ 6771 em_standby_eeprom(hw); 6772 /* 6773 * Read DO repeatedly until it is high (equal to '1'). The 6774 * EEPROM will signal that the command has been completed by 6775 * raising the DO signal. If DO does not go high in 10 6776 * milliseconds, then error out. 6777 */ 6778 for (i = 0; i < 200; i++) { 6779 eecd = E1000_READ_REG(hw, EECD); 6780 if (eecd & E1000_EECD_DO) 6781 break; 6782 usec_delay(50); 6783 } 6784 if (i == 200) { 6785 DEBUGOUT("EEPROM Write did not complete\n"); 6786 return -E1000_ERR_EEPROM; 6787 } 6788 /* Recover from write */ 6789 em_standby_eeprom(hw); 6790 6791 words_written++; 6792 } 6793 /* 6794 * Send the write disable command to the EEPROM (3-bit opcode plus 6795 * 6/8-bit dummy address beginning with 10). It's less work to 6796 * include the 10 of the dummy address as part of the opcode than it 6797 * is to shift it over the correct number of bits for the address. 6798 * This takes the EEPROM out of write/erase mode. 6799 */ 6800 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 6801 (uint16_t) (eeprom->opcode_bits + 2)); 6802 6803 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6804 6805 return E1000_SUCCESS; 6806 } 6807 6808 /****************************************************************************** 6809 * Flushes the cached eeprom to NVM. This is done by saving the modified values 6810 * in the eeprom cache and the non modified values in the currently active bank 6811 * to the new bank. 6812 * 6813 * hw - Struct containing variables accessed by shared code 6814 * offset - offset of word in the EEPROM to read 6815 * data - word read from the EEPROM 6816 * words - number of words to read 6817 *****************************************************************************/ 6818 STATIC int32_t 6819 em_commit_shadow_ram(struct em_hw *hw) 6820 { 6821 uint32_t attempts = 100000; 6822 uint32_t eecd = 0; 6823 uint32_t flop = 0; 6824 uint32_t i = 0; 6825 int32_t error = E1000_SUCCESS; 6826 uint32_t old_bank_offset = 0; 6827 uint32_t new_bank_offset = 0; 6828 uint8_t low_byte = 0; 6829 uint8_t high_byte = 0; 6830 boolean_t sector_write_failed = FALSE; 6831 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6832 /* 6833 * The flop register will be used to determine if flash type 6834 * is STM 6835 */ 6836 flop = E1000_READ_REG(hw, FLOP); 6837 for (i = 0; i < attempts; i++) { 6838 eecd = E1000_READ_REG(hw, EECD); 6839 if ((eecd & E1000_EECD_FLUPD) == 0) { 6840 break; 6841 } 6842 usec_delay(5); 6843 } 6844 6845 if (i == attempts) { 6846 return -E1000_ERR_EEPROM; 6847 } 6848 /* 6849 * If STM opcode located in bits 15:8 of flop, reset firmware 6850 */ 6851 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 6852 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 6853 } 6854 /* Perform the flash update */ 6855 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 6856 6857 for (i = 0; i < attempts; i++) { 6858 eecd = E1000_READ_REG(hw, EECD); 6859 if ((eecd & E1000_EECD_FLUPD) == 0) { 6860 break; 6861 } 6862 usec_delay(5); 6863 } 6864 6865 if (i == attempts) { 6866 return -E1000_ERR_EEPROM; 6867 } 6868 } 6869 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 6870 hw->eeprom_shadow_ram != NULL) { 6871 /* 6872 * We're writing to the opposite bank so if we're on bank 1, 6873 * write to bank 0 etc. We also need to erase the segment 6874 * that is going to be written 6875 */ 6876 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 6877 new_bank_offset = hw->flash_bank_size * 2; 6878 old_bank_offset = 0; 6879 em_erase_ich8_4k_segment(hw, 1); 6880 } else { 6881 old_bank_offset = hw->flash_bank_size * 2; 6882 new_bank_offset = 0; 6883 em_erase_ich8_4k_segment(hw, 0); 6884 } 6885 6886 sector_write_failed = FALSE; 6887 /* 6888 * Loop for every byte in the shadow RAM, which is in units 6889 * of words. 6890 */ 6891 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6892 /* 6893 * Determine whether to write the value stored in the 6894 * other NVM bank or a modified value stored in the 6895 * shadow RAM 6896 */ 6897 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 6898 low_byte = (uint8_t) 6899 hw->eeprom_shadow_ram[i].eeprom_word; 6900 usec_delay(100); 6901 error = em_verify_write_ich8_byte(hw, 6902 (i << 1) + new_bank_offset, low_byte); 6903 6904 if (error != E1000_SUCCESS) 6905 sector_write_failed = TRUE; 6906 else { 6907 high_byte = (uint8_t) 6908 (hw->eeprom_shadow_ram 6909 [i].eeprom_word >> 8); 6910 usec_delay(100); 6911 } 6912 } else { 6913 em_read_ich8_byte(hw, (i << 1) + 6914 old_bank_offset, &low_byte); 6915 usec_delay(100); 6916 error = em_verify_write_ich8_byte(hw, 6917 (i << 1) + new_bank_offset, low_byte); 6918 6919 if (error != E1000_SUCCESS) 6920 sector_write_failed = TRUE; 6921 else { 6922 em_read_ich8_byte(hw, (i << 1) + 6923 old_bank_offset + 1, &high_byte); 6924 usec_delay(100); 6925 } 6926 } 6927 /* 6928 * If the write of the low byte was successful, go 6929 * ahread and write the high byte while checking to 6930 * make sure that if it is the signature byte, then 6931 * it is handled properly 6932 */ 6933 if (sector_write_failed == FALSE) { 6934 /* 6935 * If the word is 0x13, then make sure the 6936 * signature bits (15:14) are 11b until the 6937 * commit has completed. This will allow us 6938 * to write 10b which indicates the signature 6939 * is valid. We want to do this after the 6940 * write has completed so that we don't mark 6941 * the segment valid while the write is still 6942 * in progress 6943 */ 6944 if (i == E1000_ICH_NVM_SIG_WORD) 6945 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 6946 high_byte; 6947 6948 error = em_verify_write_ich8_byte(hw, (i << 1) 6949 + new_bank_offset + 1, high_byte); 6950 if (error != E1000_SUCCESS) 6951 sector_write_failed = TRUE; 6952 6953 } else { 6954 /* 6955 * If the write failed then break from the 6956 * loop and return an error 6957 */ 6958 break; 6959 } 6960 } 6961 /* 6962 * Don't bother writing the segment valid bits if sector 6963 * programming failed. 6964 */ 6965 if (sector_write_failed == FALSE) { 6966 /* 6967 * Finally validate the new segment by setting bit 6968 * 15:14 to 10b in word 0x13 , this can be done 6969 * without an erase as well since these bits are 11 6970 * to start with and we need to change bit 14 to 0b 6971 */ 6972 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6973 new_bank_offset, &high_byte); 6974 high_byte &= 0xBF; 6975 error = em_verify_write_ich8_byte(hw, 6976 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 6977 high_byte); 6978 /* 6979 * And invalidate the previously valid segment by 6980 * setting its signature word (0x13) high_byte to 0b. 6981 * This can be done without an erase because flash 6982 * erase sets all bits to 1's. We can write 1's to 6983 * 0's without an erase 6984 */ 6985 if (error == E1000_SUCCESS) { 6986 error = em_verify_write_ich8_byte(hw, 6987 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6988 old_bank_offset, 0); 6989 } 6990 /* Clear the now not used entry in the cache */ 6991 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6992 hw->eeprom_shadow_ram[i].modified = FALSE; 6993 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 6994 } 6995 } 6996 } 6997 return error; 6998 } 6999 7000 /****************************************************************************** 7001 * Reads the adapter's part number from the EEPROM 7002 * 7003 * hw - Struct containing variables accessed by shared code 7004 * part_num - Adapter's part number 7005 *****************************************************************************/ 7006 int32_t 7007 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 7008 { 7009 uint16_t offset = EEPROM_PBA_BYTE_1; 7010 uint16_t eeprom_data; 7011 DEBUGFUNC("em_read_part_num"); 7012 7013 /* Get word 0 from EEPROM */ 7014 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 7015 DEBUGOUT("EEPROM Read Error\n"); 7016 return -E1000_ERR_EEPROM; 7017 } 7018 /* Save word 0 in upper half of part_num */ 7019 *part_num = (uint32_t) (eeprom_data << 16); 7020 7021 /* Get word 1 from EEPROM */ 7022 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 7023 DEBUGOUT("EEPROM Read Error\n"); 7024 return -E1000_ERR_EEPROM; 7025 } 7026 /* Save word 1 in lower half of part_num */ 7027 *part_num |= eeprom_data; 7028 7029 return E1000_SUCCESS; 7030 } 7031 7032 /****************************************************************************** 7033 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 7034 * second function of dual function devices 7035 * 7036 * hw - Struct containing variables accessed by shared code 7037 *****************************************************************************/ 7038 int32_t 7039 em_read_mac_addr(struct em_hw *hw) 7040 { 7041 uint16_t offset; 7042 uint16_t eeprom_data, i; 7043 uint16_t ia_base_addr = 0; 7044 DEBUGFUNC("em_read_mac_addr"); 7045 7046 if (hw->mac_type == em_icp_xxxx) { 7047 ia_base_addr = (uint16_t) 7048 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 7049 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 7050 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 7051 } 7052 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 7053 offset = i >> 1; 7054 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 7055 < 0) { 7056 DEBUGOUT("EEPROM Read Error\n"); 7057 return -E1000_ERR_EEPROM; 7058 } 7059 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 7060 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 7061 } 7062 7063 switch (hw->mac_type) { 7064 default: 7065 break; 7066 case em_82546: 7067 case em_82546_rev_3: 7068 case em_82571: 7069 case em_82575: 7070 case em_80003es2lan: 7071 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 7072 hw->perm_mac_addr[5] ^= 0x01; 7073 break; 7074 } 7075 7076 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 7077 hw->mac_addr[i] = hw->perm_mac_addr[i]; 7078 return E1000_SUCCESS; 7079 } 7080 7081 /****************************************************************************** 7082 * Explicitly disables jumbo frames and resets some PHY registers back to hw- 7083 * defaults. This is necessary in case the ethernet cable was inserted AFTER 7084 * the firmware initialized the PHY. Otherwise it is left in a state where 7085 * it is possible to transmit but not receive packets. Observed on I217-LM and 7086 * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c. 7087 * 7088 * hw - Struct containing variables accessed by shared code 7089 *****************************************************************************/ 7090 STATIC int32_t 7091 em_phy_no_cable_workaround(struct em_hw *hw) { 7092 int32_t ret_val, dft_ret_val; 7093 uint32_t mac_reg; 7094 uint16_t data, phy_reg; 7095 7096 /* disable Rx path while enabling workaround */ 7097 em_read_phy_reg(hw, I2_DFT_CTRL, &phy_reg); 7098 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg | (1 << 14)); 7099 if (ret_val) 7100 return ret_val; 7101 7102 /* Write MAC register values back to h/w defaults */ 7103 mac_reg = E1000_READ_REG(hw, FFLT_DBG); 7104 mac_reg &= ~(0xF << 14); 7105 E1000_WRITE_REG(hw, FFLT_DBG, mac_reg); 7106 7107 mac_reg = E1000_READ_REG(hw, RCTL); 7108 mac_reg &= ~E1000_RCTL_SECRC; 7109 E1000_WRITE_REG(hw, RCTL, mac_reg); 7110 7111 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, &data); 7112 if (ret_val) 7113 goto out; 7114 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL, 7115 data & ~(1 << 0)); 7116 if (ret_val) 7117 goto out; 7118 7119 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, &data); 7120 if (ret_val) 7121 goto out; 7122 7123 data &= ~(0xF << 8); 7124 data |= (0xB << 8); 7125 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, data); 7126 if (ret_val) 7127 goto out; 7128 7129 /* Write PHY register values back to h/w defaults */ 7130 em_read_phy_reg(hw, I2_SMBUS_CTRL, &data); 7131 data &= ~(0x7F << 5); 7132 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL, data); 7133 if (ret_val) 7134 goto out; 7135 7136 em_read_phy_reg(hw, I2_MODE_CTRL, &data); 7137 data |= (1 << 13); 7138 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL, data); 7139 if (ret_val) 7140 goto out; 7141 7142 /* 7143 * 776.20 and 776.23 are not documented in 7144 * i217-ethernet-controller-datasheet.pdf... 7145 */ 7146 em_read_phy_reg(hw, PHY_REG(776, 20), &data); 7147 data &= ~(0x3FF << 2); 7148 data |= (0x8 << 2); 7149 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20), data); 7150 if (ret_val) 7151 goto out; 7152 7153 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23), 0x7E00); 7154 if (ret_val) 7155 goto out; 7156 7157 em_read_phy_reg(hw, I2_PCIE_POWER_CTRL, &data); 7158 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL, data & ~(1 << 10)); 7159 if (ret_val) 7160 goto out; 7161 7162 out: 7163 /* re-enable Rx path after enabling workaround */ 7164 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL, phy_reg & ~(1 << 14)); 7165 if (ret_val) 7166 return ret_val; 7167 else 7168 return dft_ret_val; 7169 } 7170 7171 /****************************************************************************** 7172 * Initializes receive address filters. 7173 * 7174 * hw - Struct containing variables accessed by shared code 7175 * 7176 * Places the MAC address in receive address register 0 and clears the rest 7177 * of the receive addresss registers. Clears the multicast table. Assumes 7178 * the receiver is in reset when the routine is called. 7179 *****************************************************************************/ 7180 STATIC void 7181 em_init_rx_addrs(struct em_hw *hw) 7182 { 7183 uint32_t i; 7184 uint32_t rar_num; 7185 DEBUGFUNC("em_init_rx_addrs"); 7186 7187 if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt || hw->mac_type == em_pch2lan) 7188 if (em_phy_no_cable_workaround(hw)) 7189 printf(" ...failed to apply em_phy_no_cable_" 7190 "workaround.\n"); 7191 7192 /* Setup the receive address. */ 7193 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 7194 7195 em_rar_set(hw, hw->mac_addr, 0); 7196 7197 rar_num = E1000_RAR_ENTRIES; 7198 /* 7199 * Reserve a spot for the Locally Administered Address to work around 7200 * an 82571 issue in which a reset on one port will reload the MAC on 7201 * the other port. 7202 */ 7203 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7204 rar_num -= 1; 7205 if (IS_ICH8(hw->mac_type)) 7206 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 7207 if (hw->mac_type == em_ich8lan) 7208 rar_num -= 1; 7209 if (hw->mac_type == em_82580) 7210 rar_num = E1000_RAR_ENTRIES_82580; 7211 if (hw->mac_type == em_i210) 7212 rar_num = E1000_RAR_ENTRIES_82575; 7213 if (hw->mac_type == em_i350) 7214 rar_num = E1000_RAR_ENTRIES_I350; 7215 7216 /* Zero out the other 15 receive addresses. */ 7217 DEBUGOUT("Clearing RAR[1-15]\n"); 7218 for (i = 1; i < rar_num; i++) { 7219 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7220 E1000_WRITE_FLUSH(hw); 7221 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7222 E1000_WRITE_FLUSH(hw); 7223 } 7224 } 7225 7226 /****************************************************************************** 7227 * Updates the MAC's list of multicast addresses. 7228 * 7229 * hw - Struct containing variables accessed by shared code 7230 * mc_addr_list - the list of new multicast addresses 7231 * mc_addr_count - number of addresses 7232 * pad - number of bytes between addresses in the list 7233 * rar_used_count - offset where to start adding mc addresses into the RAR's 7234 * 7235 * The given list replaces any existing list. Clears the last 15 receive 7236 * address registers and the multicast table. Uses receive address registers 7237 * for the first 15 multicast addresses, and hashes the rest into the 7238 * multicast table. 7239 *****************************************************************************/ 7240 void 7241 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 7242 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 7243 { 7244 uint32_t hash_value; 7245 uint32_t i; 7246 uint32_t num_rar_entry; 7247 uint32_t num_mta_entry; 7248 DEBUGFUNC("em_mc_addr_list_update"); 7249 /* 7250 * Set the new number of MC addresses that we are being requested to 7251 * use. 7252 */ 7253 hw->num_mc_addrs = mc_addr_count; 7254 7255 /* Clear RAR[1-15] */ 7256 DEBUGOUT(" Clearing RAR[1-15]\n"); 7257 num_rar_entry = E1000_RAR_ENTRIES; 7258 if (IS_ICH8(hw->mac_type)) 7259 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 7260 if (hw->mac_type == em_ich8lan) 7261 num_rar_entry -= 1; 7262 /* 7263 * Reserve a spot for the Locally Administered Address to work around 7264 * an 82571 issue in which a reset on one port will reload the MAC on 7265 * the other port. 7266 */ 7267 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 7268 num_rar_entry -= 1; 7269 7270 for (i = rar_used_count; i < num_rar_entry; i++) { 7271 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 7272 E1000_WRITE_FLUSH(hw); 7273 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 7274 E1000_WRITE_FLUSH(hw); 7275 } 7276 7277 /* Clear the MTA */ 7278 DEBUGOUT(" Clearing MTA\n"); 7279 num_mta_entry = E1000_NUM_MTA_REGISTERS; 7280 if (IS_ICH8(hw->mac_type)) 7281 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 7282 7283 for (i = 0; i < num_mta_entry; i++) { 7284 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 7285 E1000_WRITE_FLUSH(hw); 7286 } 7287 7288 /* Add the new addresses */ 7289 for (i = 0; i < mc_addr_count; i++) { 7290 DEBUGOUT(" Adding the multicast addresses:\n"); 7291 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 7292 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 7293 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 7294 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 7295 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 7296 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 7297 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 7298 7299 hash_value = em_hash_mc_addr(hw, mc_addr_list + 7300 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 7301 7302 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 7303 /* 7304 * Place this multicast address in the RAR if there is room, * 7305 * else put it in the MTA 7306 */ 7307 if (rar_used_count < num_rar_entry) { 7308 em_rar_set(hw, mc_addr_list + 7309 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 7310 rar_used_count); 7311 rar_used_count++; 7312 } else { 7313 em_mta_set(hw, hash_value); 7314 } 7315 } 7316 DEBUGOUT("MC Update Complete\n"); 7317 } 7318 7319 /****************************************************************************** 7320 * Hashes an address to determine its location in the multicast table 7321 * 7322 * hw - Struct containing variables accessed by shared code 7323 * mc_addr - the multicast address to hash 7324 *****************************************************************************/ 7325 uint32_t 7326 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 7327 { 7328 uint32_t hash_value = 0; 7329 /* 7330 * The portion of the address that is used for the hash table is 7331 * determined by the mc_filter_type setting. 7332 */ 7333 switch (hw->mc_filter_type) { 7334 /* 7335 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 7336 * MSB 7337 */ 7338 case 0: 7339 if (IS_ICH8(hw->mac_type)) { 7340 /* [47:38] i.e. 0x158 for above example address */ 7341 hash_value = ((mc_addr[4] >> 6) | 7342 (((uint16_t) mc_addr[5]) << 2)); 7343 } else { 7344 /* [47:36] i.e. 0x563 for above example address */ 7345 hash_value = ((mc_addr[4] >> 4) | 7346 (((uint16_t) mc_addr[5]) << 4)); 7347 } 7348 break; 7349 case 1: 7350 if (IS_ICH8(hw->mac_type)) { 7351 /* [46:37] i.e. 0x2B1 for above example address */ 7352 hash_value = ((mc_addr[4] >> 5) | 7353 (((uint16_t) mc_addr[5]) << 3)); 7354 } else { 7355 /* [46:35] i.e. 0xAC6 for above example address */ 7356 hash_value = ((mc_addr[4] >> 3) | 7357 (((uint16_t) mc_addr[5]) << 5)); 7358 } 7359 break; 7360 case 2: 7361 if (IS_ICH8(hw->mac_type)) { 7362 /* [45:36] i.e. 0x163 for above example address */ 7363 hash_value = ((mc_addr[4] >> 4) | 7364 (((uint16_t) mc_addr[5]) << 4)); 7365 } else { 7366 /* [45:34] i.e. 0x5D8 for above example address */ 7367 hash_value = ((mc_addr[4] >> 2) | 7368 (((uint16_t) mc_addr[5]) << 6)); 7369 } 7370 break; 7371 case 3: 7372 if (IS_ICH8(hw->mac_type)) { 7373 /* [43:34] i.e. 0x18D for above example address */ 7374 hash_value = ((mc_addr[4] >> 2) | 7375 (((uint16_t) mc_addr[5]) << 6)); 7376 } else { 7377 /* [43:32] i.e. 0x634 for above example address */ 7378 hash_value = ((mc_addr[4]) | 7379 (((uint16_t) mc_addr[5]) << 8)); 7380 } 7381 break; 7382 } 7383 7384 hash_value &= 0xFFF; 7385 if (IS_ICH8(hw->mac_type)) 7386 hash_value &= 0x3FF; 7387 7388 return hash_value; 7389 } 7390 7391 /****************************************************************************** 7392 * Sets the bit in the multicast table corresponding to the hash value. 7393 * 7394 * hw - Struct containing variables accessed by shared code 7395 * hash_value - Multicast address hash value 7396 *****************************************************************************/ 7397 void 7398 em_mta_set(struct em_hw *hw, uint32_t hash_value) 7399 { 7400 uint32_t hash_bit, hash_reg; 7401 uint32_t mta; 7402 uint32_t temp; 7403 /* 7404 * The MTA is a register array of 128 32-bit registers. It is treated 7405 * like an array of 4096 bits. We want to set bit 7406 * BitArray[hash_value]. So we figure out what register the bit is 7407 * in, read it, OR in the new bit, then write back the new value. 7408 * The register is determined by the upper 7 bits of the hash value 7409 * and the bit within that register are determined by the lower 5 7410 * bits of the value. 7411 */ 7412 hash_reg = (hash_value >> 5) & 0x7F; 7413 if (IS_ICH8(hw->mac_type)) 7414 hash_reg &= 0x1F; 7415 7416 hash_bit = hash_value & 0x1F; 7417 7418 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 7419 7420 mta |= (1 << hash_bit); 7421 /* 7422 * If we are on an 82544 and we are trying to write an odd offset in 7423 * the MTA, save off the previous entry before writing and restore 7424 * the old value after writing. 7425 */ 7426 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 7427 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 7428 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7429 E1000_WRITE_FLUSH(hw); 7430 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 7431 E1000_WRITE_FLUSH(hw); 7432 } else { 7433 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7434 E1000_WRITE_FLUSH(hw); 7435 } 7436 } 7437 7438 /****************************************************************************** 7439 * Puts an ethernet address into a receive address register. 7440 * 7441 * hw - Struct containing variables accessed by shared code 7442 * addr - Address to put into receive address register 7443 * index - Receive address register to write 7444 *****************************************************************************/ 7445 void 7446 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 7447 { 7448 uint32_t rar_low, rar_high; 7449 /* 7450 * HW expects these in little endian so we reverse the byte order 7451 * from network order (big endian) to little endian 7452 */ 7453 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 7454 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 7455 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 7456 /* 7457 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 7458 * unit hang. 7459 * 7460 * Description: If there are any Rx frames queued up or otherwise 7461 * present in the HW before RSS is enabled, and then we enable RSS, 7462 * the HW Rx unit will hang. To work around this issue, we have to 7463 * disable receives and flush out all Rx frames before we enable RSS. 7464 * To do so, we modify we redirect all Rx traffic to manageability 7465 * and then reset the HW. This flushes away Rx frames, and (since the 7466 * redirections to manageability persists across resets) keeps new 7467 * ones from coming in while we work. Then, we clear the Address 7468 * Valid AV bit for all MAC addresses and undo the re-direction to 7469 * manageability. Now, frames are coming in again, but the MAC won't 7470 * accept them, so far so good. We now proceed to initialize RSS (if 7471 * necessary) and configure the Rx unit. Last, we re-enable the AV 7472 * bits and continue on our merry way. 7473 */ 7474 switch (hw->mac_type) { 7475 case em_82571: 7476 case em_82572: 7477 case em_80003es2lan: 7478 if (hw->leave_av_bit_off == TRUE) 7479 break; 7480 default: 7481 /* Indicate to hardware the Address is Valid. */ 7482 rar_high |= E1000_RAH_AV; 7483 break; 7484 } 7485 7486 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7487 E1000_WRITE_FLUSH(hw); 7488 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7489 E1000_WRITE_FLUSH(hw); 7490 } 7491 7492 /****************************************************************************** 7493 * Clears the VLAN filer table 7494 * 7495 * hw - Struct containing variables accessed by shared code 7496 *****************************************************************************/ 7497 STATIC void 7498 em_clear_vfta(struct em_hw *hw) 7499 { 7500 uint32_t offset; 7501 uint32_t vfta_value = 0; 7502 uint32_t vfta_offset = 0; 7503 uint32_t vfta_bit_in_reg = 0; 7504 if (IS_ICH8(hw->mac_type)) 7505 return; 7506 7507 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7508 if (hw->mng_cookie.vlan_id != 0) { 7509 /* 7510 * The VFTA is a 4096b bit-field, each identifying a 7511 * single VLAN ID. The following operations 7512 * determine which 32b entry (i.e. offset) into the 7513 * array we want to set the VLAN ID (i.e. bit) of the 7514 * manageability unit. 7515 */ 7516 vfta_offset = (hw->mng_cookie.vlan_id >> 7517 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7518 7519 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7520 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7521 } 7522 } 7523 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7524 /* 7525 * If the offset we want to clear is the same offset of the 7526 * manageability VLAN ID, then clear all bits except that of 7527 * the manageability unit 7528 */ 7529 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7530 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7531 E1000_WRITE_FLUSH(hw); 7532 } 7533 } 7534 7535 /* 7536 * Due to hw errata, if the host tries to configure the VFTA register 7537 * while performing queries from the BMC or DMA, then the VFTA in some 7538 * cases won't be written. 7539 */ 7540 void 7541 em_clear_vfta_i350(struct em_hw *hw) 7542 { 7543 uint32_t offset; 7544 int i; 7545 7546 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7547 for (i = 0; i < 10; i++) 7548 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 7549 E1000_WRITE_FLUSH(hw); 7550 } 7551 } 7552 7553 STATIC int32_t 7554 em_id_led_init(struct em_hw *hw) 7555 { 7556 uint32_t ledctl; 7557 const uint32_t ledctl_mask = 0x000000FF; 7558 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7559 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7560 uint16_t eeprom_data, i, temp; 7561 const uint16_t led_mask = 0x0F; 7562 DEBUGFUNC("em_id_led_init"); 7563 7564 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7565 /* Nothing to do */ 7566 return E1000_SUCCESS; 7567 } 7568 ledctl = E1000_READ_REG(hw, LEDCTL); 7569 hw->ledctl_default = ledctl; 7570 hw->ledctl_mode1 = hw->ledctl_default; 7571 hw->ledctl_mode2 = hw->ledctl_default; 7572 7573 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7574 DEBUGOUT("EEPROM Read Error\n"); 7575 return -E1000_ERR_EEPROM; 7576 } 7577 if ((hw->mac_type == em_82573) && 7578 (eeprom_data == ID_LED_RESERVED_82573)) 7579 eeprom_data = ID_LED_DEFAULT_82573; 7580 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7581 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7582 if (hw->mac_type == em_ich8lan || 7583 hw->mac_type == em_ich9lan || 7584 hw->mac_type == em_ich10lan) // XXX 7585 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7586 else 7587 eeprom_data = ID_LED_DEFAULT; 7588 } 7589 for (i = 0; i < 4; i++) { 7590 temp = (eeprom_data >> (i << 2)) & led_mask; 7591 switch (temp) { 7592 case ID_LED_ON1_DEF2: 7593 case ID_LED_ON1_ON2: 7594 case ID_LED_ON1_OFF2: 7595 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7596 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7597 break; 7598 case ID_LED_OFF1_DEF2: 7599 case ID_LED_OFF1_ON2: 7600 case ID_LED_OFF1_OFF2: 7601 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7602 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7603 break; 7604 default: 7605 /* Do nothing */ 7606 break; 7607 } 7608 switch (temp) { 7609 case ID_LED_DEF1_ON2: 7610 case ID_LED_ON1_ON2: 7611 case ID_LED_OFF1_ON2: 7612 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7613 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7614 break; 7615 case ID_LED_DEF1_OFF2: 7616 case ID_LED_ON1_OFF2: 7617 case ID_LED_OFF1_OFF2: 7618 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7619 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7620 break; 7621 default: 7622 /* Do nothing */ 7623 break; 7624 } 7625 } 7626 return E1000_SUCCESS; 7627 } 7628 7629 /****************************************************************************** 7630 * Clears all hardware statistics counters. 7631 * 7632 * hw - Struct containing variables accessed by shared code 7633 *****************************************************************************/ 7634 void 7635 em_clear_hw_cntrs(struct em_hw *hw) 7636 { 7637 volatile uint32_t temp; 7638 temp = E1000_READ_REG(hw, CRCERRS); 7639 temp = E1000_READ_REG(hw, SYMERRS); 7640 temp = E1000_READ_REG(hw, MPC); 7641 temp = E1000_READ_REG(hw, SCC); 7642 temp = E1000_READ_REG(hw, ECOL); 7643 temp = E1000_READ_REG(hw, MCC); 7644 temp = E1000_READ_REG(hw, LATECOL); 7645 temp = E1000_READ_REG(hw, COLC); 7646 temp = E1000_READ_REG(hw, DC); 7647 temp = E1000_READ_REG(hw, SEC); 7648 temp = E1000_READ_REG(hw, RLEC); 7649 temp = E1000_READ_REG(hw, XONRXC); 7650 temp = E1000_READ_REG(hw, XONTXC); 7651 temp = E1000_READ_REG(hw, XOFFRXC); 7652 temp = E1000_READ_REG(hw, XOFFTXC); 7653 temp = E1000_READ_REG(hw, FCRUC); 7654 7655 if (!IS_ICH8(hw->mac_type)) { 7656 temp = E1000_READ_REG(hw, PRC64); 7657 temp = E1000_READ_REG(hw, PRC127); 7658 temp = E1000_READ_REG(hw, PRC255); 7659 temp = E1000_READ_REG(hw, PRC511); 7660 temp = E1000_READ_REG(hw, PRC1023); 7661 temp = E1000_READ_REG(hw, PRC1522); 7662 } 7663 temp = E1000_READ_REG(hw, GPRC); 7664 temp = E1000_READ_REG(hw, BPRC); 7665 temp = E1000_READ_REG(hw, MPRC); 7666 temp = E1000_READ_REG(hw, GPTC); 7667 temp = E1000_READ_REG(hw, GORCL); 7668 temp = E1000_READ_REG(hw, GORCH); 7669 temp = E1000_READ_REG(hw, GOTCL); 7670 temp = E1000_READ_REG(hw, GOTCH); 7671 temp = E1000_READ_REG(hw, RNBC); 7672 temp = E1000_READ_REG(hw, RUC); 7673 temp = E1000_READ_REG(hw, RFC); 7674 temp = E1000_READ_REG(hw, ROC); 7675 temp = E1000_READ_REG(hw, RJC); 7676 temp = E1000_READ_REG(hw, TORL); 7677 temp = E1000_READ_REG(hw, TORH); 7678 temp = E1000_READ_REG(hw, TOTL); 7679 temp = E1000_READ_REG(hw, TOTH); 7680 temp = E1000_READ_REG(hw, TPR); 7681 temp = E1000_READ_REG(hw, TPT); 7682 7683 if (!IS_ICH8(hw->mac_type)) { 7684 temp = E1000_READ_REG(hw, PTC64); 7685 temp = E1000_READ_REG(hw, PTC127); 7686 temp = E1000_READ_REG(hw, PTC255); 7687 temp = E1000_READ_REG(hw, PTC511); 7688 temp = E1000_READ_REG(hw, PTC1023); 7689 temp = E1000_READ_REG(hw, PTC1522); 7690 } 7691 temp = E1000_READ_REG(hw, MPTC); 7692 temp = E1000_READ_REG(hw, BPTC); 7693 7694 if (hw->mac_type < em_82543) 7695 return; 7696 7697 temp = E1000_READ_REG(hw, ALGNERRC); 7698 temp = E1000_READ_REG(hw, RXERRC); 7699 temp = E1000_READ_REG(hw, TNCRS); 7700 temp = E1000_READ_REG(hw, CEXTERR); 7701 temp = E1000_READ_REG(hw, TSCTC); 7702 temp = E1000_READ_REG(hw, TSCTFC); 7703 7704 if (hw->mac_type <= em_82544 7705 || hw->mac_type == em_icp_xxxx) 7706 return; 7707 7708 temp = E1000_READ_REG(hw, MGTPRC); 7709 temp = E1000_READ_REG(hw, MGTPDC); 7710 temp = E1000_READ_REG(hw, MGTPTC); 7711 7712 if (hw->mac_type <= em_82547_rev_2) 7713 return; 7714 7715 temp = E1000_READ_REG(hw, IAC); 7716 temp = E1000_READ_REG(hw, ICRXOC); 7717 7718 if (hw->phy_type == em_phy_82577 || 7719 hw->phy_type == em_phy_82578 || 7720 hw->phy_type == em_phy_82579 || 7721 hw->phy_type == em_phy_i217) { 7722 uint16_t phy_data; 7723 7724 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 7725 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 7726 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 7727 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 7728 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 7729 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 7730 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 7731 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 7732 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 7733 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 7734 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 7735 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 7736 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 7737 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 7738 } 7739 7740 if (hw->mac_type == em_ich8lan || 7741 hw->mac_type == em_ich9lan || 7742 hw->mac_type == em_ich10lan || 7743 hw->mac_type == em_pchlan || 7744 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt && hw->mac_type != em_pch_spt)) 7745 return; 7746 7747 temp = E1000_READ_REG(hw, ICRXPTC); 7748 temp = E1000_READ_REG(hw, ICRXATC); 7749 temp = E1000_READ_REG(hw, ICTXPTC); 7750 temp = E1000_READ_REG(hw, ICTXATC); 7751 temp = E1000_READ_REG(hw, ICTXQEC); 7752 temp = E1000_READ_REG(hw, ICTXQMTC); 7753 temp = E1000_READ_REG(hw, ICRXDMTC); 7754 } 7755 7756 #ifndef SMALL_KERNEL 7757 /****************************************************************************** 7758 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 7759 * 7760 * hw - Struct containing variables accessed by shared code 7761 * frame_len - The length of the frame in question 7762 * mac_addr - The Ethernet destination address of the frame in question 7763 *****************************************************************************/ 7764 void 7765 em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, 7766 uint32_t frame_len, uint8_t *mac_addr) 7767 { 7768 uint64_t carry_bit; 7769 /* First adjust the frame length. */ 7770 frame_len--; 7771 /* 7772 * We need to adjust the statistics counters, since the hardware 7773 * counters overcount this packet as a CRC error and undercount the 7774 * packet as a good packet 7775 */ 7776 /* This packet should not be counted as a CRC error. */ 7777 stats->crcerrs--; 7778 /* This packet does count as a Good Packet Received. */ 7779 stats->gprc++; 7780 7781 /* Adjust the Good Octets received counters */ 7782 carry_bit = 0x80000000 & stats->gorcl; 7783 stats->gorcl += frame_len; 7784 /* 7785 * If the high bit of Gorcl (the low 32 bits of the Good Octets 7786 * Received Count) was one before the addition, AND it is zero after, 7787 * then we lost the carry out, need to add one to Gorch (Good Octets 7788 * Received Count High). This could be simplified if all environments 7789 * supported 64-bit integers. 7790 */ 7791 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 7792 stats->gorch++; 7793 /* 7794 * Is this a broadcast or multicast? Check broadcast first, since 7795 * the test for a multicast frame will test positive on a broadcast 7796 * frame. 7797 */ 7798 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 7799 /* Broadcast packet */ 7800 stats->bprc++; 7801 else if (*mac_addr & 0x01) 7802 /* Multicast packet */ 7803 stats->mprc++; 7804 7805 if (frame_len == hw->max_frame_size) { 7806 /* 7807 * In this case, the hardware has overcounted the number of 7808 * oversize frames. 7809 */ 7810 if (stats->roc > 0) 7811 stats->roc--; 7812 } 7813 /* 7814 * Adjust the bin counters when the extra byte put the frame in the 7815 * wrong bin. Remember that the frame_len was adjusted above. 7816 */ 7817 if (frame_len == 64) { 7818 stats->prc64++; 7819 stats->prc127--; 7820 } else if (frame_len == 127) { 7821 stats->prc127++; 7822 stats->prc255--; 7823 } else if (frame_len == 255) { 7824 stats->prc255++; 7825 stats->prc511--; 7826 } else if (frame_len == 511) { 7827 stats->prc511++; 7828 stats->prc1023--; 7829 } else if (frame_len == 1023) { 7830 stats->prc1023++; 7831 stats->prc1522--; 7832 } else if (frame_len == 1522) { 7833 stats->prc1522++; 7834 } 7835 } 7836 #endif /* !SMALL_KERNEL */ 7837 7838 /****************************************************************************** 7839 * Gets the current PCI bus type, speed, and width of the hardware 7840 * 7841 * hw - Struct containing variables accessed by shared code 7842 *****************************************************************************/ 7843 void 7844 em_get_bus_info(struct em_hw *hw) 7845 { 7846 int32_t ret_val; 7847 uint16_t pci_ex_link_status; 7848 uint32_t status; 7849 switch (hw->mac_type) { 7850 case em_82542_rev2_0: 7851 case em_82542_rev2_1: 7852 hw->bus_type = em_bus_type_unknown; 7853 hw->bus_speed = em_bus_speed_unknown; 7854 hw->bus_width = em_bus_width_unknown; 7855 break; 7856 case em_icp_xxxx: 7857 hw->bus_type = em_bus_type_cpp; 7858 hw->bus_speed = em_bus_speed_unknown; 7859 hw->bus_width = em_bus_width_unknown; 7860 break; 7861 case em_82571: 7862 case em_82572: 7863 case em_82573: 7864 case em_82574: 7865 case em_82575: 7866 case em_82580: 7867 case em_80003es2lan: 7868 case em_i210: 7869 case em_i350: 7870 hw->bus_type = em_bus_type_pci_express; 7871 hw->bus_speed = em_bus_speed_2500; 7872 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 7873 &pci_ex_link_status); 7874 if (ret_val) 7875 hw->bus_width = em_bus_width_unknown; 7876 else 7877 hw->bus_width = (pci_ex_link_status & 7878 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 7879 break; 7880 case em_ich8lan: 7881 case em_ich9lan: 7882 case em_ich10lan: 7883 case em_pchlan: 7884 case em_pch2lan: 7885 case em_pch_lpt: 7886 case em_pch_spt: 7887 hw->bus_type = em_bus_type_pci_express; 7888 hw->bus_speed = em_bus_speed_2500; 7889 hw->bus_width = em_bus_width_pciex_1; 7890 break; 7891 default: 7892 status = E1000_READ_REG(hw, STATUS); 7893 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 7894 em_bus_type_pcix : em_bus_type_pci; 7895 7896 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 7897 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 7898 em_bus_speed_66 : em_bus_speed_120; 7899 } else if (hw->bus_type == em_bus_type_pci) { 7900 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 7901 em_bus_speed_66 : em_bus_speed_33; 7902 } else { 7903 switch (status & E1000_STATUS_PCIX_SPEED) { 7904 case E1000_STATUS_PCIX_SPEED_66: 7905 hw->bus_speed = em_bus_speed_66; 7906 break; 7907 case E1000_STATUS_PCIX_SPEED_100: 7908 hw->bus_speed = em_bus_speed_100; 7909 break; 7910 case E1000_STATUS_PCIX_SPEED_133: 7911 hw->bus_speed = em_bus_speed_133; 7912 break; 7913 default: 7914 hw->bus_speed = em_bus_speed_reserved; 7915 break; 7916 } 7917 } 7918 hw->bus_width = (status & E1000_STATUS_BUS64) ? 7919 em_bus_width_64 : em_bus_width_32; 7920 break; 7921 } 7922 } 7923 7924 /****************************************************************************** 7925 * Writes a value to one of the devices registers using port I/O (as opposed to 7926 * memory mapped I/O). Only 82544 and newer devices support port I/O. 7927 * 7928 * hw - Struct containing variables accessed by shared code 7929 * offset - offset to write to 7930 * value - value to write 7931 *****************************************************************************/ 7932 STATIC void 7933 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 7934 { 7935 unsigned long io_addr = hw->io_base; 7936 unsigned long io_data = hw->io_base + 4; 7937 em_io_write(hw, io_addr, offset); 7938 em_io_write(hw, io_data, value); 7939 } 7940 7941 /****************************************************************************** 7942 * Estimates the cable length. 7943 * 7944 * hw - Struct containing variables accessed by shared code 7945 * min_length - The estimated minimum length 7946 * max_length - The estimated maximum length 7947 * 7948 * returns: - E1000_ERR_XXX 7949 * E1000_SUCCESS 7950 * 7951 * This function always returns a ranged length (minimum & maximum). 7952 * So for M88 phy's, this function interprets the one value returned from the 7953 * register to the minimum and maximum range. 7954 * For IGP phy's, the function calculates the range by the AGC registers. 7955 *****************************************************************************/ 7956 STATIC int32_t 7957 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 7958 uint16_t *max_length) 7959 { 7960 int32_t ret_val; 7961 uint16_t agc_value = 0; 7962 uint16_t i, phy_data; 7963 uint16_t cable_length; 7964 DEBUGFUNC("em_get_cable_length"); 7965 7966 *min_length = *max_length = 0; 7967 7968 /* Use old method for Phy older than IGP */ 7969 if (hw->phy_type == em_phy_m88 || 7970 hw->phy_type == em_phy_oem || 7971 hw->phy_type == em_phy_82578) { 7972 7973 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7974 &phy_data); 7975 if (ret_val) 7976 return ret_val; 7977 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 7978 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 7979 7980 /* Convert the enum value to ranged values */ 7981 switch (cable_length) { 7982 case em_cable_length_50: 7983 *min_length = 0; 7984 *max_length = em_igp_cable_length_50; 7985 break; 7986 case em_cable_length_50_80: 7987 *min_length = em_igp_cable_length_50; 7988 *max_length = em_igp_cable_length_80; 7989 break; 7990 case em_cable_length_80_110: 7991 *min_length = em_igp_cable_length_80; 7992 *max_length = em_igp_cable_length_110; 7993 break; 7994 case em_cable_length_110_140: 7995 *min_length = em_igp_cable_length_110; 7996 *max_length = em_igp_cable_length_140; 7997 break; 7998 case em_cable_length_140: 7999 *min_length = em_igp_cable_length_140; 8000 *max_length = em_igp_cable_length_170; 8001 break; 8002 default: 8003 return -E1000_ERR_PHY; 8004 break; 8005 } 8006 } else if (hw->phy_type == em_phy_rtl8211) { 8007 /* no cable length info on RTL8211, fake */ 8008 *min_length = 0; 8009 *max_length = em_igp_cable_length_50; 8010 } else if (hw->phy_type == em_phy_gg82563) { 8011 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 8012 &phy_data); 8013 if (ret_val) 8014 return ret_val; 8015 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 8016 8017 switch (cable_length) { 8018 case em_gg_cable_length_60: 8019 *min_length = 0; 8020 *max_length = em_igp_cable_length_60; 8021 break; 8022 case em_gg_cable_length_60_115: 8023 *min_length = em_igp_cable_length_60; 8024 *max_length = em_igp_cable_length_115; 8025 break; 8026 case em_gg_cable_length_115_150: 8027 *min_length = em_igp_cable_length_115; 8028 *max_length = em_igp_cable_length_150; 8029 break; 8030 case em_gg_cable_length_150: 8031 *min_length = em_igp_cable_length_150; 8032 *max_length = em_igp_cable_length_180; 8033 break; 8034 default: 8035 return -E1000_ERR_PHY; 8036 break; 8037 } 8038 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 8039 uint16_t cur_agc_value; 8040 uint16_t min_agc_value = 8041 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 8042 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8043 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 8044 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 8045 8046 /* Read the AGC registers for all channels */ 8047 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8048 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8049 &phy_data); 8050 if (ret_val) 8051 return ret_val; 8052 8053 cur_agc_value = phy_data >> 8054 IGP01E1000_AGC_LENGTH_SHIFT; 8055 8056 /* Value bound check. */ 8057 if ((cur_agc_value >= 8058 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 8059 (cur_agc_value == 0)) 8060 return -E1000_ERR_PHY; 8061 8062 agc_value += cur_agc_value; 8063 8064 /* Update minimal AGC value. */ 8065 if (min_agc_value > cur_agc_value) 8066 min_agc_value = cur_agc_value; 8067 } 8068 8069 /* Remove the minimal AGC result for length < 50m */ 8070 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 8071 em_igp_cable_length_50) { 8072 agc_value -= min_agc_value; 8073 8074 /* 8075 * Get the average length of the remaining 3 channels 8076 */ 8077 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 8078 } else { 8079 /* Get the average length of all the 4 channels. */ 8080 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 8081 } 8082 8083 /* Set the range of the calculated length. */ 8084 *min_length = ((em_igp_cable_length_table[agc_value] - 8085 IGP01E1000_AGC_RANGE) > 0) ? 8086 (em_igp_cable_length_table[agc_value] - 8087 IGP01E1000_AGC_RANGE) : 0; 8088 *max_length = em_igp_cable_length_table[agc_value] + 8089 IGP01E1000_AGC_RANGE; 8090 } else if (hw->phy_type == em_phy_igp_2 || 8091 hw->phy_type == em_phy_igp_3) { 8092 uint16_t cur_agc_index, max_agc_index = 0; 8093 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 8094 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 8095 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 8096 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 8097 /* Read the AGC registers for all channels */ 8098 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 8099 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 8100 &phy_data); 8101 if (ret_val) 8102 return ret_val; 8103 /* 8104 * Getting bits 15:9, which represent the combination 8105 * of course and fine gain values. The result is a 8106 * number that can be put into the lookup table to 8107 * obtain the approximate cable length. 8108 */ 8109 cur_agc_index = (phy_data >> 8110 IGP02E1000_AGC_LENGTH_SHIFT) & 8111 IGP02E1000_AGC_LENGTH_MASK; 8112 8113 /* Array index bound check. */ 8114 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 8115 || (cur_agc_index == 0)) 8116 return -E1000_ERR_PHY; 8117 8118 /* Remove min & max AGC values from calculation. */ 8119 if (em_igp_2_cable_length_table[min_agc_index] > 8120 em_igp_2_cable_length_table[cur_agc_index]) 8121 min_agc_index = cur_agc_index; 8122 if (em_igp_2_cable_length_table[max_agc_index] < 8123 em_igp_2_cable_length_table[cur_agc_index]) 8124 max_agc_index = cur_agc_index; 8125 8126 agc_value += em_igp_2_cable_length_table 8127 [cur_agc_index]; 8128 } 8129 8130 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 8131 em_igp_2_cable_length_table[max_agc_index]); 8132 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 8133 /* 8134 * Calculate cable length with the error range of +/- 10 8135 * meters. 8136 */ 8137 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 8138 (agc_value - IGP02E1000_AGC_RANGE) : 0; 8139 *max_length = agc_value + IGP02E1000_AGC_RANGE; 8140 } 8141 return E1000_SUCCESS; 8142 } 8143 8144 /****************************************************************************** 8145 * Check if Downshift occured 8146 * 8147 * hw - Struct containing variables accessed by shared code 8148 * downshift - output parameter : 0 - No Downshift ocured. 8149 * 1 - Downshift ocured. 8150 * 8151 * returns: - E1000_ERR_XXX 8152 * E1000_SUCCESS 8153 * 8154 * For phy's older then IGP, this function reads the Downshift bit in the Phy 8155 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 8156 * Link Health register. In IGP this bit is latched high, so the driver must 8157 * read it immediately after link is established. 8158 *****************************************************************************/ 8159 STATIC int32_t 8160 em_check_downshift(struct em_hw *hw) 8161 { 8162 int32_t ret_val; 8163 uint16_t phy_data; 8164 DEBUGFUNC("em_check_downshift"); 8165 8166 if (hw->phy_type == em_phy_igp || 8167 hw->phy_type == em_phy_igp_3 || 8168 hw->phy_type == em_phy_igp_2) { 8169 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 8170 &phy_data); 8171 if (ret_val) 8172 return ret_val; 8173 8174 hw->speed_downgraded = (phy_data & 8175 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 8176 } else if ((hw->phy_type == em_phy_m88) || 8177 (hw->phy_type == em_phy_gg82563) || 8178 (hw->phy_type == em_phy_oem) || 8179 (hw->phy_type == em_phy_82578)) { 8180 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 8181 &phy_data); 8182 if (ret_val) 8183 return ret_val; 8184 8185 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 8186 M88E1000_PSSR_DOWNSHIFT_SHIFT; 8187 } else if (hw->phy_type == em_phy_ife) { 8188 /* em_phy_ife supports 10/100 speed only */ 8189 hw->speed_downgraded = FALSE; 8190 } 8191 return E1000_SUCCESS; 8192 } 8193 8194 /***************************************************************************** 8195 * 8196 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 8197 * gigabit link is achieved to improve link quality. 8198 * 8199 * hw: Struct containing variables accessed by shared code 8200 * 8201 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8202 * E1000_SUCCESS at any other case. 8203 * 8204 ****************************************************************************/ 8205 STATIC int32_t 8206 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 8207 { 8208 int32_t ret_val; 8209 uint16_t phy_data, phy_saved_data, speed, duplex, i; 8210 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 8211 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 8212 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 8213 uint16_t min_length, max_length; 8214 DEBUGFUNC("em_config_dsp_after_link_change"); 8215 8216 if (hw->phy_type != em_phy_igp) 8217 return E1000_SUCCESS; 8218 8219 if (link_up) { 8220 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 8221 if (ret_val) { 8222 DEBUGOUT("Error getting link speed and duplex\n"); 8223 return ret_val; 8224 } 8225 if (speed == SPEED_1000) { 8226 8227 ret_val = em_get_cable_length(hw, &min_length, &max_length); 8228 if (ret_val) 8229 return ret_val; 8230 8231 if ((hw->dsp_config_state == em_dsp_config_enabled) && 8232 min_length >= em_igp_cable_length_50) { 8233 8234 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 8235 i++) { 8236 ret_val = em_read_phy_reg(hw, 8237 dsp_reg_array[i], &phy_data); 8238 if (ret_val) 8239 return ret_val; 8240 8241 phy_data &= 8242 ~IGP01E1000_PHY_EDAC_MU_INDEX; 8243 8244 ret_val = em_write_phy_reg(hw, 8245 dsp_reg_array[i], phy_data); 8246 if (ret_val) 8247 return ret_val; 8248 } 8249 hw->dsp_config_state = em_dsp_config_activated; 8250 } 8251 if ((hw->ffe_config_state == em_ffe_config_enabled) && 8252 (min_length < em_igp_cable_length_50)) { 8253 8254 uint16_t ffe_idle_err_timeout = 8255 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 8256 uint32_t idle_errs = 0; 8257 /* clear previous idle error counts */ 8258 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 8259 &phy_data); 8260 if (ret_val) 8261 return ret_val; 8262 8263 for (i = 0; i < ffe_idle_err_timeout; i++) { 8264 usec_delay(1000); 8265 ret_val = em_read_phy_reg(hw, 8266 PHY_1000T_STATUS, &phy_data); 8267 if (ret_val) 8268 return ret_val; 8269 8270 idle_errs += (phy_data & 8271 SR_1000T_IDLE_ERROR_CNT); 8272 if (idle_errs > 8273 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 8274 hw->ffe_config_state = 8275 em_ffe_config_active; 8276 8277 ret_val = em_write_phy_reg(hw, 8278 IGP01E1000_PHY_DSP_FFE, 8279 IGP01E1000_PHY_DSP_FFE_CM_CP); 8280 if (ret_val) 8281 return ret_val; 8282 break; 8283 } 8284 if (idle_errs) 8285 ffe_idle_err_timeout = 8286 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 8287 } 8288 } 8289 } 8290 } else { 8291 if (hw->dsp_config_state == em_dsp_config_activated) { 8292 /* 8293 * Save off the current value of register 0x2F5B to 8294 * be restored at the end of the routines. 8295 */ 8296 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8297 8298 if (ret_val) 8299 return ret_val; 8300 8301 /* Disable the PHY transmitter */ 8302 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8303 8304 if (ret_val) 8305 return ret_val; 8306 8307 msec_delay_irq(20); 8308 8309 ret_val = em_write_phy_reg(hw, 0x0000, 8310 IGP01E1000_IEEE_FORCE_GIGA); 8311 if (ret_val) 8312 return ret_val; 8313 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 8314 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 8315 &phy_data); 8316 if (ret_val) 8317 return ret_val; 8318 8319 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 8320 phy_data |= 8321 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 8322 8323 ret_val = em_write_phy_reg(hw, 8324 dsp_reg_array[i], phy_data); 8325 if (ret_val) 8326 return ret_val; 8327 } 8328 8329 ret_val = em_write_phy_reg(hw, 0x0000, 8330 IGP01E1000_IEEE_RESTART_AUTONEG); 8331 if (ret_val) 8332 return ret_val; 8333 8334 msec_delay_irq(20); 8335 8336 /* Now enable the transmitter */ 8337 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8338 8339 if (ret_val) 8340 return ret_val; 8341 8342 hw->dsp_config_state = em_dsp_config_enabled; 8343 } 8344 if (hw->ffe_config_state == em_ffe_config_active) { 8345 /* 8346 * Save off the current value of register 0x2F5B to 8347 * be restored at the end of the routines. 8348 */ 8349 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8350 8351 if (ret_val) 8352 return ret_val; 8353 8354 /* Disable the PHY transmitter */ 8355 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8356 8357 if (ret_val) 8358 return ret_val; 8359 8360 msec_delay_irq(20); 8361 8362 ret_val = em_write_phy_reg(hw, 0x0000, 8363 IGP01E1000_IEEE_FORCE_GIGA); 8364 if (ret_val) 8365 return ret_val; 8366 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 8367 IGP01E1000_PHY_DSP_FFE_DEFAULT); 8368 if (ret_val) 8369 return ret_val; 8370 8371 ret_val = em_write_phy_reg(hw, 0x0000, 8372 IGP01E1000_IEEE_RESTART_AUTONEG); 8373 if (ret_val) 8374 return ret_val; 8375 8376 msec_delay_irq(20); 8377 8378 /* Now enable the transmitter */ 8379 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8380 8381 if (ret_val) 8382 return ret_val; 8383 8384 hw->ffe_config_state = em_ffe_config_enabled; 8385 } 8386 } 8387 return E1000_SUCCESS; 8388 } 8389 8390 /***************************************************************************** 8391 * Set PHY to class A mode 8392 * Assumes the following operations will follow to enable the new class mode. 8393 * 1. Do a PHY soft reset 8394 * 2. Restart auto-negotiation or force link. 8395 * 8396 * hw - Struct containing variables accessed by shared code 8397 ****************************************************************************/ 8398 static int32_t 8399 em_set_phy_mode(struct em_hw *hw) 8400 { 8401 int32_t ret_val; 8402 uint16_t eeprom_data; 8403 DEBUGFUNC("em_set_phy_mode"); 8404 8405 if ((hw->mac_type == em_82545_rev_3) && 8406 (hw->media_type == em_media_type_copper)) { 8407 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8408 &eeprom_data); 8409 if (ret_val) { 8410 return ret_val; 8411 } 8412 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8413 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8414 ret_val = em_write_phy_reg(hw, 8415 M88E1000_PHY_PAGE_SELECT, 0x000B); 8416 if (ret_val) 8417 return ret_val; 8418 ret_val = em_write_phy_reg(hw, 8419 M88E1000_PHY_GEN_CONTROL, 0x8104); 8420 if (ret_val) 8421 return ret_val; 8422 8423 hw->phy_reset_disable = FALSE; 8424 } 8425 } 8426 return E1000_SUCCESS; 8427 } 8428 8429 /***************************************************************************** 8430 * 8431 * This function sets the lplu state according to the active flag. When 8432 * activating lplu this function also disables smart speed and vise versa. 8433 * lplu will not be activated unless the device autonegotiation advertisement 8434 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8435 * hw: Struct containing variables accessed by shared code 8436 * active - true to enable lplu false to disable lplu. 8437 * 8438 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8439 * E1000_SUCCESS at any other case. 8440 * 8441 ****************************************************************************/ 8442 STATIC int32_t 8443 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8444 { 8445 uint32_t phy_ctrl = 0; 8446 int32_t ret_val; 8447 uint16_t phy_data; 8448 DEBUGFUNC("em_set_d3_lplu_state"); 8449 8450 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8451 && hw->phy_type != em_phy_igp_3) 8452 return E1000_SUCCESS; 8453 /* 8454 * During driver activity LPLU should not be used or it will attain 8455 * link from the lowest speeds starting from 10Mbps. The capability 8456 * is used for Dx transitions and states 8457 */ 8458 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8459 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8460 if (ret_val) 8461 return ret_val; 8462 } else if (IS_ICH8(hw->mac_type)) { 8463 /* 8464 * MAC writes into PHY register based on the state transition 8465 * and start auto-negotiation. SW driver can overwrite the 8466 * settings in CSR PHY power control E1000_PHY_CTRL register. 8467 */ 8468 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8469 } else { 8470 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8471 &phy_data); 8472 if (ret_val) 8473 return ret_val; 8474 } 8475 8476 if (!active) { 8477 if (hw->mac_type == em_82541_rev_2 || 8478 hw->mac_type == em_82547_rev_2) { 8479 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8480 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8481 phy_data); 8482 if (ret_val) 8483 return ret_val; 8484 } else { 8485 if (IS_ICH8(hw->mac_type)) { 8486 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8487 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8488 } else { 8489 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8490 ret_val = em_write_phy_reg(hw, 8491 IGP02E1000_PHY_POWER_MGMT, phy_data); 8492 if (ret_val) 8493 return ret_val; 8494 } 8495 } 8496 /* 8497 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8498 * during Dx states where the power conservation is most 8499 * important. During driver activity we should enable 8500 * SmartSpeed, so performance is maintained. 8501 */ 8502 if (hw->smart_speed == em_smart_speed_on) { 8503 ret_val = em_read_phy_reg(hw, 8504 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8505 if (ret_val) 8506 return ret_val; 8507 8508 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8509 ret_val = em_write_phy_reg(hw, 8510 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8511 if (ret_val) 8512 return ret_val; 8513 } else if (hw->smart_speed == em_smart_speed_off) { 8514 ret_val = em_read_phy_reg(hw, 8515 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8516 if (ret_val) 8517 return ret_val; 8518 8519 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8520 ret_val = em_write_phy_reg(hw, 8521 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8522 if (ret_val) 8523 return ret_val; 8524 } 8525 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8526 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8527 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8528 8529 if (hw->mac_type == em_82541_rev_2 || 8530 hw->mac_type == em_82547_rev_2) { 8531 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8532 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8533 phy_data); 8534 if (ret_val) 8535 return ret_val; 8536 } else { 8537 if (IS_ICH8(hw->mac_type)) { 8538 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8539 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8540 } else { 8541 phy_data |= IGP02E1000_PM_D3_LPLU; 8542 ret_val = em_write_phy_reg(hw, 8543 IGP02E1000_PHY_POWER_MGMT, phy_data); 8544 if (ret_val) 8545 return ret_val; 8546 } 8547 } 8548 8549 /* When LPLU is enabled we should disable SmartSpeed */ 8550 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8551 &phy_data); 8552 if (ret_val) 8553 return ret_val; 8554 8555 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8556 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8557 phy_data); 8558 if (ret_val) 8559 return ret_val; 8560 8561 } 8562 return E1000_SUCCESS; 8563 } 8564 8565 /***************************************************************************** 8566 * 8567 * This function sets the lplu d0 state according to the active flag. When 8568 * activating lplu this function also disables smart speed and vise versa. 8569 * lplu will not be activated unless the device autonegotiation advertisement 8570 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8571 * hw: Struct containing variables accessed by shared code 8572 * active - true to enable lplu false to disable lplu. 8573 * 8574 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8575 * E1000_SUCCESS at any other case. 8576 * 8577 ****************************************************************************/ 8578 STATIC int32_t 8579 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8580 { 8581 uint32_t phy_ctrl = 0; 8582 int32_t ret_val; 8583 uint16_t phy_data; 8584 DEBUGFUNC("em_set_d0_lplu_state"); 8585 8586 if (hw->mac_type <= em_82547_rev_2) 8587 return E1000_SUCCESS; 8588 8589 if (IS_ICH8(hw->mac_type)) { 8590 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8591 } else { 8592 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8593 &phy_data); 8594 if (ret_val) 8595 return ret_val; 8596 } 8597 8598 if (!active) { 8599 if (IS_ICH8(hw->mac_type)) { 8600 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8601 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8602 } else { 8603 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8604 ret_val = em_write_phy_reg(hw, 8605 IGP02E1000_PHY_POWER_MGMT, phy_data); 8606 if (ret_val) 8607 return ret_val; 8608 } 8609 /* 8610 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8611 * during Dx states where the power conservation is most 8612 * important. During driver activity we should enable 8613 * SmartSpeed, so performance is maintained. 8614 */ 8615 if (hw->smart_speed == em_smart_speed_on) { 8616 ret_val = em_read_phy_reg(hw, 8617 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8618 if (ret_val) 8619 return ret_val; 8620 8621 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8622 ret_val = em_write_phy_reg(hw, 8623 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8624 if (ret_val) 8625 return ret_val; 8626 } else if (hw->smart_speed == em_smart_speed_off) { 8627 ret_val = em_read_phy_reg(hw, 8628 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8629 if (ret_val) 8630 return ret_val; 8631 8632 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8633 ret_val = em_write_phy_reg(hw, 8634 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8635 if (ret_val) 8636 return ret_val; 8637 } 8638 } else { 8639 if (IS_ICH8(hw->mac_type)) { 8640 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8641 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8642 } else { 8643 phy_data |= IGP02E1000_PM_D0_LPLU; 8644 ret_val = em_write_phy_reg(hw, 8645 IGP02E1000_PHY_POWER_MGMT, phy_data); 8646 if (ret_val) 8647 return ret_val; 8648 } 8649 8650 /* When LPLU is enabled we should disable SmartSpeed */ 8651 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8652 &phy_data); 8653 if (ret_val) 8654 return ret_val; 8655 8656 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8657 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8658 phy_data); 8659 if (ret_val) 8660 return ret_val; 8661 8662 } 8663 return E1000_SUCCESS; 8664 } 8665 8666 /*************************************************************************** 8667 * Set Low Power Link Up state 8668 * 8669 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8670 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8671 * the phy speed. This function will manually set the LPLU bit and restart 8672 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8673 * since it configures the same bit. 8674 ***************************************************************************/ 8675 int32_t 8676 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8677 { 8678 int32_t ret_val = E1000_SUCCESS; 8679 uint16_t oem_reg; 8680 8681 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8682 8683 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8684 if (ret_val) 8685 goto out; 8686 8687 if (active) 8688 oem_reg |= HV_OEM_BITS_LPLU; 8689 else 8690 oem_reg &= ~HV_OEM_BITS_LPLU; 8691 8692 oem_reg |= HV_OEM_BITS_RESTART_AN; 8693 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8694 8695 out: 8696 return ret_val; 8697 } 8698 8699 /****************************************************************************** 8700 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8701 * 8702 * hw - Struct containing variables accessed by shared code 8703 *****************************************************************************/ 8704 static int32_t 8705 em_set_vco_speed(struct em_hw *hw) 8706 { 8707 int32_t ret_val; 8708 uint16_t default_page = 0; 8709 uint16_t phy_data; 8710 DEBUGFUNC("em_set_vco_speed"); 8711 8712 switch (hw->mac_type) { 8713 case em_82545_rev_3: 8714 case em_82546_rev_3: 8715 break; 8716 default: 8717 return E1000_SUCCESS; 8718 } 8719 8720 /* Set PHY register 30, page 5, bit 8 to 0 */ 8721 8722 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8723 if (ret_val) 8724 return ret_val; 8725 8726 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8727 if (ret_val) 8728 return ret_val; 8729 8730 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8731 if (ret_val) 8732 return ret_val; 8733 8734 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8735 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8736 if (ret_val) 8737 return ret_val; 8738 8739 /* Set PHY register 30, page 4, bit 11 to 1 */ 8740 8741 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8742 if (ret_val) 8743 return ret_val; 8744 8745 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8746 if (ret_val) 8747 return ret_val; 8748 8749 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 8750 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8751 if (ret_val) 8752 return ret_val; 8753 8754 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 8755 if (ret_val) 8756 return ret_val; 8757 8758 return E1000_SUCCESS; 8759 } 8760 8761 /***************************************************************************** 8762 * This function reads the cookie from ARC ram. 8763 * 8764 * returns: - E1000_SUCCESS . 8765 ****************************************************************************/ 8766 STATIC int32_t 8767 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 8768 { 8769 uint8_t i; 8770 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 8771 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 8772 length = (length >> 2); 8773 offset = (offset >> 2); 8774 8775 for (i = 0; i < length; i++) { 8776 *((uint32_t *) buffer + i) = 8777 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 8778 } 8779 return E1000_SUCCESS; 8780 } 8781 8782 /***************************************************************************** 8783 * This function checks whether the HOST IF is enabled for command operaton 8784 * and also checks whether the previous command is completed. 8785 * It busy waits in case of previous command is not completed. 8786 * 8787 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 8788 * timeout 8789 * - E1000_SUCCESS for success. 8790 ****************************************************************************/ 8791 STATIC int32_t 8792 em_mng_enable_host_if(struct em_hw *hw) 8793 { 8794 uint32_t hicr; 8795 uint8_t i; 8796 /* Check that the host interface is enabled. */ 8797 hicr = E1000_READ_REG(hw, HICR); 8798 if ((hicr & E1000_HICR_EN) == 0) { 8799 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 8800 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8801 } 8802 /* check the previous command is completed */ 8803 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 8804 hicr = E1000_READ_REG(hw, HICR); 8805 if (!(hicr & E1000_HICR_C)) 8806 break; 8807 msec_delay_irq(1); 8808 } 8809 8810 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 8811 DEBUGOUT("Previous command timeout failed .\n"); 8812 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8813 } 8814 return E1000_SUCCESS; 8815 } 8816 8817 /***************************************************************************** 8818 * This function checks the mode of the firmware. 8819 * 8820 * returns - TRUE when the mode is IAMT or FALSE. 8821 ****************************************************************************/ 8822 boolean_t 8823 em_check_mng_mode(struct em_hw *hw) 8824 { 8825 uint32_t fwsm; 8826 fwsm = E1000_READ_REG(hw, FWSM); 8827 8828 if (IS_ICH8(hw->mac_type)) { 8829 if ((fwsm & E1000_FWSM_MODE_MASK) == 8830 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8831 return TRUE; 8832 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 8833 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8834 return TRUE; 8835 8836 return FALSE; 8837 } 8838 8839 /***************************************************************************** 8840 * This function calculates the checksum. 8841 * 8842 * returns - checksum of buffer contents. 8843 ****************************************************************************/ 8844 STATIC uint8_t 8845 em_calculate_mng_checksum(char *buffer, uint32_t length) 8846 { 8847 uint8_t sum = 0; 8848 uint32_t i; 8849 if (!buffer) 8850 return 0; 8851 8852 for (i = 0; i < length; i++) 8853 sum += buffer[i]; 8854 8855 return (uint8_t) (0 - sum); 8856 } 8857 8858 /***************************************************************************** 8859 * This function checks whether tx pkt filtering needs to be enabled or not. 8860 * 8861 * returns - TRUE for packet filtering or FALSE. 8862 ****************************************************************************/ 8863 boolean_t 8864 em_enable_tx_pkt_filtering(struct em_hw *hw) 8865 { 8866 /* called in init as well as watchdog timer functions */ 8867 int32_t ret_val, checksum; 8868 boolean_t tx_filter = FALSE; 8869 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 8870 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 8871 if (em_check_mng_mode(hw)) { 8872 ret_val = em_mng_enable_host_if(hw); 8873 if (ret_val == E1000_SUCCESS) { 8874 ret_val = em_host_if_read_cookie(hw, buffer); 8875 if (ret_val == E1000_SUCCESS) { 8876 checksum = hdr->checksum; 8877 hdr->checksum = 0; 8878 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 8879 checksum == em_calculate_mng_checksum( 8880 (char *) buffer, 8881 E1000_MNG_DHCP_COOKIE_LENGTH)) { 8882 if (hdr->status & 8883 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 8884 tx_filter = TRUE; 8885 } else 8886 tx_filter = TRUE; 8887 } else 8888 tx_filter = TRUE; 8889 } 8890 } 8891 hw->tx_pkt_filtering = tx_filter; 8892 return tx_filter; 8893 } 8894 8895 static int32_t 8896 em_polarity_reversal_workaround(struct em_hw *hw) 8897 { 8898 int32_t ret_val; 8899 uint16_t mii_status_reg; 8900 uint16_t i; 8901 /* Polarity reversal workaround for forced 10F/10H links. */ 8902 8903 /* Disable the transmitter on the PHY */ 8904 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8905 if (ret_val) 8906 return ret_val; 8907 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 8908 if (ret_val) 8909 return ret_val; 8910 8911 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8912 if (ret_val) 8913 return ret_val; 8914 8915 /* This loop will early-out if the NO link condition has been met. */ 8916 for (i = PHY_FORCE_TIME; i > 0; i--) { 8917 /* 8918 * Read the MII Status Register and wait for Link Status bit 8919 * to be clear. 8920 */ 8921 8922 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8923 if (ret_val) 8924 return ret_val; 8925 8926 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8927 if (ret_val) 8928 return ret_val; 8929 8930 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 8931 break; 8932 msec_delay_irq(100); 8933 } 8934 8935 /* Recommended delay time after link has been lost */ 8936 msec_delay_irq(1000); 8937 8938 /* Now we will re-enable the transmitter on the PHY */ 8939 8940 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8941 if (ret_val) 8942 return ret_val; 8943 msec_delay_irq(50); 8944 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 8945 if (ret_val) 8946 return ret_val; 8947 msec_delay_irq(50); 8948 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 8949 if (ret_val) 8950 return ret_val; 8951 msec_delay_irq(50); 8952 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 8953 if (ret_val) 8954 return ret_val; 8955 8956 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8957 if (ret_val) 8958 return ret_val; 8959 8960 /* This loop will early-out if the link condition has been met. */ 8961 for (i = PHY_FORCE_TIME; i > 0; i--) { 8962 /* 8963 * Read the MII Status Register and wait for Link Status bit 8964 * to be set. 8965 */ 8966 8967 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8968 if (ret_val) 8969 return ret_val; 8970 8971 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8972 if (ret_val) 8973 return ret_val; 8974 8975 if (mii_status_reg & MII_SR_LINK_STATUS) 8976 break; 8977 msec_delay_irq(100); 8978 } 8979 return E1000_SUCCESS; 8980 } 8981 8982 /****************************************************************************** 8983 * 8984 * Disables PCI-Express master access. 8985 * 8986 * hw: Struct containing variables accessed by shared code 8987 * 8988 * returns: - none. 8989 * 8990 *****************************************************************************/ 8991 STATIC void 8992 em_set_pci_express_master_disable(struct em_hw *hw) 8993 { 8994 uint32_t ctrl; 8995 DEBUGFUNC("em_set_pci_express_master_disable"); 8996 8997 if (hw->bus_type != em_bus_type_pci_express) 8998 return; 8999 9000 ctrl = E1000_READ_REG(hw, CTRL); 9001 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 9002 E1000_WRITE_REG(hw, CTRL, ctrl); 9003 } 9004 9005 /****************************************************************************** 9006 * 9007 * Disables PCI-Express master access and verifies there are no pending 9008 * requests 9009 * 9010 * hw: Struct containing variables accessed by shared code 9011 * 9012 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 9013 * caused the master requests to be disabled. 9014 * E1000_SUCCESS master requests disabled. 9015 * 9016 ******************************************************************************/ 9017 int32_t 9018 em_disable_pciex_master(struct em_hw *hw) 9019 { 9020 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 9021 DEBUGFUNC("em_disable_pciex_master"); 9022 9023 if (hw->bus_type != em_bus_type_pci_express) 9024 return E1000_SUCCESS; 9025 9026 em_set_pci_express_master_disable(hw); 9027 9028 while (timeout) { 9029 if (!(E1000_READ_REG(hw, STATUS) & 9030 E1000_STATUS_GIO_MASTER_ENABLE)) 9031 break; 9032 else 9033 usec_delay(100); 9034 timeout--; 9035 } 9036 9037 if (!timeout) { 9038 DEBUGOUT("Master requests are pending.\n"); 9039 return -E1000_ERR_MASTER_REQUESTS_PENDING; 9040 } 9041 return E1000_SUCCESS; 9042 } 9043 9044 /****************************************************************************** 9045 * 9046 * Check for EEPROM Auto Read bit done. 9047 * 9048 * hw: Struct containing variables accessed by shared code 9049 * 9050 * returns: - E1000_ERR_RESET if fail to reset MAC 9051 * E1000_SUCCESS at any other case. 9052 * 9053 ******************************************************************************/ 9054 STATIC int32_t 9055 em_get_auto_rd_done(struct em_hw *hw) 9056 { 9057 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 9058 DEBUGFUNC("em_get_auto_rd_done"); 9059 9060 switch (hw->mac_type) { 9061 default: 9062 msec_delay(5); 9063 break; 9064 case em_82571: 9065 case em_82572: 9066 case em_82573: 9067 case em_82574: 9068 case em_82575: 9069 case em_82580: 9070 case em_80003es2lan: 9071 case em_i210: 9072 case em_i350: 9073 case em_ich8lan: 9074 case em_ich9lan: 9075 case em_ich10lan: 9076 case em_pchlan: 9077 case em_pch2lan: 9078 case em_pch_lpt: 9079 case em_pch_spt: 9080 while (timeout) { 9081 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 9082 break; 9083 else 9084 msec_delay(1); 9085 timeout--; 9086 } 9087 9088 if (!timeout) { 9089 DEBUGOUT("Auto read by HW from EEPROM has not" 9090 " completed.\n"); 9091 return -E1000_ERR_RESET; 9092 } 9093 break; 9094 } 9095 /* 9096 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 9097 * high. Need to wait for PHY configuration completion before 9098 * accessing NVM and PHY. 9099 */ 9100 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 9101 msec_delay(25); 9102 9103 return E1000_SUCCESS; 9104 } 9105 9106 /*************************************************************************** 9107 * Checks if the PHY configuration is done 9108 * 9109 * hw: Struct containing variables accessed by shared code 9110 * 9111 * returns: - E1000_ERR_RESET if fail to reset MAC 9112 * E1000_SUCCESS at any other case. 9113 * 9114 ***************************************************************************/ 9115 STATIC int32_t 9116 em_get_phy_cfg_done(struct em_hw *hw) 9117 { 9118 int32_t timeout = PHY_CFG_TIMEOUT; 9119 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 9120 DEBUGFUNC("em_get_phy_cfg_done"); 9121 9122 switch (hw->mac_type) { 9123 default: 9124 msec_delay_irq(10); 9125 break; 9126 case em_80003es2lan: 9127 case em_82575: 9128 case em_82580: 9129 case em_i350: 9130 switch (hw->bus_func) { 9131 case 1: 9132 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 9133 break; 9134 case 2: 9135 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 9136 break; 9137 case 3: 9138 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 9139 break; 9140 } 9141 /* FALLTHROUGH */ 9142 case em_82571: 9143 case em_82572: 9144 while (timeout) { 9145 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 9146 break; 9147 else 9148 msec_delay(1); 9149 timeout--; 9150 } 9151 if (!timeout) { 9152 DEBUGOUT("MNG configuration cycle has not completed." 9153 "\n"); 9154 } 9155 break; 9156 } 9157 9158 return E1000_SUCCESS; 9159 } 9160 9161 /*************************************************************************** 9162 * 9163 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 9164 * adapter or Eeprom access. 9165 * 9166 * hw: Struct containing variables accessed by shared code 9167 * 9168 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 9169 * E1000_SUCCESS at any other case. 9170 * 9171 ***************************************************************************/ 9172 STATIC int32_t 9173 em_get_hw_eeprom_semaphore(struct em_hw *hw) 9174 { 9175 int32_t timeout; 9176 uint32_t swsm; 9177 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 9178 9179 if (!hw->eeprom_semaphore_present) 9180 return E1000_SUCCESS; 9181 9182 if (hw->mac_type == em_80003es2lan) { 9183 /* Get the SW semaphore. */ 9184 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 9185 return -E1000_ERR_EEPROM; 9186 } 9187 /* Get the FW semaphore. */ 9188 timeout = hw->eeprom.word_size + 1; 9189 while (timeout) { 9190 swsm = E1000_READ_REG(hw, SWSM); 9191 swsm |= E1000_SWSM_SWESMBI; 9192 E1000_WRITE_REG(hw, SWSM, swsm); 9193 /* if we managed to set the bit we got the semaphore. */ 9194 swsm = E1000_READ_REG(hw, SWSM); 9195 if (swsm & E1000_SWSM_SWESMBI) 9196 break; 9197 9198 usec_delay(50); 9199 timeout--; 9200 } 9201 9202 if (!timeout) { 9203 /* Release semaphores */ 9204 em_put_hw_eeprom_semaphore(hw); 9205 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 9206 "\n"); 9207 return -E1000_ERR_EEPROM; 9208 } 9209 return E1000_SUCCESS; 9210 } 9211 9212 /*************************************************************************** 9213 * This function clears HW semaphore bits. 9214 * 9215 * hw: Struct containing variables accessed by shared code 9216 * 9217 * returns: - None. 9218 * 9219 ***************************************************************************/ 9220 STATIC void 9221 em_put_hw_eeprom_semaphore(struct em_hw *hw) 9222 { 9223 uint32_t swsm; 9224 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 9225 9226 if (!hw->eeprom_semaphore_present) 9227 return; 9228 9229 swsm = E1000_READ_REG(hw, SWSM); 9230 if (hw->mac_type == em_80003es2lan) { 9231 /* Release both semaphores. */ 9232 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 9233 } else 9234 swsm &= ~(E1000_SWSM_SWESMBI); 9235 E1000_WRITE_REG(hw, SWSM, swsm); 9236 } 9237 9238 /*************************************************************************** 9239 * 9240 * Obtaining software semaphore bit (SMBI) before resetting PHY. 9241 * 9242 * hw: Struct containing variables accessed by shared code 9243 * 9244 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 9245 * E1000_SUCCESS at any other case. 9246 * 9247 ***************************************************************************/ 9248 STATIC int32_t 9249 em_get_software_semaphore(struct em_hw *hw) 9250 { 9251 int32_t timeout = hw->eeprom.word_size + 1; 9252 uint32_t swsm; 9253 DEBUGFUNC("em_get_software_semaphore"); 9254 9255 if (hw->mac_type != em_80003es2lan) 9256 return E1000_SUCCESS; 9257 9258 while (timeout) { 9259 swsm = E1000_READ_REG(hw, SWSM); 9260 /* 9261 * If SMBI bit cleared, it is now set and we hold the 9262 * semaphore 9263 */ 9264 if (!(swsm & E1000_SWSM_SMBI)) 9265 break; 9266 msec_delay_irq(1); 9267 timeout--; 9268 } 9269 9270 if (!timeout) { 9271 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 9272 return -E1000_ERR_RESET; 9273 } 9274 return E1000_SUCCESS; 9275 } 9276 9277 /*************************************************************************** 9278 * 9279 * Release semaphore bit (SMBI). 9280 * 9281 * hw: Struct containing variables accessed by shared code 9282 * 9283 ***************************************************************************/ 9284 STATIC void 9285 em_release_software_semaphore(struct em_hw *hw) 9286 { 9287 uint32_t swsm; 9288 DEBUGFUNC("em_release_software_semaphore"); 9289 9290 if (hw->mac_type != em_80003es2lan) 9291 return; 9292 9293 swsm = E1000_READ_REG(hw, SWSM); 9294 /* Release the SW semaphores. */ 9295 swsm &= ~E1000_SWSM_SMBI; 9296 E1000_WRITE_REG(hw, SWSM, swsm); 9297 } 9298 9299 /****************************************************************************** 9300 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 9301 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 9302 * the caller to figure out how to deal with it. 9303 * 9304 * hw - Struct containing variables accessed by shared code 9305 * 9306 * returns: - E1000_BLK_PHY_RESET 9307 * E1000_SUCCESS 9308 * 9309 *****************************************************************************/ 9310 int32_t 9311 em_check_phy_reset_block(struct em_hw *hw) 9312 { 9313 uint32_t manc = 0; 9314 uint32_t fwsm = 0; 9315 DEBUGFUNC("em_check_phy_reset_block\n"); 9316 9317 if (IS_ICH8(hw->mac_type)) { 9318 fwsm = E1000_READ_REG(hw, FWSM); 9319 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS : 9320 E1000_BLK_PHY_RESET; 9321 } 9322 if (hw->mac_type > em_82547_rev_2) 9323 manc = E1000_READ_REG(hw, MANC); 9324 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 9325 E1000_BLK_PHY_RESET : E1000_SUCCESS; 9326 } 9327 9328 /****************************************************************************** 9329 * Configure PCI-Ex no-snoop 9330 * 9331 * hw - Struct containing variables accessed by shared code. 9332 * no_snoop - Bitmap of no-snoop events. 9333 * 9334 * returns: E1000_SUCCESS 9335 * 9336 *****************************************************************************/ 9337 STATIC int32_t 9338 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 9339 { 9340 uint32_t gcr_reg = 0; 9341 DEBUGFUNC("em_set_pci_ex_no_snoop"); 9342 9343 if (hw->bus_type == em_bus_type_unknown) 9344 em_get_bus_info(hw); 9345 9346 if (hw->bus_type != em_bus_type_pci_express) 9347 return E1000_SUCCESS; 9348 9349 if (no_snoop) { 9350 gcr_reg = E1000_READ_REG(hw, GCR); 9351 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 9352 gcr_reg |= no_snoop; 9353 E1000_WRITE_REG(hw, GCR, gcr_reg); 9354 } 9355 if (IS_ICH8(hw->mac_type)) { 9356 uint32_t ctrl_ext; 9357 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 9358 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 9359 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 9360 } 9361 return E1000_SUCCESS; 9362 } 9363 9364 /*************************************************************************** 9365 * 9366 * Get software semaphore FLAG bit (SWFLAG). 9367 * SWFLAG is used to synchronize the access to all shared resource between 9368 * SW, FW and HW. 9369 * 9370 * hw: Struct containing variables accessed by shared code 9371 * 9372 ***************************************************************************/ 9373 STATIC int32_t 9374 em_get_software_flag(struct em_hw *hw) 9375 { 9376 int32_t timeout = PHY_CFG_TIMEOUT; 9377 uint32_t extcnf_ctrl; 9378 DEBUGFUNC("em_get_software_flag"); 9379 9380 if (IS_ICH8(hw->mac_type)) { 9381 while (timeout) { 9382 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9383 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9384 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9385 9386 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9387 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9388 break; 9389 msec_delay_irq(1); 9390 timeout--; 9391 } 9392 9393 if (!timeout) { 9394 DEBUGOUT("FW or HW locks the resource too long.\n"); 9395 return -E1000_ERR_CONFIG; 9396 } 9397 } 9398 return E1000_SUCCESS; 9399 } 9400 9401 /*************************************************************************** 9402 * 9403 * Release software semaphore FLAG bit (SWFLAG). 9404 * SWFLAG is used to synchronize the access to all shared resource between 9405 * SW, FW and HW. 9406 * 9407 * hw: Struct containing variables accessed by shared code 9408 * 9409 ***************************************************************************/ 9410 STATIC void 9411 em_release_software_flag(struct em_hw *hw) 9412 { 9413 uint32_t extcnf_ctrl; 9414 DEBUGFUNC("em_release_software_flag"); 9415 9416 if (IS_ICH8(hw->mac_type)) { 9417 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9418 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9419 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9420 } 9421 return; 9422 } 9423 9424 /** 9425 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 9426 * @hw: pointer to the HW structure 9427 * @bank: pointer to the variable that returns the active bank 9428 * 9429 * Reads signature byte from the NVM using the flash access registers. 9430 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 9431 **/ 9432 int32_t 9433 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 9434 { 9435 uint32_t eecd; 9436 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 9437 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 9438 uint32_t nvm_dword = 0; 9439 uint8_t sig_byte = 0; 9440 int32_t ret_val; 9441 9442 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 9443 9444 switch (hw->mac_type) { 9445 case em_pch_spt: 9446 bank1_offset = hw->flash_bank_size * 2; 9447 act_offset = E1000_ICH_NVM_SIG_WORD * 2; 9448 9449 /* set bank to 0 in case flash read fails. */ 9450 *bank = 0; 9451 9452 /* Check bank 0 */ 9453 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword); 9454 if (ret_val) 9455 return ret_val; 9456 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9457 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9458 E1000_ICH_NVM_SIG_VALUE) { 9459 *bank = 0; 9460 return 0; 9461 } 9462 9463 /* Check bank 1 */ 9464 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset, 9465 &nvm_dword); 9466 if (ret_val) 9467 return ret_val; 9468 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8); 9469 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9470 E1000_ICH_NVM_SIG_VALUE) { 9471 *bank = 1; 9472 return 0; 9473 } 9474 9475 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9476 return -1; 9477 case em_ich8lan: 9478 case em_ich9lan: 9479 eecd = E1000_READ_REG(hw, EECD); 9480 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 9481 E1000_EECD_SEC1VAL_VALID_MASK) { 9482 if (eecd & E1000_EECD_SEC1VAL) 9483 *bank = 1; 9484 else 9485 *bank = 0; 9486 9487 return E1000_SUCCESS; 9488 } 9489 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 9490 /* fall-thru */ 9491 default: 9492 /* set bank to 0 in case flash read fails */ 9493 *bank = 0; 9494 9495 /* Check bank 0 */ 9496 ret_val = em_read_ich8_byte(hw, act_offset, 9497 &sig_byte); 9498 if (ret_val) 9499 return ret_val; 9500 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9501 E1000_ICH_NVM_SIG_VALUE) { 9502 *bank = 0; 9503 return E1000_SUCCESS; 9504 } 9505 9506 /* Check bank 1 */ 9507 ret_val = em_read_ich8_byte(hw, act_offset + 9508 bank1_offset, 9509 &sig_byte); 9510 if (ret_val) 9511 return ret_val; 9512 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9513 E1000_ICH_NVM_SIG_VALUE) { 9514 *bank = 1; 9515 return E1000_SUCCESS; 9516 } 9517 9518 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9519 return -1; 9520 } 9521 } 9522 9523 STATIC int32_t 9524 em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words, 9525 uint16_t *data) 9526 { 9527 int32_t error = E1000_SUCCESS; 9528 uint32_t flash_bank = 0; 9529 uint32_t act_offset = 0; 9530 uint32_t bank_offset = 0; 9531 uint32_t dword = 0; 9532 uint16_t i = 0, add; 9533 9534 /* 9535 * We need to know which is the valid flash bank. In the event that 9536 * we didn't allocate eeprom_shadow_ram, we may not be managing 9537 * flash_bank. So it cannot be trusted and needs to be updated with 9538 * each read. 9539 */ 9540 9541 if (hw->mac_type != em_pch_spt) 9542 return -E1000_ERR_EEPROM; 9543 9544 error = em_get_software_flag(hw); 9545 if (error != E1000_SUCCESS) 9546 return error; 9547 9548 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9549 if (error != E1000_SUCCESS) { 9550 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9551 flash_bank = 0; 9552 } 9553 9554 /* 9555 * Adjust offset appropriately if we're on bank 1 - adjust for word 9556 * size 9557 */ 9558 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9559 9560 for (i = add = 0; i < words; i += add) { 9561 if ((offset + i) % 2) { 9562 add = 1; 9563 if (hw->eeprom_shadow_ram != NULL 9564 && hw->eeprom_shadow_ram[offset + i].modified) { 9565 data[i] = 9566 hw->eeprom_shadow_ram[offset+i].eeprom_word; 9567 continue; 9568 } 9569 act_offset = bank_offset + (offset + i - 1) * 2; 9570 } else { 9571 add = 2; 9572 if (hw->eeprom_shadow_ram != NULL 9573 && hw->eeprom_shadow_ram[offset+i].modified 9574 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9575 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9576 data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9577 continue; 9578 } 9579 act_offset = bank_offset + (offset + i) * 2; 9580 } 9581 error = em_read_ich8_dword(hw, act_offset, &dword); 9582 if (error != E1000_SUCCESS) 9583 break; 9584 if (hw->eeprom_shadow_ram != NULL 9585 && hw->eeprom_shadow_ram[offset+i].modified) { 9586 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; 9587 } else { 9588 if (add == 1) 9589 data[i] = dword >> 16; 9590 else 9591 data[i] = dword & 0xFFFFUL; 9592 } 9593 if (add == 1 || words-i == 1) 9594 continue; 9595 if (hw->eeprom_shadow_ram != NULL 9596 && hw->eeprom_shadow_ram[offset+i+1].modified) { 9597 data[i+1] = 9598 hw->eeprom_shadow_ram[offset+i+1].eeprom_word; 9599 } else { 9600 data[i+1] = dword >> 16; 9601 } 9602 } 9603 9604 em_release_software_flag(hw); 9605 9606 return error; 9607 } 9608 9609 /****************************************************************************** 9610 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 9611 * register. 9612 * 9613 * hw - Struct containing variables accessed by shared code 9614 * offset - offset of word in the EEPROM to read 9615 * data - word read from the EEPROM 9616 * words - number of words to read 9617 *****************************************************************************/ 9618 STATIC int32_t 9619 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9620 uint16_t *data) 9621 { 9622 int32_t error = E1000_SUCCESS; 9623 uint32_t flash_bank = 0; 9624 uint32_t act_offset = 0; 9625 uint32_t bank_offset = 0; 9626 uint16_t word = 0; 9627 uint16_t i = 0; 9628 /* 9629 * We need to know which is the valid flash bank. In the event that 9630 * we didn't allocate eeprom_shadow_ram, we may not be managing 9631 * flash_bank. So it cannot be trusted and needs to be updated with 9632 * each read. 9633 */ 9634 9635 if (hw->mac_type == em_pch_spt) 9636 return em_read_eeprom_spt(hw, offset, words, data); 9637 9638 error = em_get_software_flag(hw); 9639 if (error != E1000_SUCCESS) 9640 return error; 9641 9642 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9643 if (error != E1000_SUCCESS) { 9644 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9645 flash_bank = 0; 9646 } 9647 9648 /* 9649 * Adjust offset appropriately if we're on bank 1 - adjust for word 9650 * size 9651 */ 9652 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9653 9654 for (i = 0; i < words; i++) { 9655 if (hw->eeprom_shadow_ram != NULL && 9656 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9657 data[i] = 9658 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9659 } else { 9660 /* The NVM part needs a byte offset, hence * 2 */ 9661 act_offset = bank_offset + ((offset + i) * 2); 9662 error = em_read_ich8_word(hw, act_offset, &word); 9663 if (error != E1000_SUCCESS) 9664 break; 9665 data[i] = word; 9666 } 9667 } 9668 9669 em_release_software_flag(hw); 9670 9671 return error; 9672 } 9673 9674 /****************************************************************************** 9675 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9676 * register. Actually, writes are written to the shadow ram cache in the hw 9677 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9678 * the NVM, which occurs when the NVM checksum is updated. 9679 * 9680 * hw - Struct containing variables accessed by shared code 9681 * offset - offset of word in the EEPROM to write 9682 * words - number of words to write 9683 * data - words to write to the EEPROM 9684 *****************************************************************************/ 9685 STATIC int32_t 9686 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9687 uint16_t *data) 9688 { 9689 uint32_t i = 0; 9690 int32_t error = E1000_SUCCESS; 9691 error = em_get_software_flag(hw); 9692 if (error != E1000_SUCCESS) 9693 return error; 9694 /* 9695 * A driver can write to the NVM only if it has eeprom_shadow_ram 9696 * allocated. Subsequent reads to the modified words are read from 9697 * this cached structure as well. Writes will only go into this 9698 * cached structure unless it's followed by a call to 9699 * em_update_eeprom_checksum() where it will commit the changes and 9700 * clear the "modified" field. 9701 */ 9702 if (hw->eeprom_shadow_ram != NULL) { 9703 for (i = 0; i < words; i++) { 9704 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9705 hw->eeprom_shadow_ram[offset + i].modified = 9706 TRUE; 9707 hw->eeprom_shadow_ram[offset + i].eeprom_word = 9708 data[i]; 9709 } else { 9710 error = -E1000_ERR_EEPROM; 9711 break; 9712 } 9713 } 9714 } else { 9715 /* 9716 * Drivers have the option to not allocate eeprom_shadow_ram 9717 * as long as they don't perform any NVM writes. An attempt 9718 * in doing so will result in this error. 9719 */ 9720 error = -E1000_ERR_EEPROM; 9721 } 9722 9723 em_release_software_flag(hw); 9724 9725 return error; 9726 } 9727 9728 /****************************************************************************** 9729 * This function does initial flash setup so that a new read/write/erase cycle 9730 * can be started. 9731 * 9732 * hw - The pointer to the hw structure 9733 ****************************************************************************/ 9734 STATIC int32_t 9735 em_ich8_cycle_init(struct em_hw *hw) 9736 { 9737 union ich8_hws_flash_status hsfsts; 9738 int32_t error = E1000_ERR_EEPROM; 9739 int32_t i = 0; 9740 DEBUGFUNC("em_ich8_cycle_init"); 9741 9742 if (hw->mac_type == em_pch_spt) 9743 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 9744 ICH_FLASH_HSFSTS) & 0xFFFFUL; 9745 else 9746 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9747 ICH_FLASH_HSFSTS); 9748 9749 /* May be check the Flash Des Valid bit in Hw status */ 9750 if (hsfsts.hsf_status.fldesvalid == 0) { 9751 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 9752 " used."); 9753 return error; 9754 } 9755 /* Clear FCERR in Hw status by writing 1 */ 9756 /* Clear DAEL in Hw status by writing a 1 */ 9757 hsfsts.hsf_status.flcerr = 1; 9758 hsfsts.hsf_status.dael = 1; 9759 if (hw->mac_type == em_pch_spt) 9760 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9761 hsfsts.regval & 0xFFFFUL); 9762 else 9763 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9764 hsfsts.regval); 9765 /* 9766 * Either we should have a hardware SPI cycle in progress bit to 9767 * check against, in order to start a new cycle or FDONE bit should 9768 * be changed in the hardware so that it is 1 after hardware reset, 9769 * which can then be used as an indication whether a cycle is in 9770 * progress or has been completed .. we should also have some 9771 * software semaphore mechanism to guard FDONE or the cycle in 9772 * progress bit so that two threads access to those bits can be 9773 * sequentiallized or a way so that 2 threads dont start the cycle at 9774 * the same time 9775 */ 9776 9777 if (hsfsts.hsf_status.flcinprog == 0) { 9778 /* 9779 * There is no cycle running at present, so we can start a 9780 * cycle 9781 */ 9782 /* Begin by setting Flash Cycle Done. */ 9783 hsfsts.hsf_status.flcdone = 1; 9784 if (hw->mac_type == em_pch_spt) 9785 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9786 hsfsts.regval & 0xFFFFUL); 9787 else 9788 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9789 hsfsts.regval); 9790 error = E1000_SUCCESS; 9791 } else { 9792 /* 9793 * otherwise poll for sometime so the current cycle has a 9794 * chance to end before giving up. 9795 */ 9796 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 9797 if (hw->mac_type == em_pch_spt) 9798 hsfsts.regval = E1000_READ_ICH_FLASH_REG32( 9799 hw, ICH_FLASH_HSFSTS) & 0xFFFFUL; 9800 else 9801 hsfsts.regval = E1000_READ_ICH_FLASH_REG16( 9802 hw, ICH_FLASH_HSFSTS); 9803 if (hsfsts.hsf_status.flcinprog == 0) { 9804 error = E1000_SUCCESS; 9805 break; 9806 } 9807 usec_delay(1); 9808 } 9809 if (error == E1000_SUCCESS) { 9810 /* 9811 * Successful in waiting for previous cycle to 9812 * timeout, now set the Flash Cycle Done. 9813 */ 9814 hsfsts.hsf_status.flcdone = 1; 9815 if (hw->mac_type == em_pch_spt) 9816 E1000_WRITE_ICH_FLASH_REG32(hw, 9817 ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL); 9818 else 9819 E1000_WRITE_ICH_FLASH_REG16(hw, 9820 ICH_FLASH_HSFSTS, hsfsts.regval); 9821 } else { 9822 DEBUGOUT("Flash controller busy, cannot get access"); 9823 } 9824 } 9825 return error; 9826 } 9827 9828 /****************************************************************************** 9829 * This function starts a flash cycle and waits for its completion 9830 * 9831 * hw - The pointer to the hw structure 9832 *****************************************************************************/ 9833 STATIC int32_t 9834 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 9835 { 9836 union ich8_hws_flash_ctrl hsflctl; 9837 union ich8_hws_flash_status hsfsts; 9838 int32_t error = E1000_ERR_EEPROM; 9839 uint32_t i = 0; 9840 9841 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 9842 if (hw->mac_type == em_pch_spt) 9843 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 9844 ICH_FLASH_HSFSTS) >> 16; 9845 else 9846 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9847 ICH_FLASH_HSFCTL); 9848 hsflctl.hsf_ctrl.flcgo = 1; 9849 9850 if (hw->mac_type == em_pch_spt) 9851 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9852 (uint32_t)hsflctl.regval << 16); 9853 else 9854 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9855 hsflctl.regval); 9856 9857 /* wait till FDONE bit is set to 1 */ 9858 do { 9859 if (hw->mac_type == em_pch_spt) 9860 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw, 9861 ICH_FLASH_HSFSTS) & 0xFFFFUL; 9862 else 9863 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9864 ICH_FLASH_HSFSTS); 9865 if (hsfsts.hsf_status.flcdone == 1) 9866 break; 9867 usec_delay(1); 9868 i++; 9869 } while (i < timeout); 9870 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 9871 error = E1000_SUCCESS; 9872 } 9873 return error; 9874 } 9875 9876 /****************************************************************************** 9877 * Reads a byte or word from the NVM using the ICH8 flash access registers. 9878 * 9879 * hw - The pointer to the hw structure 9880 * index - The index of the byte or word to read. 9881 * size - Size of data to read, 1=byte 2=word 9882 * data - Pointer to the word to store the value read. 9883 *****************************************************************************/ 9884 STATIC int32_t 9885 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9886 uint16_t *data) 9887 { 9888 union ich8_hws_flash_status hsfsts; 9889 union ich8_hws_flash_ctrl hsflctl; 9890 uint32_t flash_linear_address; 9891 uint32_t flash_data = 0; 9892 int32_t error = -E1000_ERR_EEPROM; 9893 int32_t count = 0; 9894 DEBUGFUNC("em_read_ich8_data"); 9895 9896 if (size < 1 || size > 2 || data == 0x0 || 9897 index > ICH_FLASH_LINEAR_ADDR_MASK) 9898 return error; 9899 9900 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9901 hw->flash_base_addr; 9902 9903 do { 9904 usec_delay(1); 9905 /* Steps */ 9906 error = em_ich8_cycle_init(hw); 9907 if (error != E1000_SUCCESS) 9908 break; 9909 9910 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9911 ICH_FLASH_HSFCTL); 9912 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9913 hsflctl.hsf_ctrl.fldbcount = size - 1; 9914 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 9915 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9916 hsflctl.regval); 9917 /* 9918 * Write the last 24 bits of index into Flash Linear address 9919 * field in Flash Address 9920 */ 9921 /* TODO: TBD maybe check the index against the size of flash */ 9922 9923 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 9924 flash_linear_address); 9925 9926 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9927 /* 9928 * Check if FCERR is set to 1, if set to 1, clear it and try 9929 * the whole sequence a few more times, else read in (shift 9930 * in) the Flash Data0, the order is least significant byte 9931 * first msb to lsb 9932 */ 9933 if (error == E1000_SUCCESS) { 9934 flash_data = E1000_READ_ICH_FLASH_REG(hw, 9935 ICH_FLASH_FDATA0); 9936 if (size == 1) { 9937 *data = (uint8_t) (flash_data & 0x000000FF); 9938 } else if (size == 2) { 9939 *data = (uint16_t) (flash_data & 0x0000FFFF); 9940 } 9941 break; 9942 } else { 9943 /* 9944 * If we've gotten here, then things are probably 9945 * completely hosed, but if the error condition is 9946 * detected, it won't hurt to give it another 9947 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9948 */ 9949 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9950 ICH_FLASH_HSFSTS); 9951 if (hsfsts.hsf_status.flcerr == 1) { 9952 /* Repeat for some time before giving up. */ 9953 continue; 9954 } else if (hsfsts.hsf_status.flcdone == 0) { 9955 DEBUGOUT("Timeout error - flash cycle did not" 9956 " complete."); 9957 break; 9958 } 9959 } 9960 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9961 9962 return error; 9963 } 9964 9965 STATIC int32_t 9966 em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data) 9967 { 9968 union ich8_hws_flash_status hsfsts; 9969 union ich8_hws_flash_ctrl hsflctl; 9970 uint32_t flash_linear_address; 9971 int32_t error = -E1000_ERR_EEPROM; 9972 uint32_t count = 0; 9973 DEBUGFUNC("em_read_ich8_data32"); 9974 9975 if (hw->mac_type != em_pch_spt) 9976 return error; 9977 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 9978 return error; 9979 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 9980 hw->flash_base_addr; 9981 9982 do { 9983 usec_delay(1); 9984 /* Steps */ 9985 error = em_ich8_cycle_init(hw); 9986 if (error != E1000_SUCCESS) 9987 break; 9988 9989 /* 32 bit accesses in SPT. */ 9990 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw, 9991 ICH_FLASH_HSFSTS) >> 16; 9992 9993 hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1; 9994 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 9995 9996 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS, 9997 (uint32_t)hsflctl.regval << 16); 9998 /* 9999 * Write the last 24 bits of offset into Flash Linear address 10000 * field in Flash Address 10001 */ 10002 /* TODO: TBD maybe check the offset against the size of flash */ 10003 10004 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10005 flash_linear_address); 10006 10007 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10008 /* 10009 * Check if FCERR is set to 1, if set to 1, clear it and try 10010 * the whole sequence a few more times, else read in (shift 10011 * in) the Flash Data0, the order is least significant byte 10012 * first msb to lsb 10013 */ 10014 if (error == E1000_SUCCESS) { 10015 (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw, 10016 ICH_FLASH_FDATA0); 10017 break; 10018 } else { 10019 /* 10020 * If we've gotten here, then things are probably 10021 * completely hosed, but if the error condition is 10022 * detected, it won't hurt to give it another 10023 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10024 */ 10025 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10026 ICH_FLASH_HSFSTS); 10027 if (hsfsts.hsf_status.flcerr == 1) { 10028 /* Repeat for some time before giving up. */ 10029 continue; 10030 } else if (hsfsts.hsf_status.flcdone == 0) { 10031 DEBUGOUT("Timeout error - flash cycle did not" 10032 " complete."); 10033 break; 10034 } 10035 } 10036 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10037 10038 return error; 10039 } 10040 10041 10042 /****************************************************************************** 10043 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 10044 * 10045 * hw - The pointer to the hw structure 10046 * index - The index of the byte/word to write. 10047 * size - Size of data to read, 1=byte 2=word 10048 * data - The byte(s) to write to the NVM. 10049 *****************************************************************************/ 10050 STATIC int32_t 10051 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 10052 uint16_t data) 10053 { 10054 union ich8_hws_flash_status hsfsts; 10055 union ich8_hws_flash_ctrl hsflctl; 10056 uint32_t flash_linear_address; 10057 uint32_t flash_data = 0; 10058 int32_t error = -E1000_ERR_EEPROM; 10059 int32_t count = 0; 10060 DEBUGFUNC("em_write_ich8_data"); 10061 10062 if (hw->mac_type == em_pch_spt) 10063 return -E1000_ERR_EEPROM; 10064 if (size < 1 || size > 2 || data > size * 0xff || 10065 index > ICH_FLASH_LINEAR_ADDR_MASK) 10066 return error; 10067 10068 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 10069 hw->flash_base_addr; 10070 10071 do { 10072 usec_delay(1); 10073 /* Steps */ 10074 error = em_ich8_cycle_init(hw); 10075 if (error != E1000_SUCCESS) 10076 break; 10077 10078 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10079 ICH_FLASH_HSFCTL); 10080 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 10081 hsflctl.hsf_ctrl.fldbcount = size - 1; 10082 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 10083 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10084 hsflctl.regval); 10085 /* 10086 * Write the last 24 bits of index into Flash Linear address 10087 * field in Flash Address 10088 */ 10089 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10090 flash_linear_address); 10091 10092 if (size == 1) 10093 flash_data = (uint32_t) data & 0x00FF; 10094 else 10095 flash_data = (uint32_t) data; 10096 10097 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data); 10098 /* 10099 * check if FCERR is set to 1 , if set to 1, clear it and try 10100 * the whole sequence a few more times else done 10101 */ 10102 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 10103 if (error == E1000_SUCCESS) { 10104 break; 10105 } else { 10106 /* 10107 * If we're here, then things are most likely 10108 * completely hosed, but if the error condition is 10109 * detected, it won't hurt to give it another 10110 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 10111 */ 10112 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10113 ICH_FLASH_HSFSTS); 10114 if (hsfsts.hsf_status.flcerr == 1) { 10115 /* Repeat for some time before giving up. */ 10116 continue; 10117 } else if (hsfsts.hsf_status.flcdone == 0) { 10118 DEBUGOUT("Timeout error - flash cycle did not" 10119 " complete."); 10120 break; 10121 } 10122 } 10123 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 10124 10125 return error; 10126 } 10127 10128 /****************************************************************************** 10129 * Reads a single byte from the NVM using the ICH8 flash access registers. 10130 * 10131 * hw - pointer to em_hw structure 10132 * index - The index of the byte to read. 10133 * data - Pointer to a byte to store the value read. 10134 *****************************************************************************/ 10135 STATIC int32_t 10136 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 10137 { 10138 int32_t status = E1000_SUCCESS; 10139 uint16_t word = 0; 10140 10141 if (hw->mac_type == em_pch_spt) 10142 return -E1000_ERR_EEPROM; 10143 else 10144 status = em_read_ich8_data(hw, index, 1, &word); 10145 if (status == E1000_SUCCESS) { 10146 *data = (uint8_t) word; 10147 } 10148 return status; 10149 } 10150 10151 /****************************************************************************** 10152 * Writes a single byte to the NVM using the ICH8 flash access registers. 10153 * Performs verification by reading back the value and then going through 10154 * a retry algorithm before giving up. 10155 * 10156 * hw - pointer to em_hw structure 10157 * index - The index of the byte to write. 10158 * byte - The byte to write to the NVM. 10159 *****************************************************************************/ 10160 STATIC int32_t 10161 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 10162 { 10163 int32_t error = E1000_SUCCESS; 10164 int32_t program_retries = 0; 10165 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 10166 10167 error = em_write_ich8_byte(hw, index, byte); 10168 10169 if (error != E1000_SUCCESS) { 10170 for (program_retries = 0; program_retries < 100; 10171 program_retries++) { 10172 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 10173 byte, index); 10174 error = em_write_ich8_byte(hw, index, byte); 10175 usec_delay(100); 10176 if (error == E1000_SUCCESS) 10177 break; 10178 } 10179 } 10180 if (program_retries == 100) 10181 error = E1000_ERR_EEPROM; 10182 10183 return error; 10184 } 10185 10186 /****************************************************************************** 10187 * Writes a single byte to the NVM using the ICH8 flash access registers. 10188 * 10189 * hw - pointer to em_hw structure 10190 * index - The index of the byte to read. 10191 * data - The byte to write to the NVM. 10192 *****************************************************************************/ 10193 STATIC int32_t 10194 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 10195 { 10196 int32_t status = E1000_SUCCESS; 10197 uint16_t word = (uint16_t) data; 10198 status = em_write_ich8_data(hw, index, 1, word); 10199 10200 return status; 10201 } 10202 10203 /****************************************************************************** 10204 * Reads a dword from the NVM using the ICH8 flash access registers. 10205 * 10206 * hw - pointer to em_hw structure 10207 * index - The starting BYTE index of the word to read. 10208 * data - Pointer to a word to store the value read. 10209 *****************************************************************************/ 10210 STATIC int32_t 10211 em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data) 10212 { 10213 int32_t status = E1000_SUCCESS; 10214 status = em_read_ich8_data32(hw, index, data); 10215 return status; 10216 } 10217 10218 /****************************************************************************** 10219 * Reads a word from the NVM using the ICH8 flash access registers. 10220 * 10221 * hw - pointer to em_hw structure 10222 * index - The starting byte index of the word to read. 10223 * data - Pointer to a word to store the value read. 10224 *****************************************************************************/ 10225 STATIC int32_t 10226 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 10227 { 10228 int32_t status = E1000_SUCCESS; 10229 status = em_read_ich8_data(hw, index, 2, data); 10230 return status; 10231 } 10232 10233 /****************************************************************************** 10234 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 10235 * based. 10236 * 10237 * hw - pointer to em_hw structure 10238 * bank - 0 for first bank, 1 for second bank 10239 * 10240 * Note that this function may actually erase as much as 8 or 64 KBytes. The 10241 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 10242 * bank size may be 4, 8 or 64 KBytes 10243 *****************************************************************************/ 10244 int32_t 10245 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 10246 { 10247 union ich8_hws_flash_status hsfsts; 10248 union ich8_hws_flash_ctrl hsflctl; 10249 uint32_t flash_linear_address; 10250 int32_t count = 0; 10251 int32_t error = E1000_ERR_EEPROM; 10252 int32_t iteration; 10253 int32_t sub_sector_size = 0; 10254 int32_t bank_size; 10255 int32_t j = 0; 10256 int32_t error_flag = 0; 10257 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 10258 /* 10259 * Determine HW Sector size: Read BERASE bits of Hw flash Status 10260 * register 10261 */ 10262 /* 10263 * 00: The Hw sector is 256 bytes, hence we need to erase 16 10264 * consecutive sectors. The start index for the nth Hw sector can be 10265 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 10266 * hence we need to erase 1 sector. The start index for the nth Hw 10267 * sector can be calculated as bank * 4096 10: The HW sector is 8K 10268 * bytes 11: The Hw sector size is 64K bytes 10269 */ 10270 if (hsfsts.hsf_status.berasesz == 0x0) { 10271 /* Hw sector size 256 */ 10272 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 10273 bank_size = ICH_FLASH_SECTOR_SIZE; 10274 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 10275 } else if (hsfsts.hsf_status.berasesz == 0x1) { 10276 bank_size = ICH_FLASH_SEG_SIZE_4K; 10277 iteration = 1; 10278 } else if (hsfsts.hsf_status.berasesz == 0x2) { 10279 if (hw->mac_type == em_ich9lan) { 10280 uint32_t gfpreg, sector_base_addr, sector_end_addr; 10281 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 10282 ICH_FLASH_GFPREG); 10283 /* 10284 * sector_X_addr is a "sector"-aligned address (4096 bytes) 10285 * Add 1 to sector_end_addr since this sector is included in 10286 * the overall size. 10287 */ 10288 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 10289 sector_end_addr = 10290 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 10291 10292 /* 10293 * find total size of the NVM, then cut in half since the total 10294 * size represents two separate NVM banks. 10295 */ 10296 bank_size = (sector_end_addr - sector_base_addr) 10297 << ICH_FLASH_SECT_ADDR_SHIFT; 10298 bank_size /= 2; 10299 /* Word align */ 10300 bank_size = 10301 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 10302 10303 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 10304 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 10305 } else { 10306 return error; 10307 } 10308 } else if (hsfsts.hsf_status.berasesz == 0x3) { 10309 bank_size = ICH_FLASH_SEG_SIZE_64K; 10310 iteration = 1; 10311 } else { 10312 return error; 10313 } 10314 10315 for (j = 0; j < iteration; j++) { 10316 do { 10317 count++; 10318 /* Steps */ 10319 error = em_ich8_cycle_init(hw); 10320 if (error != E1000_SUCCESS) { 10321 error_flag = 1; 10322 break; 10323 } 10324 /* 10325 * Write a value 11 (block Erase) in Flash Cycle 10326 * field in Hw flash Control 10327 */ 10328 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 10329 ICH_FLASH_HSFCTL); 10330 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 10331 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 10332 hsflctl.regval); 10333 /* 10334 * Write the last 24 bits of an index within the 10335 * block into Flash Linear address field in Flash 10336 * Address. This probably needs to be calculated 10337 * here based off the on-chip erase sector size and 10338 * the software bank size (4, 8 or 64 KBytes) 10339 */ 10340 flash_linear_address = 10341 bank * bank_size + j * sub_sector_size; 10342 flash_linear_address += hw->flash_base_addr; 10343 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 10344 10345 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR, 10346 flash_linear_address); 10347 10348 error = 10349 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 10350 /* 10351 * Check if FCERR is set to 1. If 1, clear it and 10352 * try the whole sequence a few more times else Done 10353 */ 10354 if (error == E1000_SUCCESS) { 10355 break; 10356 } else { 10357 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 10358 ICH_FLASH_HSFSTS); 10359 if (hsfsts.hsf_status.flcerr == 1) { 10360 /* 10361 * repeat for some time before giving 10362 * up 10363 */ 10364 continue; 10365 } else if (hsfsts.hsf_status.flcdone == 0) { 10366 error_flag = 1; 10367 break; 10368 } 10369 } 10370 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 10371 if (error_flag == 1) 10372 break; 10373 } 10374 if (error_flag != 1) 10375 error = E1000_SUCCESS; 10376 return error; 10377 } 10378 10379 /****************************************************************************** 10380 * Reads 16-bit words from the OTP. Return error when the word is not 10381 * stored in OTP. 10382 * 10383 * hw - Struct containing variables accessed by shared code 10384 * offset - offset of word in the OTP to read 10385 * data - word read from the OTP 10386 * words - number of words to read 10387 *****************************************************************************/ 10388 STATIC int32_t 10389 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words, 10390 uint16_t *data) 10391 { 10392 int32_t ret_val = E1000_SUCCESS; 10393 10394 switch (offset) 10395 { 10396 case EEPROM_MAC_ADDR_WORD0: 10397 case EEPROM_MAC_ADDR_WORD1: 10398 case EEPROM_MAC_ADDR_WORD2: 10399 /* Generate random MAC address if there's none. */ 10400 ret_val = em_read_invm_word_i210(hw, offset, data); 10401 if (ret_val != E1000_SUCCESS) { 10402 DEBUGOUT("MAC Addr not found in iNVM\n"); 10403 *data = 0xFFFF; 10404 ret_val = E1000_SUCCESS; 10405 } 10406 break; 10407 case EEPROM_INIT_CONTROL2_REG: 10408 ret_val = em_read_invm_word_i210(hw, offset, data); 10409 if (ret_val != E1000_SUCCESS) { 10410 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 10411 ret_val = E1000_SUCCESS; 10412 } 10413 break; 10414 case EEPROM_INIT_CONTROL4_REG: 10415 ret_val = em_read_invm_word_i210(hw, offset, data); 10416 if (ret_val != E1000_SUCCESS) { 10417 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 10418 ret_val = E1000_SUCCESS; 10419 } 10420 break; 10421 case EEPROM_LED_1_CFG: 10422 ret_val = em_read_invm_word_i210(hw, offset, data); 10423 if (ret_val != E1000_SUCCESS) { 10424 *data = NVM_LED_1_CFG_DEFAULT_I211; 10425 ret_val = E1000_SUCCESS; 10426 } 10427 break; 10428 case EEPROM_LED_0_2_CFG: 10429 ret_val = em_read_invm_word_i210(hw, offset, data); 10430 if (ret_val != E1000_SUCCESS) { 10431 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 10432 ret_val = E1000_SUCCESS; 10433 } 10434 break; 10435 case EEPROM_ID_LED_SETTINGS: 10436 ret_val = em_read_invm_word_i210(hw, offset, data); 10437 if (ret_val != E1000_SUCCESS) { 10438 *data = ID_LED_RESERVED_FFFF; 10439 ret_val = E1000_SUCCESS; 10440 } 10441 break; 10442 default: 10443 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset); 10444 *data = NVM_RESERVED_WORD; 10445 break; 10446 } 10447 10448 return ret_val; 10449 } 10450 10451 /****************************************************************************** 10452 * Reads 16-bit words from the OTP. Return error when the word is not 10453 * stored in OTP. 10454 * 10455 * hw - Struct containing variables accessed by shared code 10456 * offset - offset of word in the OTP to read 10457 * data - word read from the OTP 10458 *****************************************************************************/ 10459 STATIC int32_t 10460 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data) 10461 { 10462 int32_t error = -E1000_NOT_IMPLEMENTED; 10463 uint32_t invm_dword; 10464 uint16_t i; 10465 uint8_t record_type, word_address; 10466 10467 for (i = 0; i < INVM_SIZE; i++) { 10468 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i)); 10469 /* Get record type */ 10470 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 10471 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 10472 break; 10473 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 10474 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 10475 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 10476 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 10477 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 10478 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 10479 if (word_address == address) { 10480 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 10481 error = E1000_SUCCESS; 10482 break; 10483 } 10484 } 10485 } 10486 10487 return error; 10488 } 10489 10490 STATIC int32_t 10491 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 10492 uint32_t cnf_size) 10493 { 10494 uint32_t ret_val = E1000_SUCCESS; 10495 uint16_t word_addr, reg_data, reg_addr; 10496 uint16_t i; 10497 /* cnf_base_addr is in DWORD */ 10498 word_addr = (uint16_t) (cnf_base_addr << 1); 10499 10500 /* cnf_size is returned in size of dwords */ 10501 for (i = 0; i < cnf_size; i++) { 10502 ret_val = 10503 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 10504 if (ret_val) 10505 return ret_val; 10506 10507 ret_val = 10508 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 10509 if (ret_val) 10510 return ret_val; 10511 10512 ret_val = em_get_software_flag(hw); 10513 if (ret_val != E1000_SUCCESS) 10514 return ret_val; 10515 10516 ret_val = 10517 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 10518 10519 em_release_software_flag(hw); 10520 } 10521 10522 return ret_val; 10523 } 10524 10525 /****************************************************************************** 10526 * This function initializes the PHY from the NVM on ICH8 platforms. This 10527 * is needed due to an issue where the NVM configuration is not properly 10528 * autoloaded after power transitions. Therefore, after each PHY reset, we 10529 * will load the configuration data out of the NVM manually. 10530 * 10531 * hw: Struct containing variables accessed by shared code 10532 *****************************************************************************/ 10533 STATIC int32_t 10534 em_init_lcd_from_nvm(struct em_hw *hw) 10535 { 10536 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 10537 if (hw->phy_type != em_phy_igp_3) 10538 return E1000_SUCCESS; 10539 10540 /* Check if SW needs configure the PHY */ 10541 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 10542 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 10543 hw->mac_type == em_pchlan || 10544 hw->mac_type == em_pch2lan || 10545 hw->mac_type == em_pch_lpt || 10546 hw->mac_type == em_pch_spt) 10547 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 10548 else 10549 sw_cfg_mask = FEXTNVM_SW_CONFIG; 10550 10551 reg_data = E1000_READ_REG(hw, FEXTNVM); 10552 if (!(reg_data & sw_cfg_mask)) 10553 return E1000_SUCCESS; 10554 10555 /* Wait for basic configuration completes before proceeding */ 10556 loop = 0; 10557 do { 10558 reg_data = 10559 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 10560 usec_delay(100); 10561 loop++; 10562 } while ((!reg_data) && (loop < 50)); 10563 10564 /* Clear the Init Done bit for the next init event */ 10565 reg_data = E1000_READ_REG(hw, STATUS); 10566 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 10567 E1000_WRITE_REG(hw, STATUS, reg_data); 10568 /* 10569 * Make sure HW does not configure LCD from PHY extended 10570 * configuration before SW configuration 10571 */ 10572 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10573 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 10574 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 10575 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 10576 cnf_size >>= 16; 10577 if (cnf_size) { 10578 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 10579 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 10580 /* cnf_base_addr is in DWORD */ 10581 cnf_base_addr >>= 16; 10582 10583 /* Configure LCD from extended configuration region. */ 10584 ret_val = em_init_lcd_from_nvm_config_region(hw, 10585 cnf_base_addr, cnf_size); 10586 if (ret_val) 10587 return ret_val; 10588 } 10589 } 10590 return E1000_SUCCESS; 10591 } 10592 10593 /****************************************************************************** 10594 * em_set_pciex_completion_timeout - set pci-e completion timeout 10595 * 10596 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 10597 * however the hardware default for these parts is 500us to 1ms which is less 10598 * than the 10ms recommended by the pci-e spec. To address this we need to 10599 * increase the value to either 10ms to 200ms for capability version 1 config, 10600 * or 16ms to 55ms for version 2. 10601 * 10602 * * hw - pointer to em_hw structure 10603 *****************************************************************************/ 10604 int32_t 10605 em_set_pciex_completion_timeout(struct em_hw *hw) 10606 { 10607 uint32_t gcr = E1000_READ_REG(hw, GCR); 10608 int32_t ret_val = E1000_SUCCESS; 10609 10610 /* Only take action if timeout value is not set by system BIOS */ 10611 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 10612 goto out; 10613 10614 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 10615 10616 /* 10617 * If capababilities version is type 1 we can write the 10618 * timeout of 10ms to 200ms through the GCR register 10619 */ 10620 10621 if (!(gcr & E1000_GCR_CAP_VER2)) { 10622 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 10623 DEBUGOUT("PCIe capability version 1 detected, setting \ 10624 completion timeout to 10ms."); 10625 goto out; 10626 } 10627 10628 /* 10629 * For version 2 capabilities we need to write the config space 10630 * directly in order to set the completion timeout value for 10631 * 16ms to 55ms 10632 * 10633 * XXX: Implement em_*_pcie_cap_reg() first. 10634 */ 10635 #if 0 10636 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10637 &pciex_devctl2); 10638 10639 if (ret_val) 10640 goto out; 10641 10642 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 10643 10644 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10645 &pciex_devctl2); 10646 #endif 10647 10648 out: 10649 10650 /* Disable completion timeout resend */ 10651 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 10652 10653 DEBUGOUT("PCIe completion timeout resend disabled."); 10654 10655 E1000_WRITE_REG(hw, GCR, gcr); 10656 return ret_val; 10657 } 10658 10659 /*************************************************************************** 10660 * Set slow MDIO access mode 10661 ***************************************************************************/ 10662 static int32_t 10663 em_set_mdio_slow_mode_hv(struct em_hw *hw) 10664 { 10665 int32_t ret_val; 10666 uint16_t data; 10667 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 10668 10669 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 10670 if (ret_val) 10671 return ret_val; 10672 10673 data |= HV_KMRN_MDIO_SLOW; 10674 10675 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 10676 10677 return ret_val; 10678 } 10679 10680 /*************************************************************************** 10681 * A series of Phy workarounds to be done after every PHY reset. 10682 ***************************************************************************/ 10683 int32_t 10684 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 10685 { 10686 int32_t ret_val = E1000_SUCCESS; 10687 uint16_t phy_data; 10688 uint16_t swfw; 10689 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 10690 10691 if (hw->mac_type != em_pchlan) 10692 goto out; 10693 10694 swfw = E1000_SWFW_PHY0_SM; 10695 10696 /* Set MDIO slow mode before any other MDIO access */ 10697 if (hw->phy_type == em_phy_82577 || 10698 hw->phy_type == em_phy_82578) { 10699 ret_val = em_set_mdio_slow_mode_hv(hw); 10700 if (ret_val) 10701 goto out; 10702 } 10703 10704 /* Hanksville M Phy init for IEEE. */ 10705 if ((hw->revision_id == 2) && 10706 (hw->phy_type == em_phy_82577) && 10707 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10708 em_write_phy_reg(hw, 0x10, 0x8823); 10709 em_write_phy_reg(hw, 0x11, 0x0018); 10710 em_write_phy_reg(hw, 0x10, 0x8824); 10711 em_write_phy_reg(hw, 0x11, 0x0016); 10712 em_write_phy_reg(hw, 0x10, 0x8825); 10713 em_write_phy_reg(hw, 0x11, 0x001A); 10714 em_write_phy_reg(hw, 0x10, 0x888C); 10715 em_write_phy_reg(hw, 0x11, 0x0007); 10716 em_write_phy_reg(hw, 0x10, 0x888D); 10717 em_write_phy_reg(hw, 0x11, 0x0007); 10718 em_write_phy_reg(hw, 0x10, 0x888E); 10719 em_write_phy_reg(hw, 0x11, 0x0007); 10720 em_write_phy_reg(hw, 0x10, 0x8827); 10721 em_write_phy_reg(hw, 0x11, 0x0001); 10722 em_write_phy_reg(hw, 0x10, 0x8835); 10723 em_write_phy_reg(hw, 0x11, 0x0001); 10724 em_write_phy_reg(hw, 0x10, 0x8834); 10725 em_write_phy_reg(hw, 0x11, 0x0001); 10726 em_write_phy_reg(hw, 0x10, 0x8833); 10727 em_write_phy_reg(hw, 0x11, 0x0002); 10728 } 10729 10730 if (((hw->phy_type == em_phy_82577) && 10731 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 10732 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 10733 /* Disable generation of early preamble */ 10734 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 10735 if (ret_val) 10736 goto out; 10737 10738 /* Preamble tuning for SSC */ 10739 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 10740 if (ret_val) 10741 goto out; 10742 } 10743 10744 if (hw->phy_type == em_phy_82578) { 10745 /* 10746 * Return registers to default by doing a soft reset then 10747 * writing 0x3140 to the control register. 10748 */ 10749 if (hw->phy_revision < 2) { 10750 em_phy_reset(hw); 10751 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 10752 } 10753 } 10754 10755 if ((hw->revision_id == 2) && 10756 (hw->phy_type == em_phy_82577) && 10757 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10758 /* 10759 * Workaround for OEM (GbE) not operating after reset - 10760 * restart AN (twice) 10761 */ 10762 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 10763 if (ret_val) 10764 goto out; 10765 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 10766 if (ret_val) 10767 goto out; 10768 } 10769 10770 /* Select page 0 */ 10771 ret_val = em_swfw_sync_acquire(hw, swfw); 10772 if (ret_val) 10773 goto out; 10774 10775 hw->phy_addr = 1; 10776 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 10777 em_swfw_sync_release(hw, swfw); 10778 if (ret_val) 10779 goto out; 10780 10781 /* Workaround for link disconnects on a busy hub in half duplex */ 10782 ret_val = em_read_phy_reg(hw, 10783 PHY_REG(BM_PORT_CTRL_PAGE, 17), 10784 &phy_data); 10785 if (ret_val) 10786 goto release; 10787 ret_val = em_write_phy_reg(hw, 10788 PHY_REG(BM_PORT_CTRL_PAGE, 17), 10789 phy_data & 0x00FF); 10790 release: 10791 out: 10792 return ret_val; 10793 } 10794 10795 10796 /*************************************************************************** 10797 * Si workaround 10798 * 10799 * This function works around a Si bug where the link partner can get 10800 * a link up indication before the PHY does. If small packets are sent 10801 * by the link partner they can be placed in the packet buffer without 10802 * being properly accounted for by the PHY and will stall preventing 10803 * further packets from being received. The workaround is to clear the 10804 * packet buffer after the PHY detects link up. 10805 ***************************************************************************/ 10806 int32_t 10807 em_link_stall_workaround_hv(struct em_hw *hw) 10808 { 10809 int32_t ret_val = E1000_SUCCESS; 10810 uint16_t phy_data; 10811 10812 if (hw->phy_type != em_phy_82578) 10813 goto out; 10814 10815 /* Do not apply workaround if in PHY loopback bit 14 set */ 10816 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 10817 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 10818 goto out; 10819 10820 /* check if link is up and at 1Gbps */ 10821 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10822 if (ret_val) 10823 goto out; 10824 10825 phy_data &= BM_CS_STATUS_LINK_UP | 10826 BM_CS_STATUS_RESOLVED | 10827 BM_CS_STATUS_SPEED_MASK; 10828 10829 if (phy_data != (BM_CS_STATUS_LINK_UP | 10830 BM_CS_STATUS_RESOLVED | 10831 BM_CS_STATUS_SPEED_1000)) 10832 goto out; 10833 10834 msec_delay(200); 10835 10836 /* flush the packets in the fifo buffer */ 10837 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10838 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 10839 if (ret_val) 10840 goto out; 10841 10842 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10843 HV_MUX_DATA_CTRL_GEN_TO_MAC); 10844 10845 out: 10846 return ret_val; 10847 } 10848 10849 /**************************************************************************** 10850 * K1 Si workaround 10851 * 10852 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 10853 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 10854 * If link is down, the function will restore the default K1 setting located 10855 * in the NVM. 10856 ****************************************************************************/ 10857 int32_t 10858 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 10859 { 10860 int32_t ret_val; 10861 uint16_t phy_data; 10862 boolean_t k1_enable; 10863 10864 DEBUGFUNC("em_k1_gig_workaround_hv"); 10865 10866 if (hw->mac_type != em_pchlan) 10867 return E1000_SUCCESS; 10868 10869 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 10870 if (ret_val) 10871 return ret_val; 10872 10873 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 10874 10875 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 10876 if (link) { 10877 if (hw->phy_type == em_phy_82578) { 10878 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 10879 &phy_data); 10880 if (ret_val) 10881 return ret_val; 10882 10883 phy_data &= BM_CS_STATUS_LINK_UP | 10884 BM_CS_STATUS_RESOLVED | 10885 BM_CS_STATUS_SPEED_MASK; 10886 10887 if (phy_data == (BM_CS_STATUS_LINK_UP | 10888 BM_CS_STATUS_RESOLVED | 10889 BM_CS_STATUS_SPEED_1000)) 10890 k1_enable = FALSE; 10891 } 10892 10893 if (hw->phy_type == em_phy_82577) { 10894 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 10895 &phy_data); 10896 if (ret_val) 10897 return ret_val; 10898 10899 phy_data &= HV_M_STATUS_LINK_UP | 10900 HV_M_STATUS_AUTONEG_COMPLETE | 10901 HV_M_STATUS_SPEED_MASK; 10902 10903 if (phy_data == (HV_M_STATUS_LINK_UP | 10904 HV_M_STATUS_AUTONEG_COMPLETE | 10905 HV_M_STATUS_SPEED_1000)) 10906 k1_enable = FALSE; 10907 } 10908 10909 /* Link stall fix for link up */ 10910 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10911 0x0100); 10912 if (ret_val) 10913 return ret_val; 10914 10915 } else { 10916 /* Link stall fix for link down */ 10917 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10918 0x4100); 10919 if (ret_val) 10920 return ret_val; 10921 } 10922 10923 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 10924 10925 return ret_val; 10926 } 10927 10928 /* Workaround to set the K1 beacon duration for 82579 parts */ 10929 int32_t 10930 em_k1_workaround_lv(struct em_hw *hw) 10931 { 10932 int32_t ret_val; 10933 uint16_t phy_data; 10934 uint32_t mac_reg; 10935 10936 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10937 if (ret_val) 10938 return ret_val; 10939 10940 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 10941 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 10942 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 10943 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 10944 10945 if (phy_data & HV_M_STATUS_SPEED_1000) 10946 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 10947 else 10948 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 10949 10950 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 10951 } 10952 10953 return E1000_SUCCESS; 10954 } 10955 10956 /** 10957 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 10958 * 10959 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 10960 * preventing further DMA write requests. Workaround the issue by disabling 10961 * the de-assertion of the clock request when in 1Gbps mode. 10962 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 10963 * speeds in order to avoid Tx hangs. 10964 **/ 10965 int32_t 10966 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link) 10967 { 10968 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6); 10969 uint32_t status = E1000_READ_REG(hw, STATUS); 10970 int32_t ret_val = E1000_SUCCESS; 10971 uint16_t reg; 10972 10973 if (link && (status & E1000_STATUS_SPEED_1000)) { 10974 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10975 ®); 10976 if (ret_val) 10977 return ret_val; 10978 10979 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10980 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE); 10981 if (ret_val) 10982 return ret_val; 10983 10984 usec_delay(10); 10985 10986 E1000_WRITE_REG(hw, FEXTNVM6, 10987 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 10988 10989 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10990 reg); 10991 } else { 10992 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 10993 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 10994 10995 if (!link || ((status & E1000_STATUS_SPEED_100) && 10996 (status & E1000_STATUS_FD))) 10997 goto update_fextnvm6; 10998 10999 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®); 11000 if (ret_val) 11001 return ret_val; 11002 11003 /* Clear link status transmit timeout */ 11004 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 11005 11006 if (status & E1000_STATUS_SPEED_100) { 11007 /* Set inband Tx timeout to 5x10us for 100Half */ 11008 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11009 11010 /* Do not extend the K1 entry latency for 100Half */ 11011 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11012 } else { 11013 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 11014 reg |= 50 << 11015 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 11016 11017 /* Extend the K1 entry latency for 10 Mbps */ 11018 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 11019 } 11020 11021 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg); 11022 if (ret_val) 11023 return ret_val; 11024 11025 update_fextnvm6: 11026 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6); 11027 } 11028 11029 return ret_val; 11030 11031 } 11032 11033 11034 /*************************************************************************** 11035 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 11036 * @hw: pointer to the HW structure 11037 * @gate: boolean set to TRUE to gate, FALSE to ungate 11038 * 11039 * Gate/ungate the automatic PHY configuration via hardware; perform 11040 * the configuration via software instead. 11041 ***************************************************************************/ 11042 void 11043 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 11044 { 11045 uint32_t extcnf_ctrl; 11046 11047 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 11048 11049 if (hw->mac_type != em_pch2lan) 11050 return; 11051 11052 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 11053 11054 if (gate) 11055 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11056 else 11057 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 11058 11059 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 11060 } 11061 11062 /*************************************************************************** 11063 * Configure K1 power state 11064 * 11065 * Configure the K1 power state based on the provided parameter. 11066 * Assumes semaphore already acquired. 11067 * 11068 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 11069 ***************************************************************************/ 11070 int32_t 11071 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 11072 { 11073 int32_t ret_val = E1000_SUCCESS; 11074 uint32_t ctrl_reg = 0; 11075 uint32_t ctrl_ext = 0; 11076 uint32_t reg = 0; 11077 uint16_t kmrn_reg = 0; 11078 11079 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11080 &kmrn_reg); 11081 if (ret_val) 11082 goto out; 11083 11084 if (k1_enable) 11085 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 11086 else 11087 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 11088 11089 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 11090 kmrn_reg); 11091 if (ret_val) 11092 goto out; 11093 11094 usec_delay(20); 11095 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 11096 ctrl_reg = E1000_READ_REG(hw, CTRL); 11097 11098 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 11099 reg |= E1000_CTRL_FRCSPD; 11100 E1000_WRITE_REG(hw, CTRL, reg); 11101 11102 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 11103 usec_delay(20); 11104 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 11105 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 11106 usec_delay(20); 11107 11108 out: 11109 return ret_val; 11110 } 11111 11112 /*************************************************************************** 11113 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 11114 * done after every PHY reset. 11115 ***************************************************************************/ 11116 int32_t 11117 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 11118 { 11119 int32_t ret_val = E1000_SUCCESS; 11120 uint16_t swfw; 11121 11122 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 11123 11124 if (hw->mac_type != em_pch2lan) 11125 goto out; 11126 11127 /* Set MDIO slow mode before any other MDIO access */ 11128 ret_val = em_set_mdio_slow_mode_hv(hw); 11129 11130 swfw = E1000_SWFW_PHY0_SM; 11131 ret_val = em_swfw_sync_acquire(hw, swfw); 11132 if (ret_val) 11133 goto out; 11134 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11135 I82579_MSE_THRESHOLD); 11136 if (ret_val) 11137 goto release; 11138 /* set MSE higher to enable link to stay up when noise is high */ 11139 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11140 0x0034); 11141 if (ret_val) 11142 goto release; 11143 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 11144 I82579_MSE_LINK_DOWN); 11145 if (ret_val) 11146 goto release; 11147 /* drop link after 5 times MSE threshold was reached */ 11148 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 11149 0x0005); 11150 release: 11151 em_swfw_sync_release(hw, swfw); 11152 11153 out: 11154 return ret_val; 11155 } 11156 11157 int32_t 11158 em_set_eee_i350(struct em_hw *hw) 11159 { 11160 int32_t ret_val = E1000_SUCCESS; 11161 uint32_t ipcnfg, eeer; 11162 11163 if ((hw->mac_type < em_i350) || 11164 (hw->media_type != em_media_type_copper)) 11165 goto out; 11166 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 11167 eeer = EM_READ_REG(hw, E1000_EEER); 11168 11169 if (hw->eee_enable) { 11170 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11171 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11172 E1000_EEER_LPI_FC); 11173 } else { 11174 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 11175 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 11176 E1000_EEER_LPI_FC); 11177 } 11178 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 11179 EM_WRITE_REG(hw, E1000_EEER, eeer); 11180 EM_READ_REG(hw, E1000_IPCNFG); 11181 EM_READ_REG(hw, E1000_EEER); 11182 out: 11183 return ret_val; 11184 } 11185 11186 /*************************************************************************** 11187 * em_set_eee_pchlan - Enable/disable EEE support 11188 * @hw: pointer to the HW structure 11189 * 11190 * Enable/disable EEE based on setting in dev_spec structure. The bits in 11191 * the LPI Control register will remain set only if/when link is up. 11192 ***************************************************************************/ 11193 int32_t 11194 em_set_eee_pchlan(struct em_hw *hw) 11195 { 11196 int32_t ret_val = E1000_SUCCESS; 11197 uint16_t phy_reg; 11198 11199 DEBUGFUNC("em_set_eee_pchlan"); 11200 11201 if (hw->phy_type != em_phy_82579 && 11202 hw->phy_type != em_phy_i217) 11203 goto out; 11204 11205 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 11206 if (ret_val) 11207 goto out; 11208 11209 if (hw->eee_enable) 11210 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 11211 else 11212 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 11213 11214 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 11215 out: 11216 return ret_val; 11217 } 11218 11219 /** 11220 * em_initialize_M88E1512_phy - Initialize M88E1512 PHY 11221 * @hw: pointer to the HW structure 11222 * 11223 * Initialize Marvell 1512 to work correctly with Avoton. 11224 **/ 11225 int32_t 11226 em_initialize_M88E1512_phy(struct em_hw *hw) 11227 { 11228 int32_t ret_val = E1000_SUCCESS; 11229 11230 DEBUGFUNC("e1000_initialize_M88E1512_phy"); 11231 11232 /* Check if this is correct PHY. */ 11233 if (hw->phy_id != M88E1512_E_PHY_ID) 11234 goto out; 11235 11236 /* Switch to PHY page 0xFF. */ 11237 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF); 11238 if (ret_val) 11239 goto out; 11240 11241 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B); 11242 if (ret_val) 11243 goto out; 11244 11245 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144); 11246 if (ret_val) 11247 goto out; 11248 11249 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28); 11250 if (ret_val) 11251 goto out; 11252 11253 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146); 11254 if (ret_val) 11255 goto out; 11256 11257 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233); 11258 if (ret_val) 11259 goto out; 11260 11261 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D); 11262 if (ret_val) 11263 goto out; 11264 11265 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C); 11266 if (ret_val) 11267 goto out; 11268 11269 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159); 11270 if (ret_val) 11271 goto out; 11272 11273 /* Switch to PHY page 0xFB. */ 11274 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB); 11275 if (ret_val) 11276 goto out; 11277 11278 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D); 11279 if (ret_val) 11280 goto out; 11281 11282 /* Switch to PHY page 0x12. */ 11283 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12); 11284 if (ret_val) 11285 goto out; 11286 11287 /* Change mode to SGMII-to-Copper */ 11288 ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001); 11289 if (ret_val) 11290 goto out; 11291 11292 /* Return the PHY to page 0. */ 11293 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0); 11294 if (ret_val) 11295 goto out; 11296 11297 ret_val = em_phy_hw_reset(hw); 11298 if (ret_val) { 11299 DEBUGOUT("Error committing the PHY changes\n"); 11300 return ret_val; 11301 } 11302 11303 msec_delay(1000); 11304 out: 11305 return ret_val; 11306 } 11307 11308