1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.c,v 1.84 2015/05/12 02:33:39 jsg Exp $ */ 35 /* 36 * if_em_hw.c Shared functions for accessing and configuring the MAC 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/sockio.h> 42 #include <sys/mbuf.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <sys/socket.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 52 #include <netinet/in.h> 53 #include <netinet/if_ether.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pcivar.h> 59 60 #include <dev/pci/if_em_hw.h> 61 #include <dev/pci/if_em_soc.h> 62 63 #define STATIC 64 65 static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t); 66 static void em_swfw_sync_release(struct em_hw *, uint16_t); 67 static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *); 68 static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t); 69 static int32_t em_get_software_semaphore(struct em_hw *); 70 static void em_release_software_semaphore(struct em_hw *); 71 72 static int32_t em_check_downshift(struct em_hw *); 73 static void em_clear_vfta(struct em_hw *); 74 void em_clear_vfta_i350(struct em_hw *); 75 static int32_t em_commit_shadow_ram(struct em_hw *); 76 static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t); 77 static int32_t em_config_fc_after_link_up(struct em_hw *); 78 static int32_t em_match_gig_phy(struct em_hw *); 79 static int32_t em_detect_gig_phy(struct em_hw *); 80 static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t); 81 static int32_t em_get_auto_rd_done(struct em_hw *); 82 static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *); 83 static int32_t em_get_hw_eeprom_semaphore(struct em_hw *); 84 static int32_t em_get_phy_cfg_done(struct em_hw *); 85 static int32_t em_get_software_flag(struct em_hw *); 86 static int32_t em_ich8_cycle_init(struct em_hw *); 87 static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t); 88 static int32_t em_id_led_init(struct em_hw *); 89 static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t, 90 uint32_t); 91 static int32_t em_init_lcd_from_nvm(struct em_hw *); 92 static void em_init_rx_addrs(struct em_hw *); 93 static void em_initialize_hardware_bits(struct em_hw *); 94 static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); 95 static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); 96 static int32_t em_mng_enable_host_if(struct em_hw *); 97 static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, 98 uint16_t *); 99 static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, 100 uint16_t *data); 101 static int32_t em_poll_eerd_eewr_done(struct em_hw *, int); 102 static void em_put_hw_eeprom_semaphore(struct em_hw *); 103 static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *); 104 static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 105 static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t); 106 static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *); 107 static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t, 108 uint16_t *); 109 static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t, 110 uint16_t); 111 static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 112 uint16_t *); 113 static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t, 114 uint16_t *); 115 static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t, 116 uint16_t *); 117 static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *); 118 static void em_release_software_flag(struct em_hw *); 119 static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t); 120 static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t); 121 static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t); 122 static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t); 123 static void em_set_pci_express_master_disable(struct em_hw *); 124 static int32_t em_wait_autoneg(struct em_hw *); 125 static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t); 126 static int32_t em_set_phy_type(struct em_hw *); 127 static void em_phy_init_script(struct em_hw *); 128 static int32_t em_setup_copper_link(struct em_hw *); 129 static int32_t em_setup_fiber_serdes_link(struct em_hw *); 130 static int32_t em_adjust_serdes_amplitude(struct em_hw *); 131 static int32_t em_phy_force_speed_duplex(struct em_hw *); 132 static int32_t em_config_mac_to_phy(struct em_hw *); 133 static void em_raise_mdi_clk(struct em_hw *, uint32_t *); 134 static void em_lower_mdi_clk(struct em_hw *, uint32_t *); 135 static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t); 136 static uint16_t em_shift_in_mdi_bits(struct em_hw *); 137 static int32_t em_phy_reset_dsp(struct em_hw *); 138 static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t, 139 uint16_t *); 140 static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t, 141 uint16_t *); 142 static int32_t em_spi_eeprom_ready(struct em_hw *); 143 static void em_raise_ee_clk(struct em_hw *, uint32_t *); 144 static void em_lower_ee_clk(struct em_hw *, uint32_t *); 145 static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t); 146 static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t); 147 static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *); 148 static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t); 149 static int32_t em_acquire_eeprom(struct em_hw *); 150 static void em_release_eeprom(struct em_hw *); 151 static void em_standby_eeprom(struct em_hw *); 152 static int32_t em_set_vco_speed(struct em_hw *); 153 static int32_t em_polarity_reversal_workaround(struct em_hw *); 154 static int32_t em_set_phy_mode(struct em_hw *); 155 static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *); 156 static uint8_t em_calculate_mng_checksum(char *, uint32_t); 157 static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t); 158 static int32_t em_configure_kmrn_for_1000(struct em_hw *); 159 static int32_t em_set_pciex_completion_timeout(struct em_hw *hw); 160 static int32_t em_set_mdio_slow_mode_hv(struct em_hw *); 161 int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *); 162 int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *); 163 int32_t em_link_stall_workaround_hv(struct em_hw *); 164 int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t); 165 int32_t em_k1_workaround_lv(struct em_hw *); 166 int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t); 167 int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t); 168 void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t); 169 int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t, 170 uint16_t *, boolean_t); 171 int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t, 172 uint16_t *, boolean_t); 173 int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *, 174 boolean_t); 175 int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t); 176 void em_power_up_serdes_link_82575(struct em_hw *); 177 int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *, 178 uint16_t *); 179 int32_t em_set_eee_i350(struct em_hw *); 180 int32_t em_set_eee_pchlan(struct em_hw *); 181 int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); 182 183 184 /* IGP cable length table */ 185 static const uint16_t 186 em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 187 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 188 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 189 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 190 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 191 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 192 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 193 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 194 110, 195 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 196 120}; 197 198 static const uint16_t 199 em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = 200 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 201 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 202 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 203 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 204 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 205 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 206 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 207 121, 124}; 208 209 /****************************************************************************** 210 * Set the phy type member in the hw struct. 211 * 212 * hw - Struct containing variables accessed by shared code 213 *****************************************************************************/ 214 STATIC int32_t 215 em_set_phy_type(struct em_hw *hw) 216 { 217 DEBUGFUNC("em_set_phy_type"); 218 219 if (hw->mac_type == em_undefined) 220 return -E1000_ERR_PHY_TYPE; 221 222 switch (hw->phy_id) { 223 case M88E1000_E_PHY_ID: 224 case M88E1000_I_PHY_ID: 225 case M88E1011_I_PHY_ID: 226 case M88E1111_I_PHY_ID: 227 case M88E1112_E_PHY_ID: 228 case M88E1543_E_PHY_ID: 229 case I210_I_PHY_ID: 230 case I347AT4_E_PHY_ID: 231 hw->phy_type = em_phy_m88; 232 break; 233 case IGP01E1000_I_PHY_ID: 234 if (hw->mac_type == em_82541 || 235 hw->mac_type == em_82541_rev_2 || 236 hw->mac_type == em_82547 || 237 hw->mac_type == em_82547_rev_2) { 238 hw->phy_type = em_phy_igp; 239 break; 240 } 241 case IGP03E1000_E_PHY_ID: 242 case IGP04E1000_E_PHY_ID: 243 hw->phy_type = em_phy_igp_3; 244 break; 245 case IFE_E_PHY_ID: 246 case IFE_PLUS_E_PHY_ID: 247 case IFE_C_E_PHY_ID: 248 hw->phy_type = em_phy_ife; 249 break; 250 case M88E1141_E_PHY_ID: 251 hw->phy_type = em_phy_oem; 252 break; 253 case I82577_E_PHY_ID: 254 hw->phy_type = em_phy_82577; 255 break; 256 case I82578_E_PHY_ID: 257 hw->phy_type = em_phy_82578; 258 break; 259 case I82579_E_PHY_ID: 260 hw->phy_type = em_phy_82579; 261 break; 262 case I217_E_PHY_ID: 263 hw->phy_type = em_phy_i217; 264 break; 265 case I82580_I_PHY_ID: 266 case I350_I_PHY_ID: 267 hw->phy_type = em_phy_82580; 268 break; 269 case BME1000_E_PHY_ID: 270 if (hw->phy_revision == 1) { 271 hw->phy_type = em_phy_bm; 272 break; 273 } 274 /* FALLTHROUGH */ 275 case GG82563_E_PHY_ID: 276 if (hw->mac_type == em_80003es2lan) { 277 hw->phy_type = em_phy_gg82563; 278 break; 279 } 280 /* FALLTHROUGH */ 281 default: 282 /* Should never have loaded on this device */ 283 hw->phy_type = em_phy_undefined; 284 return -E1000_ERR_PHY_TYPE; 285 } 286 287 return E1000_SUCCESS; 288 } 289 290 /****************************************************************************** 291 * IGP phy init script - initializes the GbE PHY 292 * 293 * hw - Struct containing variables accessed by shared code 294 *****************************************************************************/ 295 static void 296 em_phy_init_script(struct em_hw *hw) 297 { 298 uint16_t phy_saved_data; 299 DEBUGFUNC("em_phy_init_script"); 300 301 if (hw->phy_init_script) { 302 msec_delay(20); 303 /* 304 * Save off the current value of register 0x2F5B to be 305 * restored at the end of this routine. 306 */ 307 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 308 309 /* Disabled the PHY transmitter */ 310 em_write_phy_reg(hw, 0x2F5B, 0x0003); 311 msec_delay(20); 312 em_write_phy_reg(hw, 0x0000, 0x0140); 313 msec_delay(5); 314 315 switch (hw->mac_type) { 316 case em_82541: 317 case em_82547: 318 em_write_phy_reg(hw, 0x1F95, 0x0001); 319 em_write_phy_reg(hw, 0x1F71, 0xBD21); 320 em_write_phy_reg(hw, 0x1F79, 0x0018); 321 em_write_phy_reg(hw, 0x1F30, 0x1600); 322 em_write_phy_reg(hw, 0x1F31, 0x0014); 323 em_write_phy_reg(hw, 0x1F32, 0x161C); 324 em_write_phy_reg(hw, 0x1F94, 0x0003); 325 em_write_phy_reg(hw, 0x1F96, 0x003F); 326 em_write_phy_reg(hw, 0x2010, 0x0008); 327 break; 328 case em_82541_rev_2: 329 case em_82547_rev_2: 330 em_write_phy_reg(hw, 0x1F73, 0x0099); 331 break; 332 default: 333 break; 334 } 335 336 em_write_phy_reg(hw, 0x0000, 0x3300); 337 msec_delay(20); 338 339 /* Now enable the transmitter */ 340 em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 341 342 if (hw->mac_type == em_82547) { 343 uint16_t fused, fine, coarse; 344 /* Move to analog registers page */ 345 em_read_phy_reg(hw, 346 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); 347 348 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 349 em_read_phy_reg(hw, 350 IGP01E1000_ANALOG_FUSE_STATUS, &fused); 351 352 fine = fused & 353 IGP01E1000_ANALOG_FUSE_FINE_MASK; 354 coarse = fused & 355 IGP01E1000_ANALOG_FUSE_COARSE_MASK; 356 357 if (coarse > 358 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 359 coarse -= 360 IGP01E1000_ANALOG_FUSE_COARSE_10; 361 fine -= 362 IGP01E1000_ANALOG_FUSE_FINE_1; 363 } else if (coarse == 364 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 365 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 366 367 fused = (fused & 368 IGP01E1000_ANALOG_FUSE_POLY_MASK) | 369 (fine & 370 IGP01E1000_ANALOG_FUSE_FINE_MASK) | 371 (coarse & 372 IGP01E1000_ANALOG_FUSE_COARSE_MASK); 373 374 em_write_phy_reg(hw, 375 IGP01E1000_ANALOG_FUSE_CONTROL, 376 fused); 377 378 em_write_phy_reg(hw, 379 IGP01E1000_ANALOG_FUSE_BYPASS, 380 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 381 } 382 } 383 } 384 } 385 386 /****************************************************************************** 387 * Set the mac type member in the hw struct. 388 * 389 * hw - Struct containing variables accessed by shared code 390 *****************************************************************************/ 391 int32_t 392 em_set_mac_type(struct em_hw *hw) 393 { 394 DEBUGFUNC("em_set_mac_type"); 395 396 switch (hw->device_id) { 397 case E1000_DEV_ID_82542: 398 switch (hw->revision_id) { 399 case E1000_82542_2_0_REV_ID: 400 hw->mac_type = em_82542_rev2_0; 401 break; 402 case E1000_82542_2_1_REV_ID: 403 hw->mac_type = em_82542_rev2_1; 404 break; 405 default: 406 /* Invalid 82542 revision ID */ 407 return -E1000_ERR_MAC_TYPE; 408 } 409 break; 410 case E1000_DEV_ID_82543GC_FIBER: 411 case E1000_DEV_ID_82543GC_COPPER: 412 hw->mac_type = em_82543; 413 break; 414 case E1000_DEV_ID_82544EI_COPPER: 415 case E1000_DEV_ID_82544EI_FIBER: 416 case E1000_DEV_ID_82544GC_COPPER: 417 case E1000_DEV_ID_82544GC_LOM: 418 hw->mac_type = em_82544; 419 break; 420 case E1000_DEV_ID_82540EM: 421 case E1000_DEV_ID_82540EM_LOM: 422 case E1000_DEV_ID_82540EP: 423 case E1000_DEV_ID_82540EP_LOM: 424 case E1000_DEV_ID_82540EP_LP: 425 hw->mac_type = em_82540; 426 break; 427 case E1000_DEV_ID_82545EM_COPPER: 428 case E1000_DEV_ID_82545EM_FIBER: 429 hw->mac_type = em_82545; 430 break; 431 case E1000_DEV_ID_82545GM_COPPER: 432 case E1000_DEV_ID_82545GM_FIBER: 433 case E1000_DEV_ID_82545GM_SERDES: 434 hw->mac_type = em_82545_rev_3; 435 break; 436 case E1000_DEV_ID_82546EB_COPPER: 437 case E1000_DEV_ID_82546EB_FIBER: 438 case E1000_DEV_ID_82546EB_QUAD_COPPER: 439 hw->mac_type = em_82546; 440 break; 441 case E1000_DEV_ID_82546GB_COPPER: 442 case E1000_DEV_ID_82546GB_FIBER: 443 case E1000_DEV_ID_82546GB_SERDES: 444 case E1000_DEV_ID_82546GB_PCIE: 445 case E1000_DEV_ID_82546GB_QUAD_COPPER: 446 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 447 case E1000_DEV_ID_82546GB_2: 448 hw->mac_type = em_82546_rev_3; 449 break; 450 case E1000_DEV_ID_82541EI: 451 case E1000_DEV_ID_82541EI_MOBILE: 452 case E1000_DEV_ID_82541ER_LOM: 453 hw->mac_type = em_82541; 454 break; 455 case E1000_DEV_ID_82541ER: 456 case E1000_DEV_ID_82541GI: 457 case E1000_DEV_ID_82541GI_LF: 458 case E1000_DEV_ID_82541GI_MOBILE: 459 hw->mac_type = em_82541_rev_2; 460 break; 461 case E1000_DEV_ID_82547EI: 462 case E1000_DEV_ID_82547EI_MOBILE: 463 hw->mac_type = em_82547; 464 break; 465 case E1000_DEV_ID_82547GI: 466 hw->mac_type = em_82547_rev_2; 467 break; 468 case E1000_DEV_ID_82571EB_AF: 469 case E1000_DEV_ID_82571EB_AT: 470 case E1000_DEV_ID_82571EB_COPPER: 471 case E1000_DEV_ID_82571EB_FIBER: 472 case E1000_DEV_ID_82571EB_SERDES: 473 case E1000_DEV_ID_82571EB_QUAD_COPPER: 474 case E1000_DEV_ID_82571EB_QUAD_FIBER: 475 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 476 case E1000_DEV_ID_82571EB_SERDES_DUAL: 477 case E1000_DEV_ID_82571EB_SERDES_QUAD: 478 case E1000_DEV_ID_82571PT_QUAD_COPPER: 479 hw->mac_type = em_82571; 480 break; 481 case E1000_DEV_ID_82572EI_COPPER: 482 case E1000_DEV_ID_82572EI_FIBER: 483 case E1000_DEV_ID_82572EI_SERDES: 484 case E1000_DEV_ID_82572EI: 485 hw->mac_type = em_82572; 486 break; 487 case E1000_DEV_ID_82573E: 488 case E1000_DEV_ID_82573E_IAMT: 489 case E1000_DEV_ID_82573E_PM: 490 case E1000_DEV_ID_82573L: 491 case E1000_DEV_ID_82573L_PL_1: 492 case E1000_DEV_ID_82573L_PL_2: 493 case E1000_DEV_ID_82573V_PM: 494 hw->mac_type = em_82573; 495 break; 496 case E1000_DEV_ID_82574L: 497 case E1000_DEV_ID_82574LA: 498 case E1000_DEV_ID_82583V: 499 hw->mac_type = em_82574; 500 break; 501 case E1000_DEV_ID_82575EB_PT: 502 case E1000_DEV_ID_82575EB_PF: 503 case E1000_DEV_ID_82575GB_QP: 504 case E1000_DEV_ID_82575GB_QP_PM: 505 case E1000_DEV_ID_82576: 506 case E1000_DEV_ID_82576_FIBER: 507 case E1000_DEV_ID_82576_SERDES: 508 case E1000_DEV_ID_82576_QUAD_COPPER: 509 case E1000_DEV_ID_82576_QUAD_CU_ET2: 510 case E1000_DEV_ID_82576_NS: 511 case E1000_DEV_ID_82576_NS_SERDES: 512 case E1000_DEV_ID_82576_SERDES_QUAD: 513 hw->mac_type = em_82575; 514 hw->initialize_hw_bits_disable = 1; 515 break; 516 case E1000_DEV_ID_82580_COPPER: 517 case E1000_DEV_ID_82580_FIBER: 518 case E1000_DEV_ID_82580_QUAD_FIBER: 519 case E1000_DEV_ID_82580_SERDES: 520 case E1000_DEV_ID_82580_SGMII: 521 case E1000_DEV_ID_82580_COPPER_DUAL: 522 case E1000_DEV_ID_DH89XXCC_SGMII: 523 case E1000_DEV_ID_DH89XXCC_SERDES: 524 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 525 case E1000_DEV_ID_DH89XXCC_SFP: 526 hw->mac_type = em_82580; 527 hw->initialize_hw_bits_disable = 1; 528 break; 529 case E1000_DEV_ID_I210_COPPER: 530 case E1000_DEV_ID_I210_FIBER: 531 case E1000_DEV_ID_I210_SERDES: 532 case E1000_DEV_ID_I210_SGMII: 533 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 534 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 535 case E1000_DEV_ID_I211_COPPER: 536 hw->mac_type = em_i210; 537 hw->initialize_hw_bits_disable = 1; 538 hw->eee_enable = 1; 539 break; 540 case E1000_DEV_ID_I350_COPPER: 541 case E1000_DEV_ID_I350_FIBER: 542 case E1000_DEV_ID_I350_SERDES: 543 case E1000_DEV_ID_I350_SGMII: 544 case E1000_DEV_ID_I350_DA4: 545 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 546 case E1000_DEV_ID_I354_SGMII: 547 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 548 hw->mac_type = em_i350; 549 hw->initialize_hw_bits_disable = 1; 550 hw->eee_enable = 1; 551 break; 552 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: 553 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: 554 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: 555 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 556 hw->mac_type = em_80003es2lan; 557 break; 558 case E1000_DEV_ID_ICH8_IFE: 559 case E1000_DEV_ID_ICH8_IFE_G: 560 case E1000_DEV_ID_ICH8_IFE_GT: 561 case E1000_DEV_ID_ICH8_IGP_AMT: 562 case E1000_DEV_ID_ICH8_IGP_C: 563 case E1000_DEV_ID_ICH8_IGP_M: 564 case E1000_DEV_ID_ICH8_IGP_M_AMT: 565 case E1000_DEV_ID_ICH8_82567V_3: 566 hw->mac_type = em_ich8lan; 567 break; 568 case E1000_DEV_ID_ICH9_BM: 569 case E1000_DEV_ID_ICH9_IFE: 570 case E1000_DEV_ID_ICH9_IFE_G: 571 case E1000_DEV_ID_ICH9_IFE_GT: 572 case E1000_DEV_ID_ICH9_IGP_AMT: 573 case E1000_DEV_ID_ICH9_IGP_C: 574 case E1000_DEV_ID_ICH9_IGP_M: 575 case E1000_DEV_ID_ICH9_IGP_M_AMT: 576 case E1000_DEV_ID_ICH9_IGP_M_V: 577 case E1000_DEV_ID_ICH10_R_BM_LF: 578 case E1000_DEV_ID_ICH10_R_BM_LM: 579 case E1000_DEV_ID_ICH10_R_BM_V: 580 hw->mac_type = em_ich9lan; 581 break; 582 case E1000_DEV_ID_ICH10_D_BM_LF: 583 case E1000_DEV_ID_ICH10_D_BM_LM: 584 hw->mac_type = em_ich10lan; 585 break; 586 case E1000_DEV_ID_PCH_M_HV_LC: 587 case E1000_DEV_ID_PCH_M_HV_LM: 588 case E1000_DEV_ID_PCH_D_HV_DC: 589 case E1000_DEV_ID_PCH_D_HV_DM: 590 hw->mac_type = em_pchlan; 591 hw->eee_enable = 1; 592 break; 593 case E1000_DEV_ID_PCH2_LV_LM: 594 case E1000_DEV_ID_PCH2_LV_V: 595 hw->mac_type = em_pch2lan; 596 break; 597 case E1000_DEV_ID_PCH_LPT_I217_LM: 598 case E1000_DEV_ID_PCH_LPT_I217_V: 599 case E1000_DEV_ID_PCH_LPTLP_I218_LM: 600 case E1000_DEV_ID_PCH_LPTLP_I218_V: 601 case E1000_DEV_ID_PCH_I218_LM2: 602 case E1000_DEV_ID_PCH_I218_V2: 603 case E1000_DEV_ID_PCH_I218_LM3: 604 case E1000_DEV_ID_PCH_I218_V3: 605 hw->mac_type = em_pch_lpt; 606 break; 607 case E1000_DEV_ID_EP80579_LAN_1: 608 hw->mac_type = em_icp_xxxx; 609 hw->icp_xxxx_port_num = 0; 610 break; 611 case E1000_DEV_ID_EP80579_LAN_2: 612 hw->mac_type = em_icp_xxxx; 613 hw->icp_xxxx_port_num = 1; 614 break; 615 case E1000_DEV_ID_EP80579_LAN_3: 616 hw->mac_type = em_icp_xxxx; 617 hw->icp_xxxx_port_num = 2; 618 break; 619 default: 620 /* Should never have loaded on this device */ 621 return -E1000_ERR_MAC_TYPE; 622 } 623 624 switch (hw->mac_type) { 625 case em_ich8lan: 626 case em_ich9lan: 627 case em_ich10lan: 628 case em_pchlan: 629 case em_pch2lan: 630 case em_pch_lpt: 631 hw->swfwhw_semaphore_present = TRUE; 632 hw->asf_firmware_present = TRUE; 633 break; 634 case em_80003es2lan: 635 case em_82575: 636 case em_82580: 637 case em_i210: 638 case em_i350: 639 hw->swfw_sync_present = TRUE; 640 /* FALLTHROUGH */ 641 case em_82571: 642 case em_82572: 643 case em_82573: 644 case em_82574: 645 hw->eeprom_semaphore_present = TRUE; 646 /* FALLTHROUGH */ 647 case em_82541: 648 case em_82547: 649 case em_82541_rev_2: 650 case em_82547_rev_2: 651 hw->asf_firmware_present = TRUE; 652 break; 653 default: 654 break; 655 } 656 657 return E1000_SUCCESS; 658 } 659 /***************************************************************************** 660 * Set media type and TBI compatibility. 661 * 662 * hw - Struct containing variables accessed by shared code 663 * **************************************************************************/ 664 void 665 em_set_media_type(struct em_hw *hw) 666 { 667 uint32_t status, ctrl_ext; 668 DEBUGFUNC("em_set_media_type"); 669 670 if (hw->mac_type != em_82543) { 671 /* tbi_compatibility is only valid on 82543 */ 672 hw->tbi_compatibility_en = FALSE; 673 } 674 675 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 676 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 677 hw->media_type = em_media_type_copper; 678 679 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 680 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 681 case E1000_CTRL_EXT_LINK_MODE_SGMII: 682 ctrl_ext |= E1000_CTRL_I2C_ENA; 683 break; 684 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 685 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 686 hw->media_type = em_media_type_internal_serdes; 687 ctrl_ext |= E1000_CTRL_I2C_ENA; 688 break; 689 default: 690 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 691 break; 692 } 693 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 694 return; 695 } 696 697 switch (hw->device_id) { 698 case E1000_DEV_ID_82545GM_SERDES: 699 case E1000_DEV_ID_82546GB_SERDES: 700 case E1000_DEV_ID_82571EB_SERDES: 701 case E1000_DEV_ID_82571EB_SERDES_DUAL: 702 case E1000_DEV_ID_82571EB_SERDES_QUAD: 703 case E1000_DEV_ID_82572EI_SERDES: 704 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 705 hw->media_type = em_media_type_internal_serdes; 706 break; 707 case E1000_DEV_ID_EP80579_LAN_1: 708 case E1000_DEV_ID_EP80579_LAN_2: 709 case E1000_DEV_ID_EP80579_LAN_3: 710 hw->media_type = em_media_type_oem; 711 break; 712 default: 713 switch (hw->mac_type) { 714 case em_82542_rev2_0: 715 case em_82542_rev2_1: 716 hw->media_type = em_media_type_fiber; 717 break; 718 case em_ich8lan: 719 case em_ich9lan: 720 case em_ich10lan: 721 case em_pchlan: 722 case em_pch2lan: 723 case em_pch_lpt: 724 case em_82573: 725 case em_82574: 726 /* 727 * The STATUS_TBIMODE bit is reserved or reused for 728 * the this device. 729 */ 730 hw->media_type = em_media_type_copper; 731 break; 732 default: 733 status = E1000_READ_REG(hw, STATUS); 734 if (status & E1000_STATUS_TBIMODE) { 735 hw->media_type = em_media_type_fiber; 736 /* tbi_compatibility not valid on fiber */ 737 hw->tbi_compatibility_en = FALSE; 738 } else { 739 hw->media_type = em_media_type_copper; 740 } 741 break; 742 } 743 } 744 } 745 /****************************************************************************** 746 * Reset the transmit and receive units; mask and clear all interrupts. 747 * 748 * hw - Struct containing variables accessed by shared code 749 *****************************************************************************/ 750 int32_t 751 em_reset_hw(struct em_hw *hw) 752 { 753 uint32_t ctrl; 754 uint32_t ctrl_ext; 755 uint32_t icr; 756 uint32_t manc; 757 uint32_t led_ctrl; 758 uint32_t timeout; 759 uint32_t extcnf_ctrl; 760 int32_t ret_val; 761 DEBUGFUNC("em_reset_hw"); 762 763 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ 764 if (hw->mac_type == em_82542_rev2_0) { 765 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 766 em_pci_clear_mwi(hw); 767 } 768 if (hw->bus_type == em_bus_type_pci_express) { 769 /* 770 * Prevent the PCI-E bus from sticking if there is no TLP 771 * connection on the last TLP read/write transaction when MAC 772 * is reset. 773 */ 774 if (em_disable_pciex_master(hw) != E1000_SUCCESS) { 775 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 776 } 777 } 778 779 /* Set the completion timeout for 82575 chips */ 780 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 || 781 hw->mac_type == em_i210 || hw->mac_type == em_i350) { 782 ret_val = em_set_pciex_completion_timeout(hw); 783 if (ret_val) { 784 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 785 } 786 } 787 788 /* Clear interrupt mask to stop board from generating interrupts */ 789 DEBUGOUT("Masking off all interrupts\n"); 790 E1000_WRITE_REG(hw, IMC, 0xffffffff); 791 /* 792 * Disable the Transmit and Receive units. Then delay to allow any 793 * pending transactions to complete before we hit the MAC with the 794 * global reset. 795 */ 796 E1000_WRITE_REG(hw, RCTL, 0); 797 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); 798 E1000_WRITE_FLUSH(hw); 799 /* 800 * The tbi_compatibility_on Flag must be cleared when Rctl is 801 * cleared. 802 */ 803 hw->tbi_compatibility_on = FALSE; 804 /* 805 * Delay to allow any outstanding PCI transactions to complete before 806 * resetting the device 807 */ 808 msec_delay(10); 809 810 ctrl = E1000_READ_REG(hw, CTRL); 811 812 /* Must reset the PHY before resetting the MAC */ 813 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 814 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); 815 msec_delay(5); 816 } 817 /* 818 * Must acquire the MDIO ownership before MAC reset. Ownership 819 * defaults to firmware after a reset. 820 */ 821 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 822 timeout = 10; 823 824 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 825 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 826 827 do { 828 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 829 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 830 831 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 832 break; 833 else 834 extcnf_ctrl |= 835 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 836 837 msec_delay(2); 838 timeout--; 839 } while (timeout); 840 } 841 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 842 if (hw->mac_type == em_ich8lan) { 843 /* Set Tx and Rx buffer allocation to 8k apiece. */ 844 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); 845 /* Set Packet Buffer Size to 16k. */ 846 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); 847 } 848 /* 849 * Issue a global reset to the MAC. This will reset the chip's 850 * transmit, receive, DMA, and link units. It will not effect the 851 * current PCI configuration. The global reset bit is self- 852 * clearing, and should clear within a microsecond. 853 */ 854 DEBUGOUT("Issuing a global reset to MAC\n"); 855 856 switch (hw->mac_type) { 857 case em_82544: 858 case em_82540: 859 case em_82545: 860 case em_82546: 861 case em_82541: 862 case em_82541_rev_2: 863 /* 864 * These controllers can't ack the 64-bit write when issuing 865 * the reset, so use IO-mapping as a workaround to issue the 866 * reset 867 */ 868 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); 869 break; 870 case em_82545_rev_3: 871 case em_82546_rev_3: 872 /* Reset is performed on a shadow of the control register */ 873 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); 874 break; 875 case em_ich8lan: 876 case em_ich9lan: 877 case em_ich10lan: 878 case em_pchlan: 879 case em_pch2lan: 880 case em_pch_lpt: 881 if (!hw->phy_reset_disable && 882 em_check_phy_reset_block(hw) == E1000_SUCCESS) { 883 /* 884 * PHY HW reset requires MAC CORE reset at the same 885 * time to make sure the interface between MAC and 886 * the external PHY is reset. 887 */ 888 ctrl |= E1000_CTRL_PHY_RST; 889 /* 890 * Gate automatic PHY configuration by hardware on 891 * non-managed 82579 892 */ 893 if ((hw->mac_type == em_pch2lan) && 894 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 895 em_gate_hw_phy_config_ich8lan(hw, TRUE); 896 } 897 } 898 em_get_software_flag(hw); 899 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 900 msec_delay(5); 901 902 /* Ungate automatic PHY configuration on non-managed 82579 */ 903 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable && 904 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 905 msec_delay(10); 906 em_gate_hw_phy_config_ich8lan(hw, FALSE); 907 } 908 break; 909 default: 910 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); 911 break; 912 } 913 914 if (em_check_phy_reset_block(hw) == E1000_SUCCESS) { 915 if (hw->mac_type == em_pchlan) { 916 ret_val = em_hv_phy_workarounds_ich8lan(hw); 917 if (ret_val) 918 return ret_val; 919 } 920 else if (hw->mac_type == em_pch2lan) { 921 ret_val = em_lv_phy_workarounds_ich8lan(hw); 922 if (ret_val) 923 return ret_val; 924 } 925 } 926 927 /* 928 * After MAC reset, force reload of EEPROM to restore power-on 929 * settings to device. Later controllers reload the EEPROM 930 * automatically, so just wait for reload to complete. 931 */ 932 switch (hw->mac_type) { 933 case em_82542_rev2_0: 934 case em_82542_rev2_1: 935 case em_82543: 936 case em_82544: 937 /* Wait for reset to complete */ 938 usec_delay(10); 939 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 940 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 941 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 942 E1000_WRITE_FLUSH(hw); 943 /* Wait for EEPROM reload */ 944 msec_delay(2); 945 break; 946 case em_82541: 947 case em_82541_rev_2: 948 case em_82547: 949 case em_82547_rev_2: 950 /* Wait for EEPROM reload */ 951 msec_delay(20); 952 break; 953 case em_82573: 954 case em_82574: 955 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 956 usec_delay(10); 957 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 958 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 959 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 960 E1000_WRITE_FLUSH(hw); 961 } 962 /* FALLTHROUGH */ 963 964 /* Auto read done will delay 5ms or poll based on mac type */ 965 ret_val = em_get_auto_rd_done(hw); 966 if (ret_val) 967 return ret_val; 968 break; 969 default: 970 /* Wait for EEPROM reload (it happens automatically) */ 971 msec_delay(5); 972 break; 973 } 974 975 /* Disable HW ARPs on ASF enabled adapters */ 976 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 && 977 hw->mac_type != em_icp_xxxx) { 978 manc = E1000_READ_REG(hw, MANC); 979 manc &= ~(E1000_MANC_ARP_EN); 980 E1000_WRITE_REG(hw, MANC, manc); 981 } 982 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 983 em_phy_init_script(hw); 984 985 /* Configure activity LED after PHY reset */ 986 led_ctrl = E1000_READ_REG(hw, LEDCTL); 987 led_ctrl &= IGP_ACTIVITY_LED_MASK; 988 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 989 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 990 } 991 992 /* 993 * For PCH, this write will make sure that any noise 994 * will be detected as a CRC error and be dropped rather than show up 995 * as a bad packet to the DMA engine. 996 */ 997 if (hw->mac_type == em_pchlan) 998 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); 999 1000 /* Clear interrupt mask to stop board from generating interrupts */ 1001 DEBUGOUT("Masking off all interrupts\n"); 1002 E1000_WRITE_REG(hw, IMC, 0xffffffff); 1003 1004 /* Clear any pending interrupt events. */ 1005 icr = E1000_READ_REG(hw, ICR); 1006 1007 /* If MWI was previously enabled, reenable it. */ 1008 if (hw->mac_type == em_82542_rev2_0) { 1009 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1010 em_pci_set_mwi(hw); 1011 } 1012 if (IS_ICH8(hw->mac_type)) { 1013 uint32_t kab = E1000_READ_REG(hw, KABGTXD); 1014 kab |= E1000_KABGTXD_BGSQLBIAS; 1015 E1000_WRITE_REG(hw, KABGTXD, kab); 1016 } 1017 1018 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 1019 uint32_t mdicnfg; 1020 uint16_t nvm_data; 1021 1022 /* clear global device reset status bit */ 1023 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET); 1024 1025 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A + 1026 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func), 1, 1027 &nvm_data); 1028 1029 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG); 1030 if (nvm_data & NVM_WORD24_EXT_MDIO) 1031 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1032 if (nvm_data & NVM_WORD24_COM_MDIO) 1033 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1034 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 1035 } 1036 1037 if (hw->mac_type == em_i210 || hw->mac_type == em_i350) 1038 em_set_eee_i350(hw); 1039 1040 return E1000_SUCCESS; 1041 } 1042 1043 /****************************************************************************** 1044 * 1045 * Initialize a number of hardware-dependent bits 1046 * 1047 * hw: Struct containing variables accessed by shared code 1048 * 1049 *****************************************************************************/ 1050 STATIC void 1051 em_initialize_hardware_bits(struct em_hw *hw) 1052 { 1053 DEBUGFUNC("em_initialize_hardware_bits"); 1054 1055 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) { 1056 /* Settings common to all silicon */ 1057 uint32_t reg_ctrl, reg_ctrl_ext; 1058 uint32_t reg_tarc0, reg_tarc1; 1059 uint32_t reg_tctl; 1060 uint32_t reg_txdctl, reg_txdctl1; 1061 reg_tarc0 = E1000_READ_REG(hw, TARC0); 1062 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and 1063 * 27 */ 1064 1065 reg_txdctl = E1000_READ_REG(hw, TXDCTL); 1066 reg_txdctl |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1067 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); 1068 1069 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); 1070 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; /* Set bit 22 */ 1071 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); 1072 1073 switch (hw->mac_type) { 1074 case em_82571: 1075 case em_82572: 1076 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1077 reg_tctl = E1000_READ_REG(hw, TCTL); 1078 1079 /* Set the phy Tx compatible mode bits */ 1080 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */ 1081 1082 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */ 1083 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ 1084 1085 if (reg_tctl & E1000_TCTL_MULR) 1086 /* Clear bit 28 if MULR is 1b */ 1087 reg_tarc1 &= ~0x10000000; 1088 else 1089 /* Set bit 28 if MULR is 0b */ 1090 reg_tarc1 |= 0x10000000; 1091 1092 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1093 break; 1094 case em_82573: 1095 case em_82574: 1096 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1097 reg_ctrl = E1000_READ_REG(hw, CTRL); 1098 1099 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */ 1100 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1101 reg_ctrl &= ~0x20000000; /* Clear bit 29 */ 1102 1103 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1104 E1000_WRITE_REG(hw, CTRL, reg_ctrl); 1105 break; 1106 case em_80003es2lan: 1107 if ((hw->media_type == em_media_type_fiber) || 1108 (hw->media_type == em_media_type_internal_serdes)) { 1109 /* Clear bit 20 */ 1110 reg_tarc0 &= ~0x00100000; 1111 } 1112 reg_tctl = E1000_READ_REG(hw, TCTL); 1113 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1114 if (reg_tctl & E1000_TCTL_MULR) 1115 /* Clear bit 28 if MULR is 1b */ 1116 reg_tarc1 &= ~0x10000000; 1117 else 1118 /* Set bit 28 if MULR is 0b */ 1119 reg_tarc1 |= 0x10000000; 1120 1121 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1122 break; 1123 case em_ich8lan: 1124 case em_ich9lan: 1125 case em_ich10lan: 1126 case em_pchlan: 1127 case em_pch2lan: 1128 case em_pch_lpt: 1129 if (hw->mac_type == em_ich8lan) 1130 /* Set TARC0 bits 29 and 28 */ 1131 reg_tarc0 |= 0x30000000; 1132 1133 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1134 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */ 1135 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 1136 if (hw->mac_type >= em_pchlan) 1137 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN; 1138 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); 1139 1140 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23, 1141 * 24, 26, 27 */ 1142 1143 reg_tarc1 = E1000_READ_REG(hw, TARC1); 1144 reg_tctl = E1000_READ_REG(hw, TCTL); 1145 1146 if (reg_tctl & E1000_TCTL_MULR) 1147 /* Clear bit 28 if MULR is 1b */ 1148 reg_tarc1 &= ~0x10000000; 1149 else 1150 /* Set bit 28 if MULR is 0b */ 1151 reg_tarc1 |= 0x10000000; 1152 1153 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and 1154 * 30 */ 1155 1156 E1000_WRITE_REG(hw, TARC1, reg_tarc1); 1157 break; 1158 default: 1159 break; 1160 } 1161 1162 E1000_WRITE_REG(hw, TARC0, reg_tarc0); 1163 } 1164 } 1165 1166 /****************************************************************************** 1167 * Performs basic configuration of the adapter. 1168 * 1169 * hw - Struct containing variables accessed by shared code 1170 * 1171 * Assumes that the controller has previously been reset and is in a 1172 * post-reset uninitialized state. Initializes the receive address registers, 1173 * multicast table, and VLAN filter table. Calls routines to setup link 1174 * configuration and flow control settings. Clears all on-chip counters. Leaves 1175 * the transmit and receive units disabled and uninitialized. 1176 *****************************************************************************/ 1177 int32_t 1178 em_init_hw(struct em_hw *hw) 1179 { 1180 uint32_t ctrl; 1181 uint32_t i; 1182 int32_t ret_val; 1183 uint16_t pcix_cmd_word; 1184 uint16_t pcix_stat_hi_word; 1185 uint16_t cmd_mmrbc; 1186 uint16_t stat_mmrbc; 1187 uint32_t mta_size; 1188 uint32_t reg_data; 1189 uint32_t ctrl_ext; 1190 uint32_t snoop; 1191 uint32_t fwsm; 1192 DEBUGFUNC("em_init_hw"); 1193 1194 /* force full DMA clock frequency for ICH8 */ 1195 if (hw->mac_type == em_ich8lan) { 1196 reg_data = E1000_READ_REG(hw, STATUS); 1197 reg_data &= ~0x80000000; 1198 E1000_WRITE_REG(hw, STATUS, reg_data); 1199 } 1200 1201 if (hw->mac_type == em_pchlan || 1202 hw->mac_type == em_pch2lan || 1203 hw->mac_type == em_pch_lpt) { 1204 /* 1205 * The MAC-PHY interconnect may still be in SMBus mode 1206 * after Sx->S0. Toggle the LANPHYPC Value bit to force 1207 * the interconnect to PCIe mode, but only if there is no 1208 * firmware present otherwise firmware will have done it. 1209 */ 1210 fwsm = E1000_READ_REG(hw, FWSM); 1211 if ((fwsm & E1000_FWSM_FW_VALID) == 0) { 1212 ctrl = E1000_READ_REG(hw, CTRL); 1213 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE; 1214 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE; 1215 E1000_WRITE_REG(hw, CTRL, ctrl); 1216 usec_delay(10); 1217 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 1218 E1000_WRITE_REG(hw, CTRL, ctrl); 1219 msec_delay(50); 1220 } 1221 1222 /* Gate automatic PHY configuration on non-managed 82579 */ 1223 if (hw->mac_type == em_pch2lan) 1224 em_gate_hw_phy_config_ich8lan(hw, TRUE); 1225 1226 /* 1227 * Reset the PHY before any acccess to it. Doing so, 1228 * ensures that the PHY is in a known good state before 1229 * we read/write PHY registers. The generic reset is 1230 * sufficient here, because we haven't determined 1231 * the PHY type yet. 1232 */ 1233 em_phy_reset(hw); 1234 1235 /* Ungate automatic PHY configuration on non-managed 82579 */ 1236 if (hw->mac_type == em_pch2lan && 1237 (fwsm & E1000_FWSM_FW_VALID) == 0) 1238 em_gate_hw_phy_config_ich8lan(hw, FALSE); 1239 1240 /* Set MDIO slow mode before any other MDIO access */ 1241 ret_val = em_set_mdio_slow_mode_hv(hw); 1242 if (ret_val) 1243 return ret_val; 1244 } 1245 1246 /* Initialize Identification LED */ 1247 ret_val = em_id_led_init(hw); 1248 if (ret_val) { 1249 DEBUGOUT("Error Initializing Identification LED\n"); 1250 return ret_val; 1251 } 1252 /* Set the media type and TBI compatibility */ 1253 em_set_media_type(hw); 1254 1255 /* Must be called after em_set_media_type because media_type is used */ 1256 em_initialize_hardware_bits(hw); 1257 1258 /* Disabling VLAN filtering. */ 1259 DEBUGOUT("Initializing the IEEE VLAN\n"); 1260 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */ 1261 if (!IS_ICH8(hw->mac_type)) { 1262 if (hw->mac_type < em_82545_rev_3) 1263 E1000_WRITE_REG(hw, VET, 0); 1264 if (hw->mac_type == em_i350) 1265 em_clear_vfta_i350(hw); 1266 else 1267 em_clear_vfta(hw); 1268 } 1269 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 1270 if (hw->mac_type == em_82542_rev2_0) { 1271 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 1272 em_pci_clear_mwi(hw); 1273 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1274 E1000_WRITE_FLUSH(hw); 1275 msec_delay(5); 1276 } 1277 /* 1278 * Setup the receive address. This involves initializing all of the 1279 * Receive Address Registers (RARs 0 - 15). 1280 */ 1281 em_init_rx_addrs(hw); 1282 1283 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/ 1284 if (hw->mac_type == em_82542_rev2_0) { 1285 E1000_WRITE_REG(hw, RCTL, 0); 1286 E1000_WRITE_FLUSH(hw); 1287 msec_delay(1); 1288 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1289 em_pci_set_mwi(hw); 1290 } 1291 /* Zero out the Multicast HASH table */ 1292 DEBUGOUT("Zeroing the MTA\n"); 1293 mta_size = E1000_MC_TBL_SIZE; 1294 if (IS_ICH8(hw->mac_type)) 1295 mta_size = E1000_MC_TBL_SIZE_ICH8LAN; 1296 for (i = 0; i < mta_size; i++) { 1297 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 1298 /* 1299 * use write flush to prevent Memory Write Block (MWB) from 1300 * occuring when accessing our register space 1301 */ 1302 E1000_WRITE_FLUSH(hw); 1303 } 1304 /* 1305 * Set the PCI priority bit correctly in the CTRL register. This 1306 * determines if the adapter gives priority to receives, or if it 1307 * gives equal priority to transmits and receives. Valid only on 1308 * 82542 and 82543 silicon. 1309 */ 1310 if (hw->dma_fairness && hw->mac_type <= em_82543) { 1311 ctrl = E1000_READ_REG(hw, CTRL); 1312 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); 1313 } 1314 switch (hw->mac_type) { 1315 case em_82545_rev_3: 1316 case em_82546_rev_3: 1317 break; 1318 default: 1319 /* 1320 * Workaround for PCI-X problem when BIOS sets MMRBC 1321 * incorrectly. 1322 */ 1323 if (hw->bus_type == em_bus_type_pcix) { 1324 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1325 &pcix_cmd_word); 1326 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, 1327 &pcix_stat_hi_word); 1328 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) 1329 >> PCIX_COMMAND_MMRBC_SHIFT; 1330 stat_mmrbc = (pcix_stat_hi_word & 1331 PCIX_STATUS_HI_MMRBC_MASK) >> 1332 PCIX_STATUS_HI_MMRBC_SHIFT; 1333 1334 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 1335 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 1336 if (cmd_mmrbc > stat_mmrbc) { 1337 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; 1338 pcix_cmd_word |= stat_mmrbc << 1339 PCIX_COMMAND_MMRBC_SHIFT; 1340 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, 1341 &pcix_cmd_word); 1342 } 1343 } 1344 break; 1345 } 1346 1347 /* More time needed for PHY to initialize */ 1348 if (IS_ICH8(hw->mac_type)) 1349 msec_delay(15); 1350 1351 /* 1352 * The 82578 Rx buffer will stall if wakeup is enabled in host and 1353 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 1354 * Reset the phy after disabling host wakeup to reset the Rx buffer. 1355 */ 1356 if (hw->phy_type == em_phy_82578) { 1357 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1), 1358 (uint16_t *)®_data); 1359 ret_val = em_phy_reset(hw); 1360 if (ret_val) 1361 return ret_val; 1362 } 1363 1364 /* Call a subroutine to configure the link and setup flow control. */ 1365 ret_val = em_setup_link(hw); 1366 1367 /* Set the transmit descriptor write-back policy */ 1368 if (hw->mac_type > em_82544) { 1369 ctrl = E1000_READ_REG(hw, TXDCTL); 1370 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1371 E1000_TXDCTL_FULL_TX_DESC_WB; 1372 E1000_WRITE_REG(hw, TXDCTL, ctrl); 1373 } 1374 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1375 em_enable_tx_pkt_filtering(hw); 1376 } 1377 switch (hw->mac_type) { 1378 default: 1379 break; 1380 case em_80003es2lan: 1381 /* Enable retransmit on late collisions */ 1382 reg_data = E1000_READ_REG(hw, TCTL); 1383 reg_data |= E1000_TCTL_RTLC; 1384 E1000_WRITE_REG(hw, TCTL, reg_data); 1385 1386 /* Configure Gigabit Carry Extend Padding */ 1387 reg_data = E1000_READ_REG(hw, TCTL_EXT); 1388 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 1389 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; 1390 E1000_WRITE_REG(hw, TCTL_EXT, reg_data); 1391 1392 /* Configure Transmit Inter-Packet Gap */ 1393 reg_data = E1000_READ_REG(hw, TIPG); 1394 reg_data &= ~E1000_TIPG_IPGT_MASK; 1395 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 1396 E1000_WRITE_REG(hw, TIPG, reg_data); 1397 1398 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); 1399 reg_data &= ~0x00100000; 1400 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); 1401 /* FALLTHROUGH */ 1402 case em_82571: 1403 case em_82572: 1404 case em_82575: 1405 case em_82580: 1406 case em_i210: 1407 case em_i350: 1408 case em_ich8lan: 1409 case em_ich9lan: 1410 case em_ich10lan: 1411 case em_pchlan: 1412 case em_pch2lan: 1413 case em_pch_lpt: 1414 ctrl = E1000_READ_REG(hw, TXDCTL1); 1415 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | 1416 E1000_TXDCTL_FULL_TX_DESC_WB; 1417 E1000_WRITE_REG(hw, TXDCTL1, ctrl); 1418 break; 1419 } 1420 1421 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 1422 uint32_t gcr = E1000_READ_REG(hw, GCR); 1423 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 1424 E1000_WRITE_REG(hw, GCR, gcr); 1425 } 1426 /* 1427 * Clear all of the statistics registers (clear on read). It is 1428 * important that we do this after we have tried to establish link 1429 * because the symbol error count will increment wildly if there is 1430 * no link. 1431 */ 1432 em_clear_hw_cntrs(hw); 1433 /* 1434 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default 1435 * after reset. 1436 */ 1437 if (IS_ICH8(hw->mac_type)) { 1438 if (hw->mac_type == em_ich8lan) 1439 snoop = PCI_EX_82566_SNOOP_ALL; 1440 else 1441 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); 1442 1443 em_set_pci_ex_no_snoop(hw, snoop); 1444 } 1445 1446 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || 1447 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { 1448 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1449 /* 1450 * Relaxed ordering must be disabled to avoid a parity error 1451 * crash in a PCI slot. 1452 */ 1453 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 1454 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1455 } 1456 return ret_val; 1457 } 1458 1459 /****************************************************************************** 1460 * Adjust SERDES output amplitude based on EEPROM setting. 1461 * 1462 * hw - Struct containing variables accessed by shared code. 1463 *****************************************************************************/ 1464 static int32_t 1465 em_adjust_serdes_amplitude(struct em_hw *hw) 1466 { 1467 uint16_t eeprom_data; 1468 int32_t ret_val; 1469 DEBUGFUNC("em_adjust_serdes_amplitude"); 1470 1471 if (hw->media_type != em_media_type_internal_serdes || 1472 hw->mac_type >= em_82575) 1473 return E1000_SUCCESS; 1474 1475 switch (hw->mac_type) { 1476 case em_82545_rev_3: 1477 case em_82546_rev_3: 1478 break; 1479 default: 1480 return E1000_SUCCESS; 1481 } 1482 1483 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); 1484 if (ret_val) { 1485 return ret_val; 1486 } 1487 if (eeprom_data != EEPROM_RESERVED_WORD) { 1488 /* Adjust SERDES output amplitude only. */ 1489 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 1490 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, 1491 eeprom_data); 1492 if (ret_val) 1493 return ret_val; 1494 } 1495 return E1000_SUCCESS; 1496 } 1497 1498 /****************************************************************************** 1499 * Configures flow control and link settings. 1500 * 1501 * hw - Struct containing variables accessed by shared code 1502 * 1503 * Determines which flow control settings to use. Calls the appropriate media- 1504 * specific link configuration function. Configures the flow control settings. 1505 * Assuming the adapter has a valid link partner, a valid link should be 1506 * established. Assumes the hardware has previously been reset and the 1507 * transmitter and receiver are not enabled. 1508 *****************************************************************************/ 1509 int32_t 1510 em_setup_link(struct em_hw *hw) 1511 { 1512 uint32_t ctrl_ext; 1513 int32_t ret_val; 1514 uint16_t eeprom_data; 1515 uint16_t eeprom_control2_reg_offset; 1516 DEBUGFUNC("em_setup_link"); 1517 1518 eeprom_control2_reg_offset = 1519 (hw->mac_type != em_icp_xxxx) 1520 ? EEPROM_INIT_CONTROL2_REG 1521 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num); 1522 /* 1523 * In the case of the phy reset being blocked, we already have a 1524 * link. We do not have to set it up again. 1525 */ 1526 if (em_check_phy_reset_block(hw)) 1527 return E1000_SUCCESS; 1528 /* 1529 * Read and store word 0x0F of the EEPROM. This word contains bits 1530 * that determine the hardware's default PAUSE (flow control) mode, a 1531 * bit that determines whether the HW defaults to enabling or 1532 * disabling auto-negotiation, and the direction of the SW defined 1533 * pins. If there is no SW over-ride of the flow control setting, 1534 * then the variable hw->fc will be initialized based on a value in 1535 * the EEPROM. 1536 */ 1537 if (hw->fc == E1000_FC_DEFAULT) { 1538 switch (hw->mac_type) { 1539 case em_ich8lan: 1540 case em_ich9lan: 1541 case em_ich10lan: 1542 case em_pchlan: 1543 case em_pch2lan: 1544 case em_pch_lpt: 1545 case em_82573: 1546 case em_82574: 1547 hw->fc = E1000_FC_FULL; 1548 break; 1549 default: 1550 ret_val = em_read_eeprom(hw, 1551 eeprom_control2_reg_offset, 1, &eeprom_data); 1552 if (ret_val) { 1553 DEBUGOUT("EEPROM Read Error\n"); 1554 return -E1000_ERR_EEPROM; 1555 } 1556 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) 1557 hw->fc = E1000_FC_NONE; 1558 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 1559 EEPROM_WORD0F_ASM_DIR) 1560 hw->fc = E1000_FC_TX_PAUSE; 1561 else 1562 hw->fc = E1000_FC_FULL; 1563 break; 1564 } 1565 } 1566 /* 1567 * We want to save off the original Flow Control configuration just 1568 * in case we get disconnected and then reconnected into a different 1569 * hub or switch with different Flow Control capabilities. 1570 */ 1571 if (hw->mac_type == em_82542_rev2_0) 1572 hw->fc &= (~E1000_FC_TX_PAUSE); 1573 1574 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1)) 1575 hw->fc &= (~E1000_FC_RX_PAUSE); 1576 1577 hw->original_fc = hw->fc; 1578 1579 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); 1580 /* 1581 * Take the 4 bits from EEPROM word 0x0F that determine the initial 1582 * polarity value for the SW controlled pins, and setup the Extended 1583 * Device Control reg with that info. This is needed because one of 1584 * the SW controlled pins is used for signal detection. So this 1585 * should be done before em_setup_pcs_link() or em_phy_setup() is 1586 * called. 1587 */ 1588 if (hw->mac_type == em_82543) { 1589 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1590 1, &eeprom_data); 1591 if (ret_val) { 1592 DEBUGOUT("EEPROM Read Error\n"); 1593 return -E1000_ERR_EEPROM; 1594 } 1595 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 1596 SWDPIO__EXT_SHIFT); 1597 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 1598 } 1599 /* Make sure we have a valid PHY */ 1600 ret_val = em_detect_gig_phy(hw); 1601 if (ret_val) { 1602 DEBUGOUT("Error, did not detect valid phy.\n"); 1603 if (hw->mac_type == em_icp_xxxx) 1604 return E1000_DEFER_INIT; 1605 else 1606 return ret_val; 1607 } 1608 DEBUGOUT1("Phy ID = %x \n", hw->phy_id); 1609 1610 /* Call the necessary subroutine to configure the link. */ 1611 switch (hw->media_type) { 1612 case em_media_type_copper: 1613 case em_media_type_oem: 1614 ret_val = em_setup_copper_link(hw); 1615 break; 1616 default: 1617 ret_val = em_setup_fiber_serdes_link(hw); 1618 break; 1619 } 1620 /* 1621 * Initialize the flow control address, type, and PAUSE timer 1622 * registers to their default values. This is done even if flow 1623 * control is disabled, because it does not hurt anything to 1624 * initialize these registers. 1625 */ 1626 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n" 1627 ); 1628 1629 /* 1630 * FCAL/H and FCT are hardcoded to standard values in 1631 * em_ich8lan / em_ich9lan / em_ich10lan. 1632 */ 1633 if (!IS_ICH8(hw->mac_type)) { 1634 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); 1635 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); 1636 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); 1637 } 1638 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); 1639 1640 if (hw->phy_type == em_phy_82577 || 1641 hw->phy_type == em_phy_82578 || 1642 hw->phy_type == em_phy_82579 || 1643 hw->phy_type == em_phy_i217) { 1644 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000); 1645 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 1646 hw->fc_pause_time); 1647 } 1648 1649 /* 1650 * Set the flow control receive threshold registers. Normally, these 1651 * registers will be set to a default threshold that may be adjusted 1652 * later by the driver's runtime code. However, if the ability to 1653 * transmit pause frames in not enabled, then these registers will be 1654 * set to 0. 1655 */ 1656 if (!(hw->fc & E1000_FC_TX_PAUSE)) { 1657 E1000_WRITE_REG(hw, FCRTL, 0); 1658 E1000_WRITE_REG(hw, FCRTH, 0); 1659 } else { 1660 /* 1661 * We need to set up the Receive Threshold high and low water 1662 * marks as well as (optionally) enabling the transmission of 1663 * XON frames. 1664 */ 1665 if (hw->fc_send_xon) { 1666 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water 1667 | E1000_FCRTL_XONE)); 1668 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1669 } else { 1670 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); 1671 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); 1672 } 1673 } 1674 return ret_val; 1675 } 1676 1677 void 1678 em_power_up_serdes_link_82575(struct em_hw *hw) 1679 { 1680 uint32_t reg; 1681 1682 /* Enable PCS to turn on link */ 1683 reg = E1000_READ_REG(hw, PCS_CFG0); 1684 reg |= E1000_PCS_CFG_PCS_EN; 1685 E1000_WRITE_REG(hw, PCS_CFG0, reg); 1686 1687 /* Power up the laser */ 1688 reg = E1000_READ_REG(hw, CTRL_EXT); 1689 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1690 E1000_WRITE_REG(hw, CTRL_EXT, reg); 1691 1692 /* flush the write to verify completion */ 1693 E1000_WRITE_FLUSH(hw); 1694 delay(5); 1695 } 1696 1697 /****************************************************************************** 1698 * Sets up link for a fiber based or serdes based adapter 1699 * 1700 * hw - Struct containing variables accessed by shared code 1701 * 1702 * Manipulates Physical Coding Sublayer functions in order to configure 1703 * link. Assumes the hardware has been previously reset and the transmitter 1704 * and receiver are not enabled. 1705 *****************************************************************************/ 1706 static int32_t 1707 em_setup_fiber_serdes_link(struct em_hw *hw) 1708 { 1709 uint32_t ctrl, ctrl_ext, reg; 1710 uint32_t status; 1711 uint32_t txcw = 0; 1712 uint32_t i; 1713 uint32_t signal = 0; 1714 int32_t ret_val; 1715 DEBUGFUNC("em_setup_fiber_serdes_link"); 1716 /* 1717 * On 82571 and 82572 Fiber connections, SerDes loopback mode 1718 * persists until explicitly turned off or a power cycle is 1719 * performed. A read to the register does not indicate its status. 1720 * Therefore, we ensure loopback mode is disabled during 1721 * initialization. 1722 */ 1723 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 || 1724 hw->mac_type >= em_82575) 1725 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); 1726 1727 if (hw->mac_type >= em_82575) 1728 em_power_up_serdes_link_82575(hw); 1729 1730 /* 1731 * On adapters with a MAC newer than 82544, SWDP 1 will be set when 1732 * the optics detect a signal. On older adapters, it will be cleared 1733 * when there is a signal. This applies to fiber media only. If 1734 * we're on serdes media, adjust the output amplitude to value set in 1735 * the EEPROM. 1736 */ 1737 ctrl = E1000_READ_REG(hw, CTRL); 1738 if (hw->media_type == em_media_type_fiber) 1739 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; 1740 1741 ret_val = em_adjust_serdes_amplitude(hw); 1742 if (ret_val) 1743 return ret_val; 1744 1745 /* Take the link out of reset */ 1746 ctrl &= ~(E1000_CTRL_LRST); 1747 1748 if (hw->mac_type >= em_82575) { 1749 /* set both sw defined pins on 82575/82576*/ 1750 ctrl |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1751 1752 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 1753 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1754 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1755 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1756 /* the backplane is always connected */ 1757 reg = E1000_READ_REG(hw, PCS_LCTL); 1758 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1759 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1760 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1761 DEBUGOUT("Configuring Forced Link\n"); 1762 E1000_WRITE_REG(hw, PCS_LCTL, reg); 1763 em_force_mac_fc(hw); 1764 hw->autoneg_failed = 0; 1765 return E1000_SUCCESS; 1766 break; 1767 default: 1768 /* Set switch control to serdes energy detect */ 1769 reg = E1000_READ_REG(hw, CONNSW); 1770 reg |= E1000_CONNSW_ENRGSRC; 1771 E1000_WRITE_REG(hw, CONNSW, reg); 1772 break; 1773 } 1774 } 1775 1776 /* Adjust VCO speed to improve BER performance */ 1777 ret_val = em_set_vco_speed(hw); 1778 if (ret_val) 1779 return ret_val; 1780 1781 em_config_collision_dist(hw); 1782 /* 1783 * Check for a software override of the flow control settings, and 1784 * setup the device accordingly. If auto-negotiation is enabled, 1785 * then software will have to set the "PAUSE" bits to the correct 1786 * value in the Tranmsit Config Word Register (TXCW) and re-start 1787 * auto-negotiation. However, if auto-negotiation is disabled, then 1788 * software will have to manually configure the two flow control 1789 * enable bits in the CTRL register. 1790 * 1791 * The possible values of the "fc" parameter are: 0: Flow control is 1792 * completely disabled 1: Rx flow control is enabled (we can receive 1793 * pause frames, but not send pause frames). 2: Tx flow control is 1794 * enabled (we can send pause frames but we do not support receiving 1795 * pause frames). 3: Both Rx and TX flow control (symmetric) are 1796 * enabled. 1797 */ 1798 switch (hw->fc) { 1799 case E1000_FC_NONE: 1800 /* 1801 * Flow control is completely disabled by a software 1802 * over-ride. 1803 */ 1804 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1805 break; 1806 case E1000_FC_RX_PAUSE: 1807 /* 1808 * RX Flow control is enabled and TX Flow control is disabled 1809 * by a software over-ride. Since there really isn't a way to 1810 * advertise that we are capable of RX Pause ONLY, we will 1811 * advertise that we support both symmetric and asymmetric RX 1812 * PAUSE. Later, we will disable the adapter's ability to 1813 * send PAUSE frames. 1814 */ 1815 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1816 E1000_TXCW_PAUSE_MASK); 1817 break; 1818 case E1000_FC_TX_PAUSE: 1819 /* 1820 * TX Flow control is enabled, and RX Flow control is 1821 * disabled, by a software over-ride. 1822 */ 1823 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1824 break; 1825 case E1000_FC_FULL: 1826 /* 1827 * Flow control (both RX and TX) is enabled by a software 1828 * over-ride. 1829 */ 1830 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | 1831 E1000_TXCW_PAUSE_MASK); 1832 break; 1833 default: 1834 DEBUGOUT("Flow control param set incorrectly\n"); 1835 return -E1000_ERR_CONFIG; 1836 break; 1837 } 1838 /* 1839 * Since auto-negotiation is enabled, take the link out of reset (the 1840 * link will be in reset, because we previously reset the chip). This 1841 * will restart auto-negotiation. If auto-neogtiation is successful 1842 * then the link-up status bit will be set and the flow control 1843 * enable bits (RFCE and TFCE) will be set according to their 1844 * negotiated value. 1845 */ 1846 DEBUGOUT("Auto-negotiation enabled\n"); 1847 1848 E1000_WRITE_REG(hw, TXCW, txcw); 1849 E1000_WRITE_REG(hw, CTRL, ctrl); 1850 E1000_WRITE_FLUSH(hw); 1851 1852 hw->txcw = txcw; 1853 msec_delay(1); 1854 /* 1855 * If we have a signal (the cable is plugged in) then poll for a 1856 * "Link-Up" indication in the Device Status Register. Time-out if a 1857 * link isn't seen in 500 milliseconds seconds (Auto-negotiation 1858 * should complete in less than 500 milliseconds even if the other 1859 * end is doing it in SW). For internal serdes, we just assume a 1860 * signal is present, then poll. 1861 */ 1862 if (hw->media_type == em_media_type_internal_serdes || 1863 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { 1864 DEBUGOUT("Looking for Link\n"); 1865 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { 1866 msec_delay(10); 1867 status = E1000_READ_REG(hw, STATUS); 1868 if (status & E1000_STATUS_LU) 1869 break; 1870 } 1871 if (i == (LINK_UP_TIMEOUT / 10)) { 1872 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1873 hw->autoneg_failed = 1; 1874 /* 1875 * AutoNeg failed to achieve a link, so we'll call 1876 * em_check_for_link. This routine will force the 1877 * link up if we detect a signal. This will allow us 1878 * to communicate with non-autonegotiating link 1879 * partners. 1880 */ 1881 ret_val = em_check_for_link(hw); 1882 if (ret_val) { 1883 DEBUGOUT("Error while checking for link\n"); 1884 return ret_val; 1885 } 1886 hw->autoneg_failed = 0; 1887 } else { 1888 hw->autoneg_failed = 0; 1889 DEBUGOUT("Valid Link Found\n"); 1890 } 1891 } else { 1892 DEBUGOUT("No Signal Detected\n"); 1893 } 1894 return E1000_SUCCESS; 1895 } 1896 1897 /****************************************************************************** 1898 * Make sure we have a valid PHY and change PHY mode before link setup. 1899 * 1900 * hw - Struct containing variables accessed by shared code 1901 *****************************************************************************/ 1902 static int32_t 1903 em_copper_link_preconfig(struct em_hw *hw) 1904 { 1905 uint32_t ctrl; 1906 int32_t ret_val; 1907 uint16_t phy_data; 1908 DEBUGFUNC("em_copper_link_preconfig"); 1909 1910 ctrl = E1000_READ_REG(hw, CTRL); 1911 /* 1912 * With 82543, we need to force speed and duplex on the MAC equal to 1913 * what the PHY speed and duplex configuration is. In addition, we 1914 * need to perform a hardware reset on the PHY to take it out of 1915 * reset. 1916 */ 1917 if (hw->mac_type > em_82543) { 1918 ctrl |= E1000_CTRL_SLU; 1919 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1920 E1000_WRITE_REG(hw, CTRL, ctrl); 1921 } else { 1922 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | 1923 E1000_CTRL_SLU); 1924 E1000_WRITE_REG(hw, CTRL, ctrl); 1925 ret_val = em_phy_hw_reset(hw); 1926 if (ret_val) 1927 return ret_val; 1928 } 1929 1930 /* Set PHY to class A mode (if necessary) */ 1931 ret_val = em_set_phy_mode(hw); 1932 if (ret_val) 1933 return ret_val; 1934 1935 if ((hw->mac_type == em_82545_rev_3) || 1936 (hw->mac_type == em_82546_rev_3)) { 1937 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1938 &phy_data); 1939 phy_data |= 0x00000008; 1940 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 1941 phy_data); 1942 } 1943 if (hw->mac_type <= em_82543 || 1944 hw->mac_type == em_82541 || hw->mac_type == em_82547 || 1945 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) 1946 hw->phy_reset_disable = FALSE; 1947 1948 return E1000_SUCCESS; 1949 } 1950 1951 /****************************************************************************** 1952 * Copper link setup for em_phy_igp series. 1953 * 1954 * hw - Struct containing variables accessed by shared code 1955 *****************************************************************************/ 1956 static int32_t 1957 em_copper_link_igp_setup(struct em_hw *hw) 1958 { 1959 uint32_t led_ctrl; 1960 int32_t ret_val; 1961 uint16_t phy_data; 1962 DEBUGFUNC("em_copper_link_igp_setup"); 1963 1964 if (hw->phy_reset_disable) 1965 return E1000_SUCCESS; 1966 1967 ret_val = em_phy_reset(hw); 1968 if (ret_val) { 1969 DEBUGOUT("Error Resetting the PHY\n"); 1970 return ret_val; 1971 } 1972 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 1973 msec_delay(15); 1974 if (hw->mac_type != em_ich8lan && 1975 hw->mac_type != em_ich9lan && 1976 hw->mac_type != em_ich10lan) { 1977 /* Configure activity LED after PHY reset */ 1978 led_ctrl = E1000_READ_REG(hw, LEDCTL); 1979 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1980 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1981 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 1982 } 1983 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ 1984 if (hw->phy_type == em_phy_igp) { 1985 /* disable lplu d3 during driver init */ 1986 ret_val = em_set_d3_lplu_state(hw, FALSE); 1987 if (ret_val) { 1988 DEBUGOUT("Error Disabling LPLU D3\n"); 1989 return ret_val; 1990 } 1991 } 1992 /* disable lplu d0 during driver init */ 1993 if (hw->mac_type == em_pchlan || 1994 hw->mac_type == em_pch2lan || 1995 hw->mac_type == em_pch_lpt) 1996 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 1997 else 1998 ret_val = em_set_d0_lplu_state(hw, FALSE); 1999 if (ret_val) { 2000 DEBUGOUT("Error Disabling LPLU D0\n"); 2001 return ret_val; 2002 } 2003 /* Configure mdi-mdix settings */ 2004 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 2005 if (ret_val) 2006 return ret_val; 2007 2008 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 2009 hw->dsp_config_state = em_dsp_config_disabled; 2010 /* Force MDI for earlier revs of the IGP PHY */ 2011 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | 2012 IGP01E1000_PSCR_FORCE_MDI_MDIX); 2013 hw->mdix = 1; 2014 2015 } else { 2016 hw->dsp_config_state = em_dsp_config_enabled; 2017 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 2018 2019 switch (hw->mdix) { 2020 case 1: 2021 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 2022 break; 2023 case 2: 2024 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 2025 break; 2026 case 0: 2027 default: 2028 phy_data |= IGP01E1000_PSCR_AUTO_MDIX; 2029 break; 2030 } 2031 } 2032 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 2033 if (ret_val) 2034 return ret_val; 2035 2036 /* set auto-master slave resolution settings */ 2037 if (hw->autoneg) { 2038 em_ms_type phy_ms_setting = hw->master_slave; 2039 if (hw->ffe_config_state == em_ffe_config_active) 2040 hw->ffe_config_state = em_ffe_config_enabled; 2041 2042 if (hw->dsp_config_state == em_dsp_config_activated) 2043 hw->dsp_config_state = em_dsp_config_enabled; 2044 /* 2045 * when autonegotiation advertisement is only 1000Mbps then 2046 * we should disable SmartSpeed and enable Auto MasterSlave 2047 * resolution as hardware default. 2048 */ 2049 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { 2050 /* Disable SmartSpeed */ 2051 ret_val = em_read_phy_reg(hw, 2052 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 2053 if (ret_val) 2054 return ret_val; 2055 2056 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2057 ret_val = em_write_phy_reg(hw, 2058 IGP01E1000_PHY_PORT_CONFIG, phy_data); 2059 if (ret_val) 2060 return ret_val; 2061 /* Set auto Master/Slave resolution process */ 2062 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2063 &phy_data); 2064 if (ret_val) 2065 return ret_val; 2066 2067 phy_data &= ~CR_1000T_MS_ENABLE; 2068 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2069 phy_data); 2070 if (ret_val) 2071 return ret_val; 2072 } 2073 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); 2074 if (ret_val) 2075 return ret_val; 2076 2077 /* load defaults for future use */ 2078 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? 2079 ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : 2080 em_ms_force_slave) : em_ms_auto; 2081 2082 switch (phy_ms_setting) { 2083 case em_ms_force_master: 2084 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2085 break; 2086 case em_ms_force_slave: 2087 phy_data |= CR_1000T_MS_ENABLE; 2088 phy_data &= ~(CR_1000T_MS_VALUE); 2089 break; 2090 case em_ms_auto: 2091 phy_data &= ~CR_1000T_MS_ENABLE; 2092 break; 2093 default: 2094 break; 2095 } 2096 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); 2097 if (ret_val) 2098 return ret_val; 2099 } 2100 return E1000_SUCCESS; 2101 } 2102 2103 /****************************************************************************** 2104 * Copper link setup for em_phy_gg82563 series. 2105 * 2106 * hw - Struct containing variables accessed by shared code 2107 *****************************************************************************/ 2108 static int32_t 2109 em_copper_link_ggp_setup(struct em_hw *hw) 2110 { 2111 int32_t ret_val; 2112 uint16_t phy_data; 2113 uint32_t reg_data; 2114 DEBUGFUNC("em_copper_link_ggp_setup"); 2115 2116 if (!hw->phy_reset_disable) { 2117 2118 /* Enable CRS on TX for half-duplex operation. */ 2119 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2120 &phy_data); 2121 if (ret_val) 2122 return ret_val; 2123 2124 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 2125 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ 2126 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; 2127 2128 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 2129 phy_data); 2130 if (ret_val) 2131 return ret_val; 2132 /* 2133 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 2134 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only 2135 * (MDI-X for 10/100Base-T modes) 2136 */ 2137 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2138 &phy_data); 2139 2140 if (ret_val) 2141 return ret_val; 2142 2143 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 2144 2145 switch (hw->mdix) { 2146 case 1: 2147 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 2148 break; 2149 case 2: 2150 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 2151 break; 2152 case 0: 2153 default: 2154 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 2155 break; 2156 } 2157 /* 2158 * Options: disable_polarity_correction = 0 (default) 2159 * Automatic Correction for Reversed Cable Polarity 0 - 2160 * Disabled 1 - Enabled 2161 */ 2162 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2163 if (hw->disable_polarity_correction == 1) 2164 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 2165 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, 2166 phy_data); 2167 2168 if (ret_val) 2169 return ret_val; 2170 2171 /* SW Reset the PHY so all changes take effect */ 2172 ret_val = em_phy_reset(hw); 2173 if (ret_val) { 2174 DEBUGOUT("Error Resetting the PHY\n"); 2175 return ret_val; 2176 } 2177 } /* phy_reset_disable */ 2178 if (hw->mac_type == em_80003es2lan) { 2179 /* Bypass RX and TX FIFO's */ 2180 ret_val = em_write_kmrn_reg(hw, 2181 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, 2182 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | 2183 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); 2184 if (ret_val) 2185 return ret_val; 2186 2187 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2188 &phy_data); 2189 if (ret_val) 2190 return ret_val; 2191 2192 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 2193 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, 2194 phy_data); 2195 2196 if (ret_val) 2197 return ret_val; 2198 2199 reg_data = E1000_READ_REG(hw, CTRL_EXT); 2200 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 2201 E1000_WRITE_REG(hw, CTRL_EXT, reg_data); 2202 2203 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 2204 &phy_data); 2205 if (ret_val) 2206 return ret_val; 2207 /* 2208 * Do not init these registers when the HW is in IAMT mode, 2209 * since the firmware will have already initialized them. We 2210 * only initialize them if the HW is not in IAMT mode. 2211 */ 2212 if (em_check_mng_mode(hw) == FALSE) { 2213 /* Enable Electrical Idle on the PHY */ 2214 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 2215 ret_val = em_write_phy_reg(hw, 2216 GG82563_PHY_PWR_MGMT_CTRL, phy_data); 2217 if (ret_val) 2218 return ret_val; 2219 2220 ret_val = em_read_phy_reg(hw, 2221 GG82563_PHY_KMRN_MODE_CTRL, &phy_data); 2222 if (ret_val) 2223 return ret_val; 2224 2225 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2226 ret_val = em_write_phy_reg(hw, 2227 GG82563_PHY_KMRN_MODE_CTRL, phy_data); 2228 2229 if (ret_val) 2230 return ret_val; 2231 } 2232 /* 2233 * Workaround: Disable padding in Kumeran interface in the 2234 * MAC and in the PHY to avoid CRC errors. 2235 */ 2236 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2237 &phy_data); 2238 if (ret_val) 2239 return ret_val; 2240 phy_data |= GG82563_ICR_DIS_PADDING; 2241 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, 2242 phy_data); 2243 if (ret_val) 2244 return ret_val; 2245 } 2246 return E1000_SUCCESS; 2247 } 2248 2249 /****************************************************************************** 2250 * Copper link setup for em_phy_m88 series. 2251 * 2252 * hw - Struct containing variables accessed by shared code 2253 *****************************************************************************/ 2254 static int32_t 2255 em_copper_link_mgp_setup(struct em_hw *hw) 2256 { 2257 int32_t ret_val; 2258 uint16_t phy_data; 2259 DEBUGFUNC("em_copper_link_mgp_setup"); 2260 2261 if (hw->phy_reset_disable) 2262 return E1000_SUCCESS; 2263 2264 /* disable lplu d0 during driver init */ 2265 if (hw->mac_type == em_pchlan || 2266 hw->mac_type == em_pch2lan || 2267 hw->mac_type == em_pch_lpt) 2268 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2269 2270 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2271 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2272 if (ret_val) 2273 return ret_val; 2274 2275 if (hw->phy_id == M88E1141_E_PHY_ID) { 2276 phy_data |= 0x00000008; 2277 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2278 phy_data); 2279 if (ret_val) 2280 return ret_val; 2281 2282 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 2283 &phy_data); 2284 if (ret_val) 2285 return ret_val; 2286 2287 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 2288 2289 } 2290 /* For BM PHY this bit is downshift enable */ 2291 else if (hw->phy_type != em_phy_bm) 2292 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 2293 /* 2294 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI 2295 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for 2296 * 10/100Base-T modes) 2297 */ 2298 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 2299 2300 switch (hw->mdix) { 2301 case 1: 2302 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 2303 break; 2304 case 2: 2305 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 2306 break; 2307 case 3: 2308 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 2309 break; 2310 case 0: 2311 default: 2312 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 2313 break; 2314 } 2315 /* 2316 * Options: disable_polarity_correction = 0 (default) Automatic 2317 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled 2318 */ 2319 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 2320 if (hw->disable_polarity_correction == 1) 2321 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 2322 2323 /* Enable downshift on BM (disabled by default) */ 2324 if (hw->phy_type == em_phy_bm) 2325 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 2326 2327 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 2328 if (ret_val) 2329 return ret_val; 2330 2331 if (((hw->phy_type == em_phy_m88) && 2332 (hw->phy_revision < M88E1011_I_REV_4) && 2333 (hw->phy_id != BME1000_E_PHY_ID)) || 2334 (hw->phy_type == em_phy_oem)) { 2335 /* 2336 * Force TX_CLK in the Extended PHY Specific Control Register 2337 * to 25MHz clock. 2338 */ 2339 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2340 &phy_data); 2341 if (ret_val) 2342 return ret_val; 2343 2344 if (hw->phy_type == em_phy_oem) { 2345 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL; 2346 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL; 2347 } 2348 phy_data |= M88E1000_EPSCR_TX_CLK_25; 2349 2350 if ((hw->phy_revision == E1000_REVISION_2) && 2351 (hw->phy_id == M88E1111_I_PHY_ID)) { 2352 /* Vidalia Phy, set the downshift counter to 5x */ 2353 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); 2354 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 2355 ret_val = em_write_phy_reg(hw, 2356 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2357 if (ret_val) 2358 return ret_val; 2359 } else { 2360 /* Configure Master and Slave downshift values */ 2361 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 2362 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 2363 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 2364 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 2365 ret_val = em_write_phy_reg(hw, 2366 M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 2367 if (ret_val) 2368 return ret_val; 2369 } 2370 } 2371 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 2372 /* 2373 * Set PHY page 0, register 29 to 0x0003 2374 * The next two writes are supposed to lower BER for gig 2375 * conection 2376 */ 2377 ret_val = em_write_phy_reg(hw, BM_REG_BIAS1, 0x0003); 2378 if (ret_val) 2379 return ret_val; 2380 2381 /* Set PHY page 0, register 30 to 0x0000 */ 2382 ret_val = em_write_phy_reg(hw, BM_REG_BIAS2, 0x0000); 2383 if (ret_val) 2384 return ret_val; 2385 } 2386 if (hw->phy_type == em_phy_82578) { 2387 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2388 &phy_data); 2389 if (ret_val) 2390 return ret_val; 2391 2392 /* 82578 PHY - set the downshift count to 1x. */ 2393 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 2394 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 2395 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 2396 phy_data); 2397 if (ret_val) 2398 return ret_val; 2399 } 2400 /* SW Reset the PHY so all changes take effect */ 2401 ret_val = em_phy_reset(hw); 2402 if (ret_val) { 2403 DEBUGOUT("Error Resetting the PHY\n"); 2404 return ret_val; 2405 } 2406 return E1000_SUCCESS; 2407 } 2408 2409 /****************************************************************************** 2410 * Copper link setup for em_phy_82577 series. 2411 * 2412 * hw - Struct containing variables accessed by shared code 2413 *****************************************************************************/ 2414 static int32_t 2415 em_copper_link_82577_setup(struct em_hw *hw) 2416 { 2417 int32_t ret_val; 2418 uint16_t phy_data; 2419 uint32_t led_ctl; 2420 DEBUGFUNC("em_copper_link_82577_setup"); 2421 2422 if (hw->phy_reset_disable) 2423 return E1000_SUCCESS; 2424 2425 /* Enable CRS on TX for half-duplex operation. */ 2426 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG, &phy_data); 2427 if (ret_val) 2428 return ret_val; 2429 2430 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX | 2431 I82577_PHY_CFG_ENABLE_DOWNSHIFT; 2432 2433 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG, phy_data); 2434 if (ret_val) 2435 return ret_val; 2436 2437 /* Wait 15ms for MAC to configure PHY from eeprom settings */ 2438 msec_delay(15); 2439 led_ctl = hw->ledctl_mode1; 2440 2441 /* disable lplu d0 during driver init */ 2442 ret_val = em_set_lplu_state_pchlan(hw, FALSE); 2443 if (ret_val) { 2444 DEBUGOUT("Error Disabling LPLU D0\n"); 2445 return ret_val; 2446 } 2447 2448 E1000_WRITE_REG(hw, LEDCTL, led_ctl); 2449 2450 return E1000_SUCCESS; 2451 } 2452 2453 static int32_t 2454 em_copper_link_82580_setup(struct em_hw *hw) 2455 { 2456 int32_t ret_val; 2457 uint16_t phy_data; 2458 2459 if (hw->phy_reset_disable) 2460 return E1000_SUCCESS; 2461 2462 ret_val = em_phy_reset(hw); 2463 if (ret_val) 2464 goto out; 2465 2466 /* Enable CRS on TX. This must be set for half-duplex operation. */ 2467 ret_val = em_read_phy_reg(hw, I82580_CFG_REG, &phy_data); 2468 if (ret_val) 2469 goto out; 2470 2471 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX | 2472 I82580_CFG_ENABLE_DOWNSHIFT; 2473 2474 ret_val = em_write_phy_reg(hw, I82580_CFG_REG, phy_data); 2475 2476 out: 2477 return ret_val; 2478 } 2479 2480 /****************************************************************************** 2481 * Setup auto-negotiation and flow control advertisements, 2482 * and then perform auto-negotiation. 2483 * 2484 * hw - Struct containing variables accessed by shared code 2485 *****************************************************************************/ 2486 int32_t 2487 em_copper_link_autoneg(struct em_hw *hw) 2488 { 2489 int32_t ret_val; 2490 uint16_t phy_data; 2491 DEBUGFUNC("em_copper_link_autoneg"); 2492 /* 2493 * Perform some bounds checking on the hw->autoneg_advertised 2494 * parameter. If this variable is zero, then set it to the default. 2495 */ 2496 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; 2497 /* 2498 * If autoneg_advertised is zero, we assume it was not defaulted by 2499 * the calling code so we set to advertise full capability. 2500 */ 2501 if (hw->autoneg_advertised == 0) 2502 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 2503 2504 /* IFE phy only supports 10/100 */ 2505 if (hw->phy_type == em_phy_ife) 2506 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; 2507 2508 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 2509 ret_val = em_phy_setup_autoneg(hw); 2510 if (ret_val) { 2511 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 2512 return ret_val; 2513 } 2514 DEBUGOUT("Restarting Auto-Neg\n"); 2515 /* 2516 * Restart auto-negotiation by setting the Auto Neg Enable bit and 2517 * the Auto Neg Restart bit in the PHY control register. 2518 */ 2519 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 2520 if (ret_val) 2521 return ret_val; 2522 2523 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2524 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 2525 if (ret_val) 2526 return ret_val; 2527 /* 2528 * Does the user want to wait for Auto-Neg to complete here, or check 2529 * at a later time (for example, callback routine). 2530 */ 2531 if (hw->wait_autoneg_complete) { 2532 ret_val = em_wait_autoneg(hw); 2533 if (ret_val) { 2534 DEBUGOUT("Error while waiting for autoneg to complete\n" 2535 ); 2536 return ret_val; 2537 } 2538 } 2539 hw->get_link_status = TRUE; 2540 2541 return E1000_SUCCESS; 2542 } 2543 2544 /****************************************************************************** 2545 * Config the MAC and the PHY after link is up. 2546 * 1) Set up the MAC to the current PHY speed/duplex 2547 * if we are on 82543. If we 2548 * are on newer silicon, we only need to configure 2549 * collision distance in the Transmit Control Register. 2550 * 2) Set up flow control on the MAC to that established with 2551 * the link partner. 2552 * 3) Config DSP to improve Gigabit link quality for some PHY revisions. 2553 * 2554 * hw - Struct containing variables accessed by shared code 2555 *****************************************************************************/ 2556 int32_t 2557 em_copper_link_postconfig(struct em_hw *hw) 2558 { 2559 int32_t ret_val; 2560 DEBUGFUNC("em_copper_link_postconfig"); 2561 2562 if (hw->mac_type >= em_82544 && 2563 hw->mac_type != em_icp_xxxx) { 2564 em_config_collision_dist(hw); 2565 } else { 2566 ret_val = em_config_mac_to_phy(hw); 2567 if (ret_val) { 2568 DEBUGOUT("Error configuring MAC to PHY settings\n"); 2569 return ret_val; 2570 } 2571 } 2572 ret_val = em_config_fc_after_link_up(hw); 2573 if (ret_val) { 2574 DEBUGOUT("Error Configuring Flow Control\n"); 2575 return ret_val; 2576 } 2577 /* Config DSP to improve Giga link quality */ 2578 if (hw->phy_type == em_phy_igp) { 2579 ret_val = em_config_dsp_after_link_change(hw, TRUE); 2580 if (ret_val) { 2581 DEBUGOUT("Error Configuring DSP after link up\n"); 2582 return ret_val; 2583 } 2584 } 2585 return E1000_SUCCESS; 2586 } 2587 2588 /****************************************************************************** 2589 * Detects which PHY is present and setup the speed and duplex 2590 * 2591 * hw - Struct containing variables accessed by shared code 2592 *****************************************************************************/ 2593 static int32_t 2594 em_setup_copper_link(struct em_hw *hw) 2595 { 2596 int32_t ret_val; 2597 uint16_t i; 2598 uint16_t phy_data; 2599 uint16_t reg_data; 2600 DEBUGFUNC("em_setup_copper_link"); 2601 2602 switch (hw->mac_type) { 2603 case em_80003es2lan: 2604 case em_ich8lan: 2605 case em_ich9lan: 2606 case em_ich10lan: 2607 case em_pchlan: 2608 case em_pch2lan: 2609 case em_pch_lpt: 2610 /* 2611 * Set the mac to wait the maximum time between each 2612 * iteration and increase the max iterations when polling the 2613 * phy; this fixes erroneous timeouts at 10Mbps. 2614 */ 2615 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 2616 if (ret_val) 2617 return ret_val; 2618 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), 2619 ®_data); 2620 if (ret_val) 2621 return ret_val; 2622 reg_data |= 0x3F; 2623 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), 2624 reg_data); 2625 if (ret_val) 2626 return ret_val; 2627 default: 2628 break; 2629 } 2630 2631 /* Check if it is a valid PHY and set PHY mode if necessary. */ 2632 ret_val = em_copper_link_preconfig(hw); 2633 if (ret_val) 2634 return ret_val; 2635 2636 switch (hw->mac_type) { 2637 case em_80003es2lan: 2638 /* Kumeran registers are written-only */ 2639 reg_data = 2640 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; 2641 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; 2642 ret_val = em_write_kmrn_reg(hw, 2643 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); 2644 if (ret_val) 2645 return ret_val; 2646 break; 2647 default: 2648 break; 2649 } 2650 2651 if (hw->phy_type == em_phy_igp || 2652 hw->phy_type == em_phy_igp_3 || 2653 hw->phy_type == em_phy_igp_2) { 2654 ret_val = em_copper_link_igp_setup(hw); 2655 if (ret_val) 2656 return ret_val; 2657 } else if (hw->phy_type == em_phy_m88 || 2658 hw->phy_type == em_phy_bm || 2659 hw->phy_type == em_phy_oem || 2660 hw->phy_type == em_phy_82578) { 2661 ret_val = em_copper_link_mgp_setup(hw); 2662 if (ret_val) 2663 return ret_val; 2664 } else if (hw->phy_type == em_phy_gg82563) { 2665 ret_val = em_copper_link_ggp_setup(hw); 2666 if (ret_val) 2667 return ret_val; 2668 } else if (hw->phy_type == em_phy_82577 || 2669 hw->phy_type == em_phy_82579 || 2670 hw->phy_type == em_phy_i217) { 2671 ret_val = em_copper_link_82577_setup(hw); 2672 if (ret_val) 2673 return ret_val; 2674 } else if (hw->phy_type == em_phy_82580) { 2675 ret_val = em_copper_link_82580_setup(hw); 2676 if (ret_val) 2677 return ret_val; 2678 } 2679 if (hw->autoneg) { 2680 /* 2681 * Setup autoneg and flow control advertisement and perform 2682 * autonegotiation 2683 */ 2684 ret_val = em_copper_link_autoneg(hw); 2685 if (ret_val) 2686 return ret_val; 2687 } else { 2688 /* 2689 * PHY will be set to 10H, 10F, 100H,or 100F depending on 2690 * value from forced_speed_duplex. 2691 */ 2692 DEBUGOUT("Forcing speed and duplex\n"); 2693 ret_val = em_phy_force_speed_duplex(hw); 2694 if (ret_val) { 2695 DEBUGOUT("Error Forcing Speed and Duplex\n"); 2696 return ret_val; 2697 } 2698 } 2699 /* 2700 * Check link status. Wait up to 100 microseconds for link to become 2701 * valid. 2702 */ 2703 for (i = 0; i < 10; i++) { 2704 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2705 if (ret_val) 2706 return ret_val; 2707 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 2708 if (ret_val) 2709 return ret_val; 2710 2711 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 2712 2713 if (phy_data & MII_SR_LINK_STATUS) { 2714 /* Config the MAC and PHY after link is up */ 2715 ret_val = em_copper_link_postconfig(hw); 2716 if (ret_val) 2717 return ret_val; 2718 2719 DEBUGOUT("Valid link established!!!\n"); 2720 return E1000_SUCCESS; 2721 } 2722 usec_delay(10); 2723 } 2724 2725 DEBUGOUT("Unable to establish link!!!\n"); 2726 return E1000_SUCCESS; 2727 } 2728 2729 /****************************************************************************** 2730 * Configure the MAC-to-PHY interface for 10/100Mbps 2731 * 2732 * hw - Struct containing variables accessed by shared code 2733 *****************************************************************************/ 2734 static int32_t 2735 em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex) 2736 { 2737 int32_t ret_val = E1000_SUCCESS; 2738 uint32_t tipg; 2739 uint16_t reg_data; 2740 DEBUGFUNC("em_configure_kmrn_for_10_100"); 2741 2742 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; 2743 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2744 reg_data); 2745 if (ret_val) 2746 return ret_val; 2747 2748 /* Configure Transmit Inter-Packet Gap */ 2749 tipg = E1000_READ_REG(hw, TIPG); 2750 tipg &= ~E1000_TIPG_IPGT_MASK; 2751 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; 2752 E1000_WRITE_REG(hw, TIPG, tipg); 2753 2754 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2755 2756 if (ret_val) 2757 return ret_val; 2758 2759 if (duplex == HALF_DUPLEX) 2760 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 2761 else 2762 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2763 2764 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2765 2766 return ret_val; 2767 } 2768 2769 static int32_t 2770 em_configure_kmrn_for_1000(struct em_hw *hw) 2771 { 2772 int32_t ret_val = E1000_SUCCESS; 2773 uint16_t reg_data; 2774 uint32_t tipg; 2775 DEBUGFUNC("em_configure_kmrn_for_1000"); 2776 2777 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; 2778 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, 2779 reg_data); 2780 if (ret_val) 2781 return ret_val; 2782 2783 /* Configure Transmit Inter-Packet Gap */ 2784 tipg = E1000_READ_REG(hw, TIPG); 2785 tipg &= ~E1000_TIPG_IPGT_MASK; 2786 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; 2787 E1000_WRITE_REG(hw, TIPG, tipg); 2788 2789 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); 2790 2791 if (ret_val) 2792 return ret_val; 2793 2794 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 2795 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 2796 2797 return ret_val; 2798 } 2799 2800 /****************************************************************************** 2801 * Configures PHY autoneg and flow control advertisement settings 2802 * 2803 * hw - Struct containing variables accessed by shared code 2804 *****************************************************************************/ 2805 int32_t 2806 em_phy_setup_autoneg(struct em_hw *hw) 2807 { 2808 int32_t ret_val; 2809 uint16_t mii_autoneg_adv_reg; 2810 uint16_t mii_1000t_ctrl_reg; 2811 DEBUGFUNC("em_phy_setup_autoneg"); 2812 2813 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 2814 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 2815 if (ret_val) 2816 return ret_val; 2817 2818 if (hw->phy_type != em_phy_ife) { 2819 /* Read the MII 1000Base-T Control Register (Address 9). */ 2820 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, 2821 &mii_1000t_ctrl_reg); 2822 if (ret_val) 2823 return ret_val; 2824 } else 2825 mii_1000t_ctrl_reg = 0; 2826 /* 2827 * Need to parse both autoneg_advertised and fc and set up the 2828 * appropriate PHY registers. First we will parse for 2829 * autoneg_advertised software override. Since we can advertise a 2830 * plethora of combinations, we need to check each bit individually. 2831 */ 2832 /* 2833 * First we clear all the 10/100 mb speed bits in the Auto-Neg 2834 * Advertisement Register (Address 4) and the 1000 mb speed bits in 2835 * the 1000Base-T Control Register (Address 9). 2836 */ 2837 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; 2838 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; 2839 2840 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); 2841 2842 /* Do we want to advertise 10 Mb Half Duplex? */ 2843 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { 2844 DEBUGOUT("Advertise 10mb Half duplex\n"); 2845 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 2846 } 2847 /* Do we want to advertise 10 Mb Full Duplex? */ 2848 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { 2849 DEBUGOUT("Advertise 10mb Full duplex\n"); 2850 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 2851 } 2852 /* Do we want to advertise 100 Mb Half Duplex? */ 2853 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { 2854 DEBUGOUT("Advertise 100mb Half duplex\n"); 2855 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 2856 } 2857 /* Do we want to advertise 100 Mb Full Duplex? */ 2858 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { 2859 DEBUGOUT("Advertise 100mb Full duplex\n"); 2860 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 2861 } 2862 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 2863 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { 2864 DEBUGOUT("Advertise 1000mb Half duplex requested, request" 2865 " denied!\n"); 2866 } 2867 /* Do we want to advertise 1000 Mb Full Duplex? */ 2868 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { 2869 DEBUGOUT("Advertise 1000mb Full duplex\n"); 2870 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 2871 if (hw->phy_type == em_phy_ife) { 2872 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is" 2873 " not supported.\n"); 2874 } 2875 } 2876 /* 2877 * Check for a software override of the flow control settings, and 2878 * setup the PHY advertisement registers accordingly. If 2879 * auto-negotiation is enabled, then software will have to set the 2880 * "PAUSE" bits to the correct value in the Auto-Negotiation 2881 * Advertisement Register (PHY_AUTONEG_ADV) and re-start 2882 * auto-negotiation. 2883 * 2884 * The possible values of the "fc" parameter are: 0: Flow control is 2885 * completely disabled 1: Rx flow control is enabled (we can receive 2886 * pause frames but not send pause frames). 2: Tx flow control is 2887 * enabled (we can send pause frames but we do not support receiving 2888 * pause frames). 3: Both Rx and TX flow control (symmetric) are 2889 * enabled. other: No software override. The flow control 2890 * configuration in the EEPROM is used. 2891 */ 2892 switch (hw->fc) { 2893 case E1000_FC_NONE: /* 0 */ 2894 /* 2895 * Flow control (RX & TX) is completely disabled by a 2896 * software over-ride. 2897 */ 2898 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2899 break; 2900 case E1000_FC_RX_PAUSE:/* 1 */ 2901 /* 2902 * RX Flow control is enabled, and TX Flow control is 2903 * disabled, by a software over-ride. 2904 */ 2905 /* 2906 * Since there really isn't a way to advertise that we are 2907 * capable of RX Pause ONLY, we will advertise that we 2908 * support both symmetric and asymmetric RX PAUSE. Later (in 2909 * em_config_fc_after_link_up) we will disable the hw's 2910 * ability to send PAUSE frames. 2911 */ 2912 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2913 break; 2914 case E1000_FC_TX_PAUSE:/* 2 */ 2915 /* 2916 * TX Flow control is enabled, and RX Flow control is 2917 * disabled, by a software over-ride. 2918 */ 2919 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 2920 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 2921 break; 2922 case E1000_FC_FULL: /* 3 */ 2923 /* 2924 * Flow control (both RX and TX) is enabled by a software 2925 * over-ride. 2926 */ 2927 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 2928 break; 2929 default: 2930 DEBUGOUT("Flow control param set incorrectly\n"); 2931 return -E1000_ERR_CONFIG; 2932 } 2933 2934 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 2935 if (ret_val) 2936 return ret_val; 2937 2938 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 2939 2940 if (hw->phy_type != em_phy_ife) { 2941 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, 2942 mii_1000t_ctrl_reg); 2943 if (ret_val) 2944 return ret_val; 2945 } 2946 return E1000_SUCCESS; 2947 } 2948 /****************************************************************************** 2949 * Force PHY speed and duplex settings to hw->forced_speed_duplex 2950 * 2951 * hw - Struct containing variables accessed by shared code 2952 *****************************************************************************/ 2953 static int32_t 2954 em_phy_force_speed_duplex(struct em_hw *hw) 2955 { 2956 uint32_t ctrl; 2957 int32_t ret_val; 2958 uint16_t mii_ctrl_reg; 2959 uint16_t mii_status_reg; 2960 uint16_t phy_data; 2961 uint16_t i; 2962 DEBUGFUNC("em_phy_force_speed_duplex"); 2963 2964 /* Turn off Flow control if we are forcing speed and duplex. */ 2965 hw->fc = E1000_FC_NONE; 2966 2967 DEBUGOUT1("hw->fc = %d\n", hw->fc); 2968 2969 /* Read the Device Control Register. */ 2970 ctrl = E1000_READ_REG(hw, CTRL); 2971 2972 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ 2973 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2974 ctrl &= ~(DEVICE_SPEED_MASK); 2975 2976 /* Clear the Auto Speed Detect Enable bit. */ 2977 ctrl &= ~E1000_CTRL_ASDE; 2978 2979 /* Read the MII Control Register. */ 2980 ret_val = em_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); 2981 if (ret_val) 2982 return ret_val; 2983 2984 /* We need to disable autoneg in order to force link and duplex. */ 2985 2986 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; 2987 2988 /* Are we forcing Full or Half Duplex? */ 2989 if (hw->forced_speed_duplex == em_100_full || 2990 hw->forced_speed_duplex == em_10_full) { 2991 /* 2992 * We want to force full duplex so we SET the full duplex 2993 * bits in the Device and MII Control Registers. 2994 */ 2995 ctrl |= E1000_CTRL_FD; 2996 mii_ctrl_reg |= MII_CR_FULL_DUPLEX; 2997 DEBUGOUT("Full Duplex\n"); 2998 } else { 2999 /* 3000 * We want to force half duplex so we CLEAR the full duplex 3001 * bits in the Device and MII Control Registers. 3002 */ 3003 ctrl &= ~E1000_CTRL_FD; 3004 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; 3005 DEBUGOUT("Half Duplex\n"); 3006 } 3007 3008 /* Are we forcing 100Mbps??? */ 3009 if (hw->forced_speed_duplex == em_100_full || 3010 hw->forced_speed_duplex == em_100_half) { 3011 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ 3012 ctrl |= E1000_CTRL_SPD_100; 3013 mii_ctrl_reg |= MII_CR_SPEED_100; 3014 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 3015 DEBUGOUT("Forcing 100mb "); 3016 } else { 3017 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ 3018 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 3019 mii_ctrl_reg |= MII_CR_SPEED_10; 3020 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 3021 DEBUGOUT("Forcing 10mb "); 3022 } 3023 3024 em_config_collision_dist(hw); 3025 3026 /* Write the configured values back to the Device Control Reg. */ 3027 E1000_WRITE_REG(hw, CTRL, ctrl); 3028 3029 if ((hw->phy_type == em_phy_m88) || 3030 (hw->phy_type == em_phy_gg82563) || 3031 (hw->phy_type == em_phy_bm) || 3032 (hw->phy_type == em_phy_oem || 3033 (hw->phy_type == em_phy_82578))) { 3034 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3035 &phy_data); 3036 if (ret_val) 3037 return ret_val; 3038 /* 3039 * Clear Auto-Crossover to force MDI manually. M88E1000 3040 * requires MDI forced whenever speed are duplex are forced. 3041 */ 3042 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 3043 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3044 phy_data); 3045 if (ret_val) 3046 return ret_val; 3047 3048 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); 3049 3050 /* Need to reset the PHY or these changes will be ignored */ 3051 mii_ctrl_reg |= MII_CR_RESET; 3052 3053 } 3054 /* Disable MDI-X support for 10/100 */ 3055 else if (hw->phy_type == em_phy_ife) { 3056 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); 3057 if (ret_val) 3058 return ret_val; 3059 3060 phy_data &= ~IFE_PMC_AUTO_MDIX; 3061 phy_data &= ~IFE_PMC_FORCE_MDIX; 3062 3063 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); 3064 if (ret_val) 3065 return ret_val; 3066 } else { 3067 /* 3068 * Clear Auto-Crossover to force MDI manually. IGP requires 3069 * MDI forced whenever speed or duplex are forced. 3070 */ 3071 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3072 &phy_data); 3073 if (ret_val) 3074 return ret_val; 3075 3076 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 3077 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 3078 3079 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, 3080 phy_data); 3081 if (ret_val) 3082 return ret_val; 3083 } 3084 3085 /* Write back the modified PHY MII control register. */ 3086 ret_val = em_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); 3087 if (ret_val) 3088 return ret_val; 3089 3090 usec_delay(1); 3091 /* 3092 * The wait_autoneg_complete flag may be a little misleading here. 3093 * Since we are forcing speed and duplex, Auto-Neg is not enabled. 3094 * But we do want to delay for a period while forcing only so we 3095 * don't generate false No Link messages. So we will wait here only 3096 * if the user has set wait_autoneg_complete to 1, which is the 3097 * default. 3098 */ 3099 if (hw->wait_autoneg_complete) { 3100 /* We will wait for autoneg to complete. */ 3101 DEBUGOUT("Waiting for forced speed/duplex link.\n"); 3102 mii_status_reg = 0; 3103 /* 3104 * We will wait for autoneg to complete or 4.5 seconds to 3105 * expire. 3106 */ 3107 for (i = PHY_FORCE_TIME; i > 0; i--) { 3108 /* 3109 * Read the MII Status Register and wait for Auto-Neg 3110 * Complete bit to be set. 3111 */ 3112 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3113 &mii_status_reg); 3114 if (ret_val) 3115 return ret_val; 3116 3117 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3118 &mii_status_reg); 3119 if (ret_val) 3120 return ret_val; 3121 3122 if (mii_status_reg & MII_SR_LINK_STATUS) 3123 break; 3124 msec_delay(100); 3125 } 3126 if ((i == 0) && 3127 ((hw->phy_type == em_phy_m88) || 3128 (hw->phy_type == em_phy_gg82563) || 3129 (hw->phy_type == em_phy_bm))) { 3130 /* 3131 * We didn't get link. Reset the DSP and wait again 3132 * for link. 3133 */ 3134 ret_val = em_phy_reset_dsp(hw); 3135 if (ret_val) { 3136 DEBUGOUT("Error Resetting PHY DSP\n"); 3137 return ret_val; 3138 } 3139 } 3140 /* 3141 * This loop will early-out if the link condition has been 3142 * met. 3143 */ 3144 for (i = PHY_FORCE_TIME; i > 0; i--) { 3145 if (mii_status_reg & MII_SR_LINK_STATUS) 3146 break; 3147 msec_delay(100); 3148 /* 3149 * Read the MII Status Register and wait for Auto-Neg 3150 * Complete bit to be set. 3151 */ 3152 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3153 &mii_status_reg); 3154 if (ret_val) 3155 return ret_val; 3156 3157 ret_val = em_read_phy_reg(hw, PHY_STATUS, 3158 &mii_status_reg); 3159 if (ret_val) 3160 return ret_val; 3161 } 3162 } 3163 if (hw->phy_type == em_phy_m88 || 3164 hw->phy_type == em_phy_bm || 3165 hw->phy_type == em_phy_oem) { 3166 /* 3167 * Because we reset the PHY above, we need to re-force TX_CLK 3168 * in the Extended PHY Specific Control Register to 25MHz 3169 * clock. This value defaults back to a 2.5MHz clock when 3170 * the PHY is reset. 3171 */ 3172 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3173 &phy_data); 3174 if (ret_val) 3175 return ret_val; 3176 3177 phy_data |= M88E1000_EPSCR_TX_CLK_25; 3178 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 3179 phy_data); 3180 if (ret_val) 3181 return ret_val; 3182 /* 3183 * In addition, because of the s/w reset above, we need to 3184 * enable CRS on TX. This must be set for both full and half 3185 * duplex operation. 3186 */ 3187 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3188 &phy_data); 3189 if (ret_val) 3190 return ret_val; 3191 3192 if (hw->phy_id == M88E1141_E_PHY_ID) 3193 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX; 3194 else 3195 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 3196 3197 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 3198 phy_data); 3199 if (ret_val) 3200 return ret_val; 3201 3202 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) && 3203 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full || 3204 hw->forced_speed_duplex == em_10_half)) { 3205 ret_val = em_polarity_reversal_workaround(hw); 3206 if (ret_val) 3207 return ret_val; 3208 } 3209 } else if (hw->phy_type == em_phy_gg82563) { 3210 /* 3211 * The TX_CLK of the Extended PHY Specific Control Register 3212 * defaults to 2.5MHz on a reset. We need to re-force it 3213 * back to 25MHz, if we're not in a forced 10/duplex 3214 * configuration. 3215 */ 3216 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3217 &phy_data); 3218 if (ret_val) 3219 return ret_val; 3220 3221 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 3222 if ((hw->forced_speed_duplex == em_10_full) || 3223 (hw->forced_speed_duplex == em_10_half)) 3224 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; 3225 else 3226 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; 3227 3228 /* Also due to the reset, we need to enable CRS on Tx. */ 3229 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 3230 3231 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 3232 phy_data); 3233 if (ret_val) 3234 return ret_val; 3235 } 3236 return E1000_SUCCESS; 3237 } 3238 3239 /****************************************************************************** 3240 * Sets the collision distance in the Transmit Control register 3241 * 3242 * hw - Struct containing variables accessed by shared code 3243 * 3244 * Link should have been established previously. Reads the speed and duplex 3245 * information from the Device Status register. 3246 *****************************************************************************/ 3247 void 3248 em_config_collision_dist(struct em_hw *hw) 3249 { 3250 uint32_t tctl, coll_dist; 3251 DEBUGFUNC("em_config_collision_dist"); 3252 3253 if (hw->mac_type < em_82543) 3254 coll_dist = E1000_COLLISION_DISTANCE_82542; 3255 else 3256 coll_dist = E1000_COLLISION_DISTANCE; 3257 3258 tctl = E1000_READ_REG(hw, TCTL); 3259 3260 tctl &= ~E1000_TCTL_COLD; 3261 tctl |= coll_dist << E1000_COLD_SHIFT; 3262 3263 E1000_WRITE_REG(hw, TCTL, tctl); 3264 E1000_WRITE_FLUSH(hw); 3265 } 3266 3267 /****************************************************************************** 3268 * Sets MAC speed and duplex settings to reflect the those in the PHY 3269 * 3270 * hw - Struct containing variables accessed by shared code 3271 * mii_reg - data to write to the MII control register 3272 * 3273 * The contents of the PHY register containing the needed information need to 3274 * be passed in. 3275 *****************************************************************************/ 3276 static int32_t 3277 em_config_mac_to_phy(struct em_hw *hw) 3278 { 3279 uint32_t ctrl; 3280 int32_t ret_val; 3281 uint16_t phy_data; 3282 DEBUGFUNC("em_config_mac_to_phy"); 3283 /* 3284 * 82544 or newer MAC, Auto Speed Detection takes care of MAC 3285 * speed/duplex configuration. 3286 */ 3287 if (hw->mac_type >= em_82544 3288 && hw->mac_type != em_icp_xxxx) 3289 return E1000_SUCCESS; 3290 /* 3291 * Read the Device Control Register and set the bits to Force Speed 3292 * and Duplex. 3293 */ 3294 ctrl = E1000_READ_REG(hw, CTRL); 3295 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3296 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 3297 /* 3298 * Set up duplex in the Device Control and Transmit Control registers 3299 * depending on negotiated values. 3300 */ 3301 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 3302 if (ret_val) 3303 return ret_val; 3304 3305 if (phy_data & M88E1000_PSSR_DPLX) 3306 ctrl |= E1000_CTRL_FD; 3307 else 3308 ctrl &= ~E1000_CTRL_FD; 3309 3310 em_config_collision_dist(hw); 3311 /* 3312 * Set up speed in the Device Control register depending on 3313 * negotiated values. 3314 */ 3315 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 3316 ctrl |= E1000_CTRL_SPD_1000; 3317 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 3318 ctrl |= E1000_CTRL_SPD_100; 3319 3320 /* Write the configured values back to the Device Control Reg. */ 3321 E1000_WRITE_REG(hw, CTRL, ctrl); 3322 return E1000_SUCCESS; 3323 } 3324 3325 /****************************************************************************** 3326 * Forces the MAC's flow control settings. 3327 * 3328 * hw - Struct containing variables accessed by shared code 3329 * 3330 * Sets the TFCE and RFCE bits in the device control register to reflect 3331 * the adapter settings. TFCE and RFCE need to be explicitly set by 3332 * software when a Copper PHY is used because autonegotiation is managed 3333 * by the PHY rather than the MAC. Software must also configure these 3334 * bits when link is forced on a fiber connection. 3335 *****************************************************************************/ 3336 int32_t 3337 em_force_mac_fc(struct em_hw *hw) 3338 { 3339 uint32_t ctrl; 3340 DEBUGFUNC("em_force_mac_fc"); 3341 3342 /* Get the current configuration of the Device Control Register */ 3343 ctrl = E1000_READ_REG(hw, CTRL); 3344 /* 3345 * Because we didn't get link via the internal auto-negotiation 3346 * mechanism (we either forced link or we got link via PHY auto-neg), 3347 * we have to manually enable/disable transmit an receive flow 3348 * control. 3349 * 3350 * The "Case" statement below enables/disable flow control according to 3351 * the "hw->fc" parameter. 3352 * 3353 * The possible values of the "fc" parameter are: 0: Flow control is 3354 * completely disabled 1: Rx flow control is enabled (we can receive 3355 * pause frames but not send pause frames). 2: Tx flow control is 3356 * enabled (we can send pause frames frames but we do not receive 3357 * pause frames). 3: Both Rx and TX flow control (symmetric) is 3358 * enabled. other: No other values should be possible at this point. 3359 */ 3360 3361 switch (hw->fc) { 3362 case E1000_FC_NONE: 3363 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 3364 break; 3365 case E1000_FC_RX_PAUSE: 3366 ctrl &= (~E1000_CTRL_TFCE); 3367 ctrl |= E1000_CTRL_RFCE; 3368 break; 3369 case E1000_FC_TX_PAUSE: 3370 ctrl &= (~E1000_CTRL_RFCE); 3371 ctrl |= E1000_CTRL_TFCE; 3372 break; 3373 case E1000_FC_FULL: 3374 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 3375 break; 3376 default: 3377 DEBUGOUT("Flow control param set incorrectly\n"); 3378 return -E1000_ERR_CONFIG; 3379 } 3380 3381 /* Disable TX Flow Control for 82542 (rev 2.0) */ 3382 if (hw->mac_type == em_82542_rev2_0) 3383 ctrl &= (~E1000_CTRL_TFCE); 3384 3385 E1000_WRITE_REG(hw, CTRL, ctrl); 3386 return E1000_SUCCESS; 3387 } 3388 /****************************************************************************** 3389 * Configures flow control settings after link is established 3390 * 3391 * hw - Struct containing variables accessed by shared code 3392 * 3393 * Should be called immediately after a valid link has been established. 3394 * Forces MAC flow control settings if link was forced. When in MII/GMII mode 3395 * and autonegotiation is enabled, the MAC flow control settings will be set 3396 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE 3397 * and RFCE bits will be automaticaly set to the negotiated flow control mode. 3398 *****************************************************************************/ 3399 STATIC int32_t 3400 em_config_fc_after_link_up(struct em_hw *hw) 3401 { 3402 int32_t ret_val; 3403 uint16_t mii_status_reg; 3404 uint16_t mii_nway_adv_reg; 3405 uint16_t mii_nway_lp_ability_reg; 3406 uint16_t speed; 3407 uint16_t duplex; 3408 DEBUGFUNC("em_config_fc_after_link_up"); 3409 /* 3410 * Check for the case where we have fiber media and auto-neg failed 3411 * so we had to force link. In this case, we need to force the 3412 * configuration of the MAC to match the "fc" parameter. 3413 */ 3414 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed)) 3415 || ((hw->media_type == em_media_type_internal_serdes) && 3416 (hw->autoneg_failed)) || 3417 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) || 3418 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) { 3419 ret_val = em_force_mac_fc(hw); 3420 if (ret_val) { 3421 DEBUGOUT("Error forcing flow control settings\n"); 3422 return ret_val; 3423 } 3424 } 3425 /* 3426 * Check for the case where we have copper media and auto-neg is 3427 * enabled. In this case, we need to check and see if Auto-Neg has 3428 * completed, and if so, how the PHY and link partner has flow 3429 * control configured. 3430 */ 3431 if ((hw->media_type == em_media_type_copper || 3432 (hw->media_type == em_media_type_oem)) && 3433 hw->autoneg) { 3434 /* 3435 * Read the MII Status Register and check to see if AutoNeg 3436 * has completed. We read this twice because this reg has 3437 * some "sticky" (latched) bits. 3438 */ 3439 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3440 if (ret_val) 3441 return ret_val; 3442 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 3443 if (ret_val) 3444 return ret_val; 3445 3446 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { 3447 /* 3448 * The AutoNeg process has completed, so we now need 3449 * to read both the Auto Negotiation Advertisement 3450 * Register (Address 4) and the Auto_Negotiation Base 3451 * Page Ability Register (Address 5) to determine how 3452 * flow control was negotiated. 3453 */ 3454 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV, 3455 &mii_nway_adv_reg); 3456 if (ret_val) 3457 return ret_val; 3458 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 3459 &mii_nway_lp_ability_reg); 3460 if (ret_val) 3461 return ret_val; 3462 /* 3463 * Two bits in the Auto Negotiation Advertisement 3464 * Register (Address 4) and two bits in the Auto 3465 * Negotiation Base Page Ability Register (Address 5) 3466 * determine flow control for both the PHY and the 3467 * link partner. The following table, taken out of 3468 * the IEEE 802.3ab/D6.0 dated March 25, 1999, 3469 * describes these PAUSE resolution bits and how flow 3470 * control is determined based upon these settings. 3471 * NOTE: DC = Don't Care 3472 * 3473 * LOCAL DEVICE | LINK PARTNER | 3474 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 3475 * -------|---------|-------|---------|--------------- 3476 * 0 | 0 | DC | DC | em_fc_none 3477 * 0 | 1 | 0 | DC | em_fc_none 3478 * 0 | 1 | 1 | 0 | em_fc_none 3479 * 0 | 1 | 1 | 1 | em_fc_tx_pause 3480 * 1 | 0 | 0 | DC | em_fc_none 3481 * 1 | DC | 1 | DC | em_fc_full 3482 * 1 | 1 | 0 | 0 | em_fc_none 3483 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3484 * 3485 */ 3486 /* 3487 * Are both PAUSE bits set to 1? If so, this implies 3488 * Symmetric Flow Control is enabled at both ends. 3489 * The ASM_DIR bits are irrelevant per the spec. 3490 * 3491 * For Symmetric Flow Control: 3492 * 3493 * LOCAL DEVICE | LINK PARTNER 3494 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3495 * -------|---------|-------|---------|--------------- 3496 * 1 | DC | 1 | DC | em_fc_full 3497 * 3498 */ 3499 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3500 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 3501 /* 3502 * Now we need to check if the user selected 3503 * RX ONLY of pause frames. In this case, we 3504 * had to advertise FULL flow control because 3505 * we could not advertise RX ONLY. Hence, we 3506 * must now check to see if we need to turn 3507 * OFF the TRANSMISSION of PAUSE frames. 3508 */ 3509 if (hw->original_fc == E1000_FC_FULL) { 3510 hw->fc = E1000_FC_FULL; 3511 DEBUGOUT("Flow Control = FULL.\n"); 3512 } else { 3513 hw->fc = E1000_FC_RX_PAUSE; 3514 DEBUGOUT("Flow Control = RX PAUSE" 3515 " frames only.\n"); 3516 } 3517 } 3518 /* 3519 * For receiving PAUSE frames ONLY. 3520 * 3521 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR | 3522 * PAUSE | ASM_DIR | Result 3523 * -------|---------|-------|---------|--------------- 3524 * ----- 0 | 1 | 1 | 1 | 3525 * em_fc_tx_pause 3526 * 3527 */ 3528 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 3529 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3530 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3531 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3532 hw->fc = E1000_FC_TX_PAUSE; 3533 DEBUGOUT("Flow Control = TX PAUSE frames only." 3534 "\n"); 3535 } 3536 /* 3537 * For transmitting PAUSE frames ONLY. 3538 * 3539 * LOCAL DEVICE | LINK PARTNER 3540 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 3541 * -------|---------|-------|---------|--------------- 3542 * 1 | 1 | 0 | 1 | em_fc_rx_pause 3543 * 3544 */ 3545 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 3546 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 3547 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 3548 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 3549 hw->fc = E1000_FC_RX_PAUSE; 3550 DEBUGOUT("Flow Control = RX PAUSE frames only." 3551 "\n"); 3552 } 3553 /* 3554 * Per the IEEE spec, at this point flow control 3555 * should be disabled. However, we want to consider 3556 * that we could be connected to a legacy switch that 3557 * doesn't advertise desired flow control, but can be 3558 * forced on the link partner. So if we advertised 3559 * no flow control, that is what we will resolve to. 3560 * If we advertised some kind of receive capability 3561 * (Rx Pause Only or Full Flow Control) and the link 3562 * partner advertised none, we will configure 3563 * ourselves to enable Rx Flow Control only. We can 3564 * do this safely for two reasons: If the link 3565 * partner really didn't want flow control enabled, 3566 * and we enable Rx, no harm done since we won't be 3567 * receiving any PAUSE frames anyway. If the intent 3568 * on the link partner was to have flow control 3569 * enabled, then by us enabling RX only, we can at 3570 * least receive pause frames and process them. This 3571 * is a good idea because in most cases, since we are 3572 * predominantly a server NIC, more times than not we 3573 * will be asked to delay transmission of packets 3574 * than asking our link partner to pause transmission 3575 * of frames. 3576 */ 3577 else if ((hw->original_fc == E1000_FC_NONE || 3578 hw->original_fc == E1000_FC_TX_PAUSE) || 3579 hw->fc_strict_ieee) { 3580 hw->fc = E1000_FC_NONE; 3581 DEBUGOUT("Flow Control = NONE.\n"); 3582 } else { 3583 hw->fc = E1000_FC_RX_PAUSE; 3584 DEBUGOUT("Flow Control = RX PAUSE frames only." 3585 "\n"); 3586 } 3587 /* 3588 * Now we need to do one last check... If we auto- 3589 * negotiated to HALF DUPLEX, flow control should not 3590 * be enabled per IEEE 802.3 spec. 3591 */ 3592 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3593 if (ret_val) { 3594 DEBUGOUT("Error getting link speed and duplex" 3595 "\n"); 3596 return ret_val; 3597 } 3598 if (duplex == HALF_DUPLEX) 3599 hw->fc = E1000_FC_NONE; 3600 /* 3601 * Now we call a subroutine to actually force the MAC 3602 * controller to use the correct flow control 3603 * settings. 3604 */ 3605 ret_val = em_force_mac_fc(hw); 3606 if (ret_val) { 3607 DEBUGOUT("Error forcing flow control settings" 3608 "\n"); 3609 return ret_val; 3610 } 3611 } else { 3612 DEBUGOUT("Copper PHY and Auto Neg has not completed." 3613 "\n"); 3614 } 3615 } 3616 return E1000_SUCCESS; 3617 } 3618 /****************************************************************************** 3619 * Checks to see if the link status of the hardware has changed. 3620 * 3621 * hw - Struct containing variables accessed by shared code 3622 * 3623 * Called by any function that needs to check the link status of the adapter. 3624 *****************************************************************************/ 3625 int32_t 3626 em_check_for_link(struct em_hw *hw) 3627 { 3628 uint32_t rxcw = 0; 3629 uint32_t ctrl; 3630 uint32_t status; 3631 uint32_t rctl; 3632 uint32_t icr; 3633 uint32_t signal = 0; 3634 int32_t ret_val; 3635 uint16_t phy_data; 3636 DEBUGFUNC("em_check_for_link"); 3637 uint16_t speed, duplex; 3638 3639 if (hw->mac_type >= em_82575 && 3640 hw->media_type != em_media_type_copper) { 3641 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed, 3642 &duplex); 3643 hw->get_link_status = hw->serdes_link_down; 3644 3645 return (ret_val); 3646 } 3647 3648 ctrl = E1000_READ_REG(hw, CTRL); 3649 status = E1000_READ_REG(hw, STATUS); 3650 /* 3651 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will 3652 * be set when the optics detect a signal. On older adapters, it will 3653 * be cleared when there is a signal. This applies to fiber media 3654 * only. 3655 */ 3656 if ((hw->media_type == em_media_type_fiber) || 3657 (hw->media_type == em_media_type_internal_serdes)) { 3658 rxcw = E1000_READ_REG(hw, RXCW); 3659 3660 if (hw->media_type == em_media_type_fiber) { 3661 signal = (hw->mac_type > em_82544) ? 3662 E1000_CTRL_SWDPIN1 : 0; 3663 if (status & E1000_STATUS_LU) 3664 hw->get_link_status = FALSE; 3665 } 3666 } 3667 /* 3668 * If we have a copper PHY then we only want to go out to the PHY 3669 * registers to see if Auto-Neg has completed and/or if our link 3670 * status has changed. The get_link_status flag will be set if we 3671 * receive a Link Status Change interrupt or we have Rx Sequence 3672 * Errors. 3673 */ 3674 if ((hw->media_type == em_media_type_copper || 3675 (hw->media_type == em_media_type_oem)) && 3676 hw->get_link_status) { 3677 /* 3678 * First we want to see if the MII Status Register reports 3679 * link. If so, then we want to get the current speed/duplex 3680 * of the PHY. Read the register twice since the link bit is 3681 * sticky. 3682 */ 3683 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3684 if (ret_val) 3685 return ret_val; 3686 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 3687 if (ret_val) 3688 return ret_val; 3689 3690 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS) != 0; 3691 3692 if (hw->mac_type == em_pchlan) { 3693 ret_val = em_k1_gig_workaround_hv(hw, 3694 hw->icp_xxxx_is_link_up); 3695 if (ret_val) 3696 return ret_val; 3697 } 3698 3699 if (phy_data & MII_SR_LINK_STATUS) { 3700 hw->get_link_status = FALSE; 3701 3702 if (hw->phy_type == em_phy_82578) { 3703 ret_val = em_link_stall_workaround_hv(hw); 3704 if (ret_val) 3705 return ret_val; 3706 } 3707 3708 if (hw->mac_type == em_pch2lan) { 3709 ret_val = em_k1_workaround_lv(hw); 3710 if (ret_val) 3711 return ret_val; 3712 } 3713 /* Work-around I218 hang issue */ 3714 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 3715 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 3716 (hw->device_id == E1000_DEV_ID_PCH_I218_LM3) || 3717 (hw->device_id == E1000_DEV_ID_PCH_I218_V3)) { 3718 ret_val = em_k1_workaround_lpt_lp(hw, 3719 hw->icp_xxxx_is_link_up); 3720 if (ret_val) 3721 return ret_val; 3722 } 3723 3724 /* 3725 * Check if there was DownShift, must be checked 3726 * immediately after link-up 3727 */ 3728 em_check_downshift(hw); 3729 3730 /* Enable/Disable EEE after link up */ 3731 if (hw->mac_type == em_pch2lan || 3732 hw->mac_type == em_pch_lpt) { 3733 ret_val = em_set_eee_pchlan(hw); 3734 if (ret_val) 3735 return ret_val; 3736 } 3737 3738 /* 3739 * If we are on 82544 or 82543 silicon and 3740 * speed/duplex are forced to 10H or 10F, then we 3741 * will implement the polarity reversal workaround. 3742 * We disable interrupts first, and upon returning, 3743 * place the devices interrupt state to its previous 3744 * value except for the link status change interrupt 3745 * which will happen due to the execution of this 3746 * workaround. 3747 */ 3748 if ((hw->mac_type == em_82544 || 3749 hw->mac_type == em_82543) && (!hw->autoneg) && 3750 (hw->forced_speed_duplex == em_10_full || 3751 hw->forced_speed_duplex == em_10_half)) { 3752 E1000_WRITE_REG(hw, IMC, 0xffffffff); 3753 ret_val = em_polarity_reversal_workaround(hw); 3754 icr = E1000_READ_REG(hw, ICR); 3755 E1000_WRITE_REG(hw, ICS, 3756 (icr & ~E1000_ICS_LSC)); 3757 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); 3758 } 3759 } else { 3760 /* No link detected */ 3761 em_config_dsp_after_link_change(hw, FALSE); 3762 return 0; 3763 } 3764 /* 3765 * If we are forcing speed/duplex, then we simply return 3766 * since we have already determined whether we have link or 3767 * not. 3768 */ 3769 if (!hw->autoneg) 3770 return -E1000_ERR_CONFIG; 3771 3772 /* optimize the dsp settings for the igp phy */ 3773 em_config_dsp_after_link_change(hw, TRUE); 3774 /* 3775 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 3776 * have Si on board that is 82544 or newer, Auto Speed 3777 * Detection takes care of MAC speed/duplex configuration. 3778 * So we only need to configure Collision Distance in the 3779 * MAC. Otherwise, we need to force speed/duplex on the MAC 3780 * to the current PHY speed/duplex settings. 3781 */ 3782 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) 3783 em_config_collision_dist(hw); 3784 else { 3785 ret_val = em_config_mac_to_phy(hw); 3786 if (ret_val) { 3787 DEBUGOUT("Error configuring MAC to PHY" 3788 " settings\n"); 3789 return ret_val; 3790 } 3791 } 3792 /* 3793 * Configure Flow Control now that Auto-Neg has completed. 3794 * First, we need to restore the desired flow control 3795 * settings because we may have had to re-autoneg with a 3796 * different link partner. 3797 */ 3798 ret_val = em_config_fc_after_link_up(hw); 3799 if (ret_val) { 3800 DEBUGOUT("Error configuring flow control\n"); 3801 return ret_val; 3802 } 3803 /* 3804 * At this point we know that we are on copper and we have 3805 * auto-negotiated link. These are conditions for checking 3806 * the link partner capability register. We use the link 3807 * speed to determine if TBI compatibility needs to be turned 3808 * on or off. If the link is not at gigabit speed, then TBI 3809 * compatibility is not needed. If we are at gigabit speed, 3810 * we turn on TBI compatibility. 3811 */ 3812 if (hw->tbi_compatibility_en) { 3813 uint16_t speed, duplex; 3814 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 3815 if (ret_val) { 3816 DEBUGOUT("Error getting link speed and duplex" 3817 "\n"); 3818 return ret_val; 3819 } 3820 if (speed != SPEED_1000) { 3821 /* 3822 * If link speed is not set to gigabit speed, 3823 * we do not need to enable TBI 3824 * compatibility. 3825 */ 3826 if (hw->tbi_compatibility_on) { 3827 /* 3828 * If we previously were in the mode, 3829 * turn it off. 3830 */ 3831 rctl = E1000_READ_REG(hw, RCTL); 3832 rctl &= ~E1000_RCTL_SBP; 3833 E1000_WRITE_REG(hw, RCTL, rctl); 3834 hw->tbi_compatibility_on = FALSE; 3835 } 3836 } else { 3837 /* 3838 * If TBI compatibility is was previously 3839 * off, turn it on. For compatibility with a 3840 * TBI link partner, we will store bad 3841 * packets. Some frames have an additional 3842 * byte on the end and will look like CRC 3843 * errors to to the hardware. 3844 */ 3845 if (!hw->tbi_compatibility_on) { 3846 hw->tbi_compatibility_on = TRUE; 3847 rctl = E1000_READ_REG(hw, RCTL); 3848 rctl |= E1000_RCTL_SBP; 3849 E1000_WRITE_REG(hw, RCTL, rctl); 3850 } 3851 } 3852 } 3853 } 3854 /* 3855 * If we don't have link (auto-negotiation failed or link partner 3856 * cannot auto-negotiate), the cable is plugged in (we have signal), 3857 * and our link partner is not trying to auto-negotiate with us (we 3858 * are receiving idles or data), we need to force link up. We also 3859 * need to give auto-negotiation time to complete, in case the cable 3860 * was just plugged in. The autoneg_failed flag does this. 3861 */ 3862 else if ((((hw->media_type == em_media_type_fiber) && 3863 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || 3864 (hw->media_type == em_media_type_internal_serdes)) && 3865 (!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 3866 if (hw->autoneg_failed == 0) { 3867 hw->autoneg_failed = 1; 3868 return 0; 3869 } 3870 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 3871 3872 /* Disable auto-negotiation in the TXCW register */ 3873 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); 3874 3875 /* Force link-up and also force full-duplex. */ 3876 ctrl = E1000_READ_REG(hw, CTRL); 3877 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 3878 E1000_WRITE_REG(hw, CTRL, ctrl); 3879 3880 /* Configure Flow Control after forcing link up. */ 3881 ret_val = em_config_fc_after_link_up(hw); 3882 if (ret_val) { 3883 DEBUGOUT("Error configuring flow control\n"); 3884 return ret_val; 3885 } 3886 } 3887 /* 3888 * If we are forcing link and we are receiving /C/ ordered sets, 3889 * re-enable auto-negotiation in the TXCW register and disable forced 3890 * link in the Device Control register in an attempt to 3891 * auto-negotiate with our link partner. 3892 */ 3893 else if (((hw->media_type == em_media_type_fiber) || 3894 (hw->media_type == em_media_type_internal_serdes)) && 3895 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 3896 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 3897 E1000_WRITE_REG(hw, TXCW, hw->txcw); 3898 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); 3899 3900 hw->serdes_link_down = FALSE; 3901 } 3902 /* 3903 * If we force link for non-auto-negotiation switch, check link 3904 * status based on MAC synchronization for internal serdes media 3905 * type. 3906 */ 3907 else if ((hw->media_type == em_media_type_internal_serdes) && 3908 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3909 /* SYNCH bit and IV bit are sticky. */ 3910 usec_delay(10); 3911 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { 3912 if (!(rxcw & E1000_RXCW_IV)) { 3913 hw->serdes_link_down = FALSE; 3914 DEBUGOUT("SERDES: Link is up.\n"); 3915 } 3916 } else { 3917 hw->serdes_link_down = TRUE; 3918 DEBUGOUT("SERDES: Link is down.\n"); 3919 } 3920 } 3921 if ((hw->media_type == em_media_type_internal_serdes) && 3922 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { 3923 hw->serdes_link_down = !(E1000_STATUS_LU & 3924 E1000_READ_REG(hw, STATUS)); 3925 } 3926 return E1000_SUCCESS; 3927 } 3928 3929 int32_t 3930 em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, 3931 uint16_t *duplex) 3932 { 3933 uint32_t pcs; 3934 3935 hw->serdes_link_down = TRUE; 3936 *speed = 0; 3937 *duplex = 0; 3938 3939 /* 3940 * Read the PCS Status register for link state. For non-copper mode, 3941 * the status register is not accurate. The PCS status register is 3942 * used instead. 3943 */ 3944 pcs = E1000_READ_REG(hw, PCS_LSTAT); 3945 3946 /* 3947 * The link up bit determines when link is up on autoneg. The sync ok 3948 * gets set once both sides sync up and agree upon link. Stable link 3949 * can be determined by checking for both link up and link sync ok 3950 */ 3951 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 3952 hw->serdes_link_down = FALSE; 3953 3954 /* Detect and store PCS speed */ 3955 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 3956 *speed = SPEED_1000; 3957 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 3958 *speed = SPEED_100; 3959 } else { 3960 *speed = SPEED_10; 3961 } 3962 3963 /* Detect and store PCS duplex */ 3964 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 3965 *duplex = FULL_DUPLEX; 3966 } else { 3967 *duplex = HALF_DUPLEX; 3968 } 3969 } 3970 3971 return (0); 3972 } 3973 3974 3975 /****************************************************************************** 3976 * Detects the current speed and duplex settings of the hardware. 3977 * 3978 * hw - Struct containing variables accessed by shared code 3979 * speed - Speed of the connection 3980 * duplex - Duplex setting of the connection 3981 *****************************************************************************/ 3982 int32_t 3983 em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) 3984 { 3985 uint32_t status; 3986 int32_t ret_val; 3987 uint16_t phy_data; 3988 DEBUGFUNC("em_get_speed_and_duplex"); 3989 3990 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper) 3991 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex); 3992 3993 if (hw->mac_type >= em_82543) { 3994 status = E1000_READ_REG(hw, STATUS); 3995 if (status & E1000_STATUS_SPEED_1000) { 3996 *speed = SPEED_1000; 3997 DEBUGOUT("1000 Mbs, "); 3998 } else if (status & E1000_STATUS_SPEED_100) { 3999 *speed = SPEED_100; 4000 DEBUGOUT("100 Mbs, "); 4001 } else { 4002 *speed = SPEED_10; 4003 DEBUGOUT("10 Mbs, "); 4004 } 4005 4006 if (status & E1000_STATUS_FD) { 4007 *duplex = FULL_DUPLEX; 4008 DEBUGOUT("Full Duplex\n"); 4009 } else { 4010 *duplex = HALF_DUPLEX; 4011 DEBUGOUT(" Half Duplex\n"); 4012 } 4013 } else { 4014 DEBUGOUT("1000 Mbs, Full Duplex\n"); 4015 *speed = SPEED_1000; 4016 *duplex = FULL_DUPLEX; 4017 } 4018 /* 4019 * IGP01 PHY may advertise full duplex operation after speed 4020 * downgrade even if it is operating at half duplex. Here we set the 4021 * duplex settings to match the duplex in the link partner's 4022 * capabilities. 4023 */ 4024 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) { 4025 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); 4026 if (ret_val) 4027 return ret_val; 4028 4029 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) 4030 *duplex = HALF_DUPLEX; 4031 else { 4032 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, 4033 &phy_data); 4034 if (ret_val) 4035 return ret_val; 4036 if ((*speed == SPEED_100 && 4037 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || 4038 (*speed == SPEED_10 && 4039 !(phy_data & NWAY_LPAR_10T_FD_CAPS))) 4040 *duplex = HALF_DUPLEX; 4041 } 4042 } 4043 if ((hw->mac_type == em_80003es2lan) && 4044 (hw->media_type == em_media_type_copper)) { 4045 if (*speed == SPEED_1000) 4046 ret_val = em_configure_kmrn_for_1000(hw); 4047 else 4048 ret_val = em_configure_kmrn_for_10_100(hw, *duplex); 4049 if (ret_val) 4050 return ret_val; 4051 } 4052 if ((hw->mac_type == em_ich8lan) && 4053 (hw->phy_type == em_phy_igp_3) && 4054 (*speed == SPEED_1000)) { 4055 ret_val = em_kumeran_lock_loss_workaround(hw); 4056 if (ret_val) 4057 return ret_val; 4058 } 4059 return E1000_SUCCESS; 4060 } 4061 4062 /****************************************************************************** 4063 * Blocks until autoneg completes or times out (~4.5 seconds) 4064 * 4065 * hw - Struct containing variables accessed by shared code 4066 *****************************************************************************/ 4067 STATIC int32_t 4068 em_wait_autoneg(struct em_hw *hw) 4069 { 4070 int32_t ret_val; 4071 uint16_t i; 4072 uint16_t phy_data; 4073 DEBUGFUNC("em_wait_autoneg"); 4074 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); 4075 4076 /* We will wait for autoneg to complete or 4.5 seconds to expire. */ 4077 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { 4078 /* 4079 * Read the MII Status Register and wait for Auto-Neg 4080 * Complete bit to be set. 4081 */ 4082 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4083 if (ret_val) 4084 return ret_val; 4085 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 4086 if (ret_val) 4087 return ret_val; 4088 if (phy_data & MII_SR_AUTONEG_COMPLETE) { 4089 return E1000_SUCCESS; 4090 } 4091 msec_delay(100); 4092 } 4093 return E1000_SUCCESS; 4094 } 4095 4096 /****************************************************************************** 4097 * Raises the Management Data Clock 4098 * 4099 * hw - Struct containing variables accessed by shared code 4100 * ctrl - Device control register's current value 4101 *****************************************************************************/ 4102 static void 4103 em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4104 { 4105 /* 4106 * Raise the clock input to the Management Data Clock (by setting the 4107 * MDC bit), and then delay 10 microseconds. 4108 */ 4109 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); 4110 E1000_WRITE_FLUSH(hw); 4111 usec_delay(10); 4112 } 4113 4114 /****************************************************************************** 4115 * Lowers the Management Data Clock 4116 * 4117 * hw - Struct containing variables accessed by shared code 4118 * ctrl - Device control register's current value 4119 *****************************************************************************/ 4120 static void 4121 em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl) 4122 { 4123 /* 4124 * Lower the clock input to the Management Data Clock (by clearing 4125 * the MDC bit), and then delay 10 microseconds. 4126 */ 4127 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); 4128 E1000_WRITE_FLUSH(hw); 4129 usec_delay(10); 4130 } 4131 4132 /****************************************************************************** 4133 * Shifts data bits out to the PHY 4134 * 4135 * hw - Struct containing variables accessed by shared code 4136 * data - Data to send out to the PHY 4137 * count - Number of bits to shift out 4138 * 4139 * Bits are shifted out in MSB to LSB order. 4140 *****************************************************************************/ 4141 static void 4142 em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) 4143 { 4144 uint32_t ctrl; 4145 uint32_t mask; 4146 /* 4147 * We need to shift "count" number of bits out to the PHY. So, the 4148 * value in the "data" parameter will be shifted out to the PHY one 4149 * bit at a time. In order to do this, "data" must be broken down 4150 * into bits. 4151 */ 4152 mask = 0x01; 4153 mask <<= (count - 1); 4154 4155 ctrl = E1000_READ_REG(hw, CTRL); 4156 4157 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output 4158 * pins. 4159 */ 4160 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 4161 4162 while (mask) { 4163 /* 4164 * A "1" is shifted out to the PHY by setting the MDIO bit to 4165 * "1" and then raising and lowering the Management Data 4166 * Clock. A "0" is shifted out to the PHY by setting the MDIO 4167 * bit to "0" and then raising and lowering the clock. 4168 */ 4169 if (data & mask) 4170 ctrl |= E1000_CTRL_MDIO; 4171 else 4172 ctrl &= ~E1000_CTRL_MDIO; 4173 4174 E1000_WRITE_REG(hw, CTRL, ctrl); 4175 E1000_WRITE_FLUSH(hw); 4176 4177 usec_delay(10); 4178 4179 em_raise_mdi_clk(hw, &ctrl); 4180 em_lower_mdi_clk(hw, &ctrl); 4181 4182 mask = mask >> 1; 4183 } 4184 } 4185 4186 /****************************************************************************** 4187 * Shifts data bits in from the PHY 4188 * 4189 * hw - Struct containing variables accessed by shared code 4190 * 4191 * Bits are shifted in in MSB to LSB order. 4192 *****************************************************************************/ 4193 static uint16_t 4194 em_shift_in_mdi_bits(struct em_hw *hw) 4195 { 4196 uint32_t ctrl; 4197 uint16_t data = 0; 4198 uint8_t i; 4199 /* 4200 * In order to read a register from the PHY, we need to shift in a 4201 * total of 18 bits from the PHY. The first two bit (turnaround) 4202 * times are used to avoid contention on the MDIO pin when a read 4203 * operation is performed. These two bits are ignored by us and 4204 * thrown away. Bits are "shifted in" by raising the input to the 4205 * Management Data Clock (setting the MDC bit), and then reading the 4206 * value of the MDIO bit. 4207 */ 4208 ctrl = E1000_READ_REG(hw, CTRL); 4209 /* 4210 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 4211 * input. 4212 */ 4213 ctrl &= ~E1000_CTRL_MDIO_DIR; 4214 ctrl &= ~E1000_CTRL_MDIO; 4215 4216 E1000_WRITE_REG(hw, CTRL, ctrl); 4217 E1000_WRITE_FLUSH(hw); 4218 /* 4219 * Raise and Lower the clock before reading in the data. This 4220 * accounts for the turnaround bits. The first clock occurred when we 4221 * clocked out the last bit of the Register Address. 4222 */ 4223 em_raise_mdi_clk(hw, &ctrl); 4224 em_lower_mdi_clk(hw, &ctrl); 4225 4226 for (data = 0, i = 0; i < 16; i++) { 4227 data = data << 1; 4228 em_raise_mdi_clk(hw, &ctrl); 4229 ctrl = E1000_READ_REG(hw, CTRL); 4230 /* Check to see if we shifted in a "1". */ 4231 if (ctrl & E1000_CTRL_MDIO) 4232 data |= 1; 4233 em_lower_mdi_clk(hw, &ctrl); 4234 } 4235 4236 em_raise_mdi_clk(hw, &ctrl); 4237 em_lower_mdi_clk(hw, &ctrl); 4238 4239 return data; 4240 } 4241 4242 STATIC int32_t 4243 em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) 4244 { 4245 uint32_t swfw_sync = 0; 4246 uint32_t swmask = mask; 4247 uint32_t fwmask = mask << 16; 4248 int32_t timeout = 200; 4249 DEBUGFUNC("em_swfw_sync_acquire"); 4250 4251 if (hw->swfwhw_semaphore_present) 4252 return em_get_software_flag(hw); 4253 4254 if (!hw->swfw_sync_present) 4255 return em_get_hw_eeprom_semaphore(hw); 4256 4257 while (timeout) { 4258 if (em_get_hw_eeprom_semaphore(hw)) 4259 return -E1000_ERR_SWFW_SYNC; 4260 4261 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4262 if (!(swfw_sync & (fwmask | swmask))) { 4263 break; 4264 } 4265 /* 4266 * firmware currently using resource (fwmask) 4267 * or other software thread currently using resource (swmask) 4268 */ 4269 em_put_hw_eeprom_semaphore(hw); 4270 msec_delay_irq(5); 4271 timeout--; 4272 } 4273 4274 if (!timeout) { 4275 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout." 4276 "\n"); 4277 return -E1000_ERR_SWFW_SYNC; 4278 } 4279 swfw_sync |= swmask; 4280 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4281 4282 em_put_hw_eeprom_semaphore(hw); 4283 return E1000_SUCCESS; 4284 } 4285 4286 STATIC void 4287 em_swfw_sync_release(struct em_hw *hw, uint16_t mask) 4288 { 4289 uint32_t swfw_sync; 4290 uint32_t swmask = mask; 4291 DEBUGFUNC("em_swfw_sync_release"); 4292 4293 if (hw->swfwhw_semaphore_present) { 4294 em_release_software_flag(hw); 4295 return; 4296 } 4297 if (!hw->swfw_sync_present) { 4298 em_put_hw_eeprom_semaphore(hw); 4299 return; 4300 } 4301 /* 4302 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; 4303 */ 4304 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); 4305 /* empty */ 4306 4307 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); 4308 swfw_sync &= ~swmask; 4309 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); 4310 4311 em_put_hw_eeprom_semaphore(hw); 4312 } 4313 4314 /**************************************************************************** 4315 * Read BM PHY wakeup register. It works as such: 4316 * 1) Set page 769, register 17, bit 2 = 1 4317 * 2) Set page to 800 for host (801 if we were manageability) 4318 * 3) Write the address using the address opcode (0x11) 4319 * 4) Read or write the data using the data opcode (0x12) 4320 * 5) Restore 769_17.2 to its original value 4321 ****************************************************************************/ 4322 int32_t 4323 em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr, 4324 uint16_t *phy_data, boolean_t read) 4325 { 4326 int32_t ret_val; 4327 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4328 uint16_t phy_reg = 0; 4329 4330 /* All operations in this function are phy address 1 */ 4331 hw->phy_addr = 1; 4332 4333 /* Set page 769 */ 4334 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4335 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4336 4337 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG, &phy_reg); 4338 if (ret_val) 4339 goto out; 4340 4341 /* First clear bit 4 to avoid a power state change */ 4342 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 4343 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4344 if (ret_val) 4345 goto out; 4346 4347 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 4348 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, 4349 phy_reg | BM_WUC_ENABLE_BIT); 4350 if (ret_val) 4351 goto out; 4352 4353 /* Select page 800 */ 4354 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4355 (BM_WUC_PAGE << PHY_PAGE_SHIFT)); 4356 4357 /* Write the page 800 offset value using opcode 0x11 */ 4358 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE, reg); 4359 if (ret_val) 4360 goto out; 4361 4362 if (read) 4363 /* Read the page 800 value using opcode 0x12 */ 4364 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4365 phy_data); 4366 else 4367 /* Write the page 800 value using opcode 0x12 */ 4368 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE, 4369 *phy_data); 4370 4371 if (ret_val) 4372 goto out; 4373 4374 /* 4375 * Restore 769_17.2 to its original value 4376 * Set page 769 4377 */ 4378 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4379 (BM_WUC_ENABLE_PAGE << PHY_PAGE_SHIFT)); 4380 4381 /* Clear 769_17.2 */ 4382 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG, phy_reg); 4383 if (ret_val) 4384 goto out; 4385 4386 out: 4387 return ret_val; 4388 } 4389 4390 /*************************************************************************** 4391 * Read HV PHY vendor specific high registers 4392 ***************************************************************************/ 4393 int32_t 4394 em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr, 4395 uint16_t *phy_data, boolean_t read) 4396 { 4397 int32_t ret_val; 4398 uint32_t addr_reg = 0; 4399 uint32_t data_reg = 0; 4400 4401 /* This takes care of the difference with desktop vs mobile phy */ 4402 addr_reg = (hw->phy_type == em_phy_82578) ? 4403 I82578_PHY_ADDR_REG : I82577_PHY_ADDR_REG; 4404 data_reg = addr_reg + 1; 4405 4406 /* All operations in this function are phy address 2 */ 4407 hw->phy_addr = 2; 4408 4409 /* masking with 0x3F to remove the page from offset */ 4410 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F); 4411 if (ret_val) { 4412 printf("Could not write PHY the HV address register\n"); 4413 goto out; 4414 } 4415 4416 /* Read or write the data value next */ 4417 if (read) 4418 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data); 4419 else 4420 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data); 4421 4422 if (ret_val) { 4423 printf("Could not read data value from HV data register\n"); 4424 goto out; 4425 } 4426 4427 out: 4428 return ret_val; 4429 } 4430 4431 /****************************************************************************** 4432 * Reads or writes the value from a PHY register, if the value is on a specific 4433 * non zero page, sets the page first. 4434 * hw - Struct containing variables accessed by shared code 4435 * reg_addr - address of the PHY register to read 4436 *****************************************************************************/ 4437 int32_t 4438 em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data, 4439 boolean_t read) 4440 { 4441 uint32_t ret_val; 4442 uint16_t swfw; 4443 uint16_t page = BM_PHY_REG_PAGE(reg_addr); 4444 uint16_t reg = BM_PHY_REG_NUM(reg_addr); 4445 4446 DEBUGFUNC("em_access_phy_reg_hv"); 4447 4448 swfw = E1000_SWFW_PHY0_SM; 4449 4450 if (em_swfw_sync_acquire(hw, swfw)) 4451 return -E1000_ERR_SWFW_SYNC; 4452 4453 if (page == BM_WUC_PAGE) { 4454 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr, 4455 phy_data, read); 4456 goto release; 4457 } 4458 4459 if (page >= HV_INTC_FC_PAGE_START) 4460 hw->phy_addr = 1; 4461 else 4462 hw->phy_addr = 2; 4463 4464 if (page == HV_INTC_FC_PAGE_START) 4465 page = 0; 4466 4467 /* 4468 * Workaround MDIO accesses being disabled after entering IEEE Power 4469 * Down (whenever bit 11 of the PHY Control register is set) 4470 */ 4471 if (!read && 4472 (hw->phy_type == em_phy_82578) && 4473 (hw->phy_revision >= 1) && 4474 (hw->phy_addr == 2) && 4475 ((MAX_PHY_REG_ADDRESS & reg) == 0) && 4476 (*phy_data & (1 << 11))) { 4477 uint16_t data2 = 0x7EFF; 4478 4479 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, 4480 &data2, FALSE); 4481 if (ret_val) 4482 return ret_val; 4483 } 4484 4485 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4486 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4487 (page << PHY_PAGE_SHIFT)); 4488 if (ret_val) 4489 return ret_val; 4490 } 4491 if (read) 4492 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4493 phy_data); 4494 else 4495 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg, 4496 *phy_data); 4497 release: 4498 em_swfw_sync_release(hw, swfw); 4499 return ret_val; 4500 } 4501 4502 /****************************************************************************** 4503 * Reads the value from a PHY register, if the value is on a specific non zero 4504 * page, sets the page first. 4505 * hw - Struct containing variables accessed by shared code 4506 * reg_addr - address of the PHY register to read 4507 *****************************************************************************/ 4508 int32_t 4509 em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4510 { 4511 uint32_t ret_val; 4512 uint16_t swfw; 4513 DEBUGFUNC("em_read_phy_reg"); 4514 4515 if (hw->mac_type == em_pchlan || 4516 hw->mac_type == em_pch2lan || 4517 hw->mac_type == em_pch_lpt) 4518 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE)); 4519 4520 if (((hw->mac_type == em_80003es2lan) || (hw->mac_type == em_82575)) && 4521 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { 4522 swfw = E1000_SWFW_PHY1_SM; 4523 } else { 4524 swfw = E1000_SWFW_PHY0_SM; 4525 } 4526 if (em_swfw_sync_acquire(hw, swfw)) 4527 return -E1000_ERR_SWFW_SYNC; 4528 4529 if ((hw->phy_type == em_phy_igp || 4530 hw->phy_type == em_phy_igp_3 || 4531 hw->phy_type == em_phy_igp_2) && 4532 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4533 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4534 (uint16_t) reg_addr); 4535 if (ret_val) { 4536 em_swfw_sync_release(hw, swfw); 4537 return ret_val; 4538 } 4539 } else if (hw->phy_type == em_phy_gg82563) { 4540 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4541 (hw->mac_type == em_80003es2lan)) { 4542 /* Select Configuration Page */ 4543 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4544 GG82563_MIN_ALT_REG) { 4545 ret_val = em_write_phy_reg_ex(hw, 4546 GG82563_PHY_PAGE_SELECT, 4547 (uint16_t) ((uint16_t) reg_addr >> 4548 GG82563_PAGE_SHIFT)); 4549 } else { 4550 /* 4551 * Use Alternative Page Select register to 4552 * access registers 30 and 31 4553 */ 4554 ret_val = em_write_phy_reg_ex(hw, 4555 GG82563_PHY_PAGE_SELECT_ALT, 4556 (uint16_t) ((uint16_t) reg_addr >> 4557 GG82563_PAGE_SHIFT)); 4558 } 4559 4560 if (ret_val) { 4561 em_swfw_sync_release(hw, swfw); 4562 return ret_val; 4563 } 4564 } 4565 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4566 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4567 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4568 (uint16_t) ((uint16_t) reg_addr >> 4569 PHY_PAGE_SHIFT)); 4570 if (ret_val) 4571 return ret_val; 4572 } 4573 } 4574 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4575 phy_data); 4576 4577 em_swfw_sync_release(hw, swfw); 4578 return ret_val; 4579 } 4580 4581 STATIC int32_t 4582 em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) 4583 { 4584 uint32_t i; 4585 uint32_t mdic = 0; 4586 DEBUGFUNC("em_read_phy_reg_ex"); 4587 4588 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4589 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4590 return -E1000_ERR_PARAM; 4591 } 4592 if (hw->mac_type == em_icp_xxxx) { 4593 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num, 4594 reg_addr); 4595 return E1000_SUCCESS; 4596 } 4597 if (hw->mac_type > em_82543) { 4598 /* 4599 * Set up Op-code, Phy Address, and register address in the 4600 * MDI Control register. The MAC will take care of 4601 * interfacing with the PHY to retrieve the desired data. 4602 */ 4603 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | 4604 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4605 (E1000_MDIC_OP_READ)); 4606 4607 E1000_WRITE_REG(hw, MDIC, mdic); 4608 4609 /* 4610 * Poll the ready bit to see if the MDI read completed 4611 * Increasing the time out as testing showed failures with 4612 * the lower time out (from FreeBSD driver) 4613 */ 4614 for (i = 0; i < 1960; i++) { 4615 usec_delay(50); 4616 mdic = E1000_READ_REG(hw, MDIC); 4617 if (mdic & E1000_MDIC_READY) 4618 break; 4619 } 4620 if (!(mdic & E1000_MDIC_READY)) { 4621 DEBUGOUT("MDI Read did not complete\n"); 4622 return -E1000_ERR_PHY; 4623 } 4624 if (mdic & E1000_MDIC_ERROR) { 4625 DEBUGOUT("MDI Error\n"); 4626 return -E1000_ERR_PHY; 4627 } 4628 *phy_data = (uint16_t) mdic; 4629 4630 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt) 4631 usec_delay(100); 4632 } else { 4633 /* 4634 * We must first send a preamble through the MDIO pin to 4635 * signal the beginning of an MII instruction. This is done 4636 * by sending 32 consecutive "1" bits. 4637 */ 4638 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4639 /* 4640 * Now combine the next few fields that are required for a 4641 * read operation. We use this method instead of calling the 4642 * em_shift_out_mdi_bits routine five different times. The 4643 * format of a MII read instruction consists of a shift out 4644 * of 14 bits and is defined as follows: <Preamble><SOF><Op 4645 * Code><Phy Addr><Reg Addr> followed by a shift in of 18 4646 * bits. This first two bits shifted in are TurnAround bits 4647 * used to avoid contention on the MDIO pin when a READ 4648 * operation is performed. These two bits are thrown away 4649 * followed by a shift in of 16 bits which contains the 4650 * desired data. 4651 */ 4652 mdic = ((reg_addr) | (hw->phy_addr << 5) | 4653 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 4654 4655 em_shift_out_mdi_bits(hw, mdic, 14); 4656 /* 4657 * Now that we've shifted out the read command to the MII, we 4658 * need to "shift in" the 16-bit value (18 total bits) of the 4659 * requested PHY register address. 4660 */ 4661 *phy_data = em_shift_in_mdi_bits(hw); 4662 } 4663 return E1000_SUCCESS; 4664 } 4665 4666 /****************************************************************************** 4667 * Writes a value to a PHY register 4668 * 4669 * hw - Struct containing variables accessed by shared code 4670 * reg_addr - address of the PHY register to write 4671 * data - data to write to the PHY 4672 *****************************************************************************/ 4673 int32_t 4674 em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4675 { 4676 uint32_t ret_val; 4677 DEBUGFUNC("em_write_phy_reg"); 4678 4679 if (hw->mac_type == em_pchlan || 4680 hw->mac_type == em_pch2lan || 4681 hw->mac_type == em_pch_lpt) 4682 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE)); 4683 4684 if (em_swfw_sync_acquire(hw, hw->swfw)) 4685 return -E1000_ERR_SWFW_SYNC; 4686 4687 if ((hw->phy_type == em_phy_igp || 4688 hw->phy_type == em_phy_igp_3 || 4689 hw->phy_type == em_phy_igp_2) && 4690 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { 4691 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, 4692 (uint16_t) reg_addr); 4693 if (ret_val) { 4694 em_swfw_sync_release(hw, hw->swfw); 4695 return ret_val; 4696 } 4697 } else if (hw->phy_type == em_phy_gg82563) { 4698 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || 4699 (hw->mac_type == em_80003es2lan)) { 4700 /* Select Configuration Page */ 4701 if ((reg_addr & MAX_PHY_REG_ADDRESS) < 4702 GG82563_MIN_ALT_REG) { 4703 ret_val = em_write_phy_reg_ex(hw, 4704 GG82563_PHY_PAGE_SELECT, 4705 (uint16_t) ((uint16_t) reg_addr >> 4706 GG82563_PAGE_SHIFT)); 4707 } else { 4708 /* 4709 * Use Alternative Page Select register to 4710 * access registers 30 and 31 4711 */ 4712 ret_val = em_write_phy_reg_ex(hw, 4713 GG82563_PHY_PAGE_SELECT_ALT, 4714 (uint16_t) ((uint16_t) reg_addr >> 4715 GG82563_PAGE_SHIFT)); 4716 } 4717 4718 if (ret_val) { 4719 em_swfw_sync_release(hw, hw->swfw); 4720 return ret_val; 4721 } 4722 } 4723 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { 4724 if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { 4725 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, 4726 (uint16_t) ((uint16_t) reg_addr >> 4727 PHY_PAGE_SHIFT)); 4728 if (ret_val) 4729 return ret_val; 4730 } 4731 } 4732 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, 4733 phy_data); 4734 4735 em_swfw_sync_release(hw, hw->swfw); 4736 return ret_val; 4737 } 4738 4739 STATIC int32_t 4740 em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) 4741 { 4742 uint32_t i; 4743 uint32_t mdic = 0; 4744 DEBUGFUNC("em_write_phy_reg_ex"); 4745 4746 if (reg_addr > MAX_PHY_REG_ADDRESS) { 4747 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); 4748 return -E1000_ERR_PARAM; 4749 } 4750 if (hw->mac_type == em_icp_xxxx) { 4751 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num, 4752 reg_addr, phy_data); 4753 return E1000_SUCCESS; 4754 } 4755 if (hw->mac_type > em_82543) { 4756 /* 4757 * Set up Op-code, Phy Address, register address, and data 4758 * intended for the PHY register in the MDI Control register. 4759 * The MAC will take care of interfacing with the PHY to send 4760 * the desired data. 4761 */ 4762 mdic = (((uint32_t) phy_data) | 4763 (reg_addr << E1000_MDIC_REG_SHIFT) | 4764 (hw->phy_addr << E1000_MDIC_PHY_SHIFT) | 4765 (E1000_MDIC_OP_WRITE)); 4766 4767 E1000_WRITE_REG(hw, MDIC, mdic); 4768 4769 /* Poll the ready bit to see if the MDI read completed */ 4770 for (i = 0; i < 641; i++) { 4771 usec_delay(5); 4772 mdic = E1000_READ_REG(hw, MDIC); 4773 if (mdic & E1000_MDIC_READY) 4774 break; 4775 } 4776 if (!(mdic & E1000_MDIC_READY)) { 4777 DEBUGOUT("MDI Write did not complete\n"); 4778 return -E1000_ERR_PHY; 4779 } 4780 4781 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt) 4782 usec_delay(100); 4783 } else { 4784 /* 4785 * We'll need to use the SW defined pins to shift the write 4786 * command out to the PHY. We first send a preamble to the 4787 * PHY to signal the beginning of the MII instruction. This 4788 * is done by sending 32 consecutive "1" bits. 4789 */ 4790 em_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 4791 /* 4792 * Now combine the remaining required fields that will 4793 * indicate a write operation. We use this method instead of 4794 * calling the em_shift_out_mdi_bits routine for each field 4795 * in the command. The format of a MII write instruction is 4796 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg 4797 * Addr><Turnaround><Data>. 4798 */ 4799 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | 4800 (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | 4801 (PHY_SOF << 14)); 4802 mdic <<= 16; 4803 mdic |= (uint32_t) phy_data; 4804 4805 em_shift_out_mdi_bits(hw, mdic, 32); 4806 } 4807 4808 return E1000_SUCCESS; 4809 } 4810 4811 STATIC int32_t 4812 em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data) 4813 { 4814 uint32_t reg_val; 4815 DEBUGFUNC("em_read_kmrn_reg"); 4816 4817 if (em_swfw_sync_acquire(hw, hw->swfw)) 4818 return -E1000_ERR_SWFW_SYNC; 4819 4820 /* Write register address */ 4821 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 4822 E1000_KUMCTRLSTA_OFFSET) | 4823 E1000_KUMCTRLSTA_REN; 4824 4825 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 4826 usec_delay(2); 4827 4828 /* Read the data returned */ 4829 reg_val = E1000_READ_REG(hw, KUMCTRLSTA); 4830 *data = (uint16_t) reg_val; 4831 4832 em_swfw_sync_release(hw, hw->swfw); 4833 return E1000_SUCCESS; 4834 } 4835 4836 STATIC int32_t 4837 em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data) 4838 { 4839 uint32_t reg_val; 4840 DEBUGFUNC("em_write_kmrn_reg"); 4841 4842 if (em_swfw_sync_acquire(hw, hw->swfw)) 4843 return -E1000_ERR_SWFW_SYNC; 4844 4845 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & 4846 E1000_KUMCTRLSTA_OFFSET) | data; 4847 4848 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); 4849 usec_delay(2); 4850 4851 em_swfw_sync_release(hw, hw->swfw); 4852 return E1000_SUCCESS; 4853 } 4854 4855 /****************************************************************************** 4856 * Returns the PHY to the power-on reset state 4857 * 4858 * hw - Struct containing variables accessed by shared code 4859 *****************************************************************************/ 4860 int32_t 4861 em_phy_hw_reset(struct em_hw *hw) 4862 { 4863 uint32_t ctrl, ctrl_ext; 4864 uint32_t led_ctrl; 4865 int32_t ret_val; 4866 DEBUGFUNC("em_phy_hw_reset"); 4867 /* 4868 * In the case of the phy reset being blocked, it's not an error, we 4869 * simply return success without performing the reset. 4870 */ 4871 ret_val = em_check_phy_reset_block(hw); 4872 if (ret_val) 4873 return E1000_SUCCESS; 4874 4875 DEBUGOUT("Resetting Phy...\n"); 4876 4877 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) { 4878 if (em_swfw_sync_acquire(hw, hw->swfw)) { 4879 DEBUGOUT("Unable to acquire swfw sync\n"); 4880 return -E1000_ERR_SWFW_SYNC; 4881 } 4882 /* 4883 * Read the device control register and assert the 4884 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For 4885 * pre-em_82571 hardware, we delay for 10ms between the 4886 * assert and deassert. For em_82571 hardware and later, we 4887 * instead delay for 50us between and 10ms after the 4888 * deassertion. 4889 */ 4890 ctrl = E1000_READ_REG(hw, CTRL); 4891 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); 4892 E1000_WRITE_FLUSH(hw); 4893 4894 if (hw->mac_type < em_82571) 4895 msec_delay(10); 4896 else 4897 usec_delay(100); 4898 4899 E1000_WRITE_REG(hw, CTRL, ctrl); 4900 E1000_WRITE_FLUSH(hw); 4901 4902 if (hw->mac_type >= em_82571) 4903 msec_delay_irq(10); 4904 em_swfw_sync_release(hw, hw->swfw); 4905 /* 4906 * the M88E1141_E_PHY_ID might need reset here, but nothing 4907 * proves it 4908 */ 4909 } else { 4910 /* 4911 * Read the Extended Device Control Register, assert the 4912 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it 4913 * out of reset. 4914 */ 4915 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 4916 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 4917 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 4918 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4919 E1000_WRITE_FLUSH(hw); 4920 msec_delay(10); 4921 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 4922 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 4923 E1000_WRITE_FLUSH(hw); 4924 } 4925 usec_delay(150); 4926 4927 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { 4928 /* Configure activity LED after PHY reset */ 4929 led_ctrl = E1000_READ_REG(hw, LEDCTL); 4930 led_ctrl &= IGP_ACTIVITY_LED_MASK; 4931 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 4932 E1000_WRITE_REG(hw, LEDCTL, led_ctrl); 4933 } 4934 /* Wait for FW to finish PHY configuration. */ 4935 ret_val = em_get_phy_cfg_done(hw); 4936 if (ret_val != E1000_SUCCESS) 4937 return ret_val; 4938 em_release_software_semaphore(hw); 4939 4940 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3)) 4941 ret_val = em_init_lcd_from_nvm(hw); 4942 4943 return ret_val; 4944 } 4945 4946 /***************************************************************************** 4947 * SW-based LCD Configuration. 4948 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 4949 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 4950 * in NVM determines whether HW should configure LPLU and Gbe Disable. 4951 *****************************************************************************/ 4952 int32_t 4953 em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state) 4954 { 4955 int32_t ret_val = E1000_SUCCESS; 4956 uint32_t mac_reg; 4957 uint16_t oem_reg; 4958 uint16_t swfw = E1000_SWFW_PHY0_SM; 4959 4960 if (hw->mac_type < em_pchlan) 4961 return ret_val; 4962 4963 ret_val = em_swfw_sync_acquire(hw, swfw); 4964 if (ret_val) 4965 return ret_val; 4966 4967 if (hw->mac_type == em_pchlan) { 4968 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL); 4969 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 4970 goto out; 4971 } 4972 4973 mac_reg = E1000_READ_REG(hw, FEXTNVM); 4974 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M)) 4975 goto out; 4976 4977 mac_reg = E1000_READ_REG(hw, PHY_CTRL); 4978 4979 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 4980 if (ret_val) 4981 goto out; 4982 4983 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 4984 4985 if (d0_state) { 4986 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 4987 oem_reg |= HV_OEM_BITS_GBE_DIS; 4988 4989 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 4990 oem_reg |= HV_OEM_BITS_LPLU; 4991 /* Restart auto-neg to activate the bits */ 4992 if (!em_check_phy_reset_block(hw)) 4993 oem_reg |= HV_OEM_BITS_RESTART_AN; 4994 4995 } else { 4996 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 4997 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 4998 oem_reg |= HV_OEM_BITS_GBE_DIS; 4999 5000 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 5001 E1000_PHY_CTRL_NOND0A_LPLU)) 5002 oem_reg |= HV_OEM_BITS_LPLU; 5003 } 5004 5005 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 5006 5007 out: 5008 em_swfw_sync_release(hw, swfw); 5009 5010 return ret_val; 5011 } 5012 5013 5014 /****************************************************************************** 5015 * Resets the PHY 5016 * 5017 * hw - Struct containing variables accessed by shared code 5018 * 5019 * Sets bit 15 of the MII Control regiser 5020 *****************************************************************************/ 5021 int32_t 5022 em_phy_reset(struct em_hw *hw) 5023 { 5024 int32_t ret_val; 5025 uint16_t phy_data; 5026 DEBUGFUNC("em_phy_reset"); 5027 /* 5028 * In the case of the phy reset being blocked, it's not an error, we 5029 * simply return success without performing the reset. 5030 */ 5031 ret_val = em_check_phy_reset_block(hw); 5032 if (ret_val) 5033 return E1000_SUCCESS; 5034 5035 switch (hw->phy_type) { 5036 case em_phy_igp: 5037 case em_phy_igp_2: 5038 case em_phy_igp_3: 5039 case em_phy_ife: 5040 ret_val = em_phy_hw_reset(hw); 5041 if (ret_val) 5042 return ret_val; 5043 break; 5044 default: 5045 ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data); 5046 if (ret_val) 5047 return ret_val; 5048 5049 phy_data |= MII_CR_RESET; 5050 ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data); 5051 if (ret_val) 5052 return ret_val; 5053 5054 usec_delay(1); 5055 break; 5056 } 5057 5058 /* Allow time for h/w to get to a quiescent state after reset */ 5059 msec_delay(10); 5060 5061 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2) 5062 em_phy_init_script(hw); 5063 5064 if (hw->mac_type == em_pchlan) { 5065 ret_val = em_hv_phy_workarounds_ich8lan(hw); 5066 if (ret_val) 5067 return ret_val; 5068 } else if (hw->mac_type == em_pch2lan) { 5069 ret_val = em_lv_phy_workarounds_ich8lan(hw); 5070 if (ret_val) 5071 return ret_val; 5072 } 5073 5074 if (hw->mac_type >= em_pchlan) { 5075 ret_val = em_oem_bits_config_pchlan(hw, TRUE); 5076 if (ret_val) 5077 return ret_val; 5078 } 5079 5080 /* Ungate automatic PHY configuration on non-managed 82579 */ 5081 if ((hw->mac_type == em_pch2lan) && 5082 !(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) { 5083 msec_delay(10); 5084 em_gate_hw_phy_config_ich8lan(hw, FALSE); 5085 } 5086 5087 return E1000_SUCCESS; 5088 } 5089 5090 /****************************************************************************** 5091 * Work-around for 82566 Kumeran PCS lock loss: 5092 * On link status change (i.e. PCI reset, speed change) and link is up and 5093 * speed is gigabit- 5094 * 0) if workaround is optionally disabled do nothing 5095 * 1) wait 1ms for Kumeran link to come up 5096 * 2) check Kumeran Diagnostic register PCS lock loss bit 5097 * 3) if not set the link is locked (all is good), otherwise... 5098 * 4) reset the PHY 5099 * 5) repeat up to 10 times 5100 * Note: this is only called for IGP3 copper when speed is 1gb. 5101 * 5102 * hw - struct containing variables accessed by shared code 5103 *****************************************************************************/ 5104 STATIC int32_t 5105 em_kumeran_lock_loss_workaround(struct em_hw *hw) 5106 { 5107 int32_t ret_val; 5108 int32_t reg; 5109 int32_t cnt; 5110 uint16_t phy_data; 5111 if (hw->kmrn_lock_loss_workaround_disabled) 5112 return E1000_SUCCESS; 5113 /* 5114 * Make sure link is up before proceeding. If not just return. 5115 * Attempting this while link is negotiating fouled up link stability 5116 */ 5117 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5118 ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data); 5119 5120 if (phy_data & MII_SR_LINK_STATUS) { 5121 for (cnt = 0; cnt < 10; cnt++) { 5122 /* read once to clear */ 5123 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, 5124 &phy_data); 5125 if (ret_val) 5126 return ret_val; 5127 /* and again to get new status */ 5128 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); 5129 if (ret_val) 5130 return ret_val; 5131 5132 /* check for PCS lock */ 5133 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5134 return E1000_SUCCESS; 5135 5136 /* Issue PHY reset */ 5137 em_phy_hw_reset(hw); 5138 msec_delay_irq(5); 5139 } 5140 /* Disable GigE link negotiation */ 5141 reg = E1000_READ_REG(hw, PHY_CTRL); 5142 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE 5143 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5144 5145 /* unable to acquire PCS lock */ 5146 return E1000_ERR_PHY; 5147 } 5148 return E1000_SUCCESS; 5149 } 5150 5151 /****************************************************************************** 5152 * Reads and matches the expected PHY address for known PHY IDs 5153 * 5154 * hw - Struct containing variables accessed by shared code 5155 *****************************************************************************/ 5156 STATIC int32_t 5157 em_match_gig_phy(struct em_hw *hw) 5158 { 5159 int32_t phy_init_status, ret_val; 5160 uint16_t phy_id_high, phy_id_low; 5161 boolean_t match = FALSE; 5162 DEBUGFUNC("em_match_gig_phy"); 5163 5164 ret_val = em_read_phy_reg(hw, PHY_ID1, &phy_id_high); 5165 if (ret_val) 5166 return ret_val; 5167 5168 hw->phy_id = (uint32_t) (phy_id_high << 16); 5169 usec_delay(20); 5170 ret_val = em_read_phy_reg(hw, PHY_ID2, &phy_id_low); 5171 if (ret_val) 5172 return ret_val; 5173 5174 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); 5175 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; 5176 5177 switch (hw->mac_type) { 5178 case em_82543: 5179 if (hw->phy_id == M88E1000_E_PHY_ID) 5180 match = TRUE; 5181 break; 5182 case em_82544: 5183 if (hw->phy_id == M88E1000_I_PHY_ID) 5184 match = TRUE; 5185 break; 5186 case em_82540: 5187 case em_82545: 5188 case em_82545_rev_3: 5189 case em_82546: 5190 case em_82546_rev_3: 5191 if (hw->phy_id == M88E1011_I_PHY_ID) 5192 match = TRUE; 5193 break; 5194 case em_82541: 5195 case em_82541_rev_2: 5196 case em_82547: 5197 case em_82547_rev_2: 5198 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5199 match = TRUE; 5200 break; 5201 case em_82573: 5202 if (hw->phy_id == M88E1111_I_PHY_ID) 5203 match = TRUE; 5204 break; 5205 case em_82574: 5206 if (hw->phy_id == BME1000_E_PHY_ID) 5207 match = TRUE; 5208 break; 5209 case em_82575: 5210 if (hw->phy_id == M88E1000_E_PHY_ID) 5211 match = TRUE; 5212 if (hw->phy_id == IGP01E1000_I_PHY_ID) 5213 match = TRUE; 5214 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5215 match = TRUE; 5216 break; 5217 case em_82580: 5218 case em_i210: 5219 case em_i350: 5220 if (hw->phy_id == I82580_I_PHY_ID || 5221 hw->phy_id == I210_I_PHY_ID || 5222 hw->phy_id == I347AT4_E_PHY_ID || 5223 hw->phy_id == I350_I_PHY_ID || 5224 hw->phy_id == M88E1112_E_PHY_ID || 5225 hw->phy_id == M88E1543_E_PHY_ID) { 5226 uint32_t mdic; 5227 5228 mdic = EM_READ_REG(hw, E1000_MDICNFG); 5229 mdic &= E1000_MDICNFG_PHY_MASK; 5230 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 5231 DEBUGOUT1("MDICNFG PHY ADDR %d", 5232 mdic >> E1000_MDICNFG_PHY_SHIFT); 5233 match = TRUE; 5234 } 5235 break; 5236 case em_80003es2lan: 5237 if (hw->phy_id == GG82563_E_PHY_ID) 5238 match = TRUE; 5239 break; 5240 case em_ich8lan: 5241 case em_ich9lan: 5242 case em_ich10lan: 5243 case em_pchlan: 5244 case em_pch2lan: 5245 if (hw->phy_id == IGP03E1000_E_PHY_ID) 5246 match = TRUE; 5247 if (hw->phy_id == IFE_E_PHY_ID) 5248 match = TRUE; 5249 if (hw->phy_id == IFE_PLUS_E_PHY_ID) 5250 match = TRUE; 5251 if (hw->phy_id == IFE_C_E_PHY_ID) 5252 match = TRUE; 5253 if (hw->phy_id == BME1000_E_PHY_ID) 5254 match = TRUE; 5255 if (hw->phy_id == I82577_E_PHY_ID) 5256 match = TRUE; 5257 if (hw->phy_id == I82578_E_PHY_ID) 5258 match = TRUE; 5259 if (hw->phy_id == I82579_E_PHY_ID) 5260 match = TRUE; 5261 break; 5262 case em_pch_lpt: 5263 if (hw->phy_id == I217_E_PHY_ID) 5264 match = TRUE; 5265 break; 5266 case em_icp_xxxx: 5267 if (hw->phy_id == M88E1141_E_PHY_ID) 5268 match = TRUE; 5269 break; 5270 default: 5271 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); 5272 return -E1000_ERR_CONFIG; 5273 } 5274 phy_init_status = em_set_phy_type(hw); 5275 5276 if ((match) && (phy_init_status == E1000_SUCCESS)) { 5277 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); 5278 return E1000_SUCCESS; 5279 } 5280 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); 5281 return -E1000_ERR_PHY; 5282 } 5283 5284 /****************************************************************************** 5285 * Probes the expected PHY address for known PHY IDs 5286 * 5287 * hw - Struct containing variables accessed by shared code 5288 *****************************************************************************/ 5289 STATIC int32_t 5290 em_detect_gig_phy(struct em_hw *hw) 5291 { 5292 int32_t ret_val; 5293 DEBUGFUNC("em_detect_gig_phy"); 5294 5295 if (hw->phy_id != 0) 5296 return E1000_SUCCESS; 5297 5298 /* default phy address, most phys reside here, but not all (ICH10) */ 5299 if (hw->mac_type != em_icp_xxxx) 5300 hw->phy_addr = 1; 5301 else 5302 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */ 5303 5304 /* 5305 * The 82571 firmware may still be configuring the PHY. In this 5306 * case, we cannot access the PHY until the configuration is done. 5307 * So we explicitly set the PHY values. 5308 */ 5309 if (hw->mac_type == em_82571 || 5310 hw->mac_type == em_82572) { 5311 hw->phy_id = IGP01E1000_I_PHY_ID; 5312 hw->phy_type = em_phy_igp_2; 5313 return E1000_SUCCESS; 5314 } 5315 5316 /* 5317 * Some of the fiber cards dont have a phy, so we must exit cleanly 5318 * here 5319 */ 5320 if ((hw->media_type == em_media_type_fiber) && 5321 (hw->mac_type == em_82542_rev2_0 || 5322 hw->mac_type == em_82542_rev2_1 || 5323 hw->mac_type == em_82543 || 5324 hw->mac_type == em_82574 || 5325 hw->mac_type == em_82573 || 5326 hw->mac_type == em_82574 || 5327 hw->mac_type == em_80003es2lan)) { 5328 hw->phy_type = em_phy_undefined; 5329 return E1000_SUCCESS; 5330 } 5331 5332 if ((hw->media_type == em_media_type_internal_serdes || 5333 hw->media_type == em_media_type_fiber) && 5334 hw->mac_type >= em_82575) { 5335 hw->phy_type = em_phy_undefined; 5336 return E1000_SUCCESS; 5337 } 5338 5339 /* 5340 * Up to 82543 (incl), we need reset the phy, or it might not get 5341 * detected 5342 */ 5343 if (hw->mac_type <= em_82543) { 5344 ret_val = em_phy_hw_reset(hw); 5345 if (ret_val) 5346 return ret_val; 5347 } 5348 /* 5349 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a 5350 * work- around that forces PHY page 0 to be set or the reads fail. 5351 * The rest of the code in this routine uses em_read_phy_reg to read 5352 * the PHY ID. So for ESB-2 we need to have this set so our reads 5353 * won't fail. If the attached PHY is not a em_phy_gg82563, the 5354 * routines below will figure this out as well. 5355 */ 5356 if (hw->mac_type == em_80003es2lan) 5357 hw->phy_type = em_phy_gg82563; 5358 5359 /* Power on SGMII phy if it is disabled */ 5360 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 || 5361 hw->mac_type == em_i350) { 5362 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT); 5363 EM_WRITE_REG(hw, E1000_CTRL_EXT, 5364 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 5365 delay(300); 5366 } 5367 5368 /* Read the PHY ID Registers to identify which PHY is onboard. */ 5369 for (hw->phy_addr = 1; (hw->phy_addr < 4); hw->phy_addr++) { 5370 ret_val = em_match_gig_phy(hw); 5371 if (ret_val == E1000_SUCCESS) 5372 return E1000_SUCCESS; 5373 } 5374 return -E1000_ERR_PHY; 5375 } 5376 5377 /****************************************************************************** 5378 * Resets the PHY's DSP 5379 * 5380 * hw - Struct containing variables accessed by shared code 5381 *****************************************************************************/ 5382 static int32_t 5383 em_phy_reset_dsp(struct em_hw *hw) 5384 { 5385 int32_t ret_val; 5386 DEBUGFUNC("em_phy_reset_dsp"); 5387 5388 do { 5389 if (hw->phy_type != em_phy_gg82563) { 5390 ret_val = em_write_phy_reg(hw, 29, 0x001d); 5391 if (ret_val) 5392 break; 5393 } 5394 ret_val = em_write_phy_reg(hw, 30, 0x00c1); 5395 if (ret_val) 5396 break; 5397 ret_val = em_write_phy_reg(hw, 30, 0x0000); 5398 if (ret_val) 5399 break; 5400 ret_val = E1000_SUCCESS; 5401 } while (0); 5402 5403 return ret_val; 5404 } 5405 5406 /****************************************************************************** 5407 * Sets up eeprom variables in the hw struct. Must be called after mac_type 5408 * is configured. Additionally, if this is ICH8, the flash controller GbE 5409 * registers must be mapped, or this will crash. 5410 * 5411 * hw - Struct containing variables accessed by shared code 5412 *****************************************************************************/ 5413 int32_t 5414 em_init_eeprom_params(struct em_hw *hw) 5415 { 5416 struct em_eeprom_info *eeprom = &hw->eeprom; 5417 uint32_t eecd = E1000_READ_REG(hw, EECD); 5418 int32_t ret_val = E1000_SUCCESS; 5419 uint16_t eeprom_size; 5420 DEBUGFUNC("em_init_eeprom_params"); 5421 5422 switch (hw->mac_type) { 5423 case em_82542_rev2_0: 5424 case em_82542_rev2_1: 5425 case em_82543: 5426 case em_82544: 5427 eeprom->type = em_eeprom_microwire; 5428 eeprom->word_size = 64; 5429 eeprom->opcode_bits = 3; 5430 eeprom->address_bits = 6; 5431 eeprom->delay_usec = 50; 5432 eeprom->use_eerd = FALSE; 5433 eeprom->use_eewr = FALSE; 5434 break; 5435 case em_82540: 5436 case em_82545: 5437 case em_82545_rev_3: 5438 case em_icp_xxxx: 5439 case em_82546: 5440 case em_82546_rev_3: 5441 eeprom->type = em_eeprom_microwire; 5442 eeprom->opcode_bits = 3; 5443 eeprom->delay_usec = 50; 5444 if (eecd & E1000_EECD_SIZE) { 5445 eeprom->word_size = 256; 5446 eeprom->address_bits = 8; 5447 } else { 5448 eeprom->word_size = 64; 5449 eeprom->address_bits = 6; 5450 } 5451 eeprom->use_eerd = FALSE; 5452 eeprom->use_eewr = FALSE; 5453 break; 5454 case em_82541: 5455 case em_82541_rev_2: 5456 case em_82547: 5457 case em_82547_rev_2: 5458 if (eecd & E1000_EECD_TYPE) { 5459 eeprom->type = em_eeprom_spi; 5460 eeprom->opcode_bits = 8; 5461 eeprom->delay_usec = 1; 5462 if (eecd & E1000_EECD_ADDR_BITS) { 5463 eeprom->page_size = 32; 5464 eeprom->address_bits = 16; 5465 } else { 5466 eeprom->page_size = 8; 5467 eeprom->address_bits = 8; 5468 } 5469 } else { 5470 eeprom->type = em_eeprom_microwire; 5471 eeprom->opcode_bits = 3; 5472 eeprom->delay_usec = 50; 5473 if (eecd & E1000_EECD_ADDR_BITS) { 5474 eeprom->word_size = 256; 5475 eeprom->address_bits = 8; 5476 } else { 5477 eeprom->word_size = 64; 5478 eeprom->address_bits = 6; 5479 } 5480 } 5481 eeprom->use_eerd = FALSE; 5482 eeprom->use_eewr = FALSE; 5483 break; 5484 case em_82571: 5485 case em_82572: 5486 eeprom->type = em_eeprom_spi; 5487 eeprom->opcode_bits = 8; 5488 eeprom->delay_usec = 1; 5489 if (eecd & E1000_EECD_ADDR_BITS) { 5490 eeprom->page_size = 32; 5491 eeprom->address_bits = 16; 5492 } else { 5493 eeprom->page_size = 8; 5494 eeprom->address_bits = 8; 5495 } 5496 eeprom->use_eerd = FALSE; 5497 eeprom->use_eewr = FALSE; 5498 break; 5499 case em_82573: 5500 case em_82574: 5501 case em_82575: 5502 case em_82580: 5503 case em_i210: 5504 case em_i350: 5505 eeprom->type = em_eeprom_spi; 5506 eeprom->opcode_bits = 8; 5507 eeprom->delay_usec = 1; 5508 if (eecd & E1000_EECD_ADDR_BITS) { 5509 eeprom->page_size = 32; 5510 eeprom->address_bits = 16; 5511 } else { 5512 eeprom->page_size = 8; 5513 eeprom->address_bits = 8; 5514 } 5515 eeprom->use_eerd = TRUE; 5516 eeprom->use_eewr = TRUE; 5517 if (em_is_onboard_nvm_eeprom(hw) == FALSE) { 5518 eeprom->type = em_eeprom_flash; 5519 eeprom->word_size = 2048; 5520 /* 5521 * Ensure that the Autonomous FLASH update bit is 5522 * cleared due to Flash update issue on parts which 5523 * use a FLASH for NVM. 5524 */ 5525 eecd &= ~E1000_EECD_AUPDEN; 5526 E1000_WRITE_REG(hw, EECD, eecd); 5527 } 5528 if (em_get_flash_presence_i210(hw) == FALSE) { 5529 eeprom->type = em_eeprom_invm; 5530 eeprom->word_size = INVM_SIZE; 5531 eeprom->use_eerd = FALSE; 5532 eeprom->use_eewr = FALSE; 5533 } 5534 break; 5535 case em_80003es2lan: 5536 eeprom->type = em_eeprom_spi; 5537 eeprom->opcode_bits = 8; 5538 eeprom->delay_usec = 1; 5539 if (eecd & E1000_EECD_ADDR_BITS) { 5540 eeprom->page_size = 32; 5541 eeprom->address_bits = 16; 5542 } else { 5543 eeprom->page_size = 8; 5544 eeprom->address_bits = 8; 5545 } 5546 eeprom->use_eerd = TRUE; 5547 eeprom->use_eewr = FALSE; 5548 break; 5549 case em_ich8lan: 5550 case em_ich9lan: 5551 case em_ich10lan: 5552 case em_pchlan: 5553 case em_pch2lan: 5554 case em_pch_lpt: 5555 { 5556 int32_t i = 0; 5557 uint32_t flash_size = 5558 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); 5559 eeprom->type = em_eeprom_ich8; 5560 eeprom->use_eerd = FALSE; 5561 eeprom->use_eewr = FALSE; 5562 eeprom->word_size = E1000_SHADOW_RAM_WORDS; 5563 /* 5564 * Zero the shadow RAM structure. But don't load it 5565 * from NVM so as to save time for driver init 5566 */ 5567 if (hw->eeprom_shadow_ram != NULL) { 5568 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 5569 hw->eeprom_shadow_ram[i].modified = 5570 FALSE; 5571 hw->eeprom_shadow_ram[i].eeprom_word = 5572 0xFFFF; 5573 } 5574 } 5575 hw->flash_base_addr = (flash_size & 5576 ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; 5577 5578 hw->flash_bank_size = ((flash_size >> 16) & 5579 ICH_GFPREG_BASE_MASK) + 1; 5580 hw->flash_bank_size -= (flash_size & 5581 ICH_GFPREG_BASE_MASK); 5582 5583 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; 5584 5585 hw->flash_bank_size /= 2 * sizeof(uint16_t); 5586 5587 break; 5588 } 5589 default: 5590 break; 5591 } 5592 5593 if (eeprom->type == em_eeprom_spi) { 5594 /* 5595 * eeprom_size will be an enum [0..8] that maps to eeprom 5596 * sizes 128B to 32KB (incremented by powers of 2). 5597 */ 5598 if (hw->mac_type <= em_82547_rev_2) { 5599 /* Set to default value for initial eeprom read. */ 5600 eeprom->word_size = 64; 5601 ret_val = em_read_eeprom(hw, EEPROM_CFG, 1, 5602 &eeprom_size); 5603 if (ret_val) 5604 return ret_val; 5605 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> 5606 EEPROM_SIZE_SHIFT; 5607 /* 5608 * 256B eeprom size was not supported in earlier 5609 * hardware, so we bump eeprom_size up one to ensure 5610 * that "1" (which maps to 256B) is never the result 5611 * used in the shifting logic below. 5612 */ 5613 if (eeprom_size) 5614 eeprom_size++; 5615 } else { 5616 eeprom_size = (uint16_t) ( 5617 (eecd & E1000_EECD_SIZE_EX_MASK) >> 5618 E1000_EECD_SIZE_EX_SHIFT); 5619 } 5620 5621 /* EEPROM access above 16k is unsupported */ 5622 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT > 5623 EEPROM_WORD_SIZE_SHIFT_MAX) { 5624 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; 5625 } else { 5626 eeprom->word_size = 1 << 5627 (eeprom_size + EEPROM_WORD_SIZE_SHIFT); 5628 } 5629 } 5630 return ret_val; 5631 } 5632 5633 /****************************************************************************** 5634 * Raises the EEPROM's clock input. 5635 * 5636 * hw - Struct containing variables accessed by shared code 5637 * eecd - EECD's current value 5638 *****************************************************************************/ 5639 static void 5640 em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd) 5641 { 5642 /* 5643 * Raise the clock input to the EEPROM (by setting the SK bit), and 5644 * then wait <delay> microseconds. 5645 */ 5646 *eecd = *eecd | E1000_EECD_SK; 5647 E1000_WRITE_REG(hw, EECD, *eecd); 5648 E1000_WRITE_FLUSH(hw); 5649 usec_delay(hw->eeprom.delay_usec); 5650 } 5651 5652 /****************************************************************************** 5653 * Lowers the EEPROM's clock input. 5654 * 5655 * hw - Struct containing variables accessed by shared code 5656 * eecd - EECD's current value 5657 *****************************************************************************/ 5658 static void 5659 em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd) 5660 { 5661 /* 5662 * Lower the clock input to the EEPROM (by clearing the SK bit), and 5663 * then wait 50 microseconds. 5664 */ 5665 *eecd = *eecd & ~E1000_EECD_SK; 5666 E1000_WRITE_REG(hw, EECD, *eecd); 5667 E1000_WRITE_FLUSH(hw); 5668 usec_delay(hw->eeprom.delay_usec); 5669 } 5670 5671 /****************************************************************************** 5672 * Shift data bits out to the EEPROM. 5673 * 5674 * hw - Struct containing variables accessed by shared code 5675 * data - data to send to the EEPROM 5676 * count - number of bits to shift out 5677 *****************************************************************************/ 5678 static void 5679 em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count) 5680 { 5681 struct em_eeprom_info *eeprom = &hw->eeprom; 5682 uint32_t eecd; 5683 uint32_t mask; 5684 /* 5685 * We need to shift "count" bits out to the EEPROM. So, value in the 5686 * "data" parameter will be shifted out to the EEPROM one bit at a 5687 * time. In order to do this, "data" must be broken down into bits. 5688 */ 5689 mask = 0x01 << (count - 1); 5690 eecd = E1000_READ_REG(hw, EECD); 5691 if (eeprom->type == em_eeprom_microwire) { 5692 eecd &= ~E1000_EECD_DO; 5693 } else if (eeprom->type == em_eeprom_spi) { 5694 eecd |= E1000_EECD_DO; 5695 } 5696 do { 5697 /* 5698 * A "1" is shifted out to the EEPROM by setting bit "DI" to 5699 * a "1", and then raising and then lowering the clock (the 5700 * SK bit controls the clock input to the EEPROM). A "0" is 5701 * shifted out to the EEPROM by setting "DI" to "0" and then 5702 * raising and then lowering the clock. 5703 */ 5704 eecd &= ~E1000_EECD_DI; 5705 5706 if (data & mask) 5707 eecd |= E1000_EECD_DI; 5708 5709 E1000_WRITE_REG(hw, EECD, eecd); 5710 E1000_WRITE_FLUSH(hw); 5711 5712 usec_delay(eeprom->delay_usec); 5713 5714 em_raise_ee_clk(hw, &eecd); 5715 em_lower_ee_clk(hw, &eecd); 5716 5717 mask = mask >> 1; 5718 5719 } while (mask); 5720 5721 /* We leave the "DI" bit set to "0" when we leave this routine. */ 5722 eecd &= ~E1000_EECD_DI; 5723 E1000_WRITE_REG(hw, EECD, eecd); 5724 } 5725 5726 /****************************************************************************** 5727 * Shift data bits in from the EEPROM 5728 * 5729 * hw - Struct containing variables accessed by shared code 5730 *****************************************************************************/ 5731 static uint16_t 5732 em_shift_in_ee_bits(struct em_hw *hw, uint16_t count) 5733 { 5734 uint32_t eecd; 5735 uint32_t i; 5736 uint16_t data; 5737 /* 5738 * In order to read a register from the EEPROM, we need to shift 5739 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 5740 * the clock input to the EEPROM (setting the SK bit), and then 5741 * reading the value of the "DO" bit. During this "shifting in" 5742 * process the "DI" bit should always be clear. 5743 */ 5744 5745 eecd = E1000_READ_REG(hw, EECD); 5746 5747 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 5748 data = 0; 5749 5750 for (i = 0; i < count; i++) { 5751 data = data << 1; 5752 em_raise_ee_clk(hw, &eecd); 5753 5754 eecd = E1000_READ_REG(hw, EECD); 5755 5756 eecd &= ~(E1000_EECD_DI); 5757 if (eecd & E1000_EECD_DO) 5758 data |= 1; 5759 5760 em_lower_ee_clk(hw, &eecd); 5761 } 5762 5763 return data; 5764 } 5765 /****************************************************************************** 5766 * Prepares EEPROM for access 5767 * 5768 * hw - Struct containing variables accessed by shared code 5769 * 5770 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 5771 * function should be called before issuing a command to the EEPROM. 5772 *****************************************************************************/ 5773 static int32_t 5774 em_acquire_eeprom(struct em_hw *hw) 5775 { 5776 struct em_eeprom_info *eeprom = &hw->eeprom; 5777 uint32_t eecd, i = 0; 5778 DEBUGFUNC("em_acquire_eeprom"); 5779 5780 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 5781 return -E1000_ERR_SWFW_SYNC; 5782 eecd = E1000_READ_REG(hw, EECD); 5783 5784 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) { 5785 /* Request EEPROM Access */ 5786 if (hw->mac_type > em_82544) { 5787 eecd |= E1000_EECD_REQ; 5788 E1000_WRITE_REG(hw, EECD, eecd); 5789 eecd = E1000_READ_REG(hw, EECD); 5790 while ((!(eecd & E1000_EECD_GNT)) && 5791 (i < E1000_EEPROM_GRANT_ATTEMPTS)) { 5792 i++; 5793 usec_delay(5); 5794 eecd = E1000_READ_REG(hw, EECD); 5795 } 5796 if (!(eecd & E1000_EECD_GNT)) { 5797 eecd &= ~E1000_EECD_REQ; 5798 E1000_WRITE_REG(hw, EECD, eecd); 5799 DEBUGOUT("Could not acquire EEPROM grant\n"); 5800 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5801 return -E1000_ERR_EEPROM; 5802 } 5803 } 5804 } 5805 5806 /* Setup EEPROM for Read/Write */ 5807 if (eeprom->type == em_eeprom_microwire) { 5808 /* Clear SK and DI */ 5809 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); 5810 E1000_WRITE_REG(hw, EECD, eecd); 5811 5812 /* Set CS */ 5813 eecd |= E1000_EECD_CS; 5814 E1000_WRITE_REG(hw, EECD, eecd); 5815 } else if (eeprom->type == em_eeprom_spi) { 5816 /* Clear SK and CS */ 5817 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 5818 E1000_WRITE_REG(hw, EECD, eecd); 5819 usec_delay(1); 5820 } 5821 return E1000_SUCCESS; 5822 } 5823 5824 /****************************************************************************** 5825 * Returns EEPROM to a "standby" state 5826 * 5827 * hw - Struct containing variables accessed by shared code 5828 *****************************************************************************/ 5829 static void 5830 em_standby_eeprom(struct em_hw *hw) 5831 { 5832 struct em_eeprom_info *eeprom = &hw->eeprom; 5833 uint32_t eecd; 5834 eecd = E1000_READ_REG(hw, EECD); 5835 5836 if (eeprom->type == em_eeprom_microwire) { 5837 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 5838 E1000_WRITE_REG(hw, EECD, eecd); 5839 E1000_WRITE_FLUSH(hw); 5840 usec_delay(eeprom->delay_usec); 5841 5842 /* Clock high */ 5843 eecd |= E1000_EECD_SK; 5844 E1000_WRITE_REG(hw, EECD, eecd); 5845 E1000_WRITE_FLUSH(hw); 5846 usec_delay(eeprom->delay_usec); 5847 5848 /* Select EEPROM */ 5849 eecd |= E1000_EECD_CS; 5850 E1000_WRITE_REG(hw, EECD, eecd); 5851 E1000_WRITE_FLUSH(hw); 5852 usec_delay(eeprom->delay_usec); 5853 5854 /* Clock low */ 5855 eecd &= ~E1000_EECD_SK; 5856 E1000_WRITE_REG(hw, EECD, eecd); 5857 E1000_WRITE_FLUSH(hw); 5858 usec_delay(eeprom->delay_usec); 5859 } else if (eeprom->type == em_eeprom_spi) { 5860 /* Toggle CS to flush commands */ 5861 eecd |= E1000_EECD_CS; 5862 E1000_WRITE_REG(hw, EECD, eecd); 5863 E1000_WRITE_FLUSH(hw); 5864 usec_delay(eeprom->delay_usec); 5865 eecd &= ~E1000_EECD_CS; 5866 E1000_WRITE_REG(hw, EECD, eecd); 5867 E1000_WRITE_FLUSH(hw); 5868 usec_delay(eeprom->delay_usec); 5869 } 5870 } 5871 5872 /****************************************************************************** 5873 * Terminates a command by inverting the EEPROM's chip select pin 5874 * 5875 * hw - Struct containing variables accessed by shared code 5876 *****************************************************************************/ 5877 static void 5878 em_release_eeprom(struct em_hw *hw) 5879 { 5880 uint32_t eecd; 5881 DEBUGFUNC("em_release_eeprom"); 5882 5883 eecd = E1000_READ_REG(hw, EECD); 5884 5885 if (hw->eeprom.type == em_eeprom_spi) { 5886 eecd |= E1000_EECD_CS; /* Pull CS high */ 5887 eecd &= ~E1000_EECD_SK; /* Lower SCK */ 5888 5889 E1000_WRITE_REG(hw, EECD, eecd); 5890 5891 usec_delay(hw->eeprom.delay_usec); 5892 } else if (hw->eeprom.type == em_eeprom_microwire) { 5893 /* cleanup eeprom */ 5894 5895 /* CS on Microwire is active-high */ 5896 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); 5897 5898 E1000_WRITE_REG(hw, EECD, eecd); 5899 5900 /* Rising edge of clock */ 5901 eecd |= E1000_EECD_SK; 5902 E1000_WRITE_REG(hw, EECD, eecd); 5903 E1000_WRITE_FLUSH(hw); 5904 usec_delay(hw->eeprom.delay_usec); 5905 5906 /* Falling edge of clock */ 5907 eecd &= ~E1000_EECD_SK; 5908 E1000_WRITE_REG(hw, EECD, eecd); 5909 E1000_WRITE_FLUSH(hw); 5910 usec_delay(hw->eeprom.delay_usec); 5911 } 5912 /* Stop requesting EEPROM access */ 5913 if (hw->mac_type > em_82544) { 5914 eecd &= ~E1000_EECD_REQ; 5915 E1000_WRITE_REG(hw, EECD, eecd); 5916 } 5917 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 5918 } 5919 5920 /****************************************************************************** 5921 * Reads a 16 bit word from the EEPROM. 5922 * 5923 * hw - Struct containing variables accessed by shared code 5924 *****************************************************************************/ 5925 STATIC int32_t 5926 em_spi_eeprom_ready(struct em_hw *hw) 5927 { 5928 uint16_t retry_count = 0; 5929 uint8_t spi_stat_reg; 5930 DEBUGFUNC("em_spi_eeprom_ready"); 5931 /* 5932 * Read "Status Register" repeatedly until the LSB is cleared. The 5933 * EEPROM will signal that the command has been completed by clearing 5934 * bit 0 of the internal status register. If it's not cleared within 5935 * 5 milliseconds, then error out. 5936 */ 5937 retry_count = 0; 5938 do { 5939 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, 5940 hw->eeprom.opcode_bits); 5941 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8); 5942 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) 5943 break; 5944 5945 usec_delay(5); 5946 retry_count += 5; 5947 5948 em_standby_eeprom(hw); 5949 } while (retry_count < EEPROM_MAX_RETRY_SPI); 5950 /* 5951 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and 5952 * only 0-5mSec on 5V devices) 5953 */ 5954 if (retry_count >= EEPROM_MAX_RETRY_SPI) { 5955 DEBUGOUT("SPI EEPROM Status error\n"); 5956 return -E1000_ERR_EEPROM; 5957 } 5958 return E1000_SUCCESS; 5959 } 5960 5961 /****************************************************************************** 5962 * Reads a 16 bit word from the EEPROM. 5963 * 5964 * hw - Struct containing variables accessed by shared code 5965 * offset - offset of word in the EEPROM to read 5966 * data - word read from the EEPROM 5967 * words - number of words to read 5968 *****************************************************************************/ 5969 int32_t 5970 em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 5971 uint16_t *data) 5972 { 5973 struct em_eeprom_info *eeprom = &hw->eeprom; 5974 uint32_t i = 0; 5975 DEBUGFUNC("em_read_eeprom"); 5976 5977 /* If eeprom is not yet detected, do so now */ 5978 if (eeprom->word_size == 0) 5979 em_init_eeprom_params(hw); 5980 /* 5981 * A check for invalid values: offset too large, too many words, and 5982 * not enough words. 5983 */ 5984 if ((offset >= eeprom->word_size) || 5985 (words > eeprom->word_size - offset) || 5986 (words == 0)) { 5987 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," 5988 " size = %d\n", offset, eeprom->word_size); 5989 return -E1000_ERR_EEPROM; 5990 } 5991 /* 5992 * EEPROM's that don't use EERD to read require us to bit-bang the 5993 * SPI directly. In this case, we need to acquire the EEPROM so that 5994 * FW or other port software does not interrupt. 5995 */ 5996 if (em_is_onboard_nvm_eeprom(hw) == TRUE && 5997 em_get_flash_presence_i210(hw) == TRUE && 5998 hw->eeprom.use_eerd == FALSE) { 5999 /* Prepare the EEPROM for bit-bang reading */ 6000 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6001 return -E1000_ERR_EEPROM; 6002 } 6003 /* Eerd register EEPROM access requires no eeprom aquire/release */ 6004 if (eeprom->use_eerd == TRUE) 6005 return em_read_eeprom_eerd(hw, offset, words, data); 6006 6007 /* ICH EEPROM access is done via the ICH flash controller */ 6008 if (eeprom->type == em_eeprom_ich8) 6009 return em_read_eeprom_ich8(hw, offset, words, data); 6010 6011 /* Some i210/i211 have a special OTP chip */ 6012 if (eeprom->type == em_eeprom_invm) 6013 return em_read_invm_i210(hw, offset, words, data); 6014 6015 /* 6016 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have 6017 * acquired the EEPROM at this point, so any returns should relase it 6018 */ 6019 if (eeprom->type == em_eeprom_spi) { 6020 uint16_t word_in; 6021 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; 6022 if (em_spi_eeprom_ready(hw)) { 6023 em_release_eeprom(hw); 6024 return -E1000_ERR_EEPROM; 6025 } 6026 em_standby_eeprom(hw); 6027 /* 6028 * Some SPI eeproms use the 8th address bit embedded in the 6029 * opcode 6030 */ 6031 if ((eeprom->address_bits == 8) && (offset >= 128)) 6032 read_opcode |= EEPROM_A8_OPCODE_SPI; 6033 6034 /* Send the READ command (opcode + addr) */ 6035 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); 6036 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), 6037 eeprom->address_bits); 6038 /* 6039 * Read the data. The address of the eeprom internally 6040 * increments with each byte (spi) being read, saving on the 6041 * overhead of eeprom setup and tear-down. The address 6042 * counter will roll over if reading beyond the size of the 6043 * eeprom, thus allowing the entire memory to be read 6044 * starting from any offset. 6045 */ 6046 for (i = 0; i < words; i++) { 6047 word_in = em_shift_in_ee_bits(hw, 16); 6048 data[i] = (word_in >> 8) | (word_in << 8); 6049 } 6050 } else if (eeprom->type == em_eeprom_microwire) { 6051 for (i = 0; i < words; i++) { 6052 /* Send the READ command (opcode + addr) */ 6053 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, 6054 eeprom->opcode_bits); 6055 em_shift_out_ee_bits(hw, (uint16_t) (offset + i), 6056 eeprom->address_bits); 6057 /* 6058 * Read the data. For microwire, each word requires 6059 * the overhead of eeprom setup and tear-down. 6060 */ 6061 data[i] = em_shift_in_ee_bits(hw, 16); 6062 em_standby_eeprom(hw); 6063 } 6064 } 6065 /* End this read operation */ 6066 em_release_eeprom(hw); 6067 6068 return E1000_SUCCESS; 6069 } 6070 6071 /****************************************************************************** 6072 * Reads a 16 bit word from the EEPROM using the EERD register. 6073 * 6074 * hw - Struct containing variables accessed by shared code 6075 * offset - offset of word in the EEPROM to read 6076 * data - word read from the EEPROM 6077 * words - number of words to read 6078 *****************************************************************************/ 6079 STATIC int32_t 6080 em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, 6081 uint16_t *data) 6082 { 6083 uint32_t i, eerd = 0; 6084 int32_t error = 0; 6085 for (i = 0; i < words; i++) { 6086 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) + 6087 E1000_EEPROM_RW_REG_START; 6088 6089 E1000_WRITE_REG(hw, EERD, eerd); 6090 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); 6091 6092 if (error) { 6093 break; 6094 } 6095 data[i] = (E1000_READ_REG(hw, EERD) >> 6096 E1000_EEPROM_RW_REG_DATA); 6097 6098 } 6099 6100 return error; 6101 } 6102 6103 /****************************************************************************** 6104 * Writes a 16 bit word from the EEPROM using the EEWR register. 6105 * 6106 * hw - Struct containing variables accessed by shared code 6107 * offset - offset of word in the EEPROM to read 6108 * data - word read from the EEPROM 6109 * words - number of words to read 6110 *****************************************************************************/ 6111 STATIC int32_t 6112 em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words, 6113 uint16_t *data) 6114 { 6115 uint32_t register_value = 0; 6116 uint32_t i = 0; 6117 int32_t error = 0; 6118 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) 6119 return -E1000_ERR_SWFW_SYNC; 6120 6121 for (i = 0; i < words; i++) { 6122 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | 6123 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) | 6124 E1000_EEPROM_RW_REG_START; 6125 6126 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6127 if (error) { 6128 break; 6129 } 6130 E1000_WRITE_REG(hw, EEWR, register_value); 6131 6132 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); 6133 6134 if (error) { 6135 break; 6136 } 6137 } 6138 6139 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM); 6140 return error; 6141 } 6142 6143 /****************************************************************************** 6144 * Polls the status bit (bit 1) of the EERD to determine when the read is done. 6145 * 6146 * hw - Struct containing variables accessed by shared code 6147 *****************************************************************************/ 6148 STATIC int32_t 6149 em_poll_eerd_eewr_done(struct em_hw *hw, int eerd) 6150 { 6151 uint32_t attempts = 100000; 6152 uint32_t i, reg = 0; 6153 int32_t done = E1000_ERR_EEPROM; 6154 for (i = 0; i < attempts; i++) { 6155 if (eerd == E1000_EEPROM_POLL_READ) 6156 reg = E1000_READ_REG(hw, EERD); 6157 else 6158 reg = E1000_READ_REG(hw, EEWR); 6159 6160 if (reg & E1000_EEPROM_RW_REG_DONE) { 6161 done = E1000_SUCCESS; 6162 break; 6163 } 6164 usec_delay(5); 6165 } 6166 6167 return done; 6168 } 6169 6170 /****************************************************************************** 6171 * Description: Determines if the onboard NVM is FLASH or EEPROM. 6172 * 6173 * hw - Struct containing variables accessed by shared code 6174 *****************************************************************************/ 6175 STATIC boolean_t 6176 em_is_onboard_nvm_eeprom(struct em_hw *hw) 6177 { 6178 uint32_t eecd = 0; 6179 DEBUGFUNC("em_is_onboard_nvm_eeprom"); 6180 6181 if (IS_ICH8(hw->mac_type)) 6182 return FALSE; 6183 6184 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6185 eecd = E1000_READ_REG(hw, EECD); 6186 6187 /* Isolate bits 15 & 16 */ 6188 eecd = ((eecd >> 15) & 0x03); 6189 6190 /* If both bits are set, device is Flash type */ 6191 if (eecd == 0x03) { 6192 return FALSE; 6193 } 6194 } 6195 return TRUE; 6196 } 6197 6198 /****************************************************************************** 6199 * Check if flash device is detected. 6200 * 6201 * hw - Struct containing variables accessed by shared code 6202 *****************************************************************************/ 6203 boolean_t 6204 em_get_flash_presence_i210(struct em_hw *hw) 6205 { 6206 uint32_t eecd; 6207 DEBUGFUNC("em_get_flash_presence_i210"); 6208 6209 if (hw->mac_type != em_i210) 6210 return TRUE; 6211 6212 eecd = E1000_READ_REG(hw, EECD); 6213 6214 if (eecd & E1000_EECD_FLUPD) 6215 return TRUE; 6216 6217 return FALSE; 6218 } 6219 6220 /****************************************************************************** 6221 * Verifies that the EEPROM has a valid checksum 6222 * 6223 * hw - Struct containing variables accessed by shared code 6224 * 6225 * Reads the first 64 16 bit words of the EEPROM and sums the values read. 6226 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is 6227 * valid. 6228 *****************************************************************************/ 6229 int32_t 6230 em_validate_eeprom_checksum(struct em_hw *hw) 6231 { 6232 uint16_t checksum = 0; 6233 uint16_t i, eeprom_data; 6234 uint16_t checksum_reg; 6235 DEBUGFUNC("em_validate_eeprom_checksum"); 6236 6237 checksum_reg = hw->mac_type != em_icp_xxxx ? 6238 EEPROM_CHECKSUM_REG : 6239 EEPROM_CHECKSUM_REG_ICP_xxxx; 6240 6241 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && 6242 (em_is_onboard_nvm_eeprom(hw) == FALSE)) { 6243 /* 6244 * Check bit 4 of word 10h. If it is 0, firmware is done 6245 * updating 10h-12h. Checksum may need to be fixed. 6246 */ 6247 em_read_eeprom(hw, 0x10, 1, &eeprom_data); 6248 if ((eeprom_data & 0x10) == 0) { 6249 /* 6250 * Read 0x23 and check bit 15. This bit is a 1 when 6251 * the checksum has already been fixed. If the 6252 * checksum is still wrong and this bit is a 1, we 6253 * need to return bad checksum. Otherwise, we need 6254 * to set this bit to a 1 and update the checksum. 6255 */ 6256 em_read_eeprom(hw, 0x23, 1, &eeprom_data); 6257 if ((eeprom_data & 0x8000) == 0) { 6258 eeprom_data |= 0x8000; 6259 em_write_eeprom(hw, 0x23, 1, &eeprom_data); 6260 em_update_eeprom_checksum(hw); 6261 } 6262 } 6263 } 6264 if (IS_ICH8(hw->mac_type)) { 6265 uint16_t word; 6266 uint16_t valid_csum_mask; 6267 6268 /* 6269 * Drivers must allocate the shadow ram structure for the 6270 * EEPROM checksum to be updated. Otherwise, this bit as 6271 * well as the checksum must both be set correctly for this 6272 * validation to pass. 6273 */ 6274 switch (hw->mac_type) { 6275 case em_pch_lpt: 6276 word = EEPROM_COMPAT; 6277 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM; 6278 break; 6279 default: 6280 word = EEPROM_FUTURE_INIT_WORD1; 6281 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM; 6282 break; 6283 } 6284 em_read_eeprom(hw, word, 1, &eeprom_data); 6285 if ((eeprom_data & valid_csum_mask) == 0) { 6286 eeprom_data |= valid_csum_mask; 6287 em_write_eeprom(hw, word, 1, &eeprom_data); 6288 em_update_eeprom_checksum(hw); 6289 } 6290 } 6291 for (i = 0; i < (checksum_reg + 1); i++) { 6292 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6293 DEBUGOUT("EEPROM Read Error\n"); 6294 return -E1000_ERR_EEPROM; 6295 } 6296 checksum += eeprom_data; 6297 } 6298 6299 if (checksum == (uint16_t) EEPROM_SUM) 6300 return E1000_SUCCESS; 6301 else { 6302 DEBUGOUT("EEPROM Checksum Invalid\n"); 6303 return -E1000_ERR_EEPROM; 6304 } 6305 } 6306 6307 /****************************************************************************** 6308 * Calculates the EEPROM checksum and writes it to the EEPROM 6309 * 6310 * hw - Struct containing variables accessed by shared code 6311 * 6312 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. 6313 * Writes the difference to word offset 63 of the EEPROM. 6314 *****************************************************************************/ 6315 int32_t 6316 em_update_eeprom_checksum(struct em_hw *hw) 6317 { 6318 uint32_t ctrl_ext; 6319 uint16_t checksum = 0; 6320 uint16_t i, eeprom_data; 6321 DEBUGFUNC("em_update_eeprom_checksum"); 6322 6323 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { 6324 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) { 6325 DEBUGOUT("EEPROM Read Error\n"); 6326 return -E1000_ERR_EEPROM; 6327 } 6328 checksum += eeprom_data; 6329 } 6330 checksum = (uint16_t) EEPROM_SUM - checksum; 6331 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { 6332 DEBUGOUT("EEPROM Write Error\n"); 6333 return -E1000_ERR_EEPROM; 6334 } else if (hw->eeprom.type == em_eeprom_flash) { 6335 em_commit_shadow_ram(hw); 6336 } else if (hw->eeprom.type == em_eeprom_ich8) { 6337 em_commit_shadow_ram(hw); 6338 /* 6339 * Reload the EEPROM, or else modifications will not appear 6340 * until after next adapter reset. 6341 */ 6342 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 6343 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 6344 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 6345 msec_delay(10); 6346 } 6347 return E1000_SUCCESS; 6348 } 6349 6350 /****************************************************************************** 6351 * Parent function for writing words to the different EEPROM types. 6352 * 6353 * hw - Struct containing variables accessed by shared code 6354 * offset - offset within the EEPROM to be written to 6355 * words - number of words to write 6356 * data - 16 bit word to be written to the EEPROM 6357 * 6358 * If em_update_eeprom_checksum is not called after this function, the 6359 * EEPROM will most likely contain an invalid checksum. 6360 *****************************************************************************/ 6361 int32_t 6362 em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, 6363 uint16_t *data) 6364 { 6365 struct em_eeprom_info *eeprom = &hw->eeprom; 6366 int32_t status = 0; 6367 DEBUGFUNC("em_write_eeprom"); 6368 6369 /* If eeprom is not yet detected, do so now */ 6370 if (eeprom->word_size == 0) 6371 em_init_eeprom_params(hw); 6372 /* 6373 * A check for invalid values: offset too large, too many words, and 6374 * not enough words. 6375 */ 6376 if ((offset >= eeprom->word_size) || 6377 (words > eeprom->word_size - offset) || 6378 (words == 0)) { 6379 DEBUGOUT("\"words\" parameter out of bounds\n"); 6380 return -E1000_ERR_EEPROM; 6381 } 6382 /* 82573/4 writes only through eewr */ 6383 if (eeprom->use_eewr == TRUE) 6384 return em_write_eeprom_eewr(hw, offset, words, data); 6385 6386 if (eeprom->type == em_eeprom_ich8) 6387 return em_write_eeprom_ich8(hw, offset, words, data); 6388 6389 /* Prepare the EEPROM for writing */ 6390 if (em_acquire_eeprom(hw) != E1000_SUCCESS) 6391 return -E1000_ERR_EEPROM; 6392 6393 if (eeprom->type == em_eeprom_microwire) { 6394 status = em_write_eeprom_microwire(hw, offset, words, data); 6395 } else { 6396 status = em_write_eeprom_spi(hw, offset, words, data); 6397 msec_delay(10); 6398 } 6399 6400 /* Done with writing */ 6401 em_release_eeprom(hw); 6402 6403 return status; 6404 } 6405 6406 /****************************************************************************** 6407 * Writes a 16 bit word to a given offset in an SPI EEPROM. 6408 * 6409 * hw - Struct containing variables accessed by shared code 6410 * offset - offset within the EEPROM to be written to 6411 * words - number of words to write 6412 * data - pointer to array of 8 bit words to be written to the EEPROM 6413 * 6414 *****************************************************************************/ 6415 STATIC int32_t 6416 em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words, 6417 uint16_t *data) 6418 { 6419 struct em_eeprom_info *eeprom = &hw->eeprom; 6420 uint16_t widx = 0; 6421 DEBUGFUNC("em_write_eeprom_spi"); 6422 6423 while (widx < words) { 6424 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; 6425 if (em_spi_eeprom_ready(hw)) 6426 return -E1000_ERR_EEPROM; 6427 6428 em_standby_eeprom(hw); 6429 6430 /* Send the WRITE ENABLE command (8 bit opcode ) */ 6431 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, 6432 eeprom->opcode_bits); 6433 6434 em_standby_eeprom(hw); 6435 /* 6436 * Some SPI eeproms use the 8th address bit embedded in the 6437 * opcode 6438 */ 6439 if ((eeprom->address_bits == 8) && (offset >= 128)) 6440 write_opcode |= EEPROM_A8_OPCODE_SPI; 6441 6442 /* Send the Write command (8-bit opcode + addr) */ 6443 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); 6444 6445 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2), 6446 eeprom->address_bits); 6447 6448 /* Send the data */ 6449 /* 6450 * Loop to allow for up to whole page write (32 bytes) of 6451 * eeprom 6452 */ 6453 while (widx < words) { 6454 uint16_t word_out = data[widx]; 6455 word_out = (word_out >> 8) | (word_out << 8); 6456 em_shift_out_ee_bits(hw, word_out, 16); 6457 widx++; 6458 /* 6459 * Some larger eeprom sizes are capable of a 32-byte 6460 * PAGE WRITE operation, while the smaller eeproms 6461 * are capable of an 8-byte PAGE WRITE operation. 6462 * Break the inner loop to pass new address 6463 */ 6464 if ((((offset + widx) * 2) % eeprom->page_size) == 0) { 6465 em_standby_eeprom(hw); 6466 break; 6467 } 6468 } 6469 } 6470 6471 return E1000_SUCCESS; 6472 } 6473 6474 /****************************************************************************** 6475 * Writes a 16 bit word to a given offset in a Microwire EEPROM. 6476 * 6477 * hw - Struct containing variables accessed by shared code 6478 * offset - offset within the EEPROM to be written to 6479 * words - number of words to write 6480 * data - pointer to array of 16 bit words to be written to the EEPROM 6481 * 6482 *****************************************************************************/ 6483 STATIC int32_t 6484 em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words, 6485 uint16_t *data) 6486 { 6487 struct em_eeprom_info *eeprom = &hw->eeprom; 6488 uint32_t eecd; 6489 uint16_t words_written = 0; 6490 uint16_t i = 0; 6491 DEBUGFUNC("em_write_eeprom_microwire"); 6492 /* 6493 * Send the write enable command to the EEPROM (3-bit opcode plus 6494 * 6/8-bit dummy address beginning with 11). It's less work to 6495 * include the 11 of the dummy address as part of the opcode than it 6496 * is to shift it over the correct number of bits for the address. 6497 * This puts the EEPROM into write/erase mode. 6498 */ 6499 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, 6500 (uint16_t) (eeprom->opcode_bits + 2)); 6501 6502 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6503 6504 /* Prepare the EEPROM */ 6505 em_standby_eeprom(hw); 6506 6507 while (words_written < words) { 6508 /* Send the Write command (3-bit opcode + addr) */ 6509 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, 6510 eeprom->opcode_bits); 6511 6512 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written), 6513 eeprom->address_bits); 6514 6515 /* Send the data */ 6516 em_shift_out_ee_bits(hw, data[words_written], 16); 6517 /* 6518 * Toggle the CS line. This in effect tells the EEPROM to 6519 * execute the previous command. 6520 */ 6521 em_standby_eeprom(hw); 6522 /* 6523 * Read DO repeatedly until it is high (equal to '1'). The 6524 * EEPROM will signal that the command has been completed by 6525 * raising the DO signal. If DO does not go high in 10 6526 * milliseconds, then error out. 6527 */ 6528 for (i = 0; i < 200; i++) { 6529 eecd = E1000_READ_REG(hw, EECD); 6530 if (eecd & E1000_EECD_DO) 6531 break; 6532 usec_delay(50); 6533 } 6534 if (i == 200) { 6535 DEBUGOUT("EEPROM Write did not complete\n"); 6536 return -E1000_ERR_EEPROM; 6537 } 6538 /* Recover from write */ 6539 em_standby_eeprom(hw); 6540 6541 words_written++; 6542 } 6543 /* 6544 * Send the write disable command to the EEPROM (3-bit opcode plus 6545 * 6/8-bit dummy address beginning with 10). It's less work to 6546 * include the 10 of the dummy address as part of the opcode than it 6547 * is to shift it over the correct number of bits for the address. 6548 * This takes the EEPROM out of write/erase mode. 6549 */ 6550 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, 6551 (uint16_t) (eeprom->opcode_bits + 2)); 6552 6553 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2)); 6554 6555 return E1000_SUCCESS; 6556 } 6557 6558 /****************************************************************************** 6559 * Flushes the cached eeprom to NVM. This is done by saving the modified values 6560 * in the eeprom cache and the non modified values in the currently active bank 6561 * to the new bank. 6562 * 6563 * hw - Struct containing variables accessed by shared code 6564 * offset - offset of word in the EEPROM to read 6565 * data - word read from the EEPROM 6566 * words - number of words to read 6567 *****************************************************************************/ 6568 STATIC int32_t 6569 em_commit_shadow_ram(struct em_hw *hw) 6570 { 6571 uint32_t attempts = 100000; 6572 uint32_t eecd = 0; 6573 uint32_t flop = 0; 6574 uint32_t i = 0; 6575 int32_t error = E1000_SUCCESS; 6576 uint32_t old_bank_offset = 0; 6577 uint32_t new_bank_offset = 0; 6578 uint8_t low_byte = 0; 6579 uint8_t high_byte = 0; 6580 boolean_t sector_write_failed = FALSE; 6581 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 6582 /* 6583 * The flop register will be used to determine if flash type 6584 * is STM 6585 */ 6586 flop = E1000_READ_REG(hw, FLOP); 6587 for (i = 0; i < attempts; i++) { 6588 eecd = E1000_READ_REG(hw, EECD); 6589 if ((eecd & E1000_EECD_FLUPD) == 0) { 6590 break; 6591 } 6592 usec_delay(5); 6593 } 6594 6595 if (i == attempts) { 6596 return -E1000_ERR_EEPROM; 6597 } 6598 /* 6599 * If STM opcode located in bits 15:8 of flop, reset firmware 6600 */ 6601 if ((flop & 0xFF00) == E1000_STM_OPCODE) { 6602 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); 6603 } 6604 /* Perform the flash update */ 6605 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); 6606 6607 for (i = 0; i < attempts; i++) { 6608 eecd = E1000_READ_REG(hw, EECD); 6609 if ((eecd & E1000_EECD_FLUPD) == 0) { 6610 break; 6611 } 6612 usec_delay(5); 6613 } 6614 6615 if (i == attempts) { 6616 return -E1000_ERR_EEPROM; 6617 } 6618 } 6619 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) && 6620 hw->eeprom_shadow_ram != NULL) { 6621 /* 6622 * We're writing to the opposite bank so if we're on bank 1, 6623 * write to bank 0 etc. We also need to erase the segment 6624 * that is going to be written 6625 */ 6626 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { 6627 new_bank_offset = hw->flash_bank_size * 2; 6628 old_bank_offset = 0; 6629 em_erase_ich8_4k_segment(hw, 1); 6630 } else { 6631 old_bank_offset = hw->flash_bank_size * 2; 6632 new_bank_offset = 0; 6633 em_erase_ich8_4k_segment(hw, 0); 6634 } 6635 6636 sector_write_failed = FALSE; 6637 /* 6638 * Loop for every byte in the shadow RAM, which is in units 6639 * of words. 6640 */ 6641 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6642 /* 6643 * Determine whether to write the value stored in the 6644 * other NVM bank or a modified value stored in the 6645 * shadow RAM 6646 */ 6647 if (hw->eeprom_shadow_ram[i].modified == TRUE) { 6648 low_byte = (uint8_t) 6649 hw->eeprom_shadow_ram[i].eeprom_word; 6650 usec_delay(100); 6651 error = em_verify_write_ich8_byte(hw, 6652 (i << 1) + new_bank_offset, low_byte); 6653 6654 if (error != E1000_SUCCESS) 6655 sector_write_failed = TRUE; 6656 else { 6657 high_byte = (uint8_t) 6658 (hw->eeprom_shadow_ram 6659 [i].eeprom_word >> 8); 6660 usec_delay(100); 6661 } 6662 } else { 6663 em_read_ich8_byte(hw, (i << 1) + 6664 old_bank_offset, &low_byte); 6665 usec_delay(100); 6666 error = em_verify_write_ich8_byte(hw, 6667 (i << 1) + new_bank_offset, low_byte); 6668 6669 if (error != E1000_SUCCESS) 6670 sector_write_failed = TRUE; 6671 else { 6672 em_read_ich8_byte(hw, (i << 1) + 6673 old_bank_offset + 1, &high_byte); 6674 usec_delay(100); 6675 } 6676 } 6677 /* 6678 * If the write of the low byte was successful, go 6679 * ahread and write the high byte while checking to 6680 * make sure that if it is the signature byte, then 6681 * it is handled properly 6682 */ 6683 if (sector_write_failed == FALSE) { 6684 /* 6685 * If the word is 0x13, then make sure the 6686 * signature bits (15:14) are 11b until the 6687 * commit has completed. This will allow us 6688 * to write 10b which indicates the signature 6689 * is valid. We want to do this after the 6690 * write has completed so that we don't mark 6691 * the segment valid while the write is still 6692 * in progress 6693 */ 6694 if (i == E1000_ICH_NVM_SIG_WORD) 6695 high_byte = E1000_ICH_NVM_VALID_SIG_MASK | 6696 high_byte; 6697 6698 error = em_verify_write_ich8_byte(hw, (i << 1) 6699 + new_bank_offset + 1, high_byte); 6700 if (error != E1000_SUCCESS) 6701 sector_write_failed = TRUE; 6702 6703 } else { 6704 /* 6705 * If the write failed then break from the 6706 * loop and return an error 6707 */ 6708 break; 6709 } 6710 } 6711 /* 6712 * Don't bother writing the segment valid bits if sector 6713 * programming failed. 6714 */ 6715 if (sector_write_failed == FALSE) { 6716 /* 6717 * Finally validate the new segment by setting bit 6718 * 15:14 to 10b in word 0x13 , this can be done 6719 * without an erase as well since these bits are 11 6720 * to start with and we need to change bit 14 to 0b 6721 */ 6722 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6723 new_bank_offset, &high_byte); 6724 high_byte &= 0xBF; 6725 error = em_verify_write_ich8_byte(hw, 6726 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, 6727 high_byte); 6728 /* 6729 * And invalidate the previously valid segment by 6730 * setting its signature word (0x13) high_byte to 0b. 6731 * This can be done without an erase because flash 6732 * erase sets all bits to 1's. We can write 1's to 6733 * 0's without an erase 6734 */ 6735 if (error == E1000_SUCCESS) { 6736 error = em_verify_write_ich8_byte(hw, 6737 E1000_ICH_NVM_SIG_WORD * 2 + 1 + 6738 old_bank_offset, 0); 6739 } 6740 /* Clear the now not used entry in the cache */ 6741 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { 6742 hw->eeprom_shadow_ram[i].modified = FALSE; 6743 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; 6744 } 6745 } 6746 } 6747 return error; 6748 } 6749 6750 /****************************************************************************** 6751 * Reads the adapter's part number from the EEPROM 6752 * 6753 * hw - Struct containing variables accessed by shared code 6754 * part_num - Adapter's part number 6755 *****************************************************************************/ 6756 int32_t 6757 em_read_part_num(struct em_hw *hw, uint32_t *part_num) 6758 { 6759 uint16_t offset = EEPROM_PBA_BYTE_1; 6760 uint16_t eeprom_data; 6761 DEBUGFUNC("em_read_part_num"); 6762 6763 /* Get word 0 from EEPROM */ 6764 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { 6765 DEBUGOUT("EEPROM Read Error\n"); 6766 return -E1000_ERR_EEPROM; 6767 } 6768 /* Save word 0 in upper half of part_num */ 6769 *part_num = (uint32_t) (eeprom_data << 16); 6770 6771 /* Get word 1 from EEPROM */ 6772 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) { 6773 DEBUGOUT("EEPROM Read Error\n"); 6774 return -E1000_ERR_EEPROM; 6775 } 6776 /* Save word 1 in lower half of part_num */ 6777 *part_num |= eeprom_data; 6778 6779 return E1000_SUCCESS; 6780 } 6781 6782 /****************************************************************************** 6783 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the 6784 * second function of dual function devices 6785 * 6786 * hw - Struct containing variables accessed by shared code 6787 *****************************************************************************/ 6788 int32_t 6789 em_read_mac_addr(struct em_hw *hw) 6790 { 6791 uint16_t offset; 6792 uint16_t eeprom_data, i; 6793 uint16_t ia_base_addr = 0; 6794 DEBUGFUNC("em_read_mac_addr"); 6795 6796 if (hw->mac_type == em_icp_xxxx) { 6797 ia_base_addr = (uint16_t) 6798 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num); 6799 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) { 6800 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func); 6801 } 6802 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { 6803 offset = i >> 1; 6804 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data) 6805 < 0) { 6806 DEBUGOUT("EEPROM Read Error\n"); 6807 return -E1000_ERR_EEPROM; 6808 } 6809 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); 6810 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8); 6811 } 6812 6813 switch (hw->mac_type) { 6814 default: 6815 break; 6816 case em_82546: 6817 case em_82546_rev_3: 6818 case em_82571: 6819 case em_82575: 6820 case em_80003es2lan: 6821 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) 6822 hw->perm_mac_addr[5] ^= 0x01; 6823 break; 6824 } 6825 6826 for (i = 0; i < NODE_ADDRESS_SIZE; i++) 6827 hw->mac_addr[i] = hw->perm_mac_addr[i]; 6828 return E1000_SUCCESS; 6829 } 6830 6831 /****************************************************************************** 6832 * Initializes receive address filters. 6833 * 6834 * hw - Struct containing variables accessed by shared code 6835 * 6836 * Places the MAC address in receive address register 0 and clears the rest 6837 * of the receive addresss registers. Clears the multicast table. Assumes 6838 * the receiver is in reset when the routine is called. 6839 *****************************************************************************/ 6840 STATIC void 6841 em_init_rx_addrs(struct em_hw *hw) 6842 { 6843 uint32_t i; 6844 uint32_t rar_num; 6845 DEBUGFUNC("em_init_rx_addrs"); 6846 6847 /* Setup the receive address. */ 6848 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 6849 6850 em_rar_set(hw, hw->mac_addr, 0); 6851 6852 rar_num = E1000_RAR_ENTRIES; 6853 /* 6854 * Reserve a spot for the Locally Administered Address to work around 6855 * an 82571 issue in which a reset on one port will reload the MAC on 6856 * the other port. 6857 */ 6858 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 6859 rar_num -= 1; 6860 if (IS_ICH8(hw->mac_type)) 6861 rar_num = E1000_RAR_ENTRIES_ICH8LAN; 6862 if (hw->mac_type == em_ich8lan) 6863 rar_num -= 1; 6864 if (hw->mac_type == em_82580) 6865 rar_num = E1000_RAR_ENTRIES_82580; 6866 if (hw->mac_type == em_i210) 6867 rar_num = E1000_RAR_ENTRIES_82575; 6868 if (hw->mac_type == em_i350) 6869 rar_num = E1000_RAR_ENTRIES_I350; 6870 6871 /* Zero out the other 15 receive addresses. */ 6872 DEBUGOUT("Clearing RAR[1-15]\n"); 6873 for (i = 1; i < rar_num; i++) { 6874 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 6875 E1000_WRITE_FLUSH(hw); 6876 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 6877 E1000_WRITE_FLUSH(hw); 6878 } 6879 } 6880 6881 /****************************************************************************** 6882 * Updates the MAC's list of multicast addresses. 6883 * 6884 * hw - Struct containing variables accessed by shared code 6885 * mc_addr_list - the list of new multicast addresses 6886 * mc_addr_count - number of addresses 6887 * pad - number of bytes between addresses in the list 6888 * rar_used_count - offset where to start adding mc addresses into the RAR's 6889 * 6890 * The given list replaces any existing list. Clears the last 15 receive 6891 * address registers and the multicast table. Uses receive address registers 6892 * for the first 15 multicast addresses, and hashes the rest into the 6893 * multicast table. 6894 *****************************************************************************/ 6895 void 6896 em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list, 6897 uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count) 6898 { 6899 uint32_t hash_value; 6900 uint32_t i; 6901 uint32_t num_rar_entry; 6902 uint32_t num_mta_entry; 6903 DEBUGFUNC("em_mc_addr_list_update"); 6904 /* 6905 * Set the new number of MC addresses that we are being requested to 6906 * use. 6907 */ 6908 hw->num_mc_addrs = mc_addr_count; 6909 6910 /* Clear RAR[1-15] */ 6911 DEBUGOUT(" Clearing RAR[1-15]\n"); 6912 num_rar_entry = E1000_RAR_ENTRIES; 6913 if (IS_ICH8(hw->mac_type)) 6914 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN; 6915 if (hw->mac_type == em_ich8lan) 6916 num_rar_entry -= 1; 6917 /* 6918 * Reserve a spot for the Locally Administered Address to work around 6919 * an 82571 issue in which a reset on one port will reload the MAC on 6920 * the other port. 6921 */ 6922 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE)) 6923 num_rar_entry -= 1; 6924 6925 for (i = rar_used_count; i < num_rar_entry; i++) { 6926 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); 6927 E1000_WRITE_FLUSH(hw); 6928 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); 6929 E1000_WRITE_FLUSH(hw); 6930 } 6931 6932 /* Clear the MTA */ 6933 DEBUGOUT(" Clearing MTA\n"); 6934 num_mta_entry = E1000_NUM_MTA_REGISTERS; 6935 if (IS_ICH8(hw->mac_type)) 6936 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN; 6937 6938 for (i = 0; i < num_mta_entry; i++) { 6939 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); 6940 E1000_WRITE_FLUSH(hw); 6941 } 6942 6943 /* Add the new addresses */ 6944 for (i = 0; i < mc_addr_count; i++) { 6945 DEBUGOUT(" Adding the multicast addresses:\n"); 6946 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, 6947 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)], 6948 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1], 6949 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2], 6950 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3], 6951 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4], 6952 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]); 6953 6954 hash_value = em_hash_mc_addr(hw, mc_addr_list + 6955 (i * (ETH_LENGTH_OF_ADDRESS + pad))); 6956 6957 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); 6958 /* 6959 * Place this multicast address in the RAR if there is room, * 6960 * else put it in the MTA 6961 */ 6962 if (rar_used_count < num_rar_entry) { 6963 em_rar_set(hw, mc_addr_list + 6964 (i * (ETH_LENGTH_OF_ADDRESS + pad)), 6965 rar_used_count); 6966 rar_used_count++; 6967 } else { 6968 em_mta_set(hw, hash_value); 6969 } 6970 } 6971 DEBUGOUT("MC Update Complete\n"); 6972 } 6973 6974 /****************************************************************************** 6975 * Hashes an address to determine its location in the multicast table 6976 * 6977 * hw - Struct containing variables accessed by shared code 6978 * mc_addr - the multicast address to hash 6979 *****************************************************************************/ 6980 uint32_t 6981 em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) 6982 { 6983 uint32_t hash_value = 0; 6984 /* 6985 * The portion of the address that is used for the hash table is 6986 * determined by the mc_filter_type setting. 6987 */ 6988 switch (hw->mc_filter_type) { 6989 /* 6990 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB 6991 * MSB 6992 */ 6993 case 0: 6994 if (IS_ICH8(hw->mac_type)) { 6995 /* [47:38] i.e. 0x158 for above example address */ 6996 hash_value = ((mc_addr[4] >> 6) | 6997 (((uint16_t) mc_addr[5]) << 2)); 6998 } else { 6999 /* [47:36] i.e. 0x563 for above example address */ 7000 hash_value = ((mc_addr[4] >> 4) | 7001 (((uint16_t) mc_addr[5]) << 4)); 7002 } 7003 break; 7004 case 1: 7005 if (IS_ICH8(hw->mac_type)) { 7006 /* [46:37] i.e. 0x2B1 for above example address */ 7007 hash_value = ((mc_addr[4] >> 5) | 7008 (((uint16_t) mc_addr[5]) << 3)); 7009 } else { 7010 /* [46:35] i.e. 0xAC6 for above example address */ 7011 hash_value = ((mc_addr[4] >> 3) | 7012 (((uint16_t) mc_addr[5]) << 5)); 7013 } 7014 break; 7015 case 2: 7016 if (IS_ICH8(hw->mac_type)) { 7017 /* [45:36] i.e. 0x163 for above example address */ 7018 hash_value = ((mc_addr[4] >> 4) | 7019 (((uint16_t) mc_addr[5]) << 4)); 7020 } else { 7021 /* [45:34] i.e. 0x5D8 for above example address */ 7022 hash_value = ((mc_addr[4] >> 2) | 7023 (((uint16_t) mc_addr[5]) << 6)); 7024 } 7025 break; 7026 case 3: 7027 if (IS_ICH8(hw->mac_type)) { 7028 /* [43:34] i.e. 0x18D for above example address */ 7029 hash_value = ((mc_addr[4] >> 2) | 7030 (((uint16_t) mc_addr[5]) << 6)); 7031 } else { 7032 /* [43:32] i.e. 0x634 for above example address */ 7033 hash_value = ((mc_addr[4]) | 7034 (((uint16_t) mc_addr[5]) << 8)); 7035 } 7036 break; 7037 } 7038 7039 hash_value &= 0xFFF; 7040 if (IS_ICH8(hw->mac_type)) 7041 hash_value &= 0x3FF; 7042 7043 return hash_value; 7044 } 7045 7046 /****************************************************************************** 7047 * Sets the bit in the multicast table corresponding to the hash value. 7048 * 7049 * hw - Struct containing variables accessed by shared code 7050 * hash_value - Multicast address hash value 7051 *****************************************************************************/ 7052 void 7053 em_mta_set(struct em_hw *hw, uint32_t hash_value) 7054 { 7055 uint32_t hash_bit, hash_reg; 7056 uint32_t mta; 7057 uint32_t temp; 7058 /* 7059 * The MTA is a register array of 128 32-bit registers. It is treated 7060 * like an array of 4096 bits. We want to set bit 7061 * BitArray[hash_value]. So we figure out what register the bit is 7062 * in, read it, OR in the new bit, then write back the new value. 7063 * The register is determined by the upper 7 bits of the hash value 7064 * and the bit within that register are determined by the lower 5 7065 * bits of the value. 7066 */ 7067 hash_reg = (hash_value >> 5) & 0x7F; 7068 if (IS_ICH8(hw->mac_type)) 7069 hash_reg &= 0x1F; 7070 7071 hash_bit = hash_value & 0x1F; 7072 7073 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); 7074 7075 mta |= (1 << hash_bit); 7076 /* 7077 * If we are on an 82544 and we are trying to write an odd offset in 7078 * the MTA, save off the previous entry before writing and restore 7079 * the old value after writing. 7080 */ 7081 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) { 7082 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); 7083 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7084 E1000_WRITE_FLUSH(hw); 7085 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); 7086 E1000_WRITE_FLUSH(hw); 7087 } else { 7088 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); 7089 E1000_WRITE_FLUSH(hw); 7090 } 7091 } 7092 7093 /****************************************************************************** 7094 * Puts an ethernet address into a receive address register. 7095 * 7096 * hw - Struct containing variables accessed by shared code 7097 * addr - Address to put into receive address register 7098 * index - Receive address register to write 7099 *****************************************************************************/ 7100 void 7101 em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index) 7102 { 7103 uint32_t rar_low, rar_high; 7104 /* 7105 * HW expects these in little endian so we reverse the byte order 7106 * from network order (big endian) to little endian 7107 */ 7108 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) | 7109 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); 7110 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); 7111 /* 7112 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx 7113 * unit hang. 7114 * 7115 * Description: If there are any Rx frames queued up or otherwise 7116 * present in the HW before RSS is enabled, and then we enable RSS, 7117 * the HW Rx unit will hang. To work around this issue, we have to 7118 * disable receives and flush out all Rx frames before we enable RSS. 7119 * To do so, we modify we redirect all Rx traffic to manageability 7120 * and then reset the HW. This flushes away Rx frames, and (since the 7121 * redirections to manageability persists across resets) keeps new 7122 * ones from coming in while we work. Then, we clear the Address 7123 * Valid AV bit for all MAC addresses and undo the re-direction to 7124 * manageability. Now, frames are coming in again, but the MAC won't 7125 * accept them, so far so good. We now proceed to initialize RSS (if 7126 * necessary) and configure the Rx unit. Last, we re-enable the AV 7127 * bits and continue on our merry way. 7128 */ 7129 switch (hw->mac_type) { 7130 case em_82571: 7131 case em_82572: 7132 case em_80003es2lan: 7133 if (hw->leave_av_bit_off == TRUE) 7134 break; 7135 default: 7136 /* Indicate to hardware the Address is Valid. */ 7137 rar_high |= E1000_RAH_AV; 7138 break; 7139 } 7140 7141 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); 7142 E1000_WRITE_FLUSH(hw); 7143 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); 7144 E1000_WRITE_FLUSH(hw); 7145 } 7146 7147 /****************************************************************************** 7148 * Clears the VLAN filer table 7149 * 7150 * hw - Struct containing variables accessed by shared code 7151 *****************************************************************************/ 7152 STATIC void 7153 em_clear_vfta(struct em_hw *hw) 7154 { 7155 uint32_t offset; 7156 uint32_t vfta_value = 0; 7157 uint32_t vfta_offset = 0; 7158 uint32_t vfta_bit_in_reg = 0; 7159 if (IS_ICH8(hw->mac_type)) 7160 return; 7161 7162 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) { 7163 if (hw->mng_cookie.vlan_id != 0) { 7164 /* 7165 * The VFTA is a 4096b bit-field, each identifying a 7166 * single VLAN ID. The following operations 7167 * determine which 32b entry (i.e. offset) into the 7168 * array we want to set the VLAN ID (i.e. bit) of the 7169 * manageability unit. 7170 */ 7171 vfta_offset = (hw->mng_cookie.vlan_id >> 7172 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 7173 7174 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 7175 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 7176 } 7177 } 7178 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7179 /* 7180 * If the offset we want to clear is the same offset of the 7181 * manageability VLAN ID, then clear all bits except that of 7182 * the manageability unit 7183 */ 7184 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 7185 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); 7186 E1000_WRITE_FLUSH(hw); 7187 } 7188 } 7189 7190 /* 7191 * Due to hw errata, if the host tries to configure the VFTA register 7192 * while performing queries from the BMC or DMA, then the VFTA in some 7193 * cases won't be written. 7194 */ 7195 void 7196 em_clear_vfta_i350(struct em_hw *hw) 7197 { 7198 uint32_t offset; 7199 int i; 7200 7201 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 7202 for (i = 0; i < 10; i++) 7203 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); 7204 E1000_WRITE_FLUSH(hw); 7205 } 7206 } 7207 7208 STATIC int32_t 7209 em_id_led_init(struct em_hw *hw) 7210 { 7211 uint32_t ledctl; 7212 const uint32_t ledctl_mask = 0x000000FF; 7213 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; 7214 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 7215 uint16_t eeprom_data, i, temp; 7216 const uint16_t led_mask = 0x0F; 7217 DEBUGFUNC("em_id_led_init"); 7218 7219 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) { 7220 /* Nothing to do */ 7221 return E1000_SUCCESS; 7222 } 7223 ledctl = E1000_READ_REG(hw, LEDCTL); 7224 hw->ledctl_default = ledctl; 7225 hw->ledctl_mode1 = hw->ledctl_default; 7226 hw->ledctl_mode2 = hw->ledctl_default; 7227 7228 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { 7229 DEBUGOUT("EEPROM Read Error\n"); 7230 return -E1000_ERR_EEPROM; 7231 } 7232 if ((hw->mac_type == em_82573) && 7233 (eeprom_data == ID_LED_RESERVED_82573)) 7234 eeprom_data = ID_LED_DEFAULT_82573; 7235 else if ((eeprom_data == ID_LED_RESERVED_0000) || 7236 (eeprom_data == ID_LED_RESERVED_FFFF)) { 7237 if (hw->mac_type == em_ich8lan || 7238 hw->mac_type == em_ich9lan || 7239 hw->mac_type == em_ich10lan) // XXX 7240 eeprom_data = ID_LED_DEFAULT_ICH8LAN; 7241 else 7242 eeprom_data = ID_LED_DEFAULT; 7243 } 7244 for (i = 0; i < 4; i++) { 7245 temp = (eeprom_data >> (i << 2)) & led_mask; 7246 switch (temp) { 7247 case ID_LED_ON1_DEF2: 7248 case ID_LED_ON1_ON2: 7249 case ID_LED_ON1_OFF2: 7250 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7251 hw->ledctl_mode1 |= ledctl_on << (i << 3); 7252 break; 7253 case ID_LED_OFF1_DEF2: 7254 case ID_LED_OFF1_ON2: 7255 case ID_LED_OFF1_OFF2: 7256 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 7257 hw->ledctl_mode1 |= ledctl_off << (i << 3); 7258 break; 7259 default: 7260 /* Do nothing */ 7261 break; 7262 } 7263 switch (temp) { 7264 case ID_LED_DEF1_ON2: 7265 case ID_LED_ON1_ON2: 7266 case ID_LED_OFF1_ON2: 7267 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7268 hw->ledctl_mode2 |= ledctl_on << (i << 3); 7269 break; 7270 case ID_LED_DEF1_OFF2: 7271 case ID_LED_ON1_OFF2: 7272 case ID_LED_OFF1_OFF2: 7273 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 7274 hw->ledctl_mode2 |= ledctl_off << (i << 3); 7275 break; 7276 default: 7277 /* Do nothing */ 7278 break; 7279 } 7280 } 7281 return E1000_SUCCESS; 7282 } 7283 7284 /****************************************************************************** 7285 * Clears all hardware statistics counters. 7286 * 7287 * hw - Struct containing variables accessed by shared code 7288 *****************************************************************************/ 7289 void 7290 em_clear_hw_cntrs(struct em_hw *hw) 7291 { 7292 volatile uint32_t temp; 7293 temp = E1000_READ_REG(hw, CRCERRS); 7294 temp = E1000_READ_REG(hw, SYMERRS); 7295 temp = E1000_READ_REG(hw, MPC); 7296 temp = E1000_READ_REG(hw, SCC); 7297 temp = E1000_READ_REG(hw, ECOL); 7298 temp = E1000_READ_REG(hw, MCC); 7299 temp = E1000_READ_REG(hw, LATECOL); 7300 temp = E1000_READ_REG(hw, COLC); 7301 temp = E1000_READ_REG(hw, DC); 7302 temp = E1000_READ_REG(hw, SEC); 7303 temp = E1000_READ_REG(hw, RLEC); 7304 temp = E1000_READ_REG(hw, XONRXC); 7305 temp = E1000_READ_REG(hw, XONTXC); 7306 temp = E1000_READ_REG(hw, XOFFRXC); 7307 temp = E1000_READ_REG(hw, XOFFTXC); 7308 temp = E1000_READ_REG(hw, FCRUC); 7309 7310 if (!IS_ICH8(hw->mac_type)) { 7311 temp = E1000_READ_REG(hw, PRC64); 7312 temp = E1000_READ_REG(hw, PRC127); 7313 temp = E1000_READ_REG(hw, PRC255); 7314 temp = E1000_READ_REG(hw, PRC511); 7315 temp = E1000_READ_REG(hw, PRC1023); 7316 temp = E1000_READ_REG(hw, PRC1522); 7317 } 7318 temp = E1000_READ_REG(hw, GPRC); 7319 temp = E1000_READ_REG(hw, BPRC); 7320 temp = E1000_READ_REG(hw, MPRC); 7321 temp = E1000_READ_REG(hw, GPTC); 7322 temp = E1000_READ_REG(hw, GORCL); 7323 temp = E1000_READ_REG(hw, GORCH); 7324 temp = E1000_READ_REG(hw, GOTCL); 7325 temp = E1000_READ_REG(hw, GOTCH); 7326 temp = E1000_READ_REG(hw, RNBC); 7327 temp = E1000_READ_REG(hw, RUC); 7328 temp = E1000_READ_REG(hw, RFC); 7329 temp = E1000_READ_REG(hw, ROC); 7330 temp = E1000_READ_REG(hw, RJC); 7331 temp = E1000_READ_REG(hw, TORL); 7332 temp = E1000_READ_REG(hw, TORH); 7333 temp = E1000_READ_REG(hw, TOTL); 7334 temp = E1000_READ_REG(hw, TOTH); 7335 temp = E1000_READ_REG(hw, TPR); 7336 temp = E1000_READ_REG(hw, TPT); 7337 7338 if (!IS_ICH8(hw->mac_type)) { 7339 temp = E1000_READ_REG(hw, PTC64); 7340 temp = E1000_READ_REG(hw, PTC127); 7341 temp = E1000_READ_REG(hw, PTC255); 7342 temp = E1000_READ_REG(hw, PTC511); 7343 temp = E1000_READ_REG(hw, PTC1023); 7344 temp = E1000_READ_REG(hw, PTC1522); 7345 } 7346 temp = E1000_READ_REG(hw, MPTC); 7347 temp = E1000_READ_REG(hw, BPTC); 7348 7349 if (hw->mac_type < em_82543) 7350 return; 7351 7352 temp = E1000_READ_REG(hw, ALGNERRC); 7353 temp = E1000_READ_REG(hw, RXERRC); 7354 temp = E1000_READ_REG(hw, TNCRS); 7355 temp = E1000_READ_REG(hw, CEXTERR); 7356 temp = E1000_READ_REG(hw, TSCTC); 7357 temp = E1000_READ_REG(hw, TSCTFC); 7358 7359 if (hw->mac_type <= em_82544 7360 || hw->mac_type == em_icp_xxxx) 7361 return; 7362 7363 temp = E1000_READ_REG(hw, MGTPRC); 7364 temp = E1000_READ_REG(hw, MGTPDC); 7365 temp = E1000_READ_REG(hw, MGTPTC); 7366 7367 if (hw->mac_type <= em_82547_rev_2) 7368 return; 7369 7370 temp = E1000_READ_REG(hw, IAC); 7371 temp = E1000_READ_REG(hw, ICRXOC); 7372 7373 if (hw->phy_type == em_phy_82577 || 7374 hw->phy_type == em_phy_82578 || 7375 hw->phy_type == em_phy_82579 || 7376 hw->phy_type == em_phy_i217) { 7377 uint16_t phy_data; 7378 7379 em_read_phy_reg(hw, HV_SCC_UPPER, &phy_data); 7380 em_read_phy_reg(hw, HV_SCC_LOWER, &phy_data); 7381 em_read_phy_reg(hw, HV_ECOL_UPPER, &phy_data); 7382 em_read_phy_reg(hw, HV_ECOL_LOWER, &phy_data); 7383 em_read_phy_reg(hw, HV_MCC_UPPER, &phy_data); 7384 em_read_phy_reg(hw, HV_MCC_LOWER, &phy_data); 7385 em_read_phy_reg(hw, HV_LATECOL_UPPER, &phy_data); 7386 em_read_phy_reg(hw, HV_LATECOL_LOWER, &phy_data); 7387 em_read_phy_reg(hw, HV_COLC_UPPER, &phy_data); 7388 em_read_phy_reg(hw, HV_COLC_LOWER, &phy_data); 7389 em_read_phy_reg(hw, HV_DC_UPPER, &phy_data); 7390 em_read_phy_reg(hw, HV_DC_LOWER, &phy_data); 7391 em_read_phy_reg(hw, HV_TNCRS_UPPER, &phy_data); 7392 em_read_phy_reg(hw, HV_TNCRS_LOWER, &phy_data); 7393 } 7394 7395 if (hw->mac_type == em_ich8lan || 7396 hw->mac_type == em_ich9lan || 7397 hw->mac_type == em_ich10lan || 7398 hw->mac_type == em_pchlan || 7399 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt)) 7400 return; 7401 7402 temp = E1000_READ_REG(hw, ICRXPTC); 7403 temp = E1000_READ_REG(hw, ICRXATC); 7404 temp = E1000_READ_REG(hw, ICTXPTC); 7405 temp = E1000_READ_REG(hw, ICTXATC); 7406 temp = E1000_READ_REG(hw, ICTXQEC); 7407 temp = E1000_READ_REG(hw, ICTXQMTC); 7408 temp = E1000_READ_REG(hw, ICRXDMTC); 7409 } 7410 7411 #ifndef SMALL_KERNEL 7412 /****************************************************************************** 7413 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT 7414 * 7415 * hw - Struct containing variables accessed by shared code 7416 * frame_len - The length of the frame in question 7417 * mac_addr - The Ethernet destination address of the frame in question 7418 *****************************************************************************/ 7419 void 7420 em_tbi_adjust_stats(struct em_hw *hw, struct em_hw_stats *stats, 7421 uint32_t frame_len, uint8_t *mac_addr) 7422 { 7423 uint64_t carry_bit; 7424 /* First adjust the frame length. */ 7425 frame_len--; 7426 /* 7427 * We need to adjust the statistics counters, since the hardware 7428 * counters overcount this packet as a CRC error and undercount the 7429 * packet as a good packet 7430 */ 7431 /* This packet should not be counted as a CRC error. */ 7432 stats->crcerrs--; 7433 /* This packet does count as a Good Packet Received. */ 7434 stats->gprc++; 7435 7436 /* Adjust the Good Octets received counters */ 7437 carry_bit = 0x80000000 & stats->gorcl; 7438 stats->gorcl += frame_len; 7439 /* 7440 * If the high bit of Gorcl (the low 32 bits of the Good Octets 7441 * Received Count) was one before the addition, AND it is zero after, 7442 * then we lost the carry out, need to add one to Gorch (Good Octets 7443 * Received Count High). This could be simplified if all environments 7444 * supported 64-bit integers. 7445 */ 7446 if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) 7447 stats->gorch++; 7448 /* 7449 * Is this a broadcast or multicast? Check broadcast first, since 7450 * the test for a multicast frame will test positive on a broadcast 7451 * frame. 7452 */ 7453 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) 7454 /* Broadcast packet */ 7455 stats->bprc++; 7456 else if (*mac_addr & 0x01) 7457 /* Multicast packet */ 7458 stats->mprc++; 7459 7460 if (frame_len == hw->max_frame_size) { 7461 /* 7462 * In this case, the hardware has overcounted the number of 7463 * oversize frames. 7464 */ 7465 if (stats->roc > 0) 7466 stats->roc--; 7467 } 7468 /* 7469 * Adjust the bin counters when the extra byte put the frame in the 7470 * wrong bin. Remember that the frame_len was adjusted above. 7471 */ 7472 if (frame_len == 64) { 7473 stats->prc64++; 7474 stats->prc127--; 7475 } else if (frame_len == 127) { 7476 stats->prc127++; 7477 stats->prc255--; 7478 } else if (frame_len == 255) { 7479 stats->prc255++; 7480 stats->prc511--; 7481 } else if (frame_len == 511) { 7482 stats->prc511++; 7483 stats->prc1023--; 7484 } else if (frame_len == 1023) { 7485 stats->prc1023++; 7486 stats->prc1522--; 7487 } else if (frame_len == 1522) { 7488 stats->prc1522++; 7489 } 7490 } 7491 #endif /* !SMALL_KERNEL */ 7492 7493 /****************************************************************************** 7494 * Gets the current PCI bus type, speed, and width of the hardware 7495 * 7496 * hw - Struct containing variables accessed by shared code 7497 *****************************************************************************/ 7498 void 7499 em_get_bus_info(struct em_hw *hw) 7500 { 7501 int32_t ret_val; 7502 uint16_t pci_ex_link_status; 7503 uint32_t status; 7504 switch (hw->mac_type) { 7505 case em_82542_rev2_0: 7506 case em_82542_rev2_1: 7507 hw->bus_type = em_bus_type_unknown; 7508 hw->bus_speed = em_bus_speed_unknown; 7509 hw->bus_width = em_bus_width_unknown; 7510 break; 7511 case em_icp_xxxx: 7512 hw->bus_type = em_bus_type_cpp; 7513 hw->bus_speed = em_bus_speed_unknown; 7514 hw->bus_width = em_bus_width_unknown; 7515 break; 7516 case em_82571: 7517 case em_82572: 7518 case em_82573: 7519 case em_82574: 7520 case em_82575: 7521 case em_82580: 7522 case em_80003es2lan: 7523 case em_i210: 7524 case em_i350: 7525 hw->bus_type = em_bus_type_pci_express; 7526 hw->bus_speed = em_bus_speed_2500; 7527 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS, 7528 &pci_ex_link_status); 7529 if (ret_val) 7530 hw->bus_width = em_bus_width_unknown; 7531 else 7532 hw->bus_width = (pci_ex_link_status & 7533 PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; 7534 break; 7535 case em_ich8lan: 7536 case em_ich9lan: 7537 case em_ich10lan: 7538 case em_pchlan: 7539 case em_pch2lan: 7540 case em_pch_lpt: 7541 hw->bus_type = em_bus_type_pci_express; 7542 hw->bus_speed = em_bus_speed_2500; 7543 hw->bus_width = em_bus_width_pciex_1; 7544 break; 7545 default: 7546 status = E1000_READ_REG(hw, STATUS); 7547 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? 7548 em_bus_type_pcix : em_bus_type_pci; 7549 7550 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { 7551 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ? 7552 em_bus_speed_66 : em_bus_speed_120; 7553 } else if (hw->bus_type == em_bus_type_pci) { 7554 hw->bus_speed = (status & E1000_STATUS_PCI66) ? 7555 em_bus_speed_66 : em_bus_speed_33; 7556 } else { 7557 switch (status & E1000_STATUS_PCIX_SPEED) { 7558 case E1000_STATUS_PCIX_SPEED_66: 7559 hw->bus_speed = em_bus_speed_66; 7560 break; 7561 case E1000_STATUS_PCIX_SPEED_100: 7562 hw->bus_speed = em_bus_speed_100; 7563 break; 7564 case E1000_STATUS_PCIX_SPEED_133: 7565 hw->bus_speed = em_bus_speed_133; 7566 break; 7567 default: 7568 hw->bus_speed = em_bus_speed_reserved; 7569 break; 7570 } 7571 } 7572 hw->bus_width = (status & E1000_STATUS_BUS64) ? 7573 em_bus_width_64 : em_bus_width_32; 7574 break; 7575 } 7576 } 7577 7578 /****************************************************************************** 7579 * Writes a value to one of the devices registers using port I/O (as opposed to 7580 * memory mapped I/O). Only 82544 and newer devices support port I/O. 7581 * 7582 * hw - Struct containing variables accessed by shared code 7583 * offset - offset to write to 7584 * value - value to write 7585 *****************************************************************************/ 7586 STATIC void 7587 em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value) 7588 { 7589 unsigned long io_addr = hw->io_base; 7590 unsigned long io_data = hw->io_base + 4; 7591 em_io_write(hw, io_addr, offset); 7592 em_io_write(hw, io_data, value); 7593 } 7594 7595 /****************************************************************************** 7596 * Estimates the cable length. 7597 * 7598 * hw - Struct containing variables accessed by shared code 7599 * min_length - The estimated minimum length 7600 * max_length - The estimated maximum length 7601 * 7602 * returns: - E1000_ERR_XXX 7603 * E1000_SUCCESS 7604 * 7605 * This function always returns a ranged length (minimum & maximum). 7606 * So for M88 phy's, this function interprets the one value returned from the 7607 * register to the minimum and maximum range. 7608 * For IGP phy's, the function calculates the range by the AGC registers. 7609 *****************************************************************************/ 7610 STATIC int32_t 7611 em_get_cable_length(struct em_hw *hw, uint16_t *min_length, 7612 uint16_t *max_length) 7613 { 7614 int32_t ret_val; 7615 uint16_t agc_value = 0; 7616 uint16_t i, phy_data; 7617 uint16_t cable_length; 7618 DEBUGFUNC("em_get_cable_length"); 7619 7620 *min_length = *max_length = 0; 7621 7622 /* Use old method for Phy older than IGP */ 7623 if (hw->phy_type == em_phy_m88 || 7624 hw->phy_type == em_phy_oem || 7625 hw->phy_type == em_phy_82578) { 7626 7627 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7628 &phy_data); 7629 if (ret_val) 7630 return ret_val; 7631 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 7632 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 7633 7634 /* Convert the enum value to ranged values */ 7635 switch (cable_length) { 7636 case em_cable_length_50: 7637 *min_length = 0; 7638 *max_length = em_igp_cable_length_50; 7639 break; 7640 case em_cable_length_50_80: 7641 *min_length = em_igp_cable_length_50; 7642 *max_length = em_igp_cable_length_80; 7643 break; 7644 case em_cable_length_80_110: 7645 *min_length = em_igp_cable_length_80; 7646 *max_length = em_igp_cable_length_110; 7647 break; 7648 case em_cable_length_110_140: 7649 *min_length = em_igp_cable_length_110; 7650 *max_length = em_igp_cable_length_140; 7651 break; 7652 case em_cable_length_140: 7653 *min_length = em_igp_cable_length_140; 7654 *max_length = em_igp_cable_length_170; 7655 break; 7656 default: 7657 return -E1000_ERR_PHY; 7658 break; 7659 } 7660 } else if (hw->phy_type == em_phy_gg82563) { 7661 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, 7662 &phy_data); 7663 if (ret_val) 7664 return ret_val; 7665 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; 7666 7667 switch (cable_length) { 7668 case em_gg_cable_length_60: 7669 *min_length = 0; 7670 *max_length = em_igp_cable_length_60; 7671 break; 7672 case em_gg_cable_length_60_115: 7673 *min_length = em_igp_cable_length_60; 7674 *max_length = em_igp_cable_length_115; 7675 break; 7676 case em_gg_cable_length_115_150: 7677 *min_length = em_igp_cable_length_115; 7678 *max_length = em_igp_cable_length_150; 7679 break; 7680 case em_gg_cable_length_150: 7681 *min_length = em_igp_cable_length_150; 7682 *max_length = em_igp_cable_length_180; 7683 break; 7684 default: 7685 return -E1000_ERR_PHY; 7686 break; 7687 } 7688 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ 7689 uint16_t cur_agc_value; 7690 uint16_t min_agc_value = 7691 IGP01E1000_AGC_LENGTH_TABLE_SIZE; 7692 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 7693 {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, 7694 IGP01E1000_PHY_AGC_C, IGP01E1000_PHY_AGC_D}; 7695 7696 /* Read the AGC registers for all channels */ 7697 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7698 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 7699 &phy_data); 7700 if (ret_val) 7701 return ret_val; 7702 7703 cur_agc_value = phy_data >> 7704 IGP01E1000_AGC_LENGTH_SHIFT; 7705 7706 /* Value bound check. */ 7707 if ((cur_agc_value >= 7708 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 7709 (cur_agc_value == 0)) 7710 return -E1000_ERR_PHY; 7711 7712 agc_value += cur_agc_value; 7713 7714 /* Update minimal AGC value. */ 7715 if (min_agc_value > cur_agc_value) 7716 min_agc_value = cur_agc_value; 7717 } 7718 7719 /* Remove the minimal AGC result for length < 50m */ 7720 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 7721 em_igp_cable_length_50) { 7722 agc_value -= min_agc_value; 7723 7724 /* 7725 * Get the average length of the remaining 3 channels 7726 */ 7727 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 7728 } else { 7729 /* Get the average length of all the 4 channels. */ 7730 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 7731 } 7732 7733 /* Set the range of the calculated length. */ 7734 *min_length = ((em_igp_cable_length_table[agc_value] - 7735 IGP01E1000_AGC_RANGE) > 0) ? 7736 (em_igp_cable_length_table[agc_value] - 7737 IGP01E1000_AGC_RANGE) : 0; 7738 *max_length = em_igp_cable_length_table[agc_value] + 7739 IGP01E1000_AGC_RANGE; 7740 } else if (hw->phy_type == em_phy_igp_2 || 7741 hw->phy_type == em_phy_igp_3) { 7742 uint16_t cur_agc_index, max_agc_index = 0; 7743 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; 7744 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 7745 {IGP02E1000_PHY_AGC_A, IGP02E1000_PHY_AGC_B, 7746 IGP02E1000_PHY_AGC_C, IGP02E1000_PHY_AGC_D}; 7747 /* Read the AGC registers for all channels */ 7748 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 7749 ret_val = em_read_phy_reg(hw, agc_reg_array[i], 7750 &phy_data); 7751 if (ret_val) 7752 return ret_val; 7753 /* 7754 * Getting bits 15:9, which represent the combination 7755 * of course and fine gain values. The result is a 7756 * number that can be put into the lookup table to 7757 * obtain the approximate cable length. 7758 */ 7759 cur_agc_index = (phy_data >> 7760 IGP02E1000_AGC_LENGTH_SHIFT) & 7761 IGP02E1000_AGC_LENGTH_MASK; 7762 7763 /* Array index bound check. */ 7764 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) 7765 || (cur_agc_index == 0)) 7766 return -E1000_ERR_PHY; 7767 7768 /* Remove min & max AGC values from calculation. */ 7769 if (em_igp_2_cable_length_table[min_agc_index] > 7770 em_igp_2_cable_length_table[cur_agc_index]) 7771 min_agc_index = cur_agc_index; 7772 if (em_igp_2_cable_length_table[max_agc_index] < 7773 em_igp_2_cable_length_table[cur_agc_index]) 7774 max_agc_index = cur_agc_index; 7775 7776 agc_value += em_igp_2_cable_length_table 7777 [cur_agc_index]; 7778 } 7779 7780 agc_value -= (em_igp_2_cable_length_table[min_agc_index] + 7781 em_igp_2_cable_length_table[max_agc_index]); 7782 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 7783 /* 7784 * Calculate cable length with the error range of +/- 10 7785 * meters. 7786 */ 7787 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 7788 (agc_value - IGP02E1000_AGC_RANGE) : 0; 7789 *max_length = agc_value + IGP02E1000_AGC_RANGE; 7790 } 7791 return E1000_SUCCESS; 7792 } 7793 7794 /****************************************************************************** 7795 * Check if Downshift occured 7796 * 7797 * hw - Struct containing variables accessed by shared code 7798 * downshift - output parameter : 0 - No Downshift ocured. 7799 * 1 - Downshift ocured. 7800 * 7801 * returns: - E1000_ERR_XXX 7802 * E1000_SUCCESS 7803 * 7804 * For phy's older then IGP, this function reads the Downshift bit in the Phy 7805 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the 7806 * Link Health register. In IGP this bit is latched high, so the driver must 7807 * read it immediately after link is established. 7808 *****************************************************************************/ 7809 STATIC int32_t 7810 em_check_downshift(struct em_hw *hw) 7811 { 7812 int32_t ret_val; 7813 uint16_t phy_data; 7814 DEBUGFUNC("em_check_downshift"); 7815 7816 if (hw->phy_type == em_phy_igp || 7817 hw->phy_type == em_phy_igp_3 || 7818 hw->phy_type == em_phy_igp_2) { 7819 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, 7820 &phy_data); 7821 if (ret_val) 7822 return ret_val; 7823 7824 hw->speed_downgraded = (phy_data & 7825 IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; 7826 } else if ((hw->phy_type == em_phy_m88) || 7827 (hw->phy_type == em_phy_gg82563) || 7828 (hw->phy_type == em_phy_oem) || 7829 (hw->phy_type == em_phy_82578)) { 7830 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, 7831 &phy_data); 7832 if (ret_val) 7833 return ret_val; 7834 7835 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> 7836 M88E1000_PSSR_DOWNSHIFT_SHIFT; 7837 } else if (hw->phy_type == em_phy_ife) { 7838 /* em_phy_ife supports 10/100 speed only */ 7839 hw->speed_downgraded = FALSE; 7840 } 7841 return E1000_SUCCESS; 7842 } 7843 7844 /***************************************************************************** 7845 * 7846 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 7847 * gigabit link is achieved to improve link quality. 7848 * 7849 * hw: Struct containing variables accessed by shared code 7850 * 7851 * returns: - E1000_ERR_PHY if fail to read/write the PHY 7852 * E1000_SUCCESS at any other case. 7853 * 7854 ****************************************************************************/ 7855 STATIC int32_t 7856 em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up) 7857 { 7858 int32_t ret_val; 7859 uint16_t phy_data, phy_saved_data, speed, duplex, i; 7860 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 7861 {IGP01E1000_PHY_AGC_PARAM_A, IGP01E1000_PHY_AGC_PARAM_B, 7862 IGP01E1000_PHY_AGC_PARAM_C, IGP01E1000_PHY_AGC_PARAM_D}; 7863 uint16_t min_length, max_length; 7864 DEBUGFUNC("em_config_dsp_after_link_change"); 7865 7866 if (hw->phy_type != em_phy_igp) 7867 return E1000_SUCCESS; 7868 7869 if (link_up) { 7870 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex); 7871 if (ret_val) { 7872 DEBUGOUT("Error getting link speed and duplex\n"); 7873 return ret_val; 7874 } 7875 if (speed == SPEED_1000) { 7876 7877 ret_val = em_get_cable_length(hw, &min_length, &max_length); 7878 if (ret_val) 7879 return ret_val; 7880 7881 if ((hw->dsp_config_state == em_dsp_config_enabled) && 7882 min_length >= em_igp_cable_length_50) { 7883 7884 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; 7885 i++) { 7886 ret_val = em_read_phy_reg(hw, 7887 dsp_reg_array[i], &phy_data); 7888 if (ret_val) 7889 return ret_val; 7890 7891 phy_data &= 7892 ~IGP01E1000_PHY_EDAC_MU_INDEX; 7893 7894 ret_val = em_write_phy_reg(hw, 7895 dsp_reg_array[i], phy_data); 7896 if (ret_val) 7897 return ret_val; 7898 } 7899 hw->dsp_config_state = em_dsp_config_activated; 7900 } 7901 if ((hw->ffe_config_state == em_ffe_config_enabled) && 7902 (min_length < em_igp_cable_length_50)) { 7903 7904 uint16_t ffe_idle_err_timeout = 7905 FFE_IDLE_ERR_COUNT_TIMEOUT_20; 7906 uint32_t idle_errs = 0; 7907 /* clear previous idle error counts */ 7908 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS, 7909 &phy_data); 7910 if (ret_val) 7911 return ret_val; 7912 7913 for (i = 0; i < ffe_idle_err_timeout; i++) { 7914 usec_delay(1000); 7915 ret_val = em_read_phy_reg(hw, 7916 PHY_1000T_STATUS, &phy_data); 7917 if (ret_val) 7918 return ret_val; 7919 7920 idle_errs += (phy_data & 7921 SR_1000T_IDLE_ERROR_CNT); 7922 if (idle_errs > 7923 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 7924 hw->ffe_config_state = 7925 em_ffe_config_active; 7926 7927 ret_val = em_write_phy_reg(hw, 7928 IGP01E1000_PHY_DSP_FFE, 7929 IGP01E1000_PHY_DSP_FFE_CM_CP); 7930 if (ret_val) 7931 return ret_val; 7932 break; 7933 } 7934 if (idle_errs) 7935 ffe_idle_err_timeout = 7936 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 7937 } 7938 } 7939 } 7940 } else { 7941 if (hw->dsp_config_state == em_dsp_config_activated) { 7942 /* 7943 * Save off the current value of register 0x2F5B to 7944 * be restored at the end of the routines. 7945 */ 7946 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 7947 7948 if (ret_val) 7949 return ret_val; 7950 7951 /* Disable the PHY transmitter */ 7952 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 7953 7954 if (ret_val) 7955 return ret_val; 7956 7957 msec_delay_irq(20); 7958 7959 ret_val = em_write_phy_reg(hw, 0x0000, 7960 IGP01E1000_IEEE_FORCE_GIGA); 7961 if (ret_val) 7962 return ret_val; 7963 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 7964 ret_val = em_read_phy_reg(hw, dsp_reg_array[i], 7965 &phy_data); 7966 if (ret_val) 7967 return ret_val; 7968 7969 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 7970 phy_data |= 7971 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 7972 7973 ret_val = em_write_phy_reg(hw, 7974 dsp_reg_array[i], phy_data); 7975 if (ret_val) 7976 return ret_val; 7977 } 7978 7979 ret_val = em_write_phy_reg(hw, 0x0000, 7980 IGP01E1000_IEEE_RESTART_AUTONEG); 7981 if (ret_val) 7982 return ret_val; 7983 7984 msec_delay_irq(20); 7985 7986 /* Now enable the transmitter */ 7987 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 7988 7989 if (ret_val) 7990 return ret_val; 7991 7992 hw->dsp_config_state = em_dsp_config_enabled; 7993 } 7994 if (hw->ffe_config_state == em_ffe_config_active) { 7995 /* 7996 * Save off the current value of register 0x2F5B to 7997 * be restored at the end of the routines. 7998 */ 7999 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data); 8000 8001 if (ret_val) 8002 return ret_val; 8003 8004 /* Disable the PHY transmitter */ 8005 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003); 8006 8007 if (ret_val) 8008 return ret_val; 8009 8010 msec_delay_irq(20); 8011 8012 ret_val = em_write_phy_reg(hw, 0x0000, 8013 IGP01E1000_IEEE_FORCE_GIGA); 8014 if (ret_val) 8015 return ret_val; 8016 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, 8017 IGP01E1000_PHY_DSP_FFE_DEFAULT); 8018 if (ret_val) 8019 return ret_val; 8020 8021 ret_val = em_write_phy_reg(hw, 0x0000, 8022 IGP01E1000_IEEE_RESTART_AUTONEG); 8023 if (ret_val) 8024 return ret_val; 8025 8026 msec_delay_irq(20); 8027 8028 /* Now enable the transmitter */ 8029 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data); 8030 8031 if (ret_val) 8032 return ret_val; 8033 8034 hw->ffe_config_state = em_ffe_config_enabled; 8035 } 8036 } 8037 return E1000_SUCCESS; 8038 } 8039 8040 /***************************************************************************** 8041 * Set PHY to class A mode 8042 * Assumes the following operations will follow to enable the new class mode. 8043 * 1. Do a PHY soft reset 8044 * 2. Restart auto-negotiation or force link. 8045 * 8046 * hw - Struct containing variables accessed by shared code 8047 ****************************************************************************/ 8048 static int32_t 8049 em_set_phy_mode(struct em_hw *hw) 8050 { 8051 int32_t ret_val; 8052 uint16_t eeprom_data; 8053 DEBUGFUNC("em_set_phy_mode"); 8054 8055 if ((hw->mac_type == em_82545_rev_3) && 8056 (hw->media_type == em_media_type_copper)) { 8057 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, 8058 &eeprom_data); 8059 if (ret_val) { 8060 return ret_val; 8061 } 8062 if ((eeprom_data != EEPROM_RESERVED_WORD) && 8063 (eeprom_data & EEPROM_PHY_CLASS_A)) { 8064 ret_val = em_write_phy_reg(hw, 8065 M88E1000_PHY_PAGE_SELECT, 0x000B); 8066 if (ret_val) 8067 return ret_val; 8068 ret_val = em_write_phy_reg(hw, 8069 M88E1000_PHY_GEN_CONTROL, 0x8104); 8070 if (ret_val) 8071 return ret_val; 8072 8073 hw->phy_reset_disable = FALSE; 8074 } 8075 } 8076 return E1000_SUCCESS; 8077 } 8078 8079 /***************************************************************************** 8080 * 8081 * This function sets the lplu state according to the active flag. When 8082 * activating lplu this function also disables smart speed and vise versa. 8083 * lplu will not be activated unless the device autonegotiation advertisement 8084 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8085 * hw: Struct containing variables accessed by shared code 8086 * active - true to enable lplu false to disable lplu. 8087 * 8088 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8089 * E1000_SUCCESS at any other case. 8090 * 8091 ****************************************************************************/ 8092 STATIC int32_t 8093 em_set_d3_lplu_state(struct em_hw *hw, boolean_t active) 8094 { 8095 uint32_t phy_ctrl = 0; 8096 int32_t ret_val; 8097 uint16_t phy_data; 8098 DEBUGFUNC("em_set_d3_lplu_state"); 8099 8100 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2 8101 && hw->phy_type != em_phy_igp_3) 8102 return E1000_SUCCESS; 8103 /* 8104 * During driver activity LPLU should not be used or it will attain 8105 * link from the lowest speeds starting from 10Mbps. The capability 8106 * is used for Dx transitions and states 8107 */ 8108 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) { 8109 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); 8110 if (ret_val) 8111 return ret_val; 8112 } else if (IS_ICH8(hw->mac_type)) { 8113 /* 8114 * MAC writes into PHY register based on the state transition 8115 * and start auto-negotiation. SW driver can overwrite the 8116 * settings in CSR PHY power control E1000_PHY_CTRL register. 8117 */ 8118 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8119 } else { 8120 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8121 &phy_data); 8122 if (ret_val) 8123 return ret_val; 8124 } 8125 8126 if (!active) { 8127 if (hw->mac_type == em_82541_rev_2 || 8128 hw->mac_type == em_82547_rev_2) { 8129 phy_data &= ~IGP01E1000_GMII_FLEX_SPD; 8130 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8131 phy_data); 8132 if (ret_val) 8133 return ret_val; 8134 } else { 8135 if (IS_ICH8(hw->mac_type)) { 8136 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 8137 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8138 } else { 8139 phy_data &= ~IGP02E1000_PM_D3_LPLU; 8140 ret_val = em_write_phy_reg(hw, 8141 IGP02E1000_PHY_POWER_MGMT, phy_data); 8142 if (ret_val) 8143 return ret_val; 8144 } 8145 } 8146 /* 8147 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8148 * during Dx states where the power conservation is most 8149 * important. During driver activity we should enable 8150 * SmartSpeed, so performance is maintained. 8151 */ 8152 if (hw->smart_speed == em_smart_speed_on) { 8153 ret_val = em_read_phy_reg(hw, 8154 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8155 if (ret_val) 8156 return ret_val; 8157 8158 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8159 ret_val = em_write_phy_reg(hw, 8160 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8161 if (ret_val) 8162 return ret_val; 8163 } else if (hw->smart_speed == em_smart_speed_off) { 8164 ret_val = em_read_phy_reg(hw, 8165 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8166 if (ret_val) 8167 return ret_val; 8168 8169 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8170 ret_val = em_write_phy_reg(hw, 8171 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8172 if (ret_val) 8173 return ret_val; 8174 } 8175 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) 8176 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || 8177 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { 8178 8179 if (hw->mac_type == em_82541_rev_2 || 8180 hw->mac_type == em_82547_rev_2) { 8181 phy_data |= IGP01E1000_GMII_FLEX_SPD; 8182 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, 8183 phy_data); 8184 if (ret_val) 8185 return ret_val; 8186 } else { 8187 if (IS_ICH8(hw->mac_type)) { 8188 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 8189 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8190 } else { 8191 phy_data |= IGP02E1000_PM_D3_LPLU; 8192 ret_val = em_write_phy_reg(hw, 8193 IGP02E1000_PHY_POWER_MGMT, phy_data); 8194 if (ret_val) 8195 return ret_val; 8196 } 8197 } 8198 8199 /* When LPLU is enabled we should disable SmartSpeed */ 8200 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8201 &phy_data); 8202 if (ret_val) 8203 return ret_val; 8204 8205 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8206 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8207 phy_data); 8208 if (ret_val) 8209 return ret_val; 8210 8211 } 8212 return E1000_SUCCESS; 8213 } 8214 8215 /***************************************************************************** 8216 * 8217 * This function sets the lplu d0 state according to the active flag. When 8218 * activating lplu this function also disables smart speed and vise versa. 8219 * lplu will not be activated unless the device autonegotiation advertisement 8220 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. 8221 * hw: Struct containing variables accessed by shared code 8222 * active - true to enable lplu false to disable lplu. 8223 * 8224 * returns: - E1000_ERR_PHY if fail to read/write the PHY 8225 * E1000_SUCCESS at any other case. 8226 * 8227 ****************************************************************************/ 8228 STATIC int32_t 8229 em_set_d0_lplu_state(struct em_hw *hw, boolean_t active) 8230 { 8231 uint32_t phy_ctrl = 0; 8232 int32_t ret_val; 8233 uint16_t phy_data; 8234 DEBUGFUNC("em_set_d0_lplu_state"); 8235 8236 if (hw->mac_type <= em_82547_rev_2) 8237 return E1000_SUCCESS; 8238 8239 if (IS_ICH8(hw->mac_type)) { 8240 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); 8241 } else { 8242 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, 8243 &phy_data); 8244 if (ret_val) 8245 return ret_val; 8246 } 8247 8248 if (!active) { 8249 if (IS_ICH8(hw->mac_type)) { 8250 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 8251 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8252 } else { 8253 phy_data &= ~IGP02E1000_PM_D0_LPLU; 8254 ret_val = em_write_phy_reg(hw, 8255 IGP02E1000_PHY_POWER_MGMT, phy_data); 8256 if (ret_val) 8257 return ret_val; 8258 } 8259 /* 8260 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 8261 * during Dx states where the power conservation is most 8262 * important. During driver activity we should enable 8263 * SmartSpeed, so performance is maintained. 8264 */ 8265 if (hw->smart_speed == em_smart_speed_on) { 8266 ret_val = em_read_phy_reg(hw, 8267 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8268 if (ret_val) 8269 return ret_val; 8270 8271 phy_data |= IGP01E1000_PSCFR_SMART_SPEED; 8272 ret_val = em_write_phy_reg(hw, 8273 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8274 if (ret_val) 8275 return ret_val; 8276 } else if (hw->smart_speed == em_smart_speed_off) { 8277 ret_val = em_read_phy_reg(hw, 8278 IGP01E1000_PHY_PORT_CONFIG, &phy_data); 8279 if (ret_val) 8280 return ret_val; 8281 8282 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8283 ret_val = em_write_phy_reg(hw, 8284 IGP01E1000_PHY_PORT_CONFIG, phy_data); 8285 if (ret_val) 8286 return ret_val; 8287 } 8288 } else { 8289 if (IS_ICH8(hw->mac_type)) { 8290 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 8291 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); 8292 } else { 8293 phy_data |= IGP02E1000_PM_D0_LPLU; 8294 ret_val = em_write_phy_reg(hw, 8295 IGP02E1000_PHY_POWER_MGMT, phy_data); 8296 if (ret_val) 8297 return ret_val; 8298 } 8299 8300 /* When LPLU is enabled we should disable SmartSpeed */ 8301 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8302 &phy_data); 8303 if (ret_val) 8304 return ret_val; 8305 8306 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; 8307 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 8308 phy_data); 8309 if (ret_val) 8310 return ret_val; 8311 8312 } 8313 return E1000_SUCCESS; 8314 } 8315 8316 /*************************************************************************** 8317 * Set Low Power Link Up state 8318 * 8319 * Sets the LPLU state according to the active flag. For PCH, if OEM write 8320 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 8321 * the phy speed. This function will manually set the LPLU bit and restart 8322 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 8323 * since it configures the same bit. 8324 ***************************************************************************/ 8325 int32_t 8326 em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active) 8327 { 8328 int32_t ret_val = E1000_SUCCESS; 8329 uint16_t oem_reg; 8330 8331 DEBUGFUNC("e1000_set_lplu_state_pchlan"); 8332 8333 ret_val = em_read_phy_reg(hw, HV_OEM_BITS, &oem_reg); 8334 if (ret_val) 8335 goto out; 8336 8337 if (active) 8338 oem_reg |= HV_OEM_BITS_LPLU; 8339 else 8340 oem_reg &= ~HV_OEM_BITS_LPLU; 8341 8342 oem_reg |= HV_OEM_BITS_RESTART_AN; 8343 ret_val = em_write_phy_reg(hw, HV_OEM_BITS, oem_reg); 8344 8345 out: 8346 return ret_val; 8347 } 8348 8349 /****************************************************************************** 8350 * Change VCO speed register to improve Bit Error Rate performance of SERDES. 8351 * 8352 * hw - Struct containing variables accessed by shared code 8353 *****************************************************************************/ 8354 static int32_t 8355 em_set_vco_speed(struct em_hw *hw) 8356 { 8357 int32_t ret_val; 8358 uint16_t default_page = 0; 8359 uint16_t phy_data; 8360 DEBUGFUNC("em_set_vco_speed"); 8361 8362 switch (hw->mac_type) { 8363 case em_82545_rev_3: 8364 case em_82546_rev_3: 8365 break; 8366 default: 8367 return E1000_SUCCESS; 8368 } 8369 8370 /* Set PHY register 30, page 5, bit 8 to 0 */ 8371 8372 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); 8373 if (ret_val) 8374 return ret_val; 8375 8376 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); 8377 if (ret_val) 8378 return ret_val; 8379 8380 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8381 if (ret_val) 8382 return ret_val; 8383 8384 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; 8385 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8386 if (ret_val) 8387 return ret_val; 8388 8389 /* Set PHY register 30, page 4, bit 11 to 1 */ 8390 8391 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); 8392 if (ret_val) 8393 return ret_val; 8394 8395 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); 8396 if (ret_val) 8397 return ret_val; 8398 8399 phy_data |= M88E1000_PHY_VCO_REG_BIT11; 8400 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); 8401 if (ret_val) 8402 return ret_val; 8403 8404 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); 8405 if (ret_val) 8406 return ret_val; 8407 8408 return E1000_SUCCESS; 8409 } 8410 8411 /***************************************************************************** 8412 * This function reads the cookie from ARC ram. 8413 * 8414 * returns: - E1000_SUCCESS . 8415 ****************************************************************************/ 8416 STATIC int32_t 8417 em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer) 8418 { 8419 uint8_t i; 8420 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; 8421 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; 8422 length = (length >> 2); 8423 offset = (offset >> 2); 8424 8425 for (i = 0; i < length; i++) { 8426 *((uint32_t *) buffer + i) = 8427 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); 8428 } 8429 return E1000_SUCCESS; 8430 } 8431 8432 /***************************************************************************** 8433 * This function checks whether the HOST IF is enabled for command operaton 8434 * and also checks whether the previous command is completed. 8435 * It busy waits in case of previous command is not completed. 8436 * 8437 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or 8438 * timeout 8439 * - E1000_SUCCESS for success. 8440 ****************************************************************************/ 8441 STATIC int32_t 8442 em_mng_enable_host_if(struct em_hw *hw) 8443 { 8444 uint32_t hicr; 8445 uint8_t i; 8446 /* Check that the host interface is enabled. */ 8447 hicr = E1000_READ_REG(hw, HICR); 8448 if ((hicr & E1000_HICR_EN) == 0) { 8449 DEBUGOUT("E1000_HOST_EN bit disabled.\n"); 8450 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8451 } 8452 /* check the previous command is completed */ 8453 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { 8454 hicr = E1000_READ_REG(hw, HICR); 8455 if (!(hicr & E1000_HICR_C)) 8456 break; 8457 msec_delay_irq(1); 8458 } 8459 8460 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { 8461 DEBUGOUT("Previous command timeout failed .\n"); 8462 return -E1000_ERR_HOST_INTERFACE_COMMAND; 8463 } 8464 return E1000_SUCCESS; 8465 } 8466 8467 /***************************************************************************** 8468 * This function checks the mode of the firmware. 8469 * 8470 * returns - TRUE when the mode is IAMT or FALSE. 8471 ****************************************************************************/ 8472 boolean_t 8473 em_check_mng_mode(struct em_hw *hw) 8474 { 8475 uint32_t fwsm; 8476 fwsm = E1000_READ_REG(hw, FWSM); 8477 8478 if (IS_ICH8(hw->mac_type)) { 8479 if ((fwsm & E1000_FWSM_MODE_MASK) == 8480 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8481 return TRUE; 8482 } else if ((fwsm & E1000_FWSM_MODE_MASK) == 8483 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) 8484 return TRUE; 8485 8486 return FALSE; 8487 } 8488 8489 /***************************************************************************** 8490 * This function calculates the checksum. 8491 * 8492 * returns - checksum of buffer contents. 8493 ****************************************************************************/ 8494 STATIC uint8_t 8495 em_calculate_mng_checksum(char *buffer, uint32_t length) 8496 { 8497 uint8_t sum = 0; 8498 uint32_t i; 8499 if (!buffer) 8500 return 0; 8501 8502 for (i = 0; i < length; i++) 8503 sum += buffer[i]; 8504 8505 return (uint8_t) (0 - sum); 8506 } 8507 8508 /***************************************************************************** 8509 * This function checks whether tx pkt filtering needs to be enabled or not. 8510 * 8511 * returns - TRUE for packet filtering or FALSE. 8512 ****************************************************************************/ 8513 boolean_t 8514 em_enable_tx_pkt_filtering(struct em_hw *hw) 8515 { 8516 /* called in init as well as watchdog timer functions */ 8517 int32_t ret_val, checksum; 8518 boolean_t tx_filter = FALSE; 8519 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); 8520 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie); 8521 if (em_check_mng_mode(hw)) { 8522 ret_val = em_mng_enable_host_if(hw); 8523 if (ret_val == E1000_SUCCESS) { 8524 ret_val = em_host_if_read_cookie(hw, buffer); 8525 if (ret_val == E1000_SUCCESS) { 8526 checksum = hdr->checksum; 8527 hdr->checksum = 0; 8528 if ((hdr->signature == E1000_IAMT_SIGNATURE) && 8529 checksum == em_calculate_mng_checksum( 8530 (char *) buffer, 8531 E1000_MNG_DHCP_COOKIE_LENGTH)) { 8532 if (hdr->status & 8533 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) 8534 tx_filter = TRUE; 8535 } else 8536 tx_filter = TRUE; 8537 } else 8538 tx_filter = TRUE; 8539 } 8540 } 8541 hw->tx_pkt_filtering = tx_filter; 8542 return tx_filter; 8543 } 8544 8545 static int32_t 8546 em_polarity_reversal_workaround(struct em_hw *hw) 8547 { 8548 int32_t ret_val; 8549 uint16_t mii_status_reg; 8550 uint16_t i; 8551 /* Polarity reversal workaround for forced 10F/10H links. */ 8552 8553 /* Disable the transmitter on the PHY */ 8554 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8555 if (ret_val) 8556 return ret_val; 8557 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 8558 if (ret_val) 8559 return ret_val; 8560 8561 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8562 if (ret_val) 8563 return ret_val; 8564 8565 /* This loop will early-out if the NO link condition has been met. */ 8566 for (i = PHY_FORCE_TIME; i > 0; i--) { 8567 /* 8568 * Read the MII Status Register and wait for Link Status bit 8569 * to be clear. 8570 */ 8571 8572 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8573 if (ret_val) 8574 return ret_val; 8575 8576 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8577 if (ret_val) 8578 return ret_val; 8579 8580 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 8581 break; 8582 msec_delay_irq(100); 8583 } 8584 8585 /* Recommended delay time after link has been lost */ 8586 msec_delay_irq(1000); 8587 8588 /* Now we will re-enable the transmitter on the PHY */ 8589 8590 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 8591 if (ret_val) 8592 return ret_val; 8593 msec_delay_irq(50); 8594 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 8595 if (ret_val) 8596 return ret_val; 8597 msec_delay_irq(50); 8598 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 8599 if (ret_val) 8600 return ret_val; 8601 msec_delay_irq(50); 8602 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 8603 if (ret_val) 8604 return ret_val; 8605 8606 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 8607 if (ret_val) 8608 return ret_val; 8609 8610 /* This loop will early-out if the link condition has been met. */ 8611 for (i = PHY_FORCE_TIME; i > 0; i--) { 8612 /* 8613 * Read the MII Status Register and wait for Link Status bit 8614 * to be set. 8615 */ 8616 8617 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8618 if (ret_val) 8619 return ret_val; 8620 8621 ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 8622 if (ret_val) 8623 return ret_val; 8624 8625 if (mii_status_reg & MII_SR_LINK_STATUS) 8626 break; 8627 msec_delay_irq(100); 8628 } 8629 return E1000_SUCCESS; 8630 } 8631 8632 /****************************************************************************** 8633 * 8634 * Disables PCI-Express master access. 8635 * 8636 * hw: Struct containing variables accessed by shared code 8637 * 8638 * returns: - none. 8639 * 8640 *****************************************************************************/ 8641 STATIC void 8642 em_set_pci_express_master_disable(struct em_hw *hw) 8643 { 8644 uint32_t ctrl; 8645 DEBUGFUNC("em_set_pci_express_master_disable"); 8646 8647 if (hw->bus_type != em_bus_type_pci_express) 8648 return; 8649 8650 ctrl = E1000_READ_REG(hw, CTRL); 8651 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 8652 E1000_WRITE_REG(hw, CTRL, ctrl); 8653 } 8654 8655 /****************************************************************************** 8656 * 8657 * Disables PCI-Express master access and verifies there are no pending 8658 * requests 8659 * 8660 * hw: Struct containing variables accessed by shared code 8661 * 8662 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't 8663 * caused the master requests to be disabled. 8664 * E1000_SUCCESS master requests disabled. 8665 * 8666 ******************************************************************************/ 8667 int32_t 8668 em_disable_pciex_master(struct em_hw *hw) 8669 { 8670 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ 8671 DEBUGFUNC("em_disable_pciex_master"); 8672 8673 if (hw->bus_type != em_bus_type_pci_express) 8674 return E1000_SUCCESS; 8675 8676 em_set_pci_express_master_disable(hw); 8677 8678 while (timeout) { 8679 if (!(E1000_READ_REG(hw, STATUS) & 8680 E1000_STATUS_GIO_MASTER_ENABLE)) 8681 break; 8682 else 8683 usec_delay(100); 8684 timeout--; 8685 } 8686 8687 if (!timeout) { 8688 DEBUGOUT("Master requests are pending.\n"); 8689 return -E1000_ERR_MASTER_REQUESTS_PENDING; 8690 } 8691 return E1000_SUCCESS; 8692 } 8693 8694 /****************************************************************************** 8695 * 8696 * Check for EEPROM Auto Read bit done. 8697 * 8698 * hw: Struct containing variables accessed by shared code 8699 * 8700 * returns: - E1000_ERR_RESET if fail to reset MAC 8701 * E1000_SUCCESS at any other case. 8702 * 8703 ******************************************************************************/ 8704 STATIC int32_t 8705 em_get_auto_rd_done(struct em_hw *hw) 8706 { 8707 int32_t timeout = AUTO_READ_DONE_TIMEOUT; 8708 DEBUGFUNC("em_get_auto_rd_done"); 8709 8710 switch (hw->mac_type) { 8711 default: 8712 msec_delay(5); 8713 break; 8714 case em_82571: 8715 case em_82572: 8716 case em_82573: 8717 case em_82574: 8718 case em_82575: 8719 case em_82580: 8720 case em_80003es2lan: 8721 case em_i210: 8722 case em_i350: 8723 case em_ich8lan: 8724 case em_ich9lan: 8725 case em_ich10lan: 8726 case em_pchlan: 8727 case em_pch2lan: 8728 case em_pch_lpt: 8729 while (timeout) { 8730 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 8731 break; 8732 else 8733 msec_delay(1); 8734 timeout--; 8735 } 8736 8737 if (!timeout) { 8738 DEBUGOUT("Auto read by HW from EEPROM has not" 8739 " completed.\n"); 8740 return -E1000_ERR_RESET; 8741 } 8742 break; 8743 } 8744 /* 8745 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to 8746 * high. Need to wait for PHY configuration completion before 8747 * accessing NVM and PHY. 8748 */ 8749 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) 8750 msec_delay(25); 8751 8752 return E1000_SUCCESS; 8753 } 8754 8755 /*************************************************************************** 8756 * Checks if the PHY configuration is done 8757 * 8758 * hw: Struct containing variables accessed by shared code 8759 * 8760 * returns: - E1000_ERR_RESET if fail to reset MAC 8761 * E1000_SUCCESS at any other case. 8762 * 8763 ***************************************************************************/ 8764 STATIC int32_t 8765 em_get_phy_cfg_done(struct em_hw *hw) 8766 { 8767 int32_t timeout = PHY_CFG_TIMEOUT; 8768 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_0; 8769 DEBUGFUNC("em_get_phy_cfg_done"); 8770 8771 switch (hw->mac_type) { 8772 default: 8773 msec_delay_irq(10); 8774 break; 8775 case em_80003es2lan: 8776 case em_82575: 8777 case em_82580: 8778 case em_i350: 8779 switch (hw->bus_func) { 8780 case 1: 8781 cfg_mask = E1000_NVM_CFG_DONE_PORT_1; 8782 break; 8783 case 2: 8784 cfg_mask = E1000_NVM_CFG_DONE_PORT_2; 8785 break; 8786 case 3: 8787 cfg_mask = E1000_NVM_CFG_DONE_PORT_3; 8788 break; 8789 } 8790 /* FALLTHROUGH */ 8791 case em_82571: 8792 case em_82572: 8793 while (timeout) { 8794 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) 8795 break; 8796 else 8797 msec_delay(1); 8798 timeout--; 8799 } 8800 if (!timeout) { 8801 DEBUGOUT("MNG configuration cycle has not completed." 8802 "\n"); 8803 } 8804 break; 8805 } 8806 8807 return E1000_SUCCESS; 8808 } 8809 8810 /*************************************************************************** 8811 * 8812 * Using the combination of SMBI and SWESMBI semaphore bits when resetting 8813 * adapter or Eeprom access. 8814 * 8815 * hw: Struct containing variables accessed by shared code 8816 * 8817 * returns: - E1000_ERR_EEPROM if fail to access EEPROM. 8818 * E1000_SUCCESS at any other case. 8819 * 8820 ***************************************************************************/ 8821 STATIC int32_t 8822 em_get_hw_eeprom_semaphore(struct em_hw *hw) 8823 { 8824 int32_t timeout; 8825 uint32_t swsm; 8826 DEBUGFUNC("em_get_hw_eeprom_semaphore"); 8827 8828 if (!hw->eeprom_semaphore_present) 8829 return E1000_SUCCESS; 8830 8831 if (hw->mac_type == em_80003es2lan) { 8832 /* Get the SW semaphore. */ 8833 if (em_get_software_semaphore(hw) != E1000_SUCCESS) 8834 return -E1000_ERR_EEPROM; 8835 } 8836 /* Get the FW semaphore. */ 8837 timeout = hw->eeprom.word_size + 1; 8838 while (timeout) { 8839 swsm = E1000_READ_REG(hw, SWSM); 8840 swsm |= E1000_SWSM_SWESMBI; 8841 E1000_WRITE_REG(hw, SWSM, swsm); 8842 /* if we managed to set the bit we got the semaphore. */ 8843 swsm = E1000_READ_REG(hw, SWSM); 8844 if (swsm & E1000_SWSM_SWESMBI) 8845 break; 8846 8847 usec_delay(50); 8848 timeout--; 8849 } 8850 8851 if (!timeout) { 8852 /* Release semaphores */ 8853 em_put_hw_eeprom_semaphore(hw); 8854 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set." 8855 "\n"); 8856 return -E1000_ERR_EEPROM; 8857 } 8858 return E1000_SUCCESS; 8859 } 8860 8861 /*************************************************************************** 8862 * This function clears HW semaphore bits. 8863 * 8864 * hw: Struct containing variables accessed by shared code 8865 * 8866 * returns: - None. 8867 * 8868 ***************************************************************************/ 8869 STATIC void 8870 em_put_hw_eeprom_semaphore(struct em_hw *hw) 8871 { 8872 uint32_t swsm; 8873 DEBUGFUNC("em_put_hw_eeprom_semaphore"); 8874 8875 if (!hw->eeprom_semaphore_present) 8876 return; 8877 8878 swsm = E1000_READ_REG(hw, SWSM); 8879 if (hw->mac_type == em_80003es2lan) { 8880 /* Release both semaphores. */ 8881 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 8882 } else 8883 swsm &= ~(E1000_SWSM_SWESMBI); 8884 E1000_WRITE_REG(hw, SWSM, swsm); 8885 } 8886 8887 /*************************************************************************** 8888 * 8889 * Obtaining software semaphore bit (SMBI) before resetting PHY. 8890 * 8891 * hw: Struct containing variables accessed by shared code 8892 * 8893 * returns: - E1000_ERR_RESET if fail to obtain semaphore. 8894 * E1000_SUCCESS at any other case. 8895 * 8896 ***************************************************************************/ 8897 STATIC int32_t 8898 em_get_software_semaphore(struct em_hw *hw) 8899 { 8900 int32_t timeout = hw->eeprom.word_size + 1; 8901 uint32_t swsm; 8902 DEBUGFUNC("em_get_software_semaphore"); 8903 8904 if (hw->mac_type != em_80003es2lan) 8905 return E1000_SUCCESS; 8906 8907 while (timeout) { 8908 swsm = E1000_READ_REG(hw, SWSM); 8909 /* 8910 * If SMBI bit cleared, it is now set and we hold the 8911 * semaphore 8912 */ 8913 if (!(swsm & E1000_SWSM_SMBI)) 8914 break; 8915 msec_delay_irq(1); 8916 timeout--; 8917 } 8918 8919 if (!timeout) { 8920 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 8921 return -E1000_ERR_RESET; 8922 } 8923 return E1000_SUCCESS; 8924 } 8925 8926 /*************************************************************************** 8927 * 8928 * Release semaphore bit (SMBI). 8929 * 8930 * hw: Struct containing variables accessed by shared code 8931 * 8932 ***************************************************************************/ 8933 STATIC void 8934 em_release_software_semaphore(struct em_hw *hw) 8935 { 8936 uint32_t swsm; 8937 DEBUGFUNC("em_release_software_semaphore"); 8938 8939 if (hw->mac_type != em_80003es2lan) 8940 return; 8941 8942 swsm = E1000_READ_REG(hw, SWSM); 8943 /* Release the SW semaphores. */ 8944 swsm &= ~E1000_SWSM_SMBI; 8945 E1000_WRITE_REG(hw, SWSM, swsm); 8946 } 8947 8948 /****************************************************************************** 8949 * Checks if PHY reset is blocked due to SOL/IDER session, for example. 8950 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to 8951 * the caller to figure out how to deal with it. 8952 * 8953 * hw - Struct containing variables accessed by shared code 8954 * 8955 * returns: - E1000_BLK_PHY_RESET 8956 * E1000_SUCCESS 8957 * 8958 *****************************************************************************/ 8959 int32_t 8960 em_check_phy_reset_block(struct em_hw *hw) 8961 { 8962 uint32_t manc = 0; 8963 uint32_t fwsm = 0; 8964 if (IS_ICH8(hw->mac_type)) { 8965 fwsm = E1000_READ_REG(hw, FWSM); 8966 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS : 8967 E1000_BLK_PHY_RESET; 8968 } 8969 if (hw->mac_type > em_82547_rev_2) 8970 manc = E1000_READ_REG(hw, MANC); 8971 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 8972 E1000_BLK_PHY_RESET : E1000_SUCCESS; 8973 } 8974 8975 /****************************************************************************** 8976 * Configure PCI-Ex no-snoop 8977 * 8978 * hw - Struct containing variables accessed by shared code. 8979 * no_snoop - Bitmap of no-snoop events. 8980 * 8981 * returns: E1000_SUCCESS 8982 * 8983 *****************************************************************************/ 8984 STATIC int32_t 8985 em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop) 8986 { 8987 uint32_t gcr_reg = 0; 8988 DEBUGFUNC("em_set_pci_ex_no_snoop"); 8989 8990 if (hw->bus_type == em_bus_type_unknown) 8991 em_get_bus_info(hw); 8992 8993 if (hw->bus_type != em_bus_type_pci_express) 8994 return E1000_SUCCESS; 8995 8996 if (no_snoop) { 8997 gcr_reg = E1000_READ_REG(hw, GCR); 8998 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); 8999 gcr_reg |= no_snoop; 9000 E1000_WRITE_REG(hw, GCR, gcr_reg); 9001 } 9002 if (IS_ICH8(hw->mac_type)) { 9003 uint32_t ctrl_ext; 9004 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 9005 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 9006 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 9007 } 9008 return E1000_SUCCESS; 9009 } 9010 9011 /*************************************************************************** 9012 * 9013 * Get software semaphore FLAG bit (SWFLAG). 9014 * SWFLAG is used to synchronize the access to all shared resource between 9015 * SW, FW and HW. 9016 * 9017 * hw: Struct containing variables accessed by shared code 9018 * 9019 ***************************************************************************/ 9020 STATIC int32_t 9021 em_get_software_flag(struct em_hw *hw) 9022 { 9023 int32_t timeout = PHY_CFG_TIMEOUT; 9024 uint32_t extcnf_ctrl; 9025 DEBUGFUNC("em_get_software_flag"); 9026 9027 if (IS_ICH8(hw->mac_type)) { 9028 while (timeout) { 9029 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9030 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 9031 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9032 9033 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9034 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 9035 break; 9036 msec_delay_irq(1); 9037 timeout--; 9038 } 9039 9040 if (!timeout) { 9041 DEBUGOUT("FW or HW locks the resource too long.\n"); 9042 return -E1000_ERR_CONFIG; 9043 } 9044 } 9045 return E1000_SUCCESS; 9046 } 9047 9048 /*************************************************************************** 9049 * 9050 * Release software semaphore FLAG bit (SWFLAG). 9051 * SWFLAG is used to synchronize the access to all shared resource between 9052 * SW, FW and HW. 9053 * 9054 * hw: Struct containing variables accessed by shared code 9055 * 9056 ***************************************************************************/ 9057 STATIC void 9058 em_release_software_flag(struct em_hw *hw) 9059 { 9060 uint32_t extcnf_ctrl; 9061 DEBUGFUNC("em_release_software_flag"); 9062 9063 if (IS_ICH8(hw->mac_type)) { 9064 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 9065 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 9066 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 9067 } 9068 return; 9069 } 9070 9071 /** 9072 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 9073 * @hw: pointer to the HW structure 9074 * @bank: pointer to the variable that returns the active bank 9075 * 9076 * Reads signature byte from the NVM using the flash access registers. 9077 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 9078 **/ 9079 int32_t 9080 em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank) 9081 { 9082 uint32_t eecd; 9083 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t); 9084 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 9085 uint8_t sig_byte = 0; 9086 int32_t ret_val; 9087 9088 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan"); 9089 9090 switch (hw->mac_type) { 9091 case em_ich8lan: 9092 case em_ich9lan: 9093 eecd = E1000_READ_REG(hw, EECD); 9094 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 9095 E1000_EECD_SEC1VAL_VALID_MASK) { 9096 if (eecd & E1000_EECD_SEC1VAL) 9097 *bank = 1; 9098 else 9099 *bank = 0; 9100 9101 return E1000_SUCCESS; 9102 } 9103 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 9104 /* fall-thru */ 9105 default: 9106 /* set bank to 0 in case flash read fails */ 9107 *bank = 0; 9108 9109 /* Check bank 0 */ 9110 ret_val = em_read_ich8_byte(hw, act_offset, 9111 &sig_byte); 9112 if (ret_val) 9113 return ret_val; 9114 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9115 E1000_ICH_NVM_SIG_VALUE) { 9116 *bank = 0; 9117 return E1000_SUCCESS; 9118 } 9119 9120 /* Check bank 1 */ 9121 ret_val = em_read_ich8_byte(hw, act_offset + 9122 bank1_offset, 9123 &sig_byte); 9124 if (ret_val) 9125 return ret_val; 9126 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 9127 E1000_ICH_NVM_SIG_VALUE) { 9128 *bank = 1; 9129 return E1000_SUCCESS; 9130 } 9131 9132 DEBUGOUT("ERROR: No valid NVM bank present\n"); 9133 return -1; 9134 } 9135 } 9136 9137 /****************************************************************************** 9138 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access 9139 * register. 9140 * 9141 * hw - Struct containing variables accessed by shared code 9142 * offset - offset of word in the EEPROM to read 9143 * data - word read from the EEPROM 9144 * words - number of words to read 9145 *****************************************************************************/ 9146 STATIC int32_t 9147 em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9148 uint16_t *data) 9149 { 9150 int32_t error = E1000_SUCCESS; 9151 uint32_t flash_bank = 0; 9152 uint32_t act_offset = 0; 9153 uint32_t bank_offset = 0; 9154 uint16_t word = 0; 9155 uint16_t i = 0; 9156 /* 9157 * We need to know which is the valid flash bank. In the event that 9158 * we didn't allocate eeprom_shadow_ram, we may not be managing 9159 * flash_bank. So it cannot be trusted and needs to be updated with 9160 * each read. 9161 */ 9162 9163 error = em_get_software_flag(hw); 9164 if (error != E1000_SUCCESS) 9165 return error; 9166 9167 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank); 9168 if (error != E1000_SUCCESS) { 9169 DEBUGOUT("Could not detect valid bank, assuming bank 0\n"); 9170 flash_bank = 0; 9171 } 9172 9173 /* 9174 * Adjust offset appropriately if we're on bank 1 - adjust for word 9175 * size 9176 */ 9177 bank_offset = flash_bank * (hw->flash_bank_size * 2); 9178 9179 for (i = 0; i < words; i++) { 9180 if (hw->eeprom_shadow_ram != NULL && 9181 hw->eeprom_shadow_ram[offset + i].modified == TRUE) { 9182 data[i] = 9183 hw->eeprom_shadow_ram[offset + i].eeprom_word; 9184 } else { 9185 /* The NVM part needs a byte offset, hence * 2 */ 9186 act_offset = bank_offset + ((offset + i) * 2); 9187 error = em_read_ich8_word(hw, act_offset, &word); 9188 if (error != E1000_SUCCESS) 9189 break; 9190 data[i] = word; 9191 } 9192 } 9193 9194 em_release_software_flag(hw); 9195 9196 return error; 9197 } 9198 9199 /****************************************************************************** 9200 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access 9201 * register. Actually, writes are written to the shadow ram cache in the hw 9202 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to 9203 * the NVM, which occurs when the NVM checksum is updated. 9204 * 9205 * hw - Struct containing variables accessed by shared code 9206 * offset - offset of word in the EEPROM to write 9207 * words - number of words to write 9208 * data - words to write to the EEPROM 9209 *****************************************************************************/ 9210 STATIC int32_t 9211 em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words, 9212 uint16_t *data) 9213 { 9214 uint32_t i = 0; 9215 int32_t error = E1000_SUCCESS; 9216 error = em_get_software_flag(hw); 9217 if (error != E1000_SUCCESS) 9218 return error; 9219 /* 9220 * A driver can write to the NVM only if it has eeprom_shadow_ram 9221 * allocated. Subsequent reads to the modified words are read from 9222 * this cached structure as well. Writes will only go into this 9223 * cached structure unless it's followed by a call to 9224 * em_update_eeprom_checksum() where it will commit the changes and 9225 * clear the "modified" field. 9226 */ 9227 if (hw->eeprom_shadow_ram != NULL) { 9228 for (i = 0; i < words; i++) { 9229 if ((offset + i) < E1000_SHADOW_RAM_WORDS) { 9230 hw->eeprom_shadow_ram[offset + i].modified = 9231 TRUE; 9232 hw->eeprom_shadow_ram[offset + i].eeprom_word = 9233 data[i]; 9234 } else { 9235 error = -E1000_ERR_EEPROM; 9236 break; 9237 } 9238 } 9239 } else { 9240 /* 9241 * Drivers have the option to not allocate eeprom_shadow_ram 9242 * as long as they don't perform any NVM writes. An attempt 9243 * in doing so will result in this error. 9244 */ 9245 error = -E1000_ERR_EEPROM; 9246 } 9247 9248 em_release_software_flag(hw); 9249 9250 return error; 9251 } 9252 9253 /****************************************************************************** 9254 * This function does initial flash setup so that a new read/write/erase cycle 9255 * can be started. 9256 * 9257 * hw - The pointer to the hw structure 9258 ****************************************************************************/ 9259 STATIC int32_t 9260 em_ich8_cycle_init(struct em_hw *hw) 9261 { 9262 union ich8_hws_flash_status hsfsts; 9263 int32_t error = E1000_ERR_EEPROM; 9264 int32_t i = 0; 9265 DEBUGFUNC("em_ich8_cycle_init"); 9266 9267 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 9268 9269 /* May be check the Flash Des Valid bit in Hw status */ 9270 if (hsfsts.hsf_status.fldesvalid == 0) { 9271 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be" 9272 " used."); 9273 return error; 9274 } 9275 /* Clear FCERR in Hw status by writing 1 */ 9276 /* Clear DAEL in Hw status by writing a 1 */ 9277 hsfsts.hsf_status.flcerr = 1; 9278 hsfsts.hsf_status.dael = 1; 9279 9280 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); 9281 /* 9282 * Either we should have a hardware SPI cycle in progress bit to 9283 * check against, in order to start a new cycle or FDONE bit should 9284 * be changed in the hardware so that it is 1 after harware reset, 9285 * which can then be used as an indication whether a cycle is in 9286 * progress or has been completed .. we should also have some 9287 * software semaphore mechanism to guard FDONE or the cycle in 9288 * progress bit so that two threads access to those bits can be 9289 * sequentiallized or a way so that 2 threads dont start the cycle at 9290 * the same time 9291 */ 9292 9293 if (hsfsts.hsf_status.flcinprog == 0) { 9294 /* 9295 * There is no cycle running at present, so we can start a 9296 * cycle 9297 */ 9298 /* Begin by setting Flash Cycle Done. */ 9299 hsfsts.hsf_status.flcdone = 1; 9300 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9301 hsfsts.regval); 9302 error = E1000_SUCCESS; 9303 } else { 9304 /* 9305 * otherwise poll for sometime so the current cycle has a 9306 * chance to end before giving up. 9307 */ 9308 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { 9309 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9310 ICH_FLASH_HSFSTS); 9311 if (hsfsts.hsf_status.flcinprog == 0) { 9312 error = E1000_SUCCESS; 9313 break; 9314 } 9315 usec_delay(1); 9316 } 9317 if (error == E1000_SUCCESS) { 9318 /* 9319 * Successful in waiting for previous cycle to 9320 * timeout, now set the Flash Cycle Done. 9321 */ 9322 hsfsts.hsf_status.flcdone = 1; 9323 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, 9324 hsfsts.regval); 9325 } else { 9326 DEBUGOUT("Flash controller busy, cannot get access"); 9327 } 9328 } 9329 return error; 9330 } 9331 9332 /****************************************************************************** 9333 * This function starts a flash cycle and waits for its completion 9334 * 9335 * hw - The pointer to the hw structure 9336 *****************************************************************************/ 9337 STATIC int32_t 9338 em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout) 9339 { 9340 union ich8_hws_flash_ctrl hsflctl; 9341 union ich8_hws_flash_status hsfsts; 9342 int32_t error = E1000_ERR_EEPROM; 9343 uint32_t i = 0; 9344 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 9345 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); 9346 hsflctl.hsf_ctrl.flcgo = 1; 9347 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); 9348 9349 /* wait till FDONE bit is set to 1 */ 9350 do { 9351 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9352 ICH_FLASH_HSFSTS); 9353 if (hsfsts.hsf_status.flcdone == 1) 9354 break; 9355 usec_delay(1); 9356 i++; 9357 } while (i < timeout); 9358 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { 9359 error = E1000_SUCCESS; 9360 } 9361 return error; 9362 } 9363 9364 /****************************************************************************** 9365 * Reads a byte or word from the NVM using the ICH8 flash access registers. 9366 * 9367 * hw - The pointer to the hw structure 9368 * index - The index of the byte or word to read. 9369 * size - Size of data to read, 1=byte 2=word 9370 * data - Pointer to the word to store the value read. 9371 *****************************************************************************/ 9372 STATIC int32_t 9373 em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9374 uint16_t *data) 9375 { 9376 union ich8_hws_flash_status hsfsts; 9377 union ich8_hws_flash_ctrl hsflctl; 9378 uint32_t flash_linear_address; 9379 uint32_t flash_data = 0; 9380 int32_t error = -E1000_ERR_EEPROM; 9381 int32_t count = 0; 9382 DEBUGFUNC("em_read_ich8_data"); 9383 9384 if (size < 1 || size > 2 || data == 0x0 || 9385 index > ICH_FLASH_LINEAR_ADDR_MASK) 9386 return error; 9387 9388 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9389 hw->flash_base_addr; 9390 9391 do { 9392 usec_delay(1); 9393 /* Steps */ 9394 error = em_ich8_cycle_init(hw); 9395 if (error != E1000_SUCCESS) 9396 break; 9397 9398 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9399 ICH_FLASH_HSFCTL); 9400 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9401 hsflctl.hsf_ctrl.fldbcount = size - 1; 9402 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 9403 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9404 hsflctl.regval); 9405 /* 9406 * Write the last 24 bits of index into Flash Linear address 9407 * field in Flash Address 9408 */ 9409 /* TODO: TBD maybe check the index against the size of flash */ 9410 9411 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9412 flash_linear_address); 9413 9414 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9415 /* 9416 * Check if FCERR is set to 1, if set to 1, clear it and try 9417 * the whole sequence a few more times, else read in (shift 9418 * in) the Flash Data0, the order is least significant byte 9419 * first msb to lsb 9420 */ 9421 if (error == E1000_SUCCESS) { 9422 flash_data = E1000_READ_ICH_FLASH_REG(hw, 9423 ICH_FLASH_FDATA0); 9424 if (size == 1) { 9425 *data = (uint8_t) (flash_data & 0x000000FF); 9426 } else if (size == 2) { 9427 *data = (uint16_t) (flash_data & 0x0000FFFF); 9428 } 9429 break; 9430 } else { 9431 /* 9432 * If we've gotten here, then things are probably 9433 * completely hosed, but if the error condition is 9434 * detected, it won't hurt to give it another 9435 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9436 */ 9437 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9438 ICH_FLASH_HSFSTS); 9439 if (hsfsts.hsf_status.flcerr == 1) { 9440 /* Repeat for some time before giving up. */ 9441 continue; 9442 } else if (hsfsts.hsf_status.flcdone == 0) { 9443 DEBUGOUT("Timeout error - flash cycle did not" 9444 " complete."); 9445 break; 9446 } 9447 } 9448 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9449 9450 return error; 9451 } 9452 9453 /****************************************************************************** 9454 * Writes One /two bytes to the NVM using the ICH8 flash access registers. 9455 * 9456 * hw - The pointer to the hw structure 9457 * index - The index of the byte/word to read. 9458 * size - Size of data to read, 1=byte 2=word 9459 * data - The byte(s) to write to the NVM. 9460 *****************************************************************************/ 9461 STATIC int32_t 9462 em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size, 9463 uint16_t data) 9464 { 9465 union ich8_hws_flash_status hsfsts; 9466 union ich8_hws_flash_ctrl hsflctl; 9467 uint32_t flash_linear_address; 9468 uint32_t flash_data = 0; 9469 int32_t error = -E1000_ERR_EEPROM; 9470 int32_t count = 0; 9471 DEBUGFUNC("em_write_ich8_data"); 9472 9473 if (size < 1 || size > 2 || data > size * 0xff || 9474 index > ICH_FLASH_LINEAR_ADDR_MASK) 9475 return error; 9476 9477 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + 9478 hw->flash_base_addr; 9479 9480 do { 9481 usec_delay(1); 9482 /* Steps */ 9483 error = em_ich8_cycle_init(hw); 9484 if (error != E1000_SUCCESS) 9485 break; 9486 9487 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9488 ICH_FLASH_HSFCTL); 9489 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 9490 hsflctl.hsf_ctrl.fldbcount = size - 1; 9491 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 9492 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9493 hsflctl.regval); 9494 /* 9495 * Write the last 24 bits of index into Flash Linear address 9496 * field in Flash Address 9497 */ 9498 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9499 flash_linear_address); 9500 9501 if (size == 1) 9502 flash_data = (uint32_t) data & 0x00FF; 9503 else 9504 flash_data = (uint32_t) data; 9505 9506 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); 9507 /* 9508 * check if FCERR is set to 1 , if set to 1, clear it and try 9509 * the whole sequence a few more times else done 9510 */ 9511 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); 9512 if (error == E1000_SUCCESS) { 9513 break; 9514 } else { 9515 /* 9516 * If we're here, then things are most likely 9517 * completely hosed, but if the error condition is 9518 * detected, it won't hurt to give it another 9519 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 9520 */ 9521 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9522 ICH_FLASH_HSFSTS); 9523 if (hsfsts.hsf_status.flcerr == 1) { 9524 /* Repeat for some time before giving up. */ 9525 continue; 9526 } else if (hsfsts.hsf_status.flcdone == 0) { 9527 DEBUGOUT("Timeout error - flash cycle did not" 9528 " complete."); 9529 break; 9530 } 9531 } 9532 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 9533 9534 return error; 9535 } 9536 9537 /****************************************************************************** 9538 * Reads a single byte from the NVM using the ICH8 flash access registers. 9539 * 9540 * hw - pointer to em_hw structure 9541 * index - The index of the byte to read. 9542 * data - Pointer to a byte to store the value read. 9543 *****************************************************************************/ 9544 STATIC int32_t 9545 em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data) 9546 { 9547 int32_t status = E1000_SUCCESS; 9548 uint16_t word = 0; 9549 status = em_read_ich8_data(hw, index, 1, &word); 9550 if (status == E1000_SUCCESS) { 9551 *data = (uint8_t) word; 9552 } 9553 return status; 9554 } 9555 9556 /****************************************************************************** 9557 * Writes a single byte to the NVM using the ICH8 flash access registers. 9558 * Performs verification by reading back the value and then going through 9559 * a retry algorithm before giving up. 9560 * 9561 * hw - pointer to em_hw structure 9562 * index - The index of the byte to write. 9563 * byte - The byte to write to the NVM. 9564 *****************************************************************************/ 9565 STATIC int32_t 9566 em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte) 9567 { 9568 int32_t error = E1000_SUCCESS; 9569 int32_t program_retries = 0; 9570 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); 9571 9572 error = em_write_ich8_byte(hw, index, byte); 9573 9574 if (error != E1000_SUCCESS) { 9575 for (program_retries = 0; program_retries < 100; 9576 program_retries++) { 9577 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", 9578 byte, index); 9579 error = em_write_ich8_byte(hw, index, byte); 9580 usec_delay(100); 9581 if (error == E1000_SUCCESS) 9582 break; 9583 } 9584 } 9585 if (program_retries == 100) 9586 error = E1000_ERR_EEPROM; 9587 9588 return error; 9589 } 9590 9591 /****************************************************************************** 9592 * Writes a single byte to the NVM using the ICH8 flash access registers. 9593 * 9594 * hw - pointer to em_hw structure 9595 * index - The index of the byte to read. 9596 * data - The byte to write to the NVM. 9597 *****************************************************************************/ 9598 STATIC int32_t 9599 em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data) 9600 { 9601 int32_t status = E1000_SUCCESS; 9602 uint16_t word = (uint16_t) data; 9603 status = em_write_ich8_data(hw, index, 1, word); 9604 9605 return status; 9606 } 9607 9608 /****************************************************************************** 9609 * Reads a word from the NVM using the ICH8 flash access registers. 9610 * 9611 * hw - pointer to em_hw structure 9612 * index - The starting byte index of the word to read. 9613 * data - Pointer to a word to store the value read. 9614 *****************************************************************************/ 9615 STATIC int32_t 9616 em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data) 9617 { 9618 int32_t status = E1000_SUCCESS; 9619 status = em_read_ich8_data(hw, index, 2, data); 9620 return status; 9621 } 9622 9623 /****************************************************************************** 9624 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 9625 * based. 9626 * 9627 * hw - pointer to em_hw structure 9628 * bank - 0 for first bank, 1 for second bank 9629 * 9630 * Note that this function may actually erase as much as 8 or 64 KBytes. The 9631 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the 9632 * bank size may be 4, 8 or 64 KBytes 9633 *****************************************************************************/ 9634 int32_t 9635 em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) 9636 { 9637 union ich8_hws_flash_status hsfsts; 9638 union ich8_hws_flash_ctrl hsflctl; 9639 uint32_t flash_linear_address; 9640 int32_t count = 0; 9641 int32_t error = E1000_ERR_EEPROM; 9642 int32_t iteration; 9643 int32_t sub_sector_size = 0; 9644 int32_t bank_size; 9645 int32_t j = 0; 9646 int32_t error_flag = 0; 9647 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); 9648 /* 9649 * Determine HW Sector size: Read BERASE bits of Hw flash Status 9650 * register 9651 */ 9652 /* 9653 * 00: The Hw sector is 256 bytes, hence we need to erase 16 9654 * consecutive sectors. The start index for the nth Hw sector can be 9655 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes, 9656 * hence we need to erase 1 sector. The start index for the nth Hw 9657 * sector can be calculated as bank * 4096 10: The HW sector is 8K 9658 * bytes 11: The Hw sector size is 64K bytes 9659 */ 9660 if (hsfsts.hsf_status.berasesz == 0x0) { 9661 /* Hw sector size 256 */ 9662 sub_sector_size = ICH_FLASH_SEG_SIZE_256; 9663 bank_size = ICH_FLASH_SECTOR_SIZE; 9664 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; 9665 } else if (hsfsts.hsf_status.berasesz == 0x1) { 9666 bank_size = ICH_FLASH_SEG_SIZE_4K; 9667 iteration = 1; 9668 } else if (hsfsts.hsf_status.berasesz == 0x2) { 9669 if (hw->mac_type == em_ich9lan) { 9670 uint32_t gfpreg, sector_base_addr, sector_end_addr; 9671 gfpreg = E1000_READ_ICH_FLASH_REG(hw, 9672 ICH_FLASH_GFPREG); 9673 /* 9674 * sector_X_addr is a "sector"-aligned address (4096 bytes) 9675 * Add 1 to sector_end_addr since this sector is included in 9676 * the overall size. 9677 */ 9678 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; 9679 sector_end_addr = 9680 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; 9681 9682 /* 9683 * find total size of the NVM, then cut in half since the total 9684 * size represents two separate NVM banks. 9685 */ 9686 bank_size = (sector_end_addr - sector_base_addr) 9687 << ICH_FLASH_SECT_ADDR_SHIFT; 9688 bank_size /= 2; 9689 /* Word align */ 9690 bank_size = 9691 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); 9692 9693 sub_sector_size = ICH_FLASH_SEG_SIZE_8K; 9694 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K; 9695 } else { 9696 return error; 9697 } 9698 } else if (hsfsts.hsf_status.berasesz == 0x3) { 9699 bank_size = ICH_FLASH_SEG_SIZE_64K; 9700 iteration = 1; 9701 } else { 9702 return error; 9703 } 9704 9705 for (j = 0; j < iteration; j++) { 9706 do { 9707 count++; 9708 /* Steps */ 9709 error = em_ich8_cycle_init(hw); 9710 if (error != E1000_SUCCESS) { 9711 error_flag = 1; 9712 break; 9713 } 9714 /* 9715 * Write a value 11 (block Erase) in Flash Cycle 9716 * field in Hw flash Control 9717 */ 9718 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, 9719 ICH_FLASH_HSFCTL); 9720 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 9721 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, 9722 hsflctl.regval); 9723 /* 9724 * Write the last 24 bits of an index within the 9725 * block into Flash Linear address field in Flash 9726 * Address. This probably needs to be calculated 9727 * here based off the on-chip erase sector size and 9728 * the software bank size (4, 8 or 64 KBytes) 9729 */ 9730 flash_linear_address = 9731 bank * bank_size + j * sub_sector_size; 9732 flash_linear_address += hw->flash_base_addr; 9733 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; 9734 9735 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, 9736 flash_linear_address); 9737 9738 error = 9739 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); 9740 /* 9741 * Check if FCERR is set to 1. If 1, clear it and 9742 * try the whole sequence a few more times else Done 9743 */ 9744 if (error == E1000_SUCCESS) { 9745 break; 9746 } else { 9747 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, 9748 ICH_FLASH_HSFSTS); 9749 if (hsfsts.hsf_status.flcerr == 1) { 9750 /* 9751 * repeat for some time before giving 9752 * up 9753 */ 9754 continue; 9755 } else if (hsfsts.hsf_status.flcdone == 0) { 9756 error_flag = 1; 9757 break; 9758 } 9759 } 9760 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); 9761 if (error_flag == 1) 9762 break; 9763 } 9764 if (error_flag != 1) 9765 error = E1000_SUCCESS; 9766 return error; 9767 } 9768 9769 /****************************************************************************** 9770 * Reads 16-bit words from the OTP. Return error when the word is not 9771 * stored in OTP. 9772 * 9773 * hw - Struct containing variables accessed by shared code 9774 * offset - offset of word in the OTP to read 9775 * data - word read from the OTP 9776 * words - number of words to read 9777 *****************************************************************************/ 9778 STATIC int32_t 9779 em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words, 9780 uint16_t *data) 9781 { 9782 int32_t ret_val = E1000_SUCCESS; 9783 9784 switch (offset) 9785 { 9786 case EEPROM_MAC_ADDR_WORD0: 9787 case EEPROM_MAC_ADDR_WORD1: 9788 case EEPROM_MAC_ADDR_WORD2: 9789 /* Generate random MAC address if there's none. */ 9790 ret_val = em_read_invm_word_i210(hw, offset, data); 9791 if (ret_val != E1000_SUCCESS) { 9792 DEBUGOUT("MAC Addr not found in iNVM\n"); 9793 *data = 0xFFFF; 9794 ret_val = E1000_SUCCESS; 9795 } 9796 break; 9797 case EEPROM_INIT_CONTROL2_REG: 9798 ret_val = em_read_invm_word_i210(hw, offset, data); 9799 if (ret_val != E1000_SUCCESS) { 9800 *data = NVM_INIT_CTRL_2_DEFAULT_I211; 9801 ret_val = E1000_SUCCESS; 9802 } 9803 break; 9804 case EEPROM_INIT_CONTROL4_REG: 9805 ret_val = em_read_invm_word_i210(hw, offset, data); 9806 if (ret_val != E1000_SUCCESS) { 9807 *data = NVM_INIT_CTRL_4_DEFAULT_I211; 9808 ret_val = E1000_SUCCESS; 9809 } 9810 break; 9811 case EEPROM_LED_1_CFG: 9812 ret_val = em_read_invm_word_i210(hw, offset, data); 9813 if (ret_val != E1000_SUCCESS) { 9814 *data = NVM_LED_1_CFG_DEFAULT_I211; 9815 ret_val = E1000_SUCCESS; 9816 } 9817 break; 9818 case EEPROM_LED_0_2_CFG: 9819 ret_val = em_read_invm_word_i210(hw, offset, data); 9820 if (ret_val != E1000_SUCCESS) { 9821 *data = NVM_LED_0_2_CFG_DEFAULT_I211; 9822 ret_val = E1000_SUCCESS; 9823 } 9824 break; 9825 case EEPROM_ID_LED_SETTINGS: 9826 ret_val = em_read_invm_word_i210(hw, offset, data); 9827 if (ret_val != E1000_SUCCESS) { 9828 *data = ID_LED_RESERVED_FFFF; 9829 ret_val = E1000_SUCCESS; 9830 } 9831 break; 9832 default: 9833 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset); 9834 *data = NVM_RESERVED_WORD; 9835 break; 9836 } 9837 9838 return ret_val; 9839 } 9840 9841 /****************************************************************************** 9842 * Reads 16-bit words from the OTP. Return error when the word is not 9843 * stored in OTP. 9844 * 9845 * hw - Struct containing variables accessed by shared code 9846 * offset - offset of word in the OTP to read 9847 * data - word read from the OTP 9848 *****************************************************************************/ 9849 STATIC int32_t 9850 em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data) 9851 { 9852 int32_t error = -E1000_NOT_IMPLEMENTED; 9853 uint32_t invm_dword; 9854 uint16_t i; 9855 uint8_t record_type, word_address; 9856 9857 for (i = 0; i < INVM_SIZE; i++) { 9858 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i)); 9859 /* Get record type */ 9860 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword); 9861 if (record_type == INVM_UNINITIALIZED_STRUCTURE) 9862 break; 9863 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE) 9864 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS; 9865 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE) 9866 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS; 9867 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE) { 9868 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword); 9869 if (word_address == address) { 9870 *data = INVM_DWORD_TO_WORD_DATA(invm_dword); 9871 error = E1000_SUCCESS; 9872 break; 9873 } 9874 } 9875 } 9876 9877 return error; 9878 } 9879 9880 STATIC int32_t 9881 em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr, 9882 uint32_t cnf_size) 9883 { 9884 uint32_t ret_val = E1000_SUCCESS; 9885 uint16_t word_addr, reg_data, reg_addr; 9886 uint16_t i; 9887 /* cnf_base_addr is in DWORD */ 9888 word_addr = (uint16_t) (cnf_base_addr << 1); 9889 9890 /* cnf_size is returned in size of dwords */ 9891 for (i = 0; i < cnf_size; i++) { 9892 ret_val = 9893 em_read_eeprom(hw, (word_addr + i * 2), 1, ®_data); 9894 if (ret_val) 9895 return ret_val; 9896 9897 ret_val = 9898 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, ®_addr); 9899 if (ret_val) 9900 return ret_val; 9901 9902 ret_val = em_get_software_flag(hw); 9903 if (ret_val != E1000_SUCCESS) 9904 return ret_val; 9905 9906 ret_val = 9907 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data); 9908 9909 em_release_software_flag(hw); 9910 } 9911 9912 return ret_val; 9913 } 9914 9915 /****************************************************************************** 9916 * This function initializes the PHY from the NVM on ICH8 platforms. This 9917 * is needed due to an issue where the NVM configuration is not properly 9918 * autoloaded after power transitions. Therefore, after each PHY reset, we 9919 * will load the configuration data out of the NVM manually. 9920 * 9921 * hw: Struct containing variables accessed by shared code 9922 *****************************************************************************/ 9923 STATIC int32_t 9924 em_init_lcd_from_nvm(struct em_hw *hw) 9925 { 9926 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; 9927 if (hw->phy_type != em_phy_igp_3) 9928 return E1000_SUCCESS; 9929 9930 /* Check if SW needs configure the PHY */ 9931 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT || 9932 hw->device_id == E1000_DEV_ID_ICH8_IGP_M || 9933 hw->mac_type == em_pchlan || 9934 hw->mac_type == em_pch2lan || 9935 hw->mac_type == em_pch_lpt) 9936 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M; 9937 else 9938 sw_cfg_mask = FEXTNVM_SW_CONFIG; 9939 9940 reg_data = E1000_READ_REG(hw, FEXTNVM); 9941 if (!(reg_data & sw_cfg_mask)) 9942 return E1000_SUCCESS; 9943 9944 /* Wait for basic configuration completes before proceeding */ 9945 loop = 0; 9946 do { 9947 reg_data = 9948 E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; 9949 usec_delay(100); 9950 loop++; 9951 } while ((!reg_data) && (loop < 50)); 9952 9953 /* Clear the Init Done bit for the next init event */ 9954 reg_data = E1000_READ_REG(hw, STATUS); 9955 reg_data &= ~E1000_STATUS_LAN_INIT_DONE; 9956 E1000_WRITE_REG(hw, STATUS, reg_data); 9957 /* 9958 * Make sure HW does not configure LCD from PHY extended 9959 * configuration before SW configuration 9960 */ 9961 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 9962 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { 9963 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); 9964 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; 9965 cnf_size >>= 16; 9966 if (cnf_size) { 9967 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); 9968 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; 9969 /* cnf_base_addr is in DWORD */ 9970 cnf_base_addr >>= 16; 9971 9972 /* Configure LCD from extended configuration region. */ 9973 ret_val = em_init_lcd_from_nvm_config_region(hw, 9974 cnf_base_addr, cnf_size); 9975 if (ret_val) 9976 return ret_val; 9977 } 9978 } 9979 return E1000_SUCCESS; 9980 } 9981 9982 /****************************************************************************** 9983 * em_set_pciex_completion_timeout - set pci-e completion timeout 9984 * 9985 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 9986 * however the hardware default for these parts is 500us to 1ms which is less 9987 * than the 10ms recommended by the pci-e spec. To address this we need to 9988 * increase the value to either 10ms to 200ms for capability version 1 config, 9989 * or 16ms to 55ms for version 2. 9990 * 9991 * * hw - pointer to em_hw structure 9992 *****************************************************************************/ 9993 int32_t 9994 em_set_pciex_completion_timeout(struct em_hw *hw) 9995 { 9996 uint32_t gcr = E1000_READ_REG(hw, GCR); 9997 int32_t ret_val = E1000_SUCCESS; 9998 9999 /* Only take action if timeout value is not set by system BIOS */ 10000 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 10001 goto out; 10002 10003 DEBUGOUT("PCIe completion timeout not set by system BIOS."); 10004 10005 /* 10006 * If capababilities version is type 1 we can write the 10007 * timeout of 10ms to 200ms through the GCR register 10008 */ 10009 10010 if (!(gcr & E1000_GCR_CAP_VER2)) { 10011 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 10012 DEBUGOUT("PCIe capability version 1 detected, setting \ 10013 completion timeout to 10ms."); 10014 goto out; 10015 } 10016 10017 /* 10018 * For version 2 capabilities we need to write the config space 10019 * directly in order to set the completion timeout value for 10020 * 16ms to 55ms 10021 * 10022 * XXX: Implement em_*_pcie_cap_reg() first. 10023 */ 10024 #if 0 10025 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10026 &pciex_devctl2); 10027 10028 if (ret_val) 10029 goto out; 10030 10031 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 10032 10033 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 10034 &pciex_devctl2); 10035 #endif 10036 10037 out: 10038 10039 /* Disable completion timeout resend */ 10040 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 10041 10042 DEBUGOUT("PCIe completion timeout resend disabled."); 10043 10044 E1000_WRITE_REG(hw, GCR, gcr); 10045 return ret_val; 10046 } 10047 10048 /*************************************************************************** 10049 * Set slow MDIO access mode 10050 ***************************************************************************/ 10051 static int32_t 10052 em_set_mdio_slow_mode_hv(struct em_hw *hw) 10053 { 10054 int32_t ret_val; 10055 uint16_t data; 10056 DEBUGFUNC("em_set_mdio_slow_mode_hv"); 10057 10058 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL, &data); 10059 if (ret_val) 10060 return ret_val; 10061 10062 data |= HV_KMRN_MDIO_SLOW; 10063 10064 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL, data); 10065 10066 return ret_val; 10067 } 10068 10069 /*************************************************************************** 10070 * A series of Phy workarounds to be done after every PHY reset. 10071 ***************************************************************************/ 10072 int32_t 10073 em_hv_phy_workarounds_ich8lan(struct em_hw *hw) 10074 { 10075 int32_t ret_val = E1000_SUCCESS; 10076 uint16_t phy_data; 10077 uint16_t swfw; 10078 DEBUGFUNC("em_hv_phy_workarounds_ich8lan"); 10079 10080 if (hw->mac_type != em_pchlan) 10081 goto out; 10082 10083 swfw = E1000_SWFW_PHY0_SM; 10084 10085 /* Set MDIO slow mode before any other MDIO access */ 10086 if (hw->phy_type == em_phy_82577 || 10087 hw->phy_type == em_phy_82578) { 10088 ret_val = em_set_mdio_slow_mode_hv(hw); 10089 if (ret_val) 10090 goto out; 10091 } 10092 10093 /* Hanksville M Phy init for IEEE. */ 10094 if ((hw->revision_id == 2) && 10095 (hw->phy_type == em_phy_82577) && 10096 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10097 em_write_phy_reg(hw, 0x10, 0x8823); 10098 em_write_phy_reg(hw, 0x11, 0x0018); 10099 em_write_phy_reg(hw, 0x10, 0x8824); 10100 em_write_phy_reg(hw, 0x11, 0x0016); 10101 em_write_phy_reg(hw, 0x10, 0x8825); 10102 em_write_phy_reg(hw, 0x11, 0x001A); 10103 em_write_phy_reg(hw, 0x10, 0x888C); 10104 em_write_phy_reg(hw, 0x11, 0x0007); 10105 em_write_phy_reg(hw, 0x10, 0x888D); 10106 em_write_phy_reg(hw, 0x11, 0x0007); 10107 em_write_phy_reg(hw, 0x10, 0x888E); 10108 em_write_phy_reg(hw, 0x11, 0x0007); 10109 em_write_phy_reg(hw, 0x10, 0x8827); 10110 em_write_phy_reg(hw, 0x11, 0x0001); 10111 em_write_phy_reg(hw, 0x10, 0x8835); 10112 em_write_phy_reg(hw, 0x11, 0x0001); 10113 em_write_phy_reg(hw, 0x10, 0x8834); 10114 em_write_phy_reg(hw, 0x11, 0x0001); 10115 em_write_phy_reg(hw, 0x10, 0x8833); 10116 em_write_phy_reg(hw, 0x11, 0x0002); 10117 } 10118 10119 if (((hw->phy_type == em_phy_82577) && 10120 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) || 10121 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) { 10122 /* Disable generation of early preamble */ 10123 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25), 0x4431); 10124 if (ret_val) 10125 goto out; 10126 10127 /* Preamble tuning for SSC */ 10128 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16), 0xA204); 10129 if (ret_val) 10130 goto out; 10131 } 10132 10133 if (hw->phy_type == em_phy_82578) { 10134 /* 10135 * Return registers to default by doing a soft reset then 10136 * writing 0x3140 to the control register. 10137 */ 10138 if (hw->phy_revision < 2) { 10139 em_phy_reset(hw); 10140 ret_val = em_write_phy_reg(hw, PHY_CTRL, 0x3140); 10141 } 10142 } 10143 10144 if ((hw->revision_id == 2) && 10145 (hw->phy_type == em_phy_82577) && 10146 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) { 10147 /* 10148 * Workaround for OEM (GbE) not operating after reset - 10149 * restart AN (twice) 10150 */ 10151 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 10152 if (ret_val) 10153 goto out; 10154 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25), 0x0400); 10155 if (ret_val) 10156 goto out; 10157 } 10158 10159 /* Select page 0 */ 10160 ret_val = em_swfw_sync_acquire(hw, swfw); 10161 if (ret_val) 10162 goto out; 10163 10164 hw->phy_addr = 1; 10165 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 10166 em_swfw_sync_release(hw, swfw); 10167 if (ret_val) 10168 goto out; 10169 10170 /* Workaround for link disconnects on a busy hub in half duplex */ 10171 ret_val = em_read_phy_reg(hw, 10172 PHY_REG(BM_PORT_CTRL_PAGE, 17), 10173 &phy_data); 10174 if (ret_val) 10175 goto release; 10176 ret_val = em_write_phy_reg(hw, 10177 PHY_REG(BM_PORT_CTRL_PAGE, 17), 10178 phy_data & 0x00FF); 10179 release: 10180 out: 10181 return ret_val; 10182 } 10183 10184 10185 /*************************************************************************** 10186 * Si workaround 10187 * 10188 * This function works around a Si bug where the link partner can get 10189 * a link up indication before the PHY does. If small packets are sent 10190 * by the link partner they can be placed in the packet buffer without 10191 * being properly accounted for by the PHY and will stall preventing 10192 * further packets from being received. The workaround is to clear the 10193 * packet buffer after the PHY detects link up. 10194 ***************************************************************************/ 10195 int32_t 10196 em_link_stall_workaround_hv(struct em_hw *hw) 10197 { 10198 int32_t ret_val = E1000_SUCCESS; 10199 uint16_t phy_data; 10200 10201 if (hw->phy_type != em_phy_82578) 10202 goto out; 10203 10204 /* Do not apply workaround if in PHY loopback bit 14 set */ 10205 em_read_phy_reg(hw, PHY_CTRL, &phy_data); 10206 if (phy_data & E1000_PHY_CTRL_LOOPBACK) 10207 goto out; 10208 10209 /* check if link is up and at 1Gbps */ 10210 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10211 if (ret_val) 10212 goto out; 10213 10214 phy_data &= BM_CS_STATUS_LINK_UP | 10215 BM_CS_STATUS_RESOLVED | 10216 BM_CS_STATUS_SPEED_MASK; 10217 10218 if (phy_data != (BM_CS_STATUS_LINK_UP | 10219 BM_CS_STATUS_RESOLVED | 10220 BM_CS_STATUS_SPEED_1000)) 10221 goto out; 10222 10223 msec_delay(200); 10224 10225 /* flush the packets in the fifo buffer */ 10226 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10227 HV_MUX_DATA_CTRL_GEN_TO_MAC | HV_MUX_DATA_CTRL_FORCE_SPEED); 10228 if (ret_val) 10229 goto out; 10230 10231 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL, 10232 HV_MUX_DATA_CTRL_GEN_TO_MAC); 10233 10234 out: 10235 return ret_val; 10236 } 10237 10238 /**************************************************************************** 10239 * K1 Si workaround 10240 * 10241 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 10242 * from a lower speed. This workaround disables K1 whenever link is at 1Gig. 10243 * If link is down, the function will restore the default K1 setting located 10244 * in the NVM. 10245 ****************************************************************************/ 10246 int32_t 10247 em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link) 10248 { 10249 int32_t ret_val; 10250 uint16_t phy_data; 10251 boolean_t k1_enable; 10252 10253 DEBUGFUNC("em_k1_gig_workaround_hv"); 10254 10255 if (hw->mac_type != em_pchlan) 10256 return E1000_SUCCESS; 10257 10258 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG, 1, &phy_data); 10259 if (ret_val) 10260 return ret_val; 10261 10262 k1_enable = phy_data & E1000_NVM_K1_ENABLE ? TRUE : FALSE; 10263 10264 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 10265 if (link) { 10266 if (hw->phy_type == em_phy_82578) { 10267 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, 10268 &phy_data); 10269 if (ret_val) 10270 return ret_val; 10271 10272 phy_data &= BM_CS_STATUS_LINK_UP | 10273 BM_CS_STATUS_RESOLVED | 10274 BM_CS_STATUS_SPEED_MASK; 10275 10276 if (phy_data == (BM_CS_STATUS_LINK_UP | 10277 BM_CS_STATUS_RESOLVED | 10278 BM_CS_STATUS_SPEED_1000)) 10279 k1_enable = FALSE; 10280 } 10281 10282 if (hw->phy_type == em_phy_82577) { 10283 ret_val = em_read_phy_reg(hw, HV_M_STATUS, 10284 &phy_data); 10285 if (ret_val) 10286 return ret_val; 10287 10288 phy_data &= HV_M_STATUS_LINK_UP | 10289 HV_M_STATUS_AUTONEG_COMPLETE | 10290 HV_M_STATUS_SPEED_MASK; 10291 10292 if (phy_data == (HV_M_STATUS_LINK_UP | 10293 HV_M_STATUS_AUTONEG_COMPLETE | 10294 HV_M_STATUS_SPEED_1000)) 10295 k1_enable = FALSE; 10296 } 10297 10298 /* Link stall fix for link up */ 10299 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10300 0x0100); 10301 if (ret_val) 10302 return ret_val; 10303 10304 } else { 10305 /* Link stall fix for link down */ 10306 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19), 10307 0x4100); 10308 if (ret_val) 10309 return ret_val; 10310 } 10311 10312 ret_val = em_configure_k1_ich8lan(hw, k1_enable); 10313 10314 return ret_val; 10315 } 10316 10317 /* Workaround to set the K1 beacon duration for 82579 parts */ 10318 int32_t 10319 em_k1_workaround_lv(struct em_hw *hw) 10320 { 10321 int32_t ret_val; 10322 uint16_t phy_data; 10323 uint32_t mac_reg; 10324 10325 ret_val = em_read_phy_reg(hw, BM_CS_STATUS, &phy_data); 10326 if (ret_val) 10327 return ret_val; 10328 10329 if ((phy_data & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 10330 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 10331 mac_reg = E1000_READ_REG(hw, FEXTNVM4); 10332 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 10333 10334 if (phy_data & HV_M_STATUS_SPEED_1000) 10335 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 10336 else 10337 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 10338 10339 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); 10340 } 10341 10342 return E1000_SUCCESS; 10343 } 10344 10345 /** 10346 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 10347 * 10348 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 10349 * preventing further DMA write requests. Workaround the issue by disabling 10350 * the de-assertion of the clock request when in 1Gbps mode. 10351 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 10352 * speeds in order to avoid Tx hangs. 10353 **/ 10354 int32_t 10355 em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link) 10356 { 10357 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6); 10358 uint32_t status = E1000_READ_REG(hw, STATUS); 10359 int32_t ret_val = E1000_SUCCESS; 10360 uint16_t reg; 10361 10362 if (link && (status & E1000_STATUS_SPEED_1000)) { 10363 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10364 ®); 10365 if (ret_val) 10366 return ret_val; 10367 10368 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10369 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE); 10370 if (ret_val) 10371 return ret_val; 10372 10373 usec_delay(10); 10374 10375 E1000_WRITE_REG(hw, FEXTNVM6, 10376 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 10377 10378 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10379 reg); 10380 } else { 10381 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 10382 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 10383 10384 if (!link || ((status & E1000_STATUS_SPEED_100) && 10385 (status & E1000_STATUS_FD))) 10386 goto update_fextnvm6; 10387 10388 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL, ®); 10389 if (ret_val) 10390 return ret_val; 10391 10392 /* Clear link status transmit timeout */ 10393 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 10394 10395 if (status & E1000_STATUS_SPEED_100) { 10396 /* Set inband Tx timeout to 5x10us for 100Half */ 10397 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 10398 10399 /* Do not extend the K1 entry latency for 100Half */ 10400 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 10401 } else { 10402 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 10403 reg |= 50 << 10404 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 10405 10406 /* Extend the K1 entry latency for 10 Mbps */ 10407 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 10408 } 10409 10410 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL, reg); 10411 if (ret_val) 10412 return ret_val; 10413 10414 update_fextnvm6: 10415 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6); 10416 } 10417 10418 return ret_val; 10419 10420 } 10421 10422 10423 /*************************************************************************** 10424 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 10425 * @hw: pointer to the HW structure 10426 * @gate: boolean set to TRUE to gate, FALSE to ungate 10427 * 10428 * Gate/ungate the automatic PHY configuration via hardware; perform 10429 * the configuration via software instead. 10430 ***************************************************************************/ 10431 void 10432 em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate) 10433 { 10434 uint32_t extcnf_ctrl; 10435 10436 DEBUGFUNC("em_gate_hw_phy_config_ich8lan"); 10437 10438 if (hw->mac_type != em_pch2lan) 10439 return; 10440 10441 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); 10442 10443 if (gate) 10444 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 10445 else 10446 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 10447 10448 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); 10449 } 10450 10451 /*************************************************************************** 10452 * Configure K1 power state 10453 * 10454 * Configure the K1 power state based on the provided parameter. 10455 * Assumes semaphore already acquired. 10456 * 10457 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 10458 ***************************************************************************/ 10459 int32_t 10460 em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable) 10461 { 10462 int32_t ret_val = E1000_SUCCESS; 10463 uint32_t ctrl_reg = 0; 10464 uint32_t ctrl_ext = 0; 10465 uint32_t reg = 0; 10466 uint16_t kmrn_reg = 0; 10467 10468 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10469 &kmrn_reg); 10470 if (ret_val) 10471 goto out; 10472 10473 if (k1_enable) 10474 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 10475 else 10476 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 10477 10478 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 10479 kmrn_reg); 10480 if (ret_val) 10481 goto out; 10482 10483 usec_delay(20); 10484 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 10485 ctrl_reg = E1000_READ_REG(hw, CTRL); 10486 10487 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 10488 reg |= E1000_CTRL_FRCSPD; 10489 E1000_WRITE_REG(hw, CTRL, reg); 10490 10491 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 10492 usec_delay(20); 10493 E1000_WRITE_REG(hw, CTRL, ctrl_reg); 10494 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 10495 usec_delay(20); 10496 10497 out: 10498 return ret_val; 10499 } 10500 10501 /*************************************************************************** 10502 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 10503 * done after every PHY reset. 10504 ***************************************************************************/ 10505 int32_t 10506 em_lv_phy_workarounds_ich8lan(struct em_hw *hw) 10507 { 10508 int32_t ret_val = E1000_SUCCESS; 10509 uint16_t swfw; 10510 10511 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan"); 10512 10513 if (hw->mac_type != em_pch2lan) 10514 goto out; 10515 10516 /* Set MDIO slow mode before any other MDIO access */ 10517 ret_val = em_set_mdio_slow_mode_hv(hw); 10518 10519 swfw = E1000_SWFW_PHY0_SM; 10520 ret_val = em_swfw_sync_acquire(hw, swfw); 10521 if (ret_val) 10522 goto out; 10523 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 10524 I82579_MSE_THRESHOLD); 10525 if (ret_val) 10526 goto release; 10527 /* set MSE higher to enable link to stay up when noise is high */ 10528 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 10529 0x0034); 10530 if (ret_val) 10531 goto release; 10532 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR, 10533 I82579_MSE_LINK_DOWN); 10534 if (ret_val) 10535 goto release; 10536 /* drop link after 5 times MSE threshold was reached */ 10537 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA, 10538 0x0005); 10539 release: 10540 em_swfw_sync_release(hw, swfw); 10541 10542 out: 10543 return ret_val; 10544 } 10545 10546 int32_t 10547 em_set_eee_i350(struct em_hw *hw) 10548 { 10549 int32_t ret_val = E1000_SUCCESS; 10550 uint32_t ipcnfg, eeer; 10551 10552 if ((hw->mac_type < em_i350) || 10553 (hw->media_type != em_media_type_copper)) 10554 goto out; 10555 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG); 10556 eeer = EM_READ_REG(hw, E1000_EEER); 10557 10558 if (hw->eee_enable) { 10559 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 10560 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 10561 E1000_EEER_LPI_FC); 10562 } else { 10563 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 10564 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 10565 E1000_EEER_LPI_FC); 10566 } 10567 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 10568 EM_WRITE_REG(hw, E1000_EEER, eeer); 10569 EM_READ_REG(hw, E1000_IPCNFG); 10570 EM_READ_REG(hw, E1000_EEER); 10571 out: 10572 return ret_val; 10573 } 10574 10575 /*************************************************************************** 10576 * em_set_eee_pchlan - Enable/disable EEE support 10577 * @hw: pointer to the HW structure 10578 * 10579 * Enable/disable EEE based on setting in dev_spec structure. The bits in 10580 * the LPI Control register will remain set only if/when link is up. 10581 ***************************************************************************/ 10582 int32_t 10583 em_set_eee_pchlan(struct em_hw *hw) 10584 { 10585 int32_t ret_val = E1000_SUCCESS; 10586 uint16_t phy_reg; 10587 10588 DEBUGFUNC("em_set_eee_pchlan"); 10589 10590 if (hw->phy_type != em_phy_82579 && 10591 hw->phy_type != em_phy_i217) 10592 goto out; 10593 10594 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL, &phy_reg); 10595 if (ret_val) 10596 goto out; 10597 10598 if (hw->eee_enable) 10599 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK; 10600 else 10601 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK; 10602 10603 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg); 10604 out: 10605 return ret_val; 10606 } 10607 10608