1 /* $OpenBSD: if_iwn.c,v 1.242 2020/10/11 07:05:28 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network 21 * adapters. 22 */ 23 24 #include "bpfilter.h" 25 26 #include <sys/param.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/rwlock.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/conf.h> 35 #include <sys/device.h> 36 #include <sys/task.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #if NBPFILTER > 0 47 #include <net/bpf.h> 48 #endif 49 #include <net/if.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 53 #include <netinet/in.h> 54 #include <netinet/if_ether.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_amrr.h> 58 #include <net80211/ieee80211_mira.h> 59 #include <net80211/ieee80211_radiotap.h> 60 #include <net80211/ieee80211_priv.h> /* for SEQ_LT */ 61 #undef DPRINTF /* defined in ieee80211_priv.h */ 62 63 #include <dev/pci/if_iwnreg.h> 64 #include <dev/pci/if_iwnvar.h> 65 66 static const struct pci_matchid iwn_devices[] = { 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_4965_1 }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_4965_2 }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5100_1 }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5100_2 }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5150_1 }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5150_2 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5300_1 }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5300_2 }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5350_1 }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_5350_2 }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1000_1 }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1000_2 }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6300_1 }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6300_2 }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6200_1 }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6200_2 }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6050_1 }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6050_2 }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6005_1 }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6005_2 }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6030_1 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6030_2 }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1030_1 }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_1030_2 }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_100_1 }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_100_2 }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_130_1 }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_130_2 }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6235_1 }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_6235_2 }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2230_1 }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2230_2 }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2200_1 }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_2200_2 }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_135_1 }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_135_2 }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_105_1 }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_WL_105_2 }, 105 }; 106 107 int iwn_match(struct device *, void *, void *); 108 void iwn_attach(struct device *, struct device *, void *); 109 int iwn4965_attach(struct iwn_softc *, pci_product_id_t); 110 int iwn5000_attach(struct iwn_softc *, pci_product_id_t); 111 #if NBPFILTER > 0 112 void iwn_radiotap_attach(struct iwn_softc *); 113 #endif 114 int iwn_detach(struct device *, int); 115 int iwn_activate(struct device *, int); 116 void iwn_wakeup(struct iwn_softc *); 117 void iwn_init_task(void *); 118 int iwn_nic_lock(struct iwn_softc *); 119 int iwn_eeprom_lock(struct iwn_softc *); 120 int iwn_init_otprom(struct iwn_softc *); 121 int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int); 122 int iwn_dma_contig_alloc(bus_dma_tag_t, struct iwn_dma_info *, 123 void **, bus_size_t, bus_size_t); 124 void iwn_dma_contig_free(struct iwn_dma_info *); 125 int iwn_alloc_sched(struct iwn_softc *); 126 void iwn_free_sched(struct iwn_softc *); 127 int iwn_alloc_kw(struct iwn_softc *); 128 void iwn_free_kw(struct iwn_softc *); 129 int iwn_alloc_ict(struct iwn_softc *); 130 void iwn_free_ict(struct iwn_softc *); 131 int iwn_alloc_fwmem(struct iwn_softc *); 132 void iwn_free_fwmem(struct iwn_softc *); 133 int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 134 void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 135 void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *); 136 int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *, 137 int); 138 void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 139 void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *); 140 void iwn5000_ict_reset(struct iwn_softc *); 141 int iwn_read_eeprom(struct iwn_softc *); 142 void iwn4965_read_eeprom(struct iwn_softc *); 143 void iwn4965_print_power_group(struct iwn_softc *, int); 144 void iwn5000_read_eeprom(struct iwn_softc *); 145 void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t); 146 void iwn_read_eeprom_enhinfo(struct iwn_softc *); 147 struct ieee80211_node *iwn_node_alloc(struct ieee80211com *); 148 void iwn_newassoc(struct ieee80211com *, struct ieee80211_node *, 149 int); 150 int iwn_media_change(struct ifnet *); 151 int iwn_newstate(struct ieee80211com *, enum ieee80211_state, int); 152 void iwn_iter_func(void *, struct ieee80211_node *); 153 void iwn_calib_timeout(void *); 154 int iwn_ccmp_decap(struct iwn_softc *, struct mbuf *, 155 struct ieee80211_node *); 156 void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *, 157 struct iwn_rx_data *); 158 void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *, 159 struct iwn_rx_data *, struct mbuf_list *); 160 void iwn_mira_choose(struct iwn_softc *, struct ieee80211_node *); 161 void iwn_ampdu_rate_control(struct iwn_softc *, struct ieee80211_node *, 162 struct iwn_tx_ring *, int, uint16_t, uint16_t); 163 void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *, 164 struct iwn_rx_data *); 165 void iwn5000_rx_calib_results(struct iwn_softc *, 166 struct iwn_rx_desc *, struct iwn_rx_data *); 167 void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *, 168 struct iwn_rx_data *); 169 void iwn_ampdu_txq_advance(struct iwn_softc *, struct iwn_tx_ring *, 170 int, int); 171 void iwn_ampdu_tx_done(struct iwn_softc *, struct iwn_tx_ring *, 172 struct iwn_rx_desc *, uint16_t, uint8_t, uint8_t, uint8_t, 173 int, uint32_t, struct iwn_txagg_status *); 174 void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 175 struct iwn_rx_data *); 176 void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 177 struct iwn_rx_data *); 178 void iwn_tx_done_free_txdata(struct iwn_softc *, 179 struct iwn_tx_data *); 180 void iwn_clear_oactive(struct iwn_softc *, struct iwn_tx_ring *); 181 void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, 182 uint8_t, uint8_t, int, int, uint16_t); 183 void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *); 184 void iwn_notif_intr(struct iwn_softc *); 185 void iwn_wakeup_intr(struct iwn_softc *); 186 void iwn_fatal_intr(struct iwn_softc *); 187 int iwn_intr(void *); 188 void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t, 189 uint16_t); 190 void iwn4965_reset_sched(struct iwn_softc *, int, int); 191 void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t, 192 uint16_t); 193 void iwn5000_reset_sched(struct iwn_softc *, int, int); 194 int iwn_tx(struct iwn_softc *, struct mbuf *, 195 struct ieee80211_node *); 196 int iwn_rval2ridx(int); 197 void iwn_start(struct ifnet *); 198 void iwn_watchdog(struct ifnet *); 199 int iwn_ioctl(struct ifnet *, u_long, caddr_t); 200 int iwn_cmd(struct iwn_softc *, int, const void *, int, int); 201 int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *, 202 int); 203 int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *, 204 int); 205 int iwn_set_link_quality(struct iwn_softc *, 206 struct ieee80211_node *); 207 int iwn_add_broadcast_node(struct iwn_softc *, int, int); 208 void iwn_updateedca(struct ieee80211com *); 209 void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t); 210 int iwn_set_critical_temp(struct iwn_softc *); 211 int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *); 212 void iwn4965_power_calibration(struct iwn_softc *, int); 213 int iwn4965_set_txpower(struct iwn_softc *, int); 214 int iwn5000_set_txpower(struct iwn_softc *, int); 215 int iwn4965_get_rssi(const struct iwn_rx_stat *); 216 int iwn5000_get_rssi(const struct iwn_rx_stat *); 217 int iwn_get_noise(const struct iwn_rx_general_stats *); 218 int iwn4965_get_temperature(struct iwn_softc *); 219 int iwn5000_get_temperature(struct iwn_softc *); 220 int iwn_init_sensitivity(struct iwn_softc *); 221 void iwn_collect_noise(struct iwn_softc *, 222 const struct iwn_rx_general_stats *); 223 int iwn4965_init_gains(struct iwn_softc *); 224 int iwn5000_init_gains(struct iwn_softc *); 225 int iwn4965_set_gains(struct iwn_softc *); 226 int iwn5000_set_gains(struct iwn_softc *); 227 void iwn_tune_sensitivity(struct iwn_softc *, 228 const struct iwn_rx_stats *); 229 int iwn_send_sensitivity(struct iwn_softc *); 230 int iwn_set_pslevel(struct iwn_softc *, int, int, int); 231 int iwn_send_temperature_offset(struct iwn_softc *); 232 int iwn_send_btcoex(struct iwn_softc *); 233 int iwn_send_advanced_btcoex(struct iwn_softc *); 234 int iwn5000_runtime_calib(struct iwn_softc *); 235 int iwn_config(struct iwn_softc *); 236 uint16_t iwn_get_active_dwell_time(struct iwn_softc *, uint16_t, uint8_t); 237 uint16_t iwn_limit_dwell(struct iwn_softc *, uint16_t); 238 uint16_t iwn_get_passive_dwell_time(struct iwn_softc *, uint16_t); 239 int iwn_scan(struct iwn_softc *, uint16_t, int); 240 void iwn_scan_abort(struct iwn_softc *); 241 int iwn_bgscan(struct ieee80211com *); 242 int iwn_auth(struct iwn_softc *, int); 243 int iwn_run(struct iwn_softc *); 244 int iwn_set_key(struct ieee80211com *, struct ieee80211_node *, 245 struct ieee80211_key *); 246 void iwn_delete_key(struct ieee80211com *, struct ieee80211_node *, 247 struct ieee80211_key *); 248 void iwn_update_htprot(struct ieee80211com *, 249 struct ieee80211_node *); 250 int iwn_ampdu_rx_start(struct ieee80211com *, 251 struct ieee80211_node *, uint8_t); 252 void iwn_ampdu_rx_stop(struct ieee80211com *, 253 struct ieee80211_node *, uint8_t); 254 int iwn_ampdu_tx_start(struct ieee80211com *, 255 struct ieee80211_node *, uint8_t); 256 void iwn_ampdu_tx_stop(struct ieee80211com *, 257 struct ieee80211_node *, uint8_t); 258 void iwn4965_ampdu_tx_start(struct iwn_softc *, 259 struct ieee80211_node *, uint8_t, uint16_t); 260 void iwn4965_ampdu_tx_stop(struct iwn_softc *, 261 uint8_t, uint16_t); 262 void iwn5000_ampdu_tx_start(struct iwn_softc *, 263 struct ieee80211_node *, uint8_t, uint16_t); 264 void iwn5000_ampdu_tx_stop(struct iwn_softc *, 265 uint8_t, uint16_t); 266 int iwn5000_query_calibration(struct iwn_softc *); 267 int iwn5000_send_calibration(struct iwn_softc *); 268 int iwn5000_send_wimax_coex(struct iwn_softc *); 269 int iwn5000_crystal_calib(struct iwn_softc *); 270 int iwn6000_temp_offset_calib(struct iwn_softc *); 271 int iwn2000_temp_offset_calib(struct iwn_softc *); 272 int iwn4965_post_alive(struct iwn_softc *); 273 int iwn5000_post_alive(struct iwn_softc *); 274 int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *, 275 int); 276 int iwn4965_load_firmware(struct iwn_softc *); 277 int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t, 278 const uint8_t *, int); 279 int iwn5000_load_firmware(struct iwn_softc *); 280 int iwn_read_firmware_leg(struct iwn_softc *, 281 struct iwn_fw_info *); 282 int iwn_read_firmware_tlv(struct iwn_softc *, 283 struct iwn_fw_info *, uint16_t); 284 int iwn_read_firmware(struct iwn_softc *); 285 int iwn_clock_wait(struct iwn_softc *); 286 int iwn_apm_init(struct iwn_softc *); 287 void iwn_apm_stop_master(struct iwn_softc *); 288 void iwn_apm_stop(struct iwn_softc *); 289 int iwn4965_nic_config(struct iwn_softc *); 290 int iwn5000_nic_config(struct iwn_softc *); 291 int iwn_hw_prepare(struct iwn_softc *); 292 int iwn_hw_init(struct iwn_softc *); 293 void iwn_hw_stop(struct iwn_softc *); 294 int iwn_init(struct ifnet *); 295 void iwn_stop(struct ifnet *); 296 297 #ifdef IWN_DEBUG 298 #define DPRINTF(x) do { if (iwn_debug > 0) printf x; } while (0) 299 #define DPRINTFN(n, x) do { if (iwn_debug >= (n)) printf x; } while (0) 300 int iwn_debug = 1; 301 #else 302 #define DPRINTF(x) 303 #define DPRINTFN(n, x) 304 #endif 305 306 struct cfdriver iwn_cd = { 307 NULL, "iwn", DV_IFNET 308 }; 309 310 struct cfattach iwn_ca = { 311 sizeof (struct iwn_softc), iwn_match, iwn_attach, iwn_detach, 312 iwn_activate 313 }; 314 315 int 316 iwn_match(struct device *parent, void *match, void *aux) 317 { 318 return pci_matchbyid((struct pci_attach_args *)aux, iwn_devices, 319 nitems(iwn_devices)); 320 } 321 322 void 323 iwn_attach(struct device *parent, struct device *self, void *aux) 324 { 325 struct iwn_softc *sc = (struct iwn_softc *)self; 326 struct ieee80211com *ic = &sc->sc_ic; 327 struct ifnet *ifp = &ic->ic_if; 328 struct pci_attach_args *pa = aux; 329 const char *intrstr; 330 pci_intr_handle_t ih; 331 pcireg_t memtype, reg; 332 int i, error; 333 334 sc->sc_pct = pa->pa_pc; 335 sc->sc_pcitag = pa->pa_tag; 336 sc->sc_dmat = pa->pa_dmat; 337 338 /* 339 * Get the offset of the PCI Express Capability Structure in PCI 340 * Configuration Space. 341 */ 342 error = pci_get_capability(sc->sc_pct, sc->sc_pcitag, 343 PCI_CAP_PCIEXPRESS, &sc->sc_cap_off, NULL); 344 if (error == 0) { 345 printf(": PCIe capability structure not found!\n"); 346 return; 347 } 348 349 /* Clear device-specific "PCI retry timeout" register (41h). */ 350 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 351 if (reg & 0xff00) 352 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 353 354 /* Hardware bug workaround. */ 355 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, PCI_COMMAND_STATUS_REG); 356 if (reg & PCI_COMMAND_INTERRUPT_DISABLE) { 357 DPRINTF(("PCIe INTx Disable set\n")); 358 reg &= ~PCI_COMMAND_INTERRUPT_DISABLE; 359 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 360 PCI_COMMAND_STATUS_REG, reg); 361 } 362 363 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IWN_PCI_BAR0); 364 error = pci_mapreg_map(pa, IWN_PCI_BAR0, memtype, 0, &sc->sc_st, 365 &sc->sc_sh, NULL, &sc->sc_sz, 0); 366 if (error != 0) { 367 printf(": can't map mem space\n"); 368 return; 369 } 370 371 /* Install interrupt handler. */ 372 if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { 373 printf(": can't map interrupt\n"); 374 return; 375 } 376 intrstr = pci_intr_string(sc->sc_pct, ih); 377 sc->sc_ih = pci_intr_establish(sc->sc_pct, ih, IPL_NET, iwn_intr, sc, 378 sc->sc_dev.dv_xname); 379 if (sc->sc_ih == NULL) { 380 printf(": can't establish interrupt"); 381 if (intrstr != NULL) 382 printf(" at %s", intrstr); 383 printf("\n"); 384 return; 385 } 386 printf(": %s", intrstr); 387 388 /* Read hardware revision and attach. */ 389 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0x1f; 390 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 391 error = iwn4965_attach(sc, PCI_PRODUCT(pa->pa_id)); 392 else 393 error = iwn5000_attach(sc, PCI_PRODUCT(pa->pa_id)); 394 if (error != 0) { 395 printf(": could not attach device\n"); 396 return; 397 } 398 399 if ((error = iwn_hw_prepare(sc)) != 0) { 400 printf(": hardware not ready\n"); 401 return; 402 } 403 404 /* Read MAC address, channels, etc from EEPROM. */ 405 if ((error = iwn_read_eeprom(sc)) != 0) { 406 printf(": could not read EEPROM\n"); 407 return; 408 } 409 410 /* Allocate DMA memory for firmware transfers. */ 411 if ((error = iwn_alloc_fwmem(sc)) != 0) { 412 printf(": could not allocate memory for firmware\n"); 413 return; 414 } 415 416 /* Allocate "Keep Warm" page. */ 417 if ((error = iwn_alloc_kw(sc)) != 0) { 418 printf(": could not allocate keep warm page\n"); 419 goto fail1; 420 } 421 422 /* Allocate ICT table for 5000 Series. */ 423 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 424 (error = iwn_alloc_ict(sc)) != 0) { 425 printf(": could not allocate ICT table\n"); 426 goto fail2; 427 } 428 429 /* Allocate TX scheduler "rings". */ 430 if ((error = iwn_alloc_sched(sc)) != 0) { 431 printf(": could not allocate TX scheduler rings\n"); 432 goto fail3; 433 } 434 435 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */ 436 for (i = 0; i < sc->ntxqs; i++) { 437 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) { 438 printf(": could not allocate TX ring %d\n", i); 439 goto fail4; 440 } 441 } 442 443 /* Allocate RX ring. */ 444 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) { 445 printf(": could not allocate RX ring\n"); 446 goto fail4; 447 } 448 449 /* Clear pending interrupts. */ 450 IWN_WRITE(sc, IWN_INT, 0xffffffff); 451 452 /* Count the number of available chains. */ 453 sc->ntxchains = 454 ((sc->txchainmask >> 2) & 1) + 455 ((sc->txchainmask >> 1) & 1) + 456 ((sc->txchainmask >> 0) & 1); 457 sc->nrxchains = 458 ((sc->rxchainmask >> 2) & 1) + 459 ((sc->rxchainmask >> 1) & 1) + 460 ((sc->rxchainmask >> 0) & 1); 461 printf(", MIMO %dT%dR, %.4s, address %s\n", sc->ntxchains, 462 sc->nrxchains, sc->eeprom_domain, ether_sprintf(ic->ic_myaddr)); 463 464 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 465 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 466 ic->ic_state = IEEE80211_S_INIT; 467 468 /* Set device capabilities. */ 469 ic->ic_caps = 470 IEEE80211_C_WEP | /* WEP */ 471 IEEE80211_C_RSN | /* WPA/RSN */ 472 IEEE80211_C_SCANALL | /* device scans all channels at once */ 473 IEEE80211_C_SCANALLBAND | /* driver scans all bands at once */ 474 IEEE80211_C_MONITOR | /* monitor mode supported */ 475 IEEE80211_C_SHSLOT | /* short slot time supported */ 476 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 477 IEEE80211_C_PMGT; /* power saving supported */ 478 479 /* No optional HT features supported for now, */ 480 ic->ic_htcaps = 0; 481 ic->ic_htxcaps = 0; 482 ic->ic_txbfcaps = 0; 483 ic->ic_aselcaps = 0; 484 ic->ic_ampdu_params = (IEEE80211_AMPDU_PARAM_SS_4 | 0x3 /* 64k */); 485 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 486 ic->ic_caps |= (IEEE80211_C_QOS | IEEE80211_C_TX_AMPDU); 487 /* Set HT capabilities. */ 488 ic->ic_htcaps = IEEE80211_HTCAP_SGI20; 489 #ifdef notyet 490 ic->ic_htcaps |= 491 #if IWN_RBUF_SIZE == 8192 492 IEEE80211_HTCAP_AMSDU7935 | 493 #endif 494 IEEE80211_HTCAP_CBW20_40 | 495 IEEE80211_HTCAP_SGI40; 496 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 497 ic->ic_htcaps |= IEEE80211_HTCAP_GF; 498 if (sc->hw_type == IWN_HW_REV_TYPE_6050) 499 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN; 500 else 501 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS; 502 #endif /* notyet */ 503 } 504 505 /* Set supported legacy rates. */ 506 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 507 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 508 if (sc->sc_flags & IWN_FLAG_HAS_5GHZ) { 509 ic->ic_sup_rates[IEEE80211_MODE_11A] = 510 ieee80211_std_rateset_11a; 511 } 512 if (sc->sc_flags & IWN_FLAG_HAS_11N) { 513 /* Set supported HT rates. */ 514 ic->ic_sup_mcs[0] = 0xff; /* MCS 0-7 */ 515 #ifdef notyet 516 if (sc->nrxchains > 1) 517 ic->ic_sup_mcs[1] = 0xff; /* MCS 8-15 */ 518 if (sc->nrxchains > 2) 519 ic->ic_sup_mcs[2] = 0xff; /* MCS 16-23 */ 520 #endif 521 } 522 523 /* IBSS channel undefined for now. */ 524 ic->ic_ibss_chan = &ic->ic_channels[0]; 525 526 ifp->if_softc = sc; 527 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 528 ifp->if_ioctl = iwn_ioctl; 529 ifp->if_start = iwn_start; 530 ifp->if_watchdog = iwn_watchdog; 531 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 532 533 if_attach(ifp); 534 ieee80211_ifattach(ifp); 535 ic->ic_node_alloc = iwn_node_alloc; 536 ic->ic_bgscan_start = iwn_bgscan; 537 ic->ic_newassoc = iwn_newassoc; 538 ic->ic_updateedca = iwn_updateedca; 539 ic->ic_set_key = iwn_set_key; 540 ic->ic_delete_key = iwn_delete_key; 541 ic->ic_update_htprot = iwn_update_htprot; 542 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start; 543 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop; 544 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start; 545 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop; 546 547 /* Override 802.11 state transition machine. */ 548 sc->sc_newstate = ic->ic_newstate; 549 ic->ic_newstate = iwn_newstate; 550 ieee80211_media_init(ifp, iwn_media_change, ieee80211_media_status); 551 552 sc->amrr.amrr_min_success_threshold = 1; 553 sc->amrr.amrr_max_success_threshold = 15; 554 555 #if NBPFILTER > 0 556 iwn_radiotap_attach(sc); 557 #endif 558 timeout_set(&sc->calib_to, iwn_calib_timeout, sc); 559 rw_init(&sc->sc_rwlock, "iwnlock"); 560 task_set(&sc->init_task, iwn_init_task, sc); 561 return; 562 563 /* Free allocated memory if something failed during attachment. */ 564 fail4: while (--i >= 0) 565 iwn_free_tx_ring(sc, &sc->txq[i]); 566 iwn_free_sched(sc); 567 fail3: if (sc->ict != NULL) 568 iwn_free_ict(sc); 569 fail2: iwn_free_kw(sc); 570 fail1: iwn_free_fwmem(sc); 571 } 572 573 int 574 iwn4965_attach(struct iwn_softc *sc, pci_product_id_t pid) 575 { 576 struct iwn_ops *ops = &sc->ops; 577 578 ops->load_firmware = iwn4965_load_firmware; 579 ops->read_eeprom = iwn4965_read_eeprom; 580 ops->post_alive = iwn4965_post_alive; 581 ops->nic_config = iwn4965_nic_config; 582 ops->reset_sched = iwn4965_reset_sched; 583 ops->update_sched = iwn4965_update_sched; 584 ops->get_temperature = iwn4965_get_temperature; 585 ops->get_rssi = iwn4965_get_rssi; 586 ops->set_txpower = iwn4965_set_txpower; 587 ops->init_gains = iwn4965_init_gains; 588 ops->set_gains = iwn4965_set_gains; 589 ops->add_node = iwn4965_add_node; 590 ops->tx_done = iwn4965_tx_done; 591 ops->ampdu_tx_start = iwn4965_ampdu_tx_start; 592 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop; 593 sc->ntxqs = IWN4965_NTXQUEUES; 594 sc->first_agg_txq = IWN4965_FIRST_AGG_TXQUEUE; 595 sc->ndmachnls = IWN4965_NDMACHNLS; 596 sc->broadcast_id = IWN4965_ID_BROADCAST; 597 sc->rxonsz = IWN4965_RXONSZ; 598 sc->schedsz = IWN4965_SCHEDSZ; 599 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ; 600 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ; 601 sc->fwsz = IWN4965_FWSZ; 602 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT; 603 sc->limits = &iwn4965_sensitivity_limits; 604 sc->fwname = "iwn-4965"; 605 /* Override chains masks, ROM is known to be broken. */ 606 sc->txchainmask = IWN_ANT_AB; 607 sc->rxchainmask = IWN_ANT_ABC; 608 609 return 0; 610 } 611 612 int 613 iwn5000_attach(struct iwn_softc *sc, pci_product_id_t pid) 614 { 615 struct iwn_ops *ops = &sc->ops; 616 617 ops->load_firmware = iwn5000_load_firmware; 618 ops->read_eeprom = iwn5000_read_eeprom; 619 ops->post_alive = iwn5000_post_alive; 620 ops->nic_config = iwn5000_nic_config; 621 ops->reset_sched = iwn5000_reset_sched; 622 ops->update_sched = iwn5000_update_sched; 623 ops->get_temperature = iwn5000_get_temperature; 624 ops->get_rssi = iwn5000_get_rssi; 625 ops->set_txpower = iwn5000_set_txpower; 626 ops->init_gains = iwn5000_init_gains; 627 ops->set_gains = iwn5000_set_gains; 628 ops->add_node = iwn5000_add_node; 629 ops->tx_done = iwn5000_tx_done; 630 ops->ampdu_tx_start = iwn5000_ampdu_tx_start; 631 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop; 632 sc->ntxqs = IWN5000_NTXQUEUES; 633 sc->first_agg_txq = IWN5000_FIRST_AGG_TXQUEUE; 634 sc->ndmachnls = IWN5000_NDMACHNLS; 635 sc->broadcast_id = IWN5000_ID_BROADCAST; 636 sc->rxonsz = IWN5000_RXONSZ; 637 sc->schedsz = IWN5000_SCHEDSZ; 638 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ; 639 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ; 640 sc->fwsz = IWN5000_FWSZ; 641 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT; 642 643 switch (sc->hw_type) { 644 case IWN_HW_REV_TYPE_5100: 645 sc->limits = &iwn5000_sensitivity_limits; 646 sc->fwname = "iwn-5000"; 647 /* Override chains masks, ROM is known to be broken. */ 648 sc->txchainmask = IWN_ANT_B; 649 sc->rxchainmask = IWN_ANT_AB; 650 break; 651 case IWN_HW_REV_TYPE_5150: 652 sc->limits = &iwn5150_sensitivity_limits; 653 sc->fwname = "iwn-5150"; 654 break; 655 case IWN_HW_REV_TYPE_5300: 656 case IWN_HW_REV_TYPE_5350: 657 sc->limits = &iwn5000_sensitivity_limits; 658 sc->fwname = "iwn-5000"; 659 break; 660 case IWN_HW_REV_TYPE_1000: 661 sc->limits = &iwn1000_sensitivity_limits; 662 sc->fwname = "iwn-1000"; 663 break; 664 case IWN_HW_REV_TYPE_6000: 665 sc->limits = &iwn6000_sensitivity_limits; 666 sc->fwname = "iwn-6000"; 667 if (pid == PCI_PRODUCT_INTEL_WL_6200_1 || 668 pid == PCI_PRODUCT_INTEL_WL_6200_2) { 669 sc->sc_flags |= IWN_FLAG_INTERNAL_PA; 670 /* Override chains masks, ROM is known to be broken. */ 671 sc->txchainmask = IWN_ANT_BC; 672 sc->rxchainmask = IWN_ANT_BC; 673 } 674 break; 675 case IWN_HW_REV_TYPE_6050: 676 sc->limits = &iwn6000_sensitivity_limits; 677 sc->fwname = "iwn-6050"; 678 break; 679 case IWN_HW_REV_TYPE_6005: 680 sc->limits = &iwn6000_sensitivity_limits; 681 if (pid != PCI_PRODUCT_INTEL_WL_6005_1 && 682 pid != PCI_PRODUCT_INTEL_WL_6005_2) { 683 sc->fwname = "iwn-6030"; 684 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 685 } else 686 sc->fwname = "iwn-6005"; 687 break; 688 case IWN_HW_REV_TYPE_2030: 689 sc->limits = &iwn2000_sensitivity_limits; 690 sc->fwname = "iwn-2030"; 691 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 692 break; 693 case IWN_HW_REV_TYPE_2000: 694 sc->limits = &iwn2000_sensitivity_limits; 695 sc->fwname = "iwn-2000"; 696 break; 697 case IWN_HW_REV_TYPE_135: 698 sc->limits = &iwn2000_sensitivity_limits; 699 sc->fwname = "iwn-135"; 700 sc->sc_flags |= IWN_FLAG_ADV_BT_COEX; 701 break; 702 case IWN_HW_REV_TYPE_105: 703 sc->limits = &iwn2000_sensitivity_limits; 704 sc->fwname = "iwn-105"; 705 break; 706 default: 707 printf(": adapter type %d not supported\n", sc->hw_type); 708 return ENOTSUP; 709 } 710 return 0; 711 } 712 713 #if NBPFILTER > 0 714 /* 715 * Attach the interface to 802.11 radiotap. 716 */ 717 void 718 iwn_radiotap_attach(struct iwn_softc *sc) 719 { 720 bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_if, DLT_IEEE802_11_RADIO, 721 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN); 722 723 sc->sc_rxtap_len = sizeof sc->sc_rxtapu; 724 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 725 sc->sc_rxtap.wr_ihdr.it_present = htole32(IWN_RX_RADIOTAP_PRESENT); 726 727 sc->sc_txtap_len = sizeof sc->sc_txtapu; 728 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 729 sc->sc_txtap.wt_ihdr.it_present = htole32(IWN_TX_RADIOTAP_PRESENT); 730 } 731 #endif 732 733 int 734 iwn_detach(struct device *self, int flags) 735 { 736 struct iwn_softc *sc = (struct iwn_softc *)self; 737 struct ifnet *ifp = &sc->sc_ic.ic_if; 738 int qid; 739 740 timeout_del(&sc->calib_to); 741 task_del(systq, &sc->init_task); 742 743 /* Uninstall interrupt handler. */ 744 if (sc->sc_ih != NULL) 745 pci_intr_disestablish(sc->sc_pct, sc->sc_ih); 746 747 /* Free DMA resources. */ 748 iwn_free_rx_ring(sc, &sc->rxq); 749 for (qid = 0; qid < sc->ntxqs; qid++) 750 iwn_free_tx_ring(sc, &sc->txq[qid]); 751 iwn_free_sched(sc); 752 iwn_free_kw(sc); 753 if (sc->ict != NULL) 754 iwn_free_ict(sc); 755 iwn_free_fwmem(sc); 756 757 bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz); 758 759 ieee80211_ifdetach(ifp); 760 if_detach(ifp); 761 762 return 0; 763 } 764 765 int 766 iwn_activate(struct device *self, int act) 767 { 768 struct iwn_softc *sc = (struct iwn_softc *)self; 769 struct ifnet *ifp = &sc->sc_ic.ic_if; 770 771 switch (act) { 772 case DVACT_SUSPEND: 773 if (ifp->if_flags & IFF_RUNNING) 774 iwn_stop(ifp); 775 break; 776 case DVACT_WAKEUP: 777 iwn_wakeup(sc); 778 break; 779 } 780 781 return 0; 782 } 783 784 void 785 iwn_wakeup(struct iwn_softc *sc) 786 { 787 pcireg_t reg; 788 789 /* Clear device-specific "PCI retry timeout" register (41h). */ 790 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 0x40); 791 if (reg & 0xff00) 792 pci_conf_write(sc->sc_pct, sc->sc_pcitag, 0x40, reg & ~0xff00); 793 iwn_init_task(sc); 794 } 795 796 void 797 iwn_init_task(void *arg1) 798 { 799 struct iwn_softc *sc = arg1; 800 struct ifnet *ifp = &sc->sc_ic.ic_if; 801 int s; 802 803 rw_enter_write(&sc->sc_rwlock); 804 s = splnet(); 805 806 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 807 iwn_init(ifp); 808 809 splx(s); 810 rw_exit_write(&sc->sc_rwlock); 811 } 812 813 int 814 iwn_nic_lock(struct iwn_softc *sc) 815 { 816 int ntries; 817 818 /* Request exclusive access to NIC. */ 819 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 820 821 /* Spin until we actually get the lock. */ 822 for (ntries = 0; ntries < 1000; ntries++) { 823 if ((IWN_READ(sc, IWN_GP_CNTRL) & 824 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) == 825 IWN_GP_CNTRL_MAC_ACCESS_ENA) 826 return 0; 827 DELAY(10); 828 } 829 return ETIMEDOUT; 830 } 831 832 static __inline void 833 iwn_nic_unlock(struct iwn_softc *sc) 834 { 835 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ); 836 } 837 838 static __inline uint32_t 839 iwn_prph_read(struct iwn_softc *sc, uint32_t addr) 840 { 841 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr); 842 IWN_BARRIER_READ_WRITE(sc); 843 return IWN_READ(sc, IWN_PRPH_RDATA); 844 } 845 846 static __inline void 847 iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 848 { 849 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr); 850 IWN_BARRIER_WRITE(sc); 851 IWN_WRITE(sc, IWN_PRPH_WDATA, data); 852 } 853 854 static __inline void 855 iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 856 { 857 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask); 858 } 859 860 static __inline void 861 iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask) 862 { 863 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask); 864 } 865 866 static __inline void 867 iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr, 868 const uint32_t *data, int count) 869 { 870 for (; count > 0; count--, data++, addr += 4) 871 iwn_prph_write(sc, addr, *data); 872 } 873 874 static __inline uint32_t 875 iwn_mem_read(struct iwn_softc *sc, uint32_t addr) 876 { 877 IWN_WRITE(sc, IWN_MEM_RADDR, addr); 878 IWN_BARRIER_READ_WRITE(sc); 879 return IWN_READ(sc, IWN_MEM_RDATA); 880 } 881 882 static __inline void 883 iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data) 884 { 885 IWN_WRITE(sc, IWN_MEM_WADDR, addr); 886 IWN_BARRIER_WRITE(sc); 887 IWN_WRITE(sc, IWN_MEM_WDATA, data); 888 } 889 890 static __inline void 891 iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data) 892 { 893 uint32_t tmp; 894 895 tmp = iwn_mem_read(sc, addr & ~3); 896 if (addr & 3) 897 tmp = (tmp & 0x0000ffff) | data << 16; 898 else 899 tmp = (tmp & 0xffff0000) | data; 900 iwn_mem_write(sc, addr & ~3, tmp); 901 } 902 903 #ifdef IWN_DEBUG 904 905 static __inline void 906 iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data, 907 int count) 908 { 909 for (; count > 0; count--, addr += 4) 910 *data++ = iwn_mem_read(sc, addr); 911 } 912 913 #endif 914 915 static __inline void 916 iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val, 917 int count) 918 { 919 for (; count > 0; count--, addr += 4) 920 iwn_mem_write(sc, addr, val); 921 } 922 923 int 924 iwn_eeprom_lock(struct iwn_softc *sc) 925 { 926 int i, ntries; 927 928 for (i = 0; i < 100; i++) { 929 /* Request exclusive access to EEPROM. */ 930 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 931 IWN_HW_IF_CONFIG_EEPROM_LOCKED); 932 933 /* Spin until we actually get the lock. */ 934 for (ntries = 0; ntries < 100; ntries++) { 935 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 936 IWN_HW_IF_CONFIG_EEPROM_LOCKED) 937 return 0; 938 DELAY(10); 939 } 940 } 941 return ETIMEDOUT; 942 } 943 944 static __inline void 945 iwn_eeprom_unlock(struct iwn_softc *sc) 946 { 947 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED); 948 } 949 950 /* 951 * Initialize access by host to One Time Programmable ROM. 952 * NB: This kind of ROM can be found on 1000 or 6000 Series only. 953 */ 954 int 955 iwn_init_otprom(struct iwn_softc *sc) 956 { 957 uint16_t prev, base, next; 958 int count, error; 959 960 /* Wait for clock stabilization before accessing prph. */ 961 if ((error = iwn_clock_wait(sc)) != 0) 962 return error; 963 964 if ((error = iwn_nic_lock(sc)) != 0) 965 return error; 966 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 967 DELAY(5); 968 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ); 969 iwn_nic_unlock(sc); 970 971 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */ 972 if (sc->hw_type != IWN_HW_REV_TYPE_1000) { 973 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT, 974 IWN_RESET_LINK_PWR_MGMT_DIS); 975 } 976 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER); 977 /* Clear ECC status. */ 978 IWN_SETBITS(sc, IWN_OTP_GP, 979 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS); 980 981 /* 982 * Find the block before last block (contains the EEPROM image) 983 * for HW without OTP shadow RAM. 984 */ 985 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 986 /* Switch to absolute addressing mode. */ 987 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS); 988 base = 0; 989 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) { 990 error = iwn_read_prom_data(sc, base, &next, 2); 991 if (error != 0) 992 return error; 993 if (next == 0) /* End of linked-list. */ 994 break; 995 prev = base; 996 base = letoh16(next); 997 } 998 if (count == 0 || count == IWN1000_OTP_NBLOCKS) 999 return EIO; 1000 /* Skip "next" word. */ 1001 sc->prom_base = prev + 1; 1002 } 1003 return 0; 1004 } 1005 1006 int 1007 iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count) 1008 { 1009 uint8_t *out = data; 1010 uint32_t val, tmp; 1011 int ntries; 1012 1013 addr += sc->prom_base; 1014 for (; count > 0; count -= 2, addr++) { 1015 IWN_WRITE(sc, IWN_EEPROM, addr << 2); 1016 for (ntries = 0; ntries < 10; ntries++) { 1017 val = IWN_READ(sc, IWN_EEPROM); 1018 if (val & IWN_EEPROM_READ_VALID) 1019 break; 1020 DELAY(5); 1021 } 1022 if (ntries == 10) { 1023 printf("%s: timeout reading ROM at 0x%x\n", 1024 sc->sc_dev.dv_xname, addr); 1025 return ETIMEDOUT; 1026 } 1027 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1028 /* OTPROM, check for ECC errors. */ 1029 tmp = IWN_READ(sc, IWN_OTP_GP); 1030 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) { 1031 printf("%s: OTPROM ECC error at 0x%x\n", 1032 sc->sc_dev.dv_xname, addr); 1033 return EIO; 1034 } 1035 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) { 1036 /* Correctable ECC error, clear bit. */ 1037 IWN_SETBITS(sc, IWN_OTP_GP, 1038 IWN_OTP_GP_ECC_CORR_STTS); 1039 } 1040 } 1041 *out++ = val >> 16; 1042 if (count > 1) 1043 *out++ = val >> 24; 1044 } 1045 return 0; 1046 } 1047 1048 int 1049 iwn_dma_contig_alloc(bus_dma_tag_t tag, struct iwn_dma_info *dma, void **kvap, 1050 bus_size_t size, bus_size_t alignment) 1051 { 1052 int nsegs, error; 1053 1054 dma->tag = tag; 1055 dma->size = size; 1056 1057 error = bus_dmamap_create(tag, size, 1, size, 0, BUS_DMA_NOWAIT, 1058 &dma->map); 1059 if (error != 0) 1060 goto fail; 1061 1062 error = bus_dmamem_alloc(tag, size, alignment, 0, &dma->seg, 1, &nsegs, 1063 BUS_DMA_NOWAIT | BUS_DMA_ZERO); 1064 if (error != 0) 1065 goto fail; 1066 1067 error = bus_dmamem_map(tag, &dma->seg, 1, size, &dma->vaddr, 1068 BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 1069 if (error != 0) 1070 goto fail; 1071 1072 error = bus_dmamap_load_raw(tag, dma->map, &dma->seg, 1, size, 1073 BUS_DMA_NOWAIT); 1074 if (error != 0) 1075 goto fail; 1076 1077 bus_dmamap_sync(tag, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 1078 1079 dma->paddr = dma->map->dm_segs[0].ds_addr; 1080 if (kvap != NULL) 1081 *kvap = dma->vaddr; 1082 1083 return 0; 1084 1085 fail: iwn_dma_contig_free(dma); 1086 return error; 1087 } 1088 1089 void 1090 iwn_dma_contig_free(struct iwn_dma_info *dma) 1091 { 1092 if (dma->map != NULL) { 1093 if (dma->vaddr != NULL) { 1094 bus_dmamap_sync(dma->tag, dma->map, 0, dma->size, 1095 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1096 bus_dmamap_unload(dma->tag, dma->map); 1097 bus_dmamem_unmap(dma->tag, dma->vaddr, dma->size); 1098 bus_dmamem_free(dma->tag, &dma->seg, 1); 1099 dma->vaddr = NULL; 1100 } 1101 bus_dmamap_destroy(dma->tag, dma->map); 1102 dma->map = NULL; 1103 } 1104 } 1105 1106 int 1107 iwn_alloc_sched(struct iwn_softc *sc) 1108 { 1109 /* TX scheduler rings must be aligned on a 1KB boundary. */ 1110 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->sched_dma, 1111 (void **)&sc->sched, sc->schedsz, 1024); 1112 } 1113 1114 void 1115 iwn_free_sched(struct iwn_softc *sc) 1116 { 1117 iwn_dma_contig_free(&sc->sched_dma); 1118 } 1119 1120 int 1121 iwn_alloc_kw(struct iwn_softc *sc) 1122 { 1123 /* "Keep Warm" page must be aligned on a 4KB boundary. */ 1124 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->kw_dma, NULL, 4096, 1125 4096); 1126 } 1127 1128 void 1129 iwn_free_kw(struct iwn_softc *sc) 1130 { 1131 iwn_dma_contig_free(&sc->kw_dma); 1132 } 1133 1134 int 1135 iwn_alloc_ict(struct iwn_softc *sc) 1136 { 1137 /* ICT table must be aligned on a 4KB boundary. */ 1138 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->ict_dma, 1139 (void **)&sc->ict, IWN_ICT_SIZE, 4096); 1140 } 1141 1142 void 1143 iwn_free_ict(struct iwn_softc *sc) 1144 { 1145 iwn_dma_contig_free(&sc->ict_dma); 1146 } 1147 1148 int 1149 iwn_alloc_fwmem(struct iwn_softc *sc) 1150 { 1151 /* Must be aligned on a 16-byte boundary. */ 1152 return iwn_dma_contig_alloc(sc->sc_dmat, &sc->fw_dma, NULL, 1153 sc->fwsz, 16); 1154 } 1155 1156 void 1157 iwn_free_fwmem(struct iwn_softc *sc) 1158 { 1159 iwn_dma_contig_free(&sc->fw_dma); 1160 } 1161 1162 int 1163 iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1164 { 1165 bus_size_t size; 1166 int i, error; 1167 1168 ring->cur = 0; 1169 1170 /* Allocate RX descriptors (256-byte aligned). */ 1171 size = IWN_RX_RING_COUNT * sizeof (uint32_t); 1172 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1173 (void **)&ring->desc, size, 256); 1174 if (error != 0) { 1175 printf("%s: could not allocate RX ring DMA memory\n", 1176 sc->sc_dev.dv_xname); 1177 goto fail; 1178 } 1179 1180 /* Allocate RX status area (16-byte aligned). */ 1181 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->stat_dma, 1182 (void **)&ring->stat, sizeof (struct iwn_rx_status), 16); 1183 if (error != 0) { 1184 printf("%s: could not allocate RX status DMA memory\n", 1185 sc->sc_dev.dv_xname); 1186 goto fail; 1187 } 1188 1189 /* 1190 * Allocate and map RX buffers. 1191 */ 1192 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1193 struct iwn_rx_data *data = &ring->data[i]; 1194 1195 error = bus_dmamap_create(sc->sc_dmat, IWN_RBUF_SIZE, 1, 1196 IWN_RBUF_SIZE, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1197 &data->map); 1198 if (error != 0) { 1199 printf("%s: could not create RX buf DMA map\n", 1200 sc->sc_dev.dv_xname); 1201 goto fail; 1202 } 1203 1204 data->m = MCLGETI(NULL, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 1205 if (data->m == NULL) { 1206 printf("%s: could not allocate RX mbuf\n", 1207 sc->sc_dev.dv_xname); 1208 error = ENOBUFS; 1209 goto fail; 1210 } 1211 1212 error = bus_dmamap_load(sc->sc_dmat, data->map, 1213 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 1214 BUS_DMA_NOWAIT | BUS_DMA_READ); 1215 if (error != 0) { 1216 printf("%s: can't map mbuf (error %d)\n", 1217 sc->sc_dev.dv_xname, error); 1218 goto fail; 1219 } 1220 1221 /* Set physical address of RX buffer (256-byte aligned). */ 1222 ring->desc[i] = htole32(data->map->dm_segs[0].ds_addr >> 8); 1223 } 1224 1225 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, size, 1226 BUS_DMASYNC_PREWRITE); 1227 1228 return 0; 1229 1230 fail: iwn_free_rx_ring(sc, ring); 1231 return error; 1232 } 1233 1234 void 1235 iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1236 { 1237 int ntries; 1238 1239 if (iwn_nic_lock(sc) == 0) { 1240 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 1241 for (ntries = 0; ntries < 1000; ntries++) { 1242 if (IWN_READ(sc, IWN_FH_RX_STATUS) & 1243 IWN_FH_RX_STATUS_IDLE) 1244 break; 1245 DELAY(10); 1246 } 1247 iwn_nic_unlock(sc); 1248 } 1249 ring->cur = 0; 1250 sc->last_rx_valid = 0; 1251 } 1252 1253 void 1254 iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring) 1255 { 1256 int i; 1257 1258 iwn_dma_contig_free(&ring->desc_dma); 1259 iwn_dma_contig_free(&ring->stat_dma); 1260 1261 for (i = 0; i < IWN_RX_RING_COUNT; i++) { 1262 struct iwn_rx_data *data = &ring->data[i]; 1263 1264 if (data->m != NULL) { 1265 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1266 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD); 1267 bus_dmamap_unload(sc->sc_dmat, data->map); 1268 m_freem(data->m); 1269 } 1270 if (data->map != NULL) 1271 bus_dmamap_destroy(sc->sc_dmat, data->map); 1272 } 1273 } 1274 1275 int 1276 iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid) 1277 { 1278 bus_addr_t paddr; 1279 bus_size_t size; 1280 int i, error; 1281 1282 ring->qid = qid; 1283 ring->queued = 0; 1284 ring->cur = 0; 1285 1286 /* Allocate TX descriptors (256-byte aligned). */ 1287 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc); 1288 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->desc_dma, 1289 (void **)&ring->desc, size, 256); 1290 if (error != 0) { 1291 printf("%s: could not allocate TX ring DMA memory\n", 1292 sc->sc_dev.dv_xname); 1293 goto fail; 1294 } 1295 1296 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd); 1297 error = iwn_dma_contig_alloc(sc->sc_dmat, &ring->cmd_dma, 1298 (void **)&ring->cmd, size, 4); 1299 if (error != 0) { 1300 printf("%s: could not allocate TX cmd DMA memory\n", 1301 sc->sc_dev.dv_xname); 1302 goto fail; 1303 } 1304 1305 paddr = ring->cmd_dma.paddr; 1306 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1307 struct iwn_tx_data *data = &ring->data[i]; 1308 1309 data->cmd_paddr = paddr; 1310 data->scratch_paddr = paddr + 12; 1311 paddr += sizeof (struct iwn_tx_cmd); 1312 1313 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1314 IWN_MAX_SCATTER - 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 1315 &data->map); 1316 if (error != 0) { 1317 printf("%s: could not create TX buf DMA map\n", 1318 sc->sc_dev.dv_xname); 1319 goto fail; 1320 } 1321 } 1322 return 0; 1323 1324 fail: iwn_free_tx_ring(sc, ring); 1325 return error; 1326 } 1327 1328 void 1329 iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1330 { 1331 int i; 1332 1333 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1334 struct iwn_tx_data *data = &ring->data[i]; 1335 1336 if (data->m != NULL) { 1337 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1338 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1339 bus_dmamap_unload(sc->sc_dmat, data->map); 1340 m_freem(data->m); 1341 data->m = NULL; 1342 } 1343 } 1344 /* Clear TX descriptors. */ 1345 memset(ring->desc, 0, ring->desc_dma.size); 1346 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 0, 1347 ring->desc_dma.size, BUS_DMASYNC_PREWRITE); 1348 sc->qfullmsk &= ~(1 << ring->qid); 1349 ring->queued = 0; 1350 ring->cur = 0; 1351 } 1352 1353 void 1354 iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring) 1355 { 1356 int i; 1357 1358 iwn_dma_contig_free(&ring->desc_dma); 1359 iwn_dma_contig_free(&ring->cmd_dma); 1360 1361 for (i = 0; i < IWN_TX_RING_COUNT; i++) { 1362 struct iwn_tx_data *data = &ring->data[i]; 1363 1364 if (data->m != NULL) { 1365 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 1366 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1367 bus_dmamap_unload(sc->sc_dmat, data->map); 1368 m_freem(data->m); 1369 } 1370 if (data->map != NULL) 1371 bus_dmamap_destroy(sc->sc_dmat, data->map); 1372 } 1373 } 1374 1375 void 1376 iwn5000_ict_reset(struct iwn_softc *sc) 1377 { 1378 /* Disable interrupts. */ 1379 IWN_WRITE(sc, IWN_INT_MASK, 0); 1380 1381 /* Reset ICT table. */ 1382 memset(sc->ict, 0, IWN_ICT_SIZE); 1383 sc->ict_cur = 0; 1384 1385 /* Set physical address of ICT table (4KB aligned). */ 1386 DPRINTF(("enabling ICT\n")); 1387 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE | 1388 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12); 1389 1390 /* Enable periodic RX interrupt. */ 1391 sc->int_mask |= IWN_INT_RX_PERIODIC; 1392 /* Switch to ICT interrupt mode in driver. */ 1393 sc->sc_flags |= IWN_FLAG_USE_ICT; 1394 1395 /* Re-enable interrupts. */ 1396 IWN_WRITE(sc, IWN_INT, 0xffffffff); 1397 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 1398 } 1399 1400 int 1401 iwn_read_eeprom(struct iwn_softc *sc) 1402 { 1403 struct iwn_ops *ops = &sc->ops; 1404 struct ieee80211com *ic = &sc->sc_ic; 1405 uint16_t val; 1406 int error; 1407 1408 /* Check whether adapter has an EEPROM or an OTPROM. */ 1409 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 && 1410 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP)) 1411 sc->sc_flags |= IWN_FLAG_HAS_OTPROM; 1412 DPRINTF(("%s found\n", (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? 1413 "OTPROM" : "EEPROM")); 1414 1415 /* Adapter has to be powered on for EEPROM access to work. */ 1416 if ((error = iwn_apm_init(sc)) != 0) { 1417 printf("%s: could not power ON adapter\n", 1418 sc->sc_dev.dv_xname); 1419 return error; 1420 } 1421 1422 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) { 1423 printf("%s: bad ROM signature\n", sc->sc_dev.dv_xname); 1424 return EIO; 1425 } 1426 if ((error = iwn_eeprom_lock(sc)) != 0) { 1427 printf("%s: could not lock ROM (error=%d)\n", 1428 sc->sc_dev.dv_xname, error); 1429 return error; 1430 } 1431 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) { 1432 if ((error = iwn_init_otprom(sc)) != 0) { 1433 printf("%s: could not initialize OTPROM\n", 1434 sc->sc_dev.dv_xname); 1435 return error; 1436 } 1437 } 1438 1439 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2); 1440 DPRINTF(("SKU capabilities=0x%04x\n", letoh16(val))); 1441 /* Check if HT support is bonded out. */ 1442 if (val & htole16(IWN_EEPROM_SKU_CAP_11N)) 1443 sc->sc_flags |= IWN_FLAG_HAS_11N; 1444 1445 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2); 1446 sc->rfcfg = letoh16(val); 1447 DPRINTF(("radio config=0x%04x\n", sc->rfcfg)); 1448 /* Read Tx/Rx chains from ROM unless it's known to be broken. */ 1449 if (sc->txchainmask == 0) 1450 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg); 1451 if (sc->rxchainmask == 0) 1452 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg); 1453 1454 /* Read MAC address. */ 1455 iwn_read_prom_data(sc, IWN_EEPROM_MAC, ic->ic_myaddr, 6); 1456 1457 /* Read adapter-specific information from EEPROM. */ 1458 ops->read_eeprom(sc); 1459 1460 iwn_apm_stop(sc); /* Power OFF adapter. */ 1461 1462 iwn_eeprom_unlock(sc); 1463 return 0; 1464 } 1465 1466 void 1467 iwn4965_read_eeprom(struct iwn_softc *sc) 1468 { 1469 uint32_t addr; 1470 uint16_t val; 1471 int i; 1472 1473 /* Read regulatory domain (4 ASCII characters). */ 1474 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4); 1475 1476 /* Read the list of authorized channels (20MHz ones only). */ 1477 for (i = 0; i < 5; i++) { 1478 addr = iwn4965_regulatory_bands[i]; 1479 iwn_read_eeprom_channels(sc, i, addr); 1480 } 1481 1482 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */ 1483 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2); 1484 sc->maxpwr2GHz = val & 0xff; 1485 sc->maxpwr5GHz = val >> 8; 1486 /* Check that EEPROM values are within valid range. */ 1487 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50) 1488 sc->maxpwr5GHz = 38; 1489 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50) 1490 sc->maxpwr2GHz = 38; 1491 DPRINTF(("maxpwr 2GHz=%d 5GHz=%d\n", sc->maxpwr2GHz, sc->maxpwr5GHz)); 1492 1493 /* Read samples for each TX power group. */ 1494 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands, 1495 sizeof sc->bands); 1496 1497 /* Read voltage at which samples were taken. */ 1498 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2); 1499 sc->eeprom_voltage = (int16_t)letoh16(val); 1500 DPRINTF(("voltage=%d (in 0.3V)\n", sc->eeprom_voltage)); 1501 1502 #ifdef IWN_DEBUG 1503 /* Print samples. */ 1504 if (iwn_debug > 0) { 1505 for (i = 0; i < IWN_NBANDS; i++) 1506 iwn4965_print_power_group(sc, i); 1507 } 1508 #endif 1509 } 1510 1511 #ifdef IWN_DEBUG 1512 void 1513 iwn4965_print_power_group(struct iwn_softc *sc, int i) 1514 { 1515 struct iwn4965_eeprom_band *band = &sc->bands[i]; 1516 struct iwn4965_eeprom_chan_samples *chans = band->chans; 1517 int j, c; 1518 1519 printf("===band %d===\n", i); 1520 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi); 1521 printf("chan1 num=%d\n", chans[0].num); 1522 for (c = 0; c < 2; c++) { 1523 for (j = 0; j < IWN_NSAMPLES; j++) { 1524 printf("chain %d, sample %d: temp=%d gain=%d " 1525 "power=%d pa_det=%d\n", c, j, 1526 chans[0].samples[c][j].temp, 1527 chans[0].samples[c][j].gain, 1528 chans[0].samples[c][j].power, 1529 chans[0].samples[c][j].pa_det); 1530 } 1531 } 1532 printf("chan2 num=%d\n", chans[1].num); 1533 for (c = 0; c < 2; c++) { 1534 for (j = 0; j < IWN_NSAMPLES; j++) { 1535 printf("chain %d, sample %d: temp=%d gain=%d " 1536 "power=%d pa_det=%d\n", c, j, 1537 chans[1].samples[c][j].temp, 1538 chans[1].samples[c][j].gain, 1539 chans[1].samples[c][j].power, 1540 chans[1].samples[c][j].pa_det); 1541 } 1542 } 1543 } 1544 #endif 1545 1546 void 1547 iwn5000_read_eeprom(struct iwn_softc *sc) 1548 { 1549 struct iwn5000_eeprom_calib_hdr hdr; 1550 int32_t volt; 1551 uint32_t base, addr; 1552 uint16_t val; 1553 int i; 1554 1555 /* Read regulatory domain (4 ASCII characters). */ 1556 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1557 base = letoh16(val); 1558 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN, 1559 sc->eeprom_domain, 4); 1560 1561 /* Read the list of authorized channels (20MHz ones only). */ 1562 for (i = 0; i < 5; i++) { 1563 addr = base + iwn5000_regulatory_bands[i]; 1564 iwn_read_eeprom_channels(sc, i, addr); 1565 } 1566 1567 /* Read enhanced TX power information for 6000 Series. */ 1568 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 1569 iwn_read_eeprom_enhinfo(sc); 1570 1571 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2); 1572 base = letoh16(val); 1573 iwn_read_prom_data(sc, base, &hdr, sizeof hdr); 1574 DPRINTF(("calib version=%u pa type=%u voltage=%u\n", 1575 hdr.version, hdr.pa_type, letoh16(hdr.volt))); 1576 sc->calib_ver = hdr.version; 1577 1578 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 1579 sc->hw_type == IWN_HW_REV_TYPE_2000 || 1580 sc->hw_type == IWN_HW_REV_TYPE_135 || 1581 sc->hw_type == IWN_HW_REV_TYPE_105) { 1582 sc->eeprom_voltage = letoh16(hdr.volt); 1583 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1584 sc->eeprom_temp = letoh16(val); 1585 iwn_read_prom_data(sc, base + IWN2000_EEPROM_RAWTEMP, &val, 2); 1586 sc->eeprom_rawtemp = letoh16(val); 1587 } 1588 1589 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 1590 /* Compute temperature offset. */ 1591 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2); 1592 sc->eeprom_temp = letoh16(val); 1593 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2); 1594 volt = letoh16(val); 1595 sc->temp_off = sc->eeprom_temp - (volt / -5); 1596 DPRINTF(("temp=%d volt=%d offset=%dK\n", 1597 sc->eeprom_temp, volt, sc->temp_off)); 1598 } else { 1599 /* Read crystal calibration. */ 1600 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL, 1601 &sc->eeprom_crystal, sizeof (uint32_t)); 1602 DPRINTF(("crystal calibration 0x%08x\n", 1603 letoh32(sc->eeprom_crystal))); 1604 } 1605 } 1606 1607 void 1608 iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr) 1609 { 1610 struct ieee80211com *ic = &sc->sc_ic; 1611 const struct iwn_chan_band *band = &iwn_bands[n]; 1612 struct iwn_eeprom_chan channels[IWN_MAX_CHAN_PER_BAND]; 1613 uint8_t chan; 1614 int i; 1615 1616 iwn_read_prom_data(sc, addr, channels, 1617 band->nchan * sizeof (struct iwn_eeprom_chan)); 1618 1619 for (i = 0; i < band->nchan; i++) { 1620 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) 1621 continue; 1622 1623 chan = band->chan[i]; 1624 1625 if (n == 0) { /* 2GHz band */ 1626 ic->ic_channels[chan].ic_freq = 1627 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ); 1628 ic->ic_channels[chan].ic_flags = 1629 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 1630 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 1631 1632 } else { /* 5GHz band */ 1633 /* 1634 * Some adapters support channels 7, 8, 11 and 12 1635 * both in the 2GHz and 4.9GHz bands. 1636 * Because of limitations in our net80211 layer, 1637 * we don't support them in the 4.9GHz band. 1638 */ 1639 if (chan <= 14) 1640 continue; 1641 1642 ic->ic_channels[chan].ic_freq = 1643 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ); 1644 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A; 1645 /* We have at least one valid 5GHz channel. */ 1646 sc->sc_flags |= IWN_FLAG_HAS_5GHZ; 1647 } 1648 1649 /* Is active scan allowed on this channel? */ 1650 if (!(channels[i].flags & IWN_EEPROM_CHAN_ACTIVE)) { 1651 ic->ic_channels[chan].ic_flags |= 1652 IEEE80211_CHAN_PASSIVE; 1653 } 1654 1655 /* Save maximum allowed TX power for this channel. */ 1656 sc->maxpwr[chan] = channels[i].maxpwr; 1657 1658 if (sc->sc_flags & IWN_FLAG_HAS_11N) 1659 ic->ic_channels[chan].ic_flags |= IEEE80211_CHAN_HT; 1660 1661 DPRINTF(("adding chan %d flags=0x%x maxpwr=%d\n", 1662 chan, channels[i].flags, sc->maxpwr[chan])); 1663 } 1664 } 1665 1666 void 1667 iwn_read_eeprom_enhinfo(struct iwn_softc *sc) 1668 { 1669 struct iwn_eeprom_enhinfo enhinfo[35]; 1670 uint16_t val, base; 1671 int8_t maxpwr; 1672 int i; 1673 1674 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2); 1675 base = letoh16(val); 1676 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO, 1677 enhinfo, sizeof enhinfo); 1678 1679 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr); 1680 for (i = 0; i < nitems(enhinfo); i++) { 1681 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0) 1682 continue; /* Skip invalid entries. */ 1683 1684 maxpwr = 0; 1685 if (sc->txchainmask & IWN_ANT_A) 1686 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]); 1687 if (sc->txchainmask & IWN_ANT_B) 1688 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]); 1689 if (sc->txchainmask & IWN_ANT_C) 1690 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]); 1691 if (sc->ntxchains == 2) 1692 maxpwr = MAX(maxpwr, enhinfo[i].mimo2); 1693 else if (sc->ntxchains == 3) 1694 maxpwr = MAX(maxpwr, enhinfo[i].mimo3); 1695 maxpwr /= 2; /* Convert half-dBm to dBm. */ 1696 1697 DPRINTF(("enhinfo %d, maxpwr=%d\n", i, maxpwr)); 1698 sc->enh_maxpwr[i] = maxpwr; 1699 } 1700 } 1701 1702 struct ieee80211_node * 1703 iwn_node_alloc(struct ieee80211com *ic) 1704 { 1705 return malloc(sizeof (struct iwn_node), M_DEVBUF, M_NOWAIT | M_ZERO); 1706 } 1707 1708 void 1709 iwn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) 1710 { 1711 struct iwn_softc *sc = ic->ic_if.if_softc; 1712 struct iwn_node *wn = (void *)ni; 1713 uint8_t rate; 1714 int ridx, i; 1715 1716 if ((ni->ni_flags & IEEE80211_NODE_HT) == 0) 1717 ieee80211_amrr_node_init(&sc->amrr, &wn->amn); 1718 1719 /* Start at lowest available bit-rate, AMRR/MiRA will raise. */ 1720 ni->ni_txrate = 0; 1721 ni->ni_txmcs = 0; 1722 1723 for (i = 0; i < ni->ni_rates.rs_nrates; i++) { 1724 rate = ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL; 1725 /* Map 802.11 rate to HW rate index. */ 1726 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 1727 if (iwn_rates[ridx].plcp != IWN_PLCP_INVALID && 1728 iwn_rates[ridx].rate == rate) 1729 break; 1730 } 1731 wn->ridx[i] = ridx; 1732 } 1733 } 1734 1735 int 1736 iwn_media_change(struct ifnet *ifp) 1737 { 1738 struct iwn_softc *sc = ifp->if_softc; 1739 struct ieee80211com *ic = &sc->sc_ic; 1740 uint8_t rate, ridx; 1741 int error; 1742 1743 error = ieee80211_media_change(ifp); 1744 if (error != ENETRESET) 1745 return error; 1746 1747 if (ic->ic_fixed_mcs != -1) 1748 sc->fixed_ridx = iwn_mcs2ridx[ic->ic_fixed_mcs]; 1749 if (ic->ic_fixed_rate != -1) { 1750 rate = ic->ic_sup_rates[ic->ic_curmode]. 1751 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL; 1752 /* Map 802.11 rate to HW rate index. */ 1753 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) 1754 if (iwn_rates[ridx].plcp != IWN_PLCP_INVALID && 1755 iwn_rates[ridx].rate == rate) 1756 break; 1757 sc->fixed_ridx = ridx; 1758 } 1759 1760 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1761 (IFF_UP | IFF_RUNNING)) { 1762 iwn_stop(ifp); 1763 error = iwn_init(ifp); 1764 } 1765 return error; 1766 } 1767 1768 int 1769 iwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1770 { 1771 struct ifnet *ifp = &ic->ic_if; 1772 struct iwn_softc *sc = ifp->if_softc; 1773 struct ieee80211_node *ni = ic->ic_bss; 1774 struct iwn_node *wn = (void *)ni; 1775 int error; 1776 1777 if (ic->ic_state == IEEE80211_S_RUN) { 1778 if (nstate == IEEE80211_S_SCAN) { 1779 /* 1780 * During RUN->SCAN we don't call sc_newstate() so 1781 * we must stop A-MPDU Tx ourselves in this case. 1782 */ 1783 ieee80211_stop_ampdu_tx(ic, ni, -1); 1784 ieee80211_ba_del(ni); 1785 } 1786 ieee80211_mira_cancel_timeouts(&wn->mn); 1787 timeout_del(&sc->calib_to); 1788 sc->calib.state = IWN_CALIB_STATE_INIT; 1789 if (sc->sc_flags & IWN_FLAG_BGSCAN) 1790 iwn_scan_abort(sc); 1791 } 1792 1793 if (ic->ic_state == IEEE80211_S_SCAN) { 1794 if (nstate == IEEE80211_S_SCAN) { 1795 if (sc->sc_flags & IWN_FLAG_SCANNING) 1796 return 0; 1797 } else 1798 sc->sc_flags &= ~IWN_FLAG_SCANNING; 1799 /* Turn LED off when leaving scan state. */ 1800 iwn_set_led(sc, IWN_LED_LINK, 1, 0); 1801 } 1802 1803 if (ic->ic_state >= IEEE80211_S_ASSOC && 1804 nstate <= IEEE80211_S_ASSOC) { 1805 /* Reset state to handle re- and disassociations. */ 1806 sc->rxon.associd = 0; 1807 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS); 1808 sc->calib.state = IWN_CALIB_STATE_INIT; 1809 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 1810 if (error != 0) 1811 printf("%s: RXON command failed\n", 1812 sc->sc_dev.dv_xname); 1813 } 1814 1815 switch (nstate) { 1816 case IEEE80211_S_SCAN: 1817 /* Make the link LED blink while we're scanning. */ 1818 iwn_set_led(sc, IWN_LED_LINK, 10, 10); 1819 1820 if ((error = iwn_scan(sc, IEEE80211_CHAN_2GHZ, 0)) != 0) { 1821 printf("%s: could not initiate scan\n", 1822 sc->sc_dev.dv_xname); 1823 return error; 1824 } 1825 if (ifp->if_flags & IFF_DEBUG) 1826 printf("%s: %s -> %s\n", ifp->if_xname, 1827 ieee80211_state_name[ic->ic_state], 1828 ieee80211_state_name[nstate]); 1829 if ((sc->sc_flags & IWN_FLAG_BGSCAN) == 0) { 1830 ieee80211_set_link_state(ic, LINK_STATE_DOWN); 1831 ieee80211_node_cleanup(ic, ic->ic_bss); 1832 } 1833 ic->ic_state = nstate; 1834 return 0; 1835 1836 case IEEE80211_S_ASSOC: 1837 if (ic->ic_state != IEEE80211_S_RUN) 1838 break; 1839 /* FALLTHROUGH */ 1840 case IEEE80211_S_AUTH: 1841 if ((error = iwn_auth(sc, arg)) != 0) { 1842 printf("%s: could not move to auth state\n", 1843 sc->sc_dev.dv_xname); 1844 return error; 1845 } 1846 break; 1847 1848 case IEEE80211_S_RUN: 1849 if ((error = iwn_run(sc)) != 0) { 1850 printf("%s: could not move to run state\n", 1851 sc->sc_dev.dv_xname); 1852 return error; 1853 } 1854 break; 1855 1856 case IEEE80211_S_INIT: 1857 sc->calib.state = IWN_CALIB_STATE_INIT; 1858 break; 1859 } 1860 1861 return sc->sc_newstate(ic, nstate, arg); 1862 } 1863 1864 void 1865 iwn_iter_func(void *arg, struct ieee80211_node *ni) 1866 { 1867 struct iwn_softc *sc = arg; 1868 struct iwn_node *wn = (void *)ni; 1869 1870 if ((ni->ni_flags & IEEE80211_NODE_HT) == 0) { 1871 int old_txrate = ni->ni_txrate; 1872 ieee80211_amrr_choose(&sc->amrr, ni, &wn->amn); 1873 if (old_txrate != ni->ni_txrate) 1874 iwn_set_link_quality(sc, ni); 1875 } 1876 } 1877 1878 void 1879 iwn_calib_timeout(void *arg) 1880 { 1881 struct iwn_softc *sc = arg; 1882 struct ieee80211com *ic = &sc->sc_ic; 1883 int s; 1884 1885 s = splnet(); 1886 if (ic->ic_fixed_rate == -1) { 1887 if (ic->ic_opmode == IEEE80211_M_STA) 1888 iwn_iter_func(sc, ic->ic_bss); 1889 else 1890 ieee80211_iterate_nodes(ic, iwn_iter_func, sc); 1891 } 1892 /* Force automatic TX power calibration every 60 secs. */ 1893 if (++sc->calib_cnt >= 120) { 1894 uint32_t flags = 0; 1895 1896 DPRINTFN(2, ("sending request for statistics\n")); 1897 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, 1898 sizeof flags, 1); 1899 sc->calib_cnt = 0; 1900 } 1901 splx(s); 1902 1903 /* Automatic rate control triggered every 500ms. */ 1904 timeout_add_msec(&sc->calib_to, 500); 1905 } 1906 1907 int 1908 iwn_ccmp_decap(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1909 { 1910 struct ieee80211com *ic = &sc->sc_ic; 1911 struct ieee80211_key *k = &ni->ni_pairwise_key; 1912 struct ieee80211_frame *wh; 1913 struct ieee80211_rx_ba *ba; 1914 uint64_t pn, *prsc; 1915 uint8_t *ivp; 1916 uint8_t tid; 1917 int hdrlen, hasqos; 1918 1919 wh = mtod(m, struct ieee80211_frame *); 1920 hdrlen = ieee80211_get_hdrlen(wh); 1921 ivp = (uint8_t *)wh + hdrlen; 1922 1923 /* Check that ExtIV bit is set. */ 1924 if (!(ivp[3] & IEEE80211_WEP_EXTIV)) { 1925 DPRINTF(("CCMP decap ExtIV not set\n")); 1926 return 1; 1927 } 1928 hasqos = ieee80211_has_qos(wh); 1929 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0; 1930 ba = hasqos ? &ni->ni_rx_ba[tid] : NULL; 1931 prsc = &k->k_rsc[tid]; 1932 1933 /* Extract the 48-bit PN from the CCMP header. */ 1934 pn = (uint64_t)ivp[0] | 1935 (uint64_t)ivp[1] << 8 | 1936 (uint64_t)ivp[4] << 16 | 1937 (uint64_t)ivp[5] << 24 | 1938 (uint64_t)ivp[6] << 32 | 1939 (uint64_t)ivp[7] << 40; 1940 if (pn <= *prsc) { 1941 DPRINTF(("CCMP replayed\n")); 1942 ic->ic_stats.is_ccmp_replays++; 1943 return 1; 1944 } 1945 /* Last seen packet number is updated in ieee80211_inputm(). */ 1946 1947 /* Strip MIC. IV will be stripped by ieee80211_inputm(). */ 1948 m_adj(m, -IEEE80211_CCMP_MICLEN); 1949 return 0; 1950 } 1951 1952 /* 1953 * Process an RX_PHY firmware notification. This is usually immediately 1954 * followed by an MPDU_RX_DONE notification. 1955 */ 1956 void 1957 iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1958 struct iwn_rx_data *data) 1959 { 1960 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1); 1961 1962 DPRINTFN(2, ("received PHY stats\n")); 1963 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 1964 sizeof (*stat), BUS_DMASYNC_POSTREAD); 1965 1966 /* Save RX statistics, they will be used on MPDU_RX_DONE. */ 1967 memcpy(&sc->last_rx_stat, stat, sizeof (*stat)); 1968 sc->last_rx_valid = IWN_LAST_RX_VALID; 1969 /* 1970 * The firmware does not send separate RX_PHY 1971 * notifications for A-MPDU subframes. 1972 */ 1973 if (stat->flags & htole16(IWN_STAT_FLAG_AGG)) 1974 sc->last_rx_valid |= IWN_LAST_RX_AMPDU; 1975 } 1976 1977 /* 1978 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification. 1979 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one. 1980 */ 1981 void 1982 iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 1983 struct iwn_rx_data *data, struct mbuf_list *ml) 1984 { 1985 struct iwn_ops *ops = &sc->ops; 1986 struct ieee80211com *ic = &sc->sc_ic; 1987 struct ifnet *ifp = &ic->ic_if; 1988 struct iwn_rx_ring *ring = &sc->rxq; 1989 struct ieee80211_frame *wh; 1990 struct ieee80211_rxinfo rxi; 1991 struct ieee80211_node *ni; 1992 struct ieee80211_channel *bss_chan = NULL; 1993 uint8_t saved_bssid[IEEE80211_ADDR_LEN] = { 0 }; 1994 struct mbuf *m, *m1; 1995 struct iwn_rx_stat *stat; 1996 caddr_t head; 1997 uint32_t flags; 1998 int error, len, rssi; 1999 uint16_t chan; 2000 2001 if (desc->type == IWN_MPDU_RX_DONE) { 2002 /* Check for prior RX_PHY notification. */ 2003 if (!sc->last_rx_valid) { 2004 DPRINTF(("missing RX_PHY\n")); 2005 return; 2006 } 2007 sc->last_rx_valid &= ~IWN_LAST_RX_VALID; 2008 stat = &sc->last_rx_stat; 2009 if ((sc->last_rx_valid & IWN_LAST_RX_AMPDU) && 2010 (stat->flags & htole16(IWN_STAT_FLAG_AGG)) == 0) { 2011 DPRINTF(("missing RX_PHY (expecting A-MPDU)\n")); 2012 return; 2013 } 2014 if ((sc->last_rx_valid & IWN_LAST_RX_AMPDU) == 0 && 2015 (stat->flags & htole16(IWN_STAT_FLAG_AGG))) { 2016 DPRINTF(("missing RX_PHY (unexpected A-MPDU)\n")); 2017 return; 2018 } 2019 } else 2020 stat = (struct iwn_rx_stat *)(desc + 1); 2021 2022 bus_dmamap_sync(sc->sc_dmat, data->map, 0, IWN_RBUF_SIZE, 2023 BUS_DMASYNC_POSTREAD); 2024 2025 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) { 2026 printf("%s: invalid RX statistic header\n", 2027 sc->sc_dev.dv_xname); 2028 return; 2029 } 2030 if (desc->type == IWN_MPDU_RX_DONE) { 2031 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1); 2032 head = (caddr_t)(mpdu + 1); 2033 len = letoh16(mpdu->len); 2034 } else { 2035 head = (caddr_t)(stat + 1) + stat->cfg_phy_len; 2036 len = letoh16(stat->len); 2037 } 2038 2039 flags = letoh32(*(uint32_t *)(head + len)); 2040 2041 /* Discard frames with a bad FCS early. */ 2042 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) { 2043 DPRINTFN(2, ("RX flags error %x\n", flags)); 2044 ifp->if_ierrors++; 2045 return; 2046 } 2047 /* Discard frames that are too short. */ 2048 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2049 /* Allow control frames in monitor mode. */ 2050 if (len < sizeof (struct ieee80211_frame_cts)) { 2051 DPRINTF(("frame too short: %d\n", len)); 2052 ic->ic_stats.is_rx_tooshort++; 2053 ifp->if_ierrors++; 2054 return; 2055 } 2056 } else if (len < sizeof (*wh)) { 2057 DPRINTF(("frame too short: %d\n", len)); 2058 ic->ic_stats.is_rx_tooshort++; 2059 ifp->if_ierrors++; 2060 return; 2061 } 2062 2063 m1 = MCLGETI(NULL, M_DONTWAIT, NULL, IWN_RBUF_SIZE); 2064 if (m1 == NULL) { 2065 ic->ic_stats.is_rx_nombuf++; 2066 ifp->if_ierrors++; 2067 return; 2068 } 2069 bus_dmamap_unload(sc->sc_dmat, data->map); 2070 2071 error = bus_dmamap_load(sc->sc_dmat, data->map, mtod(m1, void *), 2072 IWN_RBUF_SIZE, NULL, BUS_DMA_NOWAIT | BUS_DMA_READ); 2073 if (error != 0) { 2074 m_freem(m1); 2075 2076 /* Try to reload the old mbuf. */ 2077 error = bus_dmamap_load(sc->sc_dmat, data->map, 2078 mtod(data->m, void *), IWN_RBUF_SIZE, NULL, 2079 BUS_DMA_NOWAIT | BUS_DMA_READ); 2080 if (error != 0) { 2081 panic("%s: could not load old RX mbuf", 2082 sc->sc_dev.dv_xname); 2083 } 2084 /* Physical address may have changed. */ 2085 ring->desc[ring->cur] = 2086 htole32(data->map->dm_segs[0].ds_addr >> 8); 2087 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2088 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2089 BUS_DMASYNC_PREWRITE); 2090 ifp->if_ierrors++; 2091 return; 2092 } 2093 2094 m = data->m; 2095 data->m = m1; 2096 /* Update RX descriptor. */ 2097 ring->desc[ring->cur] = htole32(data->map->dm_segs[0].ds_addr >> 8); 2098 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 2099 ring->cur * sizeof (uint32_t), sizeof (uint32_t), 2100 BUS_DMASYNC_PREWRITE); 2101 2102 /* Finalize mbuf. */ 2103 m->m_data = head; 2104 m->m_pkthdr.len = m->m_len = len; 2105 2106 /* 2107 * Grab a reference to the source node. Note that control frames are 2108 * shorter than struct ieee80211_frame but ieee80211_find_rxnode() 2109 * is being careful about control frames. 2110 */ 2111 wh = mtod(m, struct ieee80211_frame *); 2112 if (len < sizeof (*wh) && 2113 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 2114 ic->ic_stats.is_rx_tooshort++; 2115 ifp->if_ierrors++; 2116 m_freem(m); 2117 return; 2118 } 2119 ni = ieee80211_find_rxnode(ic, wh); 2120 2121 rxi.rxi_flags = 0; 2122 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) 2123 && (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) && 2124 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 2125 (ni->ni_flags & IEEE80211_NODE_RXPROT) && 2126 ni->ni_pairwise_key.k_cipher == IEEE80211_CIPHER_CCMP) { 2127 if ((flags & IWN_RX_CIPHER_MASK) != IWN_RX_CIPHER_CCMP) { 2128 ic->ic_stats.is_ccmp_dec_errs++; 2129 ifp->if_ierrors++; 2130 m_freem(m); 2131 ieee80211_release_node(ic, ni); 2132 return; 2133 } 2134 /* Check whether decryption was successful or not. */ 2135 if ((desc->type == IWN_MPDU_RX_DONE && 2136 (flags & (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) != 2137 (IWN_RX_MPDU_DEC | IWN_RX_MPDU_MIC_OK)) || 2138 (desc->type != IWN_MPDU_RX_DONE && 2139 (flags & IWN_RX_DECRYPT_MASK) != IWN_RX_DECRYPT_OK)) { 2140 DPRINTF(("CCMP decryption failed 0x%x\n", flags)); 2141 ic->ic_stats.is_ccmp_dec_errs++; 2142 ifp->if_ierrors++; 2143 m_freem(m); 2144 ieee80211_release_node(ic, ni); 2145 return; 2146 } 2147 if (iwn_ccmp_decap(sc, m, ni) != 0) { 2148 ifp->if_ierrors++; 2149 m_freem(m); 2150 ieee80211_release_node(ic, ni); 2151 return; 2152 } 2153 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 2154 } 2155 2156 rssi = ops->get_rssi(stat); 2157 2158 chan = stat->chan; 2159 if (chan > IEEE80211_CHAN_MAX) 2160 chan = IEEE80211_CHAN_MAX; 2161 2162 /* Fix current channel. */ 2163 if (ni == ic->ic_bss) { 2164 /* 2165 * We may switch ic_bss's channel during scans. 2166 * Record the current channel so we can restore it later. 2167 */ 2168 bss_chan = ni->ni_chan; 2169 IEEE80211_ADDR_COPY(&saved_bssid, ni->ni_macaddr); 2170 } 2171 ni->ni_chan = &ic->ic_channels[chan]; 2172 2173 #if NBPFILTER > 0 2174 if (sc->sc_drvbpf != NULL) { 2175 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap; 2176 uint16_t chan_flags; 2177 2178 tap->wr_flags = 0; 2179 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE)) 2180 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2181 tap->wr_chan_freq = htole16(ic->ic_channels[chan].ic_freq); 2182 chan_flags = ic->ic_channels[chan].ic_flags; 2183 if (ic->ic_curmode != IEEE80211_MODE_11N) 2184 chan_flags &= ~IEEE80211_CHAN_HT; 2185 tap->wr_chan_flags = htole16(chan_flags); 2186 tap->wr_dbm_antsignal = (int8_t)rssi; 2187 tap->wr_dbm_antnoise = (int8_t)sc->noise; 2188 tap->wr_tsft = stat->tstamp; 2189 if (stat->rflags & IWN_RFLAG_MCS) { 2190 tap->wr_rate = (0x80 | stat->rate); /* HT MCS index */ 2191 } else { 2192 switch (stat->rate) { 2193 /* CCK rates. */ 2194 case 10: tap->wr_rate = 2; break; 2195 case 20: tap->wr_rate = 4; break; 2196 case 55: tap->wr_rate = 11; break; 2197 case 110: tap->wr_rate = 22; break; 2198 /* OFDM rates. */ 2199 case 0xd: tap->wr_rate = 12; break; 2200 case 0xf: tap->wr_rate = 18; break; 2201 case 0x5: tap->wr_rate = 24; break; 2202 case 0x7: tap->wr_rate = 36; break; 2203 case 0x9: tap->wr_rate = 48; break; 2204 case 0xb: tap->wr_rate = 72; break; 2205 case 0x1: tap->wr_rate = 96; break; 2206 case 0x3: tap->wr_rate = 108; break; 2207 /* Unknown rate: should not happen. */ 2208 default: tap->wr_rate = 0; 2209 } 2210 } 2211 2212 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, 2213 m, BPF_DIRECTION_IN); 2214 } 2215 #endif 2216 2217 /* Send the frame to the 802.11 layer. */ 2218 rxi.rxi_rssi = rssi; 2219 rxi.rxi_tstamp = 0; /* unused */ 2220 ieee80211_inputm(ifp, m, ni, &rxi, ml); 2221 2222 /* 2223 * ieee80211_inputm() might have changed our BSS. 2224 * Restore ic_bss's channel if we are still in the same BSS. 2225 */ 2226 if (ni == ic->ic_bss && IEEE80211_ADDR_EQ(saved_bssid, ni->ni_macaddr)) 2227 ni->ni_chan = bss_chan; 2228 2229 /* Node is no longer needed. */ 2230 ieee80211_release_node(ic, ni); 2231 } 2232 2233 void 2234 iwn_mira_choose(struct iwn_softc *sc, struct ieee80211_node *ni) 2235 { 2236 struct ieee80211com *ic = &sc->sc_ic; 2237 struct iwn_node *wn = (void *)ni; 2238 int best_mcs = ieee80211_mira_get_best_mcs(&wn->mn); 2239 2240 ieee80211_mira_choose(&wn->mn, ic, ni); 2241 2242 /* 2243 * Update firmware's LQ retry table if MiRA has chosen a new MCS. 2244 * 2245 * We only need to do this if the best MCS has changed because 2246 * we ask firmware to use a fixed MCS while MiRA is probing a 2247 * candidate MCS. 2248 * While not probing we ask firmware to retry at lower rates in case 2249 * Tx at the newly chosen best MCS ends up failing, and then report 2250 * any resulting Tx retries to MiRA in order to trigger probing. 2251 */ 2252 if (best_mcs != ieee80211_mira_get_best_mcs(&wn->mn)) 2253 iwn_set_link_quality(sc, ni); 2254 } 2255 2256 void 2257 iwn_ampdu_rate_control(struct iwn_softc *sc, struct ieee80211_node *ni, 2258 struct iwn_tx_ring *txq, int tid, uint16_t seq, uint16_t ssn) 2259 { 2260 struct ieee80211com *ic = &sc->sc_ic; 2261 struct iwn_node *wn = (void *)ni; 2262 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 2263 int min_ampdu_id, max_ampdu_id, id; 2264 int idx, end_idx; 2265 2266 /* Determine the min/max IDs we assigned to AMPDUs in this range. */ 2267 idx = IWN_AGG_SSN_TO_TXQ_IDX(seq); 2268 end_idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 2269 min_ampdu_id = txq->data[idx].ampdu_id; 2270 max_ampdu_id = min_ampdu_id; 2271 while (idx != end_idx) { 2272 struct iwn_tx_data *txdata = &txq->data[idx]; 2273 2274 if (txdata->m != NULL) { 2275 if (min_ampdu_id > txdata->ampdu_id) 2276 min_ampdu_id = txdata->ampdu_id; 2277 if (max_ampdu_id < txdata->ampdu_id) 2278 max_ampdu_id = txdata->ampdu_id; 2279 } 2280 2281 idx = (idx + 1) % IWN_TX_RING_COUNT; 2282 } 2283 2284 /* 2285 * Update Tx rate statistics for A-MPDUs before firmware's BA window. 2286 */ 2287 for (id = min_ampdu_id; id <= max_ampdu_id; id++) { 2288 int have_ack = 0, bit = 0; 2289 idx = IWN_AGG_SSN_TO_TXQ_IDX(seq); 2290 end_idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 2291 wn->mn.agglen = 0; 2292 wn->mn.ampdu_size = 0; 2293 while (idx != end_idx) { 2294 struct iwn_tx_data *txdata = &txq->data[idx]; 2295 uint16_t s = (seq + bit) & 0xfff; 2296 /* 2297 * We can assume that this subframe has been ACKed 2298 * because ACK failures come as single frames and 2299 * before failing an A-MPDU subframe the firmware 2300 * sends it as a single frame at least once. 2301 * 2302 * However, when this A-MPDU was transmitted we 2303 * learned how many subframes it contained. 2304 * So if firmware isn't reporting all subframes now 2305 * we can deduce an ACK failure for missing frames. 2306 */ 2307 if (txdata->m != NULL && txdata->ampdu_id == id && 2308 txdata->ampdu_txmcs == ni->ni_txmcs && 2309 txdata->ampdu_nframes > 0 && 2310 (SEQ_LT(ba->ba_winend, s) || 2311 (ba->ba_bitmap & (1 << bit)) == 0)) { 2312 have_ack++; 2313 wn->mn.frames = txdata->ampdu_nframes; 2314 wn->mn.agglen = txdata->ampdu_nframes; 2315 wn->mn.ampdu_size = txdata->ampdu_size; 2316 if (txdata->retries > 1) 2317 wn->mn.retries++; 2318 if (!SEQ_LT(ba->ba_winend, s)) 2319 ieee80211_output_ba_record_ack(ic, ni, 2320 tid, s); 2321 } 2322 2323 idx = (idx + 1) % IWN_TX_RING_COUNT; 2324 bit++; 2325 } 2326 2327 if (have_ack > 0) { 2328 wn->mn.txfail = wn->mn.frames - have_ack; 2329 iwn_mira_choose(sc, ni); 2330 } 2331 } 2332 } 2333 2334 /* 2335 * Process an incoming Compressed BlockAck. 2336 * Note that these block ack notifications are generated by firmware and do 2337 * not necessarily correspond to contents of block ack frames seen on the air. 2338 */ 2339 void 2340 iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2341 struct iwn_rx_data *data) 2342 { 2343 struct iwn_compressed_ba *cba = (struct iwn_compressed_ba *)(desc + 1); 2344 struct ieee80211com *ic = &sc->sc_ic; 2345 struct ieee80211_node *ni; 2346 struct ieee80211_tx_ba *ba; 2347 struct iwn_tx_ring *txq; 2348 uint16_t seq, ssn; 2349 int qid; 2350 2351 if (ic->ic_state != IEEE80211_S_RUN) 2352 return; 2353 2354 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), sizeof (*cba), 2355 BUS_DMASYNC_POSTREAD); 2356 2357 if (!IEEE80211_ADDR_EQ(ic->ic_bss->ni_macaddr, cba->macaddr)) 2358 return; 2359 2360 ni = ic->ic_bss; 2361 2362 qid = le16toh(cba->qid); 2363 if (qid < sc->first_agg_txq || qid >= sc->ntxqs) 2364 return; 2365 2366 txq = &sc->txq[qid]; 2367 2368 /* Protect against a firmware bug where the queue/TID are off. */ 2369 if (qid != sc->first_agg_txq + cba->tid) 2370 return; 2371 2372 ba = &ni->ni_tx_ba[cba->tid]; 2373 if (ba->ba_state != IEEE80211_BA_AGREED) 2374 return; 2375 2376 /* 2377 * The first bit in cba->bitmap corresponds to the sequence number 2378 * stored in the sequence control field cba->seq. 2379 * Multiple BA notifications in a row may be using this number, with 2380 * additional bits being set in cba->bitmap. It is unclear how the 2381 * firmware decides to shift this window forward. 2382 * We rely on ba->ba_winstart instead. 2383 */ 2384 seq = le16toh(cba->seq) >> IEEE80211_SEQ_SEQ_SHIFT; 2385 2386 /* 2387 * The firmware's new BA window starting sequence number 2388 * corresponds to the first hole in cba->bitmap, implying 2389 * that all frames between 'seq' and 'ssn' (non-inclusive) 2390 * have been acked. 2391 */ 2392 ssn = le16toh(cba->ssn); 2393 2394 /* Skip rate control if our Tx rate is fixed. */ 2395 if (ic->ic_fixed_mcs == -1) 2396 iwn_ampdu_rate_control(sc, ni, txq, cba->tid, ba->ba_winstart, 2397 ssn); 2398 2399 /* 2400 * SSN corresponds to the first (perhaps not yet transmitted) frame 2401 * in firmware's BA window. Firmware is not going to retransmit any 2402 * frames before its BA window so mark them all as done. 2403 */ 2404 if (SEQ_LT(ba->ba_winstart, ssn)) { 2405 ieee80211_output_ba_move_window(ic, ni, cba->tid, ssn); 2406 iwn_ampdu_txq_advance(sc, txq, qid, 2407 IWN_AGG_SSN_TO_TXQ_IDX(ssn)); 2408 iwn_clear_oactive(sc, txq); 2409 } 2410 } 2411 2412 /* 2413 * Process a CALIBRATION_RESULT notification sent by the initialization 2414 * firmware on response to a CMD_CALIB_CONFIG command (5000 only). 2415 */ 2416 void 2417 iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2418 struct iwn_rx_data *data) 2419 { 2420 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1); 2421 int len, idx = -1; 2422 2423 /* Runtime firmware should not send such a notification. */ 2424 if (sc->sc_flags & IWN_FLAG_CALIB_DONE) 2425 return; 2426 2427 len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK) - 4; 2428 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), len, 2429 BUS_DMASYNC_POSTREAD); 2430 2431 switch (calib->code) { 2432 case IWN5000_PHY_CALIB_DC: 2433 if (sc->hw_type == IWN_HW_REV_TYPE_5150 || 2434 sc->hw_type == IWN_HW_REV_TYPE_2030 || 2435 sc->hw_type == IWN_HW_REV_TYPE_2000 || 2436 sc->hw_type == IWN_HW_REV_TYPE_135 || 2437 sc->hw_type == IWN_HW_REV_TYPE_105) 2438 idx = 0; 2439 break; 2440 case IWN5000_PHY_CALIB_LO: 2441 idx = 1; 2442 break; 2443 case IWN5000_PHY_CALIB_TX_IQ: 2444 idx = 2; 2445 break; 2446 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC: 2447 if (sc->hw_type < IWN_HW_REV_TYPE_6000 && 2448 sc->hw_type != IWN_HW_REV_TYPE_5150) 2449 idx = 3; 2450 break; 2451 case IWN5000_PHY_CALIB_BASE_BAND: 2452 idx = 4; 2453 break; 2454 } 2455 if (idx == -1) /* Ignore other results. */ 2456 return; 2457 2458 /* Save calibration result. */ 2459 if (sc->calibcmd[idx].buf != NULL) 2460 free(sc->calibcmd[idx].buf, M_DEVBUF, 0); 2461 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT); 2462 if (sc->calibcmd[idx].buf == NULL) { 2463 DPRINTF(("not enough memory for calibration result %d\n", 2464 calib->code)); 2465 return; 2466 } 2467 DPRINTF(("saving calibration result code=%d len=%d\n", 2468 calib->code, len)); 2469 sc->calibcmd[idx].len = len; 2470 memcpy(sc->calibcmd[idx].buf, calib, len); 2471 } 2472 2473 /* 2474 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification. 2475 * The latter is sent by the firmware after each received beacon. 2476 */ 2477 void 2478 iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2479 struct iwn_rx_data *data) 2480 { 2481 struct iwn_ops *ops = &sc->ops; 2482 struct ieee80211com *ic = &sc->sc_ic; 2483 struct iwn_calib_state *calib = &sc->calib; 2484 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1); 2485 int temp; 2486 2487 /* Ignore statistics received during a scan. */ 2488 if (ic->ic_state != IEEE80211_S_RUN) 2489 return; 2490 2491 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2492 sizeof (*stats), BUS_DMASYNC_POSTREAD); 2493 2494 DPRINTFN(3, ("received statistics (cmd=%d)\n", desc->type)); 2495 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */ 2496 2497 /* Test if temperature has changed. */ 2498 if (stats->general.temp != sc->rawtemp) { 2499 /* Convert "raw" temperature to degC. */ 2500 sc->rawtemp = stats->general.temp; 2501 temp = ops->get_temperature(sc); 2502 DPRINTFN(2, ("temperature=%dC\n", temp)); 2503 2504 /* Update TX power if need be (4965AGN only). */ 2505 if (sc->hw_type == IWN_HW_REV_TYPE_4965) 2506 iwn4965_power_calibration(sc, temp); 2507 } 2508 2509 if (desc->type != IWN_BEACON_STATISTICS) 2510 return; /* Reply to a statistics request. */ 2511 2512 sc->noise = iwn_get_noise(&stats->rx.general); 2513 2514 /* Test that RSSI and noise are present in stats report. */ 2515 if (sc->noise == -127) 2516 return; 2517 2518 if (letoh32(stats->rx.general.flags) != 1) { 2519 DPRINTF(("received statistics without RSSI\n")); 2520 return; 2521 } 2522 2523 /* 2524 * XXX Differential gain calibration makes the 6005 firmware 2525 * crap out, so skip it for now. This effectively disables 2526 * sensitivity tuning as well. 2527 */ 2528 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 2529 return; 2530 2531 if (calib->state == IWN_CALIB_STATE_ASSOC) 2532 iwn_collect_noise(sc, &stats->rx.general); 2533 else if (calib->state == IWN_CALIB_STATE_RUN) 2534 iwn_tune_sensitivity(sc, &stats->rx); 2535 } 2536 2537 void 2538 iwn_ampdu_txq_advance(struct iwn_softc *sc, struct iwn_tx_ring *txq, int qid, 2539 int idx) 2540 { 2541 struct iwn_ops *ops = &sc->ops; 2542 2543 DPRINTFN(3, ("%s: txq->cur=%d txq->read=%d txq->queued=%d qid=%d " 2544 "idx=%d\n", __func__, txq->cur, txq->read, txq->queued, qid, idx)); 2545 2546 while (txq->read != idx) { 2547 struct iwn_tx_data *txdata = &txq->data[txq->read]; 2548 if (txdata->m != NULL) { 2549 ops->reset_sched(sc, qid, txq->read); 2550 iwn_tx_done_free_txdata(sc, txdata); 2551 txq->queued--; 2552 } 2553 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT; 2554 } 2555 } 2556 2557 /* 2558 * Handle A-MPDU Tx queue status report. 2559 * Tx failures come as single frames (perhaps out of order), and before failing 2560 * an A-MPDU subframe the firmware transmits it as a single frame at least once 2561 * and reports Tx success/failure here. Frames successfully transmitted in an 2562 * A-MPDU are completed when a compressed block ack notification is received. 2563 */ 2564 void 2565 iwn_ampdu_tx_done(struct iwn_softc *sc, struct iwn_tx_ring *txq, 2566 struct iwn_rx_desc *desc, uint16_t status, uint8_t ackfailcnt, 2567 uint8_t rate, uint8_t rflags, int nframes, uint32_t ssn, 2568 struct iwn_txagg_status *agg_status) 2569 { 2570 struct ieee80211com *ic = &sc->sc_ic; 2571 int tid = desc->qid - sc->first_agg_txq; 2572 struct iwn_tx_data *txdata = &txq->data[desc->idx]; 2573 struct ieee80211_node *ni = txdata->ni; 2574 struct iwn_node *wn = (void *)ni; 2575 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2576 status != IWN_TX_STATUS_DIRECT_DONE); 2577 struct ieee80211_tx_ba *ba; 2578 uint16_t seq; 2579 2580 sc->sc_tx_timer = 0; 2581 2582 if (ic->ic_state != IEEE80211_S_RUN) 2583 return; 2584 2585 if (nframes > 1) { 2586 int ampdu_id, have_ampdu_id = 0, ampdu_size = 0; 2587 int i; 2588 2589 /* Compute the size of this A-MPDU. */ 2590 for (i = 0; i < nframes; i++) { 2591 uint8_t qid = agg_status[i].qid; 2592 uint8_t idx = agg_status[i].idx; 2593 2594 if (qid != desc->qid) 2595 continue; 2596 2597 txdata = &txq->data[idx]; 2598 if (txdata->ni == NULL) 2599 continue; 2600 2601 ampdu_size += txdata->totlen + IEEE80211_CRC_LEN; 2602 } 2603 2604 /* 2605 * For each subframe collect Tx status, retries, and Tx rate. 2606 * (The Tx rate is the same for all subframes in this batch.) 2607 */ 2608 for (i = 0; i < nframes; i++) { 2609 uint8_t qid = agg_status[i].qid; 2610 uint8_t idx = agg_status[i].idx; 2611 uint16_t txstatus = (le16toh(agg_status[i].status) & 2612 IWN_AGG_TX_STATUS_MASK); 2613 uint16_t trycnt = (le16toh(agg_status[i].status) & 2614 IWN_AGG_TX_TRY) >> IWN_AGG_TX_TRY_SHIFT; 2615 2616 if (qid != desc->qid) 2617 continue; 2618 2619 txdata = &txq->data[idx]; 2620 if (txdata->ni == NULL) 2621 continue; 2622 2623 if (rflags & IWN_RFLAG_MCS) 2624 txdata->ampdu_txmcs = rate; 2625 if (txstatus != IWN_AGG_TX_STATE_TRANSMITTED) 2626 txdata->txfail++; 2627 if (trycnt > 1) 2628 txdata->retries++; 2629 2630 /* 2631 * Assign a common ID to all subframes of this A-MPDU. 2632 * This ID will be used during Tx rate control to 2633 * infer the ACK status of individual subframes. 2634 */ 2635 if (!have_ampdu_id) { 2636 wn = (void *)txdata->ni; 2637 ampdu_id = wn->next_ampdu_id++; 2638 have_ampdu_id = 1; 2639 } 2640 txdata->ampdu_id = ampdu_id; 2641 2642 /* 2643 * We will also need to know the total number of 2644 * subframes and the size of this A-MPDU. We store 2645 * this redundantly on each subframe because firmware 2646 * only reports acknowledged subframes via compressed 2647 * block-ack notification. This way we will know what 2648 * the total number of subframes and size were even if 2649 * just one of these subframes gets acknowledged. 2650 */ 2651 txdata->ampdu_nframes = nframes; 2652 txdata->ampdu_size = ampdu_size; 2653 } 2654 return; 2655 } 2656 2657 if (ni == NULL) 2658 return; 2659 2660 ba = &ni->ni_tx_ba[tid]; 2661 if (ba->ba_state != IEEE80211_BA_AGREED) 2662 return; 2663 2664 /* This was a final single-frame Tx attempt for frame SSN-1. */ 2665 seq = (ssn - 1) & 0xfff; 2666 2667 /* 2668 * Skip rate control if our Tx rate is fixed. 2669 * Don't report frames to MiRA which were sent at a different 2670 * Tx rate than ni->ni_txmcs. 2671 */ 2672 if (ic->ic_fixed_mcs == -1 && txdata->txmcs == ni->ni_txmcs) { 2673 wn->mn.frames++; 2674 wn->mn.agglen = 1; 2675 wn->mn.ampdu_size = txdata->totlen + IEEE80211_CRC_LEN; 2676 if (ackfailcnt > 0) 2677 wn->mn.retries++; 2678 if (txfail) 2679 wn->mn.txfail++; 2680 iwn_mira_choose(sc, ni); 2681 } 2682 2683 if (txfail) 2684 ieee80211_tx_compressed_bar(ic, ni, tid, ssn); 2685 else if (!SEQ_LT(seq, ba->ba_winstart)) { 2686 /* 2687 * Move window forward if SEQ lies beyond end of window, 2688 * otherwise we can't record the ACK for this frame. 2689 * Non-acked frames which left holes in the bitmap near 2690 * the beginning of the window must be discarded. 2691 */ 2692 uint16_t s = seq; 2693 while (SEQ_LT(ba->ba_winend, s)) { 2694 ieee80211_output_ba_move_window(ic, ni, tid, s); 2695 iwn_ampdu_txq_advance(sc, txq, desc->qid, 2696 IWN_AGG_SSN_TO_TXQ_IDX(s)); 2697 s = (s + 1) % 0xfff; 2698 } 2699 /* SEQ should now be within window; set corresponding bit. */ 2700 ieee80211_output_ba_record_ack(ic, ni, tid, seq); 2701 } 2702 2703 /* Move window forward up to the first hole in the bitmap. */ 2704 ieee80211_output_ba_move_window_to_first_unacked(ic, ni, tid, ssn); 2705 iwn_ampdu_txq_advance(sc, txq, desc->qid, 2706 IWN_AGG_SSN_TO_TXQ_IDX(ba->ba_winstart)); 2707 2708 iwn_clear_oactive(sc, txq); 2709 } 2710 2711 /* 2712 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN 2713 * and 5000 adapters have different incompatible TX status formats. 2714 */ 2715 void 2716 iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2717 struct iwn_rx_data *data) 2718 { 2719 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1); 2720 struct iwn_tx_ring *ring; 2721 size_t len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK); 2722 uint16_t status = letoh32(stat->stat.status) & 0xff; 2723 uint32_t ssn; 2724 2725 if (desc->qid > IWN4965_NTXQUEUES) 2726 return; 2727 2728 ring = &sc->txq[desc->qid]; 2729 2730 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2731 len, BUS_DMASYNC_POSTREAD); 2732 2733 /* Sanity checks. */ 2734 if (sizeof(*stat) > len) 2735 return; 2736 if (stat->nframes < 1 || stat->nframes > IWN_AMPDU_MAX) 2737 return; 2738 if (desc->qid < sc->first_agg_txq && stat->nframes > 1) 2739 return; 2740 if (desc->qid >= sc->first_agg_txq && sizeof(*stat) + sizeof(ssn) + 2741 stat->nframes * sizeof(stat->stat) > len) 2742 return; 2743 2744 if (desc->qid < sc->first_agg_txq) { 2745 /* XXX 4965 does not report byte count */ 2746 struct iwn_tx_data *txdata = &ring->data[desc->idx]; 2747 uint16_t framelen = txdata->totlen + IEEE80211_CRC_LEN; 2748 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2749 status != IWN_TX_STATUS_DIRECT_DONE); 2750 2751 iwn_tx_done(sc, desc, stat->ackfailcnt, stat->rate, txfail, 2752 desc->qid, framelen); 2753 } else { 2754 memcpy(&ssn, &stat->stat.status + stat->nframes, sizeof(ssn)); 2755 ssn = le32toh(ssn) & 0xfff; 2756 iwn_ampdu_tx_done(sc, ring, desc, status, stat->ackfailcnt, 2757 stat->rate, stat->rflags, stat->nframes, ssn, 2758 stat->stat.agg_status); 2759 } 2760 } 2761 2762 void 2763 iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2764 struct iwn_rx_data *data) 2765 { 2766 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1); 2767 struct iwn_tx_ring *ring; 2768 size_t len = (letoh32(desc->len) & IWN_RX_DESC_LEN_MASK); 2769 uint16_t status = letoh32(stat->stat.status) & 0xff; 2770 uint32_t ssn; 2771 2772 if (desc->qid > IWN5000_NTXQUEUES) 2773 return; 2774 2775 ring = &sc->txq[desc->qid]; 2776 2777 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2778 sizeof (*stat), BUS_DMASYNC_POSTREAD); 2779 2780 /* Sanity checks. */ 2781 if (sizeof(*stat) > len) 2782 return; 2783 if (stat->nframes < 1 || stat->nframes > IWN_AMPDU_MAX) 2784 return; 2785 if (desc->qid < sc->first_agg_txq && stat->nframes > 1) 2786 return; 2787 if (desc->qid >= sc->first_agg_txq && sizeof(*stat) + sizeof(ssn) + 2788 stat->nframes * sizeof(stat->stat) > len) 2789 return; 2790 2791 /* If this was not an aggregated frame, complete it now. */ 2792 if (desc->qid < sc->first_agg_txq) { 2793 int txfail = (status != IWN_TX_STATUS_SUCCESS && 2794 status != IWN_TX_STATUS_DIRECT_DONE); 2795 2796 /* Reset TX scheduler slot. */ 2797 iwn5000_reset_sched(sc, desc->qid, desc->idx); 2798 2799 iwn_tx_done(sc, desc, stat->ackfailcnt, stat->rate, txfail, 2800 desc->qid, letoh16(stat->len)); 2801 } else { 2802 memcpy(&ssn, &stat->stat.status + stat->nframes, sizeof(ssn)); 2803 ssn = le32toh(ssn) & 0xfff; 2804 iwn_ampdu_tx_done(sc, ring, desc, status, stat->ackfailcnt, 2805 stat->rate, stat->rflags, stat->nframes, ssn, 2806 stat->stat.agg_status); 2807 } 2808 } 2809 2810 void 2811 iwn_tx_done_free_txdata(struct iwn_softc *sc, struct iwn_tx_data *data) 2812 { 2813 struct ieee80211com *ic = &sc->sc_ic; 2814 2815 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 2816 BUS_DMASYNC_POSTWRITE); 2817 bus_dmamap_unload(sc->sc_dmat, data->map); 2818 m_freem(data->m); 2819 data->m = NULL; 2820 ieee80211_release_node(ic, data->ni); 2821 data->ni = NULL; 2822 data->totlen = 0; 2823 data->retries = 0; 2824 data->txfail = 0; 2825 data->txmcs = 0; 2826 data->ampdu_txmcs = 0; 2827 data->txrate = 0; 2828 } 2829 2830 void 2831 iwn_clear_oactive(struct iwn_softc *sc, struct iwn_tx_ring *ring) 2832 { 2833 struct ieee80211com *ic = &sc->sc_ic; 2834 struct ifnet *ifp = &ic->ic_if; 2835 2836 if (ring->queued < IWN_TX_RING_LOMARK) { 2837 sc->qfullmsk &= ~(1 << ring->qid); 2838 if (sc->qfullmsk == 0 && ifq_is_oactive(&ifp->if_snd)) { 2839 ifq_clr_oactive(&ifp->if_snd); 2840 (*ifp->if_start)(ifp); 2841 } 2842 } 2843 } 2844 2845 /* 2846 * Adapter-independent backend for TX_DONE firmware notifications. 2847 * This handles Tx status for non-aggregation queues. 2848 */ 2849 void 2850 iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, 2851 uint8_t ackfailcnt, uint8_t rate, int txfail, int qid, uint16_t len) 2852 { 2853 struct ieee80211com *ic = &sc->sc_ic; 2854 struct ifnet *ifp = &ic->ic_if; 2855 struct iwn_tx_ring *ring = &sc->txq[qid]; 2856 struct iwn_tx_data *data = &ring->data[desc->idx]; 2857 struct iwn_node *wn = (void *)data->ni; 2858 2859 if (data->ni == NULL) 2860 return; 2861 2862 if (data->ni->ni_flags & IEEE80211_NODE_HT) { 2863 if (ic->ic_state == IEEE80211_S_RUN && 2864 ic->ic_fixed_mcs == -1 && 2865 data->txmcs == data->ni->ni_txmcs) { 2866 wn->mn.frames++; 2867 wn->mn.ampdu_size = len; 2868 wn->mn.agglen = 1; 2869 if (ackfailcnt > 0) 2870 wn->mn.retries++; 2871 if (txfail) 2872 wn->mn.txfail++; 2873 iwn_mira_choose(sc, data->ni); 2874 } 2875 } else if (data->txrate == data->ni->ni_txrate) { 2876 wn->amn.amn_txcnt++; 2877 if (ackfailcnt > 0) 2878 wn->amn.amn_retrycnt++; 2879 if (txfail) 2880 wn->amn.amn_retrycnt++; 2881 } 2882 if (txfail) 2883 ifp->if_oerrors++; 2884 2885 iwn_tx_done_free_txdata(sc, data); 2886 2887 sc->sc_tx_timer = 0; 2888 ring->queued--; 2889 iwn_clear_oactive(sc, ring); 2890 } 2891 2892 /* 2893 * Process a "command done" firmware notification. This is where we wakeup 2894 * processes waiting for a synchronous command completion. 2895 */ 2896 void 2897 iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc) 2898 { 2899 struct iwn_tx_ring *ring = &sc->txq[4]; 2900 struct iwn_tx_data *data; 2901 2902 if ((desc->qid & 0xf) != 4) 2903 return; /* Not a command ack. */ 2904 2905 data = &ring->data[desc->idx]; 2906 2907 /* If the command was mapped in an mbuf, free it. */ 2908 if (data->m != NULL) { 2909 bus_dmamap_sync(sc->sc_dmat, data->map, 0, 2910 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 2911 bus_dmamap_unload(sc->sc_dmat, data->map); 2912 m_freem(data->m); 2913 data->m = NULL; 2914 } 2915 wakeup(&ring->desc[desc->idx]); 2916 } 2917 2918 /* 2919 * Process an INT_FH_RX or INT_SW_RX interrupt. 2920 */ 2921 void 2922 iwn_notif_intr(struct iwn_softc *sc) 2923 { 2924 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 2925 struct iwn_ops *ops = &sc->ops; 2926 struct ieee80211com *ic = &sc->sc_ic; 2927 struct ifnet *ifp = &ic->ic_if; 2928 uint16_t hw; 2929 2930 bus_dmamap_sync(sc->sc_dmat, sc->rxq.stat_dma.map, 2931 0, sc->rxq.stat_dma.size, BUS_DMASYNC_POSTREAD); 2932 2933 hw = letoh16(sc->rxq.stat->closed_count) & 0xfff; 2934 while (sc->rxq.cur != hw) { 2935 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 2936 struct iwn_rx_desc *desc; 2937 2938 bus_dmamap_sync(sc->sc_dmat, data->map, 0, sizeof (*desc), 2939 BUS_DMASYNC_POSTREAD); 2940 desc = mtod(data->m, struct iwn_rx_desc *); 2941 2942 DPRINTFN(4, ("notification qid=%d idx=%d flags=%x type=%d\n", 2943 desc->qid & 0xf, desc->idx, desc->flags, desc->type)); 2944 2945 if (!(desc->qid & 0x80)) /* Reply to a command. */ 2946 iwn_cmd_done(sc, desc); 2947 2948 switch (desc->type) { 2949 case IWN_RX_PHY: 2950 iwn_rx_phy(sc, desc, data); 2951 break; 2952 2953 case IWN_RX_DONE: /* 4965AGN only. */ 2954 case IWN_MPDU_RX_DONE: 2955 /* An 802.11 frame has been received. */ 2956 iwn_rx_done(sc, desc, data, &ml); 2957 break; 2958 case IWN_RX_COMPRESSED_BA: 2959 /* A Compressed BlockAck has been received. */ 2960 iwn_rx_compressed_ba(sc, desc, data); 2961 break; 2962 case IWN_TX_DONE: 2963 /* An 802.11 frame has been transmitted. */ 2964 ops->tx_done(sc, desc, data); 2965 break; 2966 2967 case IWN_RX_STATISTICS: 2968 case IWN_BEACON_STATISTICS: 2969 iwn_rx_statistics(sc, desc, data); 2970 break; 2971 2972 case IWN_BEACON_MISSED: 2973 { 2974 struct iwn_beacon_missed *miss = 2975 (struct iwn_beacon_missed *)(desc + 1); 2976 uint32_t missed; 2977 2978 if ((ic->ic_opmode != IEEE80211_M_STA) || 2979 (ic->ic_state != IEEE80211_S_RUN)) 2980 break; 2981 2982 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 2983 sizeof (*miss), BUS_DMASYNC_POSTREAD); 2984 missed = letoh32(miss->consecutive); 2985 2986 /* 2987 * If more than 5 consecutive beacons are missed, 2988 * reinitialize the sensitivity state machine. 2989 */ 2990 if (missed > 5) 2991 (void)iwn_init_sensitivity(sc); 2992 2993 /* 2994 * Rather than go directly to scan state, try to send a 2995 * directed probe request first. If that fails then the 2996 * state machine will drop us into scanning after timing 2997 * out waiting for a probe response. 2998 */ 2999 if (missed > ic->ic_bmissthres && !ic->ic_mgt_timer) { 3000 if (ic->ic_if.if_flags & IFF_DEBUG) 3001 printf("%s: receiving no beacons from " 3002 "%s; checking if this AP is still " 3003 "responding to probe requests\n", 3004 sc->sc_dev.dv_xname, ether_sprintf( 3005 ic->ic_bss->ni_macaddr)); 3006 IEEE80211_SEND_MGMT(ic, ic->ic_bss, 3007 IEEE80211_FC0_SUBTYPE_PROBE_REQ, 0); 3008 } 3009 break; 3010 } 3011 case IWN_UC_READY: 3012 { 3013 struct iwn_ucode_info *uc = 3014 (struct iwn_ucode_info *)(desc + 1); 3015 3016 /* The microcontroller is ready. */ 3017 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 3018 sizeof (*uc), BUS_DMASYNC_POSTREAD); 3019 DPRINTF(("microcode alive notification version=%d.%d " 3020 "subtype=%x alive=%x\n", uc->major, uc->minor, 3021 uc->subtype, letoh32(uc->valid))); 3022 3023 if (letoh32(uc->valid) != 1) { 3024 printf("%s: microcontroller initialization " 3025 "failed\n", sc->sc_dev.dv_xname); 3026 break; 3027 } 3028 if (uc->subtype == IWN_UCODE_INIT) { 3029 /* Save microcontroller report. */ 3030 memcpy(&sc->ucode_info, uc, sizeof (*uc)); 3031 } 3032 /* Save the address of the error log in SRAM. */ 3033 sc->errptr = letoh32(uc->errptr); 3034 break; 3035 } 3036 case IWN_STATE_CHANGED: 3037 { 3038 uint32_t *status = (uint32_t *)(desc + 1); 3039 3040 /* Enabled/disabled notification. */ 3041 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 3042 sizeof (*status), BUS_DMASYNC_POSTREAD); 3043 DPRINTF(("state changed to %x\n", letoh32(*status))); 3044 3045 if (letoh32(*status) & 1) { 3046 /* Radio transmitter is off, power down. */ 3047 iwn_stop(ifp); 3048 return; /* No further processing. */ 3049 } 3050 break; 3051 } 3052 case IWN_START_SCAN: 3053 { 3054 struct iwn_start_scan *scan = 3055 (struct iwn_start_scan *)(desc + 1); 3056 3057 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 3058 sizeof (*scan), BUS_DMASYNC_POSTREAD); 3059 DPRINTFN(2, ("scan start: chan %d status %x\n", 3060 scan->chan, letoh32(scan->status))); 3061 3062 if (sc->sc_flags & IWN_FLAG_BGSCAN) 3063 break; 3064 3065 /* Fix current channel. */ 3066 ic->ic_bss->ni_chan = &ic->ic_channels[scan->chan]; 3067 break; 3068 } 3069 case IWN_STOP_SCAN: 3070 { 3071 struct iwn_stop_scan *scan = 3072 (struct iwn_stop_scan *)(desc + 1); 3073 3074 bus_dmamap_sync(sc->sc_dmat, data->map, sizeof (*desc), 3075 sizeof (*scan), BUS_DMASYNC_POSTREAD); 3076 DPRINTFN(2, ("scan stop: nchan=%d status=%d chan=%d\n", 3077 scan->nchan, scan->status, scan->chan)); 3078 3079 if (scan->status == 1 && scan->chan <= 14 && 3080 (sc->sc_flags & IWN_FLAG_HAS_5GHZ)) { 3081 int error; 3082 /* 3083 * We just finished scanning 2GHz channels, 3084 * start scanning 5GHz ones. 3085 */ 3086 error = iwn_scan(sc, IEEE80211_CHAN_5GHZ, 3087 (sc->sc_flags & IWN_FLAG_BGSCAN) ? 1 : 0); 3088 if (error == 0) 3089 break; 3090 } 3091 sc->sc_flags &= ~IWN_FLAG_SCANNING; 3092 sc->sc_flags &= ~IWN_FLAG_BGSCAN; 3093 ieee80211_end_scan(ifp); 3094 break; 3095 } 3096 case IWN5000_CALIBRATION_RESULT: 3097 iwn5000_rx_calib_results(sc, desc, data); 3098 break; 3099 3100 case IWN5000_CALIBRATION_DONE: 3101 sc->sc_flags |= IWN_FLAG_CALIB_DONE; 3102 wakeup(sc); 3103 break; 3104 } 3105 3106 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT; 3107 } 3108 if_input(&sc->sc_ic.ic_if, &ml); 3109 3110 /* Tell the firmware what we have processed. */ 3111 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1; 3112 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7); 3113 } 3114 3115 /* 3116 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up 3117 * from power-down sleep mode. 3118 */ 3119 void 3120 iwn_wakeup_intr(struct iwn_softc *sc) 3121 { 3122 int qid; 3123 3124 DPRINTF(("ucode wakeup from power-down sleep\n")); 3125 3126 /* Wakeup RX and TX rings. */ 3127 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7); 3128 for (qid = 0; qid < sc->ntxqs; qid++) { 3129 struct iwn_tx_ring *ring = &sc->txq[qid]; 3130 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur); 3131 } 3132 } 3133 3134 #ifdef IWN_DEBUG 3135 /* 3136 * Dump the error log of the firmware when a firmware panic occurs. Although 3137 * we can't debug the firmware because it is neither open source nor free, it 3138 * can help us to identify certain classes of problems. 3139 */ 3140 void 3141 iwn_fatal_intr(struct iwn_softc *sc) 3142 { 3143 struct iwn_fw_dump dump; 3144 int i; 3145 3146 /* Check that the error log address is valid. */ 3147 if (sc->errptr < IWN_FW_DATA_BASE || 3148 sc->errptr + sizeof (dump) > 3149 IWN_FW_DATA_BASE + sc->fw_data_maxsz) { 3150 printf("%s: bad firmware error log address 0x%08x\n", 3151 sc->sc_dev.dv_xname, sc->errptr); 3152 return; 3153 } 3154 if (iwn_nic_lock(sc) != 0) { 3155 printf("%s: could not read firmware error log\n", 3156 sc->sc_dev.dv_xname); 3157 return; 3158 } 3159 /* Read firmware error log from SRAM. */ 3160 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump, 3161 sizeof (dump) / sizeof (uint32_t)); 3162 iwn_nic_unlock(sc); 3163 3164 if (dump.valid == 0) { 3165 printf("%s: firmware error log is empty\n", 3166 sc->sc_dev.dv_xname); 3167 return; 3168 } 3169 printf("firmware error log:\n"); 3170 printf(" error type = \"%s\" (0x%08X)\n", 3171 (dump.id < nitems(iwn_fw_errmsg)) ? 3172 iwn_fw_errmsg[dump.id] : "UNKNOWN", 3173 dump.id); 3174 printf(" program counter = 0x%08X\n", dump.pc); 3175 printf(" source line = 0x%08X\n", dump.src_line); 3176 printf(" error data = 0x%08X%08X\n", 3177 dump.error_data[0], dump.error_data[1]); 3178 printf(" branch link = 0x%08X%08X\n", 3179 dump.branch_link[0], dump.branch_link[1]); 3180 printf(" interrupt link = 0x%08X%08X\n", 3181 dump.interrupt_link[0], dump.interrupt_link[1]); 3182 printf(" time = %u\n", dump.time[0]); 3183 3184 /* Dump driver status (TX and RX rings) while we're here. */ 3185 printf("driver status:\n"); 3186 for (i = 0; i < sc->ntxqs; i++) { 3187 struct iwn_tx_ring *ring = &sc->txq[i]; 3188 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n", 3189 i, ring->qid, ring->cur, ring->queued); 3190 } 3191 printf(" rx ring: cur=%d\n", sc->rxq.cur); 3192 printf(" 802.11 state %d\n", sc->sc_ic.ic_state); 3193 } 3194 #endif 3195 3196 int 3197 iwn_intr(void *arg) 3198 { 3199 struct iwn_softc *sc = arg; 3200 struct ifnet *ifp = &sc->sc_ic.ic_if; 3201 uint32_t r1, r2, tmp; 3202 3203 /* Disable interrupts. */ 3204 IWN_WRITE(sc, IWN_INT_MASK, 0); 3205 3206 /* Read interrupts from ICT (fast) or from registers (slow). */ 3207 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3208 tmp = 0; 3209 while (sc->ict[sc->ict_cur] != 0) { 3210 tmp |= sc->ict[sc->ict_cur]; 3211 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */ 3212 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT; 3213 } 3214 tmp = letoh32(tmp); 3215 if (tmp == 0xffffffff) /* Shouldn't happen. */ 3216 tmp = 0; 3217 else if (tmp & 0xc0000) /* Workaround a HW bug. */ 3218 tmp |= 0x8000; 3219 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff); 3220 r2 = 0; /* Unused. */ 3221 } else { 3222 r1 = IWN_READ(sc, IWN_INT); 3223 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0) 3224 return 0; /* Hardware gone! */ 3225 r2 = IWN_READ(sc, IWN_FH_INT); 3226 } 3227 if (r1 == 0 && r2 == 0) { 3228 if (ifp->if_flags & IFF_UP) 3229 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3230 return 0; /* Interrupt not for us. */ 3231 } 3232 3233 /* Acknowledge interrupts. */ 3234 IWN_WRITE(sc, IWN_INT, r1); 3235 if (!(sc->sc_flags & IWN_FLAG_USE_ICT)) 3236 IWN_WRITE(sc, IWN_FH_INT, r2); 3237 3238 if (r1 & IWN_INT_RF_TOGGLED) { 3239 tmp = IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL; 3240 printf("%s: RF switch: radio %s\n", sc->sc_dev.dv_xname, 3241 tmp ? "enabled" : "disabled"); 3242 if (tmp) 3243 task_add(systq, &sc->init_task); 3244 } 3245 if (r1 & IWN_INT_CT_REACHED) { 3246 printf("%s: critical temperature reached!\n", 3247 sc->sc_dev.dv_xname); 3248 } 3249 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) { 3250 printf("%s: fatal firmware error\n", sc->sc_dev.dv_xname); 3251 3252 /* Force a complete recalibration on next init. */ 3253 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE; 3254 3255 /* Dump firmware error log and stop. */ 3256 #ifdef IWN_DEBUG 3257 iwn_fatal_intr(sc); 3258 #endif 3259 iwn_stop(ifp); 3260 task_add(systq, &sc->init_task); 3261 return 1; 3262 } 3263 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) || 3264 (r2 & IWN_FH_INT_RX)) { 3265 if (sc->sc_flags & IWN_FLAG_USE_ICT) { 3266 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) 3267 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX); 3268 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3269 IWN_INT_PERIODIC_DIS); 3270 iwn_notif_intr(sc); 3271 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) { 3272 IWN_WRITE_1(sc, IWN_INT_PERIODIC, 3273 IWN_INT_PERIODIC_ENA); 3274 } 3275 } else 3276 iwn_notif_intr(sc); 3277 } 3278 3279 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) { 3280 if (sc->sc_flags & IWN_FLAG_USE_ICT) 3281 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX); 3282 wakeup(sc); /* FH DMA transfer completed. */ 3283 } 3284 3285 if (r1 & IWN_INT_ALIVE) 3286 wakeup(sc); /* Firmware is alive. */ 3287 3288 if (r1 & IWN_INT_WAKEUP) 3289 iwn_wakeup_intr(sc); 3290 3291 /* Re-enable interrupts. */ 3292 if (ifp->if_flags & IFF_UP) 3293 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 3294 3295 return 1; 3296 } 3297 3298 /* 3299 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and 3300 * 5000 adapters use a slightly different format). 3301 */ 3302 void 3303 iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3304 uint16_t len) 3305 { 3306 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx]; 3307 3308 *w = htole16(len + 8); 3309 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3310 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3311 BUS_DMASYNC_PREWRITE); 3312 if (idx < IWN_SCHED_WINSZ) { 3313 *(w + IWN_TX_RING_COUNT) = *w; 3314 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3315 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3316 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3317 } 3318 } 3319 3320 void 3321 iwn4965_reset_sched(struct iwn_softc *sc, int qid, int idx) 3322 { 3323 /* TBD */ 3324 } 3325 3326 void 3327 iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id, 3328 uint16_t len) 3329 { 3330 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3331 3332 *w = htole16(id << 12 | (len + 8)); 3333 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3334 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3335 BUS_DMASYNC_PREWRITE); 3336 if (idx < IWN_SCHED_WINSZ) { 3337 *(w + IWN_TX_RING_COUNT) = *w; 3338 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3339 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3340 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3341 } 3342 } 3343 3344 void 3345 iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx) 3346 { 3347 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx]; 3348 3349 *w = (*w & htole16(0xf000)) | htole16(1); 3350 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3351 (caddr_t)w - sc->sched_dma.vaddr, sizeof (uint16_t), 3352 BUS_DMASYNC_PREWRITE); 3353 if (idx < IWN_SCHED_WINSZ) { 3354 *(w + IWN_TX_RING_COUNT) = *w; 3355 bus_dmamap_sync(sc->sc_dmat, sc->sched_dma.map, 3356 (caddr_t)(w + IWN_TX_RING_COUNT) - sc->sched_dma.vaddr, 3357 sizeof (uint16_t), BUS_DMASYNC_PREWRITE); 3358 } 3359 } 3360 3361 int 3362 iwn_rval2ridx(int rval) 3363 { 3364 int ridx; 3365 3366 for (ridx = 0; ridx < nitems(iwn_rates); ridx++) { 3367 if (rval == iwn_rates[ridx].rate) 3368 break; 3369 } 3370 3371 return ridx; 3372 } 3373 3374 int 3375 iwn_tx(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 3376 { 3377 struct iwn_ops *ops = &sc->ops; 3378 struct ieee80211com *ic = &sc->sc_ic; 3379 struct iwn_node *wn = (void *)ni; 3380 struct iwn_tx_ring *ring; 3381 struct iwn_tx_desc *desc; 3382 struct iwn_tx_data *data; 3383 struct iwn_tx_cmd *cmd; 3384 struct iwn_cmd_data *tx; 3385 const struct iwn_rate *rinfo; 3386 struct ieee80211_frame *wh; 3387 struct ieee80211_key *k = NULL; 3388 enum ieee80211_edca_ac ac; 3389 int qid; 3390 uint32_t flags; 3391 uint16_t qos; 3392 u_int hdrlen; 3393 bus_dma_segment_t *seg; 3394 uint8_t *ivp, tid, ridx, txant, type, subtype; 3395 int i, totlen, hasqos, error, pad; 3396 3397 wh = mtod(m, struct ieee80211_frame *); 3398 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 3399 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3400 if (type == IEEE80211_FC0_TYPE_CTL) 3401 hdrlen = sizeof(struct ieee80211_frame_min); 3402 else 3403 hdrlen = ieee80211_get_hdrlen(wh); 3404 3405 if ((hasqos = ieee80211_has_qos(wh))) { 3406 /* Select EDCA Access Category and TX ring for this frame. */ 3407 struct ieee80211_tx_ba *ba; 3408 qos = ieee80211_get_qos(wh); 3409 tid = qos & IEEE80211_QOS_TID; 3410 ac = ieee80211_up_to_ac(ic, tid); 3411 qid = ac; 3412 3413 /* If possible, put this frame on an aggregation queue. */ 3414 if (sc->sc_tx_ba[tid].wn == wn) { 3415 ba = &ni->ni_tx_ba[tid]; 3416 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 3417 ba->ba_state == IEEE80211_BA_AGREED) { 3418 qid = sc->first_agg_txq + tid; 3419 if (sc->qfullmsk & (1 << qid)) { 3420 m_freem(m); 3421 return ENOBUFS; 3422 } 3423 } 3424 } 3425 } else { 3426 qos = 0; 3427 tid = IWN_NONQOS_TID; 3428 ac = EDCA_AC_BE; 3429 qid = ac; 3430 } 3431 3432 ring = &sc->txq[qid]; 3433 desc = &ring->desc[ring->cur]; 3434 data = &ring->data[ring->cur]; 3435 3436 /* Choose a TX rate index. */ 3437 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3438 type != IEEE80211_FC0_TYPE_DATA) 3439 ridx = iwn_rval2ridx(ieee80211_min_basic_rate(ic)); 3440 else if (ic->ic_fixed_mcs != -1) 3441 ridx = sc->fixed_ridx; 3442 else if (ic->ic_fixed_rate != -1) 3443 ridx = sc->fixed_ridx; 3444 else { 3445 if (ni->ni_flags & IEEE80211_NODE_HT) 3446 ridx = iwn_mcs2ridx[ni->ni_txmcs]; 3447 else 3448 ridx = wn->ridx[ni->ni_txrate]; 3449 } 3450 rinfo = &iwn_rates[ridx]; 3451 #if NBPFILTER > 0 3452 if (sc->sc_drvbpf != NULL) { 3453 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap; 3454 uint16_t chan_flags; 3455 3456 tap->wt_flags = 0; 3457 tap->wt_chan_freq = htole16(ni->ni_chan->ic_freq); 3458 chan_flags = ni->ni_chan->ic_flags; 3459 if (ic->ic_curmode != IEEE80211_MODE_11N) 3460 chan_flags &= ~IEEE80211_CHAN_HT; 3461 tap->wt_chan_flags = htole16(chan_flags); 3462 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3463 !IEEE80211_IS_MULTICAST(wh->i_addr1) && 3464 type == IEEE80211_FC0_TYPE_DATA) { 3465 tap->wt_rate = (0x80 | ni->ni_txmcs); 3466 } else 3467 tap->wt_rate = rinfo->rate; 3468 if ((ic->ic_flags & IEEE80211_F_WEPON) && 3469 (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)) 3470 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3471 3472 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, 3473 m, BPF_DIRECTION_OUT); 3474 } 3475 #endif 3476 3477 totlen = m->m_pkthdr.len; 3478 3479 /* Encrypt the frame if need be. */ 3480 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 3481 /* Retrieve key for TX. */ 3482 k = ieee80211_get_txkey(ic, wh, ni); 3483 if (k->k_cipher != IEEE80211_CIPHER_CCMP) { 3484 /* Do software encryption. */ 3485 if ((m = ieee80211_encrypt(ic, m, k)) == NULL) 3486 return ENOBUFS; 3487 /* 802.11 header may have moved. */ 3488 wh = mtod(m, struct ieee80211_frame *); 3489 totlen = m->m_pkthdr.len; 3490 3491 } else /* HW appends CCMP MIC. */ 3492 totlen += IEEE80211_CCMP_HDRLEN; 3493 } 3494 3495 data->totlen = totlen; 3496 3497 /* Prepare TX firmware command. */ 3498 cmd = &ring->cmd[ring->cur]; 3499 cmd->code = IWN_CMD_TX_DATA; 3500 cmd->flags = 0; 3501 cmd->qid = ring->qid; 3502 cmd->idx = ring->cur; 3503 3504 tx = (struct iwn_cmd_data *)cmd->data; 3505 /* NB: No need to clear tx, all fields are reinitialized here. */ 3506 tx->scratch = 0; /* clear "scratch" area */ 3507 3508 flags = 0; 3509 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3510 /* Unicast frame, check if an ACK is expected. */ 3511 if (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) != 3512 IEEE80211_QOS_ACK_POLICY_NOACK) 3513 flags |= IWN_TX_NEED_ACK; 3514 } 3515 if (type == IEEE80211_FC0_TYPE_CTL && 3516 subtype == IEEE80211_FC0_SUBTYPE_BAR) { 3517 struct ieee80211_frame_min *mwh; 3518 uint8_t *barfrm; 3519 uint16_t ctl; 3520 mwh = mtod(m, struct ieee80211_frame_min *); 3521 barfrm = (uint8_t *)&mwh[1]; 3522 ctl = LE_READ_2(barfrm); 3523 tid = (ctl & IEEE80211_BA_TID_INFO_MASK) >> 3524 IEEE80211_BA_TID_INFO_SHIFT; 3525 flags |= (IWN_TX_NEED_ACK | IWN_TX_IMM_BA); 3526 } 3527 3528 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 3529 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */ 3530 3531 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */ 3532 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 3533 int rtsthres = ic->ic_rtsthreshold; 3534 if (ni->ni_flags & IEEE80211_NODE_HT) 3535 rtsthres = ieee80211_mira_get_rts_threshold(&wn->mn, 3536 ic, ni, totlen + IEEE80211_CRC_LEN); 3537 3538 /* NB: Group frames are sent using CCK in 802.11b/g/n (2GHz). */ 3539 if (totlen + IEEE80211_CRC_LEN > rtsthres) { 3540 flags |= IWN_TX_NEED_RTS; 3541 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3542 ridx >= IWN_RIDX_OFDM6) { 3543 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3544 flags |= IWN_TX_NEED_CTS; 3545 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3546 flags |= IWN_TX_NEED_RTS; 3547 } 3548 3549 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) { 3550 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 3551 /* 5000 autoselects RTS/CTS or CTS-to-self. */ 3552 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS); 3553 flags |= IWN_TX_NEED_PROTECTION; 3554 } else 3555 flags |= IWN_TX_FULL_TXOP; 3556 } 3557 } 3558 3559 if (IEEE80211_IS_MULTICAST(wh->i_addr1) || 3560 type != IEEE80211_FC0_TYPE_DATA) 3561 tx->id = sc->broadcast_id; 3562 else 3563 tx->id = wn->id; 3564 3565 if (type == IEEE80211_FC0_TYPE_MGT) { 3566 #ifndef IEEE80211_STA_ONLY 3567 /* Tell HW to set timestamp in probe responses. */ 3568 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3569 flags |= IWN_TX_INSERT_TSTAMP; 3570 #endif 3571 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ || 3572 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ) 3573 tx->timeout = htole16(3); 3574 else 3575 tx->timeout = htole16(2); 3576 } else 3577 tx->timeout = htole16(0); 3578 3579 if (hdrlen & 3) { 3580 /* First segment length must be a multiple of 4. */ 3581 flags |= IWN_TX_NEED_PADDING; 3582 pad = 4 - (hdrlen & 3); 3583 } else 3584 pad = 0; 3585 3586 tx->len = htole16(totlen); 3587 tx->tid = tid; 3588 tx->rts_ntries = 60; 3589 tx->data_ntries = 15; 3590 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 3591 3592 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3593 tx->id != sc->broadcast_id) 3594 tx->plcp = rinfo->ht_plcp; 3595 else 3596 tx->plcp = rinfo->plcp; 3597 3598 if ((ni->ni_flags & IEEE80211_NODE_HT) && 3599 tx->id != sc->broadcast_id) { 3600 tx->rflags = rinfo->ht_flags; 3601 if (ni->ni_htcaps & IEEE80211_HTCAP_SGI20) 3602 tx->rflags |= IWN_RFLAG_SGI; 3603 } 3604 else 3605 tx->rflags = rinfo->flags; 3606 /* 3607 * Keep the Tx rate constant while mira is probing, or if this is 3608 * an aggregation queue in which case a fixed Tx rate works around 3609 * FIFO_UNDERRUN Tx errors. 3610 */ 3611 if (tx->id == sc->broadcast_id || ieee80211_mira_is_probing(&wn->mn) || 3612 qid >= sc->first_agg_txq || 3613 ic->ic_fixed_mcs != -1 || ic->ic_fixed_rate != -1) { 3614 /* Group or management frame, or probing, or fixed Tx rate. */ 3615 tx->linkq = 0; 3616 /* XXX Alternate between antenna A and B? */ 3617 txant = IWN_LSB(sc->txchainmask); 3618 tx->rflags |= IWN_RFLAG_ANT(txant); 3619 } else { 3620 tx->linkq = 0; /* initial index into firmware LQ retry table */ 3621 flags |= IWN_TX_LINKQ; /* enable multi-rate retry */ 3622 } 3623 /* Set physical address of "scratch area". */ 3624 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr)); 3625 tx->hiaddr = IWN_HIADDR(data->scratch_paddr); 3626 3627 /* Copy 802.11 header in TX command. */ 3628 memcpy((uint8_t *)(tx + 1), wh, hdrlen); 3629 3630 if (k != NULL && k->k_cipher == IEEE80211_CIPHER_CCMP) { 3631 /* Trim 802.11 header and prepend CCMP IV. */ 3632 m_adj(m, hdrlen - IEEE80211_CCMP_HDRLEN); 3633 ivp = mtod(m, uint8_t *); 3634 k->k_tsc++; 3635 ivp[0] = k->k_tsc; 3636 ivp[1] = k->k_tsc >> 8; 3637 ivp[2] = 0; 3638 ivp[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3639 ivp[4] = k->k_tsc >> 16; 3640 ivp[5] = k->k_tsc >> 24; 3641 ivp[6] = k->k_tsc >> 32; 3642 ivp[7] = k->k_tsc >> 40; 3643 3644 tx->security = IWN_CIPHER_CCMP; 3645 if (qid >= sc->first_agg_txq) 3646 flags |= IWN_TX_AMPDU_CCMP; 3647 memcpy(tx->key, k->k_key, k->k_len); 3648 3649 /* TX scheduler includes CCMP MIC len w/5000 Series. */ 3650 if (sc->hw_type != IWN_HW_REV_TYPE_4965) 3651 totlen += IEEE80211_CCMP_MICLEN; 3652 } else { 3653 /* Trim 802.11 header. */ 3654 m_adj(m, hdrlen); 3655 tx->security = 0; 3656 } 3657 tx->flags = htole32(flags); 3658 3659 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3660 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3661 if (error != 0 && error != EFBIG) { 3662 printf("%s: can't map mbuf (error %d)\n", 3663 sc->sc_dev.dv_xname, error); 3664 m_freem(m); 3665 return error; 3666 } 3667 if (error != 0) { 3668 /* Too many DMA segments, linearize mbuf. */ 3669 if (m_defrag(m, M_DONTWAIT)) { 3670 m_freem(m); 3671 return ENOBUFS; 3672 } 3673 error = bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, 3674 BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3675 if (error != 0) { 3676 printf("%s: can't map mbuf (error %d)\n", 3677 sc->sc_dev.dv_xname, error); 3678 m_freem(m); 3679 return error; 3680 } 3681 } 3682 3683 data->m = m; 3684 data->ni = ni; 3685 data->txmcs = ni->ni_txmcs; 3686 data->txrate = ni->ni_txrate; 3687 data->ampdu_txmcs = ni->ni_txmcs; /* updated upon Tx interrupt */ 3688 3689 DPRINTFN(4, ("sending data: qid=%d idx=%d len=%d nsegs=%d\n", 3690 ring->qid, ring->cur, m->m_pkthdr.len, data->map->dm_nsegs)); 3691 3692 /* Fill TX descriptor. */ 3693 desc->nsegs = 1 + data->map->dm_nsegs; 3694 /* First DMA segment is used by the TX command. */ 3695 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr)); 3696 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) | 3697 (4 + sizeof (*tx) + hdrlen + pad) << 4); 3698 /* Other DMA segments are for data payload. */ 3699 seg = data->map->dm_segs; 3700 for (i = 1; i <= data->map->dm_nsegs; i++) { 3701 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr)); 3702 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) | 3703 seg->ds_len << 4); 3704 seg++; 3705 } 3706 3707 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize, 3708 BUS_DMASYNC_PREWRITE); 3709 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3710 (caddr_t)cmd - ring->cmd_dma.vaddr, sizeof (*cmd), 3711 BUS_DMASYNC_PREWRITE); 3712 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3713 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 3714 BUS_DMASYNC_PREWRITE); 3715 3716 /* Update TX scheduler. */ 3717 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen); 3718 3719 /* Kick TX ring. */ 3720 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3721 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3722 3723 /* Mark TX ring as full if we reach a certain threshold. */ 3724 if (++ring->queued > IWN_TX_RING_HIMARK) 3725 sc->qfullmsk |= 1 << ring->qid; 3726 3727 return 0; 3728 } 3729 3730 void 3731 iwn_start(struct ifnet *ifp) 3732 { 3733 struct iwn_softc *sc = ifp->if_softc; 3734 struct ieee80211com *ic = &sc->sc_ic; 3735 struct ieee80211_node *ni; 3736 struct mbuf *m; 3737 3738 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 3739 return; 3740 3741 for (;;) { 3742 if (sc->qfullmsk != 0) { 3743 ifq_set_oactive(&ifp->if_snd); 3744 break; 3745 } 3746 3747 /* Send pending management frames first. */ 3748 m = mq_dequeue(&ic->ic_mgtq); 3749 if (m != NULL) { 3750 ni = m->m_pkthdr.ph_cookie; 3751 goto sendit; 3752 } 3753 if (ic->ic_state != IEEE80211_S_RUN || 3754 (ic->ic_xflags & IEEE80211_F_TX_MGMT_ONLY)) 3755 break; 3756 3757 /* Encapsulate and send data frames. */ 3758 m = ifq_dequeue(&ifp->if_snd); 3759 if (m == NULL) 3760 break; 3761 #if NBPFILTER > 0 3762 if (ifp->if_bpf != NULL) 3763 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 3764 #endif 3765 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 3766 continue; 3767 sendit: 3768 #if NBPFILTER > 0 3769 if (ic->ic_rawbpf != NULL) 3770 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 3771 #endif 3772 if (iwn_tx(sc, m, ni) != 0) { 3773 ieee80211_release_node(ic, ni); 3774 ifp->if_oerrors++; 3775 continue; 3776 } 3777 3778 sc->sc_tx_timer = 5; 3779 ifp->if_timer = 1; 3780 } 3781 } 3782 3783 void 3784 iwn_watchdog(struct ifnet *ifp) 3785 { 3786 struct iwn_softc *sc = ifp->if_softc; 3787 3788 ifp->if_timer = 0; 3789 3790 if (sc->sc_tx_timer > 0) { 3791 if (--sc->sc_tx_timer == 0) { 3792 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 3793 iwn_stop(ifp); 3794 ifp->if_oerrors++; 3795 return; 3796 } 3797 ifp->if_timer = 1; 3798 } 3799 3800 ieee80211_watchdog(ifp); 3801 } 3802 3803 int 3804 iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3805 { 3806 struct iwn_softc *sc = ifp->if_softc; 3807 struct ieee80211com *ic = &sc->sc_ic; 3808 int s, error = 0; 3809 3810 error = rw_enter(&sc->sc_rwlock, RW_WRITE | RW_INTR); 3811 if (error) 3812 return error; 3813 s = splnet(); 3814 3815 switch (cmd) { 3816 case SIOCSIFADDR: 3817 ifp->if_flags |= IFF_UP; 3818 /* FALLTHROUGH */ 3819 case SIOCSIFFLAGS: 3820 if (ifp->if_flags & IFF_UP) { 3821 if (!(ifp->if_flags & IFF_RUNNING)) 3822 error = iwn_init(ifp); 3823 } else { 3824 if (ifp->if_flags & IFF_RUNNING) 3825 iwn_stop(ifp); 3826 } 3827 break; 3828 3829 case SIOCS80211POWER: 3830 error = ieee80211_ioctl(ifp, cmd, data); 3831 if (error != ENETRESET) 3832 break; 3833 if (ic->ic_state == IEEE80211_S_RUN && 3834 sc->calib.state == IWN_CALIB_STATE_RUN) { 3835 if (ic->ic_flags & IEEE80211_F_PMGTON) 3836 error = iwn_set_pslevel(sc, 0, 3, 0); 3837 else /* back to CAM */ 3838 error = iwn_set_pslevel(sc, 0, 0, 0); 3839 } else { 3840 /* Defer until transition to IWN_CALIB_STATE_RUN. */ 3841 error = 0; 3842 } 3843 break; 3844 3845 default: 3846 error = ieee80211_ioctl(ifp, cmd, data); 3847 } 3848 3849 if (error == ENETRESET) { 3850 error = 0; 3851 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 3852 (IFF_UP | IFF_RUNNING)) { 3853 iwn_stop(ifp); 3854 error = iwn_init(ifp); 3855 } 3856 } 3857 3858 splx(s); 3859 rw_exit_write(&sc->sc_rwlock); 3860 return error; 3861 } 3862 3863 /* 3864 * Send a command to the firmware. 3865 */ 3866 int 3867 iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async) 3868 { 3869 struct iwn_ops *ops = &sc->ops; 3870 struct iwn_tx_ring *ring = &sc->txq[4]; 3871 struct iwn_tx_desc *desc; 3872 struct iwn_tx_data *data; 3873 struct iwn_tx_cmd *cmd; 3874 struct mbuf *m; 3875 bus_addr_t paddr; 3876 int totlen, error; 3877 3878 desc = &ring->desc[ring->cur]; 3879 data = &ring->data[ring->cur]; 3880 totlen = 4 + size; 3881 3882 if (size > sizeof cmd->data) { 3883 /* Command is too large to fit in a descriptor. */ 3884 if (totlen > MCLBYTES) 3885 return EINVAL; 3886 MGETHDR(m, M_DONTWAIT, MT_DATA); 3887 if (m == NULL) 3888 return ENOMEM; 3889 if (totlen > MHLEN) { 3890 MCLGET(m, M_DONTWAIT); 3891 if (!(m->m_flags & M_EXT)) { 3892 m_freem(m); 3893 return ENOMEM; 3894 } 3895 } 3896 cmd = mtod(m, struct iwn_tx_cmd *); 3897 error = bus_dmamap_load(sc->sc_dmat, data->map, cmd, totlen, 3898 NULL, BUS_DMA_NOWAIT | BUS_DMA_WRITE); 3899 if (error != 0) { 3900 m_freem(m); 3901 return error; 3902 } 3903 data->m = m; 3904 paddr = data->map->dm_segs[0].ds_addr; 3905 } else { 3906 cmd = &ring->cmd[ring->cur]; 3907 paddr = data->cmd_paddr; 3908 } 3909 3910 cmd->code = code; 3911 cmd->flags = 0; 3912 cmd->qid = ring->qid; 3913 cmd->idx = ring->cur; 3914 memcpy(cmd->data, buf, size); 3915 3916 desc->nsegs = 1; 3917 desc->segs[0].addr = htole32(IWN_LOADDR(paddr)); 3918 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4); 3919 3920 if (size > sizeof cmd->data) { 3921 bus_dmamap_sync(sc->sc_dmat, data->map, 0, totlen, 3922 BUS_DMASYNC_PREWRITE); 3923 } else { 3924 bus_dmamap_sync(sc->sc_dmat, ring->cmd_dma.map, 3925 (caddr_t)cmd - ring->cmd_dma.vaddr, totlen, 3926 BUS_DMASYNC_PREWRITE); 3927 } 3928 bus_dmamap_sync(sc->sc_dmat, ring->desc_dma.map, 3929 (caddr_t)desc - ring->desc_dma.vaddr, sizeof (*desc), 3930 BUS_DMASYNC_PREWRITE); 3931 3932 /* Update TX scheduler. */ 3933 ops->update_sched(sc, ring->qid, ring->cur, 0, 0); 3934 3935 /* Kick command ring. */ 3936 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT; 3937 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur); 3938 3939 return async ? 0 : tsleep_nsec(desc, PCATCH, "iwncmd", SEC_TO_NSEC(1)); 3940 } 3941 3942 int 3943 iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3944 { 3945 struct iwn4965_node_info hnode; 3946 caddr_t src, dst; 3947 3948 /* 3949 * We use the node structure for 5000 Series internally (it is 3950 * a superset of the one for 4965AGN). We thus copy the common 3951 * fields before sending the command. 3952 */ 3953 src = (caddr_t)node; 3954 dst = (caddr_t)&hnode; 3955 memcpy(dst, src, 48); 3956 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */ 3957 memcpy(dst + 48, src + 72, 20); 3958 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async); 3959 } 3960 3961 int 3962 iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async) 3963 { 3964 /* Direct mapping. */ 3965 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async); 3966 } 3967 3968 int 3969 iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni) 3970 { 3971 struct ieee80211com *ic = &sc->sc_ic; 3972 struct iwn_node *wn = (void *)ni; 3973 struct iwn_cmd_link_quality linkq; 3974 const struct iwn_rate *rinfo; 3975 uint8_t txant; 3976 int i; 3977 3978 /* Use the first valid TX antenna. */ 3979 txant = IWN_LSB(sc->txchainmask); 3980 3981 memset(&linkq, 0, sizeof linkq); 3982 linkq.id = wn->id; 3983 linkq.antmsk_1stream = txant; 3984 linkq.antmsk_2stream = IWN_ANT_AB; 3985 linkq.ampdu_max = IWN_AMPDU_MAX; 3986 linkq.ampdu_threshold = 3; 3987 linkq.ampdu_limit = htole16(4000); /* 4ms */ 3988 3989 i = 0; 3990 if (ni->ni_flags & IEEE80211_NODE_HT) { 3991 int txmcs; 3992 for (txmcs = ni->ni_txmcs; txmcs >= 0; txmcs--) { 3993 rinfo = &iwn_rates[iwn_mcs2ridx[txmcs]]; 3994 linkq.retry[i].plcp = rinfo->ht_plcp; 3995 linkq.retry[i].rflags = rinfo->ht_flags; 3996 3997 if (ni->ni_htcaps & IEEE80211_HTCAP_SGI20) 3998 linkq.retry[i].rflags |= IWN_RFLAG_SGI; 3999 4000 /* XXX set correct ant mask for MIMO rates here */ 4001 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 4002 4003 if (++i >= IWN_MAX_TX_RETRIES) 4004 break; 4005 } 4006 } else { 4007 int txrate; 4008 for (txrate = ni->ni_txrate; txrate >= 0; txrate--) { 4009 rinfo = &iwn_rates[wn->ridx[txrate]]; 4010 linkq.retry[i].plcp = rinfo->plcp; 4011 linkq.retry[i].rflags = rinfo->flags; 4012 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 4013 if (++i >= IWN_MAX_TX_RETRIES) 4014 break; 4015 } 4016 } 4017 4018 /* Fill the rest with the lowest basic rate. */ 4019 rinfo = &iwn_rates[iwn_rval2ridx(ieee80211_min_basic_rate(ic))]; 4020 while (i < IWN_MAX_TX_RETRIES) { 4021 linkq.retry[i].plcp = rinfo->plcp; 4022 linkq.retry[i].rflags = rinfo->flags; 4023 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant); 4024 i++; 4025 } 4026 4027 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1); 4028 } 4029 4030 /* 4031 * Broadcast node is used to send group-addressed and management frames. 4032 */ 4033 int 4034 iwn_add_broadcast_node(struct iwn_softc *sc, int async, int ridx) 4035 { 4036 struct iwn_ops *ops = &sc->ops; 4037 struct iwn_node_info node; 4038 struct iwn_cmd_link_quality linkq; 4039 const struct iwn_rate *rinfo; 4040 uint8_t txant; 4041 int i, error; 4042 4043 memset(&node, 0, sizeof node); 4044 IEEE80211_ADDR_COPY(node.macaddr, etherbroadcastaddr); 4045 node.id = sc->broadcast_id; 4046 DPRINTF(("adding broadcast node\n")); 4047 if ((error = ops->add_node(sc, &node, async)) != 0) 4048 return error; 4049 4050 /* Use the first valid TX antenna. */ 4051 txant = IWN_LSB(sc->txchainmask); 4052 4053 memset(&linkq, 0, sizeof linkq); 4054 linkq.id = sc->broadcast_id; 4055 linkq.antmsk_1stream = txant; 4056 linkq.antmsk_2stream = IWN_ANT_AB; 4057 linkq.ampdu_max = IWN_AMPDU_MAX_NO_AGG; 4058 linkq.ampdu_threshold = 3; 4059 linkq.ampdu_limit = htole16(4000); /* 4ms */ 4060 4061 /* Use lowest mandatory bit-rate. */ 4062 rinfo = &iwn_rates[ridx]; 4063 linkq.retry[0].plcp = rinfo->plcp; 4064 linkq.retry[0].rflags = rinfo->flags; 4065 linkq.retry[0].rflags |= IWN_RFLAG_ANT(txant); 4066 /* Use same bit-rate for all TX retries. */ 4067 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) { 4068 linkq.retry[i].plcp = linkq.retry[0].plcp; 4069 linkq.retry[i].rflags = linkq.retry[0].rflags; 4070 } 4071 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async); 4072 } 4073 4074 void 4075 iwn_updateedca(struct ieee80211com *ic) 4076 { 4077 #define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */ 4078 struct iwn_softc *sc = ic->ic_softc; 4079 struct iwn_edca_params cmd; 4080 int aci; 4081 4082 memset(&cmd, 0, sizeof cmd); 4083 cmd.flags = htole32(IWN_EDCA_UPDATE); 4084 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 4085 const struct ieee80211_edca_ac_params *ac = 4086 &ic->ic_edca_ac[aci]; 4087 cmd.ac[aci].aifsn = ac->ac_aifsn; 4088 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->ac_ecwmin)); 4089 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->ac_ecwmax)); 4090 cmd.ac[aci].txoplimit = 4091 htole16(IEEE80211_TXOP_TO_US(ac->ac_txoplimit)); 4092 } 4093 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1); 4094 #undef IWN_EXP2 4095 } 4096 4097 void 4098 iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on) 4099 { 4100 struct iwn_cmd_led led; 4101 4102 /* Clear microcode LED ownership. */ 4103 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL); 4104 4105 led.which = which; 4106 led.unit = htole32(10000); /* on/off in unit of 100ms */ 4107 led.off = off; 4108 led.on = on; 4109 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1); 4110 } 4111 4112 /* 4113 * Set the critical temperature at which the firmware will stop the radio 4114 * and notify us. 4115 */ 4116 int 4117 iwn_set_critical_temp(struct iwn_softc *sc) 4118 { 4119 struct iwn_critical_temp crit; 4120 int32_t temp; 4121 4122 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF); 4123 4124 if (sc->hw_type == IWN_HW_REV_TYPE_5150) 4125 temp = (IWN_CTOK(110) - sc->temp_off) * -5; 4126 else if (sc->hw_type == IWN_HW_REV_TYPE_4965) 4127 temp = IWN_CTOK(110); 4128 else 4129 temp = 110; 4130 memset(&crit, 0, sizeof crit); 4131 crit.tempR = htole32(temp); 4132 DPRINTF(("setting critical temperature to %d\n", temp)); 4133 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0); 4134 } 4135 4136 int 4137 iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni) 4138 { 4139 struct iwn_cmd_timing cmd; 4140 uint64_t val, mod; 4141 4142 memset(&cmd, 0, sizeof cmd); 4143 memcpy(&cmd.tstamp, ni->ni_tstamp, sizeof (uint64_t)); 4144 cmd.bintval = htole16(ni->ni_intval); 4145 cmd.lintval = htole16(10); 4146 4147 /* Compute remaining time until next beacon. */ 4148 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU; 4149 mod = letoh64(cmd.tstamp) % val; 4150 cmd.binitval = htole32((uint32_t)(val - mod)); 4151 4152 DPRINTF(("timing bintval=%u, tstamp=%llu, init=%u\n", 4153 ni->ni_intval, letoh64(cmd.tstamp), (uint32_t)(val - mod))); 4154 4155 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1); 4156 } 4157 4158 void 4159 iwn4965_power_calibration(struct iwn_softc *sc, int temp) 4160 { 4161 /* Adjust TX power if need be (delta >= 3 degC). */ 4162 DPRINTF(("temperature %d->%d\n", sc->temp, temp)); 4163 if (abs(temp - sc->temp) >= 3) { 4164 /* Record temperature of last calibration. */ 4165 sc->temp = temp; 4166 (void)iwn4965_set_txpower(sc, 1); 4167 } 4168 } 4169 4170 /* 4171 * Set TX power for current channel (each rate has its own power settings). 4172 * This function takes into account the regulatory information from EEPROM, 4173 * the current temperature and the current voltage. 4174 */ 4175 int 4176 iwn4965_set_txpower(struct iwn_softc *sc, int async) 4177 { 4178 /* Fixed-point arithmetic division using a n-bit fractional part. */ 4179 #define fdivround(a, b, n) \ 4180 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n)) 4181 /* Linear interpolation. */ 4182 #define interpolate(x, x1, y1, x2, y2, n) \ 4183 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n)) 4184 4185 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 }; 4186 struct ieee80211com *ic = &sc->sc_ic; 4187 struct iwn_ucode_info *uc = &sc->ucode_info; 4188 struct ieee80211_channel *ch; 4189 struct iwn4965_cmd_txpower cmd; 4190 struct iwn4965_eeprom_chan_samples *chans; 4191 const uint8_t *rf_gain, *dsp_gain; 4192 int32_t vdiff, tdiff; 4193 int i, c, grp, maxpwr; 4194 uint8_t chan; 4195 4196 /* Retrieve current channel from last RXON. */ 4197 chan = sc->rxon.chan; 4198 DPRINTF(("setting TX power for channel %d\n", chan)); 4199 ch = &ic->ic_channels[chan]; 4200 4201 memset(&cmd, 0, sizeof cmd); 4202 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1; 4203 cmd.chan = chan; 4204 4205 if (IEEE80211_IS_CHAN_5GHZ(ch)) { 4206 maxpwr = sc->maxpwr5GHz; 4207 rf_gain = iwn4965_rf_gain_5ghz; 4208 dsp_gain = iwn4965_dsp_gain_5ghz; 4209 } else { 4210 maxpwr = sc->maxpwr2GHz; 4211 rf_gain = iwn4965_rf_gain_2ghz; 4212 dsp_gain = iwn4965_dsp_gain_2ghz; 4213 } 4214 4215 /* Compute voltage compensation. */ 4216 vdiff = ((int32_t)letoh32(uc->volt) - sc->eeprom_voltage) / 7; 4217 if (vdiff > 0) 4218 vdiff *= 2; 4219 if (abs(vdiff) > 2) 4220 vdiff = 0; 4221 DPRINTF(("voltage compensation=%d (UCODE=%d, EEPROM=%d)\n", 4222 vdiff, letoh32(uc->volt), sc->eeprom_voltage)); 4223 4224 /* Get channel attenuation group. */ 4225 if (chan <= 20) /* 1-20 */ 4226 grp = 4; 4227 else if (chan <= 43) /* 34-43 */ 4228 grp = 0; 4229 else if (chan <= 70) /* 44-70 */ 4230 grp = 1; 4231 else if (chan <= 124) /* 71-124 */ 4232 grp = 2; 4233 else /* 125-200 */ 4234 grp = 3; 4235 DPRINTF(("chan %d, attenuation group=%d\n", chan, grp)); 4236 4237 /* Get channel sub-band. */ 4238 for (i = 0; i < IWN_NBANDS; i++) 4239 if (sc->bands[i].lo != 0 && 4240 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi) 4241 break; 4242 if (i == IWN_NBANDS) /* Can't happen in real-life. */ 4243 return EINVAL; 4244 chans = sc->bands[i].chans; 4245 DPRINTF(("chan %d sub-band=%d\n", chan, i)); 4246 4247 for (c = 0; c < 2; c++) { 4248 uint8_t power, gain, temp; 4249 int maxchpwr, pwr, ridx, idx; 4250 4251 power = interpolate(chan, 4252 chans[0].num, chans[0].samples[c][1].power, 4253 chans[1].num, chans[1].samples[c][1].power, 1); 4254 gain = interpolate(chan, 4255 chans[0].num, chans[0].samples[c][1].gain, 4256 chans[1].num, chans[1].samples[c][1].gain, 1); 4257 temp = interpolate(chan, 4258 chans[0].num, chans[0].samples[c][1].temp, 4259 chans[1].num, chans[1].samples[c][1].temp, 1); 4260 DPRINTF(("TX chain %d: power=%d gain=%d temp=%d\n", 4261 c, power, gain, temp)); 4262 4263 /* Compute temperature compensation. */ 4264 tdiff = ((sc->temp - temp) * 2) / tdiv[grp]; 4265 DPRINTF(("temperature compensation=%d (current=%d, " 4266 "EEPROM=%d)\n", tdiff, sc->temp, temp)); 4267 4268 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) { 4269 /* Convert dBm to half-dBm. */ 4270 maxchpwr = sc->maxpwr[chan] * 2; 4271 #ifdef notyet 4272 if (ridx > iwn_mcs2ridx[7] && ridx < iwn_mcs2ridx[16]) 4273 maxchpwr -= 6; /* MIMO 2T: -3dB */ 4274 #endif 4275 4276 pwr = maxpwr; 4277 4278 /* Adjust TX power based on rate. */ 4279 if ((ridx % 8) == 5) 4280 pwr -= 15; /* OFDM48: -7.5dB */ 4281 else if ((ridx % 8) == 6) 4282 pwr -= 17; /* OFDM54: -8.5dB */ 4283 else if ((ridx % 8) == 7) 4284 pwr -= 20; /* OFDM60: -10dB */ 4285 else 4286 pwr -= 10; /* Others: -5dB */ 4287 4288 /* Do not exceed channel max TX power. */ 4289 if (pwr > maxchpwr) 4290 pwr = maxchpwr; 4291 4292 idx = gain - (pwr - power) - tdiff - vdiff; 4293 if (ridx > iwn_mcs2ridx[7]) /* MIMO */ 4294 idx += (int32_t)letoh32(uc->atten[grp][c]); 4295 4296 if (cmd.band == 0) 4297 idx += 9; /* 5GHz */ 4298 if (ridx == IWN_RIDX_MAX) 4299 idx += 5; /* CCK */ 4300 4301 /* Make sure idx stays in a valid range. */ 4302 if (idx < 0) 4303 idx = 0; 4304 else if (idx > IWN4965_MAX_PWR_INDEX) 4305 idx = IWN4965_MAX_PWR_INDEX; 4306 4307 DPRINTF(("TX chain %d, rate idx %d: power=%d\n", 4308 c, ridx, idx)); 4309 cmd.power[ridx].rf_gain[c] = rf_gain[idx]; 4310 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx]; 4311 } 4312 } 4313 4314 DPRINTF(("setting TX power for chan %d\n", chan)); 4315 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async); 4316 4317 #undef interpolate 4318 #undef fdivround 4319 } 4320 4321 int 4322 iwn5000_set_txpower(struct iwn_softc *sc, int async) 4323 { 4324 struct iwn5000_cmd_txpower cmd; 4325 4326 /* 4327 * TX power calibration is handled automatically by the firmware 4328 * for 5000 Series. 4329 */ 4330 memset(&cmd, 0, sizeof cmd); 4331 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */ 4332 cmd.flags = IWN5000_TXPOWER_NO_CLOSED; 4333 cmd.srv_limit = IWN5000_TXPOWER_AUTO; 4334 DPRINTF(("setting TX power\n")); 4335 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async); 4336 } 4337 4338 /* 4339 * Retrieve the maximum RSSI (in dBm) among receivers. 4340 */ 4341 int 4342 iwn4965_get_rssi(const struct iwn_rx_stat *stat) 4343 { 4344 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf; 4345 uint8_t mask, agc; 4346 int rssi; 4347 4348 mask = (letoh16(phy->antenna) >> 4) & IWN_ANT_ABC; 4349 agc = (letoh16(phy->agc) >> 7) & 0x7f; 4350 4351 rssi = 0; 4352 if (mask & IWN_ANT_A) 4353 rssi = MAX(rssi, phy->rssi[0]); 4354 if (mask & IWN_ANT_B) 4355 rssi = MAX(rssi, phy->rssi[2]); 4356 if (mask & IWN_ANT_C) 4357 rssi = MAX(rssi, phy->rssi[4]); 4358 4359 return rssi - agc - IWN_RSSI_TO_DBM; 4360 } 4361 4362 int 4363 iwn5000_get_rssi(const struct iwn_rx_stat *stat) 4364 { 4365 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf; 4366 uint8_t agc; 4367 int rssi; 4368 4369 agc = (letoh32(phy->agc) >> 9) & 0x7f; 4370 4371 rssi = MAX(letoh16(phy->rssi[0]) & 0xff, 4372 letoh16(phy->rssi[1]) & 0xff); 4373 rssi = MAX(letoh16(phy->rssi[2]) & 0xff, rssi); 4374 4375 return rssi - agc - IWN_RSSI_TO_DBM; 4376 } 4377 4378 /* 4379 * Retrieve the average noise (in dBm) among receivers. 4380 */ 4381 int 4382 iwn_get_noise(const struct iwn_rx_general_stats *stats) 4383 { 4384 int i, total, nbant, noise; 4385 4386 total = nbant = 0; 4387 for (i = 0; i < 3; i++) { 4388 if ((noise = letoh32(stats->noise[i]) & 0xff) == 0) 4389 continue; 4390 total += noise; 4391 nbant++; 4392 } 4393 /* There should be at least one antenna but check anyway. */ 4394 return (nbant == 0) ? -127 : (total / nbant) - 107; 4395 } 4396 4397 /* 4398 * Compute temperature (in degC) from last received statistics. 4399 */ 4400 int 4401 iwn4965_get_temperature(struct iwn_softc *sc) 4402 { 4403 struct iwn_ucode_info *uc = &sc->ucode_info; 4404 int32_t r1, r2, r3, r4, temp; 4405 4406 r1 = letoh32(uc->temp[0].chan20MHz); 4407 r2 = letoh32(uc->temp[1].chan20MHz); 4408 r3 = letoh32(uc->temp[2].chan20MHz); 4409 r4 = letoh32(sc->rawtemp); 4410 4411 if (r1 == r3) /* Prevents division by 0 (should not happen). */ 4412 return 0; 4413 4414 /* Sign-extend 23-bit R4 value to 32-bit. */ 4415 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000; 4416 /* Compute temperature in Kelvin. */ 4417 temp = (259 * (r4 - r2)) / (r3 - r1); 4418 temp = (temp * 97) / 100 + 8; 4419 4420 DPRINTF(("temperature %dK/%dC\n", temp, IWN_KTOC(temp))); 4421 return IWN_KTOC(temp); 4422 } 4423 4424 int 4425 iwn5000_get_temperature(struct iwn_softc *sc) 4426 { 4427 int32_t temp; 4428 4429 /* 4430 * Temperature is not used by the driver for 5000 Series because 4431 * TX power calibration is handled by firmware. 4432 */ 4433 temp = letoh32(sc->rawtemp); 4434 if (sc->hw_type == IWN_HW_REV_TYPE_5150) { 4435 temp = (temp / -5) + sc->temp_off; 4436 temp = IWN_KTOC(temp); 4437 } 4438 return temp; 4439 } 4440 4441 /* 4442 * Initialize sensitivity calibration state machine. 4443 */ 4444 int 4445 iwn_init_sensitivity(struct iwn_softc *sc) 4446 { 4447 struct iwn_ops *ops = &sc->ops; 4448 struct iwn_calib_state *calib = &sc->calib; 4449 uint32_t flags; 4450 int error; 4451 4452 /* Reset calibration state machine. */ 4453 memset(calib, 0, sizeof (*calib)); 4454 calib->state = IWN_CALIB_STATE_INIT; 4455 calib->cck_state = IWN_CCK_STATE_HIFA; 4456 /* Set initial correlation values. */ 4457 calib->ofdm_x1 = sc->limits->min_ofdm_x1; 4458 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1; 4459 calib->ofdm_x4 = sc->limits->min_ofdm_x4; 4460 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4; 4461 calib->cck_x4 = 125; 4462 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4; 4463 calib->energy_cck = sc->limits->energy_cck; 4464 4465 /* Write initial sensitivity. */ 4466 if ((error = iwn_send_sensitivity(sc)) != 0) 4467 return error; 4468 4469 /* Write initial gains. */ 4470 if ((error = ops->init_gains(sc)) != 0) 4471 return error; 4472 4473 /* Request statistics at each beacon interval. */ 4474 flags = 0; 4475 DPRINTFN(2, ("sending request for statistics\n")); 4476 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1); 4477 } 4478 4479 /* 4480 * Collect noise and RSSI statistics for the first 20 beacons received 4481 * after association and use them to determine connected antennas and 4482 * to set differential gains. 4483 */ 4484 void 4485 iwn_collect_noise(struct iwn_softc *sc, 4486 const struct iwn_rx_general_stats *stats) 4487 { 4488 struct iwn_ops *ops = &sc->ops; 4489 struct iwn_calib_state *calib = &sc->calib; 4490 uint32_t val; 4491 int i; 4492 4493 /* Accumulate RSSI and noise for all 3 antennas. */ 4494 for (i = 0; i < 3; i++) { 4495 calib->rssi[i] += letoh32(stats->rssi[i]) & 0xff; 4496 calib->noise[i] += letoh32(stats->noise[i]) & 0xff; 4497 } 4498 /* NB: We update differential gains only once after 20 beacons. */ 4499 if (++calib->nbeacons < 20) 4500 return; 4501 4502 /* Determine highest average RSSI. */ 4503 val = MAX(calib->rssi[0], calib->rssi[1]); 4504 val = MAX(calib->rssi[2], val); 4505 4506 /* Determine which antennas are connected. */ 4507 sc->chainmask = sc->rxchainmask; 4508 for (i = 0; i < 3; i++) 4509 if (val - calib->rssi[i] > 15 * 20) 4510 sc->chainmask &= ~(1 << i); 4511 DPRINTF(("RX chains mask: theoretical=0x%x, actual=0x%x\n", 4512 sc->rxchainmask, sc->chainmask)); 4513 4514 /* If none of the TX antennas are connected, keep at least one. */ 4515 if ((sc->chainmask & sc->txchainmask) == 0) 4516 sc->chainmask |= IWN_LSB(sc->txchainmask); 4517 4518 (void)ops->set_gains(sc); 4519 calib->state = IWN_CALIB_STATE_RUN; 4520 4521 #ifdef notyet 4522 /* XXX Disable RX chains with no antennas connected. */ 4523 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask)); 4524 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 4525 #endif 4526 4527 /* Enable power-saving mode if requested by user. */ 4528 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON) 4529 (void)iwn_set_pslevel(sc, 0, 3, 1); 4530 } 4531 4532 int 4533 iwn4965_init_gains(struct iwn_softc *sc) 4534 { 4535 struct iwn_phy_calib_gain cmd; 4536 4537 memset(&cmd, 0, sizeof cmd); 4538 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4539 /* Differential gains initially set to 0 for all 3 antennas. */ 4540 DPRINTF(("setting initial differential gains\n")); 4541 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4542 } 4543 4544 int 4545 iwn5000_init_gains(struct iwn_softc *sc) 4546 { 4547 struct iwn_phy_calib cmd; 4548 4549 memset(&cmd, 0, sizeof cmd); 4550 cmd.code = sc->reset_noise_gain; 4551 cmd.ngroups = 1; 4552 cmd.isvalid = 1; 4553 DPRINTF(("setting initial differential gains\n")); 4554 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4555 } 4556 4557 int 4558 iwn4965_set_gains(struct iwn_softc *sc) 4559 { 4560 struct iwn_calib_state *calib = &sc->calib; 4561 struct iwn_phy_calib_gain cmd; 4562 int i, delta, noise; 4563 4564 /* Get minimal noise among connected antennas. */ 4565 noise = INT_MAX; /* NB: There's at least one antenna. */ 4566 for (i = 0; i < 3; i++) 4567 if (sc->chainmask & (1 << i)) 4568 noise = MIN(calib->noise[i], noise); 4569 4570 memset(&cmd, 0, sizeof cmd); 4571 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN; 4572 /* Set differential gains for connected antennas. */ 4573 for (i = 0; i < 3; i++) { 4574 if (sc->chainmask & (1 << i)) { 4575 /* Compute attenuation (in unit of 1.5dB). */ 4576 delta = (noise - (int32_t)calib->noise[i]) / 30; 4577 /* NB: delta <= 0 */ 4578 /* Limit to [-4.5dB,0]. */ 4579 cmd.gain[i] = MIN(abs(delta), 3); 4580 if (delta < 0) 4581 cmd.gain[i] |= 1 << 2; /* sign bit */ 4582 } 4583 } 4584 DPRINTF(("setting differential gains Ant A/B/C: %x/%x/%x (%x)\n", 4585 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask)); 4586 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4587 } 4588 4589 int 4590 iwn5000_set_gains(struct iwn_softc *sc) 4591 { 4592 struct iwn_calib_state *calib = &sc->calib; 4593 struct iwn_phy_calib_gain cmd; 4594 int i, ant, div, delta; 4595 4596 /* We collected 20 beacons and !=6050 need a 1.5 factor. */ 4597 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30; 4598 4599 memset(&cmd, 0, sizeof cmd); 4600 cmd.code = sc->noise_gain; 4601 cmd.ngroups = 1; 4602 cmd.isvalid = 1; 4603 /* 4604 * Get first available RX antenna as referential. 4605 * IWN_LSB() return values start with 1, but antenna gain array 4606 * cmd.gain[] and noise array calib->noise[] start with 0. 4607 */ 4608 ant = IWN_LSB(sc->rxchainmask) - 1; 4609 4610 /* Set differential gains for other antennas. */ 4611 for (i = ant + 1; i < 3; i++) { 4612 if (sc->chainmask & (1 << i)) { 4613 /* The delta is relative to antenna "ant". */ 4614 delta = ((int32_t)calib->noise[ant] - 4615 (int32_t)calib->noise[i]) / div; 4616 DPRINTF(("Ant[%d] vs. Ant[%d]: delta %d\n", ant, i, delta)); 4617 /* Limit to [-4.5dB,+4.5dB]. */ 4618 cmd.gain[i] = MIN(abs(delta), 3); 4619 if (delta < 0) 4620 cmd.gain[i] |= 1 << 2; /* sign bit */ 4621 DPRINTF(("Setting differential gains for antenna %d: %x\n", 4622 i, cmd.gain[i])); 4623 } 4624 } 4625 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1); 4626 } 4627 4628 /* 4629 * Tune RF RX sensitivity based on the number of false alarms detected 4630 * during the last beacon period. 4631 */ 4632 void 4633 iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats) 4634 { 4635 #define inc(val, inc, max) \ 4636 if ((val) < (max)) { \ 4637 if ((val) < (max) - (inc)) \ 4638 (val) += (inc); \ 4639 else \ 4640 (val) = (max); \ 4641 needs_update = 1; \ 4642 } 4643 #define dec(val, dec, min) \ 4644 if ((val) > (min)) { \ 4645 if ((val) > (min) + (dec)) \ 4646 (val) -= (dec); \ 4647 else \ 4648 (val) = (min); \ 4649 needs_update = 1; \ 4650 } 4651 4652 const struct iwn_sensitivity_limits *limits = sc->limits; 4653 struct iwn_calib_state *calib = &sc->calib; 4654 uint32_t val, rxena, fa; 4655 uint32_t energy[3], energy_min; 4656 uint8_t noise[3], noise_ref; 4657 int i, needs_update = 0; 4658 4659 /* Check that we've been enabled long enough. */ 4660 if ((rxena = letoh32(stats->general.load)) == 0) 4661 return; 4662 4663 /* Compute number of false alarms since last call for OFDM. */ 4664 fa = letoh32(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm; 4665 fa += letoh32(stats->ofdm.fa) - calib->fa_ofdm; 4666 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4667 4668 /* Save counters values for next call. */ 4669 calib->bad_plcp_ofdm = letoh32(stats->ofdm.bad_plcp); 4670 calib->fa_ofdm = letoh32(stats->ofdm.fa); 4671 4672 if (fa > 50 * rxena) { 4673 /* High false alarm count, decrease sensitivity. */ 4674 DPRINTFN(2, ("OFDM high false alarm count: %u\n", fa)); 4675 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1); 4676 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1); 4677 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4); 4678 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4); 4679 4680 } else if (fa < 5 * rxena) { 4681 /* Low false alarm count, increase sensitivity. */ 4682 DPRINTFN(2, ("OFDM low false alarm count: %u\n", fa)); 4683 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1); 4684 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1); 4685 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4); 4686 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4); 4687 } 4688 4689 /* Compute maximum noise among 3 receivers. */ 4690 for (i = 0; i < 3; i++) 4691 noise[i] = (letoh32(stats->general.noise[i]) >> 8) & 0xff; 4692 val = MAX(noise[0], noise[1]); 4693 val = MAX(noise[2], val); 4694 /* Insert it into our samples table. */ 4695 calib->noise_samples[calib->cur_noise_sample] = val; 4696 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20; 4697 4698 /* Compute maximum noise among last 20 samples. */ 4699 noise_ref = calib->noise_samples[0]; 4700 for (i = 1; i < 20; i++) 4701 noise_ref = MAX(noise_ref, calib->noise_samples[i]); 4702 4703 /* Compute maximum energy among 3 receivers. */ 4704 for (i = 0; i < 3; i++) 4705 energy[i] = letoh32(stats->general.energy[i]); 4706 val = MIN(energy[0], energy[1]); 4707 val = MIN(energy[2], val); 4708 /* Insert it into our samples table. */ 4709 calib->energy_samples[calib->cur_energy_sample] = val; 4710 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10; 4711 4712 /* Compute minimum energy among last 10 samples. */ 4713 energy_min = calib->energy_samples[0]; 4714 for (i = 1; i < 10; i++) 4715 energy_min = MAX(energy_min, calib->energy_samples[i]); 4716 energy_min += 6; 4717 4718 /* Compute number of false alarms since last call for CCK. */ 4719 fa = letoh32(stats->cck.bad_plcp) - calib->bad_plcp_cck; 4720 fa += letoh32(stats->cck.fa) - calib->fa_cck; 4721 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */ 4722 4723 /* Save counters values for next call. */ 4724 calib->bad_plcp_cck = letoh32(stats->cck.bad_plcp); 4725 calib->fa_cck = letoh32(stats->cck.fa); 4726 4727 if (fa > 50 * rxena) { 4728 /* High false alarm count, decrease sensitivity. */ 4729 DPRINTFN(2, ("CCK high false alarm count: %u\n", fa)); 4730 calib->cck_state = IWN_CCK_STATE_HIFA; 4731 calib->low_fa = 0; 4732 4733 if (calib->cck_x4 > 160) { 4734 calib->noise_ref = noise_ref; 4735 if (calib->energy_cck > 2) 4736 dec(calib->energy_cck, 2, energy_min); 4737 } 4738 if (calib->cck_x4 < 160) { 4739 calib->cck_x4 = 161; 4740 needs_update = 1; 4741 } else 4742 inc(calib->cck_x4, 3, limits->max_cck_x4); 4743 4744 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4); 4745 4746 } else if (fa < 5 * rxena) { 4747 /* Low false alarm count, increase sensitivity. */ 4748 DPRINTFN(2, ("CCK low false alarm count: %u\n", fa)); 4749 calib->cck_state = IWN_CCK_STATE_LOFA; 4750 calib->low_fa++; 4751 4752 if (calib->cck_state != IWN_CCK_STATE_INIT && 4753 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 || 4754 calib->low_fa > 100)) { 4755 inc(calib->energy_cck, 2, limits->min_energy_cck); 4756 dec(calib->cck_x4, 3, limits->min_cck_x4); 4757 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4); 4758 } 4759 } else { 4760 /* Not worth to increase or decrease sensitivity. */ 4761 DPRINTFN(2, ("CCK normal false alarm count: %u\n", fa)); 4762 calib->low_fa = 0; 4763 calib->noise_ref = noise_ref; 4764 4765 if (calib->cck_state == IWN_CCK_STATE_HIFA) { 4766 /* Previous interval had many false alarms. */ 4767 dec(calib->energy_cck, 8, energy_min); 4768 } 4769 calib->cck_state = IWN_CCK_STATE_INIT; 4770 } 4771 4772 if (needs_update) 4773 (void)iwn_send_sensitivity(sc); 4774 #undef dec 4775 #undef inc 4776 } 4777 4778 int 4779 iwn_send_sensitivity(struct iwn_softc *sc) 4780 { 4781 struct iwn_calib_state *calib = &sc->calib; 4782 struct iwn_enhanced_sensitivity_cmd cmd; 4783 int len; 4784 4785 memset(&cmd, 0, sizeof cmd); 4786 len = sizeof (struct iwn_sensitivity_cmd); 4787 cmd.which = IWN_SENSITIVITY_WORKTBL; 4788 /* OFDM modulation. */ 4789 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1); 4790 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1); 4791 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4); 4792 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4); 4793 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm); 4794 cmd.energy_ofdm_th = htole16(62); 4795 /* CCK modulation. */ 4796 cmd.corr_cck_x4 = htole16(calib->cck_x4); 4797 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4); 4798 cmd.energy_cck = htole16(calib->energy_cck); 4799 /* Barker modulation: use default values. */ 4800 cmd.corr_barker = htole16(190); 4801 cmd.corr_barker_mrc = htole16(390); 4802 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS)) 4803 goto send; 4804 /* Enhanced sensitivity settings. */ 4805 len = sizeof (struct iwn_enhanced_sensitivity_cmd); 4806 cmd.ofdm_det_slope_mrc = htole16(668); 4807 cmd.ofdm_det_icept_mrc = htole16(4); 4808 cmd.ofdm_det_slope = htole16(486); 4809 cmd.ofdm_det_icept = htole16(37); 4810 cmd.cck_det_slope_mrc = htole16(853); 4811 cmd.cck_det_icept_mrc = htole16(4); 4812 cmd.cck_det_slope = htole16(476); 4813 cmd.cck_det_icept = htole16(99); 4814 send: 4815 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1); 4816 } 4817 4818 /* 4819 * Set STA mode power saving level (between 0 and 5). 4820 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving. 4821 */ 4822 int 4823 iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async) 4824 { 4825 struct iwn_pmgt_cmd cmd; 4826 const struct iwn_pmgt *pmgt; 4827 uint32_t max, skip_dtim; 4828 pcireg_t reg; 4829 int i; 4830 4831 /* Select which PS parameters to use. */ 4832 if (dtim <= 2) 4833 pmgt = &iwn_pmgt[0][level]; 4834 else if (dtim <= 10) 4835 pmgt = &iwn_pmgt[1][level]; 4836 else 4837 pmgt = &iwn_pmgt[2][level]; 4838 4839 memset(&cmd, 0, sizeof cmd); 4840 if (level != 0) /* not CAM */ 4841 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP); 4842 if (level == 5) 4843 cmd.flags |= htole16(IWN_PS_FAST_PD); 4844 /* Retrieve PCIe Active State Power Management (ASPM). */ 4845 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 4846 sc->sc_cap_off + PCI_PCIE_LCSR); 4847 if (!(reg & PCI_PCIE_LCSR_ASPM_L0S)) /* L0s Entry disabled. */ 4848 cmd.flags |= htole16(IWN_PS_PCI_PMGT); 4849 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024); 4850 cmd.txtimeout = htole32(pmgt->txtimeout * 1024); 4851 4852 if (dtim == 0) { 4853 dtim = 1; 4854 skip_dtim = 0; 4855 } else 4856 skip_dtim = pmgt->skip_dtim; 4857 if (skip_dtim != 0) { 4858 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM); 4859 max = pmgt->intval[4]; 4860 if (max == (uint32_t)-1) 4861 max = dtim * (skip_dtim + 1); 4862 else if (max > dtim) 4863 max = (max / dtim) * dtim; 4864 } else 4865 max = dtim; 4866 for (i = 0; i < 5; i++) 4867 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i])); 4868 4869 DPRINTF(("setting power saving level to %d\n", level)); 4870 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async); 4871 } 4872 4873 int 4874 iwn_send_btcoex(struct iwn_softc *sc) 4875 { 4876 struct iwn_bluetooth cmd; 4877 4878 memset(&cmd, 0, sizeof cmd); 4879 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO; 4880 cmd.lead_time = IWN_BT_LEAD_TIME_DEF; 4881 cmd.max_kill = IWN_BT_MAX_KILL_DEF; 4882 DPRINTF(("configuring bluetooth coexistence\n")); 4883 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0); 4884 } 4885 4886 int 4887 iwn_send_advanced_btcoex(struct iwn_softc *sc) 4888 { 4889 static const uint32_t btcoex_3wire[12] = { 4890 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa, 4891 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa, 4892 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000, 4893 }; 4894 struct iwn_btcoex_priotable btprio; 4895 struct iwn_btcoex_prot btprot; 4896 int error, i; 4897 4898 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 4899 sc->hw_type == IWN_HW_REV_TYPE_135) { 4900 struct iwn2000_btcoex_config btconfig; 4901 4902 memset(&btconfig, 0, sizeof btconfig); 4903 btconfig.flags = IWN_BT_COEX6000_CHAN_INHIBITION | 4904 (IWN_BT_COEX6000_MODE_3W << IWN_BT_COEX6000_MODE_SHIFT) | 4905 IWN_BT_SYNC_2_BT_DISABLE; 4906 btconfig.max_kill = 5; 4907 btconfig.bt3_t7_timer = 1; 4908 btconfig.kill_ack = htole32(0xffff0000); 4909 btconfig.kill_cts = htole32(0xffff0000); 4910 btconfig.sample_time = 2; 4911 btconfig.bt3_t2_timer = 0xc; 4912 for (i = 0; i < 12; i++) 4913 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4914 btconfig.valid = htole16(0xff); 4915 btconfig.prio_boost = htole32(0xf0); 4916 DPRINTF(("configuring advanced bluetooth coexistence\n")); 4917 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 4918 sizeof(btconfig), 1); 4919 if (error != 0) 4920 return (error); 4921 } else { 4922 struct iwn6000_btcoex_config btconfig; 4923 4924 memset(&btconfig, 0, sizeof btconfig); 4925 btconfig.flags = IWN_BT_COEX6000_CHAN_INHIBITION | 4926 (IWN_BT_COEX6000_MODE_3W << IWN_BT_COEX6000_MODE_SHIFT) | 4927 IWN_BT_SYNC_2_BT_DISABLE; 4928 btconfig.max_kill = 5; 4929 btconfig.bt3_t7_timer = 1; 4930 btconfig.kill_ack = htole32(0xffff0000); 4931 btconfig.kill_cts = htole32(0xffff0000); 4932 btconfig.sample_time = 2; 4933 btconfig.bt3_t2_timer = 0xc; 4934 for (i = 0; i < 12; i++) 4935 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]); 4936 btconfig.valid = htole16(0xff); 4937 btconfig.prio_boost = 0xf0; 4938 DPRINTF(("configuring advanced bluetooth coexistence\n")); 4939 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, 4940 sizeof(btconfig), 1); 4941 if (error != 0) 4942 return (error); 4943 } 4944 4945 memset(&btprio, 0, sizeof btprio); 4946 btprio.calib_init1 = 0x6; 4947 btprio.calib_init2 = 0x7; 4948 btprio.calib_periodic_low1 = 0x2; 4949 btprio.calib_periodic_low2 = 0x3; 4950 btprio.calib_periodic_high1 = 0x4; 4951 btprio.calib_periodic_high2 = 0x5; 4952 btprio.dtim = 0x6; 4953 btprio.scan52 = 0x8; 4954 btprio.scan24 = 0xa; 4955 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio), 4956 1); 4957 if (error != 0) 4958 return (error); 4959 4960 /* Force BT state machine change */ 4961 memset(&btprot, 0, sizeof btprot); 4962 btprot.open = 1; 4963 btprot.type = 1; 4964 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1); 4965 if (error != 0) 4966 return (error); 4967 4968 btprot.open = 0; 4969 return (iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1)); 4970 } 4971 4972 int 4973 iwn5000_runtime_calib(struct iwn_softc *sc) 4974 { 4975 struct iwn5000_calib_config cmd; 4976 4977 memset(&cmd, 0, sizeof cmd); 4978 cmd.ucode.once.enable = 0xffffffff; 4979 cmd.ucode.once.start = IWN5000_CALIB_DC; 4980 DPRINTF(("configuring runtime calibration\n")); 4981 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0); 4982 } 4983 4984 int 4985 iwn_config(struct iwn_softc *sc) 4986 { 4987 struct iwn_ops *ops = &sc->ops; 4988 struct ieee80211com *ic = &sc->sc_ic; 4989 struct ifnet *ifp = &ic->ic_if; 4990 uint32_t txmask; 4991 uint16_t rxchain; 4992 int error, ridx; 4993 4994 /* Set radio temperature sensor offset. */ 4995 if (sc->hw_type == IWN_HW_REV_TYPE_6005) { 4996 error = iwn6000_temp_offset_calib(sc); 4997 if (error != 0) { 4998 printf("%s: could not set temperature offset\n", 4999 sc->sc_dev.dv_xname); 5000 return error; 5001 } 5002 } 5003 5004 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 5005 sc->hw_type == IWN_HW_REV_TYPE_2000 || 5006 sc->hw_type == IWN_HW_REV_TYPE_135 || 5007 sc->hw_type == IWN_HW_REV_TYPE_105) { 5008 error = iwn2000_temp_offset_calib(sc); 5009 if (error != 0) { 5010 printf("%s: could not set temperature offset\n", 5011 sc->sc_dev.dv_xname); 5012 return error; 5013 } 5014 } 5015 5016 if (sc->hw_type == IWN_HW_REV_TYPE_6050 || 5017 sc->hw_type == IWN_HW_REV_TYPE_6005) { 5018 /* Configure runtime DC calibration. */ 5019 error = iwn5000_runtime_calib(sc); 5020 if (error != 0) { 5021 printf("%s: could not configure runtime calibration\n", 5022 sc->sc_dev.dv_xname); 5023 return error; 5024 } 5025 } 5026 5027 /* Configure valid TX chains for >=5000 Series. */ 5028 if (sc->hw_type != IWN_HW_REV_TYPE_4965) { 5029 txmask = htole32(sc->txchainmask); 5030 DPRINTF(("configuring valid TX chains 0x%x\n", txmask)); 5031 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask, 5032 sizeof txmask, 0); 5033 if (error != 0) { 5034 printf("%s: could not configure valid TX chains\n", 5035 sc->sc_dev.dv_xname); 5036 return error; 5037 } 5038 } 5039 5040 /* Configure bluetooth coexistence. */ 5041 if (sc->sc_flags & IWN_FLAG_ADV_BT_COEX) 5042 error = iwn_send_advanced_btcoex(sc); 5043 else 5044 error = iwn_send_btcoex(sc); 5045 if (error != 0) { 5046 printf("%s: could not configure bluetooth coexistence\n", 5047 sc->sc_dev.dv_xname); 5048 return error; 5049 } 5050 5051 /* Set mode, channel, RX filter and enable RX. */ 5052 memset(&sc->rxon, 0, sizeof (struct iwn_rxon)); 5053 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 5054 IEEE80211_ADDR_COPY(sc->rxon.myaddr, ic->ic_myaddr); 5055 IEEE80211_ADDR_COPY(sc->rxon.wlap, ic->ic_myaddr); 5056 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); 5057 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5058 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_ibss_chan)) { 5059 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5060 if (ic->ic_flags & IEEE80211_F_USEPROT) 5061 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 5062 DPRINTF(("%s: 2ghz prot 0x%x\n", __func__, 5063 le32toh(sc->rxon.flags))); 5064 } 5065 switch (ic->ic_opmode) { 5066 case IEEE80211_M_STA: 5067 sc->rxon.mode = IWN_MODE_STA; 5068 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST); 5069 break; 5070 case IEEE80211_M_MONITOR: 5071 sc->rxon.mode = IWN_MODE_MONITOR; 5072 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST | 5073 IWN_FILTER_CTL | IWN_FILTER_PROMISC); 5074 break; 5075 default: 5076 /* Should not get there. */ 5077 break; 5078 } 5079 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */ 5080 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */ 5081 sc->rxon.ht_single_mask = 0xff; 5082 sc->rxon.ht_dual_mask = 0xff; 5083 sc->rxon.ht_triple_mask = 0xff; 5084 rxchain = 5085 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5086 IWN_RXCHAIN_MIMO_COUNT(sc->nrxchains) | 5087 IWN_RXCHAIN_IDLE_COUNT(sc->nrxchains); 5088 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5089 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5090 rxchain |= IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask); 5091 rxchain |= (IWN_RXCHAIN_DRIVER_FORCE | IWN_RXCHAIN_MIMO_FORCE); 5092 } 5093 sc->rxon.rxchain = htole16(rxchain); 5094 DPRINTF(("setting configuration\n")); 5095 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x rxchain %x\n", 5096 __func__, sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5097 sc->rxon.ofdm_mask, sc->rxon.rxchain)); 5098 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0); 5099 if (error != 0) { 5100 printf("%s: RXON command failed\n", sc->sc_dev.dv_xname); 5101 return error; 5102 } 5103 5104 ridx = (sc->sc_ic.ic_curmode == IEEE80211_MODE_11A) ? 5105 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 5106 if ((error = iwn_add_broadcast_node(sc, 0, ridx)) != 0) { 5107 printf("%s: could not add broadcast node\n", 5108 sc->sc_dev.dv_xname); 5109 return error; 5110 } 5111 5112 /* Configuration has changed, set TX power accordingly. */ 5113 if ((error = ops->set_txpower(sc, 0)) != 0) { 5114 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5115 return error; 5116 } 5117 5118 if ((error = iwn_set_critical_temp(sc)) != 0) { 5119 printf("%s: could not set critical temperature\n", 5120 sc->sc_dev.dv_xname); 5121 return error; 5122 } 5123 5124 /* Set power saving level to CAM during initialization. */ 5125 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) { 5126 printf("%s: could not set power saving level\n", 5127 sc->sc_dev.dv_xname); 5128 return error; 5129 } 5130 return 0; 5131 } 5132 5133 uint16_t 5134 iwn_get_active_dwell_time(struct iwn_softc *sc, 5135 uint16_t flags, uint8_t n_probes) 5136 { 5137 /* No channel? Default to 2GHz settings */ 5138 if (flags & IEEE80211_CHAN_2GHZ) { 5139 return (IWN_ACTIVE_DWELL_TIME_2GHZ + 5140 IWN_ACTIVE_DWELL_FACTOR_2GHZ * (n_probes + 1)); 5141 } 5142 5143 /* 5GHz dwell time */ 5144 return (IWN_ACTIVE_DWELL_TIME_5GHZ + 5145 IWN_ACTIVE_DWELL_FACTOR_5GHZ * (n_probes + 1)); 5146 } 5147 5148 /* 5149 * Limit the total dwell time to 85% of the beacon interval. 5150 * 5151 * Returns the dwell time in milliseconds. 5152 */ 5153 uint16_t 5154 iwn_limit_dwell(struct iwn_softc *sc, uint16_t dwell_time) 5155 { 5156 struct ieee80211com *ic = &sc->sc_ic; 5157 struct ieee80211_node *ni = ic->ic_bss; 5158 int bintval = 0; 5159 5160 /* bintval is in TU (1.024mS) */ 5161 if (ni != NULL) 5162 bintval = ni->ni_intval; 5163 5164 /* 5165 * If it's non-zero, we should calculate the minimum of 5166 * it and the DWELL_BASE. 5167 * 5168 * XXX Yes, the math should take into account that bintval 5169 * is 1.024mS, not 1mS.. 5170 */ 5171 if (ic->ic_state == IEEE80211_S_RUN && bintval > 0) 5172 return (MIN(IWN_PASSIVE_DWELL_BASE, ((bintval * 85) / 100))); 5173 5174 /* No association context? Default */ 5175 return dwell_time; 5176 } 5177 5178 uint16_t 5179 iwn_get_passive_dwell_time(struct iwn_softc *sc, uint16_t flags) 5180 { 5181 uint16_t passive; 5182 if (flags & IEEE80211_CHAN_2GHZ) { 5183 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_2GHZ; 5184 } else { 5185 passive = IWN_PASSIVE_DWELL_BASE + IWN_PASSIVE_DWELL_TIME_5GHZ; 5186 } 5187 5188 /* Clamp to the beacon interval if we're associated */ 5189 return (iwn_limit_dwell(sc, passive)); 5190 } 5191 5192 int 5193 iwn_scan(struct iwn_softc *sc, uint16_t flags, int bgscan) 5194 { 5195 struct ieee80211com *ic = &sc->sc_ic; 5196 struct iwn_scan_hdr *hdr; 5197 struct iwn_cmd_data *tx; 5198 struct iwn_scan_essid *essid; 5199 struct iwn_scan_chan *chan; 5200 struct ieee80211_frame *wh; 5201 struct ieee80211_rateset *rs; 5202 struct ieee80211_channel *c; 5203 uint8_t *buf, *frm; 5204 uint16_t rxchain, dwell_active, dwell_passive; 5205 uint8_t txant; 5206 int buflen, error, is_active; 5207 5208 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO); 5209 if (buf == NULL) { 5210 printf("%s: could not allocate buffer for scan command\n", 5211 sc->sc_dev.dv_xname); 5212 return ENOMEM; 5213 } 5214 hdr = (struct iwn_scan_hdr *)buf; 5215 /* 5216 * Move to the next channel if no frames are received within 10ms 5217 * after sending the probe request. 5218 */ 5219 hdr->quiet_time = htole16(10); /* timeout in milliseconds */ 5220 hdr->quiet_threshold = htole16(1); /* min # of packets */ 5221 5222 if (bgscan) { 5223 int bintval; 5224 5225 /* Set maximum off-channel time. */ 5226 hdr->max_out = htole32(200 * 1024); 5227 5228 /* Configure scan pauses which service on-channel traffic. */ 5229 bintval = ic->ic_bss->ni_intval ? ic->ic_bss->ni_intval : 100; 5230 hdr->pause_scan = htole32(((100 / bintval) << 22) | 5231 ((100 % bintval) * 1024)); 5232 } 5233 5234 /* Select antennas for scanning. */ 5235 rxchain = 5236 IWN_RXCHAIN_VALID(sc->rxchainmask) | 5237 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) | 5238 IWN_RXCHAIN_DRIVER_FORCE; 5239 if ((flags & IEEE80211_CHAN_5GHZ) && 5240 sc->hw_type == IWN_HW_REV_TYPE_4965) { 5241 /* 5242 * On 4965 ant A and C must be avoided in 5GHz because of a 5243 * HW bug which causes very weak RSSI values being reported. 5244 */ 5245 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B); 5246 } else /* Use all available RX antennas. */ 5247 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask); 5248 hdr->rxchain = htole16(rxchain); 5249 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON); 5250 5251 tx = (struct iwn_cmd_data *)(hdr + 1); 5252 tx->flags = htole32(IWN_TX_AUTO_SEQ); 5253 tx->id = sc->broadcast_id; 5254 tx->lifetime = htole32(IWN_LIFETIME_INFINITE); 5255 5256 if (flags & IEEE80211_CHAN_5GHZ) { 5257 /* Send probe requests at 6Mbps. */ 5258 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 5259 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A]; 5260 } else { 5261 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO); 5262 if (bgscan && sc->hw_type == IWN_HW_REV_TYPE_4965 && 5263 sc->rxon.chan > 14) { 5264 /* 5265 * 4965 firmware can crash when sending probe requests 5266 * with CCK rates while associated to a 5GHz AP. 5267 * Send probe requests at 6Mbps OFDM as a workaround. 5268 */ 5269 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp; 5270 } else { 5271 /* Send probe requests at 1Mbps. */ 5272 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp; 5273 tx->rflags = IWN_RFLAG_CCK; 5274 } 5275 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G]; 5276 } 5277 /* Use the first valid TX antenna. */ 5278 txant = IWN_LSB(sc->txchainmask); 5279 tx->rflags |= IWN_RFLAG_ANT(txant); 5280 5281 /* 5282 * Only do active scanning if we're announcing a probe request 5283 * for a given SSID (or more, if we ever add it to the driver.) 5284 */ 5285 is_active = 0; 5286 5287 /* 5288 * If we're scanning for a specific SSID, add it to the command. 5289 */ 5290 essid = (struct iwn_scan_essid *)(tx + 1); 5291 if (ic->ic_des_esslen != 0) { 5292 essid[0].id = IEEE80211_ELEMID_SSID; 5293 essid[0].len = ic->ic_des_esslen; 5294 memcpy(essid[0].data, ic->ic_des_essid, ic->ic_des_esslen); 5295 5296 is_active = 1; 5297 } 5298 /* 5299 * Build a probe request frame. Most of the following code is a 5300 * copy & paste of what is done in net80211. 5301 */ 5302 wh = (struct ieee80211_frame *)(essid + 20); 5303 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | 5304 IEEE80211_FC0_SUBTYPE_PROBE_REQ; 5305 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS; 5306 IEEE80211_ADDR_COPY(wh->i_addr1, etherbroadcastaddr); 5307 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_myaddr); 5308 IEEE80211_ADDR_COPY(wh->i_addr3, etherbroadcastaddr); 5309 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ 5310 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ 5311 5312 frm = (uint8_t *)(wh + 1); 5313 frm = ieee80211_add_ssid(frm, NULL, 0); 5314 frm = ieee80211_add_rates(frm, rs); 5315 if (rs->rs_nrates > IEEE80211_RATE_SIZE) 5316 frm = ieee80211_add_xrates(frm, rs); 5317 if (ic->ic_flags & IEEE80211_F_HTON) 5318 frm = ieee80211_add_htcaps(frm, ic); 5319 5320 /* Set length of probe request. */ 5321 tx->len = htole16(frm - (uint8_t *)wh); 5322 5323 /* 5324 * If active scanning is requested but a certain channel is 5325 * marked passive, we can do active scanning if we detect 5326 * transmissions. 5327 * 5328 * There is an issue with some firmware versions that triggers 5329 * a sysassert on a "good CRC threshold" of zero (== disabled), 5330 * on a radar channel even though this means that we should NOT 5331 * send probes. 5332 * 5333 * The "good CRC threshold" is the number of frames that we 5334 * need to receive during our dwell time on a channel before 5335 * sending out probes -- setting this to a huge value will 5336 * mean we never reach it, but at the same time work around 5337 * the aforementioned issue. Thus use IWN_GOOD_CRC_TH_NEVER 5338 * here instead of IWN_GOOD_CRC_TH_DISABLED. 5339 * 5340 * This was fixed in later versions along with some other 5341 * scan changes, and the threshold behaves as a flag in those 5342 * versions. 5343 */ 5344 5345 /* 5346 * If we're doing active scanning, set the crc_threshold 5347 * to a suitable value. This is different to active veruss 5348 * passive scanning depending upon the channel flags; the 5349 * firmware will obey that particular check for us. 5350 */ 5351 if (sc->tlv_feature_flags & IWN_UCODE_TLV_FLAGS_NEWSCAN) 5352 hdr->crc_threshold = is_active ? 5353 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_DISABLED; 5354 else 5355 hdr->crc_threshold = is_active ? 5356 IWN_GOOD_CRC_TH_DEFAULT : IWN_GOOD_CRC_TH_NEVER; 5357 5358 chan = (struct iwn_scan_chan *)frm; 5359 for (c = &ic->ic_channels[1]; 5360 c <= &ic->ic_channels[IEEE80211_CHAN_MAX]; c++) { 5361 if ((c->ic_flags & flags) != flags) 5362 continue; 5363 5364 chan->chan = htole16(ieee80211_chan2ieee(ic, c)); 5365 DPRINTFN(2, ("adding channel %d\n", chan->chan)); 5366 chan->flags = 0; 5367 if (ic->ic_des_esslen != 0) 5368 chan->flags |= htole32(IWN_CHAN_NPBREQS(1)); 5369 5370 if (c->ic_flags & IEEE80211_CHAN_PASSIVE) 5371 chan->flags |= htole32(IWN_CHAN_PASSIVE); 5372 else 5373 chan->flags |= htole32(IWN_CHAN_ACTIVE); 5374 5375 /* 5376 * Calculate the active/passive dwell times. 5377 */ 5378 5379 dwell_active = iwn_get_active_dwell_time(sc, flags, is_active); 5380 dwell_passive = iwn_get_passive_dwell_time(sc, flags); 5381 5382 /* Make sure they're valid */ 5383 if (dwell_passive <= dwell_active) 5384 dwell_passive = dwell_active + 1; 5385 5386 chan->active = htole16(dwell_active); 5387 chan->passive = htole16(dwell_passive); 5388 5389 chan->dsp_gain = 0x6e; 5390 if (IEEE80211_IS_CHAN_5GHZ(c)) { 5391 chan->rf_gain = 0x3b; 5392 } else { 5393 chan->rf_gain = 0x28; 5394 } 5395 hdr->nchan++; 5396 chan++; 5397 } 5398 5399 buflen = (uint8_t *)chan - buf; 5400 hdr->len = htole16(buflen); 5401 5402 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1); 5403 if (error == 0) { 5404 /* 5405 * The current mode might have been fixed during association. 5406 * Ensure all channels get scanned. 5407 */ 5408 if (IFM_MODE(ic->ic_media.ifm_cur->ifm_media) == IFM_AUTO) 5409 ieee80211_setmode(ic, IEEE80211_MODE_AUTO); 5410 5411 sc->sc_flags |= IWN_FLAG_SCANNING; 5412 if (bgscan) 5413 sc->sc_flags |= IWN_FLAG_BGSCAN; 5414 } 5415 free(buf, M_DEVBUF, IWN_SCAN_MAXSZ); 5416 return error; 5417 } 5418 5419 void 5420 iwn_scan_abort(struct iwn_softc *sc) 5421 { 5422 iwn_cmd(sc, IWN_CMD_SCAN_ABORT, NULL, 0, 1); 5423 5424 /* XXX Cannot wait for status response in interrupt context. */ 5425 DELAY(100); 5426 5427 sc->sc_flags &= ~IWN_FLAG_SCANNING; 5428 sc->sc_flags &= ~IWN_FLAG_BGSCAN; 5429 } 5430 5431 int 5432 iwn_bgscan(struct ieee80211com *ic) 5433 { 5434 struct iwn_softc *sc = ic->ic_softc; 5435 int error; 5436 5437 if (sc->sc_flags & IWN_FLAG_SCANNING) 5438 return 0; 5439 5440 error = iwn_scan(sc, IEEE80211_CHAN_2GHZ, 1); 5441 if (error) 5442 printf("%s: could not initiate background scan\n", 5443 sc->sc_dev.dv_xname); 5444 return error; 5445 } 5446 5447 int 5448 iwn_auth(struct iwn_softc *sc, int arg) 5449 { 5450 struct iwn_ops *ops = &sc->ops; 5451 struct ieee80211com *ic = &sc->sc_ic; 5452 struct ieee80211_node *ni = ic->ic_bss; 5453 int error, ridx; 5454 int bss_switch = 5455 (!IEEE80211_ADDR_EQ(sc->bss_node_addr, etheranyaddr) && 5456 !IEEE80211_ADDR_EQ(sc->bss_node_addr, ni->ni_macaddr)); 5457 5458 /* Update adapter configuration. */ 5459 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid); 5460 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan); 5461 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF); 5462 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan)) { 5463 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ); 5464 if (ic->ic_flags & IEEE80211_F_USEPROT) 5465 sc->rxon.flags |= htole32(IWN_RXON_TGG_PROT); 5466 DPRINTF(("%s: 2ghz prot 0x%x\n", __func__, 5467 le32toh(sc->rxon.flags))); 5468 } 5469 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5470 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5471 else 5472 sc->rxon.flags &= ~htole32(IWN_RXON_SHSLOT); 5473 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5474 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5475 else 5476 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE); 5477 switch (ic->ic_curmode) { 5478 case IEEE80211_MODE_11A: 5479 sc->rxon.cck_mask = 0; 5480 sc->rxon.ofdm_mask = 0x15; 5481 break; 5482 case IEEE80211_MODE_11B: 5483 sc->rxon.cck_mask = 0x03; 5484 sc->rxon.ofdm_mask = 0; 5485 break; 5486 default: /* Assume 802.11b/g/n. */ 5487 sc->rxon.cck_mask = 0x0f; 5488 sc->rxon.ofdm_mask = 0x15; 5489 } 5490 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x\n", __func__, 5491 sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5492 sc->rxon.ofdm_mask)); 5493 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5494 if (error != 0) { 5495 printf("%s: RXON command failed\n", sc->sc_dev.dv_xname); 5496 return error; 5497 } 5498 5499 /* Configuration has changed, set TX power accordingly. */ 5500 if ((error = ops->set_txpower(sc, 1)) != 0) { 5501 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5502 return error; 5503 } 5504 /* 5505 * Reconfiguring RXON clears the firmware nodes table so we must 5506 * add the broadcast node again. 5507 */ 5508 ridx = IEEE80211_IS_CHAN_5GHZ(ni->ni_chan) ? 5509 IWN_RIDX_OFDM6 : IWN_RIDX_CCK1; 5510 if ((error = iwn_add_broadcast_node(sc, 1, ridx)) != 0) { 5511 printf("%s: could not add broadcast node\n", 5512 sc->sc_dev.dv_xname); 5513 return error; 5514 } 5515 5516 /* 5517 * Make sure the firmware gets to see a beacon before we send 5518 * the auth request. Otherwise the Tx attempt can fail due to 5519 * the firmware's built-in regulatory domain enforcement. 5520 * Delaying here for every incoming deauth frame can result in a DoS. 5521 * Don't delay if we're here because of an incoming frame (arg != -1) 5522 * or if we're already waiting for a response (ic_mgt_timer != 0). 5523 * If we are switching APs after a background scan then net80211 has 5524 * just faked the reception of a deauth frame from our old AP, so it 5525 * is safe to delay in that case. 5526 */ 5527 if ((arg == -1 || bss_switch) && ic->ic_mgt_timer == 0) 5528 DELAY(ni->ni_intval * 3 * IEEE80211_DUR_TU); 5529 5530 /* We can now clear the cached address of our previous AP. */ 5531 memset(sc->bss_node_addr, 0, sizeof(sc->bss_node_addr)); 5532 5533 return 0; 5534 } 5535 5536 int 5537 iwn_run(struct iwn_softc *sc) 5538 { 5539 struct iwn_ops *ops = &sc->ops; 5540 struct ieee80211com *ic = &sc->sc_ic; 5541 struct ieee80211_node *ni = ic->ic_bss; 5542 struct iwn_node *wn = (void *)ni; 5543 struct iwn_node_info node; 5544 int error; 5545 5546 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 5547 /* Link LED blinks while monitoring. */ 5548 iwn_set_led(sc, IWN_LED_LINK, 50, 50); 5549 return 0; 5550 } 5551 if ((error = iwn_set_timing(sc, ni)) != 0) { 5552 printf("%s: could not set timing\n", sc->sc_dev.dv_xname); 5553 return error; 5554 } 5555 5556 /* Update adapter configuration. */ 5557 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd)); 5558 /* Short preamble and slot time are negotiated when associating. */ 5559 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT); 5560 if (ic->ic_flags & IEEE80211_F_SHSLOT) 5561 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT); 5562 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 5563 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE); 5564 sc->rxon.filter |= htole32(IWN_FILTER_BSS); 5565 5566 /* HT is negotiated when associating. */ 5567 if (ni->ni_flags & IEEE80211_NODE_HT) { 5568 enum ieee80211_htprot htprot = 5569 (ni->ni_htop1 & IEEE80211_HTOP1_PROT_MASK); 5570 DPRINTF(("%s: htprot = %d\n", __func__, htprot)); 5571 sc->rxon.flags |= htole32(IWN_RXON_HT_PROTMODE(htprot)); 5572 } else 5573 sc->rxon.flags &= ~htole32(IWN_RXON_HT_PROTMODE(3)); 5574 5575 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)) { 5576 /* 11a or 11n 5GHz */ 5577 sc->rxon.cck_mask = 0; 5578 sc->rxon.ofdm_mask = 0x15; 5579 } else if (ni->ni_flags & IEEE80211_NODE_HT) { 5580 /* 11n 2GHz */ 5581 sc->rxon.cck_mask = 0x0f; 5582 sc->rxon.ofdm_mask = 0x15; 5583 } else { 5584 if (ni->ni_rates.rs_nrates == 4) { 5585 /* 11b */ 5586 sc->rxon.cck_mask = 0x03; 5587 sc->rxon.ofdm_mask = 0; 5588 } else { 5589 /* assume 11g */ 5590 sc->rxon.cck_mask = 0x0f; 5591 sc->rxon.ofdm_mask = 0x15; 5592 } 5593 } 5594 DPRINTF(("%s: rxon chan %d flags %x cck %x ofdm %x\n", __func__, 5595 sc->rxon.chan, le32toh(sc->rxon.flags), sc->rxon.cck_mask, 5596 sc->rxon.ofdm_mask)); 5597 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1); 5598 if (error != 0) { 5599 printf("%s: could not update configuration\n", 5600 sc->sc_dev.dv_xname); 5601 return error; 5602 } 5603 5604 /* Configuration has changed, set TX power accordingly. */ 5605 if ((error = ops->set_txpower(sc, 1)) != 0) { 5606 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5607 return error; 5608 } 5609 5610 /* Fake a join to initialize the TX rate. */ 5611 ((struct iwn_node *)ni)->id = IWN_ID_BSS; 5612 iwn_newassoc(ic, ni, 1); 5613 5614 /* Add BSS node. */ 5615 memset(&node, 0, sizeof node); 5616 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr); 5617 node.id = IWN_ID_BSS; 5618 if (ni->ni_flags & IEEE80211_NODE_HT) { 5619 node.htmask = (IWN_AMDPU_SIZE_FACTOR_MASK | 5620 IWN_AMDPU_DENSITY_MASK); 5621 node.htflags = htole32( 5622 IWN_AMDPU_SIZE_FACTOR( 5623 (ic->ic_ampdu_params & IEEE80211_AMPDU_PARAM_LE)) | 5624 IWN_AMDPU_DENSITY( 5625 (ic->ic_ampdu_params & IEEE80211_AMPDU_PARAM_SS) >> 2)); 5626 } 5627 DPRINTF(("adding BSS node\n")); 5628 error = ops->add_node(sc, &node, 1); 5629 if (error != 0) { 5630 printf("%s: could not add BSS node\n", sc->sc_dev.dv_xname); 5631 return error; 5632 } 5633 5634 /* Cache address of AP in case it changes after a background scan. */ 5635 IEEE80211_ADDR_COPY(sc->bss_node_addr, ni->ni_macaddr); 5636 5637 DPRINTF(("setting link quality for node %d\n", node.id)); 5638 if ((error = iwn_set_link_quality(sc, ni)) != 0) { 5639 printf("%s: could not setup link quality for node %d\n", 5640 sc->sc_dev.dv_xname, node.id); 5641 return error; 5642 } 5643 5644 if ((error = iwn_init_sensitivity(sc)) != 0) { 5645 printf("%s: could not set sensitivity\n", 5646 sc->sc_dev.dv_xname); 5647 return error; 5648 } 5649 /* Start periodic calibration timer. */ 5650 sc->calib.state = IWN_CALIB_STATE_ASSOC; 5651 sc->calib_cnt = 0; 5652 timeout_add_msec(&sc->calib_to, 500); 5653 5654 ieee80211_mira_node_init(&wn->mn); 5655 5656 /* Link LED always on while associated. */ 5657 iwn_set_led(sc, IWN_LED_LINK, 0, 1); 5658 return 0; 5659 } 5660 5661 /* 5662 * We support CCMP hardware encryption/decryption of unicast frames only. 5663 * HW support for TKIP really sucks. We should let TKIP die anyway. 5664 */ 5665 int 5666 iwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5667 struct ieee80211_key *k) 5668 { 5669 struct iwn_softc *sc = ic->ic_softc; 5670 struct iwn_ops *ops = &sc->ops; 5671 struct iwn_node *wn = (void *)ni; 5672 struct iwn_node_info node; 5673 uint16_t kflags; 5674 5675 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5676 k->k_cipher != IEEE80211_CIPHER_CCMP) 5677 return ieee80211_set_key(ic, ni, k); 5678 5679 kflags = IWN_KFLAG_CCMP | IWN_KFLAG_MAP | IWN_KFLAG_KID(k->k_id); 5680 if (k->k_flags & IEEE80211_KEY_GROUP) 5681 kflags |= IWN_KFLAG_GROUP; 5682 5683 memset(&node, 0, sizeof node); 5684 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5685 sc->broadcast_id : wn->id; 5686 node.control = IWN_NODE_UPDATE; 5687 node.flags = IWN_FLAG_SET_KEY; 5688 node.kflags = htole16(kflags); 5689 node.kid = k->k_id; 5690 memcpy(node.key, k->k_key, k->k_len); 5691 DPRINTF(("set key id=%d for node %d\n", k->k_id, node.id)); 5692 return ops->add_node(sc, &node, 1); 5693 } 5694 5695 void 5696 iwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 5697 struct ieee80211_key *k) 5698 { 5699 struct iwn_softc *sc = ic->ic_softc; 5700 struct iwn_ops *ops = &sc->ops; 5701 struct iwn_node *wn = (void *)ni; 5702 struct iwn_node_info node; 5703 5704 if ((k->k_flags & IEEE80211_KEY_GROUP) || 5705 k->k_cipher != IEEE80211_CIPHER_CCMP) { 5706 /* See comment about other ciphers above. */ 5707 ieee80211_delete_key(ic, ni, k); 5708 return; 5709 } 5710 if (ic->ic_state != IEEE80211_S_RUN) 5711 return; /* Nothing to do. */ 5712 memset(&node, 0, sizeof node); 5713 node.id = (k->k_flags & IEEE80211_KEY_GROUP) ? 5714 sc->broadcast_id : wn->id; 5715 node.control = IWN_NODE_UPDATE; 5716 node.flags = IWN_FLAG_SET_KEY; 5717 node.kflags = htole16(IWN_KFLAG_INVALID); 5718 node.kid = 0xff; 5719 DPRINTF(("delete keys for node %d\n", node.id)); 5720 (void)ops->add_node(sc, &node, 1); 5721 } 5722 5723 /* 5724 * This function is called by upper layer when HT protection settings in 5725 * beacons have changed. 5726 */ 5727 void 5728 iwn_update_htprot(struct ieee80211com *ic, struct ieee80211_node *ni) 5729 { 5730 struct iwn_softc *sc = ic->ic_softc; 5731 struct iwn_ops *ops = &sc->ops; 5732 enum ieee80211_htprot htprot; 5733 struct iwn_rxon_assoc rxon_assoc; 5734 int s, error; 5735 5736 /* Update HT protection mode setting. */ 5737 htprot = (ni->ni_htop1 & IEEE80211_HTOP1_PROT_MASK) >> 5738 IEEE80211_HTOP1_PROT_SHIFT; 5739 sc->rxon.flags &= ~htole32(IWN_RXON_HT_PROTMODE(3)); 5740 sc->rxon.flags |= htole32(IWN_RXON_HT_PROTMODE(htprot)); 5741 5742 /* Update RXON config. */ 5743 memset(&rxon_assoc, 0, sizeof(rxon_assoc)); 5744 rxon_assoc.flags = sc->rxon.flags; 5745 rxon_assoc.filter = sc->rxon.filter; 5746 rxon_assoc.ofdm_mask = sc->rxon.ofdm_mask; 5747 rxon_assoc.cck_mask = sc->rxon.cck_mask; 5748 rxon_assoc.ht_single_mask = sc->rxon.ht_single_mask; 5749 rxon_assoc.ht_dual_mask = sc->rxon.ht_dual_mask; 5750 rxon_assoc.ht_triple_mask = sc->rxon.ht_triple_mask; 5751 rxon_assoc.rxchain = sc->rxon.rxchain; 5752 rxon_assoc.acquisition = sc->rxon.acquisition; 5753 5754 s = splnet(); 5755 5756 error = iwn_cmd(sc, IWN_CMD_RXON_ASSOC, &rxon_assoc, 5757 sizeof(rxon_assoc), 1); 5758 if (error != 0) 5759 printf("%s: RXON_ASSOC command failed\n", sc->sc_dev.dv_xname); 5760 5761 DELAY(100); 5762 5763 /* All RXONs wipe the firmware's txpower table. Restore it. */ 5764 error = ops->set_txpower(sc, 1); 5765 if (error != 0) 5766 printf("%s: could not set TX power\n", sc->sc_dev.dv_xname); 5767 5768 DELAY(100); 5769 5770 /* Restore power saving level */ 5771 if (ic->ic_flags & IEEE80211_F_PMGTON) 5772 error = iwn_set_pslevel(sc, 0, 3, 1); 5773 else 5774 error = iwn_set_pslevel(sc, 0, 0, 1); 5775 if (error != 0) 5776 printf("%s: could not set PS level\n", sc->sc_dev.dv_xname); 5777 5778 splx(s); 5779 } 5780 5781 /* 5782 * This function is called by upper layer when an ADDBA request is received 5783 * from another STA and before the ADDBA response is sent. 5784 */ 5785 int 5786 iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5787 uint8_t tid) 5788 { 5789 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid]; 5790 struct iwn_softc *sc = ic->ic_softc; 5791 struct iwn_ops *ops = &sc->ops; 5792 struct iwn_node *wn = (void *)ni; 5793 struct iwn_node_info node; 5794 5795 memset(&node, 0, sizeof node); 5796 node.id = wn->id; 5797 node.control = IWN_NODE_UPDATE; 5798 node.flags = IWN_FLAG_SET_ADDBA; 5799 node.addba_tid = tid; 5800 node.addba_ssn = htole16(ba->ba_winstart); 5801 DPRINTF(("ADDBA RA=%d TID=%d SSN=%d\n", wn->id, tid, 5802 ba->ba_winstart)); 5803 /* XXX async command, so firmware may still fail to add BA agreement */ 5804 return ops->add_node(sc, &node, 1); 5805 } 5806 5807 /* 5808 * This function is called by upper layer on teardown of an HT-immediate 5809 * Block Ack agreement (eg. uppon receipt of a DELBA frame). 5810 */ 5811 void 5812 iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5813 uint8_t tid) 5814 { 5815 struct iwn_softc *sc = ic->ic_softc; 5816 struct iwn_ops *ops = &sc->ops; 5817 struct iwn_node *wn = (void *)ni; 5818 struct iwn_node_info node; 5819 5820 memset(&node, 0, sizeof node); 5821 node.id = wn->id; 5822 node.control = IWN_NODE_UPDATE; 5823 node.flags = IWN_FLAG_SET_DELBA; 5824 node.delba_tid = tid; 5825 DPRINTF(("DELBA RA=%d TID=%d\n", wn->id, tid)); 5826 (void)ops->add_node(sc, &node, 1); 5827 } 5828 5829 /* 5830 * This function is called by upper layer when an ADDBA response is received 5831 * from another STA. 5832 */ 5833 int 5834 iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 5835 uint8_t tid) 5836 { 5837 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5838 struct iwn_softc *sc = ic->ic_softc; 5839 struct iwn_ops *ops = &sc->ops; 5840 struct iwn_node *wn = (void *)ni; 5841 struct iwn_node_info node; 5842 int qid = sc->first_agg_txq + tid; 5843 int error; 5844 5845 /* Ensure we can map this TID to an aggregation queue. */ 5846 if (tid >= IWN_NUM_AMPDU_TID || ba->ba_winsize > IWN_SCHED_WINSZ || 5847 qid > sc->ntxqs || (sc->agg_queue_mask & (1 << qid))) 5848 return ENOSPC; 5849 5850 /* Enable TX for the specified RA/TID. */ 5851 wn->disable_tid &= ~(1 << tid); 5852 memset(&node, 0, sizeof node); 5853 node.id = wn->id; 5854 node.control = IWN_NODE_UPDATE; 5855 node.flags = IWN_FLAG_SET_DISABLE_TID; 5856 node.disable_tid = htole16(wn->disable_tid); 5857 error = ops->add_node(sc, &node, 1); 5858 if (error != 0) 5859 return error; 5860 5861 if ((error = iwn_nic_lock(sc)) != 0) 5862 return error; 5863 ops->ampdu_tx_start(sc, ni, tid, ba->ba_winstart); 5864 iwn_nic_unlock(sc); 5865 5866 sc->agg_queue_mask |= (1 << qid); 5867 sc->sc_tx_ba[tid].wn = wn; 5868 ba->ba_bitmap = 0; 5869 5870 return 0; 5871 } 5872 5873 void 5874 iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 5875 uint8_t tid) 5876 { 5877 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid]; 5878 struct iwn_softc *sc = ic->ic_softc; 5879 struct iwn_ops *ops = &sc->ops; 5880 int qid = sc->first_agg_txq + tid; 5881 struct iwn_node *wn = (void *)ni; 5882 struct iwn_node_info node; 5883 5884 /* Discard all frames in the current window. */ 5885 iwn_ampdu_txq_advance(sc, &sc->txq[qid], qid, 5886 IWN_AGG_SSN_TO_TXQ_IDX(ba->ba_winend)); 5887 5888 if (iwn_nic_lock(sc) != 0) 5889 return; 5890 ops->ampdu_tx_stop(sc, tid, ba->ba_winstart); 5891 iwn_nic_unlock(sc); 5892 5893 sc->agg_queue_mask &= ~(1 << qid); 5894 sc->sc_tx_ba[tid].wn = NULL; 5895 ba->ba_bitmap = 0; 5896 5897 /* Disable TX for the specified RA/TID. */ 5898 wn->disable_tid |= (1 << tid); 5899 memset(&node, 0, sizeof node); 5900 node.id = wn->id; 5901 node.control = IWN_NODE_UPDATE; 5902 node.flags = IWN_FLAG_SET_DISABLE_TID; 5903 node.disable_tid = htole16(wn->disable_tid); 5904 ops->add_node(sc, &node, 1); 5905 } 5906 5907 void 5908 iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5909 uint8_t tid, uint16_t ssn) 5910 { 5911 struct iwn_node *wn = (void *)ni; 5912 int qid = IWN4965_FIRST_AGG_TXQUEUE + tid; 5913 uint16_t idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5914 5915 /* Stop TX scheduler while we're changing its configuration. */ 5916 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5917 IWN4965_TXQ_STATUS_CHGACT); 5918 5919 /* Assign RA/TID translation to the queue. */ 5920 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid), 5921 wn->id << 4 | tid); 5922 5923 /* Enable chain-building mode for the queue. */ 5924 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid); 5925 5926 /* Set starting sequence number from the ADDBA request. */ 5927 sc->txq[qid].cur = sc->txq[qid].read = idx; 5928 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5929 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5930 5931 /* Set scheduler window size. */ 5932 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid), 5933 IWN_SCHED_WINSZ); 5934 /* Set scheduler frame limit. */ 5935 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 5936 IWN_SCHED_LIMIT << 16); 5937 5938 /* Enable interrupts for the queue. */ 5939 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5940 5941 /* Mark the queue as active. */ 5942 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5943 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA | 5944 iwn_tid2fifo[tid] << 1); 5945 } 5946 5947 void 5948 iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 5949 { 5950 int qid = IWN4965_FIRST_AGG_TXQUEUE + tid; 5951 uint16_t idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5952 5953 /* Stop TX scheduler while we're changing its configuration. */ 5954 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5955 IWN4965_TXQ_STATUS_CHGACT); 5956 5957 /* Set starting sequence number from the ADDBA request. */ 5958 sc->txq[qid].cur = sc->txq[qid].read = idx; 5959 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5960 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn); 5961 5962 /* Disable interrupts for the queue. */ 5963 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid); 5964 5965 /* Mark the queue as inactive. */ 5966 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 5967 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1); 5968 } 5969 5970 void 5971 iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni, 5972 uint8_t tid, uint16_t ssn) 5973 { 5974 int qid = IWN5000_FIRST_AGG_TXQUEUE + tid; 5975 int idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 5976 struct iwn_node *wn = (void *)ni; 5977 5978 /* Stop TX scheduler while we're changing its configuration. */ 5979 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 5980 IWN5000_TXQ_STATUS_CHGACT); 5981 5982 /* Assign RA/TID translation to the queue. */ 5983 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid), 5984 wn->id << 4 | tid); 5985 5986 /* Enable chain-building mode for the queue. */ 5987 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid); 5988 5989 /* Enable aggregation for the queue. */ 5990 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 5991 5992 /* Set starting sequence number from the ADDBA request. */ 5993 sc->txq[qid].cur = sc->txq[qid].read = idx; 5994 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 5995 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 5996 5997 /* Set scheduler window size and frame limit. */ 5998 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 5999 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 6000 6001 /* Enable interrupts for the queue. */ 6002 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 6003 6004 /* Mark the queue as active. */ 6005 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6006 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]); 6007 } 6008 6009 void 6010 iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn) 6011 { 6012 int qid = IWN5000_FIRST_AGG_TXQUEUE + tid; 6013 int idx = IWN_AGG_SSN_TO_TXQ_IDX(ssn); 6014 6015 /* Stop TX scheduler while we're changing its configuration. */ 6016 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6017 IWN5000_TXQ_STATUS_CHGACT); 6018 6019 /* Disable aggregation for the queue. */ 6020 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid); 6021 6022 /* Set starting sequence number from the ADDBA request. */ 6023 sc->txq[qid].cur = sc->txq[qid].read = idx; 6024 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | idx); 6025 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn); 6026 6027 /* Disable interrupts for the queue. */ 6028 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid); 6029 6030 /* Mark the queue as inactive. */ 6031 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6032 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]); 6033 } 6034 6035 /* 6036 * Query calibration tables from the initialization firmware. We do this 6037 * only once at first boot. Called from a process context. 6038 */ 6039 int 6040 iwn5000_query_calibration(struct iwn_softc *sc) 6041 { 6042 struct iwn5000_calib_config cmd; 6043 int error; 6044 6045 memset(&cmd, 0, sizeof cmd); 6046 cmd.ucode.once.enable = 0xffffffff; 6047 cmd.ucode.once.start = 0xffffffff; 6048 cmd.ucode.once.send = 0xffffffff; 6049 cmd.ucode.flags = 0xffffffff; 6050 DPRINTF(("sending calibration query\n")); 6051 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0); 6052 if (error != 0) 6053 return error; 6054 6055 /* Wait at most two seconds for calibration to complete. */ 6056 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) 6057 error = tsleep_nsec(sc, PCATCH, "iwncal", SEC_TO_NSEC(2)); 6058 return error; 6059 } 6060 6061 /* 6062 * Send calibration results to the runtime firmware. These results were 6063 * obtained on first boot from the initialization firmware. 6064 */ 6065 int 6066 iwn5000_send_calibration(struct iwn_softc *sc) 6067 { 6068 int idx, error; 6069 6070 for (idx = 0; idx < 5; idx++) { 6071 if (sc->calibcmd[idx].buf == NULL) 6072 continue; /* No results available. */ 6073 DPRINTF(("send calibration result idx=%d len=%d\n", 6074 idx, sc->calibcmd[idx].len)); 6075 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf, 6076 sc->calibcmd[idx].len, 0); 6077 if (error != 0) { 6078 printf("%s: could not send calibration result\n", 6079 sc->sc_dev.dv_xname); 6080 return error; 6081 } 6082 } 6083 return 0; 6084 } 6085 6086 int 6087 iwn5000_send_wimax_coex(struct iwn_softc *sc) 6088 { 6089 struct iwn5000_wimax_coex wimax; 6090 6091 #ifdef notyet 6092 if (sc->hw_type == IWN_HW_REV_TYPE_6050) { 6093 /* Enable WiMAX coexistence for combo adapters. */ 6094 wimax.flags = 6095 IWN_WIMAX_COEX_ASSOC_WA_UNMASK | 6096 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK | 6097 IWN_WIMAX_COEX_STA_TABLE_VALID | 6098 IWN_WIMAX_COEX_ENABLE; 6099 memcpy(wimax.events, iwn6050_wimax_events, 6100 sizeof iwn6050_wimax_events); 6101 } else 6102 #endif 6103 { 6104 /* Disable WiMAX coexistence. */ 6105 wimax.flags = 0; 6106 memset(wimax.events, 0, sizeof wimax.events); 6107 } 6108 DPRINTF(("Configuring WiMAX coexistence\n")); 6109 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0); 6110 } 6111 6112 int 6113 iwn5000_crystal_calib(struct iwn_softc *sc) 6114 { 6115 struct iwn5000_phy_calib_crystal cmd; 6116 6117 memset(&cmd, 0, sizeof cmd); 6118 cmd.code = IWN5000_PHY_CALIB_CRYSTAL; 6119 cmd.ngroups = 1; 6120 cmd.isvalid = 1; 6121 cmd.cap_pin[0] = letoh32(sc->eeprom_crystal) & 0xff; 6122 cmd.cap_pin[1] = (letoh32(sc->eeprom_crystal) >> 16) & 0xff; 6123 DPRINTF(("sending crystal calibration %d, %d\n", 6124 cmd.cap_pin[0], cmd.cap_pin[1])); 6125 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6126 } 6127 6128 int 6129 iwn6000_temp_offset_calib(struct iwn_softc *sc) 6130 { 6131 struct iwn6000_phy_calib_temp_offset cmd; 6132 6133 memset(&cmd, 0, sizeof cmd); 6134 cmd.code = IWN6000_PHY_CALIB_TEMP_OFFSET; 6135 cmd.ngroups = 1; 6136 cmd.isvalid = 1; 6137 if (sc->eeprom_temp != 0) 6138 cmd.offset = htole16(sc->eeprom_temp); 6139 else 6140 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET); 6141 DPRINTF(("setting radio sensor offset to %d\n", letoh16(cmd.offset))); 6142 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6143 } 6144 6145 int 6146 iwn2000_temp_offset_calib(struct iwn_softc *sc) 6147 { 6148 struct iwn2000_phy_calib_temp_offset cmd; 6149 6150 memset(&cmd, 0, sizeof cmd); 6151 cmd.code = IWN2000_PHY_CALIB_TEMP_OFFSET; 6152 cmd.ngroups = 1; 6153 cmd.isvalid = 1; 6154 if (sc->eeprom_rawtemp != 0) { 6155 cmd.offset_low = htole16(sc->eeprom_rawtemp); 6156 cmd.offset_high = htole16(sc->eeprom_temp); 6157 } else { 6158 cmd.offset_low = htole16(IWN_DEFAULT_TEMP_OFFSET); 6159 cmd.offset_high = htole16(IWN_DEFAULT_TEMP_OFFSET); 6160 } 6161 cmd.burnt_voltage_ref = htole16(sc->eeprom_voltage); 6162 DPRINTF(("setting radio sensor offset to %d:%d, voltage to %d\n", 6163 letoh16(cmd.offset_low), letoh16(cmd.offset_high), 6164 letoh16(cmd.burnt_voltage_ref))); 6165 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0); 6166 } 6167 6168 /* 6169 * This function is called after the runtime firmware notifies us of its 6170 * readiness (called in a process context). 6171 */ 6172 int 6173 iwn4965_post_alive(struct iwn_softc *sc) 6174 { 6175 int error, qid; 6176 6177 if ((error = iwn_nic_lock(sc)) != 0) 6178 return error; 6179 6180 /* Clear TX scheduler state in SRAM. */ 6181 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 6182 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0, 6183 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t)); 6184 6185 /* Set physical address of TX scheduler rings (1KB aligned). */ 6186 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 6187 6188 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 6189 6190 /* Disable chain mode for all our 16 queues. */ 6191 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0); 6192 6193 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) { 6194 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0); 6195 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6196 6197 /* Set scheduler window size. */ 6198 iwn_mem_write(sc, sc->sched_base + 6199 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ); 6200 /* Set scheduler frame limit. */ 6201 iwn_mem_write(sc, sc->sched_base + 6202 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4, 6203 IWN_SCHED_LIMIT << 16); 6204 } 6205 6206 /* Enable interrupts for all our 16 queues. */ 6207 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff); 6208 /* Identify TX FIFO rings (0-7). */ 6209 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff); 6210 6211 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6212 for (qid = 0; qid < 7; qid++) { 6213 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; 6214 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid), 6215 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1); 6216 } 6217 iwn_nic_unlock(sc); 6218 return 0; 6219 } 6220 6221 /* 6222 * This function is called after the initialization or runtime firmware 6223 * notifies us of its readiness (called in a process context). 6224 */ 6225 int 6226 iwn5000_post_alive(struct iwn_softc *sc) 6227 { 6228 int error, qid; 6229 6230 /* Switch to using ICT interrupt mode. */ 6231 iwn5000_ict_reset(sc); 6232 6233 if ((error = iwn_nic_lock(sc)) != 0) 6234 return error; 6235 6236 /* Clear TX scheduler state in SRAM. */ 6237 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR); 6238 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0, 6239 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t)); 6240 6241 /* Set physical address of TX scheduler rings (1KB aligned). */ 6242 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10); 6243 6244 /* Disable scheduler chain extension (enabled by default in HW). */ 6245 iwn_prph_write(sc, IWN5000_SCHED_CHAINEXT_EN, 0); 6246 6247 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY); 6248 6249 /* Enable chain mode for all queues, except command queue. */ 6250 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef); 6251 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0); 6252 6253 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) { 6254 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0); 6255 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0); 6256 6257 iwn_mem_write(sc, sc->sched_base + 6258 IWN5000_SCHED_QUEUE_OFFSET(qid), 0); 6259 /* Set scheduler window size and frame limit. */ 6260 iwn_mem_write(sc, sc->sched_base + 6261 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4, 6262 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ); 6263 } 6264 6265 /* Enable interrupts for all our 20 queues. */ 6266 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff); 6267 /* Identify TX FIFO rings (0-7). */ 6268 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff); 6269 6270 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ 6271 for (qid = 0; qid < 7; qid++) { 6272 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; 6273 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid), 6274 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]); 6275 } 6276 iwn_nic_unlock(sc); 6277 6278 /* Configure WiMAX coexistence for combo adapters. */ 6279 error = iwn5000_send_wimax_coex(sc); 6280 if (error != 0) { 6281 printf("%s: could not configure WiMAX coexistence\n", 6282 sc->sc_dev.dv_xname); 6283 return error; 6284 } 6285 if (sc->hw_type != IWN_HW_REV_TYPE_5150) { 6286 /* Perform crystal calibration. */ 6287 error = iwn5000_crystal_calib(sc); 6288 if (error != 0) { 6289 printf("%s: crystal calibration failed\n", 6290 sc->sc_dev.dv_xname); 6291 return error; 6292 } 6293 } 6294 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) { 6295 /* Query calibration from the initialization firmware. */ 6296 if ((error = iwn5000_query_calibration(sc)) != 0) { 6297 printf("%s: could not query calibration\n", 6298 sc->sc_dev.dv_xname); 6299 return error; 6300 } 6301 /* 6302 * We have the calibration results now, reboot with the 6303 * runtime firmware (call ourselves recursively!) 6304 */ 6305 iwn_hw_stop(sc); 6306 error = iwn_hw_init(sc); 6307 } else { 6308 /* Send calibration results to runtime firmware. */ 6309 error = iwn5000_send_calibration(sc); 6310 } 6311 return error; 6312 } 6313 6314 /* 6315 * The firmware boot code is small and is intended to be copied directly into 6316 * the NIC internal memory (no DMA transfer). 6317 */ 6318 int 6319 iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size) 6320 { 6321 int error, ntries; 6322 6323 size /= sizeof (uint32_t); 6324 6325 if ((error = iwn_nic_lock(sc)) != 0) 6326 return error; 6327 6328 /* Copy microcode image into NIC memory. */ 6329 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE, 6330 (const uint32_t *)ucode, size); 6331 6332 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0); 6333 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE); 6334 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size); 6335 6336 /* Start boot load now. */ 6337 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START); 6338 6339 /* Wait for transfer to complete. */ 6340 for (ntries = 0; ntries < 1000; ntries++) { 6341 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) & 6342 IWN_BSM_WR_CTRL_START)) 6343 break; 6344 DELAY(10); 6345 } 6346 if (ntries == 1000) { 6347 printf("%s: could not load boot firmware\n", 6348 sc->sc_dev.dv_xname); 6349 iwn_nic_unlock(sc); 6350 return ETIMEDOUT; 6351 } 6352 6353 /* Enable boot after power up. */ 6354 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN); 6355 6356 iwn_nic_unlock(sc); 6357 return 0; 6358 } 6359 6360 int 6361 iwn4965_load_firmware(struct iwn_softc *sc) 6362 { 6363 struct iwn_fw_info *fw = &sc->fw; 6364 struct iwn_dma_info *dma = &sc->fw_dma; 6365 int error; 6366 6367 /* Copy initialization sections into pre-allocated DMA-safe memory. */ 6368 memcpy(dma->vaddr, fw->init.data, fw->init.datasz); 6369 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->init.datasz, 6370 BUS_DMASYNC_PREWRITE); 6371 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6372 fw->init.text, fw->init.textsz); 6373 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 6374 fw->init.textsz, BUS_DMASYNC_PREWRITE); 6375 6376 /* Tell adapter where to find initialization sections. */ 6377 if ((error = iwn_nic_lock(sc)) != 0) 6378 return error; 6379 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6380 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz); 6381 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6382 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6383 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz); 6384 iwn_nic_unlock(sc); 6385 6386 /* Load firmware boot code. */ 6387 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz); 6388 if (error != 0) { 6389 printf("%s: could not load boot firmware\n", 6390 sc->sc_dev.dv_xname); 6391 return error; 6392 } 6393 /* Now press "execute". */ 6394 IWN_WRITE(sc, IWN_RESET, 0); 6395 6396 /* Wait at most one second for first alive notification. */ 6397 if ((error = tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(1))) != 0) { 6398 printf("%s: timeout waiting for adapter to initialize\n", 6399 sc->sc_dev.dv_xname); 6400 return error; 6401 } 6402 6403 /* Retrieve current temperature for initial TX power calibration. */ 6404 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz; 6405 sc->temp = iwn4965_get_temperature(sc); 6406 6407 /* Copy runtime sections into pre-allocated DMA-safe memory. */ 6408 memcpy(dma->vaddr, fw->main.data, fw->main.datasz); 6409 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, fw->main.datasz, 6410 BUS_DMASYNC_PREWRITE); 6411 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ, 6412 fw->main.text, fw->main.textsz); 6413 bus_dmamap_sync(sc->sc_dmat, dma->map, IWN4965_FW_DATA_MAXSZ, 6414 fw->main.textsz, BUS_DMASYNC_PREWRITE); 6415 6416 /* Tell adapter where to find runtime sections. */ 6417 if ((error = iwn_nic_lock(sc)) != 0) 6418 return error; 6419 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4); 6420 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz); 6421 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR, 6422 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4); 6423 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, 6424 IWN_FW_UPDATED | fw->main.textsz); 6425 iwn_nic_unlock(sc); 6426 6427 return 0; 6428 } 6429 6430 int 6431 iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst, 6432 const uint8_t *section, int size) 6433 { 6434 struct iwn_dma_info *dma = &sc->fw_dma; 6435 int error; 6436 6437 /* Copy firmware section into pre-allocated DMA-safe memory. */ 6438 memcpy(dma->vaddr, section, size); 6439 bus_dmamap_sync(sc->sc_dmat, dma->map, 0, size, BUS_DMASYNC_PREWRITE); 6440 6441 if ((error = iwn_nic_lock(sc)) != 0) 6442 return error; 6443 6444 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6445 IWN_FH_TX_CONFIG_DMA_PAUSE); 6446 6447 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst); 6448 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL), 6449 IWN_LOADDR(dma->paddr)); 6450 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL), 6451 IWN_HIADDR(dma->paddr) << 28 | size); 6452 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL), 6453 IWN_FH_TXBUF_STATUS_TBNUM(1) | 6454 IWN_FH_TXBUF_STATUS_TBIDX(1) | 6455 IWN_FH_TXBUF_STATUS_TFBD_VALID); 6456 6457 /* Kick Flow Handler to start DMA transfer. */ 6458 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL), 6459 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD); 6460 6461 iwn_nic_unlock(sc); 6462 6463 /* Wait at most five seconds for FH DMA transfer to complete. */ 6464 return tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(5)); 6465 } 6466 6467 int 6468 iwn5000_load_firmware(struct iwn_softc *sc) 6469 { 6470 struct iwn_fw_part *fw; 6471 int error; 6472 6473 /* Load the initialization firmware on first boot only. */ 6474 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ? 6475 &sc->fw.main : &sc->fw.init; 6476 6477 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE, 6478 fw->text, fw->textsz); 6479 if (error != 0) { 6480 printf("%s: could not load firmware %s section\n", 6481 sc->sc_dev.dv_xname, ".text"); 6482 return error; 6483 } 6484 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE, 6485 fw->data, fw->datasz); 6486 if (error != 0) { 6487 printf("%s: could not load firmware %s section\n", 6488 sc->sc_dev.dv_xname, ".data"); 6489 return error; 6490 } 6491 6492 /* Now press "execute". */ 6493 IWN_WRITE(sc, IWN_RESET, 0); 6494 return 0; 6495 } 6496 6497 /* 6498 * Extract text and data sections from a legacy firmware image. 6499 */ 6500 int 6501 iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw) 6502 { 6503 const uint32_t *ptr; 6504 size_t hdrlen = 24; 6505 uint32_t rev; 6506 6507 ptr = (const uint32_t *)fw->data; 6508 rev = letoh32(*ptr++); 6509 6510 /* Check firmware API version. */ 6511 if (IWN_FW_API(rev) <= 1) { 6512 printf("%s: bad firmware, need API version >=2\n", 6513 sc->sc_dev.dv_xname); 6514 return EINVAL; 6515 } 6516 if (IWN_FW_API(rev) >= 3) { 6517 /* Skip build number (version 2 header). */ 6518 hdrlen += 4; 6519 ptr++; 6520 } 6521 if (fw->size < hdrlen) { 6522 printf("%s: firmware too short: %zu bytes\n", 6523 sc->sc_dev.dv_xname, fw->size); 6524 return EINVAL; 6525 } 6526 fw->main.textsz = letoh32(*ptr++); 6527 fw->main.datasz = letoh32(*ptr++); 6528 fw->init.textsz = letoh32(*ptr++); 6529 fw->init.datasz = letoh32(*ptr++); 6530 fw->boot.textsz = letoh32(*ptr++); 6531 6532 /* Check that all firmware sections fit. */ 6533 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz + 6534 fw->init.textsz + fw->init.datasz + fw->boot.textsz) { 6535 printf("%s: firmware too short: %zu bytes\n", 6536 sc->sc_dev.dv_xname, fw->size); 6537 return EINVAL; 6538 } 6539 6540 /* Get pointers to firmware sections. */ 6541 fw->main.text = (const uint8_t *)ptr; 6542 fw->main.data = fw->main.text + fw->main.textsz; 6543 fw->init.text = fw->main.data + fw->main.datasz; 6544 fw->init.data = fw->init.text + fw->init.textsz; 6545 fw->boot.text = fw->init.data + fw->init.datasz; 6546 return 0; 6547 } 6548 6549 /* 6550 * Extract text and data sections from a TLV firmware image. 6551 */ 6552 int 6553 iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw, 6554 uint16_t alt) 6555 { 6556 const struct iwn_fw_tlv_hdr *hdr; 6557 const struct iwn_fw_tlv *tlv; 6558 const uint8_t *ptr, *end; 6559 uint64_t altmask; 6560 uint32_t len; 6561 6562 if (fw->size < sizeof (*hdr)) { 6563 printf("%s: firmware too short: %zu bytes\n", 6564 sc->sc_dev.dv_xname, fw->size); 6565 return EINVAL; 6566 } 6567 hdr = (const struct iwn_fw_tlv_hdr *)fw->data; 6568 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) { 6569 printf("%s: bad firmware signature 0x%08x\n", 6570 sc->sc_dev.dv_xname, letoh32(hdr->signature)); 6571 return EINVAL; 6572 } 6573 DPRINTF(("FW: \"%.64s\", build 0x%x\n", hdr->descr, 6574 letoh32(hdr->build))); 6575 6576 /* 6577 * Select the closest supported alternative that is less than 6578 * or equal to the specified one. 6579 */ 6580 altmask = letoh64(hdr->altmask); 6581 while (alt > 0 && !(altmask & (1ULL << alt))) 6582 alt--; /* Downgrade. */ 6583 DPRINTF(("using alternative %d\n", alt)); 6584 6585 ptr = (const uint8_t *)(hdr + 1); 6586 end = (const uint8_t *)(fw->data + fw->size); 6587 6588 /* Parse type-length-value fields. */ 6589 while (ptr + sizeof (*tlv) <= end) { 6590 tlv = (const struct iwn_fw_tlv *)ptr; 6591 len = letoh32(tlv->len); 6592 6593 ptr += sizeof (*tlv); 6594 if (ptr + len > end) { 6595 printf("%s: firmware too short: %zu bytes\n", 6596 sc->sc_dev.dv_xname, fw->size); 6597 return EINVAL; 6598 } 6599 /* Skip other alternatives. */ 6600 if (tlv->alt != 0 && tlv->alt != htole16(alt)) 6601 goto next; 6602 6603 switch (letoh16(tlv->type)) { 6604 case IWN_FW_TLV_MAIN_TEXT: 6605 fw->main.text = ptr; 6606 fw->main.textsz = len; 6607 break; 6608 case IWN_FW_TLV_MAIN_DATA: 6609 fw->main.data = ptr; 6610 fw->main.datasz = len; 6611 break; 6612 case IWN_FW_TLV_INIT_TEXT: 6613 fw->init.text = ptr; 6614 fw->init.textsz = len; 6615 break; 6616 case IWN_FW_TLV_INIT_DATA: 6617 fw->init.data = ptr; 6618 fw->init.datasz = len; 6619 break; 6620 case IWN_FW_TLV_BOOT_TEXT: 6621 fw->boot.text = ptr; 6622 fw->boot.textsz = len; 6623 break; 6624 case IWN_FW_TLV_ENH_SENS: 6625 if (len != 0) { 6626 printf("%s: TLV type %d has invalid size %u\n", 6627 sc->sc_dev.dv_xname, letoh16(tlv->type), 6628 len); 6629 goto next; 6630 } 6631 sc->sc_flags |= IWN_FLAG_ENH_SENS; 6632 break; 6633 case IWN_FW_TLV_PHY_CALIB: 6634 if (len != sizeof(uint32_t)) { 6635 printf("%s: TLV type %d has invalid size %u\n", 6636 sc->sc_dev.dv_xname, letoh16(tlv->type), 6637 len); 6638 goto next; 6639 } 6640 if (letoh32(*ptr) <= IWN5000_PHY_CALIB_MAX) { 6641 sc->reset_noise_gain = letoh32(*ptr); 6642 sc->noise_gain = letoh32(*ptr) + 1; 6643 } 6644 break; 6645 case IWN_FW_TLV_FLAGS: 6646 if (len < sizeof(uint32_t)) 6647 break; 6648 if (len % sizeof(uint32_t)) 6649 break; 6650 sc->tlv_feature_flags = letoh32(*ptr); 6651 DPRINTF(("feature: 0x%08x\n", sc->tlv_feature_flags)); 6652 break; 6653 default: 6654 DPRINTF(("TLV type %d not handled\n", 6655 letoh16(tlv->type))); 6656 break; 6657 } 6658 next: /* TLV fields are 32-bit aligned. */ 6659 ptr += (len + 3) & ~3; 6660 } 6661 return 0; 6662 } 6663 6664 int 6665 iwn_read_firmware(struct iwn_softc *sc) 6666 { 6667 struct iwn_fw_info *fw = &sc->fw; 6668 int error; 6669 6670 /* 6671 * Some PHY calibration commands are firmware-dependent; these 6672 * are the default values that will be overridden if 6673 * necessary. 6674 */ 6675 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN; 6676 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN; 6677 6678 memset(fw, 0, sizeof (*fw)); 6679 6680 /* Read firmware image from filesystem. */ 6681 if ((error = loadfirmware(sc->fwname, &fw->data, &fw->size)) != 0) { 6682 printf("%s: could not read firmware %s (error %d)\n", 6683 sc->sc_dev.dv_xname, sc->fwname, error); 6684 return error; 6685 } 6686 if (fw->size < sizeof (uint32_t)) { 6687 printf("%s: firmware too short: %zu bytes\n", 6688 sc->sc_dev.dv_xname, fw->size); 6689 free(fw->data, M_DEVBUF, fw->size); 6690 return EINVAL; 6691 } 6692 6693 /* Retrieve text and data sections. */ 6694 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */ 6695 error = iwn_read_firmware_leg(sc, fw); 6696 else 6697 error = iwn_read_firmware_tlv(sc, fw, 1); 6698 if (error != 0) { 6699 printf("%s: could not read firmware sections\n", 6700 sc->sc_dev.dv_xname); 6701 free(fw->data, M_DEVBUF, fw->size); 6702 return error; 6703 } 6704 6705 /* Make sure text and data sections fit in hardware memory. */ 6706 if (fw->main.textsz > sc->fw_text_maxsz || 6707 fw->main.datasz > sc->fw_data_maxsz || 6708 fw->init.textsz > sc->fw_text_maxsz || 6709 fw->init.datasz > sc->fw_data_maxsz || 6710 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ || 6711 (fw->boot.textsz & 3) != 0) { 6712 printf("%s: firmware sections too large\n", 6713 sc->sc_dev.dv_xname); 6714 free(fw->data, M_DEVBUF, fw->size); 6715 return EINVAL; 6716 } 6717 6718 /* We can proceed with loading the firmware. */ 6719 return 0; 6720 } 6721 6722 int 6723 iwn_clock_wait(struct iwn_softc *sc) 6724 { 6725 int ntries; 6726 6727 /* Set "initialization complete" bit. */ 6728 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6729 6730 /* Wait for clock stabilization. */ 6731 for (ntries = 0; ntries < 2500; ntries++) { 6732 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY) 6733 return 0; 6734 DELAY(10); 6735 } 6736 printf("%s: timeout waiting for clock stabilization\n", 6737 sc->sc_dev.dv_xname); 6738 return ETIMEDOUT; 6739 } 6740 6741 int 6742 iwn_apm_init(struct iwn_softc *sc) 6743 { 6744 pcireg_t reg; 6745 int error; 6746 6747 /* Disable L0s exit timer (NMI bug workaround). */ 6748 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER); 6749 /* Don't wait for ICH L0s (ICH bug workaround). */ 6750 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX); 6751 6752 /* Set FH wait threshold to max (HW bug under stress workaround). */ 6753 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000); 6754 6755 /* Enable HAP INTA to move adapter from L1a to L0s. */ 6756 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A); 6757 6758 /* Retrieve PCIe Active State Power Management (ASPM). */ 6759 reg = pci_conf_read(sc->sc_pct, sc->sc_pcitag, 6760 sc->sc_cap_off + PCI_PCIE_LCSR); 6761 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ 6762 if (reg & PCI_PCIE_LCSR_ASPM_L1) /* L1 Entry enabled. */ 6763 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6764 else 6765 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA); 6766 6767 if (sc->hw_type != IWN_HW_REV_TYPE_4965 && 6768 sc->hw_type <= IWN_HW_REV_TYPE_1000) 6769 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT); 6770 6771 /* Wait for clock stabilization before accessing prph. */ 6772 if ((error = iwn_clock_wait(sc)) != 0) 6773 return error; 6774 6775 if ((error = iwn_nic_lock(sc)) != 0) 6776 return error; 6777 if (sc->hw_type == IWN_HW_REV_TYPE_4965) { 6778 /* Enable DMA and BSM (Bootstrap State Machine). */ 6779 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6780 IWN_APMG_CLK_CTRL_DMA_CLK_RQT | 6781 IWN_APMG_CLK_CTRL_BSM_CLK_RQT); 6782 } else { 6783 /* Enable DMA. */ 6784 iwn_prph_write(sc, IWN_APMG_CLK_EN, 6785 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 6786 } 6787 DELAY(20); 6788 /* Disable L1-Active. */ 6789 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS); 6790 iwn_nic_unlock(sc); 6791 6792 return 0; 6793 } 6794 6795 void 6796 iwn_apm_stop_master(struct iwn_softc *sc) 6797 { 6798 int ntries; 6799 6800 /* Stop busmaster DMA activity. */ 6801 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER); 6802 for (ntries = 0; ntries < 100; ntries++) { 6803 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED) 6804 return; 6805 DELAY(10); 6806 } 6807 printf("%s: timeout waiting for master\n", sc->sc_dev.dv_xname); 6808 } 6809 6810 void 6811 iwn_apm_stop(struct iwn_softc *sc) 6812 { 6813 iwn_apm_stop_master(sc); 6814 6815 /* Reset the entire device. */ 6816 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW); 6817 DELAY(10); 6818 /* Clear "initialization complete" bit. */ 6819 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE); 6820 } 6821 6822 int 6823 iwn4965_nic_config(struct iwn_softc *sc) 6824 { 6825 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) { 6826 /* 6827 * I don't believe this to be correct but this is what the 6828 * vendor driver is doing. Probably the bits should not be 6829 * shifted in IWN_RFCFG_*. 6830 */ 6831 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6832 IWN_RFCFG_TYPE(sc->rfcfg) | 6833 IWN_RFCFG_STEP(sc->rfcfg) | 6834 IWN_RFCFG_DASH(sc->rfcfg)); 6835 } 6836 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6837 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6838 return 0; 6839 } 6840 6841 int 6842 iwn5000_nic_config(struct iwn_softc *sc) 6843 { 6844 uint32_t tmp; 6845 int error; 6846 6847 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) { 6848 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6849 IWN_RFCFG_TYPE(sc->rfcfg) | 6850 IWN_RFCFG_STEP(sc->rfcfg) | 6851 IWN_RFCFG_DASH(sc->rfcfg)); 6852 } 6853 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, 6854 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI); 6855 6856 if ((error = iwn_nic_lock(sc)) != 0) 6857 return error; 6858 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS); 6859 6860 if (sc->hw_type == IWN_HW_REV_TYPE_1000) { 6861 /* 6862 * Select first Switching Voltage Regulator (1.32V) to 6863 * solve a stability issue related to noisy DC2DC line 6864 * in the silicon of 1000 Series. 6865 */ 6866 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR); 6867 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK; 6868 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32; 6869 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp); 6870 } 6871 iwn_nic_unlock(sc); 6872 6873 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) { 6874 /* Use internal power amplifier only. */ 6875 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA); 6876 } 6877 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 || 6878 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) { 6879 /* Indicate that ROM calibration version is >=6. */ 6880 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6); 6881 } 6882 if (sc->hw_type == IWN_HW_REV_TYPE_6005) 6883 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2); 6884 if (sc->hw_type == IWN_HW_REV_TYPE_2030 || 6885 sc->hw_type == IWN_HW_REV_TYPE_2000 || 6886 sc->hw_type == IWN_HW_REV_TYPE_135 || 6887 sc->hw_type == IWN_HW_REV_TYPE_105) 6888 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_IQ_INVERT); 6889 return 0; 6890 } 6891 6892 /* 6893 * Take NIC ownership over Intel Active Management Technology (AMT). 6894 */ 6895 int 6896 iwn_hw_prepare(struct iwn_softc *sc) 6897 { 6898 int ntries; 6899 6900 /* Check if hardware is ready. */ 6901 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6902 for (ntries = 0; ntries < 5; ntries++) { 6903 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6904 IWN_HW_IF_CONFIG_NIC_READY) 6905 return 0; 6906 DELAY(10); 6907 } 6908 6909 /* Hardware not ready, force into ready state. */ 6910 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE); 6911 for (ntries = 0; ntries < 15000; ntries++) { 6912 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) & 6913 IWN_HW_IF_CONFIG_PREPARE_DONE)) 6914 break; 6915 DELAY(10); 6916 } 6917 if (ntries == 15000) 6918 return ETIMEDOUT; 6919 6920 /* Hardware should be ready now. */ 6921 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY); 6922 for (ntries = 0; ntries < 5; ntries++) { 6923 if (IWN_READ(sc, IWN_HW_IF_CONFIG) & 6924 IWN_HW_IF_CONFIG_NIC_READY) 6925 return 0; 6926 DELAY(10); 6927 } 6928 return ETIMEDOUT; 6929 } 6930 6931 int 6932 iwn_hw_init(struct iwn_softc *sc) 6933 { 6934 struct iwn_ops *ops = &sc->ops; 6935 int error, chnl, qid; 6936 6937 /* Clear pending interrupts. */ 6938 IWN_WRITE(sc, IWN_INT, 0xffffffff); 6939 6940 if ((error = iwn_apm_init(sc)) != 0) { 6941 printf("%s: could not power on adapter\n", 6942 sc->sc_dev.dv_xname); 6943 return error; 6944 } 6945 6946 /* Select VMAIN power source. */ 6947 if ((error = iwn_nic_lock(sc)) != 0) 6948 return error; 6949 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK); 6950 iwn_nic_unlock(sc); 6951 6952 /* Perform adapter-specific initialization. */ 6953 if ((error = ops->nic_config(sc)) != 0) 6954 return error; 6955 6956 /* Initialize RX ring. */ 6957 if ((error = iwn_nic_lock(sc)) != 0) 6958 return error; 6959 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0); 6960 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0); 6961 /* Set physical address of RX ring (256-byte aligned). */ 6962 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8); 6963 /* Set physical address of RX status (16-byte aligned). */ 6964 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4); 6965 /* Enable RX. */ 6966 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 6967 IWN_FH_RX_CONFIG_ENA | 6968 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */ 6969 IWN_FH_RX_CONFIG_IRQ_DST_HOST | 6970 IWN_FH_RX_CONFIG_SINGLE_FRAME | 6971 IWN_FH_RX_CONFIG_RB_TIMEOUT(0x11) | /* about 1/2 msec */ 6972 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG)); 6973 iwn_nic_unlock(sc); 6974 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7); 6975 6976 if ((error = iwn_nic_lock(sc)) != 0) 6977 return error; 6978 6979 /* Initialize TX scheduler. */ 6980 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 6981 6982 /* Set physical address of "keep warm" page (16-byte aligned). */ 6983 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4); 6984 6985 /* Initialize TX rings. */ 6986 for (qid = 0; qid < sc->ntxqs; qid++) { 6987 struct iwn_tx_ring *txq = &sc->txq[qid]; 6988 6989 /* Set physical address of TX ring (256-byte aligned). */ 6990 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid), 6991 txq->desc_dma.paddr >> 8); 6992 } 6993 iwn_nic_unlock(sc); 6994 6995 /* Enable DMA channels. */ 6996 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 6997 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 6998 IWN_FH_TX_CONFIG_DMA_ENA | 6999 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA); 7000 } 7001 7002 /* Clear "radio off" and "commands blocked" bits. */ 7003 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 7004 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED); 7005 7006 /* Clear pending interrupts. */ 7007 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7008 /* Enable interrupt coalescing. */ 7009 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8); 7010 /* Enable interrupts. */ 7011 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 7012 7013 /* _Really_ make sure "radio off" bit is cleared! */ 7014 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 7015 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL); 7016 7017 /* Enable shadow registers. */ 7018 if (sc->hw_type >= IWN_HW_REV_TYPE_6000) 7019 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff); 7020 7021 if ((error = ops->load_firmware(sc)) != 0) { 7022 printf("%s: could not load firmware\n", sc->sc_dev.dv_xname); 7023 return error; 7024 } 7025 /* Wait at most one second for firmware alive notification. */ 7026 if ((error = tsleep_nsec(sc, PCATCH, "iwninit", SEC_TO_NSEC(1))) != 0) { 7027 printf("%s: timeout waiting for adapter to initialize\n", 7028 sc->sc_dev.dv_xname); 7029 return error; 7030 } 7031 /* Do post-firmware initialization. */ 7032 return ops->post_alive(sc); 7033 } 7034 7035 void 7036 iwn_hw_stop(struct iwn_softc *sc) 7037 { 7038 int chnl, qid, ntries; 7039 7040 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO); 7041 7042 /* Disable interrupts. */ 7043 IWN_WRITE(sc, IWN_INT_MASK, 0); 7044 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7045 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff); 7046 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 7047 7048 /* Make sure we no longer hold the NIC lock. */ 7049 iwn_nic_unlock(sc); 7050 7051 /* Stop TX scheduler. */ 7052 iwn_prph_write(sc, sc->sched_txfact_addr, 0); 7053 7054 /* Stop all DMA channels. */ 7055 if (iwn_nic_lock(sc) == 0) { 7056 for (chnl = 0; chnl < sc->ndmachnls; chnl++) { 7057 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0); 7058 for (ntries = 0; ntries < 200; ntries++) { 7059 if (IWN_READ(sc, IWN_FH_TX_STATUS) & 7060 IWN_FH_TX_STATUS_IDLE(chnl)) 7061 break; 7062 DELAY(10); 7063 } 7064 } 7065 iwn_nic_unlock(sc); 7066 } 7067 7068 /* Stop RX ring. */ 7069 iwn_reset_rx_ring(sc, &sc->rxq); 7070 7071 /* Reset all TX rings. */ 7072 for (qid = 0; qid < sc->ntxqs; qid++) 7073 iwn_reset_tx_ring(sc, &sc->txq[qid]); 7074 7075 if (iwn_nic_lock(sc) == 0) { 7076 iwn_prph_write(sc, IWN_APMG_CLK_DIS, 7077 IWN_APMG_CLK_CTRL_DMA_CLK_RQT); 7078 iwn_nic_unlock(sc); 7079 } 7080 DELAY(5); 7081 /* Power OFF adapter. */ 7082 iwn_apm_stop(sc); 7083 } 7084 7085 int 7086 iwn_init(struct ifnet *ifp) 7087 { 7088 struct iwn_softc *sc = ifp->if_softc; 7089 struct ieee80211com *ic = &sc->sc_ic; 7090 int error; 7091 7092 memset(sc->bss_node_addr, 0, sizeof(sc->bss_node_addr)); 7093 sc->agg_queue_mask = 0; 7094 memset(sc->sc_tx_ba, 0, sizeof(sc->sc_tx_ba)); 7095 7096 if ((error = iwn_hw_prepare(sc)) != 0) { 7097 printf("%s: hardware not ready\n", sc->sc_dev.dv_xname); 7098 goto fail; 7099 } 7100 7101 /* Initialize interrupt mask to default value. */ 7102 sc->int_mask = IWN_INT_MASK_DEF; 7103 sc->sc_flags &= ~IWN_FLAG_USE_ICT; 7104 7105 /* Check that the radio is not disabled by hardware switch. */ 7106 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) { 7107 printf("%s: radio is disabled by hardware switch\n", 7108 sc->sc_dev.dv_xname); 7109 error = EPERM; /* :-) */ 7110 /* Re-enable interrupts. */ 7111 IWN_WRITE(sc, IWN_INT, 0xffffffff); 7112 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask); 7113 return error; 7114 } 7115 7116 /* Read firmware images from the filesystem. */ 7117 if ((error = iwn_read_firmware(sc)) != 0) { 7118 printf("%s: could not read firmware\n", sc->sc_dev.dv_xname); 7119 goto fail; 7120 } 7121 7122 /* Initialize hardware and upload firmware. */ 7123 error = iwn_hw_init(sc); 7124 free(sc->fw.data, M_DEVBUF, sc->fw.size); 7125 if (error != 0) { 7126 printf("%s: could not initialize hardware\n", 7127 sc->sc_dev.dv_xname); 7128 goto fail; 7129 } 7130 7131 /* Configure adapter now that it is ready. */ 7132 if ((error = iwn_config(sc)) != 0) { 7133 printf("%s: could not configure device\n", 7134 sc->sc_dev.dv_xname); 7135 goto fail; 7136 } 7137 7138 ifq_clr_oactive(&ifp->if_snd); 7139 ifp->if_flags |= IFF_RUNNING; 7140 7141 if (ic->ic_opmode != IEEE80211_M_MONITOR) 7142 ieee80211_begin_scan(ifp); 7143 else 7144 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 7145 7146 return 0; 7147 7148 fail: iwn_stop(ifp); 7149 return error; 7150 } 7151 7152 void 7153 iwn_stop(struct ifnet *ifp) 7154 { 7155 struct iwn_softc *sc = ifp->if_softc; 7156 struct ieee80211com *ic = &sc->sc_ic; 7157 7158 timeout_del(&sc->calib_to); 7159 ifp->if_timer = sc->sc_tx_timer = 0; 7160 ifp->if_flags &= ~IFF_RUNNING; 7161 ifq_clr_oactive(&ifp->if_snd); 7162 7163 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 7164 7165 /* Power OFF hardware. */ 7166 iwn_hw_stop(sc); 7167 } 7168