1 /* $OpenBSD: if_iwxreg.h,v 1.19 2021/04/25 15:32:21 stsp Exp $ */ 2 3 /*- 4 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 5 * which were used as the reference documentation for this implementation. 6 * 7 ****************************************************************************** 8 * 9 * This file is provided under a dual BSD/GPLv2 license. When using or 10 * redistributing this file, you may do so under either license. 11 * 12 * GPL LICENSE SUMMARY 13 * 14 * Copyright(c) 2017 Intel Deutschland GmbH 15 * Copyright(c) 2018 - 2019 Intel Corporation 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of version 2 of the GNU General Public License as 19 * published by the Free Software Foundation. 20 * 21 * This program is distributed in the hope that it will be useful, but 22 * WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 24 * General Public License for more details. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2017 Intel Deutschland GmbH 29 * Copyright(c) 2018 - 2019 Intel Corporation 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 36 * * Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * * Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in 40 * the documentation and/or other materials provided with the 41 * distribution. 42 * * Neither the name Intel Corporation nor the names of its 43 * contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 ***************************************************************************** 59 */ 60 61 62 /* maximmum number of DRAM map entries supported by FW */ 63 #define IWX_MAX_DRAM_ENTRY 64 64 #define IWX_CSR_CTXT_INFO_BA 0x40 65 66 /** 67 * enum iwx_context_info_flags - Context information control flags 68 * @IWX_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting 69 * the init done for driver command that configures several system modes 70 * @IWX_CTXT_INFO_EARLY_DEBUG: enable early debug 71 * @IWX_CTXT_INFO_ENABLE_CDMP: enable core dump 72 * @IWX_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size 73 * exponent, the actual size is 2**value, valid sizes are 8-2048. 74 * The value is four bits long. Maximum valid exponent is 12 75 * @IWX_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the 76 * default is short format - not supported by the driver) 77 * @IWX_CTXT_INFO_RB_SIZE_POS: RB size position 78 * (values are IWX_CTXT_INFO_RB_SIZE_*K) 79 * @IWX_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size 80 * @IWX_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size 81 * @IWX_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size 82 * @IWX_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size 83 * @IWX_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size 84 * @IWX_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size 85 * @IWX_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size 86 * @IWX_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size 87 * @IWX_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size 88 * @IWX_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size 89 */ 90 enum iwx_context_info_flags { 91 IWX_CTXT_INFO_AUTO_FUNC_INIT = (1 << 0), 92 IWX_CTXT_INFO_EARLY_DEBUG = (1 << 1), 93 IWX_CTXT_INFO_ENABLE_CDMP = (1 << 2), 94 IWX_CTXT_INFO_RB_CB_SIZE_POS = 4, 95 IWX_CTXT_INFO_TFD_FORMAT_LONG = (1 << 8), 96 IWX_CTXT_INFO_RB_SIZE_POS = 9, 97 IWX_CTXT_INFO_RB_SIZE_1K = 0x1, 98 IWX_CTXT_INFO_RB_SIZE_2K = 0x2, 99 IWX_CTXT_INFO_RB_SIZE_4K = 0x4, 100 IWX_CTXT_INFO_RB_SIZE_8K = 0x8, 101 IWX_CTXT_INFO_RB_SIZE_12K = 0x9, 102 IWX_CTXT_INFO_RB_SIZE_16K = 0xa, 103 IWX_CTXT_INFO_RB_SIZE_20K = 0xb, 104 IWX_CTXT_INFO_RB_SIZE_24K = 0xc, 105 IWX_CTXT_INFO_RB_SIZE_28K = 0xd, 106 IWX_CTXT_INFO_RB_SIZE_32K = 0xe, 107 }; 108 109 /* 110 * struct iwx_context_info_version - version structure 111 * @mac_id: SKU and revision id 112 * @version: context information version id 113 * @size: the size of the context information in DWs 114 */ 115 struct iwx_context_info_version { 116 uint16_t mac_id; 117 uint16_t version; 118 uint16_t size; 119 uint16_t reserved; 120 } __packed; 121 122 /* 123 * struct iwx_context_info_control - version structure 124 * @control_flags: context information flags see &enum iwx_context_info_flags 125 */ 126 struct iwx_context_info_control { 127 uint32_t control_flags; 128 uint32_t reserved; 129 } __packed; 130 131 /* 132 * struct iwx_context_info_dram - images DRAM map 133 * each entry in the map represents a DRAM chunk of up to 32 KB 134 * @umac_img: UMAC image DRAM map 135 * @lmac_img: LMAC image DRAM map 136 * @virtual_img: paged image DRAM map 137 */ 138 struct iwx_context_info_dram { 139 uint64_t umac_img[IWX_MAX_DRAM_ENTRY]; 140 uint64_t lmac_img[IWX_MAX_DRAM_ENTRY]; 141 uint64_t virtual_img[IWX_MAX_DRAM_ENTRY]; 142 } __packed; 143 144 /* 145 * struct iwx_context_info_rbd_cfg - RBDs configuration 146 * @free_rbd_addr: default queue free RB CB base address 147 * @used_rbd_addr: default queue used RB CB base address 148 * @status_wr_ptr: default queue used RB status write pointer 149 */ 150 struct iwx_context_info_rbd_cfg { 151 uint64_t free_rbd_addr; 152 uint64_t used_rbd_addr; 153 uint64_t status_wr_ptr; 154 } __packed; 155 156 /* 157 * struct iwx_context_info_hcmd_cfg - command queue configuration 158 * @cmd_queue_addr: address of command queue 159 * @cmd_queue_size: number of entries 160 */ 161 struct iwx_context_info_hcmd_cfg { 162 uint64_t cmd_queue_addr; 163 uint8_t cmd_queue_size; 164 uint8_t reserved[7]; 165 } __packed; 166 167 /* 168 * struct iwx_context_info_dump_cfg - Core Dump configuration 169 * @core_dump_addr: core dump (debug DRAM address) start address 170 * @core_dump_size: size, in DWs 171 */ 172 struct iwx_context_info_dump_cfg { 173 uint64_t core_dump_addr; 174 uint32_t core_dump_size; 175 uint32_t reserved; 176 } __packed; 177 178 /* 179 * struct iwx_context_info_pnvm_cfg - platform NVM data configuration 180 * @platform_nvm_addr: Platform NVM data start address 181 * @platform_nvm_size: size in DWs 182 */ 183 struct iwx_context_info_pnvm_cfg { 184 uint64_t platform_nvm_addr; 185 uint32_t platform_nvm_size; 186 uint32_t reserved; 187 } __packed; 188 189 /* 190 * struct iwx_context_info_early_dbg_cfg - early debug configuration for 191 * dumping DRAM addresses 192 * @early_debug_addr: early debug start address 193 * @early_debug_size: size in DWs 194 */ 195 struct iwx_context_info_early_dbg_cfg { 196 uint64_t early_debug_addr; 197 uint32_t early_debug_size; 198 uint32_t reserved; 199 } __packed; 200 201 /* 202 * struct iwx_context_info - device INIT configuration 203 * @version: version information of context info and HW 204 * @control: control flags of FH configurations 205 * @rbd_cfg: default RX queue configuration 206 * @hcmd_cfg: command queue configuration 207 * @dump_cfg: core dump data 208 * @edbg_cfg: early debug configuration 209 * @pnvm_cfg: platform nvm configuration 210 * @dram: firmware image addresses in DRAM 211 */ 212 struct iwx_context_info { 213 struct iwx_context_info_version version; 214 struct iwx_context_info_control control; 215 uint64_t reserved0; 216 struct iwx_context_info_rbd_cfg rbd_cfg; 217 struct iwx_context_info_hcmd_cfg hcmd_cfg; 218 uint32_t reserved1[4]; 219 struct iwx_context_info_dump_cfg dump_cfg; 220 struct iwx_context_info_early_dbg_cfg edbg_cfg; 221 struct iwx_context_info_pnvm_cfg pnvm_cfg; 222 uint32_t reserved2[16]; 223 struct iwx_context_info_dram dram; 224 uint32_t reserved3[16]; 225 } __packed; 226 227 #define IWX_MGMT_TID 15 228 229 #define IWX_MQ_RX_TABLE_SIZE 512 230 231 /* cb size is the exponent */ 232 #define IWX_RX_QUEUE_CB_SIZE(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1)) 233 234 /* 235 * CSR (control and status registers) 236 * 237 * CSR registers are mapped directly into PCI bus space, and are accessible 238 * whenever platform supplies power to device, even when device is in 239 * low power states due to driver-invoked device resets 240 * (e.g. IWX_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 241 * 242 * Use iwl_write32() and iwl_read32() family to access these registers; 243 * these provide simple PCI bus access, without waking up the MAC. 244 * Do not use iwl_write_direct32() family for these registers; 245 * no need to "grab nic access" via IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 246 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 247 * the CSR registers. 248 * 249 * NOTE: Device does need to be awake in order to read this memory 250 * via IWX_CSR_EEPROM and IWX_CSR_OTP registers 251 */ 252 #define IWX_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 253 #define IWX_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 254 #define IWX_CSR_INT (0x008) /* host interrupt status/ack */ 255 #define IWX_CSR_INT_MASK (0x00c) /* host interrupt enable */ 256 #define IWX_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 257 #define IWX_CSR_GPIO_IN (0x018) /* read external chip pins */ 258 #define IWX_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 259 #define IWX_CSR_GP_CNTRL (0x024) 260 261 /* 2nd byte of IWX_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 262 #define IWX_CSR_INT_PERIODIC_REG (0x005) 263 264 /* 265 * Hardware revision info 266 * Bit fields: 267 * 31-16: Reserved 268 * 15-4: Type of device: see IWX_CSR_HW_REV_TYPE_xxx definitions 269 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 270 * 1-0: "Dash" (-) value, as in A-1, etc. 271 */ 272 #define IWX_CSR_HW_REV (0x028) 273 274 #define IWX_CSR_GIO_REG (0x03C) 275 276 /* 277 * UCODE-DRIVER GP (general purpose) mailbox registers. 278 * SET/CLR registers set/clear bit(s) if "1" is written. 279 */ 280 #define IWX_CSR_UCODE_DRV_GP1 (0x054) 281 #define IWX_CSR_UCODE_DRV_GP1_SET (0x058) 282 #define IWX_CSR_UCODE_DRV_GP1_CLR (0x05c) 283 #define IWX_CSR_UCODE_DRV_GP2 (0x060) 284 285 #define IWX_CSR_MBOX_SET_REG (0x088) 286 #define IWX_CSR_MBOX_SET_REG_OS_ALIVE 0x20 287 288 #define IWX_CSR_DRAM_INT_TBL_REG (0x0A0) 289 #define IWX_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 290 291 292 /* GIO Chicken Bits (PCI Express bus link power management) */ 293 #define IWX_CSR_GIO_CHICKEN_BITS (0x100) 294 295 #define IWX_CSR_DBG_HPET_MEM_REG (0x240) 296 #define IWX_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 297 298 /* Bits for IWX_CSR_HW_IF_CONFIG_REG */ 299 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 300 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 301 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 302 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 303 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 304 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 305 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 306 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 307 308 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 309 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 310 #define IWX_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 311 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 312 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 313 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 314 315 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 316 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 317 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 318 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 319 #define IWX_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 320 #define IWX_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 321 #define IWX_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 322 323 #define IWX_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 324 #define IWX_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 325 326 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 327 * acknowledged (reset) by host writing "1" to flagged bits. */ 328 #define IWX_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 329 #define IWX_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 330 #define IWX_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 331 #define IWX_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 332 #define IWX_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 333 #define IWX_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 334 #define IWX_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 335 #define IWX_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 336 #define IWX_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 337 #define IWX_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 338 #define IWX_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 339 340 #define IWX_CSR_INI_SET_MASK (IWX_CSR_INT_BIT_FH_RX | \ 341 IWX_CSR_INT_BIT_HW_ERR | \ 342 IWX_CSR_INT_BIT_FH_TX | \ 343 IWX_CSR_INT_BIT_SW_ERR | \ 344 IWX_CSR_INT_BIT_RF_KILL | \ 345 IWX_CSR_INT_BIT_SW_RX | \ 346 IWX_CSR_INT_BIT_WAKEUP | \ 347 IWX_CSR_INT_BIT_ALIVE | \ 348 IWX_CSR_INT_BIT_RX_PERIODIC) 349 350 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 351 #define IWX_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ 352 #define IWX_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 353 #define IWX_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 354 #define IWX_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 355 #define IWX_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 356 #define IWX_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 357 358 #define IWX_CSR_FH_INT_RX_MASK (IWX_CSR_FH_INT_BIT_HI_PRIOR | \ 359 IWX_CSR_FH_INT_BIT_RX_CHNL1 | \ 360 IWX_CSR_FH_INT_BIT_RX_CHNL0) 361 362 #define IWX_CSR_FH_INT_TX_MASK (IWX_CSR_FH_INT_BIT_TX_CHNL1 | \ 363 IWX_CSR_FH_INT_BIT_TX_CHNL0) 364 365 /* RESET */ 366 #define IWX_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 367 #define IWX_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 368 #define IWX_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 369 #define IWX_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 370 #define IWX_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 371 #define IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 372 373 /* 374 * GP (general purpose) CONTROL REGISTER 375 * Bit fields: 376 * 27: HW_RF_KILL_SW 377 * Indicates state of (platform's) hardware RF-Kill switch 378 * 26-24: POWER_SAVE_TYPE 379 * Indicates current power-saving mode: 380 * 000 -- No power saving 381 * 001 -- MAC power-down 382 * 010 -- PHY (radio) power-down 383 * 011 -- Error 384 * 9-6: SYS_CONFIG 385 * Indicates current system configuration, reflecting pins on chip 386 * as forced high/low by device circuit board. 387 * 4: GOING_TO_SLEEP 388 * Indicates MAC is entering a power-saving sleep power-down. 389 * Not a good time to access device-internal resources. 390 * 3: MAC_ACCESS_REQ 391 * Host sets this to request and maintain MAC wakeup, to allow host 392 * access to device-internal resources. Host must wait for 393 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 394 * device registers. 395 * 2: INIT_DONE 396 * Host sets this to put device into fully operational D0 power mode. 397 * Host resets this after SW_RESET to put device into low power mode. 398 * 0: MAC_CLOCK_READY 399 * Indicates MAC (ucode processor, etc.) is powered up and can run. 400 * Internal resources are accessible. 401 * NOTE: This does not indicate that the processor is actually running. 402 * NOTE: This does not indicate that device has completed 403 * init or post-power-down restore of internal SRAM memory. 404 * Use IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 405 * SRAM is restored and uCode is in normal operation mode. 406 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 407 * do not need to save/restore it. 408 * NOTE: After device reset, this bit remains "0" until host sets 409 * INIT_DONE 410 */ 411 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 412 #define IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 413 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 414 #define IWX_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 415 416 #define IWX_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 417 418 #define IWX_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 419 #define IWX_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 420 #define IWX_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 421 422 423 /* HW REV */ 424 #define IWX_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 425 #define IWX_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 426 427 #define IWX_CSR_HW_REV_TYPE_MSK (0x000FFF0) 428 #define IWX_CSR_HW_REV_TYPE_QUZ (0x0000354) 429 430 /* CSR GIO */ 431 #define IWX_CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) 432 433 /* 434 * UCODE-DRIVER GP (general purpose) mailbox register 1 435 * Host driver and uCode write and/or read this register to communicate with 436 * each other. 437 * Bit fields: 438 * 4: UCODE_DISABLE 439 * Host sets this to request permanent halt of uCode, same as 440 * sending CARD_STATE command with "halt" bit set. 441 * 3: CT_KILL_EXIT 442 * Host sets this to request exit from CT_KILL state, i.e. host thinks 443 * device temperature is low enough to continue normal operation. 444 * 2: CMD_BLOCKED 445 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 446 * to release uCode to clear all Tx and command queues, enter 447 * unassociated mode, and power down. 448 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 449 * 1: SW_BIT_RFKILL 450 * Host sets this when issuing CARD_STATE command to request 451 * device sleep. 452 * 0: MAC_SLEEP 453 * uCode sets this when preparing a power-saving power-down. 454 * uCode resets this when power-up is complete and SRAM is sane. 455 * NOTE: device saves internal SRAM data to host when powering down, 456 * and must restore this data after powering back up. 457 * MAC_SLEEP is the best indication that restore is complete. 458 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 459 * do not need to save/restore it. 460 */ 461 #define IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 462 #define IWX_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 463 #define IWX_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 464 #define IWX_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 465 #define IWX_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 466 467 /* GIO Chicken Bits (PCI Express bus link power management) */ 468 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 469 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 470 471 /* HPET MEM debug */ 472 #define IWX_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 473 474 /* DRAM INT TABLE */ 475 #define IWX_CSR_DRAM_INT_TBL_ENABLE (1U << 31) 476 #define IWX_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 477 #define IWX_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 478 479 /* 22000 configuration registers */ 480 481 /* 482 * TFH Configuration register. 483 * 484 * BIT fields: 485 * 486 * Bits 3:0: 487 * Define the maximum number of pending read requests. 488 * Maximum configration value allowed is 0xC 489 * Bits 9:8: 490 * Define the maximum transfer size. (64 / 128 / 256) 491 * Bit 10: 492 * When bit is set and transfer size is set to 128B, the TFH will enable 493 * reading chunks of more than 64B only if the read address is aligned to 128B. 494 * In case of DRAM read address which is not aligned to 128B, the TFH will 495 * enable transfer size which doesn't cross 64B DRAM address boundary. 496 */ 497 #define IWX_TFH_TRANSFER_MODE (0x1F40) 498 #define IWX_TFH_TRANSFER_MAX_PENDING_REQ 0xc 499 #define IWX_TFH_CHUNK_SIZE_128 (1 << 8) 500 #define IWX_TFH_CHUNK_SPLIT_MODE (1 << 10) 501 502 /* 503 * Defines the offset address in dwords referring from the beginning of the 504 * Tx CMD which will be updated in DRAM. 505 * Note that the TFH offset address for Tx CMD update is always referring to 506 * the start of the TFD first TB. 507 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID 508 */ 509 #define IWX_TFH_TXCMD_UPDATE_CFG (0x1F48) 510 511 /* 512 * Controls TX DMA operation 513 * 514 * BIT fields: 515 * 516 * Bits 31:30: Enable the SRAM DMA channel. 517 * Turning on bit 31 will kick the SRAM2DRAM DMA. 518 * Note that the sram2dram may be enabled only after configuring the DRAM and 519 * SRAM addresses registers and the byte count register. 520 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When 521 * set to 1 - interrupt is sent to the driver 522 * Bit 0: Indicates the snoop configuration 523 */ 524 #define IWX_TFH_SRV_DMA_CHNL0_CTRL (0x1F60) 525 #define IWX_TFH_SRV_DMA_SNOOP (1 << 0) 526 #define IWX_TFH_SRV_DMA_TO_DRIVER (1 << 24) 527 #define IWX_TFH_SRV_DMA_START (1U << 31) 528 529 /* Defines the DMA SRAM write start address to transfer a data block */ 530 #define IWX_TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64) 531 532 /* Defines the 64bits DRAM start address to read the DMA data block from */ 533 #define IWX_TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68) 534 535 /* 536 * Defines the number of bytes to transfer from DRAM to SRAM. 537 * Note that this register may be configured with non-dword aligned size. 538 */ 539 #define IWX_TFH_SRV_DMA_CHNL0_BC (0x1F70) 540 541 /* 9000 rx series registers */ 542 543 #define IWX_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 544 #define IWX_RFH_Q_FRBDCB_BA_LSB(q) (IWX_RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 545 /* Write index table */ 546 #define IWX_RFH_Q0_FRBDCB_WIDX 0xA08080 547 #define IWX_RFH_Q_FRBDCB_WIDX(q) (IWX_RFH_Q0_FRBDCB_WIDX + (q) * 4) 548 /* Write index table - shadow registers */ 549 #define IWX_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 550 #define IWX_RFH_Q_FRBDCB_WIDX_TRG(q) (IWX_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 551 /* Read index table */ 552 #define IWX_RFH_Q0_FRBDCB_RIDX 0xA080C0 553 #define IWX_RFH_Q_FRBDCB_RIDX(q) (IWX_RFH_Q0_FRBDCB_RIDX + (q) * 4) 554 /* Used list table */ 555 #define IWX_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 556 #define IWX_RFH_Q_URBDCB_BA_LSB(q) (IWX_RFH_Q0_URBDCB_BA_LSB + (q) * 8) 557 /* Write index table */ 558 #define IWX_RFH_Q0_URBDCB_WIDX 0xA08180 559 #define IWX_RFH_Q_URBDCB_WIDX(q) (IWX_RFH_Q0_URBDCB_WIDX + (q) * 4) 560 #define IWX_RFH_Q0_URBDCB_VAID 0xA081C0 561 #define IWX_RFH_Q_URBDCB_VAID(q) (IWX_RFH_Q0_URBDCB_VAID + (q) * 4) 562 /* stts */ 563 #define IWX_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 564 #define IWX_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWX_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 565 566 #define IWX_RFH_Q0_ORB_WPTR_LSB 0xA08280 567 #define IWX_RFH_Q_ORB_WPTR_LSB(q) (IWX_RFH_Q0_ORB_WPTR_LSB + (q) * 8) 568 #define IWX_RFH_RBDBUF_RBD0_LSB 0xA08300 569 #define IWX_RFH_RBDBUF_RBD_LSB(q) (IWX_RFH_RBDBUF_RBD0_LSB + (q) * 8) 570 571 /** 572 * RFH Status Register 573 * 574 * Bit fields: 575 * 576 * Bit 29: RBD_FETCH_IDLE 577 * This status flag is set by the RFH when there is no active RBD fetch from 578 * DRAM. 579 * Once the RFH RBD controller starts fetching (or when there is a pending 580 * RBD read response from DRAM), this flag is immediately turned off. 581 * 582 * Bit 30: SRAM_DMA_IDLE 583 * This status flag is set by the RFH when there is no active transaction from 584 * SRAM to DRAM. 585 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 586 * 587 * Bit 31: RXF_DMA_IDLE 588 * This status flag is set by the RFH when there is no active transaction from 589 * RXF to DRAM. 590 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 591 */ 592 #define IWX_RFH_GEN_STATUS 0xA09808 593 #define IWX_RFH_GEN_STATUS_GEN3 0xA07824 594 #define IWX_RBD_FETCH_IDLE (1 << 29) 595 #define IWX_SRAM_DMA_IDLE (1 << 30) 596 #define IWX_RXF_DMA_IDLE (1U << 31) 597 598 /* DMA configuration */ 599 #define IWX_RFH_RXF_DMA_CFG 0xA09820 600 #define IWX_RFH_RXF_DMA_CFG_GEN3 0xA07880 601 /* RB size */ 602 #define IWX_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 603 #define IWX_RFH_RXF_DMA_RB_SIZE_POS 16 604 #define IWX_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 605 #define IWX_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 606 #define IWX_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 607 #define IWX_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 608 #define IWX_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 609 #define IWX_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWX_RFH_RXF_DMA_RB_SIZE_POS) 610 #define IWX_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWX_RFH_RXF_DMA_RB_SIZE_POS) 611 #define IWX_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWX_RFH_RXF_DMA_RB_SIZE_POS) 612 #define IWX_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWX_RFH_RXF_DMA_RB_SIZE_POS) 613 #define IWX_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWX_RFH_RXF_DMA_RB_SIZE_POS) 614 /* RB Circular Buffer size:defines the table sizes in RBD units */ 615 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 616 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_POS 20 617 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 618 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 619 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 620 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 621 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 622 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 623 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 624 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 625 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 626 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 627 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS 24 628 #define IWX_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS) 629 #define IWX_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 630 #define IWX_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 631 #define IWX_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 632 #define IWX_RFH_DMA_EN_ENABLE_VAL (1U << 31) 633 634 #define IWX_RFH_RXF_RXQ_ACTIVE 0xA0980C 635 636 #define IWX_RFH_GEN_CFG 0xA09800 637 #define IWX_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0) 638 #define IWX_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1) 639 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010 640 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000 641 /* the driver assumes everywhere that the default RXQ is 0 */ 642 #define IWX_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 643 644 /* end of 9000 rx series registers */ 645 646 /* 647 * This register is writen by driver and is read by uCode during boot flow. 648 * Note this address is cleared after MAC reset. 649 */ 650 #define IWX_UREG_UCODE_LOAD_STATUS (0xa05c40) 651 #define IWX_UREG_CPU_INIT_RUN (0xa05c44) 652 653 /* 654 * HBUS (Host-side Bus) 655 * 656 * HBUS registers are mapped directly into PCI bus space, but are used 657 * to indirectly access device's internal memory or registers that 658 * may be powered-down. 659 * 660 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 661 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 662 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 663 * internal resources. 664 * 665 * Do not use iwl_write32()/iwl_read32() family to access these registers; 666 * these provide only simple PCI bus access, without waking up the MAC. 667 */ 668 #define IWX_HBUS_BASE (0x400) 669 670 /* 671 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 672 * structures, error log, event log, verifying uCode load). 673 * First write to address register, then read from or write to data register 674 * to complete the job. Once the address register is set up, accesses to 675 * data registers auto-increment the address by one dword. 676 * Bit usage for address registers (read or write): 677 * 0-31: memory address within device 678 */ 679 #define IWX_HBUS_TARG_MEM_RADDR (IWX_HBUS_BASE+0x00c) 680 #define IWX_HBUS_TARG_MEM_WADDR (IWX_HBUS_BASE+0x010) 681 #define IWX_HBUS_TARG_MEM_WDAT (IWX_HBUS_BASE+0x018) 682 #define IWX_HBUS_TARG_MEM_RDAT (IWX_HBUS_BASE+0x01c) 683 684 /* 685 * Registers for accessing device's internal peripheral registers 686 * (e.g. SCD, BSM, etc.). First write to address register, 687 * then read from or write to data register to complete the job. 688 * Bit usage for address registers (read or write): 689 * 0-15: register address (offset) within device 690 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 691 */ 692 #define IWX_HBUS_TARG_PRPH_WADDR (IWX_HBUS_BASE+0x044) 693 #define IWX_HBUS_TARG_PRPH_RADDR (IWX_HBUS_BASE+0x048) 694 #define IWX_HBUS_TARG_PRPH_WDAT (IWX_HBUS_BASE+0x04c) 695 #define IWX_HBUS_TARG_PRPH_RDAT (IWX_HBUS_BASE+0x050) 696 697 /* enable the ID buf for read */ 698 #define IWX_WFPM_PS_CTL_CLR 0xa0300c 699 #define IWX_WFMP_MAC_ADDR_0 0xa03080 700 #define IWX_WFMP_MAC_ADDR_1 0xa03084 701 #define IWX_LMPM_PMG_EN 0xa01cec 702 #define IWX_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 703 #define IWX_RFIC_REG_RD 0xad0470 704 #define IWX_WFPM_CTRL_REG 0xa03030 705 #define IWX_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 706 #define IWX_ENABLE_WFPM 0x80000000 707 708 #define IWX_AUX_MISC_REG 0xa200b0 709 #define IWX_HW_STEP_LOCATION_BITS 24 710 711 #define IWX_AUX_MISC_MASTER1_EN 0xa20818 712 #define IWX_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 713 #define IWX_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 714 #define IWX_RSA_ENABLE 0xa24b08 715 #define IWX_PREG_AUX_BUS_WPROT_0 0xa04cc0 716 #define IWX_PREG_PRPH_WPROT_9000 0xa04ce0 717 #define IWX_PREG_PRPH_WPROT_22000 0xa04d00 718 #define IWX_SB_CFG_OVERRIDE_ADDR 0xa26c78 719 #define IWX_SB_CFG_OVERRIDE_ENABLE 0x8000 720 #define IWX_SB_CFG_BASE_OVERRIDE 0xa20000 721 #define IWX_SB_MODIFY_CFG_FLAG 0xa03088 722 #define IWX_UMAG_SB_CPU_1_STATUS 0xa038c0 723 #define IWX_UMAG_SB_CPU_2_STATUS 0xa038c4 724 725 #define IWX_UREG_CHICK 0xa05c00 726 #define IWX_UREG_CHICK_MSI_ENABLE (1 << 24) 727 #define IWX_UREG_CHICK_MSIX_ENABLE (1 << 25) 728 729 #define IWX_HPM_DEBUG 0xa03440 730 #define IWX_PERSISTENCE_BIT (1 << 12) 731 #define IWX_PREG_WFPM_ACCESS (1 << 12) 732 733 #define IWX_HPM_HIPM_GEN_CFG 0xa03458 734 #define IWX_HPM_HIPM_GEN_CFG_CR_PG_EN (1 << 0) 735 #define IWX_HPM_HIPM_GEN_CFG_CR_SLP_EN (1 << 1) 736 #define IWX_HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE (1 << 10) 737 738 /* 739 * Per-Tx-queue write pointer (index, really!) 740 * Indicates index to next TFD that driver will fill (1 past latest filled). 741 * Bit usage: 742 * 0-7: queue write index 743 * 11-8: queue selector 744 */ 745 #define IWX_HBUS_TARG_WRPTR (IWX_HBUS_BASE+0x060) 746 747 /********************************************************** 748 * CSR values 749 **********************************************************/ 750 /* 751 * host interrupt timeout value 752 * used with setting interrupt coalescing timer 753 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 754 * 755 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 756 */ 757 #define IWX_HOST_INT_TIMEOUT_MAX (0xFF) 758 #define IWX_HOST_INT_TIMEOUT_DEF (0x40) 759 #define IWX_HOST_INT_TIMEOUT_MIN (0x0) 760 #define IWX_HOST_INT_OPER_MODE (1U << 31) 761 762 /***************************************************************************** 763 * MSIX related registers * 764 *****************************************************************************/ 765 766 #define IWX_CSR_MSIX_BASE (0x2000) 767 #define IWX_CSR_MSIX_FH_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x800) 768 #define IWX_CSR_MSIX_FH_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x804) 769 #define IWX_CSR_MSIX_HW_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x808) 770 #define IWX_CSR_MSIX_HW_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x80C) 771 #define IWX_CSR_MSIX_AUTOMASK_ST_AD (IWX_CSR_MSIX_BASE + 0x810) 772 #define IWX_CSR_MSIX_RX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x880) 773 #define IWX_CSR_MSIX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x890) 774 #define IWX_CSR_MSIX_PENDING_PBA_AD (IWX_CSR_MSIX_BASE + 0x1000) 775 #define IWX_CSR_MSIX_RX_IVAR(cause) (IWX_CSR_MSIX_RX_IVAR_AD_REG + (cause)) 776 #define IWX_CSR_MSIX_IVAR(cause) (IWX_CSR_MSIX_IVAR_AD_REG + (cause)) 777 778 /* 779 * Causes for the FH register interrupts 780 */ 781 enum msix_fh_int_causes { 782 IWX_MSIX_FH_INT_CAUSES_Q0 = (1 << 0), 783 IWX_MSIX_FH_INT_CAUSES_Q1 = (1 << 1), 784 IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16), 785 IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17), 786 IWX_MSIX_FH_INT_CAUSES_S2D = (1 << 19), 787 IWX_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21), 788 }; 789 790 /* 791 * Causes for the HW register interrupts 792 */ 793 enum msix_hw_int_causes { 794 IWX_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0), 795 IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1), 796 IWX_MSIX_HW_INT_CAUSES_REG_IPC = (1 << 1), 797 IWX_MSIX_HW_INT_CAUSES_REG_IML = (1 << 2), 798 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5), 799 IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6), 800 IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7), 801 IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8), 802 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25), 803 IWX_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26), 804 IWX_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27), 805 IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29), 806 IWX_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30), 807 }; 808 809 /* 810 * Registers to map causes to vectors 811 */ 812 enum msix_ivar_for_cause { 813 IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0, 814 IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1, 815 IWX_MSIX_IVAR_CAUSE_S2D = 0x3, 816 IWX_MSIX_IVAR_CAUSE_FH_ERR = 0x5, 817 IWX_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10, 818 IWX_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11, 819 IWX_MSIX_IVAR_CAUSE_REG_IML = 0x12, 820 IWX_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16, 821 IWX_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17, 822 IWX_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18, 823 IWX_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29, 824 IWX_MSIX_IVAR_CAUSE_REG_SCD = 0x2a, 825 IWX_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b, 826 IWX_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d, 827 IWX_MSIX_IVAR_CAUSE_REG_HAP = 0x2e, 828 }; 829 830 #define IWX_MSIX_AUTO_CLEAR_CAUSE (0 << 7) 831 #define IWX_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7) 832 833 /** 834 * uCode API flags 835 * @IWX_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 836 * was a separate TLV but moved here to save space. 837 * @IWX_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 838 * treats good CRC threshold as a boolean 839 * @IWX_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 840 * @IWX_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 841 * @IWX_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 842 * @IWX_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 843 * @IWX_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 844 * offload profile config command. 845 * @IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 846 * (rather than two) IPv6 addresses 847 * @IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 848 * from the probe request template. 849 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 850 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 851 * @IWX_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 852 * single bound interface). 853 * @IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 854 * @IWX_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 855 * @IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 856 * @IWX_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 857 * @IWX_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 858 * 859 */ 860 #define IWX_UCODE_TLV_FLAGS_PAN (1 << 0) 861 #define IWX_UCODE_TLV_FLAGS_NEWSCAN (1 << 1) 862 #define IWX_UCODE_TLV_FLAGS_MFP (1 << 2) 863 #define IWX_UCODE_TLV_FLAGS_P2P (1 << 3) 864 #define IWX_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4) 865 #define IWX_UCODE_TLV_FLAGS_SHORT_BL (1 << 7) 866 #define IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10) 867 #define IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12) 868 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15) 869 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16) 870 #define IWX_UCODE_TLV_FLAGS_P2P_PS (1 << 21) 871 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22) 872 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23) 873 #define IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24) 874 #define IWX_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25) 875 #define IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26) 876 #define IWX_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29) 877 #define IWX_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30) 878 #define IWX_UCODE_TLV_FLAGS_LTE_COEX (1U << 31) 879 880 #define IWX_UCODE_TLV_FLAG_BITS \ 881 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 882 883 /** 884 * uCode TLV api 885 * @IWX_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 886 * longer than the passive one, which is essential for fragmented scan. 887 * @IWX_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 888 * @IWX_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 889 * @IWX_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 890 * @IWX_UCODE_TLV_API_NEW_VERSION: new versioning format 891 * @IWX_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 892 * (command version 3) that supports per-chain limits 893 * @IWX_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan 894 * iteration complete notification, and the timestamp reported for RX 895 * received during scan, are reported in TSF of the mac specified in the 896 * scan request. 897 * @IWX_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of 898 * ADD_MODIFY_STA_KEY_API_S_VER_2. 899 * @IWX_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement. 900 * @IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 901 * instead of 3. 902 * @IWX_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used 903 * @IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG: This ucode supports v3 of 904 * SCAN_CONFIG_DB_CMD_API_S. 905 * 906 * @IWX_NUM_UCODE_TLV_API: number of bits used 907 */ 908 #define IWX_UCODE_TLV_API_FRAGMENTED_SCAN 8 909 #define IWX_UCODE_TLV_API_WIFI_MCC_UPDATE 9 910 #define IWX_UCODE_TLV_API_WIDE_CMD_HDR 14 911 #define IWX_UCODE_TLV_API_LQ_SS_PARAMS 18 912 #define IWX_UCODE_TLV_API_NEW_VERSION 20 913 #define IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY 24 914 #define IWX_UCODE_TLV_API_TX_POWER_CHAIN 27 915 #define IWX_UCODE_TLV_API_SCAN_TSF_REPORT 28 916 #define IWX_UCODE_TLV_API_TKIP_MIC_KEYS 29 917 #define IWX_UCODE_TLV_API_STA_TYPE 30 918 #define IWX_UCODE_TLV_API_NAN2_VER2 31 919 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL 32 920 #define IWX_UCODE_TLV_API_NEW_RX_STATS 35 921 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42 922 #define IWX_UCODE_TLV_API_BEACON_FILTER_V4 47 923 #define IWX_UCODE_TLV_API_REGULATORY_NVM_INFO 48 924 #define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56 925 #define IWX_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58 926 #define IWX_NUM_UCODE_TLV_API 128 927 928 #define IWX_UCODE_TLV_API_BITS \ 929 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS" 930 931 /** 932 * uCode capabilities 933 * @IWX_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 934 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 935 * @IWX_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 936 * @IWX_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 937 * @IWX_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 938 * @IWX_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 939 * @IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 940 * tx power value into TPC Report action frame and Link Measurement Report 941 * action frame 942 * @IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 943 * channel in DS parameter set element in probe requests. 944 * @IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 945 * probe requests. 946 * @IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 947 * @IWX_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 948 * which also implies support for the scheduler configuration command 949 * @IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 950 * @IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 951 * @IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 952 * @IWX_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 953 * @IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 954 * @IWX_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 955 * @IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 956 * @IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 957 * @IWX_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 958 * @IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 959 * sources for the MCC. This TLV bit is a future replacement to 960 * IWX_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 961 * is supported. 962 * @IWX_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 963 * @IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 964 * @IWX_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 965 * @IWX_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 966 * 0=no support) 967 * @IWx_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS: firmware supports ultra high band 968 * (6 GHz). 969 * @IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 970 * @IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 971 * @IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 972 * @IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 973 * antenna the beacon should be transmitted 974 * @IWX_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 975 * from AP and will send it upon d0i3 exit. 976 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 977 * @IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 978 * @IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 979 * thresholds reporting 980 * @IWX_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 981 * @IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 982 * regular image. 983 * @IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 984 * memory addresses from the firmware. 985 * @IWX_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 986 * @IWX_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 987 * 0=no support) 988 * 989 * @IWX_NUM_UCODE_TLV_CAPA: number of bits used 990 */ 991 #define IWX_UCODE_TLV_CAPA_D0I3_SUPPORT 0 992 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT 1 993 #define IWX_UCODE_TLV_CAPA_UMAC_SCAN 2 994 #define IWX_UCODE_TLV_CAPA_BEAMFORMER 3 995 #define IWX_UCODE_TLV_CAPA_TOF_SUPPORT 5 996 #define IWX_UCODE_TLV_CAPA_TDLS_SUPPORT 6 997 #define IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8 998 #define IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9 999 #define IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10 1000 #define IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11 1001 #define IWX_UCODE_TLV_CAPA_DQA_SUPPORT 12 1002 #define IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13 1003 #define IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17 1004 #define IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18 1005 #define IWX_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19 1006 #define IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20 1007 #define IWX_UCODE_TLV_CAPA_CSUM_SUPPORT 21 1008 #define IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22 1009 #define IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26 1010 #define IWX_UCODE_TLV_CAPA_BT_COEX_PLCR 28 1011 #define IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC 29 1012 #define IWX_UCODE_TLV_CAPA_BT_COEX_RRC 30 1013 #define IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT 31 1014 #define IWX_UCODE_TLV_CAPA_NAN_SUPPORT 34 1015 #define IWX_UCODE_TLV_CAPA_UMAC_UPLOAD 35 1016 #define IWX_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39 1017 #define IWX_UCODE_TLV_CAPA_CDB_SUPPORT 40 1018 #define IWX_UCODE_TLV_CAPA_TLC_OFFLOAD 43 1019 #define IWX_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44 1020 #define IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48 1021 #define IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64 1022 #define IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65 1023 #define IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67 1024 #define IWX_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68 1025 #define IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71 1026 #define IWX_UCODE_TLV_CAPA_BEACON_STORING 72 1027 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73 1028 #define IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW 74 1029 #define IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75 1030 #define IWX_UCODE_TLV_CAPA_CTDP_SUPPORT 76 1031 #define IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77 1032 #define IWX_UCODE_TLV_CAPA_LMAC_UPLOAD 79 1033 #define IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80 1034 #define IWX_UCODE_TLV_CAPA_LQM_SUPPORT 81 1035 #define IWX_UCODE_TLV_CAPA_LED_CMD_SUPPORT 88 1036 1037 #define IWX_NUM_UCODE_TLV_CAPA 128 1038 1039 /* 1040 * For 16.0 uCode and above, there is no differentiation between sections, 1041 * just an offset to the HW address. 1042 */ 1043 #define IWX_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 1044 #define IWX_PAGING_SEPARATOR_SECTION 0xAAAABBBB 1045 1046 /* uCode version contains 4 values: Major/Minor/API/Serial */ 1047 #define IWX_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 1048 #define IWX_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 1049 #define IWX_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 1050 #define IWX_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 1051 1052 /* 1053 * Calibration control struct. 1054 * Sent as part of the phy configuration command. 1055 * @flow_trigger: bitmap for which calibrations to perform according to 1056 * flow triggers. 1057 * @event_trigger: bitmap for which calibrations to perform according to 1058 * event triggers. 1059 */ 1060 struct iwx_tlv_calib_ctrl { 1061 uint32_t flow_trigger; 1062 uint32_t event_trigger; 1063 } __packed; 1064 1065 #define IWX_FW_PHY_CFG_RADIO_TYPE_POS 0 1066 #define IWX_FW_PHY_CFG_RADIO_TYPE (0x3 << IWX_FW_PHY_CFG_RADIO_TYPE_POS) 1067 #define IWX_FW_PHY_CFG_RADIO_STEP_POS 2 1068 #define IWX_FW_PHY_CFG_RADIO_STEP (0x3 << IWX_FW_PHY_CFG_RADIO_STEP_POS) 1069 #define IWX_FW_PHY_CFG_RADIO_DASH_POS 4 1070 #define IWX_FW_PHY_CFG_RADIO_DASH (0x3 << IWX_FW_PHY_CFG_RADIO_DASH_POS) 1071 #define IWX_FW_PHY_CFG_TX_CHAIN_POS 16 1072 #define IWX_FW_PHY_CFG_TX_CHAIN (0xf << IWX_FW_PHY_CFG_TX_CHAIN_POS) 1073 #define IWX_FW_PHY_CFG_RX_CHAIN_POS 20 1074 #define IWX_FW_PHY_CFG_RX_CHAIN (0xf << IWX_FW_PHY_CFG_RX_CHAIN_POS) 1075 1076 /** 1077 * struct iwx_fw_cipher_scheme - a cipher scheme supported by FW. 1078 * @cipher: a cipher suite selector 1079 * @flags: cipher scheme flags (currently reserved for a future use) 1080 * @hdr_len: a size of MPDU security header 1081 * @pn_len: a size of PN 1082 * @pn_off: an offset of pn from the beginning of the security header 1083 * @key_idx_off: an offset of key index byte in the security header 1084 * @key_idx_mask: a bit mask of key_idx bits 1085 * @key_idx_shift: bit shift needed to get key_idx 1086 * @mic_len: mic length in bytes 1087 * @hw_cipher: a HW cipher index used in host commands 1088 */ 1089 struct iwx_fw_cipher_scheme { 1090 uint32_t cipher; 1091 uint8_t flags; 1092 uint8_t hdr_len; 1093 uint8_t pn_len; 1094 uint8_t pn_off; 1095 uint8_t key_idx_off; 1096 uint8_t key_idx_mask; 1097 uint8_t key_idx_shift; 1098 uint8_t mic_len; 1099 uint8_t hw_cipher; 1100 } __packed; 1101 1102 /** 1103 * struct iwx_fw_cscheme_list - a cipher scheme list 1104 * @size: a number of entries 1105 * @cs: cipher scheme entries 1106 */ 1107 struct iwx_fw_cscheme_list { 1108 uint8_t size; 1109 struct iwx_fw_cipher_scheme cs[]; 1110 } __packed; 1111 1112 /* v1/v2 uCode file layout */ 1113 struct iwx_ucode_header { 1114 uint32_t ver; /* major/minor/API/serial */ 1115 union { 1116 struct { 1117 uint32_t inst_size; /* bytes of runtime code */ 1118 uint32_t data_size; /* bytes of runtime data */ 1119 uint32_t init_size; /* bytes of init code */ 1120 uint32_t init_data_size; /* bytes of init data */ 1121 uint32_t boot_size; /* bytes of bootstrap code */ 1122 uint8_t data[0]; /* in same order as sizes */ 1123 } v1; 1124 struct { 1125 uint32_t build; /* build number */ 1126 uint32_t inst_size; /* bytes of runtime code */ 1127 uint32_t data_size; /* bytes of runtime data */ 1128 uint32_t init_size; /* bytes of init code */ 1129 uint32_t init_data_size; /* bytes of init data */ 1130 uint32_t boot_size; /* bytes of bootstrap code */ 1131 uint8_t data[0]; /* in same order as sizes */ 1132 } v2; 1133 } u; 1134 }; 1135 1136 /* 1137 * new TLV uCode file layout 1138 * 1139 * The new TLV file format contains TLVs, that each specify 1140 * some piece of data. 1141 */ 1142 1143 #define IWX_UCODE_TLV_INVALID 0 /* unused */ 1144 #define IWX_UCODE_TLV_INST 1 1145 #define IWX_UCODE_TLV_DATA 2 1146 #define IWX_UCODE_TLV_INIT 3 1147 #define IWX_UCODE_TLV_INIT_DATA 4 1148 #define IWX_UCODE_TLV_BOOT 5 1149 #define IWX_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */ 1150 #define IWX_UCODE_TLV_PAN 7 1151 #define IWX_UCODE_TLV_RUNT_EVTLOG_PTR 8 1152 #define IWX_UCODE_TLV_RUNT_EVTLOG_SIZE 9 1153 #define IWX_UCODE_TLV_RUNT_ERRLOG_PTR 10 1154 #define IWX_UCODE_TLV_INIT_EVTLOG_PTR 11 1155 #define IWX_UCODE_TLV_INIT_EVTLOG_SIZE 12 1156 #define IWX_UCODE_TLV_INIT_ERRLOG_PTR 13 1157 #define IWX_UCODE_TLV_ENHANCE_SENS_TBL 14 1158 #define IWX_UCODE_TLV_PHY_CALIBRATION_SIZE 15 1159 #define IWX_UCODE_TLV_WOWLAN_INST 16 1160 #define IWX_UCODE_TLV_WOWLAN_DATA 17 1161 #define IWX_UCODE_TLV_FLAGS 18 1162 #define IWX_UCODE_TLV_SEC_RT 19 1163 #define IWX_UCODE_TLV_SEC_INIT 20 1164 #define IWX_UCODE_TLV_SEC_WOWLAN 21 1165 #define IWX_UCODE_TLV_DEF_CALIB 22 1166 #define IWX_UCODE_TLV_PHY_SKU 23 1167 #define IWX_UCODE_TLV_SECURE_SEC_RT 24 1168 #define IWX_UCODE_TLV_SECURE_SEC_INIT 25 1169 #define IWX_UCODE_TLV_SECURE_SEC_WOWLAN 26 1170 #define IWX_UCODE_TLV_NUM_OF_CPU 27 1171 #define IWX_UCODE_TLV_CSCHEME 28 1172 #define IWX_UCODE_TLV_API_CHANGES_SET 29 1173 #define IWX_UCODE_TLV_ENABLED_CAPABILITIES 30 1174 #define IWX_UCODE_TLV_N_SCAN_CHANNELS 31 1175 #define IWX_UCODE_TLV_PAGING 32 1176 #define IWX_UCODE_TLV_SEC_RT_USNIFFER 34 1177 #define IWX_UCODE_TLV_SDIO_ADMA_ADDR 35 1178 #define IWX_UCODE_TLV_FW_VERSION 36 1179 #define IWX_UCODE_TLV_FW_DBG_DEST 38 1180 #define IWX_UCODE_TLV_FW_DBG_CONF 39 1181 #define IWX_UCODE_TLV_FW_DBG_TRIGGER 40 1182 #define IWX_UCODE_TLV_CMD_VERSIONS 48 1183 #define IWX_UCODE_TLV_FW_GSCAN_CAPA 50 1184 #define IWX_UCODE_TLV_FW_MEM_SEG 51 1185 #define IWX_UCODE_TLV_IML 52 1186 #define IWX_UCODE_TLV_FW_FMAC_API_VERSION 53 1187 #define IWX_UCODE_TLV_UMAC_DEBUG_ADDRS 54 1188 #define IWX_UCODE_TLV_LMAC_DEBUG_ADDRS 55 1189 #define IWX_UCODE_TLV_FW_RECOVERY_INFO 57 1190 #define IWX_UCODE_TLV_FW_FMAC_RECOVERY_INFO 59 1191 #define IWX_UCODE_TLV_FW_FSEQ_VERSION 60 1192 1193 #define IWX_UCODE_TLV_DEBUG_BASE 0x1000005 1194 #define IWX_UCODE_TLV_TYPE_DEBUG_INFO (IWX_UCODE_TLV_DEBUG_BASE + 0) 1195 #define IWX_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWX_UCODE_TLV_DEBUG_BASE + 1) 1196 #define IWX_UCODE_TLV_TYPE_HCMD (IWX_UCODE_TLV_DEBUG_BASE + 2) 1197 #define IWX_UCODE_TLV_TYPE_REGIONS (IWX_UCODE_TLV_DEBUG_BASE + 3) 1198 #define IWX_UCODE_TLV_TYPE_TRIGGERS (IWX_UCODE_TLV_DEBUG_BASE + 4) 1199 #define IWX_UCODE_TLV_DEBUG_MAX IWX_UCODE_TLV_TYPE_TRIGGERS 1200 1201 1202 struct iwx_ucode_tlv { 1203 uint32_t type; /* see above */ 1204 uint32_t length; /* not including type/length fields */ 1205 uint8_t data[0]; 1206 }; 1207 1208 struct iwx_ucode_api { 1209 uint32_t api_index; 1210 uint32_t api_flags; 1211 } __packed; 1212 1213 struct iwx_ucode_capa { 1214 uint32_t api_index; 1215 uint32_t api_capa; 1216 } __packed; 1217 1218 #define IWX_TLV_UCODE_MAGIC 0x0a4c5749 1219 1220 struct iwx_tlv_ucode_header { 1221 /* 1222 * The TLV style ucode header is distinguished from 1223 * the v1/v2 style header by first four bytes being 1224 * zero, as such is an invalid combination of 1225 * major/minor/API/serial versions. 1226 */ 1227 uint32_t zero; 1228 uint32_t magic; 1229 uint8_t human_readable[64]; 1230 uint32_t ver; /* major/minor/API/serial */ 1231 uint32_t build; 1232 uint64_t ignore; 1233 /* 1234 * The data contained herein has a TLV layout, 1235 * see above for the TLV header and types. 1236 * Note that each TLV is padded to a length 1237 * that is a multiple of 4 for alignment. 1238 */ 1239 uint8_t data[0]; 1240 }; 1241 1242 /* 1243 * Registers in this file are internal, not PCI bus memory mapped. 1244 * Driver accesses these via IWX_HBUS_TARG_PRPH_* registers. 1245 */ 1246 #define IWX_PRPH_BASE (0x00000) 1247 #define IWX_PRPH_END (0xFFFFF) 1248 1249 /****************************/ 1250 /* Flow Handler Definitions */ 1251 /****************************/ 1252 1253 /** 1254 * struct iwx_rb_status - receive buffer status 1255 * host memory mapped FH registers 1256 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1257 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1258 * @finished_rb_num [0:11] - Indicates the index of the current RB 1259 * in which the last frame was written to 1260 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1261 * which was transferred 1262 */ 1263 struct iwx_rb_status { 1264 uint16_t closed_rb_num; 1265 uint16_t closed_fr_num; 1266 uint16_t finished_rb_num; 1267 uint16_t finished_fr_nam; 1268 uint32_t unused; 1269 } __packed; 1270 1271 1272 #define IWX_TFD_QUEUE_SIZE_MAX (256) 1273 #define IWX_TFD_QUEUE_SIZE_MAX_GEN3 (65536) 1274 /* cb size is the exponent - 3 */ 1275 #define IWX_TFD_QUEUE_CB_SIZE(x) (IWX_RX_QUEUE_CB_SIZE(x) - 3) 1276 #define IWX_TFD_QUEUE_SIZE_BC_DUP (64) 1277 #define IWX_TFD_QUEUE_BC_SIZE (IWX_TFD_QUEUE_SIZE_MAX + \ 1278 IWX_TFD_QUEUE_SIZE_BC_DUP) 1279 #define IWX_TFD_QUEUE_BC_SIZE_GEN3 (IWX_TFD_QUEUE_SIZE_MAX_GEN3 + \ 1280 IWX_TFD_QUEUE_SIZE_BC_DUP) 1281 #define IWX_TFH_NUM_TBS 25 1282 1283 /** 1284 * struct iwx_tfh_tb transmit buffer descriptor within transmit frame descriptor 1285 * 1286 * This structure contains dma address and length of transmission address 1287 * 1288 * @tb_len length of the tx buffer 1289 * @addr 64 bits dma address 1290 */ 1291 struct iwx_tfh_tb { 1292 uint16_t tb_len; 1293 uint64_t addr; 1294 } __packed; 1295 1296 /** 1297 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1298 * Both driver and device share these circular buffers, each of which must be 1299 * contiguous 256 TFDs. 1300 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes 1301 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes 1302 * 1303 * Each TFD contains pointer/size information for up to 25 data buffers 1304 * in host DRAM. These buffers collectively contain the (one) frame described 1305 * by the TFD. Each buffer must be a single contiguous block of memory within 1306 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1307 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1308 * Tx frame, up to 8 KBytes in size. 1309 * 1310 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1311 */ 1312 1313 /** 1314 * struct iwx_tfh_tfd - Transmit Frame Descriptor (TFD) 1315 * @ num_tbs 0-4 number of active tbs 1316 * 5 -15 reserved 1317 * @ tbs[25] transmit frame buffer descriptors 1318 * @ __pad padding 1319 */ 1320 struct iwx_tfh_tfd { 1321 uint16_t num_tbs; 1322 struct iwx_tfh_tb tbs[IWX_TFH_NUM_TBS]; 1323 uint32_t __pad; 1324 } __packed; 1325 1326 /* Fixed (non-configurable) rx data from phy */ 1327 1328 /** 1329 * struct iwx_agn_schedq_bc_tbl scheduler byte count table 1330 * base physical address provided by IWX_SCD_DRAM_BASE_ADDR 1331 * @tfd_offset 0-12 - tx command byte count 1332 * 12-16 - station index 1333 */ 1334 struct iwx_agn_scd_bc_tbl { 1335 uint16_t tfd_offset[IWX_TFD_QUEUE_BC_SIZE]; 1336 } __packed; 1337 1338 /** 1339 * struct iwx_gen3_bc_tbl scheduler byte count table gen3 1340 * For 22560 and on: 1341 * @tfd_offset: 0-12 - tx command byte count 1342 * 12-13 - number of 64 byte chunks 1343 * 14-16 - reserved 1344 */ 1345 struct iwx_gen3_bc_tbl { 1346 uint16_t tfd_offset[IWX_TFD_QUEUE_BC_SIZE_GEN3]; 1347 } __packed; 1348 1349 /* Maximum number of Tx queues. */ 1350 #define IWX_MAX_QUEUES 31 1351 1352 /** 1353 * DQA - Dynamic Queue Allocation -introduction 1354 * 1355 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi 1356 * to allow dynamic allocation of queues on-demand, rather than allocate them 1357 * statically ahead of time. Ideally, we would like to allocate one queue 1358 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2 1359 * even if it also needs to send traffic to a sleeping STA1, without being 1360 * blocked by the sleeping station. 1361 * 1362 * Although the queues in DQA mode are dynamically allocated, there are still 1363 * some queues that are statically allocated: 1364 * TXQ #0 - command queue 1365 * TXQ #1 - aux frames 1366 * TXQ #2 - P2P device frames 1367 * TXQ #3 - P2P GO/SoftAP GCAST/BCAST frames 1368 * TXQ #4 - BSS DATA frames queue 1369 * TXQ #5-8 - non-QoS data, QoS no-data, and MGMT frames queue pool 1370 * TXQ #9 - P2P GO/SoftAP probe responses 1371 * TXQ #10-31 - QoS DATA frames queue pool (for Tx aggregation) 1372 */ 1373 1374 /* static DQA Tx queue numbers */ 1375 #define IWX_DQA_CMD_QUEUE 0 1376 #define IWX_DQA_AUX_QUEUE 1 1377 #define IWX_DQA_P2P_DEVICE_QUEUE 2 1378 #define IWX_DQA_INJECT_MONITOR_QUEUE 2 1379 #define IWX_DQA_GCAST_QUEUE 3 1380 #define IWX_DQA_BSS_CLIENT_QUEUE 4 1381 #define IWX_DQA_MIN_MGMT_QUEUE 5 1382 #define IWX_DQA_MAX_MGMT_QUEUE 8 1383 #define IWX_DQA_AP_PROBE_RESP_QUEUE 9 1384 #define IWX_DQA_MIN_DATA_QUEUE 10 1385 #define IWX_DQA_MAX_DATA_QUEUE 31 1386 1387 #define IWX_TX_FIFO_BK 0 1388 #define IWX_TX_FIFO_BE 1 1389 #define IWX_TX_FIFO_VI 2 1390 #define IWX_TX_FIFO_VO 3 1391 #define IWX_TX_FIFO_MCAST 5 1392 #define IWX_TX_FIFO_CMD 7 1393 1394 enum iwx_gen2_tx_fifo { 1395 IWX_GEN2_TX_FIFO_CMD = 0, 1396 IWX_GEN2_EDCA_TX_FIFO_BK, 1397 IWX_GEN2_EDCA_TX_FIFO_BE, 1398 IWX_GEN2_EDCA_TX_FIFO_VI, 1399 IWX_GEN2_EDCA_TX_FIFO_VO, 1400 IWX_GEN2_TRIG_TX_FIFO_BK, 1401 IWX_GEN2_TRIG_TX_FIFO_BE, 1402 IWX_GEN2_TRIG_TX_FIFO_VI, 1403 IWX_GEN2_TRIG_TX_FIFO_VO, 1404 }; 1405 1406 /** 1407 * TXQ config options 1408 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue 1409 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format 1410 */ 1411 #define IWX_TX_QUEUE_CFG_ENABLE_QUEUE (1 << 0) 1412 #define IWX_TX_QUEUE_CFG_TFD_SHORT_FORMAT (1 << 1) 1413 1414 #define IWX_DEFAULT_QUEUE_SIZE IWX_TFD_QUEUE_SIZE_MAX 1415 1416 /** 1417 * struct iwx_tx_queue_cfg_cmd - txq hw scheduler config command 1418 * @sta_id: station id 1419 * @tid: tid of the queue 1420 * @flags: see &enum iwl_tx_queue_cfg_actions 1421 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3. 1422 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs) 1423 * @byte_cnt_addr: address of byte count table 1424 * @tfdq_addr: address of TFD circular buffer 1425 */ 1426 struct iwx_tx_queue_cfg_cmd { 1427 uint8_t sta_id; 1428 uint8_t tid; 1429 uint16_t flags; 1430 uint32_t cb_size; 1431 uint64_t byte_cnt_addr; 1432 uint64_t tfdq_addr; 1433 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */ 1434 1435 /** 1436 * struct iwx_tx_queue_cfg_rsp - response to txq hw scheduler config 1437 * @queue_number: queue number assigned to this RA -TID 1438 * @flags: set on failure 1439 * @write_pointer: initial value for write pointer 1440 * @reserved: reserved 1441 */ 1442 struct iwx_tx_queue_cfg_rsp { 1443 uint16_t queue_number; 1444 uint16_t flags; 1445 uint16_t write_pointer; 1446 uint16_t reserved; 1447 } __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */ 1448 1449 1450 /* 1451 * Commands 1452 */ 1453 #define IWX_ALIVE 0x1 1454 #define IWX_REPLY_ERROR 0x2 1455 #define IWX_INIT_COMPLETE_NOTIF 0x4 1456 1457 /* PHY context commands */ 1458 #define IWX_PHY_CONTEXT_CMD 0x8 1459 #define IWX_DBG_CFG 0x9 1460 1461 /* UMAC scan commands */ 1462 #define IWX_SCAN_ITERATION_COMPLETE_UMAC 0xb5 1463 #define IWX_SCAN_CFG_CMD 0xc 1464 #define IWX_SCAN_REQ_UMAC 0xd 1465 #define IWX_SCAN_ABORT_UMAC 0xe 1466 #define IWX_SCAN_COMPLETE_UMAC 0xf 1467 1468 /* station table */ 1469 #define IWX_ADD_STA_KEY 0x17 1470 #define IWX_ADD_STA 0x18 1471 #define IWX_REMOVE_STA 0x19 1472 1473 /* TX */ 1474 #define IWX_TX_CMD 0x1c 1475 #define IWX_TXPATH_FLUSH 0x1e 1476 #define IWX_MGMT_MCAST_KEY 0x1f 1477 1478 /* scheduler config */ 1479 #define IWX_SCD_QUEUE_CFG 0x1d 1480 1481 /* global key */ 1482 #define IWX_WEP_KEY 0x20 1483 1484 /* MAC and Binding commands */ 1485 #define IWX_MAC_CONTEXT_CMD 0x28 1486 #define IWX_TIME_EVENT_CMD 0x29 /* both CMD and response */ 1487 #define IWX_TIME_EVENT_NOTIFICATION 0x2a 1488 #define IWX_BINDING_CONTEXT_CMD 0x2b 1489 #define IWX_TIME_QUOTA_CMD 0x2c 1490 #define IWX_NON_QOS_TX_COUNTER_CMD 0x2d 1491 1492 /* Calibration */ 1493 #define IWX_TEMPERATURE_NOTIFICATION 0x62 1494 #define IWX_CALIBRATION_CFG_CMD 0x65 1495 #define IWX_CALIBRATION_RES_NOTIFICATION 0x66 1496 #define IWX_CALIBRATION_COMPLETE_NOTIFICATION 0x67 1497 #define IWX_RADIO_VERSION_NOTIFICATION 0x68 1498 1499 /* Phy */ 1500 #define IWX_PHY_CONFIGURATION_CMD 0x6a 1501 1502 /* Power - legacy power table command */ 1503 #define IWX_POWER_TABLE_CMD 0x77 1504 #define IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78 1505 #define IWX_LTR_CONFIG 0xee 1506 1507 /* NVM */ 1508 #define IWX_NVM_ACCESS_CMD 0x88 1509 1510 #define IWX_SET_CALIB_DEFAULT_CMD 0x8e 1511 1512 #define IWX_BEACON_NOTIFICATION 0x90 1513 #define IWX_BEACON_TEMPLATE_CMD 0x91 1514 #define IWX_TX_ANT_CONFIGURATION_CMD 0x98 1515 #define IWX_BT_CONFIG 0x9b 1516 #define IWX_STATISTICS_CMD 0x9c 1517 #define IWX_STATISTICS_NOTIFICATION 0x9d 1518 #define IWX_REDUCE_TX_POWER_CMD 0x9f 1519 1520 /* RF-KILL commands and notifications */ 1521 #define IWX_CARD_STATE_CMD 0xa0 1522 #define IWX_CARD_STATE_NOTIFICATION 0xa1 1523 1524 #define IWX_MISSED_BEACONS_NOTIFICATION 0xa2 1525 1526 #define IWX_MFUART_LOAD_NOTIFICATION 0xb1 1527 1528 /* Power - new power table command */ 1529 #define IWX_MAC_PM_POWER_TABLE 0xa9 1530 1531 #define IWX_REPLY_RX_PHY_CMD 0xc0 1532 #define IWX_REPLY_RX_MPDU_CMD 0xc1 1533 #define IWX_BA_NOTIF 0xc5 1534 1535 /* Location Aware Regulatory */ 1536 #define IWX_MCC_UPDATE_CMD 0xc8 1537 #define IWX_MCC_CHUB_UPDATE_CMD 0xc9 1538 1539 /* BT Coex */ 1540 #define IWX_BT_COEX_PRIO_TABLE 0xcc 1541 #define IWX_BT_COEX_PROT_ENV 0xcd 1542 #define IWX_BT_PROFILE_NOTIFICATION 0xce 1543 #define IWX_BT_COEX_CI 0x5d 1544 1545 #define IWX_REPLY_SF_CFG_CMD 0xd1 1546 #define IWX_REPLY_BEACON_FILTERING_CMD 0xd2 1547 1548 /* DTS measurements */ 1549 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER 0xdc 1550 #define IWX_DTS_MEASUREMENT_NOTIFICATION 0xdd 1551 1552 #define IWX_REPLY_DEBUG_CMD 0xf0 1553 #define IWX_DEBUG_LOG_MSG 0xf7 1554 1555 #define IWX_MCAST_FILTER_CMD 0xd0 1556 1557 /* D3 commands/notifications */ 1558 #define IWX_D3_CONFIG_CMD 0xd3 1559 #define IWX_PROT_OFFLOAD_CONFIG_CMD 0xd4 1560 #define IWX_OFFLOADS_QUERY_CMD 0xd5 1561 #define IWX_REMOTE_WAKE_CONFIG_CMD 0xd6 1562 1563 /* for WoWLAN in particular */ 1564 #define IWX_WOWLAN_PATTERNS 0xe0 1565 #define IWX_WOWLAN_CONFIGURATION 0xe1 1566 #define IWX_WOWLAN_TSC_RSC_PARAM 0xe2 1567 #define IWX_WOWLAN_TKIP_PARAM 0xe3 1568 #define IWX_WOWLAN_KEK_KCK_MATERIAL 0xe4 1569 #define IWX_WOWLAN_GET_STATUSES 0xe5 1570 #define IWX_WOWLAN_TX_POWER_PER_DB 0xe6 1571 1572 /* and for NetDetect */ 1573 #define IWX_NET_DETECT_CONFIG_CMD 0x54 1574 #define IWX_NET_DETECT_PROFILES_QUERY_CMD 0x56 1575 #define IWX_NET_DETECT_PROFILES_CMD 0x57 1576 #define IWX_NET_DETECT_HOTSPOTS_CMD 0x58 1577 #define IWX_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59 1578 1579 /* system group command IDs */ 1580 #define IWX_FSEQ_VER_MISMATCH_NOTIFICATION 0xff 1581 1582 #define IWX_REPLY_MAX 0xff 1583 1584 /* PHY_OPS subcommand IDs */ 1585 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0 1586 #define IWX_CTDP_CONFIG_CMD 0x03 1587 #define IWX_TEMP_REPORTING_THRESHOLDS_CMD 0x04 1588 #define IWX_CT_KILL_NOTIFICATION 0xFE 1589 #define IWX_DTS_MEASUREMENT_NOTIF_WIDE 0xFF 1590 1591 /* command groups */ 1592 #define IWX_LEGACY_GROUP 0x0 1593 #define IWX_LONG_GROUP 0x1 1594 #define IWX_SYSTEM_GROUP 0x2 1595 #define IWX_MAC_CONF_GROUP 0x3 1596 #define IWX_PHY_OPS_GROUP 0x4 1597 #define IWX_DATA_PATH_GROUP 0x5 1598 #define IWX_PROT_OFFLOAD_GROUP 0xb 1599 #define IWX_REGULATORY_AND_NVM_GROUP 0xc 1600 1601 /* SYSTEM_GROUP group subcommand IDs */ 1602 1603 #define IWX_SHARED_MEM_CFG_CMD 0x00 1604 #define IWX_SOC_CONFIGURATION_CMD 0x01 1605 #define IWX_INIT_EXTENDED_CFG_CMD 0x03 1606 #define IWX_FW_ERROR_RECOVERY_CMD 0x07 1607 1608 /* DATA_PATH group subcommand IDs */ 1609 #define IWX_DQA_ENABLE_CMD 0x00 1610 #define IWX_TLC_MNG_CONFIG_CMD 0x0f 1611 #define IWX_RX_NO_DATA_NOTIF 0xf5 1612 #define IWX_TLC_MNG_UPDATE_NOTIF 0xf7 1613 1614 /* REGULATORY_AND_NVM group subcommand IDs */ 1615 #define IWX_NVM_ACCESS_COMPLETE 0x00 1616 #define IWX_NVM_GET_INFO 0x02 1617 1618 /* 1619 * struct iwx_dqa_enable_cmd 1620 * @cmd_queue: the TXQ number of the command queue 1621 */ 1622 struct iwx_dqa_enable_cmd { 1623 uint32_t cmd_queue; 1624 } __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */ 1625 1626 /** 1627 * struct iwx_cmd_response - generic response struct for most commands 1628 * @status: status of the command asked, changes for each one 1629 */ 1630 struct iwx_cmd_response { 1631 uint32_t status; 1632 }; 1633 1634 /* 1635 * struct iwx_tx_ant_cfg_cmd 1636 * @valid: valid antenna configuration 1637 */ 1638 struct iwx_tx_ant_cfg_cmd { 1639 uint32_t valid; 1640 } __packed; 1641 1642 /* 1643 * Calibration control struct. 1644 * Sent as part of the phy configuration command. 1645 * @flow_trigger: bitmap for which calibrations to perform according to 1646 * flow triggers. 1647 * @event_trigger: bitmap for which calibrations to perform according to 1648 * event triggers. 1649 */ 1650 struct iwx_calib_ctrl { 1651 uint32_t flow_trigger; 1652 uint32_t event_trigger; 1653 } __packed; 1654 1655 /* This defines the bitmap of various calibrations to enable in both 1656 * init ucode and runtime ucode through IWX_CALIBRATION_CFG_CMD. 1657 */ 1658 #define IWX_CALIB_CFG_XTAL_IDX (1 << 0) 1659 #define IWX_CALIB_CFG_TEMPERATURE_IDX (1 << 1) 1660 #define IWX_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2) 1661 #define IWX_CALIB_CFG_PAPD_IDX (1 << 3) 1662 #define IWX_CALIB_CFG_TX_PWR_IDX (1 << 4) 1663 #define IWX_CALIB_CFG_DC_IDX (1 << 5) 1664 #define IWX_CALIB_CFG_BB_FILTER_IDX (1 << 6) 1665 #define IWX_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7) 1666 #define IWX_CALIB_CFG_TX_IQ_IDX (1 << 8) 1667 #define IWX_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9) 1668 #define IWX_CALIB_CFG_RX_IQ_IDX (1 << 10) 1669 #define IWX_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11) 1670 #define IWX_CALIB_CFG_SENSITIVITY_IDX (1 << 12) 1671 #define IWX_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13) 1672 #define IWX_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14) 1673 #define IWX_CALIB_CFG_ANT_COUPLING_IDX (1 << 15) 1674 #define IWX_CALIB_CFG_DAC_IDX (1 << 16) 1675 #define IWX_CALIB_CFG_ABS_IDX (1 << 17) 1676 #define IWX_CALIB_CFG_AGC_IDX (1 << 18) 1677 1678 /* 1679 * Phy configuration command. 1680 */ 1681 struct iwx_phy_cfg_cmd { 1682 uint32_t phy_cfg; 1683 struct iwx_calib_ctrl calib_control; 1684 } __packed; 1685 1686 #define IWX_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1687 #define IWX_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1688 #define IWX_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1689 #define IWX_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1690 #define IWX_PHY_CFG_TX_CHAIN_A (1 << 8) 1691 #define IWX_PHY_CFG_TX_CHAIN_B (1 << 9) 1692 #define IWX_PHY_CFG_TX_CHAIN_C (1 << 10) 1693 #define IWX_PHY_CFG_RX_CHAIN_A (1 << 12) 1694 #define IWX_PHY_CFG_RX_CHAIN_B (1 << 13) 1695 #define IWX_PHY_CFG_RX_CHAIN_C (1 << 14) 1696 1697 #define IWX_MAX_DTS_TRIPS 8 1698 1699 /** 1700 * struct iwx_ct_kill_notif - CT-kill entry notification 1701 * 1702 * @temperature: the current temperature in celsius 1703 * @reserved: reserved 1704 */ 1705 struct iwx_ct_kill_notif { 1706 uint16_t temperature; 1707 uint16_t reserved; 1708 } __packed; /* GRP_PHY_CT_KILL_NTF */ 1709 1710 /** 1711 * struct iwx_temp_report_ths_cmd - set temperature thresholds 1712 * (IWX_TEMP_REPORTING_THRESHOLDS_CMD) 1713 * 1714 * @num_temps: number of temperature thresholds passed 1715 * @thresholds: array with the thresholds to be configured 1716 */ 1717 struct iwx_temp_report_ths_cmd { 1718 uint32_t num_temps; 1719 uint16_t thresholds[IWX_MAX_DTS_TRIPS]; 1720 } __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */ 1721 1722 /* 1723 * channel flags in NVM 1724 * @IWX_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 1725 * @IWX_NVM_CHANNEL_IBSS: usable as an IBSS channel 1726 * @IWX_NVM_CHANNEL_ACTIVE: active scanning allowed 1727 * @IWX_NVM_CHANNEL_RADAR: radar detection required 1728 * @IWX_NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 1729 * @IWX_NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 1730 * on same channel on 2.4 or same UNII band on 5.2 1731 * @IWX_NVM_CHANNEL_DFS: dynamic freq selection candidate 1732 * @IWX_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 1733 * @IWX_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 1734 * @IWX_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 1735 * @IWX_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 1736 * @IWX_NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 1737 */ 1738 #define IWX_NVM_CHANNEL_VALID (1 << 0) 1739 #define IWX_NVM_CHANNEL_IBSS (1 << 1) 1740 #define IWX_NVM_CHANNEL_ACTIVE (1 << 3) 1741 #define IWX_NVM_CHANNEL_RADAR (1 << 4) 1742 #define IWX_NVM_CHANNEL_INDOOR_ONLY (1 << 5) 1743 #define IWX_NVM_CHANNEL_GO_CONCURRENT (1 << 6) 1744 #define IWX_NVM_CHANNEL_DFS (1 << 7) 1745 #define IWX_NVM_CHANNEL_WIDE (1 << 8) 1746 #define IWX_NVM_CHANNEL_40MHZ (1 << 9) 1747 #define IWX_NVM_CHANNEL_80MHZ (1 << 10) 1748 #define IWX_NVM_CHANNEL_160MHZ (1 << 11) 1749 #define IWX_NVM_CHANNEL_DC_HIGH (1 << 12) 1750 1751 /** 1752 * struct iwx_nvm_access_complete_cmd - NVM_ACCESS commands are completed 1753 * @reserved: reserved 1754 */ 1755 struct iwx_nvm_access_complete_cmd { 1756 uint32_t reserved; 1757 } __packed; /* NVM_ACCESS_COMPLETE_CMD_API_S_VER_1 */ 1758 1759 /* 1760 * struct iwx_nvm_get_info - request to get NVM data 1761 */ 1762 struct iwx_nvm_get_info { 1763 uint32_t reserved; 1764 } __packed; /* REGULATORY_NVM_GET_INFO_CMD_API_S_VER_1 */ 1765 1766 /** 1767 * enum iwx_nvm_info_general_flags - flags in NVM_GET_INFO resp 1768 * @NVM_GENERAL_FLAGS_EMPTY_OTP: 1 if OTP is empty 1769 */ 1770 #define IWX_NVM_GENERAL_FLAGS_EMPTY_OTP (1 << 0) 1771 1772 /** 1773 * struct iwx_nvm_get_info_general - general NVM data 1774 * @flags: bit 0: 1 - empty, 0 - non-empty 1775 * @nvm_version: nvm version 1776 * @board_type: board type 1777 * @n_hw_addrs: number of reserved MAC addresses 1778 */ 1779 struct iwx_nvm_get_info_general { 1780 uint32_t flags; 1781 uint16_t nvm_version; 1782 uint8_t board_type; 1783 uint8_t n_hw_addrs; 1784 } __packed; /* REGULATORY_NVM_GET_INFO_GENERAL_S_VER_2 */ 1785 1786 /** 1787 * iwx_nvm_mac_sku_flags - flags in &iwl_nvm_get_info_sku 1788 * @NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED: true if 2.4 band enabled 1789 * @NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED: true if 5.2 band enabled 1790 * @NVM_MAC_SKU_FLAGS_802_11N_ENABLED: true if 11n enabled 1791 * @NVM_MAC_SKU_FLAGS_802_11AC_ENABLED: true if 11ac enabled 1792 * @NVM_MAC_SKU_FLAGS_802_11AX_ENABLED: true if 11ax enabled 1793 * @NVM_MAC_SKU_FLAGS_MIMO_DISABLED: true if MIMO disabled 1794 * @NVM_MAC_SKU_FLAGS_WAPI_ENABLED: true if WAPI enabled 1795 * @NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED: true if regulatory checker enabled 1796 * @NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED: true if API lock enabled 1797 */ 1798 #define IWX_NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED (1 << 0) 1799 #define IWX_NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED (1 << 1) 1800 #define IWX_NVM_MAC_SKU_FLAGS_802_11N_ENABLED (1 << 2) 1801 #define IWX_NVM_MAC_SKU_FLAGS_802_11AC_ENABLED (1 << 3) 1802 #define IWX_NVM_MAC_SKU_FLAGS_802_11AX_ENABLED (1 << 4) 1803 #define IWX_NVM_MAC_SKU_FLAGS_MIMO_DISABLED (1 << 5) 1804 #define IWX_NVM_MAC_SKU_FLAGS_WAPI_ENABLED (1 << 8) 1805 #define IWX_NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED (1 << 14) 1806 #define IWX_NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED (1 << 15) 1807 1808 /** 1809 * struct iwx_nvm_get_info_sku - mac information 1810 * @mac_sku_flags: flags for SKU, see &enum iwl_nvm_mac_sku_flags 1811 */ 1812 struct iwx_nvm_get_info_sku { 1813 uint32_t mac_sku_flags; 1814 } __packed; /* REGULATORY_NVM_GET_INFO_MAC_SKU_SECTION_S_VER_2 */ 1815 1816 /** 1817 * struct iwx_nvm_get_info_phy - phy information 1818 * @tx_chains: BIT 0 chain A, BIT 1 chain B 1819 * @rx_chains: BIT 0 chain A, BIT 1 chain B 1820 */ 1821 struct iwx_nvm_get_info_phy { 1822 uint32_t tx_chains; 1823 uint32_t rx_chains; 1824 } __packed; /* REGULATORY_NVM_GET_INFO_PHY_SKU_SECTION_S_VER_1 */ 1825 1826 #define IWX_NUM_CHANNELS_V1 51 1827 #define IWX_NUM_CHANNELS 110 1828 1829 /** 1830 * struct iwx_nvm_get_info_regulatory - regulatory information 1831 * @lar_enabled: is LAR enabled 1832 * @channel_profile: regulatory data of this channel 1833 * @reserved: reserved 1834 */ 1835 struct iwx_nvm_get_info_regulatory_v1 { 1836 uint32_t lar_enabled; 1837 uint16_t channel_profile[IWX_NUM_CHANNELS_V1]; 1838 uint16_t reserved; 1839 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_1 */ 1840 1841 /** 1842 * struct iwx_nvm_get_info_regulatory - regulatory information 1843 * @lar_enabled: is LAR enabled 1844 * @n_channels: number of valid channels in the array 1845 * @channel_profile: regulatory data of this channel 1846 */ 1847 struct iwx_nvm_get_info_regulatory { 1848 uint32_t lar_enabled; 1849 uint32_t n_channels; 1850 uint32_t channel_profile[IWX_NUM_CHANNELS]; 1851 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_2 */ 1852 1853 /** 1854 * struct iwx_nvm_get_info_rsp_v3 - response to get NVM data 1855 * @general: general NVM data 1856 * @mac_sku: data relating to MAC sku 1857 * @phy_sku: data relating to PHY sku 1858 * @regulatory: regulatory data 1859 */ 1860 struct iwx_nvm_get_info_rsp_v3 { 1861 struct iwx_nvm_get_info_general general; 1862 struct iwx_nvm_get_info_sku mac_sku; 1863 struct iwx_nvm_get_info_phy phy_sku; 1864 struct iwx_nvm_get_info_regulatory_v1 regulatory; 1865 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_3 */ 1866 1867 /** 1868 * struct iwx_nvm_get_info_rsp - response to get NVM data 1869 * @general: general NVM data 1870 * @mac_sku: data relating to MAC sku 1871 * @phy_sku: data relating to PHY sku 1872 * @regulatory: regulatory data 1873 */ 1874 struct iwx_nvm_get_info_rsp { 1875 struct iwx_nvm_get_info_general general; 1876 struct iwx_nvm_get_info_sku mac_sku; 1877 struct iwx_nvm_get_info_phy phy_sku; 1878 struct iwx_nvm_get_info_regulatory regulatory; 1879 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_4 */ 1880 1881 1882 #define IWX_ALIVE_STATUS_ERR 0xDEAD 1883 #define IWX_ALIVE_STATUS_OK 0xCAFE 1884 1885 struct iwx_lmac_debug_addrs { 1886 uint32_t error_event_table_ptr; /* SRAM address for error log */ 1887 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 1888 uint32_t cpu_register_ptr; 1889 uint32_t dbgm_config_ptr; 1890 uint32_t alive_counter_ptr; 1891 uint32_t scd_base_ptr; /* SRAM address for SCD */ 1892 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 1893 uint32_t st_fwrd_size; 1894 } __packed; /* UCODE_DEBUG_ADDRS_API_S_VER_2 */ 1895 1896 struct iwx_lmac_alive { 1897 uint32_t ucode_major; 1898 uint32_t ucode_minor; 1899 uint8_t ver_subtype; 1900 uint8_t ver_type; 1901 uint8_t mac; 1902 uint8_t opt; 1903 uint32_t timestamp; 1904 struct iwx_lmac_debug_addrs dbg_ptrs; 1905 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */ 1906 1907 struct iwx_umac_debug_addrs { 1908 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 1909 uint32_t dbg_print_buff_addr; 1910 } __packed; /* UMAC_DEBUG_ADDRS_API_S_VER_1 */ 1911 1912 struct iwx_umac_alive { 1913 uint32_t umac_major; /* UMAC version: major */ 1914 uint32_t umac_minor; /* UMAC version: minor */ 1915 struct iwx_umac_debug_addrs dbg_ptrs; 1916 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */ 1917 1918 struct iwx_alive_resp_v4 { 1919 uint16_t status; 1920 uint16_t flags; 1921 struct iwx_lmac_alive lmac_data[2]; 1922 struct iwx_umac_alive umac_data; 1923 } __packed; /* ALIVE_RES_API_S_VER_4 */ 1924 1925 #define IWX_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0) 1926 #define IWX_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1) 1927 1928 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc 1929 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0 1930 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_200 1 1931 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_2500 2 1932 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_1820 3 1933 1934 /** 1935 * struct iwx_soc_configuration_cmd - Set device stabilization latency 1936 * 1937 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE 1938 * flag, because the FW treats the whole value as an integer. In 1939 * VER_2, we can set the bits independently. 1940 * @latency: time for SOC to ensure stable power & XTAL 1941 */ 1942 struct iwx_soc_configuration_cmd { 1943 uint32_t flags; 1944 uint32_t latency; 1945 } __packed; /* 1946 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above) 1947 * SOC_CONFIGURATION_CMD_S_VER_2 1948 */ 1949 1950 /** 1951 * commands driver may send before finishing init flow 1952 * @IWX_INIT_DEBUG_CFG: driver is going to send debug config command 1953 * @IWX_INIT_NVM: driver is going to send NVM_ACCESS commands 1954 */ 1955 #define IWX_INIT_DEBUG_CFG (1 << 0) 1956 #define IWX_INIT_NVM (1 << 1) 1957 1958 /** 1959 * struct iwx_extended_cfg_cmd - mark what commands ucode should wait for 1960 * before finishing init flows 1961 * @init_flags: IWX_INIT_* flag bits 1962 */ 1963 struct iwx_init_extended_cfg_cmd { 1964 uint32_t init_flags; 1965 } __packed; /* INIT_EXTENDED_CFG_CMD_API_S_VER_1 */ 1966 1967 /* Error response/notification */ 1968 #define IWX_FW_ERR_UNKNOWN_CMD 0x0 1969 #define IWX_FW_ERR_INVALID_CMD_PARAM 0x1 1970 #define IWX_FW_ERR_SERVICE 0x2 1971 #define IWX_FW_ERR_ARC_MEMORY 0x3 1972 #define IWX_FW_ERR_ARC_CODE 0x4 1973 #define IWX_FW_ERR_WATCH_DOG 0x5 1974 #define IWX_FW_ERR_WEP_GRP_KEY_INDX 0x10 1975 #define IWX_FW_ERR_WEP_KEY_SIZE 0x11 1976 #define IWX_FW_ERR_OBSOLETE_FUNC 0x12 1977 #define IWX_FW_ERR_UNEXPECTED 0xFE 1978 #define IWX_FW_ERR_FATAL 0xFF 1979 1980 /** 1981 * struct iwx_error_resp - FW error indication 1982 * ( IWX_REPLY_ERROR = 0x2 ) 1983 * @error_type: one of IWX_FW_ERR_* 1984 * @cmd_id: the command ID for which the error occured 1985 * @bad_cmd_seq_num: sequence number of the erroneous command 1986 * @error_service: which service created the error, applicable only if 1987 * error_type = 2, otherwise 0 1988 * @timestamp: TSF in usecs. 1989 */ 1990 struct iwx_error_resp { 1991 uint32_t error_type; 1992 uint8_t cmd_id; 1993 uint8_t reserved1; 1994 uint16_t bad_cmd_seq_num; 1995 uint32_t error_service; 1996 uint64_t timestamp; 1997 } __packed; 1998 1999 enum iwx_fw_dbg_reg_operator { 2000 CSR_ASSIGN, 2001 CSR_SETBIT, 2002 CSR_CLEARBIT, 2003 2004 PRPH_ASSIGN, 2005 PRPH_SETBIT, 2006 PRPH_CLEARBIT, 2007 2008 INDIRECT_ASSIGN, 2009 INDIRECT_SETBIT, 2010 INDIRECT_CLEARBIT, 2011 2012 PRPH_BLOCKBIT, 2013 }; 2014 2015 /** 2016 * struct iwx_fw_dbg_reg_op - an operation on a register 2017 * 2018 * @op: &enum iwx_fw_dbg_reg_operator 2019 * @addr: offset of the register 2020 * @val: value 2021 */ 2022 struct iwx_fw_dbg_reg_op { 2023 uint8_t op; 2024 uint8_t reserved[3]; 2025 uint32_t addr; 2026 uint32_t val; 2027 } __packed; 2028 2029 /** 2030 * enum iwx_fw_dbg_monitor_mode - available monitor recording modes 2031 * 2032 * @SMEM_MODE: monitor stores the data in SMEM 2033 * @EXTERNAL_MODE: monitor stores the data in allocated DRAM 2034 * @MARBH_MODE: monitor stores the data in MARBH buffer 2035 * @MIPI_MODE: monitor outputs the data through the MIPI interface 2036 */ 2037 enum iwx_fw_dbg_monitor_mode { 2038 SMEM_MODE = 0, 2039 EXTERNAL_MODE = 1, 2040 MARBH_MODE = 2, 2041 MIPI_MODE = 3, 2042 }; 2043 2044 /** 2045 * struct iwx_fw_dbg_mem_seg_tlv - configures the debug data memory segments 2046 * 2047 * @data_type: the memory segment type to record 2048 * @ofs: the memory segment offset 2049 * @len: the memory segment length, in bytes 2050 * 2051 * This parses IWX_UCODE_TLV_FW_MEM_SEG 2052 */ 2053 struct iwx_fw_dbg_mem_seg_tlv { 2054 uint32_t data_type; 2055 uint32_t ofs; 2056 uint32_t len; 2057 } __packed; 2058 2059 /** 2060 * struct iwx_fw_dbg_dest_tlv_v1 - configures the destination of the debug data 2061 * 2062 * @version: version of the TLV - currently 0 2063 * @monitor_mode: &enum iwx_fw_dbg_monitor_mode 2064 * @size_power: buffer size will be 2^(size_power + 11) 2065 * @base_reg: addr of the base addr register (PRPH) 2066 * @end_reg: addr of the end addr register (PRPH) 2067 * @write_ptr_reg: the addr of the reg of the write pointer 2068 * @wrap_count: the addr of the reg of the wrap_count 2069 * @base_shift: shift right of the base addr reg 2070 * @end_shift: shift right of the end addr reg 2071 * @reg_ops: array of registers operations 2072 * 2073 * This parses IWX_UCODE_TLV_FW_DBG_DEST 2074 */ 2075 struct iwx_fw_dbg_dest_tlv_v1 { 2076 uint8_t version; 2077 uint8_t monitor_mode; 2078 uint8_t size_power; 2079 uint8_t reserved; 2080 uint32_t base_reg; 2081 uint32_t end_reg; 2082 uint32_t write_ptr_reg; 2083 uint32_t wrap_count; 2084 uint8_t base_shift; 2085 uint8_t end_shift; 2086 struct iwx_fw_dbg_reg_op reg_ops[0]; 2087 } __packed; 2088 2089 /* Mask of the register for defining the LDBG MAC2SMEM buffer SMEM size */ 2090 #define IWX_LDBG_M2S_BUF_SIZE_MSK 0x0fff0000 2091 /* Mask of the register for defining the LDBG MAC2SMEM SMEM base address */ 2092 #define IWX_LDBG_M2S_BUF_BA_MSK 0x00000fff 2093 /* The smem buffer chunks are in units of 256 bits */ 2094 #define IWX_M2S_UNIT_SIZE 0x100 2095 2096 struct iwx_fw_dbg_dest_tlv { 2097 uint8_t version; 2098 uint8_t monitor_mode; 2099 uint8_t size_power; 2100 uint8_t reserved; 2101 uint32_t cfg_reg; 2102 uint32_t write_ptr_reg; 2103 uint32_t wrap_count; 2104 uint8_t base_shift; 2105 uint8_t size_shift; 2106 struct iwx_fw_dbg_reg_op reg_ops[0]; 2107 } __packed; 2108 2109 struct iwx_fw_dbg_conf_hcmd { 2110 uint8_t id; 2111 uint8_t reserved; 2112 uint16_t len; 2113 uint8_t data[0]; 2114 } __packed; 2115 2116 /** 2117 * enum iwx_fw_dbg_trigger_mode - triggers functionalities 2118 * 2119 * @IWX_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism 2120 * @IWX_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data 2121 * @IWX_FW_DBG_TRIGGER_MONITOR_ONLY: when trigger occurs trigger is set to 2122 * collect only monitor data 2123 */ 2124 enum iwx_fw_dbg_trigger_mode { 2125 IWX_FW_DBG_TRIGGER_START = (1 << 0), 2126 IWX_FW_DBG_TRIGGER_STOP = (1 << 1), 2127 IWX_FW_DBG_TRIGGER_MONITOR_ONLY = (1 << 2), 2128 }; 2129 2130 /** 2131 * enum iwx_fw_dbg_trigger_flags - the flags supported by wrt triggers 2132 * @IWX_FW_DBG_FORCE_RESTART: force a firmware restart 2133 */ 2134 enum iwx_fw_dbg_trigger_flags { 2135 IWX_FW_DBG_FORCE_RESTART = (1 << 0), 2136 }; 2137 2138 /** 2139 * enum iwx_fw_dbg_trigger_vif_type - define the VIF type for a trigger 2140 * @IWX_FW_DBG_CONF_VIF_ANY: any vif type 2141 * @IWX_FW_DBG_CONF_VIF_IBSS: IBSS mode 2142 * @IWX_FW_DBG_CONF_VIF_STATION: BSS mode 2143 * @IWX_FW_DBG_CONF_VIF_AP: AP mode 2144 * @IWX_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode 2145 * @IWX_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode 2146 * @IWX_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device 2147 * @IWX_FW_DBG_CONF_VIF_NAN: NAN device 2148 */ 2149 enum iwx_fw_dbg_trigger_vif_type { 2150 IWX_FW_DBG_CONF_VIF_ANY = 0, 2151 IWX_FW_DBG_CONF_VIF_IBSS = 1, 2152 IWX_FW_DBG_CONF_VIF_STATION = 2, 2153 IWX_FW_DBG_CONF_VIF_AP = 3, 2154 IWX_FW_DBG_CONF_VIF_P2P_CLIENT = 8, 2155 IWX_FW_DBG_CONF_VIF_P2P_GO = 9, 2156 IWX_FW_DBG_CONF_VIF_P2P_DEVICE = 10, 2157 IWX_FW_DBG_CONF_VIF_NAN = 12, 2158 }; 2159 2160 /** 2161 * enum iwl_fw_dbg_trigger - triggers available 2162 * 2163 * @FW_DBG_TRIGGER_USER: trigger log collection by user 2164 * This should not be defined as a trigger to the driver, but a value the 2165 * driver should set to indicate that the trigger was initiated by the 2166 * user. 2167 * @FW_DBG_TRIGGER_FW_ASSERT: trigger log collection when the firmware asserts 2168 * @FW_DBG_TRIGGER_MISSED_BEACONS: trigger log collection when beacons are 2169 * missed. 2170 * @FW_DBG_TRIGGER_CHANNEL_SWITCH: trigger log collection upon channel switch. 2171 * @FW_DBG_TRIGGER_FW_NOTIF: trigger log collection when the firmware sends a 2172 * command response or a notification. 2173 * @FW_DBG_TRIGGER_MLME: trigger log collection upon MLME event. 2174 * @FW_DBG_TRIGGER_STATS: trigger log collection upon statistics threshold. 2175 * @FW_DBG_TRIGGER_RSSI: trigger log collection when the rssi of the beacon 2176 * goes below a threshold. 2177 * @FW_DBG_TRIGGER_TXQ_TIMERS: configures the timers for the Tx queue hang 2178 * detection. 2179 * @FW_DBG_TRIGGER_TIME_EVENT: trigger log collection upon time events related 2180 * events. 2181 * @FW_DBG_TRIGGER_BA: trigger log collection upon BlockAck related events. 2182 * @FW_DBG_TX_LATENCY: trigger log collection when the tx latency goes above a 2183 * threshold. 2184 * @FW_DBG_TDLS: trigger log collection upon TDLS related events. 2185 * @FW_DBG_TRIGGER_TX_STATUS: trigger log collection upon tx status when 2186 * the firmware sends a tx reply. 2187 * @FW_DBG_TRIGGER_USER_EXTENDED: trigger log collection upon user space 2188 * request. 2189 * @FW_DBG_TRIGGER_ALIVE_TIMEOUT: trigger log collection if alive flow timeouts 2190 * @FW_DBG_TRIGGER_DRIVER: trigger log collection upon a flow failure 2191 * in the driver. 2192 */ 2193 enum iwx_fw_dbg_trigger { 2194 IWX_FW_DBG_TRIGGER_INVALID = 0, 2195 IWX_FW_DBG_TRIGGER_USER, 2196 IWX_FW_DBG_TRIGGER_FW_ASSERT, 2197 IWX_FW_DBG_TRIGGER_MISSED_BEACONS, 2198 IWX_FW_DBG_TRIGGER_CHANNEL_SWITCH, 2199 IWX_FW_DBG_TRIGGER_FW_NOTIF, 2200 IWX_FW_DBG_TRIGGER_MLME, 2201 IWX_FW_DBG_TRIGGER_STATS, 2202 IWX_FW_DBG_TRIGGER_RSSI, 2203 IWX_FW_DBG_TRIGGER_TXQ_TIMERS, 2204 IWX_FW_DBG_TRIGGER_TIME_EVENT, 2205 IWX_FW_DBG_TRIGGER_BA, 2206 IWX_FW_DBG_TRIGGER_TX_LATENCY, 2207 IWX_FW_DBG_TRIGGER_TDLS, 2208 IWX_FW_DBG_TRIGGER_TX_STATUS, 2209 IWX_FW_DBG_TRIGGER_USER_EXTENDED, 2210 IWX_FW_DBG_TRIGGER_ALIVE_TIMEOUT, 2211 IWX_FW_DBG_TRIGGER_DRIVER, 2212 2213 /* must be last */ 2214 IWX_FW_DBG_TRIGGER_MAX, 2215 }; 2216 2217 2218 /** 2219 * struct iwx_fw_dbg_trigger_tlv - a TLV that describes the trigger 2220 * @id: &enum iwx_fw_dbg_trigger 2221 * @vif_type: &enum iwx_fw_dbg_trigger_vif_type 2222 * @stop_conf_ids: bitmap of configurations this trigger relates to. 2223 * if the mode is %IWX_FW_DBG_TRIGGER_STOP, then if the bit corresponding 2224 * to the currently running configuration is set, the data should be 2225 * collected. 2226 * @stop_delay: how many milliseconds to wait before collecting the data 2227 * after the STOP trigger fires. 2228 * @mode: &enum iwx_fw_dbg_trigger_mode - can be stop / start of both 2229 * @start_conf_id: if mode is %IWX_FW_DBG_TRIGGER_START, this defines what 2230 * configuration should be applied when the triggers kicks in. 2231 * @occurrences: number of occurrences. 0 means the trigger will never fire. 2232 * @trig_dis_ms: the time, in milliseconds, after an occurrence of this 2233 * trigger in which another occurrence should be ignored. 2234 * @flags: &enum iwx_fw_dbg_trigger_flags 2235 */ 2236 struct iwx_fw_dbg_trigger_tlv { 2237 uint32_t id; 2238 uint32_t vif_type; 2239 uint32_t stop_conf_ids; 2240 uint32_t stop_delay; 2241 uint8_t mode; 2242 uint8_t start_conf_id; 2243 uint16_t occurrences; 2244 uint16_t trig_dis_ms; 2245 uint8_t flags; 2246 uint8_t reserved[5]; 2247 2248 uint8_t data[0]; 2249 } __packed; 2250 2251 #define IWX_FW_DBG_START_FROM_ALIVE 0 2252 #define IWX_FW_DBG_CONF_MAX 32 2253 #define IWX_FW_DBG_INVALID 0xff 2254 2255 /** 2256 * struct iwx_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons 2257 * @stop_consec_missed_bcon: stop recording if threshold is crossed. 2258 * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed. 2259 * @start_consec_missed_bcon: start recording if threshold is crossed. 2260 * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed. 2261 * @reserved1: reserved 2262 * @reserved2: reserved 2263 */ 2264 struct iwx_fw_dbg_trigger_missed_bcon { 2265 uint32_t stop_consec_missed_bcon; 2266 uint32_t stop_consec_missed_bcon_since_rx; 2267 uint32_t reserved2[2]; 2268 uint32_t start_consec_missed_bcon; 2269 uint32_t start_consec_missed_bcon_since_rx; 2270 uint32_t reserved1[2]; 2271 } __packed; 2272 2273 /** 2274 * struct iwx_fw_dbg_trigger_cmd - configures trigger for messages from FW. 2275 * cmds: the list of commands to trigger the collection on 2276 */ 2277 struct iwx_fw_dbg_trigger_cmd { 2278 struct cmd { 2279 uint8_t cmd_id; 2280 uint8_t group_id; 2281 } __packed cmds[16]; 2282 } __packed; 2283 2284 /** 2285 * iwx_fw_dbg_trigger_stats - configures trigger for statistics 2286 * @stop_offset: the offset of the value to be monitored 2287 * @stop_threshold: the threshold above which to collect 2288 * @start_offset: the offset of the value to be monitored 2289 * @start_threshold: the threshold above which to start recording 2290 */ 2291 struct iwx_fw_dbg_trigger_stats { 2292 uint32_t stop_offset; 2293 uint32_t stop_threshold; 2294 uint32_t start_offset; 2295 uint32_t start_threshold; 2296 } __packed; 2297 2298 /** 2299 * struct iwx_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI 2300 * @rssi: RSSI value to trigger at 2301 */ 2302 struct iwx_fw_dbg_trigger_low_rssi { 2303 uint32_t rssi; 2304 } __packed; 2305 2306 /** 2307 * struct iwx_fw_dbg_trigger_mlme - configures trigger for mlme events 2308 * @stop_auth_denied: number of denied authentication to collect 2309 * @stop_auth_timeout: number of authentication timeout to collect 2310 * @stop_rx_deauth: number of Rx deauth before to collect 2311 * @stop_tx_deauth: number of Tx deauth before to collect 2312 * @stop_assoc_denied: number of denied association to collect 2313 * @stop_assoc_timeout: number of association timeout to collect 2314 * @stop_connection_loss: number of connection loss to collect 2315 * @start_auth_denied: number of denied authentication to start recording 2316 * @start_auth_timeout: number of authentication timeout to start recording 2317 * @start_rx_deauth: number of Rx deauth to start recording 2318 * @start_tx_deauth: number of Tx deauth to start recording 2319 * @start_assoc_denied: number of denied association to start recording 2320 * @start_assoc_timeout: number of association timeout to start recording 2321 * @start_connection_loss: number of connection loss to start recording 2322 */ 2323 struct iwx_fw_dbg_trigger_mlme { 2324 uint8_t stop_auth_denied; 2325 uint8_t stop_auth_timeout; 2326 uint8_t stop_rx_deauth; 2327 uint8_t stop_tx_deauth; 2328 2329 uint8_t stop_assoc_denied; 2330 uint8_t stop_assoc_timeout; 2331 uint8_t stop_connection_loss; 2332 uint8_t reserved; 2333 2334 uint8_t start_auth_denied; 2335 uint8_t start_auth_timeout; 2336 uint8_t start_rx_deauth; 2337 uint8_t start_tx_deauth; 2338 2339 uint8_t start_assoc_denied; 2340 uint8_t start_assoc_timeout; 2341 uint8_t start_connection_loss; 2342 uint8_t reserved2; 2343 } __packed; 2344 2345 /** 2346 * struct iwx_fw_dbg_trigger_txq_timer - configures the Tx queue's timer 2347 * @command_queue: timeout for the command queue in ms 2348 * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms 2349 * @softap: timeout for the queues of a softAP in ms 2350 * @p2p_go: timeout for the queues of a P2P GO in ms 2351 * @p2p_client: timeout for the queues of a P2P client in ms 2352 * @p2p_device: timeout for the queues of a P2P device in ms 2353 * @ibss: timeout for the queues of an IBSS in ms 2354 * @tdls: timeout for the queues of a TDLS station in ms 2355 */ 2356 struct iwx_fw_dbg_trigger_txq_timer { 2357 uint32_t command_queue; 2358 uint32_t bss; 2359 uint32_t softap; 2360 uint32_t p2p_go; 2361 uint32_t p2p_client; 2362 uint32_t p2p_device; 2363 uint32_t ibss; 2364 uint32_t tdls; 2365 uint32_t reserved[4]; 2366 } __packed; 2367 2368 /** 2369 * struct iwx_fw_dbg_trigger_time_event - configures a time event trigger 2370 * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a 2371 * trigger each time a time event notification that relates to time event 2372 * id with one of the actions in the bitmap is received and 2373 * BIT(notif->status) is set in status_bitmap. 2374 * 2375 */ 2376 struct iwx_fw_dbg_trigger_time_event { 2377 struct { 2378 uint32_t id; 2379 uint32_t action_bitmap; 2380 uint32_t status_bitmap; 2381 } __packed time_events[16]; 2382 } __packed; 2383 2384 /** 2385 * struct iwx_fw_dbg_trigger_ba - configures BlockAck related trigger 2386 * rx_ba_start: tid bitmap to configure on what tid the trigger should occur 2387 * when an Rx BlockAck session is started. 2388 * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur 2389 * when an Rx BlockAck session is stopped. 2390 * tx_ba_start: tid bitmap to configure on what tid the trigger should occur 2391 * when a Tx BlockAck session is started. 2392 * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur 2393 * when a Tx BlockAck session is stopped. 2394 * rx_bar: tid bitmap to configure on what tid the trigger should occur 2395 * when a BAR is received (for a Tx BlockAck session). 2396 * tx_bar: tid bitmap to configure on what tid the trigger should occur 2397 * when a BAR is send (for an Rx BlocAck session). 2398 * frame_timeout: tid bitmap to configure on what tid the trigger should occur 2399 * when a frame times out in the reodering buffer. 2400 */ 2401 struct iwx_fw_dbg_trigger_ba { 2402 uint16_t rx_ba_start; 2403 uint16_t rx_ba_stop; 2404 uint16_t tx_ba_start; 2405 uint16_t tx_ba_stop; 2406 uint16_t rx_bar; 2407 uint16_t tx_bar; 2408 uint16_t frame_timeout; 2409 } __packed; 2410 2411 /** 2412 * struct iwx_fw_dbg_trigger_tx_latency - configures tx latency related trigger 2413 * @thrshold: the wanted threshold. 2414 * @tid_bitmap: the tid to apply the threshold on 2415 * @mode: recording mode (Internal buffer or continues recording) 2416 * @window: the size of the window before collecting. 2417 * @reserved: reserved. 2418 */ 2419 struct iwx_fw_dbg_trigger_tx_latency { 2420 uint32_t thrshold; 2421 uint16_t tid_bitmap; 2422 uint16_t mode; 2423 uint32_t window; 2424 uint32_t reserved[4]; 2425 } __packed; 2426 2427 /** 2428 * struct iwx_fw_dbg_trigger_tdls - configures trigger for TDLS events. 2429 * @action_bitmap: the TDLS action to trigger the collection upon 2430 * @peer_mode: trigger on specific peer or all 2431 * @peer: the TDLS peer to trigger the collection on 2432 */ 2433 struct iwx_fw_dbg_trigger_tdls { 2434 uint8_t action_bitmap; 2435 uint8_t peer_mode; 2436 uint8_t peer[ETHER_ADDR_LEN]; 2437 uint8_t reserved[4]; 2438 } __packed; 2439 2440 /** 2441 * struct iwx_fw_dbg_trigger_tx_status - configures trigger for tx response 2442 * status. 2443 * @statuses: the list of statuses to trigger the collection on 2444 */ 2445 struct iwx_fw_dbg_trigger_tx_status { 2446 struct tx_status { 2447 uint8_t status; 2448 uint8_t reserved[3]; 2449 } __packed statuses[16]; 2450 uint32_t reserved[2]; 2451 } __packed; 2452 2453 /** 2454 * struct iwx_fw_dbg_conf_tlv - a TLV that describes a debug configuration. 2455 * @id: conf id 2456 * @usniffer: should the uSniffer image be used 2457 * @num_of_hcmds: how many HCMDs to send are present here 2458 * @hcmd: a variable length host command to be sent to apply the configuration. 2459 * If there is more than one HCMD to send, they will appear one after the 2460 * other and be sent in the order that they appear in. 2461 * This parses IWX_UCODE_TLV_FW_DBG_CONF. The user can add up-to 2462 * %IWX_FW_DBG_CONF_MAX configuration per run. 2463 */ 2464 struct iwx_fw_dbg_conf_tlv { 2465 uint8_t id; 2466 uint8_t usniffer; 2467 uint8_t reserved; 2468 uint8_t num_of_hcmds; 2469 struct iwx_fw_dbg_conf_hcmd hcmd; 2470 } __packed; 2471 2472 #define IWX_FW_CMD_VER_UNKNOWN 99 2473 2474 /** 2475 * struct iwx_fw_cmd_version - firmware command version entry 2476 * @cmd: command ID 2477 * @group: group ID 2478 * @cmd_ver: command version 2479 * @notif_ver: notification version 2480 */ 2481 struct iwx_fw_cmd_version { 2482 uint8_t cmd; 2483 uint8_t group; 2484 uint8_t cmd_ver; 2485 uint8_t notif_ver; 2486 } __packed; 2487 2488 /* Common PHY, MAC and Bindings definitions */ 2489 2490 #define IWX_MAX_MACS_IN_BINDING (3) 2491 #define IWX_MAX_BINDINGS (4) 2492 #define IWX_AUX_BINDING_INDEX (3) 2493 #define IWX_MAX_PHYS (4) 2494 2495 /* Used to extract ID and color from the context dword */ 2496 #define IWX_FW_CTXT_ID_POS (0) 2497 #define IWX_FW_CTXT_ID_MSK (0xff << IWX_FW_CTXT_ID_POS) 2498 #define IWX_FW_CTXT_COLOR_POS (8) 2499 #define IWX_FW_CTXT_COLOR_MSK (0xff << IWX_FW_CTXT_COLOR_POS) 2500 #define IWX_FW_CTXT_INVALID (0xffffffff) 2501 2502 #define IWX_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWX_FW_CTXT_ID_POS) |\ 2503 (_color << IWX_FW_CTXT_COLOR_POS)) 2504 2505 /* Possible actions on PHYs, MACs and Bindings */ 2506 #define IWX_FW_CTXT_ACTION_STUB 0 2507 #define IWX_FW_CTXT_ACTION_ADD 1 2508 #define IWX_FW_CTXT_ACTION_MODIFY 2 2509 #define IWX_FW_CTXT_ACTION_REMOVE 3 2510 #define IWX_FW_CTXT_ACTION_NUM 4 2511 /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2512 2513 /* Time Events */ 2514 2515 /* Time Event types, according to MAC type */ 2516 2517 /* BSS Station Events */ 2518 #define IWX_TE_BSS_STA_AGGRESSIVE_ASSOC 0 2519 #define IWX_TE_BSS_STA_ASSOC 1 2520 #define IWX_TE_BSS_EAP_DHCP_PROT 2 2521 #define IWX_TE_BSS_QUIET_PERIOD 3 2522 2523 /* P2P Device Events */ 2524 #define IWX_TE_P2P_DEVICE_DISCOVERABLE 4 2525 #define IWX_TE_P2P_DEVICE_LISTEN 5 2526 #define IWX_TE_P2P_DEVICE_ACTION_SCAN 6 2527 #define IWX_TE_P2P_DEVICE_FULL_SCAN 7 2528 2529 /* P2P Client Events */ 2530 #define IWX_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8 2531 #define IWX_TE_P2P_CLIENT_ASSOC 9 2532 #define IWX_TE_P2P_CLIENT_QUIET_PERIOD 10 2533 2534 /* P2P GO Events */ 2535 #define IWX_TE_P2P_GO_ASSOC_PROT 11 2536 #define IWX_TE_P2P_GO_REPETITIVE_NOA 12 2537 #define IWX_TE_P2P_GO_CT_WINDOW 13 2538 2539 /* WiDi Sync Events */ 2540 #define IWX_TE_WIDI_TX_SYNC 14 2541 2542 /* Time event - defines for command API */ 2543 2544 /** 2545 * DOC: Time Events - what is it? 2546 * 2547 * Time Events are a fw feature that allows the driver to control the presence 2548 * of the device on the channel. Since the fw supports multiple channels 2549 * concurrently, the fw may choose to jump to another channel at any time. 2550 * In order to make sure that the fw is on a specific channel at a certain time 2551 * and for a certain duration, the driver needs to issue a time event. 2552 * 2553 * The simplest example is for BSS association. The driver issues a time event, 2554 * waits for it to start, and only then tells mac80211 that we can start the 2555 * association. This way, we make sure that the association will be done 2556 * smoothly and won't be interrupted by channel switch decided within the fw. 2557 */ 2558 2559 /** 2560 * DOC: The flow against the fw 2561 * 2562 * When the driver needs to make sure we are in a certain channel, at a certain 2563 * time and for a certain duration, it sends a Time Event. The flow against the 2564 * fw goes like this: 2565 * 1) Driver sends a TIME_EVENT_CMD to the fw 2566 * 2) Driver gets the response for that command. This response contains the 2567 * Unique ID (UID) of the event. 2568 * 3) The fw sends notification when the event starts. 2569 * 2570 * Of course the API provides various options that allow to cover parameters 2571 * of the flow. 2572 * What is the duration of the event? 2573 * What is the start time of the event? 2574 * Is there an end-time for the event? 2575 * How much can the event be delayed? 2576 * Can the event be split? 2577 * If yes what is the maximal number of chunks? 2578 * etc... 2579 */ 2580 2581 /* 2582 * @IWX_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2583 * @IWX_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2584 * the first fragment is scheduled. 2585 * @IWX_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2586 * the first 2 fragments are scheduled. 2587 * @IWX_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2588 * number of fragments are valid. 2589 * 2590 * Other than the constant defined above, specifying a fragmentation value 'x' 2591 * means that the event can be fragmented but only the first 'x' will be 2592 * scheduled. 2593 */ 2594 #define IWX_TE_V2_FRAG_NONE 0 2595 #define IWX_TE_V2_FRAG_SINGLE 1 2596 #define IWX_TE_V2_FRAG_DUAL 2 2597 #define IWX_TE_V2_FRAG_MAX 0xfe 2598 #define IWX_TE_V2_FRAG_ENDLESS 0xff 2599 2600 /* Repeat the time event endlessly (until removed) */ 2601 #define IWX_TE_V2_REPEAT_ENDLESS 0xff 2602 /* If a Time Event has bounded repetitions, this is the maximal value */ 2603 #define IWX_TE_V2_REPEAT_MAX 0xfe 2604 2605 #define IWX_TE_V2_PLACEMENT_POS 12 2606 #define IWX_TE_V2_ABSENCE_POS 15 2607 2608 /* Time event policy values 2609 * A notification (both event and fragment) includes a status indicating weather 2610 * the FW was able to schedule the event or not. For fragment start/end 2611 * notification the status is always success. There is no start/end fragment 2612 * notification for monolithic events. 2613 * 2614 * @IWX_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2615 * @IWX_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2616 * @IWX_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2617 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2618 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2619 * @IWX_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2620 * @IWX_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2621 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2622 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2623 * @IWX_TE_V2_DEP_OTHER: depends on another time event 2624 * @IWX_TE_V2_DEP_TSF: depends on a specific time 2625 * @IWX_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2626 * @IWX_TE_V2_ABSENCE: are we present or absent during the Time Event. 2627 */ 2628 #define IWX_TE_V2_DEFAULT_POLICY 0x0 2629 2630 /* notifications (event start/stop, fragment start/stop) */ 2631 #define IWX_TE_V2_NOTIF_HOST_EVENT_START (1 << 0) 2632 #define IWX_TE_V2_NOTIF_HOST_EVENT_END (1 << 1) 2633 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2) 2634 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3) 2635 2636 #define IWX_TE_V2_NOTIF_HOST_FRAG_START (1 << 4) 2637 #define IWX_TE_V2_NOTIF_HOST_FRAG_END (1 << 5) 2638 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6) 2639 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7) 2640 #define IWX_T2_V2_START_IMMEDIATELY (1 << 11) 2641 2642 #define IWX_TE_V2_NOTIF_MSK 0xff 2643 2644 /* placement characteristics */ 2645 #define IWX_TE_V2_DEP_OTHER (1 << IWX_TE_V2_PLACEMENT_POS) 2646 #define IWX_TE_V2_DEP_TSF (1 << (IWX_TE_V2_PLACEMENT_POS + 1)) 2647 #define IWX_TE_V2_EVENT_SOCIOPATHIC (1 << (IWX_TE_V2_PLACEMENT_POS + 2)) 2648 2649 /* are we present or absent during the Time Event. */ 2650 #define IWX_TE_V2_ABSENCE (1 << IWX_TE_V2_ABSENCE_POS) 2651 2652 /** 2653 * struct iwx_time_event_cmd_api - configuring Time Events 2654 * with struct IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2655 * with version 1. determined by IWX_UCODE_TLV_FLAGS) 2656 * ( IWX_TIME_EVENT_CMD = 0x29 ) 2657 * @id_and_color: ID and color of the relevant MAC 2658 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 2659 * @id: this field has two meanings, depending on the action: 2660 * If the action is ADD, then it means the type of event to add. 2661 * For all other actions it is the unique event ID assigned when the 2662 * event was added by the FW. 2663 * @apply_time: When to start the Time Event (in GP2) 2664 * @max_delay: maximum delay to event's start (apply time), in TU 2665 * @depends_on: the unique ID of the event we depend on (if any) 2666 * @interval: interval between repetitions, in TU 2667 * @duration: duration of event in TU 2668 * @repeat: how many repetitions to do, can be IWX_TE_REPEAT_ENDLESS 2669 * @max_frags: maximal number of fragments the Time Event can be divided to 2670 * @policy: defines whether uCode shall notify the host or other uCode modules 2671 * on event and/or fragment start and/or end 2672 * using one of IWX_TE_INDEPENDENT, IWX_TE_DEP_OTHER, IWX_TE_DEP_TSF 2673 * IWX_TE_EVENT_SOCIOPATHIC 2674 * using IWX_TE_ABSENCE and using IWX_TE_NOTIF_* 2675 */ 2676 struct iwx_time_event_cmd { 2677 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2678 uint32_t id_and_color; 2679 uint32_t action; 2680 uint32_t id; 2681 /* IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2682 uint32_t apply_time; 2683 uint32_t max_delay; 2684 uint32_t depends_on; 2685 uint32_t interval; 2686 uint32_t duration; 2687 uint8_t repeat; 2688 uint8_t max_frags; 2689 uint16_t policy; 2690 } __packed; /* IWX_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2691 2692 /** 2693 * struct iwx_time_event_resp - response structure to iwx_time_event_cmd 2694 * @status: bit 0 indicates success, all others specify errors 2695 * @id: the Time Event type 2696 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2697 * @id_and_color: ID and color of the relevant MAC 2698 */ 2699 struct iwx_time_event_resp { 2700 uint32_t status; 2701 uint32_t id; 2702 uint32_t unique_id; 2703 uint32_t id_and_color; 2704 } __packed; /* IWX_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2705 2706 /** 2707 * struct iwx_time_event_notif - notifications of time event start/stop 2708 * ( IWX_TIME_EVENT_NOTIFICATION = 0x2a ) 2709 * @timestamp: action timestamp in GP2 2710 * @session_id: session's unique id 2711 * @unique_id: unique id of the Time Event itself 2712 * @id_and_color: ID and color of the relevant MAC 2713 * @action: one of IWX_TE_NOTIF_START or IWX_TE_NOTIF_END 2714 * @status: true if scheduled, false otherwise (not executed) 2715 */ 2716 struct iwx_time_event_notif { 2717 uint32_t timestamp; 2718 uint32_t session_id; 2719 uint32_t unique_id; 2720 uint32_t id_and_color; 2721 uint32_t action; 2722 uint32_t status; 2723 } __packed; /* IWX_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2724 2725 2726 /* Bindings and Time Quota */ 2727 2728 /** 2729 * struct iwx_binding_cmd - configuring bindings 2730 * ( IWX_BINDING_CONTEXT_CMD = 0x2b ) 2731 * @id_and_color: ID and color of the relevant Binding 2732 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 2733 * @macs: array of MAC id and colors which belong to the binding 2734 * @phy: PHY id and color which belongs to the binding 2735 * @lmac_id: the lmac id the binding belongs to 2736 */ 2737 struct iwx_binding_cmd { 2738 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2739 uint32_t id_and_color; 2740 uint32_t action; 2741 /* IWX_BINDING_DATA_API_S_VER_1 */ 2742 uint32_t macs[IWX_MAX_MACS_IN_BINDING]; 2743 uint32_t phy; 2744 uint32_t lmac_id; 2745 } __packed; /* IWX_BINDING_CMD_API_S_VER_2 */ 2746 2747 #define IWX_LMAC_24G_INDEX 0 2748 #define IWX_LMAC_5G_INDEX 1 2749 2750 /* The maximal number of fragments in the FW's schedule session */ 2751 #define IWX_MAX_QUOTA 128 2752 2753 /** 2754 * struct iwx_time_quota_data - configuration of time quota per binding 2755 * @id_and_color: ID and color of the relevant Binding 2756 * @quota: absolute time quota in TU. The scheduler will try to divide the 2757 * remainig quota (after Time Events) according to this quota. 2758 * @max_duration: max uninterrupted context duration in TU 2759 */ 2760 struct iwx_time_quota_data { 2761 uint32_t id_and_color; 2762 uint32_t quota; 2763 uint32_t max_duration; 2764 } __packed; /* IWX_TIME_QUOTA_DATA_API_S_VER_1 */ 2765 2766 /** 2767 * struct iwx_time_quota_cmd - configuration of time quota between bindings 2768 * ( IWX_TIME_QUOTA_CMD = 0x2c ) 2769 * @quotas: allocations per binding 2770 */ 2771 struct iwx_time_quota_cmd { 2772 struct iwx_time_quota_data quotas[IWX_MAX_BINDINGS]; 2773 } __packed; /* IWX_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2774 2775 2776 /* PHY context */ 2777 2778 /* Supported bands */ 2779 #define IWX_PHY_BAND_5 (0) 2780 #define IWX_PHY_BAND_24 (1) 2781 2782 /* Supported channel width, vary if there is VHT support */ 2783 #define IWX_PHY_VHT_CHANNEL_MODE20 (0x0) 2784 #define IWX_PHY_VHT_CHANNEL_MODE40 (0x1) 2785 #define IWX_PHY_VHT_CHANNEL_MODE80 (0x2) 2786 #define IWX_PHY_VHT_CHANNEL_MODE160 (0x3) 2787 2788 /* 2789 * Control channel position: 2790 * For legacy set bit means upper channel, otherwise lower. 2791 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2792 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2793 * center_freq 2794 * | 2795 * 40Mhz |_______|_______| 2796 * 80Mhz |_______|_______|_______|_______| 2797 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2798 * code 011 010 001 000 | 100 101 110 111 2799 */ 2800 #define IWX_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2801 #define IWX_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2802 #define IWX_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2803 #define IWX_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2804 #define IWX_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2805 #define IWX_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2806 #define IWX_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2807 #define IWX_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2808 2809 /* 2810 * @band: IWX_PHY_BAND_* 2811 * @channel: channel number 2812 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2813 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2814 */ 2815 struct iwx_fw_channel_info_v1 { 2816 uint8_t band; 2817 uint8_t channel; 2818 uint8_t width; 2819 uint8_t ctrl_pos; 2820 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */ 2821 2822 /* 2823 * struct iwx_fw_channel_info - channel information 2824 * 2825 * @channel: channel number 2826 * @band: PHY_BAND_* 2827 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2828 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2829 * @reserved: for future use and alignment 2830 */ 2831 struct iwx_fw_channel_info { 2832 uint32_t channel; 2833 uint8_t band; 2834 uint8_t width; 2835 uint8_t ctrl_pos; 2836 uint8_t reserved; 2837 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */ 2838 2839 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2840 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2841 (0x1 << IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2842 #define IWX_PHY_RX_CHAIN_VALID_POS (1) 2843 #define IWX_PHY_RX_CHAIN_VALID_MSK \ 2844 (0x7 << IWX_PHY_RX_CHAIN_VALID_POS) 2845 #define IWX_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2846 #define IWX_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2847 (0x7 << IWX_PHY_RX_CHAIN_FORCE_SEL_POS) 2848 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2849 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2850 (0x7 << IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2851 #define IWX_PHY_RX_CHAIN_CNT_POS (10) 2852 #define IWX_PHY_RX_CHAIN_CNT_MSK \ 2853 (0x3 << IWX_PHY_RX_CHAIN_CNT_POS) 2854 #define IWX_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2855 #define IWX_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2856 (0x3 << IWX_PHY_RX_CHAIN_MIMO_CNT_POS) 2857 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2858 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2859 (0x1 << IWX_PHY_RX_CHAIN_MIMO_FORCE_POS) 2860 2861 /* TODO: fix the value, make it depend on firmware at runtime? */ 2862 #define IWX_NUM_PHY_CTX 3 2863 2864 /* TODO: complete missing documentation */ 2865 /** 2866 * struct iwx_phy_context_cmd - config of the PHY context 2867 * ( IWX_PHY_CONTEXT_CMD = 0x8 ) 2868 * @id_and_color: ID and color of the relevant Binding 2869 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 2870 * @apply_time: 0 means immediate apply and context switch. 2871 * other value means apply new params after X usecs 2872 * @tx_param_color: ??? 2873 * @channel_info: 2874 * @txchain_info: ??? 2875 * @rxchain_info: ??? 2876 * @acquisition_data: ??? 2877 * @dsp_cfg_flags: set to 0 2878 */ 2879 /* 2880 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased 2881 * the size of fw_channel_info from v1 to v2. 2882 * To keep things simple we define two versions of this struct, and both 2883 * are labled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark 2884 * magic with pointers to struct members instead.) 2885 */ 2886 /* This version must be used if IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */ 2887 struct iwx_phy_context_cmd_uhb { 2888 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2889 uint32_t id_and_color; 2890 uint32_t action; 2891 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */ 2892 uint32_t apply_time; 2893 uint32_t tx_param_color; 2894 struct iwx_fw_channel_info ci; 2895 uint32_t txchain_info; 2896 uint32_t rxchain_info; 2897 uint32_t acquisition_data; 2898 uint32_t dsp_cfg_flags; 2899 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */ 2900 /* This version must be used otherwise: */ 2901 struct iwx_phy_context_cmd { 2902 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2903 uint32_t id_and_color; 2904 uint32_t action; 2905 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */ 2906 uint32_t apply_time; 2907 uint32_t tx_param_color; 2908 struct iwx_fw_channel_info_v1 ci; 2909 uint32_t txchain_info; 2910 uint32_t rxchain_info; 2911 uint32_t acquisition_data; 2912 uint32_t dsp_cfg_flags; 2913 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */ 2914 2915 2916 #define IWX_RX_INFO_PHY_CNT 8 2917 #define IWX_RX_INFO_ENERGY_ANT_ABC_IDX 1 2918 #define IWX_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2919 #define IWX_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2920 #define IWX_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2921 #define IWX_RX_INFO_ENERGY_ANT_A_POS 0 2922 #define IWX_RX_INFO_ENERGY_ANT_B_POS 8 2923 #define IWX_RX_INFO_ENERGY_ANT_C_POS 16 2924 2925 #define IWX_RX_INFO_AGC_IDX 1 2926 #define IWX_RX_INFO_RSSI_AB_IDX 2 2927 #define IWX_OFDM_AGC_A_MSK 0x0000007f 2928 #define IWX_OFDM_AGC_A_POS 0 2929 #define IWX_OFDM_AGC_B_MSK 0x00003f80 2930 #define IWX_OFDM_AGC_B_POS 7 2931 #define IWX_OFDM_AGC_CODE_MSK 0x3fe00000 2932 #define IWX_OFDM_AGC_CODE_POS 20 2933 #define IWX_OFDM_RSSI_INBAND_A_MSK 0x00ff 2934 #define IWX_OFDM_RSSI_A_POS 0 2935 #define IWX_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2936 #define IWX_OFDM_RSSI_ALLBAND_A_POS 8 2937 #define IWX_OFDM_RSSI_INBAND_B_MSK 0xff0000 2938 #define IWX_OFDM_RSSI_B_POS 16 2939 #define IWX_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2940 #define IWX_OFDM_RSSI_ALLBAND_B_POS 24 2941 2942 /** 2943 * struct iwx_rx_phy_info - phy info 2944 * (IWX_REPLY_RX_PHY_CMD = 0xc0) 2945 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2946 * @cfg_phy_cnt: configurable DSP phy data byte count 2947 * @stat_id: configurable DSP phy data set ID 2948 * @reserved1: 2949 * @system_timestamp: GP2 at on air rise 2950 * @timestamp: TSF at on air rise 2951 * @beacon_time_stamp: beacon at on-air rise 2952 * @phy_flags: general phy flags: band, modulation, ... 2953 * @channel: channel number 2954 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2955 * @rate_n_flags: IWX_RATE_MCS_* 2956 * @byte_count: frame's byte-count 2957 * @frame_time: frame's time on the air, based on byte count and frame rate 2958 * calculation 2959 * @mac_active_msk: what MACs were active when the frame was received 2960 * 2961 * Before each Rx, the device sends this data. It contains PHY information 2962 * about the reception of the packet. 2963 */ 2964 struct iwx_rx_phy_info { 2965 uint8_t non_cfg_phy_cnt; 2966 uint8_t cfg_phy_cnt; 2967 uint8_t stat_id; 2968 uint8_t reserved1; 2969 uint32_t system_timestamp; 2970 uint64_t timestamp; 2971 uint32_t beacon_time_stamp; 2972 uint16_t phy_flags; 2973 #define IWX_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2974 uint16_t channel; 2975 uint32_t non_cfg_phy[IWX_RX_INFO_PHY_CNT]; 2976 uint32_t rate_n_flags; 2977 uint32_t byte_count; 2978 uint16_t mac_active_msk; 2979 uint16_t frame_time; 2980 } __packed; 2981 2982 struct iwx_rx_mpdu_res_start { 2983 uint16_t byte_count; 2984 uint16_t reserved; 2985 } __packed; 2986 2987 /** 2988 * Values to parse %iwx_rx_phy_info phy_flags 2989 * @IWX_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2990 * @IWX_RX_RES_PHY_FLAGS_MOD_CCK: 2991 * @IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2992 * @IWX_RX_RES_PHY_FLAGS_NARROW_BAND: 2993 * @IWX_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2994 * @IWX_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2995 * @IWX_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2996 * @IWX_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2997 * @IWX_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2998 */ 2999 #define IWX_RX_RES_PHY_FLAGS_BAND_24 (1 << 0) 3000 #define IWX_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1) 3001 #define IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2) 3002 #define IWX_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3) 3003 #define IWX_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4) 3004 #define IWX_RX_RES_PHY_FLAGS_ANTENNA_POS 4 3005 #define IWX_RX_RES_PHY_FLAGS_AGG (1 << 7) 3006 #define IWX_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8) 3007 #define IWX_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9) 3008 #define IWX_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10) 3009 3010 /** 3011 * Values written by fw for each Rx packet 3012 * @IWX_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 3013 * @IWX_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 3014 * @IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 3015 * @IWX_RX_MPDU_RES_STATUS_KEY_VALID: 3016 * @IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 3017 * @IWX_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 3018 * @IWX_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 3019 * in the driver. 3020 * @IWX_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 3021 * @IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 3022 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 3023 * %IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 3024 * @IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 3025 * @IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 3026 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 3027 * @IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 3028 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 3029 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 3030 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 3031 * @IWX_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 3032 * @IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 3033 * @IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 3034 * @IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 3035 * @IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 3036 * @IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 3037 * @IWX_RX_MPDU_RES_STATUS_STA_ID_MSK: 3038 * @IWX_RX_MPDU_RES_STATUS_RRF_KILL: 3039 * @IWX_RX_MPDU_RES_STATUS_FILTERING_MSK: 3040 * @IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK: 3041 */ 3042 #define IWX_RX_MPDU_RES_STATUS_CRC_OK (1 << 0) 3043 #define IWX_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1) 3044 #define IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2) 3045 #define IWX_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3) 3046 #define IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4) 3047 #define IWX_RX_MPDU_RES_STATUS_ICV_OK (1 << 5) 3048 #define IWX_RX_MPDU_RES_STATUS_MIC_OK (1 << 6) 3049 #define IWX_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7) 3050 #define IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7) 3051 #define IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8) 3052 #define IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8) 3053 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8) 3054 #define IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8) 3055 #define IWX_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8) 3056 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8) 3057 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8) 3058 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8) 3059 #define IWX_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11) 3060 #define IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12) 3061 #define IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13) 3062 #define IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14) 3063 #define IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15) 3064 #define IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000) 3065 #define IWX_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000) 3066 #define IWX_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29) 3067 #define IWX_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000) 3068 #define IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000) 3069 3070 #define IWX_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03 3071 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0 3072 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3 3073 3074 #define IWX_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f 3075 #define IWX_RX_MPDU_MFLG2_PAD 0x20 3076 #define IWX_RX_MPDU_MFLG2_AMSDU 0x40 3077 3078 #define IWX_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f 3079 #define IWX_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80 3080 3081 #define IWX_RX_MPDU_PHY_AMPDU (1 << 5) 3082 #define IWX_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6) 3083 #define IWX_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7) 3084 #define IWX_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7) 3085 #define IWX_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8) 3086 3087 struct iwx_rx_mpdu_desc_v1 { 3088 union { 3089 uint32_t rss_hash; 3090 uint32_t phy_data2; 3091 }; 3092 union { 3093 uint32_t filter_match; 3094 uint32_t phy_data3; 3095 }; 3096 uint32_t rate_n_flags; 3097 uint8_t energy_a; 3098 uint8_t energy_b; 3099 uint8_t channel; 3100 uint8_t mac_context; 3101 uint32_t gp2_on_air_rise; 3102 union { 3103 uint64_t tsf_on_air_rise; 3104 struct { 3105 uint32_t phy_data0; 3106 uint32_t phy_data1; 3107 }; 3108 }; 3109 } __packed; 3110 3111 #define IWX_RX_REORDER_DATA_INVALID_BAID 0x7f 3112 3113 #define IWX_RX_MPDU_REORDER_NSSN_MASK 0x00000fff 3114 #define IWX_RX_MPDU_REORDER_SN_MASK 0x00fff000 3115 #define IWX_RX_MPDU_REORDER_SN_SHIFT 12 3116 #define IWX_RX_MPDU_REORDER_BAID_MASK 0x7f000000 3117 #define IWX_RX_MPDU_REORDER_BAID_SHIFT 24 3118 #define IWX_RX_MPDU_REORDER_BA_OLD_SN 0x80000000 3119 3120 struct iwx_rx_mpdu_desc { 3121 uint16_t mpdu_len; 3122 uint8_t mac_flags1; 3123 uint8_t mac_flags2; 3124 uint8_t amsdu_info; 3125 uint16_t phy_info; 3126 uint8_t mac_phy_idx; 3127 uint16_t raw_csum; 3128 union { 3129 uint16_t l3l4_flags; 3130 uint16_t phy_data4; 3131 }; 3132 uint16_t status; 3133 uint8_t hash_filter; 3134 uint8_t sta_id_flags; 3135 uint32_t reorder_data; 3136 struct iwx_rx_mpdu_desc_v1 v1; 3137 } __packed; 3138 3139 /** 3140 * struct iwx_radio_version_notif - information on the radio version 3141 * ( IWX_RADIO_VERSION_NOTIFICATION = 0x68 ) 3142 * @radio_flavor: 3143 * @radio_step: 3144 * @radio_dash: 3145 */ 3146 struct iwx_radio_version_notif { 3147 uint32_t radio_flavor; 3148 uint32_t radio_step; 3149 uint32_t radio_dash; 3150 } __packed; /* IWX_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 3151 3152 #define IWX_CARD_ENABLED 0x00 3153 #define IWX_HW_CARD_DISABLED 0x01 3154 #define IWX_SW_CARD_DISABLED 0x02 3155 #define IWX_CT_KILL_CARD_DISABLED 0x04 3156 #define IWX_HALT_CARD_DISABLED 0x08 3157 #define IWX_CARD_DISABLED_MSK 0x0f 3158 #define IWX_CARD_IS_RX_ON 0x10 3159 3160 /** 3161 * struct iwx_radio_version_notif - information on the radio version 3162 * (IWX_CARD_STATE_NOTIFICATION = 0xa1 ) 3163 * @flags: %iwx_card_state_flags 3164 */ 3165 struct iwx_card_state_notif { 3166 uint32_t flags; 3167 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 3168 3169 /** 3170 * struct iwx_missed_beacons_notif - information on missed beacons 3171 * ( IWX_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 3172 * @mac_id: interface ID 3173 * @consec_missed_beacons_since_last_rx: number of consecutive missed 3174 * beacons since last RX. 3175 * @consec_missed_beacons: number of consecutive missed beacons 3176 * @num_expected_beacons: 3177 * @num_recvd_beacons: 3178 */ 3179 struct iwx_missed_beacons_notif { 3180 uint32_t mac_id; 3181 uint32_t consec_missed_beacons_since_last_rx; 3182 uint32_t consec_missed_beacons; 3183 uint32_t num_expected_beacons; 3184 uint32_t num_recvd_beacons; 3185 } __packed; /* IWX_MISSED_BEACON_NTFY_API_S_VER_3 */ 3186 3187 /** 3188 * struct iwx_mfuart_load_notif - mfuart image version & status 3189 * ( IWX_MFUART_LOAD_NOTIFICATION = 0xb1 ) 3190 * @installed_ver: installed image version 3191 * @external_ver: external image version 3192 * @status: MFUART loading status 3193 * @duration: MFUART loading time 3194 */ 3195 struct iwx_mfuart_load_notif { 3196 uint32_t installed_ver; 3197 uint32_t external_ver; 3198 uint32_t status; 3199 uint32_t duration; 3200 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 3201 3202 /** 3203 * struct iwx_set_calib_default_cmd - set default value for calibration. 3204 * ( IWX_SET_CALIB_DEFAULT_CMD = 0x8e ) 3205 * @calib_index: the calibration to set value for 3206 * @length: of data 3207 * @data: the value to set for the calibration result 3208 */ 3209 struct iwx_set_calib_default_cmd { 3210 uint16_t calib_index; 3211 uint16_t length; 3212 uint8_t data[0]; 3213 } __packed; /* IWX_PHY_CALIB_OVERRIDE_VALUES_S */ 3214 3215 #define IWX_MAX_PORT_ID_NUM 2 3216 #define IWX_MAX_MCAST_FILTERING_ADDRESSES 256 3217 3218 /** 3219 * struct iwx_mcast_filter_cmd - configure multicast filter. 3220 * @filter_own: Set 1 to filter out multicast packets sent by station itself 3221 * @port_id: Multicast MAC addresses array specifier. This is a strange way 3222 * to identify network interface adopted in host-device IF. 3223 * It is used by FW as index in array of addresses. This array has 3224 * IWX_MAX_PORT_ID_NUM members. 3225 * @count: Number of MAC addresses in the array 3226 * @pass_all: Set 1 to pass all multicast packets. 3227 * @bssid: current association BSSID. 3228 * @addr_list: Place holder for array of MAC addresses. 3229 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 3230 */ 3231 struct iwx_mcast_filter_cmd { 3232 uint8_t filter_own; 3233 uint8_t port_id; 3234 uint8_t count; 3235 uint8_t pass_all; 3236 uint8_t bssid[6]; 3237 uint8_t reserved[2]; 3238 uint8_t addr_list[0]; 3239 } __packed; /* IWX_MCAST_FILTERING_CMD_API_S_VER_1 */ 3240 3241 struct iwx_statistics_dbg { 3242 uint32_t burst_check; 3243 uint32_t burst_count; 3244 uint32_t wait_for_silence_timeout_cnt; 3245 uint32_t reserved[3]; 3246 } __packed; /* IWX_STATISTICS_DEBUG_API_S_VER_2 */ 3247 3248 struct iwx_statistics_div { 3249 uint32_t tx_on_a; 3250 uint32_t tx_on_b; 3251 uint32_t exec_time; 3252 uint32_t probe_time; 3253 uint32_t rssi_ant; 3254 uint32_t reserved2; 3255 } __packed; /* IWX_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3256 3257 struct iwx_statistics_bt_activity { 3258 uint32_t hi_priority_tx_req_cnt; 3259 uint32_t hi_priority_tx_denied_cnt; 3260 uint32_t lo_priority_tx_req_cnt; 3261 uint32_t lo_priority_tx_denied_cnt; 3262 uint32_t hi_priority_rx_req_cnt; 3263 uint32_t hi_priority_rx_denied_cnt; 3264 uint32_t lo_priority_rx_req_cnt; 3265 uint32_t lo_priority_rx_denied_cnt; 3266 } __packed; /* IWX_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3267 3268 struct iwx_statistics_general_common { 3269 uint32_t radio_temperature; 3270 struct iwx_statistics_dbg dbg; 3271 uint32_t sleep_time; 3272 uint32_t slots_out; 3273 uint32_t slots_idle; 3274 uint32_t ttl_timestamp; 3275 struct iwx_statistics_div slow_div; 3276 uint32_t rx_enable_counter; 3277 /* 3278 * num_of_sos_states: 3279 * count the number of times we have to re-tune 3280 * in order to get out of bad PHY status 3281 */ 3282 uint32_t num_of_sos_states; 3283 uint32_t beacon_filtered; 3284 uint32_t missed_beacons; 3285 uint8_t beacon_filter_average_energy; 3286 uint8_t beacon_filter_reason; 3287 uint8_t beacon_filter_current_energy; 3288 uint8_t beacon_filter_reserved; 3289 uint32_t beacon_filter_delta_time; 3290 struct iwx_statistics_bt_activity bt_activity; 3291 uint64_t rx_time; 3292 uint64_t on_time_rf; 3293 uint64_t on_time_scan; 3294 uint64_t tx_time; 3295 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */ 3296 3297 struct iwx_statistics_rx_non_phy { 3298 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3299 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3300 uint32_t non_bssid_frames; /* number of frames with BSSID that 3301 * doesn't belong to the STA BSSID */ 3302 uint32_t filtered_frames; /* count frames that were dumped in the 3303 * filtering process */ 3304 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3305 * our serving channel */ 3306 uint32_t channel_beacons; /* beacons with our bss id and in our 3307 * serving channel */ 3308 uint32_t num_missed_bcon; /* number of missed beacons */ 3309 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3310 * ADC was in saturation */ 3311 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3312 * for INA */ 3313 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3314 uint32_t interference_data_flag; /* flag for interference data 3315 * availability. 1 when data is 3316 * available. */ 3317 uint32_t channel_load; /* counts RX Enable time in uSec */ 3318 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3319 * and CCK) counter */ 3320 uint32_t beacon_rssi_a; 3321 uint32_t beacon_rssi_b; 3322 uint32_t beacon_rssi_c; 3323 uint32_t beacon_energy_a; 3324 uint32_t beacon_energy_b; 3325 uint32_t beacon_energy_c; 3326 uint32_t num_bt_kills; 3327 uint32_t mac_id; 3328 uint32_t directed_data_mpdu; 3329 } __packed; /* IWX_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3330 3331 struct iwx_statistics_rx_phy { 3332 uint32_t ina_cnt; 3333 uint32_t fina_cnt; 3334 uint32_t plcp_err; 3335 uint32_t crc32_err; 3336 uint32_t overrun_err; 3337 uint32_t early_overrun_err; 3338 uint32_t crc32_good; 3339 uint32_t false_alarm_cnt; 3340 uint32_t fina_sync_err_cnt; 3341 uint32_t sfd_timeout; 3342 uint32_t fina_timeout; 3343 uint32_t unresponded_rts; 3344 uint32_t rxe_frame_limit_overrun; 3345 uint32_t sent_ack_cnt; 3346 uint32_t sent_cts_cnt; 3347 uint32_t sent_ba_rsp_cnt; 3348 uint32_t dsp_self_kill; 3349 uint32_t mh_format_err; 3350 uint32_t re_acq_main_rssi_sum; 3351 uint32_t reserved; 3352 } __packed; /* IWX_STATISTICS_RX_PHY_API_S_VER_2 */ 3353 3354 struct iwx_statistics_rx_ht_phy { 3355 uint32_t plcp_err; 3356 uint32_t overrun_err; 3357 uint32_t early_overrun_err; 3358 uint32_t crc32_good; 3359 uint32_t crc32_err; 3360 uint32_t mh_format_err; 3361 uint32_t agg_crc32_good; 3362 uint32_t agg_mpdu_cnt; 3363 uint32_t agg_cnt; 3364 uint32_t unsupport_mcs; 3365 } __packed; /* IWX_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3366 3367 /* 3368 * The first MAC indices (starting from 0) 3369 * are available to the driver, AUX follows 3370 */ 3371 #define IWX_MAC_INDEX_AUX 4 3372 #define IWX_MAC_INDEX_MIN_DRIVER 0 3373 #define IWX_NUM_MAC_INDEX_DRIVER IWX_MAC_INDEX_AUX 3374 3375 #define IWX_STATION_COUNT 16 3376 3377 #define IWX_MAX_CHAINS 3 3378 3379 struct iwx_statistics_tx_non_phy_agg { 3380 uint32_t ba_timeout; 3381 uint32_t ba_reschedule_frames; 3382 uint32_t scd_query_agg_frame_cnt; 3383 uint32_t scd_query_no_agg; 3384 uint32_t scd_query_agg; 3385 uint32_t scd_query_mismatch; 3386 uint32_t frame_not_ready; 3387 uint32_t underrun; 3388 uint32_t bt_prio_kill; 3389 uint32_t rx_ba_rsp_cnt; 3390 int8_t txpower[IWX_MAX_CHAINS]; 3391 int8_t reserved; 3392 uint32_t reserved2; 3393 } __packed; /* IWX_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3394 3395 struct iwx_statistics_tx_channel_width { 3396 uint32_t ext_cca_narrow_ch20[1]; 3397 uint32_t ext_cca_narrow_ch40[2]; 3398 uint32_t ext_cca_narrow_ch80[3]; 3399 uint32_t ext_cca_narrow_ch160[4]; 3400 uint32_t last_tx_ch_width_indx; 3401 uint32_t rx_detected_per_ch_width[4]; 3402 uint32_t success_per_ch_width[4]; 3403 uint32_t fail_per_ch_width[4]; 3404 }; /* IWX_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3405 3406 struct iwx_statistics_tx { 3407 uint32_t preamble_cnt; 3408 uint32_t rx_detected_cnt; 3409 uint32_t bt_prio_defer_cnt; 3410 uint32_t bt_prio_kill_cnt; 3411 uint32_t few_bytes_cnt; 3412 uint32_t cts_timeout; 3413 uint32_t ack_timeout; 3414 uint32_t expected_ack_cnt; 3415 uint32_t actual_ack_cnt; 3416 uint32_t dump_msdu_cnt; 3417 uint32_t burst_abort_next_frame_mismatch_cnt; 3418 uint32_t burst_abort_missing_next_frame_cnt; 3419 uint32_t cts_timeout_collision; 3420 uint32_t ack_or_ba_timeout_collision; 3421 struct iwx_statistics_tx_non_phy_agg agg; 3422 struct iwx_statistics_tx_channel_width channel_width; 3423 } __packed; /* IWX_STATISTICS_TX_API_S_VER_4 */ 3424 3425 struct iwx_statistics_general { 3426 struct iwx_statistics_general_common common; 3427 uint32_t beacon_counter[IWX_MAC_INDEX_AUX]; 3428 uint8_t beacon_average_energy[IWX_MAC_INDEX_AUX]; 3429 uint8_t reserved[8 - IWX_MAC_INDEX_AUX]; 3430 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */ 3431 3432 struct iwx_statistics_rx { 3433 struct iwx_statistics_rx_phy ofdm; 3434 struct iwx_statistics_rx_phy cck; 3435 struct iwx_statistics_rx_non_phy general; 3436 struct iwx_statistics_rx_ht_phy ofdm_ht; 3437 } __packed; /* IWX_STATISTICS_RX_API_S_VER_3 */ 3438 3439 /* 3440 * IWX_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3441 * 3442 * By default, uCode issues this notification after receiving a beacon 3443 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3444 * IWX_REPLY_STATISTICS_CMD 0x9c, above. 3445 * 3446 * Statistics counters continue to increment beacon after beacon, but are 3447 * cleared when changing channels or when driver issues IWX_REPLY_STATISTICS_CMD 3448 * 0x9c with CLEAR_STATS bit set (see above). 3449 * 3450 * uCode also issues this notification during scans. uCode clears statistics 3451 * appropriately so that each notification contains statistics for only the 3452 * one channel that has just been scanned. 3453 */ 3454 3455 /** 3456 * struct iwx_statistics_load - RX statistics for multi-queue devices 3457 * @air_time: accumulated air time, per mac 3458 * @byte_count: accumulated byte count, per mac 3459 * @pkt_count: accumulated packet count, per mac 3460 * @avg_energy: average RSSI, per station 3461 */ 3462 struct iwx_statistics_load { 3463 uint32_t air_time[IWX_MAC_INDEX_AUX]; 3464 uint32_t byte_count[IWX_MAC_INDEX_AUX]; 3465 uint32_t pkt_count[IWX_MAC_INDEX_AUX]; 3466 uint8_t avg_energy[IWX_STATION_COUNT]; 3467 } __packed; /* STATISTICS_RX_MAC_STATION_S_VER_3 */ 3468 3469 struct iwx_notif_statistics { 3470 uint32_t flag; 3471 struct iwx_statistics_rx rx; 3472 struct iwx_statistics_tx tx; 3473 struct iwx_statistics_general general; 3474 struct iwx_statistics_load load_stats; 3475 } __packed; /* STATISTICS_NTFY_API_S_VER_13 */ 3476 3477 3478 /** 3479 * flags used in statistics notification 3480 * @IWX_STATISTICS_REPLY_FLG_CLEAR: statistics were cleared after this report 3481 */ 3482 #define IWX_STATISTICS_REPLY_FLG_CLEAR 0x01 3483 3484 /** 3485 * flags used in statistics command 3486 * @IWX_STATISTICS_FLG_CLEAR: request to clear statistics after the report 3487 * that's sent after this command 3488 * @IWX_STATISTICS_FLG_DISABLE_NOTIF: disable unilateral statistics 3489 * notifications 3490 */ 3491 #define IWX_STATISTICS_FLG_CLEAR 0x01 3492 #define IWX_STATISTICS_FLG_DISABLE_NOTIF 0x02 3493 3494 /** 3495 * struct iwx_statistics_cmd - statistics config command 3496 * @flags: IWX_STATISTICS_* flags 3497 */ 3498 struct iwx_statistics_cmd { 3499 uint32_t flags; 3500 } __packed; /* STATISTICS_CMD_API_S_VER_1 */ 3501 3502 3503 /*********************************** 3504 * Smart Fifo API 3505 ***********************************/ 3506 /* Smart Fifo state */ 3507 #define IWX_SF_LONG_DELAY_ON 0 /* should never be called by driver */ 3508 #define IWX_SF_FULL_ON 1 3509 #define IWX_SF_UNINIT 2 3510 #define IWX_SF_INIT_OFF 3 3511 #define IWX_SF_HW_NUM_STATES 4 3512 3513 /* Smart Fifo possible scenario */ 3514 #define IWX_SF_SCENARIO_SINGLE_UNICAST 0 3515 #define IWX_SF_SCENARIO_AGG_UNICAST 1 3516 #define IWX_SF_SCENARIO_MULTICAST 2 3517 #define IWX_SF_SCENARIO_BA_RESP 3 3518 #define IWX_SF_SCENARIO_TX_RESP 4 3519 #define IWX_SF_NUM_SCENARIO 5 3520 3521 #define IWX_SF_TRANSIENT_STATES_NUMBER 2 /* IWX_SF_LONG_DELAY_ON and IWX_SF_FULL_ON */ 3522 #define IWX_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3523 3524 /* smart FIFO default values */ 3525 #define IWX_SF_W_MARK_SISO 4096 3526 #define IWX_SF_W_MARK_MIMO2 8192 3527 #define IWX_SF_W_MARK_MIMO3 6144 3528 #define IWX_SF_W_MARK_LEGACY 4096 3529 #define IWX_SF_W_MARK_SCAN 4096 3530 3531 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3532 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3533 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3534 #define IWX_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3535 #define IWX_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3536 #define IWX_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3537 #define IWX_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3538 #define IWX_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3539 #define IWX_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3540 #define IWX_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3541 #define IWX_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3542 3543 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3544 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3545 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3546 #define IWX_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3547 #define IWX_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3548 #define IWX_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3549 #define IWX_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3550 #define IWX_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3551 #define IWX_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3552 #define IWX_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3553 #define IWX_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3554 3555 #define IWX_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3556 3557 #define IWX_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3558 3559 /** 3560 * Smart Fifo configuration command. 3561 * @state: smart fifo state, types listed in enum %iwx_sf_state. 3562 * @watermark: Minimum allowed availabe free space in RXF for transient state. 3563 * @long_delay_timeouts: aging and idle timer values for each scenario 3564 * in long delay state. 3565 * @full_on_timeouts: timer values for each scenario in full on state. 3566 */ 3567 struct iwx_sf_cfg_cmd { 3568 uint32_t state; 3569 uint32_t watermark[IWX_SF_TRANSIENT_STATES_NUMBER]; 3570 uint32_t long_delay_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES]; 3571 uint32_t full_on_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES]; 3572 } __packed; /* IWX_SF_CFG_API_S_VER_2 */ 3573 3574 #define IWX_AC_BK 0 3575 #define IWX_AC_BE 1 3576 #define IWX_AC_VI 2 3577 #define IWX_AC_VO 3 3578 #define IWX_AC_NUM 4 3579 3580 /** 3581 * MAC context flags 3582 * @IWX_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3583 * this will require CCK RTS/CTS2self. 3584 * RTS/CTS will protect full burst time. 3585 * @IWX_MAC_PROT_FLG_HT_PROT: enable HT protection 3586 * @IWX_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3587 * @IWX_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3588 */ 3589 #define IWX_MAC_PROT_FLG_TGG_PROTECT (1 << 3) 3590 #define IWX_MAC_PROT_FLG_HT_PROT (1 << 23) 3591 #define IWX_MAC_PROT_FLG_FAT_PROT (1 << 24) 3592 #define IWX_MAC_PROT_FLG_SELF_CTS_EN (1 << 30) 3593 3594 #define IWX_MAC_FLG_SHORT_SLOT (1 << 4) 3595 #define IWX_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3596 3597 /** 3598 * Supported MAC types 3599 * @IWX_FW_MAC_TYPE_FIRST: lowest supported MAC type 3600 * @IWX_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3601 * @IWX_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3602 * @IWX_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3603 * @IWX_FW_MAC_TYPE_IBSS: IBSS 3604 * @IWX_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3605 * @IWX_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3606 * @IWX_FW_MAC_TYPE_P2P_STA: P2P client 3607 * @IWX_FW_MAC_TYPE_GO: P2P GO 3608 * @IWX_FW_MAC_TYPE_TEST: ? 3609 * @IWX_FW_MAC_TYPE_MAX: highest support MAC type 3610 */ 3611 #define IWX_FW_MAC_TYPE_FIRST 1 3612 #define IWX_FW_MAC_TYPE_AUX IWX_FW_MAC_TYPE_FIRST 3613 #define IWX_FW_MAC_TYPE_LISTENER 2 3614 #define IWX_FW_MAC_TYPE_PIBSS 3 3615 #define IWX_FW_MAC_TYPE_IBSS 4 3616 #define IWX_FW_MAC_TYPE_BSS_STA 5 3617 #define IWX_FW_MAC_TYPE_P2P_DEVICE 6 3618 #define IWX_FW_MAC_TYPE_P2P_STA 7 3619 #define IWX_FW_MAC_TYPE_GO 8 3620 #define IWX_FW_MAC_TYPE_TEST 9 3621 #define IWX_FW_MAC_TYPE_MAX IWX_FW_MAC_TYPE_TEST 3622 /* IWX_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3623 3624 /** 3625 * TSF hw timer ID 3626 * @IWX_TSF_ID_A: use TSF A 3627 * @IWX_TSF_ID_B: use TSF B 3628 * @IWX_TSF_ID_C: use TSF C 3629 * @IWX_TSF_ID_D: use TSF D 3630 * @IWX_NUM_TSF_IDS: number of TSF timers available 3631 */ 3632 #define IWX_TSF_ID_A 0 3633 #define IWX_TSF_ID_B 1 3634 #define IWX_TSF_ID_C 2 3635 #define IWX_TSF_ID_D 3 3636 #define IWX_NUM_TSF_IDS 4 3637 /* IWX_TSF_ID_API_E_VER_1 */ 3638 3639 /** 3640 * struct iwx_mac_data_ap - configuration data for AP MAC context 3641 * @beacon_time: beacon transmit time in system time 3642 * @beacon_tsf: beacon transmit time in TSF 3643 * @bi: beacon interval in TU 3644 * @bi_reciprocal: 2^32 / bi 3645 * @dtim_interval: dtim transmit time in TU 3646 * @dtim_reciprocal: 2^32 / dtim_interval 3647 * @mcast_qid: queue ID for multicast traffic 3648 * NOTE: obsolete from VER2 and on 3649 * @beacon_template: beacon template ID 3650 */ 3651 struct iwx_mac_data_ap { 3652 uint32_t beacon_time; 3653 uint64_t beacon_tsf; 3654 uint32_t bi; 3655 uint32_t bi_reciprocal; 3656 uint32_t dtim_interval; 3657 uint32_t dtim_reciprocal; 3658 uint32_t mcast_qid; 3659 uint32_t beacon_template; 3660 } __packed; /* AP_MAC_DATA_API_S_VER_2 */ 3661 3662 /** 3663 * struct iwx_mac_data_ibss - configuration data for IBSS MAC context 3664 * @beacon_time: beacon transmit time in system time 3665 * @beacon_tsf: beacon transmit time in TSF 3666 * @bi: beacon interval in TU 3667 * @bi_reciprocal: 2^32 / bi 3668 * @beacon_template: beacon template ID 3669 */ 3670 struct iwx_mac_data_ibss { 3671 uint32_t beacon_time; 3672 uint64_t beacon_tsf; 3673 uint32_t bi; 3674 uint32_t bi_reciprocal; 3675 uint32_t beacon_template; 3676 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3677 3678 /** 3679 * struct iwx_mac_data_sta - configuration data for station MAC context 3680 * @is_assoc: 1 for associated state, 0 otherwise 3681 * @dtim_time: DTIM arrival time in system time 3682 * @dtim_tsf: DTIM arrival time in TSF 3683 * @bi: beacon interval in TU, applicable only when associated 3684 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3685 * @dtim_interval: DTIM interval in TU, applicable only when associated 3686 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3687 * @listen_interval: in beacon intervals, applicable only when associated 3688 * @assoc_id: unique ID assigned by the AP during association 3689 */ 3690 struct iwx_mac_data_sta { 3691 uint32_t is_assoc; 3692 uint32_t dtim_time; 3693 uint64_t dtim_tsf; 3694 uint32_t bi; 3695 uint32_t bi_reciprocal; 3696 uint32_t dtim_interval; 3697 uint32_t dtim_reciprocal; 3698 uint32_t listen_interval; 3699 uint32_t assoc_id; 3700 uint32_t assoc_beacon_arrive_time; 3701 } __packed; /* IWX_STA_MAC_DATA_API_S_VER_1 */ 3702 3703 /** 3704 * struct iwx_mac_data_go - configuration data for P2P GO MAC context 3705 * @ap: iwx_mac_data_ap struct with most config data 3706 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3707 * 0 indicates that there is no CT window. 3708 * @opp_ps_enabled: indicate that opportunistic PS allowed 3709 */ 3710 struct iwx_mac_data_go { 3711 struct iwx_mac_data_ap ap; 3712 uint32_t ctwin; 3713 uint32_t opp_ps_enabled; 3714 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3715 3716 /** 3717 * struct iwx_mac_data_p2p_sta - configuration data for P2P client MAC context 3718 * @sta: iwx_mac_data_sta struct with most config data 3719 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3720 * 0 indicates that there is no CT window. 3721 */ 3722 struct iwx_mac_data_p2p_sta { 3723 struct iwx_mac_data_sta sta; 3724 uint32_t ctwin; 3725 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3726 3727 /** 3728 * struct iwx_mac_data_pibss - Pseudo IBSS config data 3729 * @stats_interval: interval in TU between statistics notifications to host. 3730 */ 3731 struct iwx_mac_data_pibss { 3732 uint32_t stats_interval; 3733 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3734 3735 /* 3736 * struct iwx_mac_data_p2p_dev - configuration data for the P2P Device MAC 3737 * context. 3738 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3739 * other channels as well. This should be to true only in case that the 3740 * device is discoverable and there is an active GO. Note that setting this 3741 * field when not needed, will increase the number of interrupts and have 3742 * effect on the platform power, as this setting opens the Rx filters on 3743 * all macs. 3744 */ 3745 struct iwx_mac_data_p2p_dev { 3746 uint32_t is_disc_extended; 3747 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3748 3749 /** 3750 * MAC context filter flags 3751 * @IWX_MAC_FILTER_IN_PROMISC: accept all data frames 3752 * @IWX_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3753 * control frames to the host 3754 * @IWX_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3755 * @IWX_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3756 * @IWX_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3757 * @IWX_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3758 * (in station mode when associated) 3759 * @IWX_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3760 * @IWX_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3761 * @IWX_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3762 */ 3763 #define IWX_MAC_FILTER_IN_PROMISC (1 << 0) 3764 #define IWX_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1) 3765 #define IWX_MAC_FILTER_ACCEPT_GRP (1 << 2) 3766 #define IWX_MAC_FILTER_DIS_DECRYPT (1 << 3) 3767 #define IWX_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4) 3768 #define IWX_MAC_FILTER_IN_BEACON (1 << 6) 3769 #define IWX_MAC_FILTER_OUT_BCAST (1 << 8) 3770 #define IWX_MAC_FILTER_IN_CRC32 (1 << 11) 3771 #define IWX_MAC_FILTER_IN_PROBE_REQUEST (1 << 12) 3772 3773 /** 3774 * QoS flags 3775 * @IWX_MAC_QOS_FLG_UPDATE_EDCA: ? 3776 * @IWX_MAC_QOS_FLG_TGN: HT is enabled 3777 * @IWX_MAC_QOS_FLG_TXOP_TYPE: ? 3778 * 3779 */ 3780 #define IWX_MAC_QOS_FLG_UPDATE_EDCA (1 << 0) 3781 #define IWX_MAC_QOS_FLG_TGN (1 << 1) 3782 #define IWX_MAC_QOS_FLG_TXOP_TYPE (1 << 4) 3783 3784 /** 3785 * struct iwx_ac_qos - QOS timing params for IWX_MAC_CONTEXT_CMD 3786 * @cw_min: Contention window, start value in numbers of slots. 3787 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3788 * @cw_max: Contention window, max value in numbers of slots. 3789 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3790 * @aifsn: Number of slots in Arbitration Interframe Space (before 3791 * performing random backoff timing prior to Tx). Device default 1. 3792 * @fifos_mask: FIFOs used by this MAC for this AC 3793 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3794 * 3795 * One instance of this config struct for each of 4 EDCA access categories 3796 * in struct iwx_qosparam_cmd. 3797 * 3798 * Device will automatically increase contention window by (2*CW) + 1 for each 3799 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3800 * value, to cap the CW value. 3801 */ 3802 struct iwx_ac_qos { 3803 uint16_t cw_min; 3804 uint16_t cw_max; 3805 uint8_t aifsn; 3806 uint8_t fifos_mask; 3807 uint16_t edca_txop; 3808 } __packed; /* IWX_AC_QOS_API_S_VER_2 */ 3809 3810 /** 3811 * struct iwx_mac_ctx_cmd - command structure to configure MAC contexts 3812 * ( IWX_MAC_CONTEXT_CMD = 0x28 ) 3813 * @id_and_color: ID and color of the MAC 3814 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3815 * @mac_type: one of IWX_FW_MAC_TYPE_* 3816 * @tsf_id: TSF HW timer, one of IWX_TSF_ID_* 3817 * @node_addr: MAC address 3818 * @bssid_addr: BSSID 3819 * @cck_rates: basic rates available for CCK 3820 * @ofdm_rates: basic rates available for OFDM 3821 * @protection_flags: combination of IWX_MAC_PROT_FLG_FLAG_* 3822 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3823 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3824 * @filter_flags: combination of IWX_MAC_FILTER_* 3825 * @qos_flags: from IWX_MAC_QOS_FLG_* 3826 * @ac: one iwx_mac_qos configuration for each AC 3827 * @mac_specific: one of struct iwx_mac_data_*, according to mac_type 3828 */ 3829 struct iwx_mac_ctx_cmd { 3830 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3831 uint32_t id_and_color; 3832 uint32_t action; 3833 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3834 uint32_t mac_type; 3835 uint32_t tsf_id; 3836 uint8_t node_addr[6]; 3837 uint16_t reserved_for_node_addr; 3838 uint8_t bssid_addr[6]; 3839 uint16_t reserved_for_bssid_addr; 3840 uint32_t cck_rates; 3841 uint32_t ofdm_rates; 3842 uint32_t protection_flags; 3843 uint32_t cck_short_preamble; 3844 uint32_t short_slot; 3845 uint32_t filter_flags; 3846 /* IWX_MAC_QOS_PARAM_API_S_VER_1 */ 3847 uint32_t qos_flags; 3848 struct iwx_ac_qos ac[IWX_AC_NUM+1]; 3849 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S */ 3850 union { 3851 struct iwx_mac_data_ap ap; 3852 struct iwx_mac_data_go go; 3853 struct iwx_mac_data_sta sta; 3854 struct iwx_mac_data_p2p_sta p2p_sta; 3855 struct iwx_mac_data_p2p_dev p2p_dev; 3856 struct iwx_mac_data_pibss pibss; 3857 struct iwx_mac_data_ibss ibss; 3858 }; 3859 } __packed; /* IWX_MAC_CONTEXT_CMD_API_S_VER_1 */ 3860 3861 static inline uint32_t iwx_reciprocal(uint32_t v) 3862 { 3863 if (!v) 3864 return 0; 3865 return 0xFFFFFFFF / v; 3866 } 3867 3868 /* Power Management Commands, Responses, Notifications */ 3869 3870 /** 3871 * masks for LTR config command flags 3872 * @IWX_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 3873 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 3874 * memory access 3875 * @IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 3876 * reg change 3877 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 3878 * D0 to D3 3879 * @IWX_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 3880 * @IWX_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 3881 * @IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 3882 */ 3883 #define IWX_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001 3884 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002 3885 #define IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004 3886 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008 3887 #define IWX_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010 3888 #define IWX_LTR_CFG_FLAG_SW_SET_LONG 0x00000020 3889 #define IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040 3890 3891 #define IWX_LTR_VALID_STATES_NUM 4 3892 3893 /** 3894 * struct iwx_ltr_config_cmd - configures the LTR 3895 * @flags: See %enum iwx_ltr_config_flags 3896 * @static_long: 3897 * @static_short: 3898 * @ltr_cfg_values: 3899 * @ltr_short_idle_timeout: 3900 */ 3901 struct iwx_ltr_config_cmd { 3902 uint32_t flags; 3903 uint32_t static_long; 3904 uint32_t static_short; 3905 uint32_t ltr_cfg_values[IWX_LTR_VALID_STATES_NUM]; 3906 uint32_t ltr_short_idle_timeout; 3907 } __packed; /* LTR_CAPABLE_API_S_VER_2 */ 3908 3909 /* Radio LP RX Energy Threshold measured in dBm */ 3910 #define IWX_POWER_LPRX_RSSI_THRESHOLD 75 3911 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3912 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3913 3914 /** 3915 * Masks for iwx_mac_power_cmd command flags 3916 * @IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3917 * receiver and transmitter. '0' - does not allow. 3918 * @IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3919 * '1' Driver enables PM (use rest of parameters) 3920 * @IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3921 * '1' PM could sleep over DTIM till listen Interval. 3922 * @IWX_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3923 * access categories are both delivery and trigger enabled. 3924 * @IWX_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3925 * PBW Snoozing enabled 3926 * @IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3927 * @IWX_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3928 * @IWX_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3929 * detection enablement 3930 */ 3931 #define IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 3932 #define IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1) 3933 #define IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2) 3934 #define IWX_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5) 3935 #define IWX_POWER_FLAGS_BT_SCO_ENA (1 << 8) 3936 #define IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9) 3937 #define IWX_POWER_FLAGS_LPRX_ENA_MSK (1 << 11) 3938 #define IWX_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12) 3939 3940 #define IWX_POWER_VEC_SIZE 5 3941 3942 /** 3943 * Masks for device power command flags 3944 * @IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 3945 * '1' Allow to save power by turning off receiver and transmitter. 3946 * '0' Do not allow. This flag should be always set to '1' unless 3947 * one needs to disable actual power down for debug purposes. 3948 * @IWX_DEVICE_POWER_FLAGS_CAM_MSK: 3949 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 3950 * '0' Power management is enabled, one of the power schemes is applied. 3951 */ 3952 #define IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 3953 #define IWX_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13) 3954 3955 /** 3956 * struct iwx_device_power_cmd - device wide power command. 3957 * IWX_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3958 * 3959 * @flags: Power table command flags from IWX_DEVICE_POWER_FLAGS_* 3960 */ 3961 struct iwx_device_power_cmd { 3962 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3963 uint16_t flags; 3964 uint16_t reserved; 3965 } __packed; 3966 3967 /** 3968 * struct iwx_mac_power_cmd - New power command containing uAPSD support 3969 * IWX_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3970 * @id_and_color: MAC contex identifier 3971 * @flags: Power table command flags from POWER_FLAGS_* 3972 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3973 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3974 * set regardless of power scheme or current power state. 3975 * FW use this value also when PM is disabled. 3976 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3977 * PSM transition - legacy PM 3978 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3979 * PSM transition - legacy PM 3980 * @sleep_interval: not in use 3981 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3982 * is set. For example, if it is required to skip over 3983 * one DTIM, this value need to be set to 2 (DTIM periods). 3984 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3985 * PSM transition - uAPSD 3986 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3987 * PSM transition - uAPSD 3988 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3989 * Default: 80dbm 3990 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3991 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3992 * from the AP [msec] 3993 * @snooze_window: A window of time in which PBW snoozing insures that all 3994 * packets received. It is also the minimum time from last 3995 * received unicast RX packet, before client stops snoozing 3996 * for data. [msec] 3997 * @snooze_step: TBD 3998 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3999 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 4000 * each corresponding AC. 4001 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 4002 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 4003 * values. 4004 * @heavy_tx_thld_packets: TX threshold measured in number of packets 4005 * @heavy_rx_thld_packets: RX threshold measured in number of packets 4006 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 4007 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 4008 * @limited_ps_threshold: 4009 */ 4010 struct iwx_mac_power_cmd { 4011 /* CONTEXT_DESC_API_T_VER_1 */ 4012 uint32_t id_and_color; 4013 4014 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 4015 uint16_t flags; 4016 uint16_t keep_alive_seconds; 4017 uint32_t rx_data_timeout; 4018 uint32_t tx_data_timeout; 4019 uint32_t rx_data_timeout_uapsd; 4020 uint32_t tx_data_timeout_uapsd; 4021 uint8_t lprx_rssi_threshold; 4022 uint8_t skip_dtim_periods; 4023 uint16_t snooze_interval; 4024 uint16_t snooze_window; 4025 uint8_t snooze_step; 4026 uint8_t qndp_tid; 4027 uint8_t uapsd_ac_flags; 4028 uint8_t uapsd_max_sp; 4029 uint8_t heavy_tx_thld_packets; 4030 uint8_t heavy_rx_thld_packets; 4031 uint8_t heavy_tx_thld_percentage; 4032 uint8_t heavy_rx_thld_percentage; 4033 uint8_t limited_ps_threshold; 4034 uint8_t reserved; 4035 } __packed; 4036 4037 #define IWX_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 4038 #define IWX_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 4039 4040 /* 4041 * struct iwx_uapsd_misbehaving_ap_notif - FW sends this notification when 4042 * associated AP is identified as improperly implementing uAPSD protocol. 4043 * IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 4044 * @sta_id: index of station in uCode's station table - associated AP ID in 4045 * this context. 4046 */ 4047 struct iwx_uapsd_misbehaving_ap_notif { 4048 uint32_t sta_id; 4049 uint8_t mac_id; 4050 uint8_t reserved[3]; 4051 } __packed; 4052 4053 /** 4054 * struct iwx_beacon_filter_cmd 4055 * IWX_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 4056 * @id_and_color: MAC contex identifier 4057 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 4058 * to driver if delta in Energy values calculated for this and last 4059 * passed beacon is greater than this threshold. Zero value means that 4060 * the Energy change is ignored for beacon filtering, and beacon will 4061 * not be forced to be sent to driver regardless of this delta. Typical 4062 * energy delta 5dB. 4063 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 4064 * Send beacon to driver if delta in Energy values calculated for this 4065 * and last passed beacon is greater than this threshold. Zero value 4066 * means that the Energy change is ignored for beacon filtering while in 4067 * Roaming state, typical energy delta 1dB. 4068 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 4069 * calculated for current beacon is less than the threshold, use 4070 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 4071 * Threshold. Typical energy threshold is -72dBm. 4072 * @bf_temp_threshold: This threshold determines the type of temperature 4073 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 4074 * If the current temperature is above this threshold - Fast filter 4075 * will be used, If the current temperature is below this threshold - 4076 * Slow filter will be used. 4077 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 4078 * calculated for this and the last passed beacon is greater than this 4079 * threshold. Zero value means that the temperature change is ignored for 4080 * beacon filtering; beacons will not be forced to be sent to driver 4081 * regardless of whether its temerature has been changed. 4082 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 4083 * calculated for this and the last passed beacon is greater than this 4084 * threshold. Zero value means that the temperature change is ignored for 4085 * beacon filtering; beacons will not be forced to be sent to driver 4086 * regardless of whether its temerature has been changed. 4087 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 4088 * @bf_escape_timer: Send beacons to driver if no beacons were passed 4089 * for a specific period of time. Units: Beacons. 4090 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 4091 * for a longer period of time then this escape-timeout. Units: Beacons. 4092 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 4093 * @bf_threshold_absolute_low: See below. 4094 * @bf_threshold_absolute_high: Send Beacon to driver if Energy value calculated 4095 * for this beacon crossed this absolute threshold. For the 'Increase' 4096 * direction the bf_energy_absolute_low[i] is used. For the 'Decrease' 4097 * direction the bf_energy_absolute_high[i] is used. Zero value means 4098 * that this specific threshold is ignored for beacon filtering, and 4099 * beacon will not be forced to be sent to driver due to this setting. 4100 */ 4101 struct iwx_beacon_filter_cmd { 4102 uint32_t bf_energy_delta; 4103 uint32_t bf_roaming_energy_delta; 4104 uint32_t bf_roaming_state; 4105 uint32_t bf_temp_threshold; 4106 uint32_t bf_temp_fast_filter; 4107 uint32_t bf_temp_slow_filter; 4108 uint32_t bf_enable_beacon_filter; 4109 uint32_t bf_debug_flag; 4110 uint32_t bf_escape_timer; 4111 uint32_t ba_escape_timer; 4112 uint32_t ba_enable_beacon_abort; 4113 uint32_t bf_threshold_absolute_low[2]; 4114 uint32_t bf_threshold_absolute_high[2]; 4115 } __packed; /* BEACON_FILTER_CONFIG_API_S_VER_4 */ 4116 4117 /* Beacon filtering and beacon abort */ 4118 #define IWX_BF_ENERGY_DELTA_DEFAULT 5 4119 #define IWX_BF_ENERGY_DELTA_MAX 255 4120 #define IWX_BF_ENERGY_DELTA_MIN 0 4121 4122 #define IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 4123 #define IWX_BF_ROAMING_ENERGY_DELTA_MAX 255 4124 #define IWX_BF_ROAMING_ENERGY_DELTA_MIN 0 4125 4126 #define IWX_BF_ROAMING_STATE_DEFAULT 72 4127 #define IWX_BF_ROAMING_STATE_MAX 255 4128 #define IWX_BF_ROAMING_STATE_MIN 0 4129 4130 #define IWX_BF_TEMP_THRESHOLD_DEFAULT 112 4131 #define IWX_BF_TEMP_THRESHOLD_MAX 255 4132 #define IWX_BF_TEMP_THRESHOLD_MIN 0 4133 4134 #define IWX_BF_TEMP_FAST_FILTER_DEFAULT 1 4135 #define IWX_BF_TEMP_FAST_FILTER_MAX 255 4136 #define IWX_BF_TEMP_FAST_FILTER_MIN 0 4137 4138 #define IWX_BF_TEMP_SLOW_FILTER_DEFAULT 5 4139 #define IWX_BF_TEMP_SLOW_FILTER_MAX 255 4140 #define IWX_BF_TEMP_SLOW_FILTER_MIN 0 4141 4142 #define IWX_BF_ENABLE_BEACON_FILTER_DEFAULT 1 4143 4144 #define IWX_BF_DEBUG_FLAG_DEFAULT 0 4145 4146 #define IWX_BF_ESCAPE_TIMER_DEFAULT 50 4147 #define IWX_BF_ESCAPE_TIMER_MAX 1024 4148 #define IWX_BF_ESCAPE_TIMER_MIN 0 4149 4150 #define IWX_BA_ESCAPE_TIMER_DEFAULT 6 4151 #define IWX_BA_ESCAPE_TIMER_D3 9 4152 #define IWX_BA_ESCAPE_TIMER_MAX 1024 4153 #define IWX_BA_ESCAPE_TIMER_MIN 0 4154 4155 #define IWX_BA_ENABLE_BEACON_ABORT_DEFAULT 1 4156 4157 #define IWX_BF_CMD_CONFIG_DEFAULTS \ 4158 .bf_energy_delta = htole32(IWX_BF_ENERGY_DELTA_DEFAULT), \ 4159 .bf_roaming_energy_delta = \ 4160 htole32(IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 4161 .bf_roaming_state = htole32(IWX_BF_ROAMING_STATE_DEFAULT), \ 4162 .bf_temp_threshold = htole32(IWX_BF_TEMP_THRESHOLD_DEFAULT), \ 4163 .bf_temp_fast_filter = htole32(IWX_BF_TEMP_FAST_FILTER_DEFAULT), \ 4164 .bf_temp_slow_filter = htole32(IWX_BF_TEMP_SLOW_FILTER_DEFAULT), \ 4165 .bf_debug_flag = htole32(IWX_BF_DEBUG_FLAG_DEFAULT), \ 4166 .bf_escape_timer = htole32(IWX_BF_ESCAPE_TIMER_DEFAULT), \ 4167 .ba_escape_timer = htole32(IWX_BA_ESCAPE_TIMER_DEFAULT) 4168 4169 /* uCode API values for HT/VHT bit rates */ 4170 #define IWX_RATE_HT_SISO_MCS_0_PLCP 0 4171 #define IWX_RATE_HT_SISO_MCS_1_PLCP 1 4172 #define IWX_RATE_HT_SISO_MCS_2_PLCP 2 4173 #define IWX_RATE_HT_SISO_MCS_3_PLCP 3 4174 #define IWX_RATE_HT_SISO_MCS_4_PLCP 4 4175 #define IWX_RATE_HT_SISO_MCS_5_PLCP 5 4176 #define IWX_RATE_HT_SISO_MCS_6_PLCP 6 4177 #define IWX_RATE_HT_SISO_MCS_7_PLCP 7 4178 #define IWX_RATE_HT_MIMO2_MCS_8_PLCP 0x8 4179 #define IWX_RATE_HT_MIMO2_MCS_9_PLCP 0x9 4180 #define IWX_RATE_HT_MIMO2_MCS_10_PLCP 0xA 4181 #define IWX_RATE_HT_MIMO2_MCS_11_PLCP 0xB 4182 #define IWX_RATE_HT_MIMO2_MCS_12_PLCP 0xC 4183 #define IWX_RATE_HT_MIMO2_MCS_13_PLCP 0xD 4184 #define IWX_RATE_HT_MIMO2_MCS_14_PLCP 0xE 4185 #define IWX_RATE_HT_MIMO2_MCS_15_PLCP 0xF 4186 #define IWX_RATE_VHT_SISO_MCS_0_PLCP 0 4187 #define IWX_RATE_VHT_SISO_MCS_1_PLCP 1 4188 #define IWX_RATE_VHT_SISO_MCS_2_PLCP 2 4189 #define IWX_RATE_VHT_SISO_MCS_3_PLCP 3 4190 #define IWX_RATE_VHT_SISO_MCS_4_PLCP 4 4191 #define IWX_RATE_VHT_SISO_MCS_5_PLCP 5 4192 #define IWX_RATE_VHT_SISO_MCS_6_PLCP 6 4193 #define IWX_RATE_VHT_SISO_MCS_7_PLCP 7 4194 #define IWX_RATE_VHT_SISO_MCS_8_PLCP 8 4195 #define IWX_RATE_VHT_SISO_MCS_9_PLCP 9 4196 #define IWX_RATE_VHT_MIMO2_MCS_0_PLCP 0x10 4197 #define IWX_RATE_VHT_MIMO2_MCS_1_PLCP 0x11 4198 #define IWX_RATE_VHT_MIMO2_MCS_2_PLCP 0x12 4199 #define IWX_RATE_VHT_MIMO2_MCS_3_PLCP 0x13 4200 #define IWX_RATE_VHT_MIMO2_MCS_4_PLCP 0x14 4201 #define IWX_RATE_VHT_MIMO2_MCS_5_PLCP 0x15 4202 #define IWX_RATE_VHT_MIMO2_MCS_6_PLCP 0x16 4203 #define IWX_RATE_VHT_MIMO2_MCS_7_PLCP 0x17 4204 #define IWX_RATE_VHT_MIMO2_MCS_8_PLCP 0x18 4205 #define IWX_RATE_VHT_MIMO2_MCS_9_PLCP 0x19 4206 #define IWX_RATE_HT_SISO_MCS_INV_PLCP 0x20 4207 #define IWX_RATE_HT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4208 #define IWX_RATE_VHT_SISO_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4209 #define IWX_RATE_VHT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4210 #define IWX_RATE_HT_SISO_MCS_8_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4211 #define IWX_RATE_HT_SISO_MCS_9_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4212 4213 /* 4214 * These serve as indexes into struct iwx_rate iwx_rates[IWX_RIDX_MAX]. 4215 */ 4216 enum { 4217 IWX_RATE_1M_INDEX = 0, 4218 IWX_FIRST_CCK_RATE = IWX_RATE_1M_INDEX, 4219 IWX_RATE_2M_INDEX, 4220 IWX_RATE_5M_INDEX, 4221 IWX_RATE_11M_INDEX, 4222 IWX_LAST_CCK_RATE = IWX_RATE_11M_INDEX, 4223 IWX_RATE_6M_INDEX, 4224 IWX_FIRST_OFDM_RATE = IWX_RATE_6M_INDEX, 4225 IWX_RATE_MCS_0_INDEX = IWX_RATE_6M_INDEX, 4226 IWX_FIRST_HT_RATE = IWX_RATE_MCS_0_INDEX, 4227 IWX_FIRST_VHT_RATE = IWX_RATE_MCS_0_INDEX, 4228 IWX_RATE_9M_INDEX, 4229 IWX_RATE_12M_INDEX, 4230 IWX_RATE_MCS_1_INDEX = IWX_RATE_12M_INDEX, 4231 IWX_RATE_MCS_8_INDEX, 4232 IWX_FIRST_HT_MIMO2_RATE = IWX_RATE_MCS_8_INDEX, 4233 IWX_RATE_18M_INDEX, 4234 IWX_RATE_MCS_2_INDEX = IWX_RATE_18M_INDEX, 4235 IWX_RATE_24M_INDEX, 4236 IWX_RATE_MCS_3_INDEX = IWX_RATE_24M_INDEX, 4237 IWX_RATE_MCS_9_INDEX, 4238 IWX_RATE_36M_INDEX, 4239 IWX_RATE_MCS_4_INDEX = IWX_RATE_36M_INDEX, 4240 IWX_RATE_MCS_10_INDEX, 4241 IWX_RATE_48M_INDEX, 4242 IWX_RATE_MCS_5_INDEX = IWX_RATE_48M_INDEX, 4243 IWX_RATE_MCS_11_INDEX, 4244 IWX_RATE_54M_INDEX, 4245 IWX_RATE_MCS_6_INDEX = IWX_RATE_54M_INDEX, 4246 IWX_LAST_NON_HT_RATE = IWX_RATE_54M_INDEX, 4247 IWX_RATE_MCS_7_INDEX, 4248 IWX_LAST_HT_SISO_RATE = IWX_RATE_MCS_7_INDEX, 4249 IWX_RATE_MCS_12_INDEX, 4250 IWX_RATE_MCS_13_INDEX, 4251 IWX_RATE_MCS_14_INDEX, 4252 IWX_RATE_MCS_15_INDEX, 4253 IWX_LAST_HT_RATE = IWX_RATE_MCS_15_INDEX, 4254 IWX_LAST_VHT_RATE = IWX_RATE_MCS_9_INDEX, 4255 IWX_RATE_COUNT_LEGACY = IWX_LAST_NON_HT_RATE + 1, 4256 IWX_RATE_COUNT = IWX_LAST_HT_RATE + 1, 4257 }; 4258 4259 #define IWX_RATE_BIT_MSK(r) (1 << (IWX_RATE_##r##M_INDEX)) 4260 4261 /* fw API values for legacy bit rates, both OFDM and CCK */ 4262 #define IWX_RATE_6M_PLCP 13 4263 #define IWX_RATE_9M_PLCP 15 4264 #define IWX_RATE_12M_PLCP 5 4265 #define IWX_RATE_18M_PLCP 7 4266 #define IWX_RATE_24M_PLCP 9 4267 #define IWX_RATE_36M_PLCP 11 4268 #define IWX_RATE_48M_PLCP 1 4269 #define IWX_RATE_54M_PLCP 3 4270 #define IWX_RATE_1M_PLCP 10 4271 #define IWX_RATE_2M_PLCP 20 4272 #define IWX_RATE_5M_PLCP 55 4273 #define IWX_RATE_11M_PLCP 110 4274 #define IWX_RATE_INVM_PLCP 0xff 4275 4276 /* 4277 * rate_n_flags bit fields 4278 * 4279 * The 32-bit value has different layouts in the low 8 bites depending on the 4280 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 4281 * for CCK and OFDM). 4282 * 4283 * High-throughput (HT) rate format 4284 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 4285 * Very High-throughput (VHT) rate format 4286 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 4287 * Legacy OFDM rate format for bits 7:0 4288 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 4289 * Legacy CCK rate format for bits 7:0: 4290 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 4291 */ 4292 4293 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 4294 #define IWX_RATE_MCS_HT_POS 8 4295 #define IWX_RATE_MCS_HT_MSK (1 << IWX_RATE_MCS_HT_POS) 4296 4297 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 4298 #define IWX_RATE_MCS_CCK_POS 9 4299 #define IWX_RATE_MCS_CCK_MSK (1 << IWX_RATE_MCS_CCK_POS) 4300 4301 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 4302 #define IWX_RATE_MCS_VHT_POS 26 4303 #define IWX_RATE_MCS_VHT_MSK (1 << IWX_RATE_MCS_VHT_POS) 4304 4305 4306 /* 4307 * High-throughput (HT) rate format for bits 7:0 4308 * 4309 * 2-0: MCS rate base 4310 * 0) 6 Mbps 4311 * 1) 12 Mbps 4312 * 2) 18 Mbps 4313 * 3) 24 Mbps 4314 * 4) 36 Mbps 4315 * 5) 48 Mbps 4316 * 6) 54 Mbps 4317 * 7) 60 Mbps 4318 * 4-3: 0) Single stream (SISO) 4319 * 1) Dual stream (MIMO) 4320 * 2) Triple stream (MIMO) 4321 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4322 * (bits 7-6 are zero) 4323 * 4324 * Together the low 5 bits work out to the MCS index because we don't 4325 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4326 * streams and 16-23 have three streams. We could also support MCS 32 4327 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4328 */ 4329 #define IWX_RATE_HT_MCS_RATE_CODE_MSK 0x7 4330 #define IWX_RATE_HT_MCS_NSS_POS 3 4331 #define IWX_RATE_HT_MCS_NSS_MSK (3 << IWX_RATE_HT_MCS_NSS_POS) 4332 4333 /* Bit 10: (1) Use Green Field preamble */ 4334 #define IWX_RATE_HT_MCS_GF_POS 10 4335 #define IWX_RATE_HT_MCS_GF_MSK (1 << IWX_RATE_HT_MCS_GF_POS) 4336 4337 #define IWX_RATE_HT_MCS_INDEX_MSK 0x3f 4338 4339 /* 4340 * Very High-throughput (VHT) rate format for bits 7:0 4341 * 4342 * 3-0: VHT MCS (0-9) 4343 * 5-4: number of streams - 1: 4344 * 0) Single stream (SISO) 4345 * 1) Dual stream (MIMO) 4346 * 2) Triple stream (MIMO) 4347 */ 4348 4349 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4350 #define IWX_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4351 #define IWX_RATE_VHT_MCS_NSS_POS 4 4352 #define IWX_RATE_VHT_MCS_NSS_MSK (3 << IWX_RATE_VHT_MCS_NSS_POS) 4353 4354 /* 4355 * Legacy OFDM rate format for bits 7:0 4356 * 4357 * 3-0: 0xD) 6 Mbps 4358 * 0xF) 9 Mbps 4359 * 0x5) 12 Mbps 4360 * 0x7) 18 Mbps 4361 * 0x9) 24 Mbps 4362 * 0xB) 36 Mbps 4363 * 0x1) 48 Mbps 4364 * 0x3) 54 Mbps 4365 * (bits 7-4 are 0) 4366 * 4367 * Legacy CCK rate format for bits 7:0: 4368 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4369 * 4370 * 6-0: 10) 1 Mbps 4371 * 20) 2 Mbps 4372 * 55) 5.5 Mbps 4373 * 110) 11 Mbps 4374 * (bit 7 is 0) 4375 */ 4376 #define IWX_RATE_LEGACY_RATE_MSK 0xff 4377 4378 4379 /* 4380 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4381 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4382 */ 4383 #define IWX_RATE_MCS_CHAN_WIDTH_POS 11 4384 #define IWX_RATE_MCS_CHAN_WIDTH_MSK (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4385 #define IWX_RATE_MCS_CHAN_WIDTH_20 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4386 #define IWX_RATE_MCS_CHAN_WIDTH_40 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4387 #define IWX_RATE_MCS_CHAN_WIDTH_80 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4388 #define IWX_RATE_MCS_CHAN_WIDTH_160 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4389 4390 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4391 #define IWX_RATE_MCS_SGI_POS 13 4392 #define IWX_RATE_MCS_SGI_MSK (1 << IWX_RATE_MCS_SGI_POS) 4393 4394 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4395 #define IWX_RATE_MCS_ANT_POS 14 4396 #define IWX_RATE_MCS_ANT_A_MSK (1 << IWX_RATE_MCS_ANT_POS) 4397 #define IWX_RATE_MCS_ANT_B_MSK (2 << IWX_RATE_MCS_ANT_POS) 4398 #define IWX_RATE_MCS_ANT_C_MSK (4 << IWX_RATE_MCS_ANT_POS) 4399 #define IWX_RATE_MCS_ANT_AB_MSK (IWX_RATE_MCS_ANT_A_MSK | \ 4400 IWX_RATE_MCS_ANT_B_MSK) 4401 #define IWX_RATE_MCS_ANT_ABC_MSK (IWX_RATE_MCS_ANT_AB_MSK | \ 4402 IWX_RATE_MCS_ANT_C_MSK) 4403 #define IWX_RATE_MCS_ANT_MSK IWX_RATE_MCS_ANT_ABC_MSK 4404 #define IWX_RATE_MCS_ANT_NUM 3 4405 4406 /* Bit 17-18: (0) SS, (1) SS*2 */ 4407 #define IWX_RATE_MCS_STBC_POS 17 4408 #define IWX_RATE_MCS_STBC_MSK (1 << IWX_RATE_MCS_STBC_POS) 4409 4410 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4411 #define IWX_RATE_MCS_BF_POS 19 4412 #define IWX_RATE_MCS_BF_MSK (1 << IWX_RATE_MCS_BF_POS) 4413 4414 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4415 #define IWX_RATE_MCS_ZLF_POS 20 4416 #define IWX_RATE_MCS_ZLF_MSK (1 << IWX_RATE_MCS_ZLF_POS) 4417 4418 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4419 #define IWX_RATE_MCS_DUP_POS 24 4420 #define IWX_RATE_MCS_DUP_MSK (3 << IWX_RATE_MCS_DUP_POS) 4421 4422 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4423 #define IWX_RATE_MCS_LDPC_POS 27 4424 #define IWX_RATE_MCS_LDPC_MSK (1 << IWX_RATE_MCS_LDPC_POS) 4425 4426 4427 /* Link Quality definitions */ 4428 4429 /* # entries in rate scale table to support Tx retries */ 4430 #define IWX_LQ_MAX_RETRY_NUM 16 4431 4432 /* Link quality command flags bit fields */ 4433 4434 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4435 #define IWX_LQ_FLAG_USE_RTS_POS 0 4436 #define IWX_LQ_FLAG_USE_RTS_MSK (1 << IWX_LQ_FLAG_USE_RTS_POS) 4437 4438 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4439 #define IWX_LQ_FLAG_COLOR_POS 1 4440 #define IWX_LQ_FLAG_COLOR_MSK (7 << IWX_LQ_FLAG_COLOR_POS) 4441 4442 /* Bit 4-5: Tx RTS BW Signalling 4443 * (0) No RTS BW signalling 4444 * (1) Static BW signalling 4445 * (2) Dynamic BW signalling 4446 */ 4447 #define IWX_LQ_FLAG_RTS_BW_SIG_POS 4 4448 #define IWX_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 4449 #define IWX_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 4450 #define IWX_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 4451 4452 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4453 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4454 */ 4455 #define IWX_LQ_FLAG_DYNAMIC_BW_POS 6 4456 #define IWX_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWX_LQ_FLAG_DYNAMIC_BW_POS) 4457 4458 /** 4459 * Options for TLC config flags 4460 * @IWX_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for 4461 * bandwidths <= 80MHz 4462 * @IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC 4463 * @IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz 4464 * bandwidth 4465 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation 4466 * for BPSK (MCS 0) with 1 spatial 4467 * stream 4468 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation 4469 * for BPSK (MCS 0) with 2 spatial 4470 * streams 4471 */ 4472 #define IWX_TLC_MNG_CFG_FLAGS_STBC_MSK (1 << 0) 4473 #define IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK (1 << 1) 4474 #define IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK (1 << 2) 4475 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK (1 << 3) 4476 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK (1 << 4) 4477 4478 /** 4479 * enum iwx_tlc_mng_cfg_cw - channel width options 4480 * @IWX_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel 4481 * @IWX_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel 4482 * @IWX_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel 4483 * @IWX_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel 4484 * @IWX_TLC_MNG_CH_WIDTH_LAST: maximum value 4485 */ 4486 enum iwx_tlc_mng_cfg_cw { 4487 IWX_TLC_MNG_CH_WIDTH_20MHZ, 4488 IWX_TLC_MNG_CH_WIDTH_40MHZ, 4489 IWX_TLC_MNG_CH_WIDTH_80MHZ, 4490 IWX_TLC_MNG_CH_WIDTH_160MHZ, 4491 IWX_TLC_MNG_CH_WIDTH_LAST = IWX_TLC_MNG_CH_WIDTH_160MHZ, 4492 }; 4493 4494 /** 4495 * @IWX_TLC_MNG_CHAIN_A_MSK: chain A 4496 * @IWX_TLC_MNG_CHAIN_B_MSK: chain B 4497 */ 4498 #define IWX_TLC_MNG_CHAIN_A_MSK (1 << 0) 4499 #define IWX_TLC_MNG_CHAIN_B_MSK (1 << 1) 4500 4501 /** 4502 * enum iwx_tlc_mng_cfg_mode - supported modes 4503 * @IWX_TLC_MNG_MODE_CCK: enable CCK 4504 * @IWX_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT) 4505 * @IWX_TLC_MNG_MODE_NON_HT: enable non HT 4506 * @IWX_TLC_MNG_MODE_HT: enable HT 4507 * @IWX_TLC_MNG_MODE_VHT: enable VHT 4508 * @IWX_TLC_MNG_MODE_HE: enable HE 4509 * @IWX_TLC_MNG_MODE_INVALID: invalid value 4510 * @IWX_TLC_MNG_MODE_NUM: a count of possible modes 4511 */ 4512 enum iwx_tlc_mng_cfg_mode { 4513 IWX_TLC_MNG_MODE_CCK = 0, 4514 IWX_TLC_MNG_MODE_OFDM_NON_HT = IWX_TLC_MNG_MODE_CCK, 4515 IWX_TLC_MNG_MODE_NON_HT = IWX_TLC_MNG_MODE_CCK, 4516 IWX_TLC_MNG_MODE_HT, 4517 IWX_TLC_MNG_MODE_VHT, 4518 IWX_TLC_MNG_MODE_HE, 4519 IWX_TLC_MNG_MODE_INVALID, 4520 IWX_TLC_MNG_MODE_NUM = IWX_TLC_MNG_MODE_INVALID, 4521 }; 4522 4523 /** 4524 * @IWX_TLC_MNG_HT_RATE_MCS0: index of MCS0 4525 * @IWX_TLC_MNG_HT_RATE_MCS1: index of MCS1 4526 * @IWX_TLC_MNG_HT_RATE_MCS2: index of MCS2 4527 * @IWX_TLC_MNG_HT_RATE_MCS3: index of MCS3 4528 * @IWX_TLC_MNG_HT_RATE_MCS4: index of MCS4 4529 * @IWX_TLC_MNG_HT_RATE_MCS5: index of MCS5 4530 * @IWX_TLC_MNG_HT_RATE_MCS6: index of MCS6 4531 * @IWX_TLC_MNG_HT_RATE_MCS7: index of MCS7 4532 * @IWX_TLC_MNG_HT_RATE_MCS8: index of MCS8 4533 * @IWX_TLC_MNG_HT_RATE_MCS9: index of MCS9 4534 * @IWX_TLC_MNG_HT_RATE_MCS10: index of MCS10 4535 * @IWX_TLC_MNG_HT_RATE_MCS11: index of MCS11 4536 * @IWX_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT 4537 */ 4538 enum iwx_tlc_mng_ht_rates { 4539 IWX_TLC_MNG_HT_RATE_MCS0 = 0, 4540 IWX_TLC_MNG_HT_RATE_MCS1, 4541 IWX_TLC_MNG_HT_RATE_MCS2, 4542 IWX_TLC_MNG_HT_RATE_MCS3, 4543 IWX_TLC_MNG_HT_RATE_MCS4, 4544 IWX_TLC_MNG_HT_RATE_MCS5, 4545 IWX_TLC_MNG_HT_RATE_MCS6, 4546 IWX_TLC_MNG_HT_RATE_MCS7, 4547 IWX_TLC_MNG_HT_RATE_MCS8, 4548 IWX_TLC_MNG_HT_RATE_MCS9, 4549 IWX_TLC_MNG_HT_RATE_MCS10, 4550 IWX_TLC_MNG_HT_RATE_MCS11, 4551 IWX_TLC_MNG_HT_RATE_MAX = IWX_TLC_MNG_HT_RATE_MCS11, 4552 }; 4553 4554 #define IWX_TLC_NSS_1 0 4555 #define IWX_TLC_NSS_2 1 4556 #define IWX_TLC_NSS_MAX 2 4557 4558 #define IWX_TLC_HT_BW_NONE_160 0 4559 #define IWX_TLC_HT_BW_160 1 4560 4561 /** 4562 * struct iwx_tlc_config_cmd - TLC configuration 4563 * @sta_id: station id 4564 * @reserved1: reserved 4565 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw 4566 * @mode: &enum iwx_tlc_mng_cfg_mode 4567 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK 4568 * @amsdu: 1 = TX amsdu is supported, 0 = not supported 4569 * @flags: bitmask of IWX_TLC_MNG_CFG_* 4570 * @non_ht_rates: bitmap of supported legacy rates 4571 * @ht_rates: bitmap of &enum iwx_tlc_mng_ht_rates, per <nss, channel-width> 4572 * pair (0 - 80mhz width and below, 1 - 160mhz). 4573 * @max_mpdu_len: max MPDU length, in bytes 4574 * @sgi_ch_width_supp: bitmap of SGI support per channel width 4575 * use (1 << @enum iwx_tlc_mng_cfg_cw) 4576 * @reserved2: reserved 4577 */ 4578 struct iwx_tlc_config_cmd { 4579 uint8_t sta_id; 4580 uint8_t reserved1[3]; 4581 uint8_t max_ch_width; 4582 uint8_t mode; 4583 uint8_t chains; 4584 uint8_t amsdu; 4585 uint16_t flags; 4586 uint16_t non_ht_rates; 4587 uint16_t ht_rates[IWX_TLC_NSS_MAX][2]; 4588 uint16_t max_mpdu_len; 4589 uint8_t sgi_ch_width_supp; 4590 uint8_t reserved2[1]; 4591 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_2 */ 4592 4593 /** 4594 * @IWX_TLC_NOTIF_FLAG_RATE: last initial rate update 4595 * @IWX_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update 4596 */ 4597 #define IWX_TLC_NOTIF_FLAG_RATE (1 << 0) 4598 #define IWX_TLC_NOTIF_FLAG_AMSDU (1 << 1) 4599 4600 /** 4601 * struct iwx_tlc_update_notif - TLC notification from FW 4602 * @sta_id: station id 4603 * @reserved: reserved 4604 * @flags: bitmap of notifications reported 4605 * @rate: current initial rate 4606 * @amsdu_size: Max AMSDU size, in bytes 4607 * @amsdu_enabled: bitmap for per-TID AMSDU enablement 4608 */ 4609 struct iwx_tlc_update_notif { 4610 uint8_t sta_id; 4611 uint8_t reserved[3]; 4612 uint32_t flags; 4613 uint32_t rate; 4614 uint32_t amsdu_size; 4615 uint32_t amsdu_enabled; 4616 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */ 4617 4618 /* Antenna flags. */ 4619 #define IWX_ANT_A (1 << 0) 4620 #define IWX_ANT_B (1 << 1) 4621 #define IWX_ANT_C (1 << 2) 4622 /* Shortcuts. */ 4623 #define IWX_ANT_AB (IWX_ANT_A | IWX_ANT_B) 4624 #define IWX_ANT_BC (IWX_ANT_B | IWX_ANT_C) 4625 #define IWX_ANT_ABC (IWX_ANT_A | IWX_ANT_B | IWX_ANT_C) 4626 4627 /** 4628 * bitmasks for tx_flags in TX command 4629 * @IWX_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4630 * @IWX_TX_CMD_FLG_ACK: expect ACK from receiving station 4631 * @IWX_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4632 * Otherwise, use rate_n_flags from the TX command 4633 * @IWX_TX_CMD_FLG_BA: this frame is a block ack 4634 * @IWX_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4635 * Must set IWX_TX_CMD_FLG_ACK with this flag. 4636 * @IWX_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4637 * @IWX_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4638 * @IWX_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4639 * @IWX_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4640 * @IWX_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4641 * @IWX_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4642 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4643 * @IWX_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4644 * @IWX_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4645 * @IWX_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4646 * Should be set for beacons and probe responses 4647 * @IWX_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4648 * @IWX_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4649 * @IWX_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4650 * @IWX_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4651 * Should be set for 26/30 length MAC headers 4652 * @IWX_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4653 * @IWX_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4654 * @IWX_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4655 * @IWX_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4656 * @IWX_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4657 * @IWX_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4658 * @IWX_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4659 * @IWX_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4660 */ 4661 #define IWX_TX_CMD_FLG_PROT_REQUIRE (1 << 0) 4662 #define IWX_TX_CMD_FLG_ACK (1 << 3) 4663 #define IWX_TX_CMD_FLG_STA_RATE (1 << 4) 4664 #define IWX_TX_CMD_FLG_BA (1 << 5) 4665 #define IWX_TX_CMD_FLG_BAR (1 << 6) 4666 #define IWX_TX_CMD_FLG_TXOP_PROT (1 << 7) 4667 #define IWX_TX_CMD_FLG_VHT_NDPA (1 << 8) 4668 #define IWX_TX_CMD_FLG_HT_NDPA (1 << 9) 4669 #define IWX_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10) 4670 #define IWX_TX_CMD_FLG_BT_DIS (1 << 12) 4671 #define IWX_TX_CMD_FLG_SEQ_CTL (1 << 13) 4672 #define IWX_TX_CMD_FLG_MORE_FRAG (1 << 14) 4673 #define IWX_TX_CMD_FLG_NEXT_FRAME (1 << 15) 4674 #define IWX_TX_CMD_FLG_TSF (1 << 16) 4675 #define IWX_TX_CMD_FLG_CALIB (1 << 17) 4676 #define IWX_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18) 4677 #define IWX_TX_CMD_FLG_AGG_START (1 << 19) 4678 #define IWX_TX_CMD_FLG_MH_PAD (1 << 20) 4679 #define IWX_TX_CMD_FLG_RESP_TO_DRV (1 << 21) 4680 #define IWX_TX_CMD_FLG_CCMP_AGG (1 << 22) 4681 #define IWX_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23) 4682 #define IWX_TX_CMD_FLG_DUR (1 << 25) 4683 #define IWX_TX_CMD_FLG_FW_DROP (1 << 26) 4684 #define IWX_TX_CMD_FLG_EXEC_PAPD (1 << 27) 4685 #define IWX_TX_CMD_FLG_PAPD_TYPE (1 << 28) 4686 #define IWX_TX_CMD_FLG_HCCA_CHUNK (1U << 31) 4687 /* IWX_TX_FLAGS_BITS_API_S_VER_1 */ 4688 4689 /* 4690 * TX command security control 4691 */ 4692 #define IWX_TX_CMD_SEC_WEP 0x01 4693 #define IWX_TX_CMD_SEC_CCM 0x02 4694 #define IWX_TX_CMD_SEC_TKIP 0x03 4695 #define IWX_TX_CMD_SEC_EXT 0x04 4696 #define IWX_TX_CMD_SEC_MSK 0x07 4697 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4698 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4699 #define IWX_TX_CMD_SEC_KEY128 0x08 4700 4701 /* TODO: how does these values are OK with only 16 bit variable??? */ 4702 /* 4703 * TX command next frame info 4704 * 4705 * bits 0:2 - security control (IWX_TX_CMD_SEC_*) 4706 * bit 3 - immediate ACK required 4707 * bit 4 - rate is taken from STA table 4708 * bit 5 - frame belongs to BA stream 4709 * bit 6 - immediate BA response expected 4710 * bit 7 - unused 4711 * bits 8:15 - Station ID 4712 * bits 16:31 - rate 4713 */ 4714 #define IWX_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4715 #define IWX_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4716 #define IWX_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4717 #define IWX_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4718 #define IWX_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4719 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4720 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4721 #define IWX_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4722 #define IWX_TX_CMD_NEXT_FRAME_RATE_POS (16) 4723 4724 /* 4725 * TX command Frame life time in us - to be written in pm_frame_timeout 4726 */ 4727 #define IWX_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4728 #define IWX_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4729 #define IWX_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4730 #define IWX_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4731 4732 /* 4733 * TID for non QoS frames - to be written in tid_tspec 4734 */ 4735 #define IWX_MAX_TID_COUNT 8 4736 #define IWX_TID_NON_QOS 0 4737 4738 /* 4739 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4740 */ 4741 #define IWX_DEFAULT_TX_RETRY 15 4742 #define IWX_MGMT_DFAULT_RETRY_LIMIT 3 4743 #define IWX_RTS_DFAULT_RETRY_LIMIT 3 4744 #define IWX_BAR_DFAULT_RETRY_LIMIT 60 4745 #define IWX_LOW_RETRY_LIMIT 7 4746 4747 /* 4748 * The FH will write back to the first TB only, so we need to copy some data 4749 * into the buffer regardless of whether it should be mapped or not. 4750 * This indicates how big the first TB must be to include the scratch buffer 4751 * and the assigned PN. 4752 * Since PN location is 8 bytes at offset 12, it's 20 now. 4753 * If we make it bigger then allocations will be bigger and copy slower, so 4754 * that's probably not useful. 4755 */ 4756 #define IWX_FIRST_TB_SIZE 20 4757 #define IWX_FIRST_TB_SIZE_ALIGN ((IWX_FIRST_TB_SIZE + (64 - 1)) & ~(64 - 1)) 4758 4759 /** 4760 * %iwl_tx_cmd offload_assist values 4761 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words) 4762 * from mac header end. For normal case it is 4 words for SNAP. 4763 * note: tx_cmd, mac header and pad are not counted in the offset. 4764 * This is used to help the offload in case there is tunneling such as 4765 * IPv6 in IPv4, in such case the ip header offset should point to the 4766 * inner ip header and IPv4 checksum of the external header should be 4767 * calculated by driver. 4768 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum 4769 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum 4770 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV 4771 * field. Doesn't include the pad. 4772 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for 4773 * alignment 4774 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU 4775 */ 4776 #define IWX_TX_CMD_OFFLD_IP_HDR(x) ((x) << 0) 4777 #define IWX_TX_CMD_OFFLD_L4_EN (1 << 6) 4778 #define IWX_TX_CMD_OFFLD_L3_EN (1 << 7) 4779 #define IWX_TX_CMD_OFFLD_MH_SIZE(x) ((x) << 8) 4780 #define IWX_TX_CMD_OFFLD_PAD (1 << 13) 4781 #define IWX_TX_CMD_OFFLD_AMSDU (1 << 14) 4782 #define IWX_TX_CMD_OFFLD_MH_MASK 0x1f 4783 #define IWX_TX_CMD_OFFLD_IP_HDR_MASK 0x3f 4784 4785 struct iwx_dram_sec_info { 4786 uint32_t pn_low; 4787 uint16_t pn_high; 4788 uint16_t aux_info; 4789 } __packed; /* DRAM_SEC_INFO_API_S_VER_1 */ 4790 4791 /** 4792 * bitmasks for tx_flags in TX command for 22000 4793 * @IWX_TX_FLAGS_CMD_RATE: use rate from the TX command 4794 * @IWX_TX_FLAGS_ENCRYPT_DIS: frame should not be encrypted, even if it belongs 4795 * to a secured STA 4796 * @IWX_TX_FLAGS_HIGH_PRI: high priority frame (like EAPOL) - can affect rate 4797 * selection, retry limits and BT kill 4798 */ 4799 #define IWX_TX_FLAGS_CMD_RATE (1 << 0) 4800 #define IWX_TX_FLAGS_ENCRYPT_DIS (1 << 1) 4801 #define IWX_TX_FLAGS_HIGH_PRI (1 << 2) 4802 /* TX_FLAGS_BITS_API_S_VER_3 */ 4803 4804 /** 4805 * struct iwx_tx_cmd_gen2 - TX command struct to FW for 22000 devices 4806 * ( TX_CMD = 0x1c ) 4807 * @len: in bytes of the payload, see below for details 4808 * @offload_assist: TX offload configuration 4809 * @flags: combination of TX_CMD_FLG_* 4810 * @dram_info: FW internal DRAM storage 4811 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4812 * cleared. Combination of RATE_MCS_* 4813 * @hdr: 802.11 header 4814 */ 4815 struct iwx_tx_cmd_gen2 { 4816 uint16_t len; 4817 uint16_t offload_assist; 4818 uint32_t flags; 4819 struct iwx_dram_sec_info dram_info; 4820 uint32_t rate_n_flags; 4821 struct ieee80211_frame hdr[0]; 4822 } __packed; /* TX_CMD_API_S_VER_7 */ 4823 4824 /* 4825 * TX response related data 4826 */ 4827 4828 /* 4829 * status that is returned by the fw after attempts to Tx 4830 * @IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4831 * STA table 4832 * Valid only if frame_count =1 4833 */ 4834 #define IWX_TX_STATUS_MSK 0x000000ff 4835 #define IWX_TX_STATUS_SUCCESS 0x01 4836 #define IWX_TX_STATUS_DIRECT_DONE 0x02 4837 /* postpone TX */ 4838 #define IWX_TX_STATUS_POSTPONE_DELAY 0x40 4839 #define IWX_TX_STATUS_POSTPONE_FEW_BYTES 0x41 4840 #define IWX_TX_STATUS_POSTPONE_BT_PRIO 0x42 4841 #define IWX_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 4842 #define IWX_TX_STATUS_POSTPONE_CALC_TTAK 0x44 4843 /* abort TX */ 4844 #define IWX_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 4845 #define IWX_TX_STATUS_FAIL_SHORT_LIMIT 0x82 4846 #define IWX_TX_STATUS_FAIL_LONG_LIMIT 0x83 4847 #define IWX_TX_STATUS_FAIL_UNDERRUN 0x84 4848 #define IWX_TX_STATUS_FAIL_DRAIN_FLOW 0x85 4849 #define IWX_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 4850 #define IWX_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 4851 #define IWX_TX_STATUS_FAIL_DEST_PS 0x88 4852 #define IWX_TX_STATUS_FAIL_HOST_ABORTED 0x89 4853 #define IWX_TX_STATUS_FAIL_BT_RETRY 0x8a 4854 #define IWX_TX_STATUS_FAIL_STA_INVALID 0x8b 4855 #define IWX_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 4856 #define IWX_TX_STATUS_FAIL_TID_DISABLE 0x8d 4857 #define IWX_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 4858 #define IWX_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f 4859 #define IWX_TX_STATUS_FAIL_FW_DROP 0x90 4860 #define IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91 4861 #define IWX_TX_STATUS_INTERNAL_ABORT 0x92 4862 #define IWX_TX_MODE_MSK 0x00000f00 4863 #define IWX_TX_MODE_NO_BURST 0x00000000 4864 #define IWX_TX_MODE_IN_BURST_SEQ 0x00000100 4865 #define IWX_TX_MODE_FIRST_IN_BURST 0x00000200 4866 #define IWX_TX_QUEUE_NUM_MSK 0x0001f000 4867 #define IWX_TX_NARROW_BW_MSK 0x00060000 4868 #define IWX_TX_NARROW_BW_1DIV2 0x00020000 4869 #define IWX_TX_NARROW_BW_1DIV4 0x00040000 4870 #define IWX_TX_NARROW_BW_1DIV8 0x00060000 4871 4872 /* 4873 * TX aggregation status 4874 * @IWX_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4875 * occur if tx failed for this frame when it was a member of a previous 4876 * aggregation block). If rate scaling is used, retry count indicates the 4877 * rate table entry used for all frames in the new agg. 4878 * @IWX_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4879 * this frame 4880 */ 4881 #define IWX_AGG_TX_STATE_STATUS_MSK 0x0fff 4882 #define IWX_AGG_TX_STATE_TRANSMITTED 0x0000 4883 #define IWX_AGG_TX_STATE_UNDERRUN 0x0001 4884 #define IWX_AGG_TX_STATE_BT_PRIO 0x0002 4885 #define IWX_AGG_TX_STATE_FEW_BYTES 0x0004 4886 #define IWX_AGG_TX_STATE_ABORT 0x0008 4887 #define IWX_AGG_TX_STATE_LAST_SENT_TTL 0x0010 4888 #define IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 4889 #define IWX_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 4890 #define IWX_AGG_TX_STATE_SCD_QUERY 0x0080 4891 #define IWX_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 4892 #define IWX_AGG_TX_STATE_RESPONSE 0x01ff 4893 #define IWX_AGG_TX_STATE_DUMP_TX 0x0200 4894 #define IWX_AGG_TX_STATE_DELAY_TX 0x0400 4895 #define IWX_AGG_TX_STATE_TRY_CNT_POS 12 4896 #define IWX_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWX_AGG_TX_STATE_TRY_CNT_POS) 4897 4898 #define IWX_AGG_TX_STATE_LAST_SENT_MSK (IWX_AGG_TX_STATE_LAST_SENT_TTL| \ 4899 IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4900 IWX_AGG_TX_STATE_LAST_SENT_BT_KILL) 4901 4902 /* 4903 * The mask below describes a status where we are absolutely sure that the MPDU 4904 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4905 * written the bytes to the TXE, but we know nothing about what the DSP did. 4906 */ 4907 #define IWX_AGG_TX_STAT_FRAME_NOT_SENT (IWX_AGG_TX_STATE_FEW_BYTES | \ 4908 IWX_AGG_TX_STATE_ABORT | \ 4909 IWX_AGG_TX_STATE_SCD_QUERY) 4910 4911 /* 4912 * IWX_REPLY_TX = 0x1c (response) 4913 * 4914 * This response may be in one of two slightly different formats, indicated 4915 * by the frame_count field: 4916 * 4917 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4918 * frame. Multiple attempts, at various bit rates, may have been made for 4919 * this frame. 4920 * 4921 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4922 * frames that used block-acknowledge. All frames were transmitted at 4923 * same rate. Rate scaling may have been used if first frame in this new 4924 * agg block failed in previous agg block(s). 4925 * 4926 * Note that, for aggregation, ACK (block-ack) status is not delivered 4927 * here; block-ack has not been received by the time the device records 4928 * this status. 4929 * This status relates to reasons the tx might have been blocked or aborted 4930 * within the device, rather than whether it was received successfully by 4931 * the destination station. 4932 */ 4933 4934 /** 4935 * struct iwx_agg_tx_status - per packet TX aggregation status 4936 * @status: enum iwx_tx_agg_status 4937 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4938 */ 4939 struct iwx_agg_tx_status { 4940 uint16_t status; 4941 uint16_t sequence; 4942 } __packed; 4943 4944 /* 4945 * definitions for initial rate index field 4946 * bits [3:0] initial rate index 4947 * bits [6:4] rate table color, used for the initial rate 4948 * bit-7 invalid rate indication 4949 */ 4950 #define IWX_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4951 #define IWX_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4952 #define IWX_TX_RES_INV_RATE_INDEX_MSK 0x80 4953 4954 #define IWX_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4955 #define IWX_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4956 4957 /** 4958 * struct iwx_tx_resp_v3 - notifies that fw is TXing a packet 4959 * ( IWX_REPLY_TX = 0x1c ) 4960 * @frame_count: 1 no aggregation, >1 aggregation 4961 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4962 * @failure_rts: num of failures due to unsuccessful RTS 4963 * @failure_frame: num failures due to no ACK (unused for agg) 4964 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4965 * Tx of all the batch. IWX_RATE_MCS_* 4966 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4967 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4968 * in usec. 4969 * @pa_status: tx power info 4970 * @pa_integ_res_a: tx power info 4971 * @pa_integ_res_b: tx power info 4972 * @pa_integ_res_c: tx power info 4973 * @measurement_req_id: tx power info 4974 * @tfd_info: TFD information set by the FH 4975 * @seq_ctl: sequence control from the Tx cmd 4976 * @byte_cnt: byte count from the Tx cmd 4977 * @tlc_info: TLC rate info 4978 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4979 * @frame_ctrl: frame control 4980 * @status: for non-agg: frame status IWX_TX_STATUS_* 4981 * for agg: status of 1st frame, IWX_AGG_TX_STATE_*; other frame status fields 4982 * follow this one, up to frame_count. 4983 * 4984 * After the array of statuses comes the SSN of the SCD. Look at 4985 * %iwx_get_scd_ssn for more details. 4986 */ 4987 struct iwx_tx_resp_v3 { 4988 uint8_t frame_count; 4989 uint8_t bt_kill_count; 4990 uint8_t failure_rts; 4991 uint8_t failure_frame; 4992 uint32_t initial_rate; 4993 uint16_t wireless_media_time; 4994 4995 uint8_t pa_status; 4996 uint8_t pa_integ_res_a[3]; 4997 uint8_t pa_integ_res_b[3]; 4998 uint8_t pa_integ_res_c[3]; 4999 uint16_t measurement_req_id; 5000 uint16_t reserved; 5001 5002 uint32_t tfd_info; 5003 uint16_t seq_ctl; 5004 uint16_t byte_cnt; 5005 uint8_t tlc_info; 5006 uint8_t ra_tid; 5007 uint16_t frame_ctrl; 5008 5009 struct iwx_agg_tx_status status; 5010 } __packed; /* IWX_TX_RSP_API_S_VER_3 */ 5011 5012 /** 5013 * struct iwx_tx_resp - notifies that fw is TXing a packet 5014 * ( REPLY_TX = 0x1c ) 5015 * @frame_count: 1 no aggregation, >1 aggregation 5016 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 5017 * @failure_rts: num of failures due to unsuccessful RTS 5018 * @failure_frame: num failures due to no ACK (unused for agg) 5019 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 5020 * Tx of all the batch. RATE_MCS_* 5021 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 5022 * for agg: RTS + CTS + aggregation tx time + block-ack time. 5023 * in usec. 5024 * @pa_status: tx power info 5025 * @pa_integ_res_a: tx power info 5026 * @pa_integ_res_b: tx power info 5027 * @pa_integ_res_c: tx power info 5028 * @measurement_req_id: tx power info 5029 * @reduced_tpc: transmit power reduction used 5030 * @reserved: reserved 5031 * @tfd_info: TFD information set by the FH 5032 * @seq_ctl: sequence control from the Tx cmd 5033 * @byte_cnt: byte count from the Tx cmd 5034 * @tlc_info: TLC rate info 5035 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 5036 * @frame_ctrl: frame control 5037 * @tx_queue: TX queue for this response 5038 * @reserved2: reserved for padding/alignment 5039 * @status: for non-agg: frame status TX_STATUS_* 5040 * For version 6 TX response isn't received for aggregation at all. 5041 * 5042 * After the array of statuses comes the SSN of the SCD. Look at 5043 * %iwl_mvm_get_scd_ssn for more details. 5044 */ 5045 struct iwx_tx_resp { 5046 uint8_t frame_count; 5047 uint8_t bt_kill_count; 5048 uint8_t failure_rts; 5049 uint8_t failure_frame; 5050 uint32_t initial_rate; 5051 uint16_t wireless_media_time; 5052 5053 uint8_t pa_status; 5054 uint8_t pa_integ_res_a[3]; 5055 uint8_t pa_integ_res_b[3]; 5056 uint8_t pa_integ_res_c[3]; 5057 uint16_t measurement_req_id; 5058 uint8_t reduced_tpc; 5059 uint8_t reserved; 5060 5061 uint32_t tfd_info; 5062 uint16_t seq_ctl; 5063 uint16_t byte_cnt; 5064 uint8_t tlc_info; 5065 uint8_t ra_tid; 5066 uint16_t frame_ctrl; 5067 uint16_t tx_queue; 5068 uint16_t reserved2; 5069 struct iwx_agg_tx_status status; 5070 } __packed; /* TX_RSP_API_S_VER_6 */ 5071 5072 /** 5073 * struct iwx_ba_notif - notifies about reception of BA 5074 * ( IWX_BA_NOTIF = 0xc5 ) 5075 * @sta_addr_lo32: lower 32 bits of the MAC address 5076 * @sta_addr_hi16: upper 16 bits of the MAC address 5077 * @sta_id: Index of recipient (BA-sending) station in fw's station table 5078 * @tid: tid of the session 5079 * @seq_ctl: 5080 * @bitmap: the bitmap of the BA notification as seen in the air 5081 * @scd_flow: the tx queue this BA relates to 5082 * @scd_ssn: the index of the last contiguously sent packet 5083 * @txed: number of Txed frames in this batch 5084 * @txed_2_done: number of Acked frames in this batch 5085 */ 5086 struct iwx_ba_notif { 5087 uint32_t sta_addr_lo32; 5088 uint16_t sta_addr_hi16; 5089 uint16_t reserved; 5090 5091 uint8_t sta_id; 5092 uint8_t tid; 5093 uint16_t seq_ctl; 5094 uint64_t bitmap; 5095 uint16_t scd_flow; 5096 uint16_t scd_ssn; 5097 uint8_t txed; 5098 uint8_t txed_2_done; 5099 uint16_t reserved1; 5100 } __packed; 5101 5102 struct iwx_beacon_notif { 5103 struct iwx_tx_resp_v3 beacon_notify_hdr; 5104 uint64_t tsf; 5105 uint32_t ibss_mgr_status; 5106 } __packed; 5107 5108 /** 5109 * dump (flush) control flags 5110 * @IWX_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 5111 * and the TFD queues are empty. 5112 */ 5113 #define IWX_DUMP_TX_FIFO_FLUSH (1 << 1) 5114 5115 /** 5116 * struct iwx_tx_path_flush_cmd -- queue/FIFO flush command 5117 * @queues_ctl: bitmap of queues to flush 5118 * @flush_ctl: control flags 5119 * @reserved: reserved 5120 */ 5121 struct iwx_tx_path_flush_cmd_v1 { 5122 uint32_t queues_ctl; 5123 uint16_t flush_ctl; 5124 uint16_t reserved; 5125 } __packed; /* IWX_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 5126 5127 /** 5128 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command 5129 * @sta_id: station ID to flush 5130 * @tid_mask: TID mask to flush 5131 * @reserved: reserved 5132 */ 5133 struct iwx_tx_path_flush_cmd { 5134 uint32_t sta_id; 5135 uint16_t tid_mask; 5136 uint16_t reserved; 5137 } __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */ 5138 5139 /** 5140 * iwx_get_scd_ssn - returns the SSN of the SCD 5141 * @tx_resp: the Tx response from the fw (agg or non-agg) 5142 * 5143 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 5144 * it can't know that everything will go well until the end of the AMPDU, it 5145 * can't know in advance the number of MPDUs that will be sent in the current 5146 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 5147 * Hence, it can't know in advance what the SSN of the SCD will be at the end 5148 * of the batch. This is why the SSN of the SCD is written at the end of the 5149 * whole struct at a variable offset. This function knows how to cope with the 5150 * variable offset and returns the SSN of the SCD. 5151 */ 5152 static inline uint32_t iwx_get_scd_ssn(struct iwx_tx_resp *tx_resp) 5153 { 5154 return le32_to_cpup((uint32_t *)&tx_resp->status + 5155 tx_resp->frame_count) & 0xfff; 5156 } 5157 5158 /** 5159 * struct iwx_scd_txq_cfg_cmd - New txq hw scheduler config command 5160 * @token: 5161 * @sta_id: station id 5162 * @tid: 5163 * @scd_queue: scheduler queue to confiug 5164 * @enable: 1 queue enable, 0 queue disable 5165 * @aggregate: 1 aggregated queue, 0 otherwise 5166 * @tx_fifo: %enum iwx_tx_fifo 5167 * @window: BA window size 5168 * @ssn: SSN for the BA agreement 5169 */ 5170 struct iwx_scd_txq_cfg_cmd { 5171 uint8_t token; 5172 uint8_t sta_id; 5173 uint8_t tid; 5174 uint8_t scd_queue; 5175 uint8_t enable; 5176 uint8_t aggregate; 5177 uint8_t tx_fifo; 5178 uint8_t window; 5179 uint16_t ssn; 5180 uint16_t reserved; 5181 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 5182 5183 /** 5184 * struct iwx_scd_txq_cfg_rsp 5185 * @token: taken from the command 5186 * @sta_id: station id from the command 5187 * @tid: tid from the command 5188 * @scd_queue: scd_queue from the command 5189 */ 5190 struct iwx_scd_txq_cfg_rsp { 5191 uint8_t token; 5192 uint8_t sta_id; 5193 uint8_t tid; 5194 uint8_t scd_queue; 5195 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 5196 5197 5198 /* Scan Commands, Responses, Notifications */ 5199 5200 /* Max number of IEs for direct SSID scans in a command */ 5201 #define IWX_PROBE_OPTION_MAX 20 5202 5203 /** 5204 * struct iwx_ssid_ie - directed scan network information element 5205 * 5206 * Up to 20 of these may appear in IWX_REPLY_SCAN_CMD, 5207 * selected by "type" bit field in struct iwx_scan_channel; 5208 * each channel may select different ssids from among the 20 entries. 5209 * SSID IEs get transmitted in reverse order of entry. 5210 */ 5211 struct iwx_ssid_ie { 5212 uint8_t id; 5213 uint8_t len; 5214 uint8_t ssid[IEEE80211_NWID_LEN]; 5215 } __packed; /* IWX_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5216 5217 /* scan offload */ 5218 #define IWX_SCAN_MAX_BLACKLIST_LEN 64 5219 #define IWX_SCAN_SHORT_BLACKLIST_LEN 16 5220 #define IWX_SCAN_MAX_PROFILES 11 5221 #define IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 5222 5223 /* Default watchdog (in MS) for scheduled scan iteration */ 5224 #define IWX_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 5225 5226 #define IWX_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 5227 #define IWX_CAN_ABORT_STATUS 1 5228 5229 #define IWX_FULL_SCAN_MULTIPLIER 5 5230 #define IWX_FAST_SCHED_SCAN_ITERATIONS 3 5231 #define IWX_MAX_SCHED_SCAN_PLANS 2 5232 5233 /** 5234 * iwx_scan_schedule_lmac - schedule of scan offload 5235 * @delay: delay between iterations, in seconds. 5236 * @iterations: num of scan iterations 5237 * @full_scan_mul: number of partial scans before each full scan 5238 */ 5239 struct iwx_scan_schedule_lmac { 5240 uint16_t delay; 5241 uint8_t iterations; 5242 uint8_t full_scan_mul; 5243 } __packed; /* SCAN_SCHEDULE_API_S */ 5244 5245 /** 5246 * iwx_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 5247 * @tx_flags: combination of TX_CMD_FLG_* 5248 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5249 * cleared. Combination of RATE_MCS_* 5250 * @sta_id: index of destination station in FW station table 5251 * @reserved: for alignment and future use 5252 */ 5253 struct iwx_scan_req_tx_cmd { 5254 uint32_t tx_flags; 5255 uint32_t rate_n_flags; 5256 uint8_t sta_id; 5257 uint8_t reserved[3]; 5258 } __packed; 5259 5260 #define IWX_UNIFIED_SCAN_CHANNEL_FULL (1 << 27) 5261 #define IWX_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28) 5262 5263 /** 5264 * iwx_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 5265 * @flags: bits 1-20: directed scan to i'th ssid 5266 * other bits &enum iwx_scan_channel_flags_lmac 5267 * @channel_number: channel number 1-13 etc 5268 * @iter_count: scan iteration on this channel 5269 * @iter_interval: interval in seconds between iterations on one channel 5270 */ 5271 struct iwx_scan_channel_cfg_lmac { 5272 uint32_t flags; 5273 uint16_t channel_num; 5274 uint16_t iter_count; 5275 uint32_t iter_interval; 5276 } __packed; 5277 5278 /* 5279 * iwx_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 5280 * @offset: offset in the data block 5281 * @len: length of the segment 5282 */ 5283 struct iwx_scan_probe_segment { 5284 uint16_t offset; 5285 uint16_t len; 5286 } __packed; 5287 5288 /* iwx_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 5289 * @mac_header: first (and common) part of the probe 5290 * @band_data: band specific data 5291 * @common_data: last (and common) part of the probe 5292 * @buf: raw data block 5293 */ 5294 struct iwx_scan_probe_req_v1 { 5295 struct iwx_scan_probe_segment mac_header; 5296 struct iwx_scan_probe_segment band_data[2]; 5297 struct iwx_scan_probe_segment common_data; 5298 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5299 } __packed; 5300 5301 /* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2 5302 * @mac_header: first (and common) part of the probe 5303 * @band_data: band specific data 5304 * @common_data: last (and common) part of the probe 5305 * @buf: raw data block 5306 */ 5307 struct iwx_scan_probe_req { 5308 struct iwx_scan_probe_segment mac_header; 5309 struct iwx_scan_probe_segment band_data[3]; 5310 struct iwx_scan_probe_segment common_data; 5311 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5312 } __packed; 5313 5314 5315 #define IWX_SCAN_CHANNEL_FLAG_EBS (1 << 0) 5316 #define IWX_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1) 5317 #define IWX_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2) 5318 5319 /* iwx_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 5320 * @flags: enum iwx_scan_channel_flags 5321 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 5322 * involved. 5323 * 1 - EBS is disabled. 5324 * 2 - every second scan will be full scan(and so on). 5325 */ 5326 struct iwx_scan_channel_opt { 5327 uint16_t flags; 5328 uint16_t non_ebs_ratio; 5329 } __packed; 5330 5331 #define IWX_SCAN_PRIORITY_LOW 0 5332 #define IWX_SCAN_PRIORITY_MEDIUM 1 5333 #define IWX_SCAN_PRIORITY_HIGH 2 5334 5335 /** 5336 * iwx_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 5337 * @last_schedule_line: last schedule line executed (fast or regular) 5338 * @last_schedule_iteration: last scan iteration executed before scan abort 5339 * @status: enum iwx_scan_offload_complete_status 5340 * @ebs_status: EBS success status &enum iwx_scan_ebs_status 5341 * @time_after_last_iter; time in seconds elapsed after last iteration 5342 */ 5343 struct iwx_periodic_scan_complete { 5344 uint8_t last_schedule_line; 5345 uint8_t last_schedule_iteration; 5346 uint8_t status; 5347 uint8_t ebs_status; 5348 uint32_t time_after_last_iter; 5349 uint32_t reserved; 5350 } __packed; 5351 5352 /** 5353 * struct iwx_scan_results_notif - scan results for one channel - 5354 * SCAN_RESULT_NTF_API_S_VER_3 5355 * @channel: which channel the results are from 5356 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5357 * @probe_status: IWX_SCAN_PROBE_STATUS_*, indicates success of probe request 5358 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5359 * @duration: duration spent in channel, in usecs 5360 */ 5361 struct iwx_scan_results_notif { 5362 uint8_t channel; 5363 uint8_t band; 5364 uint8_t probe_status; 5365 uint8_t num_probe_not_sent; 5366 uint32_t duration; 5367 } __packed; 5368 5369 #define IWX_SCAN_CLIENT_SCHED_SCAN (1 << 0) 5370 #define IWX_SCAN_CLIENT_NETDETECT (1 << 1) 5371 #define IWX_SCAN_CLIENT_ASSET_TRACKING (1 << 2) 5372 5373 /** 5374 * iwx_scan_offload_blacklist - IWX_SCAN_OFFLOAD_BLACKLIST_S 5375 * @ssid: MAC address to filter out 5376 * @reported_rssi: AP rssi reported to the host 5377 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5378 */ 5379 struct iwx_scan_offload_blacklist { 5380 uint8_t ssid[ETHER_ADDR_LEN]; 5381 uint8_t reported_rssi; 5382 uint8_t client_bitmap; 5383 } __packed; 5384 5385 #define IWX_NETWORK_TYPE_BSS 1 5386 #define IWX_NETWORK_TYPE_IBSS 2 5387 #define IWX_NETWORK_TYPE_ANY 3 5388 5389 #define IWX_SCAN_OFFLOAD_SELECT_2_4 0x4 5390 #define IWX_SCAN_OFFLOAD_SELECT_5_2 0x8 5391 #define IWX_SCAN_OFFLOAD_SELECT_ANY 0xc 5392 5393 /** 5394 * iwx_scan_offload_profile - IWX_SCAN_OFFLOAD_PROFILE_S 5395 * @ssid_index: index to ssid list in fixed part 5396 * @unicast_cipher: encryption olgorithm to match - bitmap 5397 * @aut_alg: authentication olgorithm to match - bitmap 5398 * @network_type: enum iwx_scan_offload_network_type 5399 * @band_selection: enum iwx_scan_offload_band_selection 5400 * @client_bitmap: clients waiting for match - enum scan_framework_client 5401 */ 5402 struct iwx_scan_offload_profile { 5403 uint8_t ssid_index; 5404 uint8_t unicast_cipher; 5405 uint8_t auth_alg; 5406 uint8_t network_type; 5407 uint8_t band_selection; 5408 uint8_t client_bitmap; 5409 uint8_t reserved[2]; 5410 } __packed; 5411 5412 /** 5413 * iwx_scan_offload_profile_cfg - IWX_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5414 * @blaclist: AP list to filter off from scan results 5415 * @profiles: profiles to search for match 5416 * @blacklist_len: length of blacklist 5417 * @num_profiles: num of profiles in the list 5418 * @match_notify: clients waiting for match found notification 5419 * @pass_match: clients waiting for the results 5420 * @active_clients: active clients bitmap - enum scan_framework_client 5421 * @any_beacon_notify: clients waiting for match notification without match 5422 */ 5423 struct iwx_scan_offload_profile_cfg { 5424 struct iwx_scan_offload_profile profiles[IWX_SCAN_MAX_PROFILES]; 5425 uint8_t blacklist_len; 5426 uint8_t num_profiles; 5427 uint8_t match_notify; 5428 uint8_t pass_match; 5429 uint8_t active_clients; 5430 uint8_t any_beacon_notify; 5431 uint8_t reserved[2]; 5432 } __packed; 5433 5434 #define IWX_SCAN_OFFLOAD_COMPLETED 1 5435 #define IWX_SCAN_OFFLOAD_ABORTED 2 5436 5437 /* UMAC Scan API */ 5438 5439 #define IWX_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0) 5440 #define IWX_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1) 5441 #define IWX_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2) 5442 #define IWX_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3) 5443 #define IWX_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8) 5444 #define IWX_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9) 5445 #define IWX_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10) 5446 #define IWX_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11) 5447 #define IWX_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12) 5448 #define IWX_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13) 5449 #define IWX_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14) 5450 #define IWX_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15) 5451 #define IWX_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16) 5452 #define IWX_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17) 5453 #define IWX_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18) 5454 #define IWX_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19) 5455 #define IWX_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20) 5456 #define IWX_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21) 5457 5458 /* Bits 26-31 are for num of channels in channel_array */ 5459 #define IWX_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5460 5461 /* OFDM basic rates */ 5462 #define IWX_SCAN_CONFIG_RATE_6M (1 << 0) 5463 #define IWX_SCAN_CONFIG_RATE_9M (1 << 1) 5464 #define IWX_SCAN_CONFIG_RATE_12M (1 << 2) 5465 #define IWX_SCAN_CONFIG_RATE_18M (1 << 3) 5466 #define IWX_SCAN_CONFIG_RATE_24M (1 << 4) 5467 #define IWX_SCAN_CONFIG_RATE_36M (1 << 5) 5468 #define IWX_SCAN_CONFIG_RATE_48M (1 << 6) 5469 #define IWX_SCAN_CONFIG_RATE_54M (1 << 7) 5470 /* CCK basic rates */ 5471 #define IWX_SCAN_CONFIG_RATE_1M (1 << 8) 5472 #define IWX_SCAN_CONFIG_RATE_2M (1 << 9) 5473 #define IWX_SCAN_CONFIG_RATE_5M (1 << 10) 5474 #define IWX_SCAN_CONFIG_RATE_11M (1 << 11) 5475 5476 /* Bits 16-27 are for supported rates */ 5477 #define IWX_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5478 5479 #define IWX_CHANNEL_FLAG_EBS (1 << 0) 5480 #define IWX_CHANNEL_FLAG_ACCURATE_EBS (1 << 1) 5481 #define IWX_CHANNEL_FLAG_EBS_ADD (1 << 2) 5482 #define IWX_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3) 5483 5484 /** 5485 * struct iwx_scan_dwell 5486 * @active: default dwell time for active scan 5487 * @passive: default dwell time for passive scan 5488 * @fragmented: default dwell time for fragmented scan 5489 * @extended: default dwell time for channels 1, 6 and 11 5490 */ 5491 struct iwx_scan_dwell { 5492 uint8_t active; 5493 uint8_t passive; 5494 uint8_t fragmented; 5495 uint8_t extended; 5496 } __packed; 5497 5498 5499 #define IWX_SCAN_TWO_LMACS 2 5500 #define IWX_SCAN_LB_LMAC_IDX 0 /* low-band */ 5501 #define IWX_SCAN_HB_LMAC_IDX 1 /* high-band */ 5502 5503 /** 5504 * struct iwx_scan_config 5505 * @flags: enum scan_config_flags 5506 * @tx_chains: valid_tx antenna - ANT_* definitions 5507 * @rx_chains: valid_rx antenna - ANT_* definitions 5508 * @legacy_rates: default legacy rates - enum scan_config_rates 5509 * @out_of_channel_time: default max out of serving channel time 5510 * @suspend_time: default max suspend time 5511 * @dwell_active: default dwell time for active scan 5512 * @dwell_passive: default dwell time for passive scan 5513 * @dwell_fragmented: default dwell time for fragmented scan 5514 * @dwell_extended: default dwell time for channels 1, 6 and 11 5515 * @mac_addr: default mac address to be used in probes 5516 * @bcast_sta_id: the index of the station in the fw 5517 * @channel_flags: default channel flags - enum iwx_channel_flags 5518 * scan_config_channel_flag 5519 * @channel_array: default supported channels 5520 */ 5521 struct iwx_scan_config { 5522 uint32_t flags; 5523 uint32_t tx_chains; 5524 uint32_t rx_chains; 5525 uint32_t legacy_rates; 5526 uint32_t out_of_channel_time[IWX_SCAN_TWO_LMACS]; 5527 uint32_t suspend_time[IWX_SCAN_TWO_LMACS]; 5528 struct iwx_scan_dwell dwell; 5529 uint8_t mac_addr[ETHER_ADDR_LEN]; 5530 uint8_t bcast_sta_id; 5531 uint8_t channel_flags; 5532 uint8_t channel_array[]; 5533 } __packed; /* SCAN_CONFIG_DB_CMD_API_S_2 */ 5534 5535 /** 5536 * iwx_umac_scan_flags 5537 *@IWX_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5538 * can be preempted by other scan requests with higher priority. 5539 * The low priority scan will be resumed when the higher proirity scan is 5540 * completed. 5541 *@IWX_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5542 * when scan starts. 5543 */ 5544 #define IWX_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0) 5545 #define IWX_UMAC_SCAN_FLAG_START_NOTIF (1 << 1) 5546 5547 #define IWX_UMAC_SCAN_UID_TYPE_OFFSET 0 5548 #define IWX_UMAC_SCAN_UID_SEQ_OFFSET 8 5549 5550 #define IWX_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0) 5551 #define IWX_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1) 5552 #define IWX_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2) 5553 #define IWX_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3) 5554 #define IWX_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4) 5555 #define IWX_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5) 5556 #define IWX_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6) 5557 #define IWX_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7) 5558 #define IWX_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8) 5559 #define IWX_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9) 5560 #define IWX_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10) 5561 /* Extended dwell is obselete when adaptive dwell is used, making this 5562 * bit reusable. Hence, probe request defer is used only when adaptive 5563 * dwell is supported. */ 5564 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10) 5565 #define IWX_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11) 5566 #define IWX_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13) 5567 #define IWX_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14) 5568 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15) 5569 5570 /** 5571 * UMAC scan general flags #2 5572 * @IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete 5573 * notification per channel or not. 5574 * @IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel 5575 * reorder optimization or not. 5576 */ 5577 #define IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0) 5578 #define IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1) 5579 5580 /** 5581 * UMAC scan general flags version 2 5582 * 5583 * The FW flags were reordered and hence the driver introduce version 2 5584 * 5585 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC: periodic or scheduled 5586 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL: pass all probe responses and beacons 5587 * during scan iterations 5588 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE: send complete notification 5589 * on every iteration instead of only once after the last iteration 5590 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1: fragmented scan LMAC1 5591 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2: fragmented scan LMAC2 5592 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH: does this scan check for profile matching 5593 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS: use all valid chains for RX 5594 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL: works with adaptive dwell 5595 * for active channel 5596 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE: can be preempted by other requests 5597 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START: send notification of scan start 5598 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID: matching on multiple SSIDs 5599 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE: all the channels scanned 5600 * as passive 5601 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN: at the end of 2.4GHz and 5602 * 5.2Ghz bands scan, trigger scan on 6GHz band to discover 5603 * the reported collocated APs 5604 */ 5605 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC (1 << 0) 5606 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL (1 << 1) 5607 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE (1 << 2) 5608 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1 (1 << 3) 5609 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2 (1 << 4) 5610 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH (1 << 5) 5611 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS (1 << 6) 5612 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL (1 << 7) 5613 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE (1 << 8) 5614 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START (1 << 9) 5615 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID (1 << 10) 5616 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE (1 << 11) 5617 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN (1 << 12) 5618 5619 /** 5620 * struct iwx_scan_channel_cfg_umac 5621 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5622 * @channel_num: channel number 1-13 etc. 5623 * @iter_count: repetition count for the channel. 5624 * @iter_interval: interval between two scan iterations on one channel. 5625 */ 5626 struct iwx_scan_channel_cfg_umac { 5627 uint32_t flags; 5628 union { 5629 struct { 5630 uint8_t channel_num; 5631 uint8_t iter_count; 5632 uint16_t iter_interval; 5633 } v1; /* SCAN_CHANNEL_CFG_S_VER1 */ 5634 struct { 5635 uint8_t channel_num; 5636 uint8_t band; 5637 uint8_t iter_count; 5638 uint8_t iter_interval; 5639 } v2; /* SCAN_CHANNEL_CFG_S_VER{2,3,4} */ 5640 }; 5641 } __packed; 5642 5643 /** 5644 * struct iwx_scan_umac_schedule 5645 * @interval: interval in seconds between scan iterations 5646 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5647 * @reserved: for alignment and future use 5648 */ 5649 struct iwx_scan_umac_schedule { 5650 uint16_t interval; 5651 uint8_t iter_count; 5652 uint8_t reserved; 5653 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5654 5655 /** 5656 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command 5657 * parameters following channels configuration array. 5658 * @schedule: two scheduling plans. 5659 * @delay: delay in TUs before starting the first scan iteration 5660 * @reserved: for future use and alignment 5661 * @preq: probe request with IEs blocks 5662 * @direct_scan: list of SSIDs for directed active scan 5663 */ 5664 struct iwx_scan_req_umac_tail_v1 { 5665 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5666 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 5667 uint16_t delay; 5668 uint16_t reserved; 5669 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5670 struct iwx_scan_probe_req_v1 preq; 5671 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 5672 } __packed; 5673 5674 /** 5675 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command 5676 * parameters following channels configuration array. 5677 * @schedule: two scheduling plans. 5678 * @delay: delay in TUs before starting the first scan iteration 5679 * @reserved: for future use and alignment 5680 * @preq: probe request with IEs blocks 5681 * @direct_scan: list of SSIDs for directed active scan 5682 */ 5683 struct iwx_scan_req_umac_tail_v2 { 5684 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5685 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 5686 uint16_t delay; 5687 uint16_t reserved; 5688 /* SCAN_PROBE_PARAMS_API_S_VER_2 */ 5689 struct iwx_scan_probe_req preq; 5690 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 5691 } __packed; 5692 5693 /** 5694 * struct iwx_scan_umac_chan_param 5695 * @flags: channel flags &enum iwl_scan_channel_flags 5696 * @count: num of channels in scan request 5697 * @reserved: for future use and alignment 5698 */ 5699 struct iwx_scan_umac_chan_param { 5700 uint8_t flags; 5701 uint8_t count; 5702 uint16_t reserved; 5703 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5704 5705 #define IWX_SCAN_LB_LMAC_IDX 0 5706 #define IWX_SCAN_HB_LMAC_IDX 1 5707 5708 /** 5709 * struct iwx_scan_req_umac 5710 * @flags: &enum iwl_umac_scan_flags 5711 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 5712 * @ooc_priority: out of channel priority - &enum iwl_scan_priority 5713 * @general_flags: &enum iwl_umac_scan_general_flags 5714 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 5715 * @extended_dwell: dwell time for channels 1, 6 and 11 5716 * @active_dwell: dwell time for active scan per LMAC 5717 * @passive_dwell: dwell time for passive scan per LMAC 5718 * @fragmented_dwell: dwell time for fragmented passive scan 5719 * @adwell_default_n_aps: for adaptive dwell the default number of APs 5720 * per channel 5721 * @adwell_default_n_aps_social: for adaptive dwell the default 5722 * number of APs per social (1,6,11) channel 5723 * @general_flags2: &enum iwl_umac_scan_general_flags2 5724 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added 5725 * to total scan time 5726 * @max_out_time: max out of serving channel time, per LMAC - for CDB there 5727 * are 2 LMACs (high band and low band) 5728 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs 5729 * @scan_priority: scan internal prioritization &enum iwl_scan_priority 5730 * @num_of_fragments: Number of fragments needed for full coverage per band. 5731 * Relevant only for fragmented scan. 5732 * @channel: &struct iwx_scan_umac_chan_param 5733 * @reserved: for future use and alignment 5734 * @reserved3: for future use and alignment 5735 * @data: &struct iwx_scan_channel_cfg_umac and 5736 * &struct iwx_scan_req_umac_tail 5737 */ 5738 struct iwx_scan_req_umac { 5739 uint32_t flags; 5740 uint32_t uid; 5741 uint32_t ooc_priority; 5742 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5743 uint16_t general_flags; 5744 uint8_t reserved; 5745 uint8_t scan_start_mac_id; 5746 union { 5747 struct { 5748 uint8_t extended_dwell; 5749 uint8_t active_dwell; 5750 uint8_t passive_dwell; 5751 uint8_t fragmented_dwell; 5752 uint32_t max_out_time; 5753 uint32_t suspend_time; 5754 uint32_t scan_priority; 5755 struct iwx_scan_umac_chan_param channel; 5756 uint8_t data[]; 5757 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5758 struct { 5759 uint8_t extended_dwell; 5760 uint8_t active_dwell; 5761 uint8_t passive_dwell; 5762 uint8_t fragmented_dwell; 5763 uint32_t max_out_time[2]; 5764 uint32_t suspend_time[2]; 5765 uint32_t scan_priority; 5766 struct iwx_scan_umac_chan_param channel; 5767 uint8_t data[]; 5768 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */ 5769 struct { 5770 uint8_t active_dwell; 5771 uint8_t passive_dwell; 5772 uint8_t fragmented_dwell; 5773 uint8_t adwell_default_n_aps; 5774 uint8_t adwell_default_n_aps_social; 5775 uint8_t reserved3; 5776 uint16_t adwell_max_budget; 5777 uint32_t max_out_time[2]; 5778 uint32_t suspend_time[2]; 5779 uint32_t scan_priority; 5780 struct iwx_scan_umac_chan_param channel; 5781 uint8_t data[]; 5782 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */ 5783 struct { 5784 uint8_t active_dwell[2]; 5785 uint8_t reserved2; 5786 uint8_t adwell_default_n_aps; 5787 uint8_t adwell_default_n_aps_social; 5788 uint8_t general_flags2; 5789 uint16_t adwell_max_budget; 5790 uint32_t max_out_time[2]; 5791 uint32_t suspend_time[2]; 5792 uint32_t scan_priority; 5793 uint8_t passive_dwell[2]; 5794 uint8_t num_of_fragments[2]; 5795 struct iwx_scan_umac_chan_param channel; 5796 uint8_t data[]; 5797 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */ 5798 struct { 5799 uint8_t active_dwell[2]; 5800 uint8_t adwell_default_hb_n_aps; 5801 uint8_t adwell_default_lb_n_aps; 5802 uint8_t adwell_default_n_aps_social; 5803 uint8_t general_flags2; 5804 uint16_t adwell_max_budget; 5805 uint32_t max_out_time[2]; 5806 uint32_t suspend_time[2]; 5807 uint32_t scan_priority; 5808 uint8_t passive_dwell[2]; 5809 uint8_t num_of_fragments[2]; 5810 struct iwx_scan_umac_chan_param channel; 5811 uint8_t data[]; 5812 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */ 5813 }; 5814 } __packed; 5815 5816 #define IWX_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwx_scan_req_umac) 5817 #define IWX_SCAN_REQ_UMAC_SIZE_V7 48 5818 #define IWX_SCAN_REQ_UMAC_SIZE_V6 44 5819 #define IWX_SCAN_REQ_UMAC_SIZE_V1 36 5820 5821 /** 5822 * struct iwx_umac_scan_abort 5823 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 5824 * @flags: reserved 5825 */ 5826 struct iwx_umac_scan_abort { 5827 uint32_t uid; 5828 uint32_t flags; 5829 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5830 5831 /** 5832 * struct iwx_umac_scan_complete 5833 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 5834 * @last_schedule: last scheduling line 5835 * @last_iter: last scan iteration number 5836 * @scan status: &enum iwx_scan_offload_complete_status 5837 * @ebs_status: &enum iwx_scan_ebs_status 5838 * @time_from_last_iter: time elapsed from last iteration 5839 * @reserved: for future use 5840 */ 5841 struct iwx_umac_scan_complete { 5842 uint32_t uid; 5843 uint8_t last_schedule; 5844 uint8_t last_iter; 5845 uint8_t status; 5846 uint8_t ebs_status; 5847 uint32_t time_from_last_iter; 5848 uint32_t reserved; 5849 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5850 5851 #define IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5852 /** 5853 * struct iwx_scan_offload_profile_match - match information 5854 * @bssid: matched bssid 5855 * @channel: channel where the match occurred 5856 * @energy: 5857 * @matching_feature: 5858 * @matching_channels: bitmap of channels that matched, referencing 5859 * the channels passed in tue scan offload request 5860 */ 5861 struct iwx_scan_offload_profile_match { 5862 uint8_t bssid[ETHER_ADDR_LEN]; 5863 uint16_t reserved; 5864 uint8_t channel; 5865 uint8_t energy; 5866 uint8_t matching_feature; 5867 uint8_t matching_channels[IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5868 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5869 5870 /** 5871 * struct iwx_scan_offload_profiles_query - match results query response 5872 * @matched_profiles: bitmap of matched profiles, referencing the 5873 * matches passed in the scan offload request 5874 * @last_scan_age: age of the last offloaded scan 5875 * @n_scans_done: number of offloaded scans done 5876 * @gp2_d0u: GP2 when D0U occurred 5877 * @gp2_invoked: GP2 when scan offload was invoked 5878 * @resume_while_scanning: not used 5879 * @self_recovery: obsolete 5880 * @reserved: reserved 5881 * @matches: array of match information, one for each match 5882 */ 5883 struct iwx_scan_offload_profiles_query { 5884 uint32_t matched_profiles; 5885 uint32_t last_scan_age; 5886 uint32_t n_scans_done; 5887 uint32_t gp2_d0u; 5888 uint32_t gp2_invoked; 5889 uint8_t resume_while_scanning; 5890 uint8_t self_recovery; 5891 uint16_t reserved; 5892 struct iwx_scan_offload_profile_match matches[IWX_SCAN_MAX_PROFILES]; 5893 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5894 5895 /** 5896 * struct iwx_umac_scan_iter_complete_notif - notifies end of scanning iteration 5897 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 5898 * @scanned_channels: number of channels scanned and number of valid elements in 5899 * results array 5900 * @status: one of SCAN_COMP_STATUS_* 5901 * @bt_status: BT on/off status 5902 * @last_channel: last channel that was scanned 5903 * @tsf_low: TSF timer (lower half) in usecs 5904 * @tsf_high: TSF timer (higher half) in usecs 5905 * @results: array of scan results, only "scanned_channels" of them are valid 5906 */ 5907 struct iwx_umac_scan_iter_complete_notif { 5908 uint32_t uid; 5909 uint8_t scanned_channels; 5910 uint8_t status; 5911 uint8_t bt_status; 5912 uint8_t last_channel; 5913 uint32_t tsf_low; 5914 uint32_t tsf_high; 5915 struct iwx_scan_results_notif results[]; 5916 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5917 5918 #define IWX_GSCAN_START_CMD 0x0 5919 #define IWX_GSCAN_STOP_CMD 0x1 5920 #define IWX_GSCAN_SET_HOTLIST_CMD 0x2 5921 #define IWX_GSCAN_RESET_HOTLIST_CMD 0x3 5922 #define IWX_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4 5923 #define IWX_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5 5924 #define IWX_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD 5925 #define IWX_GSCAN_HOTLIST_CHANGE_EVENT 0xFE 5926 #define IWX_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF 5927 5928 /* STA API */ 5929 5930 /** 5931 * flags for the ADD_STA host command 5932 * @IWX_STA_FLG_REDUCED_TX_PWR_CTRL: 5933 * @IWX_STA_FLG_REDUCED_TX_PWR_DATA: 5934 * @IWX_STA_FLG_DISABLE_TX: set if TX should be disabled 5935 * @IWX_STA_FLG_PS: set if STA is in Power Save 5936 * @IWX_STA_FLG_INVALID: set if STA is invalid 5937 * @IWX_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5938 * @IWX_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5939 * @IWX_STA_FLG_DRAIN_FLOW: drain flow 5940 * @IWX_STA_FLG_PAN: STA is for PAN interface 5941 * @IWX_STA_FLG_CLASS_AUTH: 5942 * @IWX_STA_FLG_CLASS_ASSOC: 5943 * @IWX_STA_FLG_CLASS_MIMO_PROT: 5944 * @IWX_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5945 * @IWX_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5946 * @IWX_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5947 * initialised by driver and can be updated by fw upon reception of 5948 * action frames that can change the channel width. When cleared the fw 5949 * will send all the frames in 20MHz even when FAT channel is requested. 5950 * @IWX_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5951 * driver and can be updated by fw upon reception of action frames. 5952 * @IWX_STA_FLG_MFP_EN: Management Frame Protection 5953 */ 5954 #define IWX_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3) 5955 #define IWX_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6) 5956 5957 #define IWX_STA_FLG_DISABLE_TX (1 << 4) 5958 5959 #define IWX_STA_FLG_PS (1 << 8) 5960 #define IWX_STA_FLG_DRAIN_FLOW (1 << 12) 5961 #define IWX_STA_FLG_PAN (1 << 13) 5962 #define IWX_STA_FLG_CLASS_AUTH (1 << 14) 5963 #define IWX_STA_FLG_CLASS_ASSOC (1 << 15) 5964 #define IWX_STA_FLG_RTS_MIMO_PROT (1 << 17) 5965 5966 #define IWX_STA_FLG_MAX_AGG_SIZE_SHIFT 19 5967 #define IWX_STA_FLG_MAX_AGG_SIZE_8K (0 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5968 #define IWX_STA_FLG_MAX_AGG_SIZE_16K (1 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5969 #define IWX_STA_FLG_MAX_AGG_SIZE_32K (2 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5970 #define IWX_STA_FLG_MAX_AGG_SIZE_64K (3 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5971 #define IWX_STA_FLG_MAX_AGG_SIZE_128K (4 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5972 #define IWX_STA_FLG_MAX_AGG_SIZE_256K (5 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5973 #define IWX_STA_FLG_MAX_AGG_SIZE_512K (6 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5974 #define IWX_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5975 #define IWX_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5976 5977 #define IWX_STA_FLG_AGG_MPDU_DENS_SHIFT 23 5978 #define IWX_STA_FLG_AGG_MPDU_DENS_2US (4 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5979 #define IWX_STA_FLG_AGG_MPDU_DENS_4US (5 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5980 #define IWX_STA_FLG_AGG_MPDU_DENS_8US (6 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5981 #define IWX_STA_FLG_AGG_MPDU_DENS_16US (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5982 #define IWX_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5983 5984 #define IWX_STA_FLG_FAT_EN_20MHZ (0 << 26) 5985 #define IWX_STA_FLG_FAT_EN_40MHZ (1 << 26) 5986 #define IWX_STA_FLG_FAT_EN_80MHZ (2 << 26) 5987 #define IWX_STA_FLG_FAT_EN_160MHZ (3 << 26) 5988 #define IWX_STA_FLG_FAT_EN_MSK (3 << 26) 5989 5990 #define IWX_STA_FLG_MIMO_EN_SISO (0 << 28) 5991 #define IWX_STA_FLG_MIMO_EN_MIMO2 (1 << 28) 5992 #define IWX_STA_FLG_MIMO_EN_MIMO3 (2 << 28) 5993 #define IWX_STA_FLG_MIMO_EN_MSK (3 << 28) 5994 5995 /** 5996 * key flags for the ADD_STA host command 5997 * @IWX_STA_KEY_FLG_NO_ENC: no encryption 5998 * @IWX_STA_KEY_FLG_WEP: WEP encryption algorithm 5999 * @IWX_STA_KEY_FLG_CCM: CCMP encryption algorithm 6000 * @IWX_STA_KEY_FLG_TKIP: TKIP encryption algorithm 6001 * @IWX_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 6002 * @IWX_STA_KEY_FLG_CMAC: CMAC encryption algorithm 6003 * @IWX_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 6004 * @IWX_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 6005 * @IWX_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 6006 * station info array (1 - n 1X mode) 6007 * @IWX_STA_KEY_FLG_KEYID_MSK: the index of the key 6008 * @IWX_STA_KEY_NOT_VALID: key is invalid 6009 * @IWX_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 6010 * @IWX_STA_KEY_MULTICAST: set for multicast key 6011 * @IWX_STA_KEY_MFP: key is used for Management Frame Protection 6012 */ 6013 #define IWX_STA_KEY_FLG_NO_ENC (0 << 0) 6014 #define IWX_STA_KEY_FLG_WEP (1 << 0) 6015 #define IWX_STA_KEY_FLG_CCM (2 << 0) 6016 #define IWX_STA_KEY_FLG_TKIP (3 << 0) 6017 #define IWX_STA_KEY_FLG_EXT (4 << 0) 6018 #define IWX_STA_KEY_FLG_CMAC (6 << 0) 6019 #define IWX_STA_KEY_FLG_ENC_UNKNOWN (7 << 0) 6020 #define IWX_STA_KEY_FLG_EN_MSK (7 << 0) 6021 #define IWX_STA_KEY_FLG_WEP_KEY_MAP (1 << 3) 6022 #define IWX_STA_KEY_FLG_KEYID_POS 8 6023 #define IWX_STA_KEY_FLG_KEYID_MSK (3 << IWX_STA_KEY_FLG_KEYID_POS) 6024 #define IWX_STA_KEY_NOT_VALID (1 << 11) 6025 #define IWX_STA_KEY_FLG_WEP_13BYTES (1 << 12) 6026 #define IWX_STA_KEY_MULTICAST (1 << 14) 6027 #define IWX_STA_KEY_MFP (1 << 15) 6028 6029 /** 6030 * indicate to the fw what flag are being changed 6031 * @IWX_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 6032 * @IWX_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 6033 * @IWX_STA_MODIFY_TX_RATE: unused 6034 * @IWX_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 6035 * @IWX_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 6036 * @IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 6037 * @IWX_STA_MODIFY_PROT_TH: 6038 * @IWX_STA_MODIFY_QUEUES: modify the queues used by this station 6039 */ 6040 #define IWX_STA_MODIFY_QUEUE_REMOVAL (1 << 0) 6041 #define IWX_STA_MODIFY_TID_DISABLE_TX (1 << 1) 6042 #define IWX_STA_MODIFY_TX_RATE (1 << 2) 6043 #define IWX_STA_MODIFY_ADD_BA_TID (1 << 3) 6044 #define IWX_STA_MODIFY_REMOVE_BA_TID (1 << 4) 6045 #define IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5) 6046 #define IWX_STA_MODIFY_PROT_TH (1 << 6) 6047 #define IWX_STA_MODIFY_QUEUES (1 << 7) 6048 6049 #define IWX_STA_MODE_MODIFY 1 6050 6051 /** 6052 * type of sleep of the station 6053 * @IWX_STA_SLEEP_STATE_AWAKE: 6054 * @IWX_STA_SLEEP_STATE_PS_POLL: 6055 * @IWX_STA_SLEEP_STATE_UAPSD: 6056 * @IWX_STA_SLEEP_STATE_MOREDATA: set more-data bit on 6057 * (last) released frame 6058 */ 6059 #define IWX_STA_SLEEP_STATE_AWAKE 0 6060 #define IWX_STA_SLEEP_STATE_PS_POLL (1 << 0) 6061 #define IWX_STA_SLEEP_STATE_UAPSD (1 << 1) 6062 #define IWX_STA_SLEEP_STATE_MOREDATA (1 << 2) 6063 6064 /* STA ID and color bits definitions */ 6065 #define IWX_STA_ID_SEED (0x0f) 6066 #define IWX_STA_ID_POS (0) 6067 #define IWX_STA_ID_MSK (IWX_STA_ID_SEED << IWX_STA_ID_POS) 6068 6069 #define IWX_STA_COLOR_SEED (0x7) 6070 #define IWX_STA_COLOR_POS (4) 6071 #define IWX_STA_COLOR_MSK (IWX_STA_COLOR_SEED << IWX_STA_COLOR_POS) 6072 6073 #define IWX_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 6074 (((id_n_color) & IWX_STA_COLOR_MSK) >> IWX_STA_COLOR_POS) 6075 #define IWX_STA_ID_N_COLOR_GET_ID(id_n_color) \ 6076 (((id_n_color) & IWX_STA_ID_MSK) >> IWX_STA_ID_POS) 6077 6078 #define IWX_STA_KEY_MAX_NUM (16) 6079 #define IWX_STA_KEY_IDX_INVALID (0xff) 6080 #define IWX_STA_KEY_MAX_DATA_KEY_NUM (4) 6081 #define IWX_MAX_GLOBAL_KEYS (4) 6082 #define IWX_STA_KEY_LEN_WEP40 (5) 6083 #define IWX_STA_KEY_LEN_WEP104 (13) 6084 6085 /** 6086 * struct iwx_keyinfo - key information 6087 * @key_flags: type %iwx_sta_key_flag 6088 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6089 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6090 * @key_offset: key offset in the fw's key table 6091 * @key: 16-byte unicast decryption key 6092 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 6093 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 6094 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 6095 */ 6096 struct iwx_keyinfo { 6097 uint16_t key_flags; 6098 uint8_t tkip_rx_tsc_byte2; 6099 uint8_t reserved1; 6100 uint16_t tkip_rx_ttak[5]; 6101 uint8_t key_offset; 6102 uint8_t reserved2; 6103 uint8_t key[16]; 6104 uint64_t tx_secur_seq_cnt; 6105 uint64_t hw_tkip_mic_rx_key; 6106 uint64_t hw_tkip_mic_tx_key; 6107 } __packed; 6108 6109 #define IWX_ADD_STA_STATUS_MASK 0xFF 6110 #define IWX_ADD_STA_BAID_VALID_MASK 0x8000 6111 #define IWX_ADD_STA_BAID_MASK 0x7F00 6112 #define IWX_ADD_STA_BAID_SHIFT 8 6113 6114 /** 6115 * struct iwx_add_sta_cmd - Add/modify a station in the fw's sta table. 6116 * ( REPLY_ADD_STA = 0x18 ) 6117 * @add_modify: see &enum iwl_sta_mode 6118 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD) 6119 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6120 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field. 6121 * @mac_id_n_color: the Mac context this station belongs to, 6122 * see &enum iwl_ctxt_id_and_color 6123 * @addr: station's MAC address 6124 * @reserved2: reserved 6125 * @sta_id: index of station in uCode's station table 6126 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave 6127 * alone. 1 - modify, 0 - don't change. 6128 * @reserved3: reserved 6129 * @station_flags: look at &enum iwl_sta_flags 6130 * @station_flags_msk: what of %station_flags have changed, 6131 * also &enum iwl_sta_flags 6132 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6133 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set 6134 * add_immediate_ba_ssn. 6135 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6136 * Set %STA_MODIFY_REMOVE_BA_TID to use this field 6137 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6138 * add_immediate_ba_tid. 6139 * @sleep_tx_count: number of packets to transmit to station even though it is 6140 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6141 * keeps track of STA sleep state. 6142 * @station_type: type of this station. See &enum iwl_sta_type. 6143 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag. 6144 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6145 * mac-addr. 6146 * @beamform_flags: beam forming controls 6147 * @tfd_queue_msk: tfd queues used by this station. 6148 * Obselete for new TX API (9 and above). 6149 * @rx_ba_window: aggregation window size 6150 * @sp_length: the size of the SP in actual number of frames 6151 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver 6152 * enabled ACs. 6153 * 6154 * The device contains an internal table of per-station information, with info 6155 * on security keys, aggregation parameters, and Tx rates for initial Tx 6156 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD). 6157 * 6158 * ADD_STA sets up the table entry for one station, either creating a new 6159 * entry, or modifying a pre-existing one. 6160 */ 6161 struct iwx_add_sta_cmd { 6162 uint8_t add_modify; 6163 uint8_t awake_acs; 6164 uint16_t tid_disable_tx; 6165 uint32_t mac_id_n_color; 6166 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6167 uint16_t reserved2; 6168 uint8_t sta_id; 6169 uint8_t modify_mask; 6170 uint16_t reserved3; 6171 uint32_t station_flags; 6172 uint32_t station_flags_msk; 6173 uint8_t add_immediate_ba_tid; 6174 uint8_t remove_immediate_ba_tid; 6175 uint16_t add_immediate_ba_ssn; 6176 uint16_t sleep_tx_count; 6177 uint8_t sleep_state_flags; 6178 uint8_t station_type; 6179 uint16_t assoc_id; 6180 uint16_t beamform_flags; 6181 uint32_t tfd_queue_msk; 6182 uint16_t rx_ba_window; 6183 uint8_t sp_length; 6184 uint8_t uapsd_acs; 6185 } __packed; /* ADD_STA_CMD_API_S_VER_10 */ 6186 6187 /** 6188 * FW station types 6189 * ( REPLY_ADD_STA = 0x18 ) 6190 * @IWX_STA_LINK: Link station - normal RX and TX traffic. 6191 * @IWX_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons 6192 * and probe responses. 6193 * @IWX_STA_MULTICAST: multicast traffic, 6194 * @IWX_STA_TDLS_LINK: TDLS link station 6195 * @IWX_STA_AUX_ACTIVITY: auxilary station (scan, ROC and so on). 6196 */ 6197 #define IWX_STA_LINK 0 6198 #define IWX_STA_GENERAL_PURPOSE 1 6199 #define IWX_STA_MULTICAST 2 6200 #define IWX_STA_TDLS_LINK 3 6201 #define IWX_STA_AUX_ACTIVITY 4 6202 6203 /** 6204 * struct iwx_add_sta_key_common - add/modify sta key common part 6205 * ( REPLY_ADD_STA_KEY = 0x17 ) 6206 * @sta_id: index of station in uCode's station table 6207 * @key_offset: key offset in key storage 6208 * @key_flags: IWX_STA_KEY_FLG_* 6209 * @key: key material data 6210 * @rx_secur_seq_cnt: RX security sequence counter for the key 6211 */ 6212 struct iwx_add_sta_key_common { 6213 uint8_t sta_id; 6214 uint8_t key_offset; 6215 uint16_t key_flags; 6216 uint8_t key[32]; 6217 uint8_t rx_secur_seq_cnt[16]; 6218 } __packed; 6219 6220 /** 6221 * struct iwx_add_sta_key_cmd_v1 - add/modify sta key 6222 * @common: see &struct iwx_add_sta_key_common 6223 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6224 * @reserved: reserved 6225 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6226 */ 6227 struct iwx_add_sta_key_cmd_v1 { 6228 struct iwx_add_sta_key_common common; 6229 uint8_t tkip_rx_tsc_byte2; 6230 uint8_t reserved; 6231 uint16_t tkip_rx_ttak[5]; 6232 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */ 6233 6234 /** 6235 * struct iwx_add_sta_key_cmd - add/modify sta key 6236 * @common: see &struct iwx_add_sta_key_common 6237 * @rx_mic_key: TKIP RX unicast or multicast key 6238 * @tx_mic_key: TKIP TX key 6239 * @transmit_seq_cnt: TSC, transmit packet number 6240 */ 6241 struct iwx_add_sta_key_cmd { 6242 struct iwx_add_sta_key_common common; 6243 uint64_t rx_mic_key; 6244 uint64_t tx_mic_key; 6245 uint64_t transmit_seq_cnt; 6246 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */ 6247 6248 /** 6249 * status in the response to ADD_STA command 6250 * @IWX_ADD_STA_SUCCESS: operation was executed successfully 6251 * @IWX_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 6252 * @IWX_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 6253 * @IWX_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 6254 * that doesn't exist. 6255 */ 6256 #define IWX_ADD_STA_SUCCESS 0x1 6257 #define IWX_ADD_STA_STATIONS_OVERLOAD 0x2 6258 #define IWX_ADD_STA_IMMEDIATE_BA_FAILURE 0x4 6259 #define IWX_ADD_STA_MODIFY_NON_EXISTING_STA 0x8 6260 6261 /** 6262 * struct iwx_rm_sta_cmd - Add / modify a station in the fw's station table 6263 * ( IWX_REMOVE_STA = 0x19 ) 6264 * @sta_id: the station id of the station to be removed 6265 */ 6266 struct iwx_rm_sta_cmd { 6267 uint8_t sta_id; 6268 uint8_t reserved[3]; 6269 } __packed; /* IWX_REMOVE_STA_CMD_API_S_VER_2 */ 6270 6271 /** 6272 * struct iwx_mgmt_mcast_key_cmd 6273 * ( IWX_MGMT_MCAST_KEY = 0x1f ) 6274 * @ctrl_flags: %iwx_sta_key_flag 6275 * @IGTK: 6276 * @K1: IGTK master key 6277 * @K2: IGTK sub key 6278 * @sta_id: station ID that support IGTK 6279 * @key_id: 6280 * @receive_seq_cnt: initial RSC/PN needed for replay check 6281 */ 6282 struct iwx_mgmt_mcast_key_cmd { 6283 uint32_t ctrl_flags; 6284 uint8_t IGTK[16]; 6285 uint8_t K1[16]; 6286 uint8_t K2[16]; 6287 uint32_t key_id; 6288 uint32_t sta_id; 6289 uint64_t receive_seq_cnt; 6290 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 6291 6292 struct iwx_wep_key { 6293 uint8_t key_index; 6294 uint8_t key_offset; 6295 uint16_t reserved1; 6296 uint8_t key_size; 6297 uint8_t reserved2[3]; 6298 uint8_t key[16]; 6299 } __packed; 6300 6301 struct iwx_wep_key_cmd { 6302 uint32_t mac_id_n_color; 6303 uint8_t num_keys; 6304 uint8_t decryption_type; 6305 uint8_t flags; 6306 uint8_t reserved; 6307 struct iwx_wep_key wep_key[0]; 6308 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 6309 6310 /* 6311 * BT coex 6312 */ 6313 6314 #define IWX_BT_COEX_DISABLE 0x0 6315 #define IWX_BT_COEX_NW 0x1 6316 #define IWX_BT_COEX_BT 0x2 6317 #define IWX_BT_COEX_WIFI 0x3 6318 /* BT_COEX_MODES_E */ 6319 6320 #define IWX_BT_COEX_MPLUT_ENABLED (1 << 0) 6321 #define IWX_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1) 6322 #define IWX_BT_COEX_SYNC2SCO_ENABLED (1 << 2) 6323 #define IWX_BT_COEX_CORUN_ENABLED (1 << 3) 6324 #define IWX_BT_COEX_HIGH_BAND_RET (1 << 4) 6325 /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 6326 6327 /** 6328 * struct iwx_bt_coex_cmd - bt coex configuration command 6329 * @mode: enum %iwx_bt_coex_mode 6330 * @enabled_modules: enum %iwx_bt_coex_enabled_modules 6331 * 6332 * The structure is used for the BT_COEX command. 6333 */ 6334 struct iwx_bt_coex_cmd { 6335 uint32_t mode; 6336 uint32_t enabled_modules; 6337 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 6338 6339 6340 /* 6341 * Location Aware Regulatory (LAR) API - MCC updates 6342 */ 6343 6344 /** 6345 * struct iwx_mcc_update_cmd - Request the device to update geographic 6346 * regulatory profile according to the given MCC (Mobile Country Code). 6347 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6348 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6349 * MCC in the cmd response will be the relevant MCC in the NVM. 6350 * @mcc: given mobile country code 6351 * @source_id: the source from where we got the MCC, see IWX_MCC_SOURCE_* 6352 * @reserved: reserved for alignment 6353 * @key: integrity key for MCC API OEM testing 6354 * @reserved2: reserved 6355 */ 6356 struct iwx_mcc_update_cmd { 6357 uint16_t mcc; 6358 uint8_t source_id; 6359 uint8_t reserved; 6360 uint32_t key; 6361 uint32_t reserved2[5]; 6362 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6363 6364 /** 6365 * iwx_mcc_update_resp_v3 - response to MCC_UPDATE_CMD. 6366 * Contains the new channel control profile map, if changed, and the new MCC 6367 * (mobile country code). 6368 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6369 * @status: see &enum iwx_mcc_update_status 6370 * @mcc: the new applied MCC 6371 * @cap: capabilities for all channels which matches the MCC 6372 * @source_id: the MCC source, see IWX_MCC_SOURCE_* 6373 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6374 * @reserved: reserved. 6375 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6376 * channels, depending on platform) 6377 * @channels: channel control data map, DWORD for each channel. Only the first 6378 * 16bits are used. 6379 */ 6380 struct iwx_mcc_update_resp_v3 { 6381 uint32_t status; 6382 uint16_t mcc; 6383 uint8_t cap; 6384 uint8_t source_id; 6385 uint16_t time; 6386 uint16_t geo_info; 6387 uint32_t n_channels; 6388 uint32_t channels[0]; 6389 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */ 6390 6391 /** 6392 * geographic information. 6393 * @GEO_NO_INFO: no special info for this geo profile. 6394 * @GEO_WMM_ETSI_5GHZ_INFO: this geo profile limits the WMM params 6395 * for the 5 GHz band. 6396 */ 6397 #define IWX_GEO_NO_INFO 0 6398 #define IWX_GEO_WMM_ETSI_5GHZ_INFO (1 << 0) 6399 6400 /** 6401 * struct iwx_mcc_update_resp - response to MCC_UPDATE_CMD. 6402 * Contains the new channel control profile map, if changed, and the new MCC 6403 * (mobile country code). 6404 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6405 * @status: see &enum iwl_mcc_update_status 6406 * @mcc: the new applied MCC 6407 * @cap: capabilities for all channels which matches the MCC 6408 * @time: time elapsed from the MCC test start (in units of 30 seconds) 6409 * @geo_info: geographic specific profile information 6410 * see IWX_GEO_* 6411 * @source_id: the MCC source, see IWX_MCC_SOURCE_* 6412 * @reserved: for four bytes alignment. 6413 * @n_channels: number of channels in @channels_data. 6414 * @channels: channel control data map, DWORD for each channel. Only the first 6415 * 16bits are used. 6416 */ 6417 struct iwx_mcc_update_resp { 6418 uint32_t status; 6419 uint16_t mcc; 6420 uint16_t cap; 6421 uint16_t time; 6422 uint16_t geo_info; 6423 uint8_t source_id; 6424 uint8_t reserved[3]; 6425 uint32_t n_channels; 6426 uint32_t channels[0]; 6427 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_4 */ 6428 6429 /** 6430 * struct iwx_mcc_chub_notif - chub notifies of mcc change 6431 * (MCC_CHUB_UPDATE_CMD = 0xc9) 6432 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6433 * the cellular and connectivity cores that gets updates of the mcc, and 6434 * notifies the ucode directly of any mcc change. 6435 * The ucode requests the driver to request the device to update geographic 6436 * regulatory profile according to the given MCC (Mobile Country Code). 6437 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6438 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6439 * MCC in the cmd response will be the relevant MCC in the NVM. 6440 * @mcc: given mobile country code 6441 * @source_id: identity of the change originator, see IWX_MCC_SOURCE_* 6442 * @reserved1: reserved for alignment 6443 */ 6444 struct iwx_mcc_chub_notif { 6445 uint16_t mcc; 6446 uint8_t source_id; 6447 uint8_t reserved1; 6448 } __packed; /* LAR_MCC_NOTIFY_S */ 6449 6450 enum iwx_mcc_update_status { 6451 IWX_MCC_RESP_NEW_CHAN_PROFILE, 6452 IWX_MCC_RESP_SAME_CHAN_PROFILE, 6453 IWX_MCC_RESP_INVALID, 6454 IWX_MCC_RESP_NVM_DISABLED, 6455 IWX_MCC_RESP_ILLEGAL, 6456 IWX_MCC_RESP_LOW_PRIORITY, 6457 IWX_MCC_RESP_TEST_MODE_ACTIVE, 6458 IWX_MCC_RESP_TEST_MODE_NOT_ACTIVE, 6459 IWX_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 6460 }; 6461 6462 #define IWX_MCC_SOURCE_OLD_FW 0 6463 #define IWX_MCC_SOURCE_ME 1 6464 #define IWX_MCC_SOURCE_BIOS 2 6465 #define IWX_MCC_SOURCE_3G_LTE_HOST 3 6466 #define IWX_MCC_SOURCE_3G_LTE_DEVICE 4 6467 #define IWX_MCC_SOURCE_WIFI 5 6468 #define IWX_MCC_SOURCE_RESERVED 6 6469 #define IWX_MCC_SOURCE_DEFAULT 7 6470 #define IWX_MCC_SOURCE_UNINITIALIZED 8 6471 #define IWX_MCC_SOURCE_MCC_API 9 6472 #define IWX_MCC_SOURCE_GET_CURRENT 0x10 6473 #define IWX_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11 6474 6475 /* 6476 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6477 * As the firmware is slowly running out of command IDs and grouping of 6478 * commands is desirable anyway, the firmware is extending the command 6479 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6480 * former flags field, since that's always 0 on commands and thus can 6481 * be easily used to distinguish between the two). 6482 * 6483 * These functions retrieve specific information from the id field in 6484 * the iwx_host_cmd struct which contains the command id, the group id, 6485 * and the version of the command. 6486 */ 6487 static inline uint8_t 6488 iwx_cmd_opcode(uint32_t cmdid) 6489 { 6490 return cmdid & 0xff; 6491 } 6492 6493 static inline uint8_t 6494 iwx_cmd_groupid(uint32_t cmdid) 6495 { 6496 return ((cmdid & 0Xff00) >> 8); 6497 } 6498 6499 static inline uint8_t 6500 iwx_cmd_version(uint32_t cmdid) 6501 { 6502 return ((cmdid & 0xff0000) >> 16); 6503 } 6504 6505 static inline uint32_t 6506 iwx_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6507 { 6508 return opcode + (groupid << 8) + (version << 16); 6509 } 6510 6511 /* make uint16_t wide id out of uint8_t group and opcode */ 6512 #define IWX_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6513 6514 struct iwx_cmd_header { 6515 uint8_t code; 6516 uint8_t flags; 6517 uint8_t idx; 6518 uint8_t qid; 6519 } __packed; 6520 6521 struct iwx_cmd_header_wide { 6522 uint8_t opcode; 6523 uint8_t group_id; 6524 uint8_t idx; 6525 uint8_t qid; 6526 uint16_t length; 6527 uint8_t reserved; 6528 uint8_t version; 6529 } __packed; 6530 6531 #define IWX_POWER_SCHEME_CAM 1 6532 #define IWX_POWER_SCHEME_BPS 2 6533 #define IWX_POWER_SCHEME_LP 3 6534 6535 #define IWX_DEF_CMD_PAYLOAD_SIZE 320 6536 #define IWX_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwx_cmd_header)) 6537 #define IWX_CMD_FAILED_MSK 0x40 6538 6539 /** 6540 * struct iwx_device_cmd 6541 * 6542 * For allocation of the command and tx queues, this establishes the overall 6543 * size of the largest command we send to uCode, except for commands that 6544 * aren't fully copied and use other TFD space. 6545 */ 6546 struct iwx_device_cmd { 6547 union { 6548 struct { 6549 struct iwx_cmd_header hdr; 6550 uint8_t data[IWX_DEF_CMD_PAYLOAD_SIZE]; 6551 }; 6552 struct { 6553 struct iwx_cmd_header_wide hdr_wide; 6554 uint8_t data_wide[IWX_DEF_CMD_PAYLOAD_SIZE - 6555 sizeof(struct iwx_cmd_header_wide) + 6556 sizeof(struct iwx_cmd_header)]; 6557 }; 6558 }; 6559 } __packed; 6560 6561 struct iwx_rx_packet { 6562 /* 6563 * The first 4 bytes of the RX frame header contain both the RX frame 6564 * size and some flags. 6565 * Bit fields: 6566 * 31: flag flush RB request 6567 * 30: flag ignore TC (terminal counter) request 6568 * 29: flag fast IRQ request 6569 * 28-26: Reserved 6570 * 25: Offload enabled 6571 * 24: RPF enabled 6572 * 23: RSS enabled 6573 * 22: Checksum enabled 6574 * 21-16: RX queue 6575 * 15-14: Reserved 6576 * 13-00: RX frame size 6577 */ 6578 uint32_t len_n_flags; 6579 struct iwx_cmd_header hdr; 6580 uint8_t data[]; 6581 } __packed; 6582 6583 #define IWX_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6584 #define IWX_FH_RSCSR_FRAME_INVALID 0x55550000 6585 #define IWX_FH_RSCSR_FRAME_ALIGN 0x40 6586 #define IWX_FH_RSCSR_RPA_EN (1 << 25) 6587 #define IWX_FH_RSCSR_RADA_EN (1 << 26) 6588 #define IWX_FH_RSCSR_RXQ_POS 16 6589 #define IWX_FH_RSCSR_RXQ_MASK 0x3F0000 6590 6591 static uint32_t 6592 iwx_rx_packet_len(const struct iwx_rx_packet *pkt) 6593 { 6594 6595 return le32toh(pkt->len_n_flags) & IWX_FH_RSCSR_FRAME_SIZE_MSK; 6596 } 6597 6598 static uint32_t 6599 iwx_rx_packet_payload_len(const struct iwx_rx_packet *pkt) 6600 { 6601 6602 return iwx_rx_packet_len(pkt) - sizeof(pkt->hdr); 6603 } 6604 6605 6606 #define IWX_MIN_DBM -100 6607 #define IWX_MAX_DBM -33 /* realistic guess */ 6608 6609 #define IWX_READ(sc, reg) \ 6610 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6611 6612 #define IWX_WRITE(sc, reg, val) \ 6613 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6614 6615 #define IWX_WRITE_1(sc, reg, val) \ 6616 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6617 6618 #define IWX_SETBITS(sc, reg, mask) \ 6619 IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask)) 6620 6621 #define IWX_CLRBITS(sc, reg, mask) \ 6622 IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask)) 6623 6624 #define IWX_BARRIER_WRITE(sc) \ 6625 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6626 BUS_SPACE_BARRIER_WRITE) 6627 6628 #define IWX_BARRIER_READ_WRITE(sc) \ 6629 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6630 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6631