1 /* $OpenBSD: if_iwxreg.h,v 1.50 2023/03/06 11:08:56 stsp Exp $ */ 2 3 /*- 4 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 5 * which were used as the reference documentation for this implementation. 6 * 7 ****************************************************************************** 8 * 9 * This file is provided under a dual BSD/GPLv2 license. When using or 10 * redistributing this file, you may do so under either license. 11 * 12 * GPL LICENSE SUMMARY 13 * 14 * Copyright(c) 2017 Intel Deutschland GmbH 15 * Copyright(c) 2018 - 2019 Intel Corporation 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of version 2 of the GNU General Public License as 19 * published by the Free Software Foundation. 20 * 21 * This program is distributed in the hope that it will be useful, but 22 * WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 24 * General Public License for more details. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2017 Intel Deutschland GmbH 29 * Copyright(c) 2018 - 2019 Intel Corporation 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 36 * * Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * * Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in 40 * the documentation and/or other materials provided with the 41 * distribution. 42 * * Neither the name Intel Corporation nor the names of its 43 * contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 ***************************************************************************** 59 */ 60 61 62 /* maximum number of DRAM map entries supported by FW */ 63 #define IWX_MAX_DRAM_ENTRY 64 64 #define IWX_CSR_CTXT_INFO_BA 0x40 65 66 /** 67 * enum iwx_context_info_flags - Context information control flags 68 * @IWX_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting 69 * the init done for driver command that configures several system modes 70 * @IWX_CTXT_INFO_EARLY_DEBUG: enable early debug 71 * @IWX_CTXT_INFO_ENABLE_CDMP: enable core dump 72 * @IWX_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size 73 * exponent, the actual size is 2**value, valid sizes are 8-2048. 74 * The value is four bits long. Maximum valid exponent is 12 75 * @IWX_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the 76 * default is short format - not supported by the driver) 77 * @IWX_CTXT_INFO_RB_SIZE_POS: RB size position 78 * (values are IWX_CTXT_INFO_RB_SIZE_*K) 79 * @IWX_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size 80 * @IWX_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size 81 * @IWX_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size 82 * @IWX_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size 83 * @IWX_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size 84 * @IWX_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size 85 * @IWX_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size 86 * @IWX_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size 87 * @IWX_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size 88 * @IWX_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size 89 */ 90 enum iwx_context_info_flags { 91 IWX_CTXT_INFO_AUTO_FUNC_INIT = (1 << 0), 92 IWX_CTXT_INFO_EARLY_DEBUG = (1 << 1), 93 IWX_CTXT_INFO_ENABLE_CDMP = (1 << 2), 94 IWX_CTXT_INFO_RB_CB_SIZE_POS = 4, 95 IWX_CTXT_INFO_TFD_FORMAT_LONG = (1 << 8), 96 IWX_CTXT_INFO_RB_SIZE_POS = 9, 97 IWX_CTXT_INFO_RB_SIZE_1K = 0x1, 98 IWX_CTXT_INFO_RB_SIZE_2K = 0x2, 99 IWX_CTXT_INFO_RB_SIZE_4K = 0x4, 100 IWX_CTXT_INFO_RB_SIZE_8K = 0x8, 101 IWX_CTXT_INFO_RB_SIZE_12K = 0x9, 102 IWX_CTXT_INFO_RB_SIZE_16K = 0xa, 103 IWX_CTXT_INFO_RB_SIZE_20K = 0xb, 104 IWX_CTXT_INFO_RB_SIZE_24K = 0xc, 105 IWX_CTXT_INFO_RB_SIZE_28K = 0xd, 106 IWX_CTXT_INFO_RB_SIZE_32K = 0xe, 107 }; 108 109 /* 110 * struct iwx_context_info_version - version structure 111 * @mac_id: SKU and revision id 112 * @version: context information version id 113 * @size: the size of the context information in DWs 114 */ 115 struct iwx_context_info_version { 116 uint16_t mac_id; 117 uint16_t version; 118 uint16_t size; 119 uint16_t reserved; 120 } __packed; 121 122 /* 123 * struct iwx_context_info_control - version structure 124 * @control_flags: context information flags see &enum iwx_context_info_flags 125 */ 126 struct iwx_context_info_control { 127 uint32_t control_flags; 128 uint32_t reserved; 129 } __packed; 130 131 /* 132 * struct iwx_context_info_dram - images DRAM map 133 * each entry in the map represents a DRAM chunk of up to 32 KB 134 * @umac_img: UMAC image DRAM map 135 * @lmac_img: LMAC image DRAM map 136 * @virtual_img: paged image DRAM map 137 */ 138 struct iwx_context_info_dram { 139 uint64_t umac_img[IWX_MAX_DRAM_ENTRY]; 140 uint64_t lmac_img[IWX_MAX_DRAM_ENTRY]; 141 uint64_t virtual_img[IWX_MAX_DRAM_ENTRY]; 142 } __packed; 143 144 /* 145 * struct iwx_context_info_rbd_cfg - RBDs configuration 146 * @free_rbd_addr: default queue free RB CB base address 147 * @used_rbd_addr: default queue used RB CB base address 148 * @status_wr_ptr: default queue used RB status write pointer 149 */ 150 struct iwx_context_info_rbd_cfg { 151 uint64_t free_rbd_addr; 152 uint64_t used_rbd_addr; 153 uint64_t status_wr_ptr; 154 } __packed; 155 156 /* 157 * struct iwx_context_info_hcmd_cfg - command queue configuration 158 * @cmd_queue_addr: address of command queue 159 * @cmd_queue_size: number of entries 160 */ 161 struct iwx_context_info_hcmd_cfg { 162 uint64_t cmd_queue_addr; 163 uint8_t cmd_queue_size; 164 uint8_t reserved[7]; 165 } __packed; 166 167 /* 168 * struct iwx_context_info_dump_cfg - Core Dump configuration 169 * @core_dump_addr: core dump (debug DRAM address) start address 170 * @core_dump_size: size, in DWs 171 */ 172 struct iwx_context_info_dump_cfg { 173 uint64_t core_dump_addr; 174 uint32_t core_dump_size; 175 uint32_t reserved; 176 } __packed; 177 178 /* 179 * struct iwx_context_info_pnvm_cfg - platform NVM data configuration 180 * @platform_nvm_addr: Platform NVM data start address 181 * @platform_nvm_size: size in DWs 182 */ 183 struct iwx_context_info_pnvm_cfg { 184 uint64_t platform_nvm_addr; 185 uint32_t platform_nvm_size; 186 uint32_t reserved; 187 } __packed; 188 189 /* 190 * struct iwx_context_info_early_dbg_cfg - early debug configuration for 191 * dumping DRAM addresses 192 * @early_debug_addr: early debug start address 193 * @early_debug_size: size in DWs 194 */ 195 struct iwx_context_info_early_dbg_cfg { 196 uint64_t early_debug_addr; 197 uint32_t early_debug_size; 198 uint32_t reserved; 199 } __packed; 200 201 /* 202 * struct iwx_context_info - device INIT configuration 203 * @version: version information of context info and HW 204 * @control: control flags of FH configurations 205 * @rbd_cfg: default RX queue configuration 206 * @hcmd_cfg: command queue configuration 207 * @dump_cfg: core dump data 208 * @edbg_cfg: early debug configuration 209 * @pnvm_cfg: platform nvm configuration 210 * @dram: firmware image addresses in DRAM 211 */ 212 struct iwx_context_info { 213 struct iwx_context_info_version version; 214 struct iwx_context_info_control control; 215 uint64_t reserved0; 216 struct iwx_context_info_rbd_cfg rbd_cfg; 217 struct iwx_context_info_hcmd_cfg hcmd_cfg; 218 uint32_t reserved1[4]; 219 struct iwx_context_info_dump_cfg dump_cfg; 220 struct iwx_context_info_early_dbg_cfg edbg_cfg; 221 struct iwx_context_info_pnvm_cfg pnvm_cfg; 222 uint32_t reserved2[16]; 223 struct iwx_context_info_dram dram; 224 uint32_t reserved3[16]; 225 } __packed; 226 227 228 /* 229 * Context info definitions for AX210 devices. 230 */ 231 232 #define IWX_CSR_CTXT_INFO_BOOT_CTRL 0x0 233 #define IWX_CSR_CTXT_INFO_ADDR 0x118 234 #define IWX_CSR_IML_DATA_ADDR 0x120 235 #define IWX_CSR_IML_SIZE_ADDR 0x128 236 #define IWX_CSR_IML_RESP_ADDR 0x12c 237 238 /* Set bit for enabling automatic function boot */ 239 #define IWX_CSR_AUTO_FUNC_BOOT_ENA (1 << 1) 240 /* Set bit for initiating function boot */ 241 #define IWX_CSR_AUTO_FUNC_INIT (1 << 7) 242 243 /** 244 * iwx_prph_scratch_mtr_format - tfd size configuration 245 * @IWX_PRPH_MTR_FORMAT_16B: 16 bit tfd 246 * @IWX_PRPH_MTR_FORMAT_32B: 32 bit tfd 247 * @IWX_PRPH_MTR_FORMAT_64B: 64 bit tfd 248 * @IWX_PRPH_MTR_FORMAT_256B: 256 bit tfd 249 */ 250 #define IWX_PRPH_MTR_FORMAT_16B 0x0 251 #define IWX_PRPH_MTR_FORMAT_32B 0x40000 252 #define IWX_PRPH_MTR_FORMAT_64B 0x80000 253 #define IWX_PRPH_MTR_FORMAT_256B 0xC0000 254 255 /** 256 * iwx_prph_scratch_flags - PRPH scratch control flags 257 * @IWX_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug 258 * @IWX_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf 259 * @IWX_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated 260 * in hwm config. 261 * @IWX_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM 262 * @IWX_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for 263 * multicomm. 264 * @IWX_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW 265 * @IWX_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K) 266 * @IWX_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for 267 * completion descriptor, 1 for responses (legacy) 268 * @IWX_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd. 269 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit, 270 * 3: 256 bit. 271 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored 272 * by older firmware versions, so set IWX_PRPH_SCRATCH_RB_SIZE_4K 273 * appropriately; use the below values for this. 274 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size 275 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size 276 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size 277 */ 278 #define IWX_PRPH_SCRATCH_IMR_DEBUG_EN (1 << 1) 279 #define IWX_PRPH_SCRATCH_EARLY_DEBUG_EN (1 << 4) 280 #define IWX_PRPH_SCRATCH_EDBG_DEST_DRAM (1 << 8) 281 #define IWX_PRPH_SCRATCH_EDBG_DEST_INTERNAL (1 << 9) 282 #define IWX_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER (1 << 10) 283 #define IWX_PRPH_SCRATCH_EDBG_DEST_TB22DTF (1 << 11) 284 #define IWX_PRPH_SCRATCH_RB_SIZE_4K (1 << 16) 285 #define IWX_PRPH_SCRATCH_MTR_MODE (1 << 17) 286 #define IWX_PRPH_SCRATCH_MTR_FORMAT ((1 << 18) | (1 << 19)) 287 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_MASK (0xf << 20) 288 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_8K (8 << 20) 289 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_12K (9 << 20) 290 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_16K (10 << 20) 291 292 /* 293 * struct iwx_prph_scratch_version - version structure 294 * @mac_id: SKU and revision id 295 * @version: prph scratch information version id 296 * @size: the size of the context information in DWs 297 * @reserved: reserved 298 */ 299 struct iwx_prph_scratch_version { 300 uint16_t mac_id; 301 uint16_t version; 302 uint16_t size; 303 uint16_t reserved; 304 } __packed; /* PERIPH_SCRATCH_VERSION_S */ 305 306 /* 307 * struct iwx_prph_scratch_control - control structure 308 * @control_flags: context information flags see &iwx_prph_scratch_flags 309 * @reserved: reserved 310 */ 311 struct iwx_prph_scratch_control { 312 uint32_t control_flags; 313 uint32_t reserved; 314 } __packed; /* PERIPH_SCRATCH_CONTROL_S */ 315 316 /* 317 * struct iwx_prph_scratch_pnvm_cfg - ror config 318 * @pnvm_base_addr: PNVM start address 319 * @pnvm_size: PNVM size in DWs 320 * @reserved: reserved 321 */ 322 struct iwx_prph_scratch_pnvm_cfg { 323 uint64_t pnvm_base_addr; 324 uint32_t pnvm_size; 325 uint32_t reserved; 326 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */ 327 328 struct iwx_pnvm_section { 329 uint32_t offset; 330 const uint8_t data[]; 331 } __packed; 332 333 /* 334 * struct iwx_prph_scratch_hwm_cfg - hwm config 335 * @hwm_base_addr: hwm start address 336 * @hwm_size: hwm size in DWs 337 * @debug_token_config: debug preset 338 */ 339 struct iwx_prph_scratch_hwm_cfg { 340 uint64_t hwm_base_addr; 341 uint32_t hwm_size; 342 uint32_t debug_token_config; 343 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */ 344 345 /* 346 * struct iwx_prph_scratch_rbd_cfg - RBDs configuration 347 * @free_rbd_addr: default queue free RB CB base address 348 * @reserved: reserved 349 */ 350 struct iwx_prph_scratch_rbd_cfg { 351 uint64_t free_rbd_addr; 352 uint32_t reserved; 353 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */ 354 355 /* 356 * struct iwx_prph_scratch_uefi_cfg - prph scratch reduce power table 357 * @base_addr: reduce power table address 358 * @size: table size in dwords 359 */ 360 struct iwx_prph_scratch_uefi_cfg { 361 uint64_t base_addr; 362 uint32_t size; 363 uint32_t reserved; 364 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */ 365 366 /* 367 * struct iwx_prph_scratch_ctrl_cfg - prph scratch ctrl and config 368 * @version: version information of context info and HW 369 * @control: control flags of FH configurations 370 * @pnvm_cfg: ror configuration 371 * @hwm_cfg: hwm configuration 372 * @rbd_cfg: default RX queue configuration 373 */ 374 struct iwx_prph_scratch_ctrl_cfg { 375 struct iwx_prph_scratch_version version; 376 struct iwx_prph_scratch_control control; 377 struct iwx_prph_scratch_pnvm_cfg pnvm_cfg; 378 struct iwx_prph_scratch_hwm_cfg hwm_cfg; 379 struct iwx_prph_scratch_rbd_cfg rbd_cfg; 380 struct iwx_prph_scratch_uefi_cfg reduce_power_cfg; 381 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */ 382 383 /* 384 * struct iwx_prph_scratch - peripheral scratch mapping 385 * @ctrl_cfg: control and configuration of prph scratch 386 * @dram: firmware images addresses in DRAM 387 * @reserved: reserved 388 */ 389 struct iwx_prph_scratch { 390 struct iwx_prph_scratch_ctrl_cfg ctrl_cfg; 391 uint32_t reserved[12]; 392 struct iwx_context_info_dram dram; 393 } __packed; /* PERIPH_SCRATCH_S */ 394 395 /* 396 * struct iwx_prph_info - peripheral information 397 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register 398 * @ipc_status_mirror: reflects the value in the IPC Status CSR register 399 * @sleep_notif: indicates the peripheral sleep status 400 * @reserved: reserved 401 */ 402 struct iwx_prph_info { 403 uint32_t boot_stage_mirror; 404 uint32_t ipc_status_mirror; 405 uint32_t sleep_notif; 406 uint32_t reserved; 407 } __packed; /* PERIPH_INFO_S */ 408 409 /* 410 * struct iwx_context_info_gen3 - device INIT configuration 411 * @version: version of the context information 412 * @size: size of context information in DWs 413 * @config: context in which the peripheral would execute - a subset of 414 * capability csr register published by the peripheral 415 * @prph_info_base_addr: the peripheral information structure start address 416 * @cr_head_idx_arr_base_addr: the completion ring head index array 417 * start address 418 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array 419 * start address 420 * @cr_tail_idx_arr_base_addr: the completion ring tail index array 421 * start address 422 * @tr_head_idx_arr_base_addr: the transfer ring head index array 423 * start address 424 * @cr_idx_arr_size: number of entries in the completion ring index array 425 * @tr_idx_arr_size: number of entries in the transfer ring index array 426 * @mtr_base_addr: the message transfer ring start address 427 * @mcr_base_addr: the message completion ring start address 428 * @mtr_size: number of entries which the message transfer ring can hold 429 * @mcr_size: number of entries which the message completion ring can hold 430 * @mtr_doorbell_vec: the doorbell vector associated with the message 431 * transfer ring 432 * @mcr_doorbell_vec: the doorbell vector associated with the message 433 * completion ring 434 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after 435 * completing a transfer descriptor in the message transfer ring 436 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after 437 * completing a completion descriptor in the message completion ring 438 * @mtr_opt_header_size: the size of the optional header in the transfer 439 * descriptor associated with the message transfer ring in DWs 440 * @mtr_opt_footer_size: the size of the optional footer in the transfer 441 * descriptor associated with the message transfer ring in DWs 442 * @mcr_opt_header_size: the size of the optional header in the completion 443 * descriptor associated with the message completion ring in DWs 444 * @mcr_opt_footer_size: the size of the optional footer in the completion 445 * descriptor associated with the message completion ring in DWs 446 * @msg_rings_ctrl_flags: message rings control flags 447 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral 448 * after updating the Peripheral Information structure 449 * @prph_scratch_base_addr: the peripheral scratch structure start address 450 * @prph_scratch_size: the size of the peripheral scratch structure in DWs 451 * @reserved: reserved 452 */ 453 struct iwx_context_info_gen3 { 454 uint16_t version; 455 uint16_t size; 456 uint32_t config; 457 uint64_t prph_info_base_addr; 458 uint64_t cr_head_idx_arr_base_addr; 459 uint64_t tr_tail_idx_arr_base_addr; 460 uint64_t cr_tail_idx_arr_base_addr; 461 uint64_t tr_head_idx_arr_base_addr; 462 uint16_t cr_idx_arr_size; 463 uint16_t tr_idx_arr_size; 464 uint64_t mtr_base_addr; 465 uint64_t mcr_base_addr; 466 uint16_t mtr_size; 467 uint16_t mcr_size; 468 uint16_t mtr_doorbell_vec; 469 uint16_t mcr_doorbell_vec; 470 uint16_t mtr_msi_vec; 471 uint16_t mcr_msi_vec; 472 uint8_t mtr_opt_header_size; 473 uint8_t mtr_opt_footer_size; 474 uint8_t mcr_opt_header_size; 475 uint8_t mcr_opt_footer_size; 476 uint16_t msg_rings_ctrl_flags; 477 uint16_t prph_info_msi_vec; 478 uint64_t prph_scratch_base_addr; 479 uint32_t prph_scratch_size; 480 uint32_t reserved; 481 } __packed; /* IPC_CONTEXT_INFO_S */ 482 483 #define IWX_MGMT_TID 15 484 485 #define IWX_MQ_RX_TABLE_SIZE 512 486 487 /* cb size is the exponent */ 488 #define IWX_RX_QUEUE_CB_SIZE(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1)) 489 490 /* 491 * CSR (control and status registers) 492 * 493 * CSR registers are mapped directly into PCI bus space, and are accessible 494 * whenever platform supplies power to device, even when device is in 495 * low power states due to driver-invoked device resets 496 * (e.g. IWX_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 497 * 498 * Use iwl_write32() and iwl_read32() family to access these registers; 499 * these provide simple PCI bus access, without waking up the MAC. 500 * Do not use iwl_write_direct32() family for these registers; 501 * no need to "grab nic access" via IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 502 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 503 * the CSR registers. 504 * 505 * NOTE: Device does need to be awake in order to read this memory 506 * via IWX_CSR_EEPROM and IWX_CSR_OTP registers 507 */ 508 #define IWX_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 509 #define IWX_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 510 #define IWX_CSR_INT (0x008) /* host interrupt status/ack */ 511 #define IWX_CSR_INT_MASK (0x00c) /* host interrupt enable */ 512 #define IWX_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 513 #define IWX_CSR_GPIO_IN (0x018) /* read external chip pins */ 514 #define IWX_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 515 #define IWX_CSR_GP_CNTRL (0x024) 516 517 /* 2nd byte of IWX_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 518 #define IWX_CSR_INT_PERIODIC_REG (0x005) 519 520 /* 521 * Hardware revision info 522 * Bit fields: 523 * 31-16: Reserved 524 * 15-4: Type of device: see IWX_CSR_HW_REV_TYPE_xxx definitions 525 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 526 * 1-0: "Dash" (-) value, as in A-1, etc. 527 */ 528 #define IWX_CSR_HW_REV (0x028) 529 530 /* 531 * RF ID revision info 532 * Bit fields: 533 * 31:24: Reserved (set to 0x0) 534 * 23:12: Type 535 * 11:8: Step (A - 0x0, B - 0x1, etc) 536 * 7:4: Dash 537 * 3:0: Flavor 538 */ 539 #define IWX_CSR_HW_RF_ID (0x09c) 540 541 542 #define IWX_CSR_GIO_REG (0x03C) 543 544 /* 545 * UCODE-DRIVER GP (general purpose) mailbox registers. 546 * SET/CLR registers set/clear bit(s) if "1" is written. 547 */ 548 #define IWX_CSR_UCODE_DRV_GP1 (0x054) 549 #define IWX_CSR_UCODE_DRV_GP1_SET (0x058) 550 #define IWX_CSR_UCODE_DRV_GP1_CLR (0x05c) 551 #define IWX_CSR_UCODE_DRV_GP2 (0x060) 552 553 #define IWX_CSR_MBOX_SET_REG (0x088) 554 #define IWX_CSR_MBOX_SET_REG_OS_ALIVE 0x20 555 556 #define IWX_CSR_DRAM_INT_TBL_REG (0x0A0) 557 #define IWX_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 558 559 /* LTR control */ 560 #define IWX_CSR_LTR_LONG_VAL_AD (0x0d4) 561 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000 562 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_MASK 0x1c000000 563 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_SHIFT 24 564 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_MASK 0x03ff0000 565 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_SHIFT 16 566 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000 567 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_MASK 0x00001c00 568 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_SHIFT 8 569 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff 570 #define IWX_CSR_LTR_LONG_VAL_AD_SCALE_USEC 2 571 572 /* GIO Chicken Bits (PCI Express bus link power management) */ 573 #define IWX_CSR_GIO_CHICKEN_BITS (0x100) 574 575 #define IWX_CSR_DBG_HPET_MEM_REG (0x240) 576 #define IWX_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 577 578 /* Bits for IWX_CSR_HW_IF_CONFIG_REG */ 579 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 580 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 581 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 582 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 583 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 584 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 585 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 586 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 587 588 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 589 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 590 #define IWX_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 591 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 592 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 593 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 594 595 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 596 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 597 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 598 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 599 #define IWX_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 600 #define IWX_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 601 #define IWX_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 602 603 #define IWX_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 604 #define IWX_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 605 606 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 607 * acknowledged (reset) by host writing "1" to flagged bits. */ 608 #define IWX_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 609 #define IWX_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 610 #define IWX_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 611 #define IWX_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 612 #define IWX_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 613 #define IWX_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 614 #define IWX_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 615 #define IWX_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 616 #define IWX_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 617 #define IWX_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 618 #define IWX_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 619 620 #define IWX_CSR_INI_SET_MASK (IWX_CSR_INT_BIT_FH_RX | \ 621 IWX_CSR_INT_BIT_HW_ERR | \ 622 IWX_CSR_INT_BIT_FH_TX | \ 623 IWX_CSR_INT_BIT_SW_ERR | \ 624 IWX_CSR_INT_BIT_RF_KILL | \ 625 IWX_CSR_INT_BIT_SW_RX | \ 626 IWX_CSR_INT_BIT_WAKEUP | \ 627 IWX_CSR_INT_BIT_ALIVE | \ 628 IWX_CSR_INT_BIT_RX_PERIODIC) 629 630 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 631 #define IWX_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ 632 #define IWX_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 633 #define IWX_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 634 #define IWX_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 635 #define IWX_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 636 #define IWX_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 637 638 #define IWX_CSR_FH_INT_RX_MASK (IWX_CSR_FH_INT_BIT_HI_PRIOR | \ 639 IWX_CSR_FH_INT_BIT_RX_CHNL1 | \ 640 IWX_CSR_FH_INT_BIT_RX_CHNL0) 641 642 #define IWX_CSR_FH_INT_TX_MASK (IWX_CSR_FH_INT_BIT_TX_CHNL1 | \ 643 IWX_CSR_FH_INT_BIT_TX_CHNL0) 644 645 /** 646 * struct iwx_rx_transfer_desc - transfer descriptor AX210 647 * @addr: ptr to free buffer start address 648 * @rbid: unique tag of the buffer 649 * @reserved: reserved 650 */ 651 struct iwx_rx_transfer_desc { 652 uint16_t rbid; 653 uint16_t reserved[3]; 654 uint64_t addr; 655 }; 656 657 #define IWX_RX_CD_FLAGS_FRAGMENTED (1 << 0) 658 659 /** 660 * struct iwx_rx_completion_desc - completion descriptor AX210 661 * @reserved1: reserved 662 * @rbid: unique tag of the received buffer 663 * @flags: flags (0: fragmented, all others: reserved) 664 * @reserved2: reserved 665 */ 666 struct iwx_rx_completion_desc { 667 uint32_t reserved1; 668 uint16_t rbid; 669 uint8_t flags; 670 uint8_t reserved2[25]; 671 }; 672 673 /* RESET */ 674 #define IWX_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 675 #define IWX_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 676 #define IWX_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 677 #define IWX_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 678 #define IWX_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 679 #define IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 680 681 /* 682 * GP (general purpose) CONTROL REGISTER 683 * Bit fields: 684 * 27: HW_RF_KILL_SW 685 * Indicates state of (platform's) hardware RF-Kill switch 686 * 26-24: POWER_SAVE_TYPE 687 * Indicates current power-saving mode: 688 * 000 -- No power saving 689 * 001 -- MAC power-down 690 * 010 -- PHY (radio) power-down 691 * 011 -- Error 692 * 9-6: SYS_CONFIG 693 * Indicates current system configuration, reflecting pins on chip 694 * as forced high/low by device circuit board. 695 * 4: GOING_TO_SLEEP 696 * Indicates MAC is entering a power-saving sleep power-down. 697 * Not a good time to access device-internal resources. 698 * 3: MAC_ACCESS_REQ 699 * Host sets this to request and maintain MAC wakeup, to allow host 700 * access to device-internal resources. Host must wait for 701 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 702 * device registers. 703 * 2: INIT_DONE 704 * Host sets this to put device into fully operational D0 power mode. 705 * Host resets this after SW_RESET to put device into low power mode. 706 * 0: MAC_CLOCK_READY 707 * Indicates MAC (ucode processor, etc.) is powered up and can run. 708 * Internal resources are accessible. 709 * NOTE: This does not indicate that the processor is actually running. 710 * NOTE: This does not indicate that device has completed 711 * init or post-power-down restore of internal SRAM memory. 712 * Use IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 713 * SRAM is restored and uCode is in normal operation mode. 714 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 715 * do not need to save/restore it. 716 * NOTE: After device reset, this bit remains "0" until host sets 717 * INIT_DONE 718 */ 719 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 720 #define IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 721 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 722 #define IWX_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 723 724 #define IWX_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 725 726 #define IWX_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 727 #define IWX_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 728 #define IWX_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 729 730 731 /* HW REV */ 732 #define IWX_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 733 #define IWX_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 734 #define IWX_CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4) 735 736 #define IWX_CSR_HW_REV_TYPE_MSK (0x000FFF0) 737 #define IWX_CSR_HW_REV_TYPE_QU_B0 (0x0000334) 738 #define IWX_CSR_HW_REV_TYPE_QU_C0 (0x0000338) 739 #define IWX_CSR_HW_REV_TYPE_QUZ (0x0000354) 740 #define IWX_CSR_HW_REV_TYPE_SO (0x0000370) 741 #define IWX_CSR_HW_REV_TYPE_TY (0x0000420) 742 743 /* HW RFID */ 744 #define IWX_CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) 745 #define IWX_CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) 746 #define IWX_CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) 747 #define IWX_CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) 748 #define IWX_CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28) 749 #define IWX_CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29) 750 751 /* CSR GIO */ 752 #define IWX_CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) 753 754 /* 755 * UCODE-DRIVER GP (general purpose) mailbox register 1 756 * Host driver and uCode write and/or read this register to communicate with 757 * each other. 758 * Bit fields: 759 * 4: UCODE_DISABLE 760 * Host sets this to request permanent halt of uCode, same as 761 * sending CARD_STATE command with "halt" bit set. 762 * 3: CT_KILL_EXIT 763 * Host sets this to request exit from CT_KILL state, i.e. host thinks 764 * device temperature is low enough to continue normal operation. 765 * 2: CMD_BLOCKED 766 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 767 * to release uCode to clear all Tx and command queues, enter 768 * unassociated mode, and power down. 769 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 770 * 1: SW_BIT_RFKILL 771 * Host sets this when issuing CARD_STATE command to request 772 * device sleep. 773 * 0: MAC_SLEEP 774 * uCode sets this when preparing a power-saving power-down. 775 * uCode resets this when power-up is complete and SRAM is sane. 776 * NOTE: device saves internal SRAM data to host when powering down, 777 * and must restore this data after powering back up. 778 * MAC_SLEEP is the best indication that restore is complete. 779 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 780 * do not need to save/restore it. 781 */ 782 #define IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 783 #define IWX_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 784 #define IWX_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 785 #define IWX_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 786 #define IWX_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 787 788 /* GIO Chicken Bits (PCI Express bus link power management) */ 789 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 790 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 791 792 /* HPET MEM debug */ 793 #define IWX_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 794 795 /* DRAM INT TABLE */ 796 #define IWX_CSR_DRAM_INT_TBL_ENABLE (1U << 31) 797 #define IWX_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 798 #define IWX_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 799 800 /* 22000 configuration registers */ 801 802 /* 803 * TFH Configuration register. 804 * 805 * BIT fields: 806 * 807 * Bits 3:0: 808 * Define the maximum number of pending read requests. 809 * Maximum configuration value allowed is 0xC 810 * Bits 9:8: 811 * Define the maximum transfer size. (64 / 128 / 256) 812 * Bit 10: 813 * When bit is set and transfer size is set to 128B, the TFH will enable 814 * reading chunks of more than 64B only if the read address is aligned to 128B. 815 * In case of DRAM read address which is not aligned to 128B, the TFH will 816 * enable transfer size which doesn't cross 64B DRAM address boundary. 817 */ 818 #define IWX_TFH_TRANSFER_MODE (0x1F40) 819 #define IWX_TFH_TRANSFER_MAX_PENDING_REQ 0xc 820 #define IWX_TFH_CHUNK_SIZE_128 (1 << 8) 821 #define IWX_TFH_CHUNK_SPLIT_MODE (1 << 10) 822 823 /* 824 * Defines the offset address in dwords referring from the beginning of the 825 * Tx CMD which will be updated in DRAM. 826 * Note that the TFH offset address for Tx CMD update is always referring to 827 * the start of the TFD first TB. 828 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID 829 */ 830 #define IWX_TFH_TXCMD_UPDATE_CFG (0x1F48) 831 832 /* 833 * Controls TX DMA operation 834 * 835 * BIT fields: 836 * 837 * Bits 31:30: Enable the SRAM DMA channel. 838 * Turning on bit 31 will kick the SRAM2DRAM DMA. 839 * Note that the sram2dram may be enabled only after configuring the DRAM and 840 * SRAM addresses registers and the byte count register. 841 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When 842 * set to 1 - interrupt is sent to the driver 843 * Bit 0: Indicates the snoop configuration 844 */ 845 #define IWX_TFH_SRV_DMA_CHNL0_CTRL (0x1F60) 846 #define IWX_TFH_SRV_DMA_SNOOP (1 << 0) 847 #define IWX_TFH_SRV_DMA_TO_DRIVER (1 << 24) 848 #define IWX_TFH_SRV_DMA_START (1U << 31) 849 850 /* Defines the DMA SRAM write start address to transfer a data block */ 851 #define IWX_TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64) 852 853 /* Defines the 64bits DRAM start address to read the DMA data block from */ 854 #define IWX_TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68) 855 856 /* 857 * Defines the number of bytes to transfer from DRAM to SRAM. 858 * Note that this register may be configured with non-dword aligned size. 859 */ 860 #define IWX_TFH_SRV_DMA_CHNL0_BC (0x1F70) 861 862 /* 9000 rx series registers */ 863 864 #define IWX_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 865 #define IWX_RFH_Q_FRBDCB_BA_LSB(q) (IWX_RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 866 /* Write index table */ 867 #define IWX_RFH_Q0_FRBDCB_WIDX 0xA08080 868 #define IWX_RFH_Q_FRBDCB_WIDX(q) (IWX_RFH_Q0_FRBDCB_WIDX + (q) * 4) 869 /* Write index table - shadow registers */ 870 #define IWX_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 871 #define IWX_RFH_Q_FRBDCB_WIDX_TRG(q) (IWX_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 872 /* Read index table */ 873 #define IWX_RFH_Q0_FRBDCB_RIDX 0xA080C0 874 #define IWX_RFH_Q_FRBDCB_RIDX(q) (IWX_RFH_Q0_FRBDCB_RIDX + (q) * 4) 875 /* Used list table */ 876 #define IWX_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 877 #define IWX_RFH_Q_URBDCB_BA_LSB(q) (IWX_RFH_Q0_URBDCB_BA_LSB + (q) * 8) 878 /* Write index table */ 879 #define IWX_RFH_Q0_URBDCB_WIDX 0xA08180 880 #define IWX_RFH_Q_URBDCB_WIDX(q) (IWX_RFH_Q0_URBDCB_WIDX + (q) * 4) 881 #define IWX_RFH_Q0_URBDCB_VAID 0xA081C0 882 #define IWX_RFH_Q_URBDCB_VAID(q) (IWX_RFH_Q0_URBDCB_VAID + (q) * 4) 883 /* stts */ 884 #define IWX_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 885 #define IWX_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWX_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 886 887 #define IWX_RFH_Q0_ORB_WPTR_LSB 0xA08280 888 #define IWX_RFH_Q_ORB_WPTR_LSB(q) (IWX_RFH_Q0_ORB_WPTR_LSB + (q) * 8) 889 #define IWX_RFH_RBDBUF_RBD0_LSB 0xA08300 890 #define IWX_RFH_RBDBUF_RBD_LSB(q) (IWX_RFH_RBDBUF_RBD0_LSB + (q) * 8) 891 892 /** 893 * RFH Status Register 894 * 895 * Bit fields: 896 * 897 * Bit 29: RBD_FETCH_IDLE 898 * This status flag is set by the RFH when there is no active RBD fetch from 899 * DRAM. 900 * Once the RFH RBD controller starts fetching (or when there is a pending 901 * RBD read response from DRAM), this flag is immediately turned off. 902 * 903 * Bit 30: SRAM_DMA_IDLE 904 * This status flag is set by the RFH when there is no active transaction from 905 * SRAM to DRAM. 906 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 907 * 908 * Bit 31: RXF_DMA_IDLE 909 * This status flag is set by the RFH when there is no active transaction from 910 * RXF to DRAM. 911 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 912 */ 913 #define IWX_RFH_GEN_STATUS 0xA09808 914 #define IWX_RFH_GEN_STATUS_GEN3 0xA07824 915 #define IWX_RBD_FETCH_IDLE (1 << 29) 916 #define IWX_SRAM_DMA_IDLE (1 << 30) 917 #define IWX_RXF_DMA_IDLE (1U << 31) 918 919 /* DMA configuration */ 920 #define IWX_RFH_RXF_DMA_CFG 0xA09820 921 #define IWX_RFH_RXF_DMA_CFG_GEN3 0xA07880 922 /* RB size */ 923 #define IWX_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 924 #define IWX_RFH_RXF_DMA_RB_SIZE_POS 16 925 #define IWX_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 926 #define IWX_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 927 #define IWX_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 928 #define IWX_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 929 #define IWX_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 930 #define IWX_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWX_RFH_RXF_DMA_RB_SIZE_POS) 931 #define IWX_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWX_RFH_RXF_DMA_RB_SIZE_POS) 932 #define IWX_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWX_RFH_RXF_DMA_RB_SIZE_POS) 933 #define IWX_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWX_RFH_RXF_DMA_RB_SIZE_POS) 934 #define IWX_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWX_RFH_RXF_DMA_RB_SIZE_POS) 935 /* RB Circular Buffer size:defines the table sizes in RBD units */ 936 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 937 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_POS 20 938 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 939 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 940 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 941 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 942 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 943 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 944 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 945 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 946 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 947 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 948 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS 24 949 #define IWX_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS) 950 #define IWX_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 951 #define IWX_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 952 #define IWX_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 953 #define IWX_RFH_DMA_EN_ENABLE_VAL (1U << 31) 954 955 #define IWX_RFH_RXF_RXQ_ACTIVE 0xA0980C 956 957 #define IWX_RFH_GEN_CFG 0xA09800 958 #define IWX_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0) 959 #define IWX_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1) 960 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010 961 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000 962 /* the driver assumes everywhere that the default RXQ is 0 */ 963 #define IWX_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 964 965 /* end of 9000 rx series registers */ 966 967 /* 968 * This register is written by driver and is read by uCode during boot flow. 969 * Note this address is cleared after MAC reset. 970 */ 971 #define IWX_UREG_UCODE_LOAD_STATUS (0xa05c40) 972 #define IWX_UREG_CPU_INIT_RUN (0xa05c44) 973 974 /* 975 * HBUS (Host-side Bus) 976 * 977 * HBUS registers are mapped directly into PCI bus space, but are used 978 * to indirectly access device's internal memory or registers that 979 * may be powered-down. 980 * 981 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 982 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 983 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 984 * internal resources. 985 * 986 * Do not use iwl_write32()/iwl_read32() family to access these registers; 987 * these provide only simple PCI bus access, without waking up the MAC. 988 */ 989 #define IWX_HBUS_BASE (0x400) 990 991 /* 992 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 993 * structures, error log, event log, verifying uCode load). 994 * First write to address register, then read from or write to data register 995 * to complete the job. Once the address register is set up, accesses to 996 * data registers auto-increment the address by one dword. 997 * Bit usage for address registers (read or write): 998 * 0-31: memory address within device 999 */ 1000 #define IWX_HBUS_TARG_MEM_RADDR (IWX_HBUS_BASE+0x00c) 1001 #define IWX_HBUS_TARG_MEM_WADDR (IWX_HBUS_BASE+0x010) 1002 #define IWX_HBUS_TARG_MEM_WDAT (IWX_HBUS_BASE+0x018) 1003 #define IWX_HBUS_TARG_MEM_RDAT (IWX_HBUS_BASE+0x01c) 1004 1005 /* 1006 * Registers for accessing device's internal peripheral registers 1007 * (e.g. SCD, BSM, etc.). First write to address register, 1008 * then read from or write to data register to complete the job. 1009 * Bit usage for address registers (read or write): 1010 * 0-15: register address (offset) within device 1011 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 1012 */ 1013 #define IWX_HBUS_TARG_PRPH_WADDR (IWX_HBUS_BASE+0x044) 1014 #define IWX_HBUS_TARG_PRPH_RADDR (IWX_HBUS_BASE+0x048) 1015 #define IWX_HBUS_TARG_PRPH_WDAT (IWX_HBUS_BASE+0x04c) 1016 #define IWX_HBUS_TARG_PRPH_RDAT (IWX_HBUS_BASE+0x050) 1017 1018 /* enable the ID buf for read */ 1019 #define IWX_WFPM_PS_CTL_CLR 0xa0300c 1020 #define IWX_WFMP_MAC_ADDR_0 0xa03080 1021 #define IWX_WFMP_MAC_ADDR_1 0xa03084 1022 #define IWX_LMPM_PMG_EN 0xa01cec 1023 #define IWX_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 1024 #define IWX_RFIC_REG_RD 0xad0470 1025 #define IWX_WFPM_CTRL_REG 0xa03030 1026 #define IWX_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 1027 #define IWX_ENABLE_WFPM 0x80000000 1028 1029 #define IWX_AUX_MISC_MASTER1_EN 0xa20818 1030 #define IWX_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 1031 #define IWX_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 1032 #define IWX_RSA_ENABLE 0xa24b08 1033 #define IWX_PREG_AUX_BUS_WPROT_0 0xa04cc0 1034 #define IWX_PREG_PRPH_WPROT_9000 0xa04ce0 1035 #define IWX_PREG_PRPH_WPROT_22000 0xa04d00 1036 #define IWX_SB_CFG_OVERRIDE_ADDR 0xa26c78 1037 #define IWX_SB_CFG_OVERRIDE_ENABLE 0x8000 1038 #define IWX_SB_CFG_BASE_OVERRIDE 0xa20000 1039 #define IWX_SB_MODIFY_CFG_FLAG 0xa03088 1040 #define IWX_UMAG_SB_CPU_1_STATUS 0xa038c0 1041 #define IWX_UMAG_SB_CPU_2_STATUS 0xa038c4 1042 1043 #define IWX_UREG_CHICK 0xa05c00 1044 #define IWX_UREG_CHICK_MSI_ENABLE (1 << 24) 1045 #define IWX_UREG_CHICK_MSIX_ENABLE (1 << 25) 1046 1047 #define IWX_HPM_DEBUG 0xa03440 1048 #define IWX_PERSISTENCE_BIT (1 << 12) 1049 #define IWX_PREG_WFPM_ACCESS (1 << 12) 1050 1051 #define IWX_HPM_HIPM_GEN_CFG 0xa03458 1052 #define IWX_HPM_HIPM_GEN_CFG_CR_PG_EN (1 << 0) 1053 #define IWX_HPM_HIPM_GEN_CFG_CR_SLP_EN (1 << 1) 1054 #define IWX_HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE (1 << 10) 1055 1056 #define IWX_UREG_DOORBELL_TO_ISR6 0xa05c04 1057 #define IWX_UREG_DOORBELL_TO_ISR6_NMI_BIT (1 << 0) 1058 #define IWX_UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE ((1 << 0) | (1 << 1)) 1059 #define IWX_UREG_DOORBELL_TO_ISR6_SUSPEND (1 << 18) 1060 #define IWX_UREG_DOORBELL_TO_ISR6_RESUME (1 << 19) 1061 #define IWX_UREG_DOORBELL_TO_ISR6_PNVM (1 << 20) 1062 1063 /* LTR control (Qu only) */ 1064 #define IWX_HPM_MAC_LTR_CSR 0xa0348c 1065 #define IWX_HPM_MAC_LRT_ENABLE_ALL 0xf 1066 /* also uses CSR_LTR_* for values */ 1067 #define IWX_HPM_UMAC_LTR 0xa03480 1068 1069 /* 1070 * Per-Tx-queue write pointer (index, really!) 1071 * Indicates index to next TFD that driver will fill (1 past latest filled). 1072 * Bit usage: 1073 * 0-7: queue write index 1074 * 11-8: queue selector 1075 */ 1076 #define IWX_HBUS_TARG_WRPTR (IWX_HBUS_BASE+0x060) 1077 1078 /********************************************************** 1079 * CSR values 1080 **********************************************************/ 1081 /* 1082 * host interrupt timeout value 1083 * used with setting interrupt coalescing timer 1084 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 1085 * 1086 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 1087 */ 1088 #define IWX_HOST_INT_TIMEOUT_MAX (0xFF) 1089 #define IWX_HOST_INT_TIMEOUT_DEF (0x40) 1090 #define IWX_HOST_INT_TIMEOUT_MIN (0x0) 1091 #define IWX_HOST_INT_OPER_MODE (1U << 31) 1092 1093 /***************************************************************************** 1094 * MSIX related registers * 1095 *****************************************************************************/ 1096 1097 #define IWX_CSR_MSIX_BASE (0x2000) 1098 #define IWX_CSR_MSIX_FH_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x800) 1099 #define IWX_CSR_MSIX_FH_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x804) 1100 #define IWX_CSR_MSIX_HW_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x808) 1101 #define IWX_CSR_MSIX_HW_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x80C) 1102 #define IWX_CSR_MSIX_AUTOMASK_ST_AD (IWX_CSR_MSIX_BASE + 0x810) 1103 #define IWX_CSR_MSIX_RX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x880) 1104 #define IWX_CSR_MSIX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x890) 1105 #define IWX_CSR_MSIX_PENDING_PBA_AD (IWX_CSR_MSIX_BASE + 0x1000) 1106 #define IWX_CSR_MSIX_RX_IVAR(cause) (IWX_CSR_MSIX_RX_IVAR_AD_REG + (cause)) 1107 #define IWX_CSR_MSIX_IVAR(cause) (IWX_CSR_MSIX_IVAR_AD_REG + (cause)) 1108 1109 /* 1110 * Causes for the FH register interrupts 1111 */ 1112 enum msix_fh_int_causes { 1113 IWX_MSIX_FH_INT_CAUSES_Q0 = (1 << 0), 1114 IWX_MSIX_FH_INT_CAUSES_Q1 = (1 << 1), 1115 IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16), 1116 IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17), 1117 IWX_MSIX_FH_INT_CAUSES_S2D = (1 << 19), 1118 IWX_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21), 1119 }; 1120 1121 /* 1122 * Causes for the HW register interrupts 1123 */ 1124 enum mix_hw_int_causes { 1125 IWX_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0), 1126 IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1), 1127 IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE = (1 << 2), 1128 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5), 1129 IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6), 1130 IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7), 1131 IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8), 1132 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25), 1133 IWX_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26), 1134 IWX_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27), 1135 IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29), 1136 IWX_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30), 1137 }; 1138 1139 /* 1140 * Registers to map causes to vectors 1141 */ 1142 enum msix_ivar_for_cause { 1143 IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0, 1144 IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1, 1145 IWX_MSIX_IVAR_CAUSE_S2D = 0x3, 1146 IWX_MSIX_IVAR_CAUSE_FH_ERR = 0x5, 1147 IWX_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10, 1148 IWX_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11, 1149 IWX_MSIX_IVAR_CAUSE_REG_RESET_DONE = 0x12, 1150 IWX_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16, 1151 IWX_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17, 1152 IWX_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18, 1153 IWX_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29, 1154 IWX_MSIX_IVAR_CAUSE_REG_SCD = 0x2a, 1155 IWX_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b, 1156 IWX_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d, 1157 IWX_MSIX_IVAR_CAUSE_REG_HAP = 0x2e, 1158 }; 1159 1160 #define IWX_MSIX_AUTO_CLEAR_CAUSE (0 << 7) 1161 #define IWX_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7) 1162 1163 #define IWX_CSR_ADDR_BASE(sc) ((sc)->mac_addr_from_csr) 1164 #define IWX_CSR_MAC_ADDR0_OTP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x00) 1165 #define IWX_CSR_MAC_ADDR1_OTP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x04) 1166 #define IWX_CSR_MAC_ADDR0_STRAP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x08) 1167 #define IWX_CSR_MAC_ADDR1_STRAP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x0c) 1168 1169 /** 1170 * uCode API flags 1171 * @IWX_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 1172 * was a separate TLV but moved here to save space. 1173 * @IWX_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 1174 * treats good CRC threshold as a boolean 1175 * @IWX_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 1176 * @IWX_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 1177 * @IWX_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 1178 * @IWX_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 1179 * @IWX_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 1180 * offload profile config command. 1181 * @IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 1182 * (rather than two) IPv6 addresses 1183 * @IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 1184 * from the probe request template. 1185 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 1186 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 1187 * @IWX_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 1188 * single bound interface). 1189 * @IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 1190 * @IWX_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 1191 * @IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 1192 * @IWX_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 1193 * @IWX_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 1194 * 1195 */ 1196 #define IWX_UCODE_TLV_FLAGS_PAN (1 << 0) 1197 #define IWX_UCODE_TLV_FLAGS_NEWSCAN (1 << 1) 1198 #define IWX_UCODE_TLV_FLAGS_MFP (1 << 2) 1199 #define IWX_UCODE_TLV_FLAGS_P2P (1 << 3) 1200 #define IWX_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4) 1201 #define IWX_UCODE_TLV_FLAGS_SHORT_BL (1 << 7) 1202 #define IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10) 1203 #define IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12) 1204 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15) 1205 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16) 1206 #define IWX_UCODE_TLV_FLAGS_P2P_PS (1 << 21) 1207 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22) 1208 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23) 1209 #define IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24) 1210 #define IWX_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25) 1211 #define IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26) 1212 #define IWX_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29) 1213 #define IWX_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30) 1214 #define IWX_UCODE_TLV_FLAGS_LTE_COEX (1U << 31) 1215 1216 #define IWX_UCODE_TLV_FLAG_BITS \ 1217 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 1218 1219 /** 1220 * uCode TLV api 1221 * @IWX_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 1222 * longer than the passive one, which is essential for fragmented scan. 1223 * @IWX_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 1224 * @IWX_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 1225 * @IWX_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 1226 * @IWX_UCODE_TLV_API_NEW_VERSION: new versioning format 1227 * @IWX_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 1228 * (command version 3) that supports per-chain limits 1229 * @IWX_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan 1230 * iteration complete notification, and the timestamp reported for RX 1231 * received during scan, are reported in TSF of the mac specified in the 1232 * scan request. 1233 * @IWX_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of 1234 * ADD_MODIFY_STA_KEY_API_S_VER_2. 1235 * @IWX_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignment. 1236 * @IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 1237 * instead of 3. 1238 * @IWX_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used 1239 * @IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG: This ucode supports v3 of 1240 * SCAN_CONFIG_DB_CMD_API_S. 1241 * 1242 * @IWX_NUM_UCODE_TLV_API: number of bits used 1243 */ 1244 #define IWX_UCODE_TLV_API_FRAGMENTED_SCAN 8 1245 #define IWX_UCODE_TLV_API_WIFI_MCC_UPDATE 9 1246 #define IWX_UCODE_TLV_API_WIDE_CMD_HDR 14 1247 #define IWX_UCODE_TLV_API_LQ_SS_PARAMS 18 1248 #define IWX_UCODE_TLV_API_NEW_VERSION 20 1249 #define IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY 24 1250 #define IWX_UCODE_TLV_API_TX_POWER_CHAIN 27 1251 #define IWX_UCODE_TLV_API_SCAN_TSF_REPORT 28 1252 #define IWX_UCODE_TLV_API_TKIP_MIC_KEYS 29 1253 #define IWX_UCODE_TLV_API_STA_TYPE 30 1254 #define IWX_UCODE_TLV_API_NAN2_VER2 31 1255 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL 32 1256 #define IWX_UCODE_TLV_API_NEW_RX_STATS 35 1257 #define IWX_UCODE_TLV_API_WOWLAN_KEY_MATERIAL 36 1258 #define IWX_UCODE_TLV_API_QUOTA_LOW_LATENCY 38 1259 #define IWX_UCODE_TLV_API_DEPRECATE_TTAK 41 1260 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42 1261 #define IWX_UCODE_TLV_API_NAN_NOTIF_V2 43 1262 #define IWX_UCODE_TLV_API_FRAG_EBS 44 1263 #define IWX_UCODE_TLV_API_REDUCE_TX_POWER 45 1264 #define IWX_UCODE_TLV_API_SHORT_BEACON_NOTIF 46 1265 #define IWX_UCODE_TLV_API_BEACON_FILTER_V4 47 1266 #define IWX_UCODE_TLV_API_REGULATORY_NVM_INFO 48 1267 #define IWX_UCODE_TLV_API_FTM_NEW_RANGE_REQ 49 1268 #define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56 1269 #define IWX_UCODE_TLV_API_SCAN_OFFLOAD_CHANS 50 1270 #define IWX_UCODE_TLV_API_MBSSID_HE 52 1271 #define IWX_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE 53 1272 #define IWX_UCODE_TLV_API_FTM_RTT_ACCURACY 54 1273 #define IWX_UCODE_TLV_API_SAR_TABLE_VER 55 1274 #define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56 1275 #define IWX_UCODE_TLV_API_ADWELL_HB_DEF_N_AP 57 1276 #define IWX_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58 1277 #define IWX_UCODE_TLV_API_BAND_IN_RX_DATA 59 1278 #define IWX_NUM_UCODE_TLV_API 128 1279 1280 #define IWX_UCODE_TLV_API_BITS \ 1281 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS" 1282 1283 /** 1284 * uCode capabilities 1285 * @IWX_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 1286 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 1287 * @IWX_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 1288 * @IWX_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 1289 * @IWX_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 1290 * @IWX_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 1291 * @IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 1292 * tx power value into TPC Report action frame and Link Measurement Report 1293 * action frame 1294 * @IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 1295 * channel in DS parameter set element in probe requests. 1296 * @IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 1297 * probe requests. 1298 * @IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 1299 * @IWX_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 1300 * which also implies support for the scheduler configuration command 1301 * @IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 1302 * @IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 1303 * @IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 1304 * @IWX_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 1305 * @IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 1306 * @IWX_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 1307 * @IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 1308 * @IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 1309 * @IWX_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 1310 * @IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 1311 * sources for the MCC. This TLV bit is a future replacement to 1312 * IWX_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 1313 * is supported. 1314 * @IWX_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 1315 * @IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 1316 * @IWX_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 1317 * @IWX_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 1318 * 0=no support) 1319 * @IWx_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS: firmware supports ultra high band 1320 * (6 GHz). 1321 * @IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 1322 * @IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 1323 * @IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 1324 * @IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 1325 * antenna the beacon should be transmitted 1326 * @IWX_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 1327 * from AP and will send it upon d0i3 exit. 1328 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 1329 * @IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 1330 * @IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 1331 * thresholds reporting 1332 * @IWX_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 1333 * @IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 1334 * regular image. 1335 * @IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 1336 * memory addresses from the firmware. 1337 * @IWX_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 1338 * @IWX_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 1339 * 0=no support) 1340 * 1341 * @IWX_NUM_UCODE_TLV_CAPA: number of bits used 1342 */ 1343 #define IWX_UCODE_TLV_CAPA_D0I3_SUPPORT 0 1344 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT 1 1345 #define IWX_UCODE_TLV_CAPA_UMAC_SCAN 2 1346 #define IWX_UCODE_TLV_CAPA_BEAMFORMER 3 1347 #define IWX_UCODE_TLV_CAPA_TOF_SUPPORT 5 1348 #define IWX_UCODE_TLV_CAPA_TDLS_SUPPORT 6 1349 #define IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8 1350 #define IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9 1351 #define IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10 1352 #define IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11 1353 #define IWX_UCODE_TLV_CAPA_DQA_SUPPORT 12 1354 #define IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13 1355 #define IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17 1356 #define IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18 1357 #define IWX_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19 1358 #define IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20 1359 #define IWX_UCODE_TLV_CAPA_CSUM_SUPPORT 21 1360 #define IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22 1361 #define IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26 1362 #define IWX_UCODE_TLV_CAPA_BT_COEX_PLCR 28 1363 #define IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC 29 1364 #define IWX_UCODE_TLV_CAPA_BT_COEX_RRC 30 1365 #define IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT 31 1366 #define IWX_UCODE_TLV_CAPA_NAN_SUPPORT 34 1367 #define IWX_UCODE_TLV_CAPA_UMAC_UPLOAD 35 1368 #define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37 1369 #define IWX_UCODE_TLV_CAPA_STA_PM_NOTIF 38 1370 #define IWX_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39 1371 #define IWX_UCODE_TLV_CAPA_CDB_SUPPORT 40 1372 #define IWX_UCODE_TLV_CAPA_D0I3_END_FIRST 41 1373 #define IWX_UCODE_TLV_CAPA_TLC_OFFLOAD 43 1374 #define IWX_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44 1375 #define IWX_UCODE_TLV_CAPA_COEX_SCHEMA_2 45 1376 #define IWX_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD 46 1377 #define IWX_UCODE_TLV_CAPA_FTM_CALIBRATED 47 1378 #define IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48 1379 #define IWX_UCODE_TLV_CAPA_CS_MODIFY 49 1380 #define IWX_UCODE_TLV_CAPA_SET_LTR_GEN2 50 1381 #define IWX_UCODE_TLV_CAPA_SET_PPAG 52 1382 #define IWX_UCODE_TLV_CAPA_TAS_CFG 53 1383 #define IWX_UCODE_TLV_CAPA_SESSION_PROT_CMD 54 1384 #define IWX_UCODE_TLV_CAPA_PROTECTED_TWT 56 1385 #define IWX_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE 57 1386 #define IWX_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN 58 1387 #define IWX_UCODE_TLV_CAPA_PROTECTED_TWT 56 1388 #define IWX_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE 57 1389 #define IWX_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN 58 1390 #define IWX_UCODE_TLV_CAPA_BAID_ML_SUPPORT 63 1391 #define IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64 1392 #define IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65 1393 #define IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67 1394 #define IWX_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68 1395 #define IWX_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD 70 1396 #define IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71 1397 #define IWX_UCODE_TLV_CAPA_BEACON_STORING 72 1398 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V3 73 1399 #define IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW 74 1400 #define IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75 1401 #define IWX_UCODE_TLV_CAPA_CTDP_SUPPORT 76 1402 #define IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77 1403 #define IWX_UCODE_TLV_CAPA_LMAC_UPLOAD 79 1404 #define IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80 1405 #define IWX_UCODE_TLV_CAPA_LQM_SUPPORT 81 1406 #define IWX_UCODE_TLV_CAPA_TX_POWER_ACK 84 1407 #define IWX_UCODE_TLV_CAPA_D3_DEBUG 87 1408 #define IWX_UCODE_TLV_CAPA_LED_CMD_SUPPORT 88 1409 #define IWX_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT 89 1410 #define IWX_UCODE_TLV_CAPA_CSI_REPORTING 90 1411 #define IWX_UCODE_TLV_CAPA_CSI_REPORTING_V2 91 1412 #define IWX_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP 92 1413 #define IWX_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP 93 1414 #define IWX_UCODE_TLV_CAPA_MLME_OFFLOAD 96 1415 #define IWX_UCODE_TLV_CAPA_BIGTK_SUPPORT 100 1416 #define IWX_UCODE_TLV_CAPA_RFIM_SUPPORT 102 1417 1418 #define IWX_NUM_UCODE_TLV_CAPA 128 1419 1420 /* 1421 * For 16.0 uCode and above, there is no differentiation between sections, 1422 * just an offset to the HW address. 1423 */ 1424 #define IWX_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 1425 #define IWX_PAGING_SEPARATOR_SECTION 0xAAAABBBB 1426 1427 /* uCode version contains 4 values: Major/Minor/API/Serial */ 1428 #define IWX_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 1429 #define IWX_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 1430 #define IWX_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 1431 #define IWX_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 1432 1433 /* 1434 * Calibration control struct. 1435 * Sent as part of the phy configuration command. 1436 * @flow_trigger: bitmap for which calibrations to perform according to 1437 * flow triggers. 1438 * @event_trigger: bitmap for which calibrations to perform according to 1439 * event triggers. 1440 */ 1441 struct iwx_tlv_calib_ctrl { 1442 uint32_t flow_trigger; 1443 uint32_t event_trigger; 1444 } __packed; 1445 1446 #define IWX_FW_PHY_CFG_RADIO_TYPE_POS 0 1447 #define IWX_FW_PHY_CFG_RADIO_TYPE (0x3 << IWX_FW_PHY_CFG_RADIO_TYPE_POS) 1448 #define IWX_FW_PHY_CFG_RADIO_STEP_POS 2 1449 #define IWX_FW_PHY_CFG_RADIO_STEP (0x3 << IWX_FW_PHY_CFG_RADIO_STEP_POS) 1450 #define IWX_FW_PHY_CFG_RADIO_DASH_POS 4 1451 #define IWX_FW_PHY_CFG_RADIO_DASH (0x3 << IWX_FW_PHY_CFG_RADIO_DASH_POS) 1452 #define IWX_FW_PHY_CFG_TX_CHAIN_POS 16 1453 #define IWX_FW_PHY_CFG_TX_CHAIN (0xf << IWX_FW_PHY_CFG_TX_CHAIN_POS) 1454 #define IWX_FW_PHY_CFG_RX_CHAIN_POS 20 1455 #define IWX_FW_PHY_CFG_RX_CHAIN (0xf << IWX_FW_PHY_CFG_RX_CHAIN_POS) 1456 1457 /** 1458 * struct iwx_fw_cipher_scheme - a cipher scheme supported by FW. 1459 * @cipher: a cipher suite selector 1460 * @flags: cipher scheme flags (currently reserved for a future use) 1461 * @hdr_len: a size of MPDU security header 1462 * @pn_len: a size of PN 1463 * @pn_off: an offset of pn from the beginning of the security header 1464 * @key_idx_off: an offset of key index byte in the security header 1465 * @key_idx_mask: a bit mask of key_idx bits 1466 * @key_idx_shift: bit shift needed to get key_idx 1467 * @mic_len: mic length in bytes 1468 * @hw_cipher: a HW cipher index used in host commands 1469 */ 1470 struct iwx_fw_cipher_scheme { 1471 uint32_t cipher; 1472 uint8_t flags; 1473 uint8_t hdr_len; 1474 uint8_t pn_len; 1475 uint8_t pn_off; 1476 uint8_t key_idx_off; 1477 uint8_t key_idx_mask; 1478 uint8_t key_idx_shift; 1479 uint8_t mic_len; 1480 uint8_t hw_cipher; 1481 } __packed; 1482 1483 /** 1484 * struct iwx_fw_cscheme_list - a cipher scheme list 1485 * @size: a number of entries 1486 * @cs: cipher scheme entries 1487 */ 1488 struct iwx_fw_cscheme_list { 1489 uint8_t size; 1490 struct iwx_fw_cipher_scheme cs[]; 1491 } __packed; 1492 1493 /* v1/v2 uCode file layout */ 1494 struct iwx_ucode_header { 1495 uint32_t ver; /* major/minor/API/serial */ 1496 union { 1497 struct { 1498 uint32_t inst_size; /* bytes of runtime code */ 1499 uint32_t data_size; /* bytes of runtime data */ 1500 uint32_t init_size; /* bytes of init code */ 1501 uint32_t init_data_size; /* bytes of init data */ 1502 uint32_t boot_size; /* bytes of bootstrap code */ 1503 uint8_t data[0]; /* in same order as sizes */ 1504 } v1; 1505 struct { 1506 uint32_t build; /* build number */ 1507 uint32_t inst_size; /* bytes of runtime code */ 1508 uint32_t data_size; /* bytes of runtime data */ 1509 uint32_t init_size; /* bytes of init code */ 1510 uint32_t init_data_size; /* bytes of init data */ 1511 uint32_t boot_size; /* bytes of bootstrap code */ 1512 uint8_t data[0]; /* in same order as sizes */ 1513 } v2; 1514 } u; 1515 }; 1516 1517 /* 1518 * new TLV uCode file layout 1519 * 1520 * The new TLV file format contains TLVs, that each specify 1521 * some piece of data. 1522 */ 1523 1524 #define IWX_UCODE_TLV_INVALID 0 /* unused */ 1525 #define IWX_UCODE_TLV_INST 1 1526 #define IWX_UCODE_TLV_DATA 2 1527 #define IWX_UCODE_TLV_INIT 3 1528 #define IWX_UCODE_TLV_INIT_DATA 4 1529 #define IWX_UCODE_TLV_BOOT 5 1530 #define IWX_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */ 1531 #define IWX_UCODE_TLV_PAN 7 1532 #define IWX_UCODE_TLV_RUNT_EVTLOG_PTR 8 1533 #define IWX_UCODE_TLV_RUNT_EVTLOG_SIZE 9 1534 #define IWX_UCODE_TLV_RUNT_ERRLOG_PTR 10 1535 #define IWX_UCODE_TLV_INIT_EVTLOG_PTR 11 1536 #define IWX_UCODE_TLV_INIT_EVTLOG_SIZE 12 1537 #define IWX_UCODE_TLV_INIT_ERRLOG_PTR 13 1538 #define IWX_UCODE_TLV_ENHANCE_SENS_TBL 14 1539 #define IWX_UCODE_TLV_PHY_CALIBRATION_SIZE 15 1540 #define IWX_UCODE_TLV_WOWLAN_INST 16 1541 #define IWX_UCODE_TLV_WOWLAN_DATA 17 1542 #define IWX_UCODE_TLV_FLAGS 18 1543 #define IWX_UCODE_TLV_SEC_RT 19 1544 #define IWX_UCODE_TLV_SEC_INIT 20 1545 #define IWX_UCODE_TLV_SEC_WOWLAN 21 1546 #define IWX_UCODE_TLV_DEF_CALIB 22 1547 #define IWX_UCODE_TLV_PHY_SKU 23 1548 #define IWX_UCODE_TLV_SECURE_SEC_RT 24 1549 #define IWX_UCODE_TLV_SECURE_SEC_INIT 25 1550 #define IWX_UCODE_TLV_SECURE_SEC_WOWLAN 26 1551 #define IWX_UCODE_TLV_NUM_OF_CPU 27 1552 #define IWX_UCODE_TLV_CSCHEME 28 1553 #define IWX_UCODE_TLV_API_CHANGES_SET 29 1554 #define IWX_UCODE_TLV_ENABLED_CAPABILITIES 30 1555 #define IWX_UCODE_TLV_N_SCAN_CHANNELS 31 1556 #define IWX_UCODE_TLV_PAGING 32 1557 #define IWX_UCODE_TLV_SEC_RT_USNIFFER 34 1558 #define IWX_UCODE_TLV_SDIO_ADMA_ADDR 35 1559 #define IWX_UCODE_TLV_FW_VERSION 36 1560 #define IWX_UCODE_TLV_FW_DBG_DEST 38 1561 #define IWX_UCODE_TLV_FW_DBG_CONF 39 1562 #define IWX_UCODE_TLV_FW_DBG_TRIGGER 40 1563 #define IWX_UCODE_TLV_CMD_VERSIONS 48 1564 #define IWX_UCODE_TLV_FW_GSCAN_CAPA 50 1565 #define IWX_UCODE_TLV_FW_MEM_SEG 51 1566 #define IWX_UCODE_TLV_IML 52 1567 #define IWX_UCODE_TLV_FW_FMAC_API_VERSION 53 1568 #define IWX_UCODE_TLV_UMAC_DEBUG_ADDRS 54 1569 #define IWX_UCODE_TLV_LMAC_DEBUG_ADDRS 55 1570 #define IWX_UCODE_TLV_FW_RECOVERY_INFO 57 1571 #define IWX_UCODE_TLV_HW_TYPE 58 1572 #define IWX_UCODE_TLV_FW_FMAC_RECOVERY_INFO 59 1573 #define IWX_UCODE_TLV_FW_FSEQ_VERSION 60 1574 #define IWX_UCODE_TLV_PHY_INTEGRATION_VERSION 61 1575 #define IWX_UCODE_TLV_PNVM_VERSION 62 1576 #define IWX_UCODE_TLV_PNVM_SKU 64 1577 1578 #define IWX_UCODE_TLV_SEC_TABLE_ADDR 66 1579 #define IWX_UCODE_TLV_D3_KEK_KCK_ADDR 67 1580 #define IWX_UCODE_TLV_CURRENT_PC 68 1581 1582 #define IWX_UCODE_TLV_CONST_BASE 0x100 1583 #define IWX_UCODE_TLV_FW_NUM_STATIONS (IWX_UCODE_TLV_CONST_BASE + 0) 1584 #define IWX_UCODE_TLV_FW_NUM_BEACONS (IWX_UCODE_TLV_CONST_BASE + 2) 1585 1586 #define IWX_UCODE_TLV_DEBUG_BASE 0x1000005 1587 #define IWX_UCODE_TLV_TYPE_DEBUG_INFO (IWX_UCODE_TLV_DEBUG_BASE + 0) 1588 #define IWX_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWX_UCODE_TLV_DEBUG_BASE + 1) 1589 #define IWX_UCODE_TLV_TYPE_HCMD (IWX_UCODE_TLV_DEBUG_BASE + 2) 1590 #define IWX_UCODE_TLV_TYPE_REGIONS (IWX_UCODE_TLV_DEBUG_BASE + 3) 1591 #define IWX_UCODE_TLV_TYPE_TRIGGERS (IWX_UCODE_TLV_DEBUG_BASE + 4) 1592 #define IWX_UCODE_TLV_TYPE_CONF_SET (IWX_UCODE_TLV_DEBUG_BASE + 5) 1593 #define IWX_UCODE_TLV_DEBUG_MAX IWX_UCODE_TLV_TYPE_CONF_SET 1594 1595 1596 struct iwx_ucode_tlv { 1597 uint32_t type; /* see above */ 1598 uint32_t length; /* not including type/length fields */ 1599 uint8_t data[0]; 1600 }; 1601 1602 struct iwx_ucode_api { 1603 uint32_t api_index; 1604 uint32_t api_flags; 1605 } __packed; 1606 1607 struct iwx_ucode_capa { 1608 uint32_t api_index; 1609 uint32_t api_capa; 1610 } __packed; 1611 1612 #define IWX_TLV_UCODE_MAGIC 0x0a4c5749 1613 1614 struct iwx_tlv_ucode_header { 1615 /* 1616 * The TLV style ucode header is distinguished from 1617 * the v1/v2 style header by first four bytes being 1618 * zero, as such is an invalid combination of 1619 * major/minor/API/serial versions. 1620 */ 1621 uint32_t zero; 1622 uint32_t magic; 1623 uint8_t human_readable[64]; 1624 uint32_t ver; /* major/minor/API/serial */ 1625 uint32_t build; 1626 uint64_t ignore; 1627 /* 1628 * The data contained herein has a TLV layout, 1629 * see above for the TLV header and types. 1630 * Note that each TLV is padded to a length 1631 * that is a multiple of 4 for alignment. 1632 */ 1633 uint8_t data[0]; 1634 }; 1635 1636 /* 1637 * Registers in this file are internal, not PCI bus memory mapped. 1638 * Driver accesses these via IWX_HBUS_TARG_PRPH_* registers. 1639 */ 1640 #define IWX_PRPH_BASE (0x00000) 1641 #define IWX_PRPH_END (0xFFFFF) 1642 1643 /****************************/ 1644 /* Flow Handler Definitions */ 1645 /****************************/ 1646 1647 /** 1648 * struct iwx_rb_status - receive buffer status 1649 * host memory mapped FH registers 1650 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1651 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1652 * @finished_rb_num [0:11] - Indicates the index of the current RB 1653 * in which the last frame was written to 1654 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1655 * which was transferred 1656 */ 1657 struct iwx_rb_status { 1658 uint16_t closed_rb_num; 1659 uint16_t closed_fr_num; 1660 uint16_t finished_rb_num; 1661 uint16_t finished_fr_nam; 1662 uint32_t unused; 1663 } __packed; 1664 1665 1666 #define IWX_TFD_QUEUE_SIZE_MAX (256) 1667 #define IWX_TFD_QUEUE_SIZE_MAX_GEN3 (65536) 1668 /* cb size is the exponent - 3 */ 1669 #define IWX_TFD_QUEUE_CB_SIZE(x) (IWX_RX_QUEUE_CB_SIZE(x) - 3) 1670 #define IWX_TFD_QUEUE_SIZE_BC_DUP (64) 1671 #define IWX_TFD_QUEUE_BC_SIZE (IWX_TFD_QUEUE_SIZE_MAX + \ 1672 IWX_TFD_QUEUE_SIZE_BC_DUP) 1673 #define IWX_TFD_QUEUE_BC_SIZE_GEN3_AX210 1024 1674 #define IWX_TFD_QUEUE_BC_SIZE_GEN3_BZ (1024 * 4) 1675 #define IWX_TFH_NUM_TBS 25 1676 1677 /** 1678 * struct iwx_tfh_tb transmit buffer descriptor within transmit frame descriptor 1679 * 1680 * This structure contains dma address and length of transmission address 1681 * 1682 * @tb_len length of the tx buffer 1683 * @addr 64 bits dma address 1684 */ 1685 struct iwx_tfh_tb { 1686 uint16_t tb_len; 1687 uint64_t addr; 1688 } __packed; 1689 1690 /** 1691 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1692 * Both driver and device share these circular buffers, each of which must be 1693 * contiguous 256 TFDs. 1694 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes 1695 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes 1696 * 1697 * Each TFD contains pointer/size information for up to 25 data buffers 1698 * in host DRAM. These buffers collectively contain the (one) frame described 1699 * by the TFD. Each buffer must be a single contiguous block of memory within 1700 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1701 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1702 * Tx frame, up to 8 KBytes in size. 1703 * 1704 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1705 */ 1706 1707 /** 1708 * struct iwx_tfh_tfd - Transmit Frame Descriptor (TFD) 1709 * @ num_tbs 0-4 number of active tbs 1710 * 5 -15 reserved 1711 * @ tbs[25] transmit frame buffer descriptors 1712 * @ __pad padding 1713 */ 1714 struct iwx_tfh_tfd { 1715 uint16_t num_tbs; 1716 struct iwx_tfh_tb tbs[IWX_TFH_NUM_TBS]; 1717 uint32_t __pad; 1718 } __packed; 1719 1720 /* Fixed (non-configurable) rx data from phy */ 1721 1722 /** 1723 * struct iwx_agn_schedq_bc_tbl scheduler byte count table 1724 * base physical address provided by IWX_SCD_DRAM_BASE_ADDR 1725 * @tfd_offset 0-11 - tx command byte count 1726 * 12-13 - number of 64 byte chunks 1727 * 14-15 - reserved 1728 */ 1729 struct iwx_agn_scd_bc_tbl { 1730 uint16_t tfd_offset[IWX_TFD_QUEUE_BC_SIZE]; 1731 } __packed; 1732 1733 /** 1734 * struct iwx_gen3_bc_tbl_entry scheduler byte count table entry gen3 1735 * For AX210 and up, the table no longer needs to be contiguous in memory. 1736 * @tfd_offset: 0-13 - tx command byte count 1737 * 14-15 - number of 64 byte chunks 1738 */ 1739 struct iwx_gen3_bc_tbl_entry { 1740 uint16_t tfd_offset; 1741 } __packed; 1742 1743 /** 1744 * DQA - Dynamic Queue Allocation -introduction 1745 * 1746 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi 1747 * to allow dynamic allocation of queues on-demand, rather than allocate them 1748 * statically ahead of time. Ideally, we would like to allocate one queue 1749 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2 1750 * even if it also needs to send traffic to a sleeping STA1, without being 1751 * blocked by the sleeping station. 1752 * 1753 * Although the queues in DQA mode are dynamically allocated, there are still 1754 * some queues that are statically allocated: 1755 * TXQ #0 - command queue 1756 * TXQ #1 - aux frames 1757 */ 1758 1759 /* static DQA Tx queue numbers */ 1760 #define IWX_DQA_CMD_QUEUE 0 1761 #define IWX_DQA_AUX_QUEUE 1 1762 1763 #define IWX_DQA_INJECT_MONITOR_QUEUE 2 /* used in monitor mode only */ 1764 #define IWX_DQA_MGMT_QUEUE 1 /* default queue other modes */ 1765 1766 /* Reserve 8 DQA Tx queues for QoS data frames. */ 1767 #define IWX_MAX_TID_COUNT 8 1768 #define IWX_FIRST_AGG_TX_QUEUE (IWX_DQA_MGMT_QUEUE + 1) 1769 #define IWX_LAST_AGG_TX_QUEUE (IWX_FIRST_AGG_TX_QUEUE + IWX_MAX_TID_COUNT - 1) 1770 #define IWX_NUM_TX_QUEUES (IWX_LAST_AGG_TX_QUEUE + 1) 1771 1772 /** 1773 * Max Tx window size is the max number of contiguous TFDs that the scheduler 1774 * can keep track of at one time when creating block-ack chains of frames. 1775 * Note that "64" matches the number of ack bits in a block-ack packet. 1776 */ 1777 #define IWX_FRAME_LIMIT 64 1778 1779 #define IWX_TX_FIFO_BK 0 1780 #define IWX_TX_FIFO_BE 1 1781 #define IWX_TX_FIFO_VI 2 1782 #define IWX_TX_FIFO_VO 3 1783 #define IWX_TX_FIFO_MCAST 5 1784 #define IWX_TX_FIFO_CMD 7 1785 1786 enum iwx_gen2_tx_fifo { 1787 IWX_GEN2_TX_FIFO_CMD = 0, 1788 IWX_GEN2_EDCA_TX_FIFO_BK, 1789 IWX_GEN2_EDCA_TX_FIFO_BE, 1790 IWX_GEN2_EDCA_TX_FIFO_VI, 1791 IWX_GEN2_EDCA_TX_FIFO_VO, 1792 IWX_GEN2_TRIG_TX_FIFO_BK, 1793 IWX_GEN2_TRIG_TX_FIFO_BE, 1794 IWX_GEN2_TRIG_TX_FIFO_VI, 1795 IWX_GEN2_TRIG_TX_FIFO_VO, 1796 }; 1797 1798 /** 1799 * TXQ config options 1800 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue 1801 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format 1802 */ 1803 #define IWX_TX_QUEUE_CFG_ENABLE_QUEUE (1 << 0) 1804 #define IWX_TX_QUEUE_CFG_TFD_SHORT_FORMAT (1 << 1) 1805 1806 #define IWX_DEFAULT_QUEUE_SIZE IWX_TFD_QUEUE_SIZE_MAX 1807 1808 /** 1809 * struct iwx_tx_queue_cfg_cmd - txq hw scheduler config command 1810 * @sta_id: station id 1811 * @tid: tid of the queue 1812 * @flags: see &enum iwl_tx_queue_cfg_actions 1813 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3. 1814 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs) 1815 * @byte_cnt_addr: address of byte count table 1816 * @tfdq_addr: address of TFD circular buffer 1817 */ 1818 struct iwx_tx_queue_cfg_cmd { 1819 uint8_t sta_id; 1820 uint8_t tid; 1821 uint16_t flags; 1822 uint32_t cb_size; 1823 uint64_t byte_cnt_addr; 1824 uint64_t tfdq_addr; 1825 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */ 1826 1827 /** 1828 * struct iwx_tx_queue_cfg_rsp - response to txq hw scheduler config 1829 * @queue_number: queue number assigned to this RA -TID 1830 * @flags: set on failure 1831 * @write_pointer: initial value for write pointer 1832 * @reserved: reserved 1833 */ 1834 struct iwx_tx_queue_cfg_rsp { 1835 uint16_t queue_number; 1836 uint16_t flags; 1837 uint16_t write_pointer; 1838 uint16_t reserved; 1839 } __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */ 1840 1841 1842 /* 1843 * Commands 1844 */ 1845 #define IWX_ALIVE 0x1 1846 #define IWX_REPLY_ERROR 0x2 1847 #define IWX_INIT_COMPLETE_NOTIF 0x4 1848 1849 /* PHY context commands */ 1850 #define IWX_PHY_CONTEXT_CMD 0x8 1851 #define IWX_DBG_CFG 0x9 1852 1853 /* UMAC scan commands */ 1854 #define IWX_SCAN_ITERATION_COMPLETE_UMAC 0xb5 1855 #define IWX_SCAN_CFG_CMD 0xc 1856 #define IWX_SCAN_REQ_UMAC 0xd 1857 #define IWX_SCAN_ABORT_UMAC 0xe 1858 #define IWX_SCAN_COMPLETE_UMAC 0xf 1859 1860 /* station table */ 1861 #define IWX_ADD_STA_KEY 0x17 1862 #define IWX_ADD_STA 0x18 1863 #define IWX_REMOVE_STA 0x19 1864 1865 /* TX */ 1866 #define IWX_TX_CMD 0x1c 1867 #define IWX_TXPATH_FLUSH 0x1e 1868 #define IWX_MGMT_MCAST_KEY 0x1f 1869 1870 /* scheduler config */ 1871 #define IWX_SCD_QUEUE_CFG 0x1d 1872 1873 /* global key */ 1874 #define IWX_WEP_KEY 0x20 1875 1876 /* MAC and Binding commands */ 1877 #define IWX_MAC_CONTEXT_CMD 0x28 1878 #define IWX_TIME_EVENT_CMD 0x29 /* both CMD and response */ 1879 #define IWX_TIME_EVENT_NOTIFICATION 0x2a 1880 #define IWX_BINDING_CONTEXT_CMD 0x2b 1881 #define IWX_TIME_QUOTA_CMD 0x2c 1882 #define IWX_NON_QOS_TX_COUNTER_CMD 0x2d 1883 1884 /* Calibration */ 1885 #define IWX_TEMPERATURE_NOTIFICATION 0x62 1886 #define IWX_CALIBRATION_CFG_CMD 0x65 1887 #define IWX_CALIBRATION_RES_NOTIFICATION 0x66 1888 #define IWX_CALIBRATION_COMPLETE_NOTIFICATION 0x67 1889 #define IWX_RADIO_VERSION_NOTIFICATION 0x68 1890 1891 /* Phy */ 1892 #define IWX_PHY_CONFIGURATION_CMD 0x6a 1893 1894 /* Power - legacy power table command */ 1895 #define IWX_POWER_TABLE_CMD 0x77 1896 #define IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78 1897 #define IWX_LTR_CONFIG 0xee 1898 1899 /* NVM */ 1900 #define IWX_NVM_ACCESS_CMD 0x88 1901 1902 #define IWX_SET_CALIB_DEFAULT_CMD 0x8e 1903 1904 #define IWX_BEACON_NOTIFICATION 0x90 1905 #define IWX_BEACON_TEMPLATE_CMD 0x91 1906 #define IWX_TX_ANT_CONFIGURATION_CMD 0x98 1907 #define IWX_BT_CONFIG 0x9b 1908 #define IWX_STATISTICS_CMD 0x9c 1909 #define IWX_STATISTICS_NOTIFICATION 0x9d 1910 #define IWX_REDUCE_TX_POWER_CMD 0x9f 1911 1912 /* RF-KILL commands and notifications */ 1913 #define IWX_CARD_STATE_CMD 0xa0 1914 #define IWX_CARD_STATE_NOTIFICATION 0xa1 1915 1916 #define IWX_MISSED_BEACONS_NOTIFICATION 0xa2 1917 1918 #define IWX_MFUART_LOAD_NOTIFICATION 0xb1 1919 1920 /* Power - new power table command */ 1921 #define IWX_MAC_PM_POWER_TABLE 0xa9 1922 1923 #define IWX_REPLY_RX_PHY_CMD 0xc0 1924 #define IWX_REPLY_RX_MPDU_CMD 0xc1 1925 #define IWX_BAR_FRAME_RELEASE 0xc2 1926 #define IWX_FRAME_RELEASE 0xc3 1927 #define IWX_BA_NOTIF 0xc5 1928 1929 /* Location Aware Regulatory */ 1930 #define IWX_MCC_UPDATE_CMD 0xc8 1931 #define IWX_MCC_CHUB_UPDATE_CMD 0xc9 1932 1933 /* BT Coex */ 1934 #define IWX_BT_COEX_PRIO_TABLE 0xcc 1935 #define IWX_BT_COEX_PROT_ENV 0xcd 1936 #define IWX_BT_PROFILE_NOTIFICATION 0xce 1937 #define IWX_BT_COEX_CI 0x5d 1938 1939 #define IWX_REPLY_SF_CFG_CMD 0xd1 1940 #define IWX_REPLY_BEACON_FILTERING_CMD 0xd2 1941 1942 /* DTS measurements */ 1943 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER 0xdc 1944 #define IWX_DTS_MEASUREMENT_NOTIFICATION 0xdd 1945 1946 #define IWX_REPLY_DEBUG_CMD 0xf0 1947 #define IWX_DEBUG_LOG_MSG 0xf7 1948 1949 #define IWX_MCAST_FILTER_CMD 0xd0 1950 1951 /* D3 commands/notifications */ 1952 #define IWX_D3_CONFIG_CMD 0xd3 1953 #define IWX_PROT_OFFLOAD_CONFIG_CMD 0xd4 1954 #define IWX_OFFLOADS_QUERY_CMD 0xd5 1955 #define IWX_REMOTE_WAKE_CONFIG_CMD 0xd6 1956 1957 /* for WoWLAN in particular */ 1958 #define IWX_WOWLAN_PATTERNS 0xe0 1959 #define IWX_WOWLAN_CONFIGURATION 0xe1 1960 #define IWX_WOWLAN_TSC_RSC_PARAM 0xe2 1961 #define IWX_WOWLAN_TKIP_PARAM 0xe3 1962 #define IWX_WOWLAN_KEK_KCK_MATERIAL 0xe4 1963 #define IWX_WOWLAN_GET_STATUSES 0xe5 1964 #define IWX_WOWLAN_TX_POWER_PER_DB 0xe6 1965 1966 /* and for NetDetect */ 1967 #define IWX_NET_DETECT_CONFIG_CMD 0x54 1968 #define IWX_NET_DETECT_PROFILES_QUERY_CMD 0x56 1969 #define IWX_NET_DETECT_PROFILES_CMD 0x57 1970 #define IWX_NET_DETECT_HOTSPOTS_CMD 0x58 1971 #define IWX_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59 1972 1973 /* system group command IDs */ 1974 #define IWX_FSEQ_VER_MISMATCH_NOTIFICATION 0xff 1975 1976 #define IWX_REPLY_MAX 0xff 1977 1978 /* PHY_OPS subcommand IDs */ 1979 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0 1980 #define IWX_CTDP_CONFIG_CMD 0x03 1981 #define IWX_TEMP_REPORTING_THRESHOLDS_CMD 0x04 1982 #define IWX_CT_KILL_NOTIFICATION 0xFE 1983 #define IWX_DTS_MEASUREMENT_NOTIF_WIDE 0xFF 1984 1985 /* command groups */ 1986 #define IWX_LEGACY_GROUP 0x0 1987 #define IWX_LONG_GROUP 0x1 1988 #define IWX_SYSTEM_GROUP 0x2 1989 #define IWX_MAC_CONF_GROUP 0x3 1990 #define IWX_PHY_OPS_GROUP 0x4 1991 #define IWX_DATA_PATH_GROUP 0x5 1992 #define IWX_PROT_OFFLOAD_GROUP 0xb 1993 #define IWX_REGULATORY_AND_NVM_GROUP 0xc 1994 1995 /* SYSTEM_GROUP group subcommand IDs */ 1996 1997 #define IWX_SHARED_MEM_CFG_CMD 0x00 1998 #define IWX_SOC_CONFIGURATION_CMD 0x01 1999 #define IWX_INIT_EXTENDED_CFG_CMD 0x03 2000 #define IWX_FW_ERROR_RECOVERY_CMD 0x07 2001 2002 /* MAC_CONF group subcommand IDs */ 2003 #define IWX_SESSION_PROTECTION_CMD 0x05 2004 #define IWX_SESSION_PROTECTION_NOTIF 0xfb 2005 2006 /* DATA_PATH group subcommand IDs */ 2007 #define IWX_DQA_ENABLE_CMD 0x00 2008 #define IWX_RLC_CONFIG_CMD 0x08 2009 #define IWX_TLC_MNG_CONFIG_CMD 0x0f 2010 #define IWX_RX_BAID_ALLOCATION_CONFIG_CMD 0x16 2011 #define IWX_RX_NO_DATA_NOTIF 0xf5 2012 #define IWX_TLC_MNG_UPDATE_NOTIF 0xf7 2013 2014 /* REGULATORY_AND_NVM group subcommand IDs */ 2015 #define IWX_NVM_ACCESS_COMPLETE 0x00 2016 #define IWX_NVM_GET_INFO 0x02 2017 #define IWX_NVM_GET_INFO 0x02 2018 #define IWX_PNVM_INIT_COMPLETE 0xfe 2019 2020 /* 2021 * struct iwx_dqa_enable_cmd 2022 * @cmd_queue: the TXQ number of the command queue 2023 */ 2024 struct iwx_dqa_enable_cmd { 2025 uint32_t cmd_queue; 2026 } __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */ 2027 2028 /** 2029 * struct iwx_cmd_response - generic response struct for most commands 2030 * @status: status of the command asked, changes for each one 2031 */ 2032 struct iwx_cmd_response { 2033 uint32_t status; 2034 }; 2035 2036 /* 2037 * struct iwx_tx_ant_cfg_cmd 2038 * @valid: valid antenna configuration 2039 */ 2040 struct iwx_tx_ant_cfg_cmd { 2041 uint32_t valid; 2042 } __packed; 2043 2044 /* 2045 * Calibration control struct. 2046 * Sent as part of the phy configuration command. 2047 * @flow_trigger: bitmap for which calibrations to perform according to 2048 * flow triggers. 2049 * @event_trigger: bitmap for which calibrations to perform according to 2050 * event triggers. 2051 */ 2052 struct iwx_calib_ctrl { 2053 uint32_t flow_trigger; 2054 uint32_t event_trigger; 2055 } __packed; 2056 2057 /* This defines the bitmap of various calibrations to enable in both 2058 * init ucode and runtime ucode through IWX_CALIBRATION_CFG_CMD. 2059 */ 2060 #define IWX_CALIB_CFG_XTAL_IDX (1 << 0) 2061 #define IWX_CALIB_CFG_TEMPERATURE_IDX (1 << 1) 2062 #define IWX_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2) 2063 #define IWX_CALIB_CFG_PAPD_IDX (1 << 3) 2064 #define IWX_CALIB_CFG_TX_PWR_IDX (1 << 4) 2065 #define IWX_CALIB_CFG_DC_IDX (1 << 5) 2066 #define IWX_CALIB_CFG_BB_FILTER_IDX (1 << 6) 2067 #define IWX_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7) 2068 #define IWX_CALIB_CFG_TX_IQ_IDX (1 << 8) 2069 #define IWX_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9) 2070 #define IWX_CALIB_CFG_RX_IQ_IDX (1 << 10) 2071 #define IWX_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11) 2072 #define IWX_CALIB_CFG_SENSITIVITY_IDX (1 << 12) 2073 #define IWX_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13) 2074 #define IWX_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14) 2075 #define IWX_CALIB_CFG_ANT_COUPLING_IDX (1 << 15) 2076 #define IWX_CALIB_CFG_DAC_IDX (1 << 16) 2077 #define IWX_CALIB_CFG_ABS_IDX (1 << 17) 2078 #define IWX_CALIB_CFG_AGC_IDX (1 << 18) 2079 2080 /* 2081 * Phy configuration command. 2082 */ 2083 struct iwx_phy_cfg_cmd { 2084 uint32_t phy_cfg; 2085 struct iwx_calib_ctrl calib_control; 2086 } __packed; 2087 2088 #define IWX_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 2089 #define IWX_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 2090 #define IWX_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 2091 #define IWX_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 2092 #define IWX_PHY_CFG_TX_CHAIN_A (1 << 8) 2093 #define IWX_PHY_CFG_TX_CHAIN_B (1 << 9) 2094 #define IWX_PHY_CFG_TX_CHAIN_C (1 << 10) 2095 #define IWX_PHY_CFG_RX_CHAIN_A (1 << 12) 2096 #define IWX_PHY_CFG_RX_CHAIN_B (1 << 13) 2097 #define IWX_PHY_CFG_RX_CHAIN_C (1 << 14) 2098 2099 #define IWX_MAX_DTS_TRIPS 8 2100 2101 /** 2102 * struct iwx_ct_kill_notif - CT-kill entry notification 2103 * 2104 * @temperature: the current temperature in celsius 2105 * @reserved: reserved 2106 */ 2107 struct iwx_ct_kill_notif { 2108 uint16_t temperature; 2109 uint16_t reserved; 2110 } __packed; /* GRP_PHY_CT_KILL_NTF */ 2111 2112 /** 2113 * struct iwx_temp_report_ths_cmd - set temperature thresholds 2114 * (IWX_TEMP_REPORTING_THRESHOLDS_CMD) 2115 * 2116 * @num_temps: number of temperature thresholds passed 2117 * @thresholds: array with the thresholds to be configured 2118 */ 2119 struct iwx_temp_report_ths_cmd { 2120 uint32_t num_temps; 2121 uint16_t thresholds[IWX_MAX_DTS_TRIPS]; 2122 } __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */ 2123 2124 /* 2125 * channel flags in NVM 2126 * @IWX_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 2127 * @IWX_NVM_CHANNEL_IBSS: usable as an IBSS channel 2128 * @IWX_NVM_CHANNEL_ACTIVE: active scanning allowed 2129 * @IWX_NVM_CHANNEL_RADAR: radar detection required 2130 * @IWX_NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 2131 * @IWX_NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 2132 * on same channel on 2.4 or same UNII band on 5.2 2133 * @IWX_NVM_CHANNEL_DFS: dynamic freq selection candidate 2134 * @IWX_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 2135 * @IWX_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 2136 * @IWX_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 2137 * @IWX_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 2138 * @IWX_NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 2139 */ 2140 #define IWX_NVM_CHANNEL_VALID (1 << 0) 2141 #define IWX_NVM_CHANNEL_IBSS (1 << 1) 2142 #define IWX_NVM_CHANNEL_ACTIVE (1 << 3) 2143 #define IWX_NVM_CHANNEL_RADAR (1 << 4) 2144 #define IWX_NVM_CHANNEL_INDOOR_ONLY (1 << 5) 2145 #define IWX_NVM_CHANNEL_GO_CONCURRENT (1 << 6) 2146 #define IWX_NVM_CHANNEL_DFS (1 << 7) 2147 #define IWX_NVM_CHANNEL_WIDE (1 << 8) 2148 #define IWX_NVM_CHANNEL_40MHZ (1 << 9) 2149 #define IWX_NVM_CHANNEL_80MHZ (1 << 10) 2150 #define IWX_NVM_CHANNEL_160MHZ (1 << 11) 2151 #define IWX_NVM_CHANNEL_DC_HIGH (1 << 12) 2152 2153 /** 2154 * struct iwx_nvm_access_complete_cmd - NVM_ACCESS commands are completed 2155 * @reserved: reserved 2156 */ 2157 struct iwx_nvm_access_complete_cmd { 2158 uint32_t reserved; 2159 } __packed; /* NVM_ACCESS_COMPLETE_CMD_API_S_VER_1 */ 2160 2161 /* 2162 * struct iwx_nvm_get_info - request to get NVM data 2163 */ 2164 struct iwx_nvm_get_info { 2165 uint32_t reserved; 2166 } __packed; /* REGULATORY_NVM_GET_INFO_CMD_API_S_VER_1 */ 2167 2168 /** 2169 * enum iwx_nvm_info_general_flags - flags in NVM_GET_INFO resp 2170 * @NVM_GENERAL_FLAGS_EMPTY_OTP: 1 if OTP is empty 2171 */ 2172 #define IWX_NVM_GENERAL_FLAGS_EMPTY_OTP (1 << 0) 2173 2174 /** 2175 * struct iwx_nvm_get_info_general - general NVM data 2176 * @flags: bit 0: 1 - empty, 0 - non-empty 2177 * @nvm_version: nvm version 2178 * @board_type: board type 2179 * @n_hw_addrs: number of reserved MAC addresses 2180 */ 2181 struct iwx_nvm_get_info_general { 2182 uint32_t flags; 2183 uint16_t nvm_version; 2184 uint8_t board_type; 2185 uint8_t n_hw_addrs; 2186 } __packed; /* REGULATORY_NVM_GET_INFO_GENERAL_S_VER_2 */ 2187 2188 /** 2189 * iwx_nvm_mac_sku_flags - flags in &iwl_nvm_get_info_sku 2190 * @NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED: true if 2.4 band enabled 2191 * @NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED: true if 5.2 band enabled 2192 * @NVM_MAC_SKU_FLAGS_802_11N_ENABLED: true if 11n enabled 2193 * @NVM_MAC_SKU_FLAGS_802_11AC_ENABLED: true if 11ac enabled 2194 * @NVM_MAC_SKU_FLAGS_802_11AX_ENABLED: true if 11ax enabled 2195 * @NVM_MAC_SKU_FLAGS_MIMO_DISABLED: true if MIMO disabled 2196 * @NVM_MAC_SKU_FLAGS_WAPI_ENABLED: true if WAPI enabled 2197 * @NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED: true if regulatory checker enabled 2198 * @NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED: true if API lock enabled 2199 */ 2200 #define IWX_NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED (1 << 0) 2201 #define IWX_NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED (1 << 1) 2202 #define IWX_NVM_MAC_SKU_FLAGS_802_11N_ENABLED (1 << 2) 2203 #define IWX_NVM_MAC_SKU_FLAGS_802_11AC_ENABLED (1 << 3) 2204 #define IWX_NVM_MAC_SKU_FLAGS_802_11AX_ENABLED (1 << 4) 2205 #define IWX_NVM_MAC_SKU_FLAGS_MIMO_DISABLED (1 << 5) 2206 #define IWX_NVM_MAC_SKU_FLAGS_WAPI_ENABLED (1 << 8) 2207 #define IWX_NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED (1 << 14) 2208 #define IWX_NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED (1 << 15) 2209 2210 /** 2211 * struct iwx_nvm_get_info_sku - mac information 2212 * @mac_sku_flags: flags for SKU, see &enum iwl_nvm_mac_sku_flags 2213 */ 2214 struct iwx_nvm_get_info_sku { 2215 uint32_t mac_sku_flags; 2216 } __packed; /* REGULATORY_NVM_GET_INFO_MAC_SKU_SECTION_S_VER_2 */ 2217 2218 /** 2219 * struct iwx_nvm_get_info_phy - phy information 2220 * @tx_chains: BIT 0 chain A, BIT 1 chain B 2221 * @rx_chains: BIT 0 chain A, BIT 1 chain B 2222 */ 2223 struct iwx_nvm_get_info_phy { 2224 uint32_t tx_chains; 2225 uint32_t rx_chains; 2226 } __packed; /* REGULATORY_NVM_GET_INFO_PHY_SKU_SECTION_S_VER_1 */ 2227 2228 #define IWX_NUM_CHANNELS_V1 51 2229 #define IWX_NUM_CHANNELS 110 2230 2231 /** 2232 * struct iwx_nvm_get_info_regulatory - regulatory information 2233 * @lar_enabled: is LAR enabled 2234 * @channel_profile: regulatory data of this channel 2235 * @reserved: reserved 2236 */ 2237 struct iwx_nvm_get_info_regulatory_v1 { 2238 uint32_t lar_enabled; 2239 uint16_t channel_profile[IWX_NUM_CHANNELS_V1]; 2240 uint16_t reserved; 2241 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_1 */ 2242 2243 /** 2244 * struct iwx_nvm_get_info_regulatory - regulatory information 2245 * @lar_enabled: is LAR enabled 2246 * @n_channels: number of valid channels in the array 2247 * @channel_profile: regulatory data of this channel 2248 */ 2249 struct iwx_nvm_get_info_regulatory { 2250 uint32_t lar_enabled; 2251 uint32_t n_channels; 2252 uint32_t channel_profile[IWX_NUM_CHANNELS]; 2253 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_2 */ 2254 2255 /** 2256 * struct iwx_nvm_get_info_rsp_v3 - response to get NVM data 2257 * @general: general NVM data 2258 * @mac_sku: data relating to MAC sku 2259 * @phy_sku: data relating to PHY sku 2260 * @regulatory: regulatory data 2261 */ 2262 struct iwx_nvm_get_info_rsp_v3 { 2263 struct iwx_nvm_get_info_general general; 2264 struct iwx_nvm_get_info_sku mac_sku; 2265 struct iwx_nvm_get_info_phy phy_sku; 2266 struct iwx_nvm_get_info_regulatory_v1 regulatory; 2267 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_3 */ 2268 2269 /** 2270 * struct iwx_nvm_get_info_rsp - response to get NVM data 2271 * @general: general NVM data 2272 * @mac_sku: data relating to MAC sku 2273 * @phy_sku: data relating to PHY sku 2274 * @regulatory: regulatory data 2275 */ 2276 struct iwx_nvm_get_info_rsp { 2277 struct iwx_nvm_get_info_general general; 2278 struct iwx_nvm_get_info_sku mac_sku; 2279 struct iwx_nvm_get_info_phy phy_sku; 2280 struct iwx_nvm_get_info_regulatory regulatory; 2281 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_4 */ 2282 2283 2284 #define IWX_ALIVE_STATUS_ERR 0xDEAD 2285 #define IWX_ALIVE_STATUS_OK 0xCAFE 2286 2287 struct iwx_lmac_debug_addrs { 2288 uint32_t error_event_table_ptr; /* SRAM address for error log */ 2289 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 2290 uint32_t cpu_register_ptr; 2291 uint32_t dbgm_config_ptr; 2292 uint32_t alive_counter_ptr; 2293 uint32_t scd_base_ptr; /* SRAM address for SCD */ 2294 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 2295 uint32_t st_fwrd_size; 2296 } __packed; /* UCODE_DEBUG_ADDRS_API_S_VER_2 */ 2297 2298 struct iwx_lmac_alive { 2299 uint32_t ucode_major; 2300 uint32_t ucode_minor; 2301 uint8_t ver_subtype; 2302 uint8_t ver_type; 2303 uint8_t mac; 2304 uint8_t opt; 2305 uint32_t timestamp; 2306 struct iwx_lmac_debug_addrs dbg_ptrs; 2307 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */ 2308 2309 struct iwx_umac_debug_addrs { 2310 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 2311 uint32_t dbg_print_buff_addr; 2312 } __packed; /* UMAC_DEBUG_ADDRS_API_S_VER_1 */ 2313 2314 struct iwx_umac_alive { 2315 uint32_t umac_major; /* UMAC version: major */ 2316 uint32_t umac_minor; /* UMAC version: minor */ 2317 struct iwx_umac_debug_addrs dbg_ptrs; 2318 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */ 2319 2320 struct iwx_alive_resp_v4 { 2321 uint16_t status; 2322 uint16_t flags; 2323 struct iwx_lmac_alive lmac_data[2]; 2324 struct iwx_umac_alive umac_data; 2325 } __packed; /* ALIVE_RES_API_S_VER_4 */ 2326 2327 struct iwx_sku_id { 2328 uint32_t data[3]; 2329 } __packed; /* SKU_ID_API_S_VER_1 */ 2330 2331 struct iwx_alive_resp_v5 { 2332 uint16_t status; 2333 uint16_t flags; 2334 struct iwx_lmac_alive lmac_data[2]; 2335 struct iwx_umac_alive umac_data; 2336 struct iwx_sku_id sku_id; 2337 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_5 */ 2338 2339 struct iwx_imr_alive_info { 2340 uint64_t base_addr; 2341 uint32_t size; 2342 uint32_t enabled; 2343 } __packed; /* IMR_ALIVE_INFO_API_S_VER_1 */ 2344 2345 struct iwx_alive_resp_v6 { 2346 uint16_t status; 2347 uint16_t flags; 2348 struct iwx_lmac_alive lmac_data[2]; 2349 struct iwx_umac_alive umac_data; 2350 struct iwx_sku_id sku_id; 2351 struct iwx_imr_alive_info imr; 2352 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_6 */ 2353 2354 2355 #define IWX_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0) 2356 #define IWX_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1) 2357 2358 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc 2359 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0 2360 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_200 1 2361 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_2500 2 2362 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_1820 3 2363 2364 /** 2365 * struct iwx_soc_configuration_cmd - Set device stabilization latency 2366 * 2367 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE 2368 * flag, because the FW treats the whole value as an integer. In 2369 * VER_2, we can set the bits independently. 2370 * @latency: time for SOC to ensure stable power & XTAL 2371 */ 2372 struct iwx_soc_configuration_cmd { 2373 uint32_t flags; 2374 uint32_t latency; 2375 } __packed; /* 2376 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above) 2377 * SOC_CONFIGURATION_CMD_S_VER_2 2378 */ 2379 2380 /** 2381 * commands driver may send before finishing init flow 2382 * @IWX_INIT_DEBUG_CFG: driver is going to send debug config command 2383 * @IWX_INIT_NVM: driver is going to send NVM_ACCESS commands 2384 */ 2385 #define IWX_INIT_DEBUG_CFG (1 << 0) 2386 #define IWX_INIT_NVM (1 << 1) 2387 2388 /** 2389 * struct iwx_extended_cfg_cmd - mark what commands ucode should wait for 2390 * before finishing init flows 2391 * @init_flags: IWX_INIT_* flag bits 2392 */ 2393 struct iwx_init_extended_cfg_cmd { 2394 uint32_t init_flags; 2395 } __packed; /* INIT_EXTENDED_CFG_CMD_API_S_VER_1 */ 2396 2397 /* Error response/notification */ 2398 #define IWX_FW_ERR_UNKNOWN_CMD 0x0 2399 #define IWX_FW_ERR_INVALID_CMD_PARAM 0x1 2400 #define IWX_FW_ERR_SERVICE 0x2 2401 #define IWX_FW_ERR_ARC_MEMORY 0x3 2402 #define IWX_FW_ERR_ARC_CODE 0x4 2403 #define IWX_FW_ERR_WATCH_DOG 0x5 2404 #define IWX_FW_ERR_WEP_GRP_KEY_INDX 0x10 2405 #define IWX_FW_ERR_WEP_KEY_SIZE 0x11 2406 #define IWX_FW_ERR_OBSOLETE_FUNC 0x12 2407 #define IWX_FW_ERR_UNEXPECTED 0xFE 2408 #define IWX_FW_ERR_FATAL 0xFF 2409 2410 /** 2411 * struct iwx_error_resp - FW error indication 2412 * ( IWX_REPLY_ERROR = 0x2 ) 2413 * @error_type: one of IWX_FW_ERR_* 2414 * @cmd_id: the command ID for which the error occurred 2415 * @bad_cmd_seq_num: sequence number of the erroneous command 2416 * @error_service: which service created the error, applicable only if 2417 * error_type = 2, otherwise 0 2418 * @timestamp: TSF in usecs. 2419 */ 2420 struct iwx_error_resp { 2421 uint32_t error_type; 2422 uint8_t cmd_id; 2423 uint8_t reserved1; 2424 uint16_t bad_cmd_seq_num; 2425 uint32_t error_service; 2426 uint64_t timestamp; 2427 } __packed; 2428 2429 enum iwx_fw_dbg_reg_operator { 2430 CSR_ASSIGN, 2431 CSR_SETBIT, 2432 CSR_CLEARBIT, 2433 2434 PRPH_ASSIGN, 2435 PRPH_SETBIT, 2436 PRPH_CLEARBIT, 2437 2438 INDIRECT_ASSIGN, 2439 INDIRECT_SETBIT, 2440 INDIRECT_CLEARBIT, 2441 2442 PRPH_BLOCKBIT, 2443 }; 2444 2445 /** 2446 * struct iwx_fw_dbg_reg_op - an operation on a register 2447 * 2448 * @op: &enum iwx_fw_dbg_reg_operator 2449 * @addr: offset of the register 2450 * @val: value 2451 */ 2452 struct iwx_fw_dbg_reg_op { 2453 uint8_t op; 2454 uint8_t reserved[3]; 2455 uint32_t addr; 2456 uint32_t val; 2457 } __packed; 2458 2459 /** 2460 * enum iwx_fw_dbg_monitor_mode - available monitor recording modes 2461 * 2462 * @SMEM_MODE: monitor stores the data in SMEM 2463 * @EXTERNAL_MODE: monitor stores the data in allocated DRAM 2464 * @MARBH_MODE: monitor stores the data in MARBH buffer 2465 * @MIPI_MODE: monitor outputs the data through the MIPI interface 2466 */ 2467 enum iwx_fw_dbg_monitor_mode { 2468 SMEM_MODE = 0, 2469 EXTERNAL_MODE = 1, 2470 MARBH_MODE = 2, 2471 MIPI_MODE = 3, 2472 }; 2473 2474 /** 2475 * struct iwx_fw_dbg_mem_seg_tlv - configures the debug data memory segments 2476 * 2477 * @data_type: the memory segment type to record 2478 * @ofs: the memory segment offset 2479 * @len: the memory segment length, in bytes 2480 * 2481 * This parses IWX_UCODE_TLV_FW_MEM_SEG 2482 */ 2483 struct iwx_fw_dbg_mem_seg_tlv { 2484 uint32_t data_type; 2485 uint32_t ofs; 2486 uint32_t len; 2487 } __packed; 2488 2489 /** 2490 * struct iwx_fw_dbg_dest_tlv_v1 - configures the destination of the debug data 2491 * 2492 * @version: version of the TLV - currently 0 2493 * @monitor_mode: &enum iwx_fw_dbg_monitor_mode 2494 * @size_power: buffer size will be 2^(size_power + 11) 2495 * @base_reg: addr of the base addr register (PRPH) 2496 * @end_reg: addr of the end addr register (PRPH) 2497 * @write_ptr_reg: the addr of the reg of the write pointer 2498 * @wrap_count: the addr of the reg of the wrap_count 2499 * @base_shift: shift right of the base addr reg 2500 * @end_shift: shift right of the end addr reg 2501 * @reg_ops: array of registers operations 2502 * 2503 * This parses IWX_UCODE_TLV_FW_DBG_DEST 2504 */ 2505 struct iwx_fw_dbg_dest_tlv_v1 { 2506 uint8_t version; 2507 uint8_t monitor_mode; 2508 uint8_t size_power; 2509 uint8_t reserved; 2510 uint32_t base_reg; 2511 uint32_t end_reg; 2512 uint32_t write_ptr_reg; 2513 uint32_t wrap_count; 2514 uint8_t base_shift; 2515 uint8_t end_shift; 2516 struct iwx_fw_dbg_reg_op reg_ops[0]; 2517 } __packed; 2518 2519 /* Mask of the register for defining the LDBG MAC2SMEM buffer SMEM size */ 2520 #define IWX_LDBG_M2S_BUF_SIZE_MSK 0x0fff0000 2521 /* Mask of the register for defining the LDBG MAC2SMEM SMEM base address */ 2522 #define IWX_LDBG_M2S_BUF_BA_MSK 0x00000fff 2523 /* The smem buffer chunks are in units of 256 bits */ 2524 #define IWX_M2S_UNIT_SIZE 0x100 2525 2526 struct iwx_fw_dbg_dest_tlv { 2527 uint8_t version; 2528 uint8_t monitor_mode; 2529 uint8_t size_power; 2530 uint8_t reserved; 2531 uint32_t cfg_reg; 2532 uint32_t write_ptr_reg; 2533 uint32_t wrap_count; 2534 uint8_t base_shift; 2535 uint8_t size_shift; 2536 struct iwx_fw_dbg_reg_op reg_ops[0]; 2537 } __packed; 2538 2539 struct iwx_fw_dbg_conf_hcmd { 2540 uint8_t id; 2541 uint8_t reserved; 2542 uint16_t len; 2543 uint8_t data[0]; 2544 } __packed; 2545 2546 /** 2547 * enum iwx_fw_dbg_trigger_mode - triggers functionalities 2548 * 2549 * @IWX_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism 2550 * @IWX_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data 2551 * @IWX_FW_DBG_TRIGGER_MONITOR_ONLY: when trigger occurs trigger is set to 2552 * collect only monitor data 2553 */ 2554 enum iwx_fw_dbg_trigger_mode { 2555 IWX_FW_DBG_TRIGGER_START = (1 << 0), 2556 IWX_FW_DBG_TRIGGER_STOP = (1 << 1), 2557 IWX_FW_DBG_TRIGGER_MONITOR_ONLY = (1 << 2), 2558 }; 2559 2560 /** 2561 * enum iwx_fw_dbg_trigger_flags - the flags supported by wrt triggers 2562 * @IWX_FW_DBG_FORCE_RESTART: force a firmware restart 2563 */ 2564 enum iwx_fw_dbg_trigger_flags { 2565 IWX_FW_DBG_FORCE_RESTART = (1 << 0), 2566 }; 2567 2568 /** 2569 * enum iwx_fw_dbg_trigger_vif_type - define the VIF type for a trigger 2570 * @IWX_FW_DBG_CONF_VIF_ANY: any vif type 2571 * @IWX_FW_DBG_CONF_VIF_IBSS: IBSS mode 2572 * @IWX_FW_DBG_CONF_VIF_STATION: BSS mode 2573 * @IWX_FW_DBG_CONF_VIF_AP: AP mode 2574 * @IWX_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode 2575 * @IWX_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode 2576 * @IWX_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device 2577 * @IWX_FW_DBG_CONF_VIF_NAN: NAN device 2578 */ 2579 enum iwx_fw_dbg_trigger_vif_type { 2580 IWX_FW_DBG_CONF_VIF_ANY = 0, 2581 IWX_FW_DBG_CONF_VIF_IBSS = 1, 2582 IWX_FW_DBG_CONF_VIF_STATION = 2, 2583 IWX_FW_DBG_CONF_VIF_AP = 3, 2584 IWX_FW_DBG_CONF_VIF_P2P_CLIENT = 8, 2585 IWX_FW_DBG_CONF_VIF_P2P_GO = 9, 2586 IWX_FW_DBG_CONF_VIF_P2P_DEVICE = 10, 2587 IWX_FW_DBG_CONF_VIF_NAN = 12, 2588 }; 2589 2590 /** 2591 * enum iwl_fw_dbg_trigger - triggers available 2592 * 2593 * @FW_DBG_TRIGGER_USER: trigger log collection by user 2594 * This should not be defined as a trigger to the driver, but a value the 2595 * driver should set to indicate that the trigger was initiated by the 2596 * user. 2597 * @FW_DBG_TRIGGER_FW_ASSERT: trigger log collection when the firmware asserts 2598 * @FW_DBG_TRIGGER_MISSED_BEACONS: trigger log collection when beacons are 2599 * missed. 2600 * @FW_DBG_TRIGGER_CHANNEL_SWITCH: trigger log collection upon channel switch. 2601 * @FW_DBG_TRIGGER_FW_NOTIF: trigger log collection when the firmware sends a 2602 * command response or a notification. 2603 * @FW_DBG_TRIGGER_MLME: trigger log collection upon MLME event. 2604 * @FW_DBG_TRIGGER_STATS: trigger log collection upon statistics threshold. 2605 * @FW_DBG_TRIGGER_RSSI: trigger log collection when the rssi of the beacon 2606 * goes below a threshold. 2607 * @FW_DBG_TRIGGER_TXQ_TIMERS: configures the timers for the Tx queue hang 2608 * detection. 2609 * @FW_DBG_TRIGGER_TIME_EVENT: trigger log collection upon time events related 2610 * events. 2611 * @FW_DBG_TRIGGER_BA: trigger log collection upon BlockAck related events. 2612 * @FW_DBG_TX_LATENCY: trigger log collection when the tx latency goes above a 2613 * threshold. 2614 * @FW_DBG_TDLS: trigger log collection upon TDLS related events. 2615 * @FW_DBG_TRIGGER_TX_STATUS: trigger log collection upon tx status when 2616 * the firmware sends a tx reply. 2617 * @FW_DBG_TRIGGER_USER_EXTENDED: trigger log collection upon user space 2618 * request. 2619 * @FW_DBG_TRIGGER_ALIVE_TIMEOUT: trigger log collection if alive flow timeouts 2620 * @FW_DBG_TRIGGER_DRIVER: trigger log collection upon a flow failure 2621 * in the driver. 2622 */ 2623 enum iwx_fw_dbg_trigger { 2624 IWX_FW_DBG_TRIGGER_INVALID = 0, 2625 IWX_FW_DBG_TRIGGER_USER, 2626 IWX_FW_DBG_TRIGGER_FW_ASSERT, 2627 IWX_FW_DBG_TRIGGER_MISSED_BEACONS, 2628 IWX_FW_DBG_TRIGGER_CHANNEL_SWITCH, 2629 IWX_FW_DBG_TRIGGER_FW_NOTIF, 2630 IWX_FW_DBG_TRIGGER_MLME, 2631 IWX_FW_DBG_TRIGGER_STATS, 2632 IWX_FW_DBG_TRIGGER_RSSI, 2633 IWX_FW_DBG_TRIGGER_TXQ_TIMERS, 2634 IWX_FW_DBG_TRIGGER_TIME_EVENT, 2635 IWX_FW_DBG_TRIGGER_BA, 2636 IWX_FW_DBG_TRIGGER_TX_LATENCY, 2637 IWX_FW_DBG_TRIGGER_TDLS, 2638 IWX_FW_DBG_TRIGGER_TX_STATUS, 2639 IWX_FW_DBG_TRIGGER_USER_EXTENDED, 2640 IWX_FW_DBG_TRIGGER_ALIVE_TIMEOUT, 2641 IWX_FW_DBG_TRIGGER_DRIVER, 2642 2643 /* must be last */ 2644 IWX_FW_DBG_TRIGGER_MAX, 2645 }; 2646 2647 2648 /** 2649 * struct iwx_fw_dbg_trigger_tlv - a TLV that describes the trigger 2650 * @id: &enum iwx_fw_dbg_trigger 2651 * @vif_type: &enum iwx_fw_dbg_trigger_vif_type 2652 * @stop_conf_ids: bitmap of configurations this trigger relates to. 2653 * if the mode is %IWX_FW_DBG_TRIGGER_STOP, then if the bit corresponding 2654 * to the currently running configuration is set, the data should be 2655 * collected. 2656 * @stop_delay: how many milliseconds to wait before collecting the data 2657 * after the STOP trigger fires. 2658 * @mode: &enum iwx_fw_dbg_trigger_mode - can be stop / start of both 2659 * @start_conf_id: if mode is %IWX_FW_DBG_TRIGGER_START, this defines what 2660 * configuration should be applied when the triggers kicks in. 2661 * @occurrences: number of occurrences. 0 means the trigger will never fire. 2662 * @trig_dis_ms: the time, in milliseconds, after an occurrence of this 2663 * trigger in which another occurrence should be ignored. 2664 * @flags: &enum iwx_fw_dbg_trigger_flags 2665 */ 2666 struct iwx_fw_dbg_trigger_tlv { 2667 uint32_t id; 2668 uint32_t vif_type; 2669 uint32_t stop_conf_ids; 2670 uint32_t stop_delay; 2671 uint8_t mode; 2672 uint8_t start_conf_id; 2673 uint16_t occurrences; 2674 uint16_t trig_dis_ms; 2675 uint8_t flags; 2676 uint8_t reserved[5]; 2677 2678 uint8_t data[0]; 2679 } __packed; 2680 2681 #define IWX_FW_DBG_START_FROM_ALIVE 0 2682 #define IWX_FW_DBG_CONF_MAX 32 2683 #define IWX_FW_DBG_INVALID 0xff 2684 2685 /** 2686 * struct iwx_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons 2687 * @stop_consec_missed_bcon: stop recording if threshold is crossed. 2688 * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed. 2689 * @start_consec_missed_bcon: start recording if threshold is crossed. 2690 * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed. 2691 * @reserved1: reserved 2692 * @reserved2: reserved 2693 */ 2694 struct iwx_fw_dbg_trigger_missed_bcon { 2695 uint32_t stop_consec_missed_bcon; 2696 uint32_t stop_consec_missed_bcon_since_rx; 2697 uint32_t reserved2[2]; 2698 uint32_t start_consec_missed_bcon; 2699 uint32_t start_consec_missed_bcon_since_rx; 2700 uint32_t reserved1[2]; 2701 } __packed; 2702 2703 /** 2704 * struct iwx_fw_dbg_trigger_cmd - configures trigger for messages from FW. 2705 * cmds: the list of commands to trigger the collection on 2706 */ 2707 struct iwx_fw_dbg_trigger_cmd { 2708 struct cmd { 2709 uint8_t cmd_id; 2710 uint8_t group_id; 2711 } __packed cmds[16]; 2712 } __packed; 2713 2714 /** 2715 * iwx_fw_dbg_trigger_stats - configures trigger for statistics 2716 * @stop_offset: the offset of the value to be monitored 2717 * @stop_threshold: the threshold above which to collect 2718 * @start_offset: the offset of the value to be monitored 2719 * @start_threshold: the threshold above which to start recording 2720 */ 2721 struct iwx_fw_dbg_trigger_stats { 2722 uint32_t stop_offset; 2723 uint32_t stop_threshold; 2724 uint32_t start_offset; 2725 uint32_t start_threshold; 2726 } __packed; 2727 2728 /** 2729 * struct iwx_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI 2730 * @rssi: RSSI value to trigger at 2731 */ 2732 struct iwx_fw_dbg_trigger_low_rssi { 2733 uint32_t rssi; 2734 } __packed; 2735 2736 /** 2737 * struct iwx_fw_dbg_trigger_mlme - configures trigger for mlme events 2738 * @stop_auth_denied: number of denied authentication to collect 2739 * @stop_auth_timeout: number of authentication timeout to collect 2740 * @stop_rx_deauth: number of Rx deauth before to collect 2741 * @stop_tx_deauth: number of Tx deauth before to collect 2742 * @stop_assoc_denied: number of denied association to collect 2743 * @stop_assoc_timeout: number of association timeout to collect 2744 * @stop_connection_loss: number of connection loss to collect 2745 * @start_auth_denied: number of denied authentication to start recording 2746 * @start_auth_timeout: number of authentication timeout to start recording 2747 * @start_rx_deauth: number of Rx deauth to start recording 2748 * @start_tx_deauth: number of Tx deauth to start recording 2749 * @start_assoc_denied: number of denied association to start recording 2750 * @start_assoc_timeout: number of association timeout to start recording 2751 * @start_connection_loss: number of connection loss to start recording 2752 */ 2753 struct iwx_fw_dbg_trigger_mlme { 2754 uint8_t stop_auth_denied; 2755 uint8_t stop_auth_timeout; 2756 uint8_t stop_rx_deauth; 2757 uint8_t stop_tx_deauth; 2758 2759 uint8_t stop_assoc_denied; 2760 uint8_t stop_assoc_timeout; 2761 uint8_t stop_connection_loss; 2762 uint8_t reserved; 2763 2764 uint8_t start_auth_denied; 2765 uint8_t start_auth_timeout; 2766 uint8_t start_rx_deauth; 2767 uint8_t start_tx_deauth; 2768 2769 uint8_t start_assoc_denied; 2770 uint8_t start_assoc_timeout; 2771 uint8_t start_connection_loss; 2772 uint8_t reserved2; 2773 } __packed; 2774 2775 /** 2776 * struct iwx_fw_dbg_trigger_txq_timer - configures the Tx queue's timer 2777 * @command_queue: timeout for the command queue in ms 2778 * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms 2779 * @softap: timeout for the queues of a softAP in ms 2780 * @p2p_go: timeout for the queues of a P2P GO in ms 2781 * @p2p_client: timeout for the queues of a P2P client in ms 2782 * @p2p_device: timeout for the queues of a P2P device in ms 2783 * @ibss: timeout for the queues of an IBSS in ms 2784 * @tdls: timeout for the queues of a TDLS station in ms 2785 */ 2786 struct iwx_fw_dbg_trigger_txq_timer { 2787 uint32_t command_queue; 2788 uint32_t bss; 2789 uint32_t softap; 2790 uint32_t p2p_go; 2791 uint32_t p2p_client; 2792 uint32_t p2p_device; 2793 uint32_t ibss; 2794 uint32_t tdls; 2795 uint32_t reserved[4]; 2796 } __packed; 2797 2798 /** 2799 * struct iwx_fw_dbg_trigger_time_event - configures a time event trigger 2800 * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a 2801 * trigger each time a time event notification that relates to time event 2802 * id with one of the actions in the bitmap is received and 2803 * BIT(notif->status) is set in status_bitmap. 2804 * 2805 */ 2806 struct iwx_fw_dbg_trigger_time_event { 2807 struct { 2808 uint32_t id; 2809 uint32_t action_bitmap; 2810 uint32_t status_bitmap; 2811 } __packed time_events[16]; 2812 } __packed; 2813 2814 /** 2815 * struct iwx_fw_dbg_trigger_ba - configures BlockAck related trigger 2816 * rx_ba_start: tid bitmap to configure on what tid the trigger should occur 2817 * when an Rx BlockAck session is started. 2818 * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur 2819 * when an Rx BlockAck session is stopped. 2820 * tx_ba_start: tid bitmap to configure on what tid the trigger should occur 2821 * when a Tx BlockAck session is started. 2822 * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur 2823 * when a Tx BlockAck session is stopped. 2824 * rx_bar: tid bitmap to configure on what tid the trigger should occur 2825 * when a BAR is received (for a Tx BlockAck session). 2826 * tx_bar: tid bitmap to configure on what tid the trigger should occur 2827 * when a BAR is send (for an Rx BlocAck session). 2828 * frame_timeout: tid bitmap to configure on what tid the trigger should occur 2829 * when a frame times out in the reordering buffer. 2830 */ 2831 struct iwx_fw_dbg_trigger_ba { 2832 uint16_t rx_ba_start; 2833 uint16_t rx_ba_stop; 2834 uint16_t tx_ba_start; 2835 uint16_t tx_ba_stop; 2836 uint16_t rx_bar; 2837 uint16_t tx_bar; 2838 uint16_t frame_timeout; 2839 } __packed; 2840 2841 /** 2842 * struct iwx_fw_dbg_trigger_tx_latency - configures tx latency related trigger 2843 * @thrshold: the wanted threshold. 2844 * @tid_bitmap: the tid to apply the threshold on 2845 * @mode: recording mode (Internal buffer or continues recording) 2846 * @window: the size of the window before collecting. 2847 * @reserved: reserved. 2848 */ 2849 struct iwx_fw_dbg_trigger_tx_latency { 2850 uint32_t thrshold; 2851 uint16_t tid_bitmap; 2852 uint16_t mode; 2853 uint32_t window; 2854 uint32_t reserved[4]; 2855 } __packed; 2856 2857 /** 2858 * struct iwx_fw_dbg_trigger_tdls - configures trigger for TDLS events. 2859 * @action_bitmap: the TDLS action to trigger the collection upon 2860 * @peer_mode: trigger on specific peer or all 2861 * @peer: the TDLS peer to trigger the collection on 2862 */ 2863 struct iwx_fw_dbg_trigger_tdls { 2864 uint8_t action_bitmap; 2865 uint8_t peer_mode; 2866 uint8_t peer[ETHER_ADDR_LEN]; 2867 uint8_t reserved[4]; 2868 } __packed; 2869 2870 /** 2871 * struct iwx_fw_dbg_trigger_tx_status - configures trigger for tx response 2872 * status. 2873 * @statuses: the list of statuses to trigger the collection on 2874 */ 2875 struct iwx_fw_dbg_trigger_tx_status { 2876 struct tx_status { 2877 uint8_t status; 2878 uint8_t reserved[3]; 2879 } __packed statuses[16]; 2880 uint32_t reserved[2]; 2881 } __packed; 2882 2883 /** 2884 * struct iwx_fw_dbg_conf_tlv - a TLV that describes a debug configuration. 2885 * @id: conf id 2886 * @usniffer: should the uSniffer image be used 2887 * @num_of_hcmds: how many HCMDs to send are present here 2888 * @hcmd: a variable length host command to be sent to apply the configuration. 2889 * If there is more than one HCMD to send, they will appear one after the 2890 * other and be sent in the order that they appear in. 2891 * This parses IWX_UCODE_TLV_FW_DBG_CONF. The user can add up-to 2892 * %IWX_FW_DBG_CONF_MAX configuration per run. 2893 */ 2894 struct iwx_fw_dbg_conf_tlv { 2895 uint8_t id; 2896 uint8_t usniffer; 2897 uint8_t reserved; 2898 uint8_t num_of_hcmds; 2899 struct iwx_fw_dbg_conf_hcmd hcmd; 2900 } __packed; 2901 2902 #define IWX_FW_CMD_VER_UNKNOWN 99 2903 2904 /** 2905 * struct iwx_fw_cmd_version - firmware command version entry 2906 * @cmd: command ID 2907 * @group: group ID 2908 * @cmd_ver: command version 2909 * @notif_ver: notification version 2910 */ 2911 struct iwx_fw_cmd_version { 2912 uint8_t cmd; 2913 uint8_t group; 2914 uint8_t cmd_ver; 2915 uint8_t notif_ver; 2916 } __packed; 2917 2918 /* Common PHY, MAC and Bindings definitions */ 2919 2920 #define IWX_MAX_MACS_IN_BINDING (3) 2921 #define IWX_MAX_BINDINGS (4) 2922 #define IWX_AUX_BINDING_INDEX (3) 2923 #define IWX_MAX_PHYS (4) 2924 2925 /* Used to extract ID and color from the context dword */ 2926 #define IWX_FW_CTXT_ID_POS (0) 2927 #define IWX_FW_CTXT_ID_MSK (0xff << IWX_FW_CTXT_ID_POS) 2928 #define IWX_FW_CTXT_COLOR_POS (8) 2929 #define IWX_FW_CTXT_COLOR_MSK (0xff << IWX_FW_CTXT_COLOR_POS) 2930 #define IWX_FW_CTXT_INVALID (0xffffffff) 2931 2932 #define IWX_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWX_FW_CTXT_ID_POS) |\ 2933 (_color << IWX_FW_CTXT_COLOR_POS)) 2934 2935 /* Possible actions on PHYs, MACs and Bindings */ 2936 #define IWX_FW_CTXT_ACTION_STUB 0 2937 #define IWX_FW_CTXT_ACTION_ADD 1 2938 #define IWX_FW_CTXT_ACTION_MODIFY 2 2939 #define IWX_FW_CTXT_ACTION_REMOVE 3 2940 #define IWX_FW_CTXT_ACTION_NUM 4 2941 /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2942 2943 /* Time Events */ 2944 2945 /* Time Event types, according to MAC type */ 2946 2947 /* BSS Station Events */ 2948 #define IWX_TE_BSS_STA_AGGRESSIVE_ASSOC 0 2949 #define IWX_TE_BSS_STA_ASSOC 1 2950 #define IWX_TE_BSS_EAP_DHCP_PROT 2 2951 #define IWX_TE_BSS_QUIET_PERIOD 3 2952 2953 /* P2P Device Events */ 2954 #define IWX_TE_P2P_DEVICE_DISCOVERABLE 4 2955 #define IWX_TE_P2P_DEVICE_LISTEN 5 2956 #define IWX_TE_P2P_DEVICE_ACTION_SCAN 6 2957 #define IWX_TE_P2P_DEVICE_FULL_SCAN 7 2958 2959 /* P2P Client Events */ 2960 #define IWX_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8 2961 #define IWX_TE_P2P_CLIENT_ASSOC 9 2962 #define IWX_TE_P2P_CLIENT_QUIET_PERIOD 10 2963 2964 /* P2P GO Events */ 2965 #define IWX_TE_P2P_GO_ASSOC_PROT 11 2966 #define IWX_TE_P2P_GO_REPETITIVE_NOA 12 2967 #define IWX_TE_P2P_GO_CT_WINDOW 13 2968 2969 /* WiDi Sync Events */ 2970 #define IWX_TE_WIDI_TX_SYNC 14 2971 2972 /* Time event - defines for command API */ 2973 2974 /** 2975 * DOC: Time Events - what is it? 2976 * 2977 * Time Events are a fw feature that allows the driver to control the presence 2978 * of the device on the channel. Since the fw supports multiple channels 2979 * concurrently, the fw may choose to jump to another channel at any time. 2980 * In order to make sure that the fw is on a specific channel at a certain time 2981 * and for a certain duration, the driver needs to issue a time event. 2982 * 2983 * The simplest example is for BSS association. The driver issues a time event, 2984 * waits for it to start, and only then tells mac80211 that we can start the 2985 * association. This way, we make sure that the association will be done 2986 * smoothly and won't be interrupted by channel switch decided within the fw. 2987 */ 2988 2989 /** 2990 * DOC: The flow against the fw 2991 * 2992 * When the driver needs to make sure we are in a certain channel, at a certain 2993 * time and for a certain duration, it sends a Time Event. The flow against the 2994 * fw goes like this: 2995 * 1) Driver sends a TIME_EVENT_CMD to the fw 2996 * 2) Driver gets the response for that command. This response contains the 2997 * Unique ID (UID) of the event. 2998 * 3) The fw sends notification when the event starts. 2999 * 3000 * Of course the API provides various options that allow to cover parameters 3001 * of the flow. 3002 * What is the duration of the event? 3003 * What is the start time of the event? 3004 * Is there an end-time for the event? 3005 * How much can the event be delayed? 3006 * Can the event be split? 3007 * If yes what is the maximal number of chunks? 3008 * etc... 3009 */ 3010 3011 /* 3012 * @IWX_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 3013 * @IWX_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 3014 * the first fragment is scheduled. 3015 * @IWX_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 3016 * the first 2 fragments are scheduled. 3017 * @IWX_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 3018 * number of fragments are valid. 3019 * 3020 * Other than the constant defined above, specifying a fragmentation value 'x' 3021 * means that the event can be fragmented but only the first 'x' will be 3022 * scheduled. 3023 */ 3024 #define IWX_TE_V2_FRAG_NONE 0 3025 #define IWX_TE_V2_FRAG_SINGLE 1 3026 #define IWX_TE_V2_FRAG_DUAL 2 3027 #define IWX_TE_V2_FRAG_MAX 0xfe 3028 #define IWX_TE_V2_FRAG_ENDLESS 0xff 3029 3030 /* Repeat the time event endlessly (until removed) */ 3031 #define IWX_TE_V2_REPEAT_ENDLESS 0xff 3032 /* If a Time Event has bounded repetitions, this is the maximal value */ 3033 #define IWX_TE_V2_REPEAT_MAX 0xfe 3034 3035 #define IWX_TE_V2_PLACEMENT_POS 12 3036 #define IWX_TE_V2_ABSENCE_POS 15 3037 3038 /* Time event policy values 3039 * A notification (both event and fragment) includes a status indicating weather 3040 * the FW was able to schedule the event or not. For fragment start/end 3041 * notification the status is always success. There is no start/end fragment 3042 * notification for monolithic events. 3043 * 3044 * @IWX_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 3045 * @IWX_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 3046 * @IWX_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 3047 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 3048 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 3049 * @IWX_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 3050 * @IWX_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 3051 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 3052 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 3053 * @IWX_TE_V2_DEP_OTHER: depends on another time event 3054 * @IWX_TE_V2_DEP_TSF: depends on a specific time 3055 * @IWX_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of the same MAC 3056 * @IWX_TE_V2_ABSENCE: are we present or absent during the Time Event. 3057 */ 3058 #define IWX_TE_V2_DEFAULT_POLICY 0x0 3059 3060 /* notifications (event start/stop, fragment start/stop) */ 3061 #define IWX_TE_V2_NOTIF_HOST_EVENT_START (1 << 0) 3062 #define IWX_TE_V2_NOTIF_HOST_EVENT_END (1 << 1) 3063 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2) 3064 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3) 3065 3066 #define IWX_TE_V2_NOTIF_HOST_FRAG_START (1 << 4) 3067 #define IWX_TE_V2_NOTIF_HOST_FRAG_END (1 << 5) 3068 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6) 3069 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7) 3070 #define IWX_T2_V2_START_IMMEDIATELY (1 << 11) 3071 3072 #define IWX_TE_V2_NOTIF_MSK 0xff 3073 3074 /* placement characteristics */ 3075 #define IWX_TE_V2_DEP_OTHER (1 << IWX_TE_V2_PLACEMENT_POS) 3076 #define IWX_TE_V2_DEP_TSF (1 << (IWX_TE_V2_PLACEMENT_POS + 1)) 3077 #define IWX_TE_V2_EVENT_SOCIOPATHIC (1 << (IWX_TE_V2_PLACEMENT_POS + 2)) 3078 3079 /* are we present or absent during the Time Event. */ 3080 #define IWX_TE_V2_ABSENCE (1 << IWX_TE_V2_ABSENCE_POS) 3081 3082 /** 3083 * struct iwx_time_event_cmd_api - configuring Time Events 3084 * with struct IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 3085 * with version 1. determined by IWX_UCODE_TLV_FLAGS) 3086 * ( IWX_TIME_EVENT_CMD = 0x29 ) 3087 * @id_and_color: ID and color of the relevant MAC 3088 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3089 * @id: this field has two meanings, depending on the action: 3090 * If the action is ADD, then it means the type of event to add. 3091 * For all other actions it is the unique event ID assigned when the 3092 * event was added by the FW. 3093 * @apply_time: When to start the Time Event (in GP2) 3094 * @max_delay: maximum delay to event's start (apply time), in TU 3095 * @depends_on: the unique ID of the event we depend on (if any) 3096 * @interval: interval between repetitions, in TU 3097 * @duration: duration of event in TU 3098 * @repeat: how many repetitions to do, can be IWX_TE_REPEAT_ENDLESS 3099 * @max_frags: maximal number of fragments the Time Event can be divided to 3100 * @policy: defines whether uCode shall notify the host or other uCode modules 3101 * on event and/or fragment start and/or end 3102 * using one of IWX_TE_INDEPENDENT, IWX_TE_DEP_OTHER, IWX_TE_DEP_TSF 3103 * IWX_TE_EVENT_SOCIOPATHIC 3104 * using IWX_TE_ABSENCE and using IWX_TE_NOTIF_* 3105 */ 3106 struct iwx_time_event_cmd { 3107 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3108 uint32_t id_and_color; 3109 uint32_t action; 3110 uint32_t id; 3111 /* IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 3112 uint32_t apply_time; 3113 uint32_t max_delay; 3114 uint32_t depends_on; 3115 uint32_t interval; 3116 uint32_t duration; 3117 uint8_t repeat; 3118 uint8_t max_frags; 3119 uint16_t policy; 3120 } __packed; /* IWX_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 3121 3122 /** 3123 * struct iwx_time_event_resp - response structure to iwx_time_event_cmd 3124 * @status: bit 0 indicates success, all others specify errors 3125 * @id: the Time Event type 3126 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 3127 * @id_and_color: ID and color of the relevant MAC 3128 */ 3129 struct iwx_time_event_resp { 3130 uint32_t status; 3131 uint32_t id; 3132 uint32_t unique_id; 3133 uint32_t id_and_color; 3134 } __packed; /* IWX_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 3135 3136 /** 3137 * struct iwx_time_event_notif - notifications of time event start/stop 3138 * ( IWX_TIME_EVENT_NOTIFICATION = 0x2a ) 3139 * @timestamp: action timestamp in GP2 3140 * @session_id: session's unique id 3141 * @unique_id: unique id of the Time Event itself 3142 * @id_and_color: ID and color of the relevant MAC 3143 * @action: one of IWX_TE_NOTIF_START or IWX_TE_NOTIF_END 3144 * @status: true if scheduled, false otherwise (not executed) 3145 */ 3146 struct iwx_time_event_notif { 3147 uint32_t timestamp; 3148 uint32_t session_id; 3149 uint32_t unique_id; 3150 uint32_t id_and_color; 3151 uint32_t action; 3152 uint32_t status; 3153 } __packed; /* IWX_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 3154 3155 /** 3156 * enum iwx_session_prot_conf_id - session protection's configurations 3157 * @SESSION_PROTECT_CONF_ASSOC: Start a session protection for association. 3158 * The firmware will allocate two events. 3159 * Valid for BSS_STA and P2P_STA. 3160 * * A rather short event that can't be fragmented and with a very 3161 * high priority. If every goes well (99% of the cases) the 3162 * association should complete within this first event. During 3163 * that event, no other activity will happen in the firmware, 3164 * which is why it can't be too long. 3165 * The length of this event is hard-coded in the firmware: 300TUs. 3166 * * Another event which can be much longer (its duration is 3167 * configurable by the driver) which has a slightly lower 3168 * priority and that can be fragmented allowing other activities 3169 * to run while this event is running. 3170 * The firmware will automatically remove both events once the driver sets 3171 * the BSS MAC as associated. Neither of the events will be removed 3172 * for the P2P_STA MAC. 3173 * Only the duration is configurable for this protection. 3174 * @SESSION_PROTECT_CONF_GO_CLIENT_ASSOC: not used 3175 * @SESSION_PROTECT_CONF_P2P_DEVICE_DISCOV: Schedule the P2P Device to be in 3176 * listen mode. Will be fragmented. Valid only on the P2P Device MAC. 3177 * Valid only on the P2P Device MAC. The firmware will take into account 3178 * the duration, the interval and the repetition count. 3179 * @SESSION_PROTECT_CONF_P2P_GO_NEGOTIATION: Schedule the P2P Device to be be 3180 * able to run the GO Negotiation. Will not be fragmented and not 3181 * repetitive. Valid only on the P2P Device MAC. Only the duration will 3182 * be taken into account. 3183 * @SESSION_PROTECT_CONF_MAX_ID: not used 3184 */ 3185 enum iwx_session_prot_conf_id { 3186 IWX_SESSION_PROTECT_CONF_ASSOC, 3187 IWX_SESSION_PROTECT_CONF_GO_CLIENT_ASSOC, 3188 IWX_SESSION_PROTECT_CONF_P2P_DEVICE_DISCOV, 3189 IWX_SESSION_PROTECT_CONF_P2P_GO_NEGOTIATION, 3190 IWX_SESSION_PROTECT_CONF_MAX_ID, 3191 }; /* SESSION_PROTECTION_CONF_ID_E_VER_1 */ 3192 3193 /** 3194 * struct iwx_session_prot_cmd - configure a session protection 3195 * @id_and_color: the id and color of the mac for which this session protection 3196 * is sent 3197 * @action: can be either FW_CTXT_ACTION_ADD or FW_CTXT_ACTION_REMOVE 3198 * @conf_id: see &enum iwx_mvm_session_prot_conf_id 3199 * @duration_tu: the duration of the whole protection in TUs. 3200 * @repetition_count: not used 3201 * @interval: not used 3202 * 3203 * Note: the session protection will always be scheduled to start as 3204 * early as possible, but the maximum delay is configuration dependent. 3205 * The firmware supports only one concurrent session protection per vif. 3206 * Adding a new session protection will remove any currently running session. 3207 */ 3208 struct iwx_session_prot_cmd { 3209 /* COMMON_INDEX_HDR_API_S_VER_1 hdr */ 3210 uint32_t id_and_color; 3211 uint32_t action; 3212 uint32_t conf_id; 3213 uint32_t duration_tu; 3214 uint32_t repetition_count; 3215 uint32_t interval; 3216 } __packed; /* SESSION_PROTECTION_CMD_API_S_VER_1 */ 3217 3218 /** 3219 * struct iwx_session_prot_notif - session protection started / ended 3220 * @mac_id: the mac id for which the session protection started / ended 3221 * @status: 1 means success, 0 means failure 3222 * @start: 1 means the session protection started, 0 means it ended 3223 * @conf_id: see &enum iwx_mvm_session_prot_conf_id 3224 * 3225 * Note that any session protection will always get two notifications: start 3226 * and end even the firmware could not schedule it. 3227 */ 3228 struct iwx_session_prot_notif { 3229 uint32_t mac_id; 3230 uint32_t status; 3231 uint32_t start; 3232 uint32_t conf_id; 3233 } __packed; /* SESSION_PROTECTION_NOTIFICATION_API_S_VER_2 */ 3234 3235 3236 /* Bindings and Time Quota */ 3237 3238 /** 3239 * struct iwx_binding_cmd - configuring bindings 3240 * ( IWX_BINDING_CONTEXT_CMD = 0x2b ) 3241 * @id_and_color: ID and color of the relevant Binding 3242 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3243 * @macs: array of MAC id and colors which belong to the binding 3244 * @phy: PHY id and color which belongs to the binding 3245 * @lmac_id: the lmac id the binding belongs to 3246 */ 3247 struct iwx_binding_cmd { 3248 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3249 uint32_t id_and_color; 3250 uint32_t action; 3251 /* IWX_BINDING_DATA_API_S_VER_1 */ 3252 uint32_t macs[IWX_MAX_MACS_IN_BINDING]; 3253 uint32_t phy; 3254 uint32_t lmac_id; 3255 } __packed; /* IWX_BINDING_CMD_API_S_VER_2 */ 3256 3257 #define IWX_LMAC_24G_INDEX 0 3258 #define IWX_LMAC_5G_INDEX 1 3259 3260 /* The maximal number of fragments in the FW's schedule session */ 3261 #define IWX_MAX_QUOTA 128 3262 3263 /** 3264 * struct iwx_time_quota_data - configuration of time quota per binding 3265 * @id_and_color: ID and color of the relevant Binding 3266 * @quota: absolute time quota in TU. The scheduler will try to divide the 3267 * remaining quota (after Time Events) according to this quota. 3268 * @max_duration: max uninterrupted context duration in TU 3269 */ 3270 struct iwx_time_quota_data { 3271 uint32_t id_and_color; 3272 uint32_t quota; 3273 uint32_t max_duration; 3274 } __packed; /* IWX_TIME_QUOTA_DATA_API_S_VER_1 */ 3275 3276 /** 3277 * struct iwx_time_quota_cmd - configuration of time quota between bindings 3278 * ( IWX_TIME_QUOTA_CMD = 0x2c ) 3279 * @quotas: allocations per binding 3280 */ 3281 struct iwx_time_quota_cmd { 3282 struct iwx_time_quota_data quotas[IWX_MAX_BINDINGS]; 3283 } __packed; /* IWX_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 3284 3285 3286 /* PHY context */ 3287 3288 /* Supported bands */ 3289 #define IWX_PHY_BAND_5 (0) 3290 #define IWX_PHY_BAND_24 (1) 3291 3292 /* Supported channel width, vary if there is VHT support */ 3293 #define IWX_PHY_VHT_CHANNEL_MODE20 (0x0) 3294 #define IWX_PHY_VHT_CHANNEL_MODE40 (0x1) 3295 #define IWX_PHY_VHT_CHANNEL_MODE80 (0x2) 3296 #define IWX_PHY_VHT_CHANNEL_MODE160 (0x3) 3297 3298 /* 3299 * Control channel position: 3300 * For legacy set bit means upper channel, otherwise lower. 3301 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 3302 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 3303 * center_freq 3304 * | 3305 * 40Mhz |_______|_______| 3306 * 80Mhz |_______|_______|_______|_______| 3307 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 3308 * code 011 010 001 000 | 100 101 110 111 3309 */ 3310 #define IWX_PHY_VHT_CTRL_POS_1_BELOW (0x0) 3311 #define IWX_PHY_VHT_CTRL_POS_2_BELOW (0x1) 3312 #define IWX_PHY_VHT_CTRL_POS_3_BELOW (0x2) 3313 #define IWX_PHY_VHT_CTRL_POS_4_BELOW (0x3) 3314 #define IWX_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 3315 #define IWX_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 3316 #define IWX_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 3317 #define IWX_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 3318 3319 /* 3320 * @band: IWX_PHY_BAND_* 3321 * @channel: channel number 3322 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3323 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3324 */ 3325 struct iwx_fw_channel_info_v1 { 3326 uint8_t band; 3327 uint8_t channel; 3328 uint8_t width; 3329 uint8_t ctrl_pos; 3330 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */ 3331 3332 /* 3333 * struct iwx_fw_channel_info - channel information 3334 * 3335 * @channel: channel number 3336 * @band: PHY_BAND_* 3337 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 3338 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 3339 * @reserved: for future use and alignment 3340 */ 3341 struct iwx_fw_channel_info { 3342 uint32_t channel; 3343 uint8_t band; 3344 uint8_t width; 3345 uint8_t ctrl_pos; 3346 uint8_t reserved; 3347 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */ 3348 3349 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 3350 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 3351 (0x1 << IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS) 3352 #define IWX_PHY_RX_CHAIN_VALID_POS (1) 3353 #define IWX_PHY_RX_CHAIN_VALID_MSK \ 3354 (0x7 << IWX_PHY_RX_CHAIN_VALID_POS) 3355 #define IWX_PHY_RX_CHAIN_FORCE_SEL_POS (4) 3356 #define IWX_PHY_RX_CHAIN_FORCE_SEL_MSK \ 3357 (0x7 << IWX_PHY_RX_CHAIN_FORCE_SEL_POS) 3358 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 3359 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 3360 (0x7 << IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 3361 #define IWX_PHY_RX_CHAIN_CNT_POS (10) 3362 #define IWX_PHY_RX_CHAIN_CNT_MSK \ 3363 (0x3 << IWX_PHY_RX_CHAIN_CNT_POS) 3364 #define IWX_PHY_RX_CHAIN_MIMO_CNT_POS (12) 3365 #define IWX_PHY_RX_CHAIN_MIMO_CNT_MSK \ 3366 (0x3 << IWX_PHY_RX_CHAIN_MIMO_CNT_POS) 3367 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 3368 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 3369 (0x1 << IWX_PHY_RX_CHAIN_MIMO_FORCE_POS) 3370 3371 /* TODO: fix the value, make it depend on firmware at runtime? */ 3372 #define IWX_NUM_PHY_CTX 3 3373 3374 /** 3375 * struct iwl_phy_context_cmd - config of the PHY context 3376 * ( IWX_PHY_CONTEXT_CMD = 0x8 ) 3377 * @id_and_color: ID and color of the relevant Binding 3378 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3379 * @lmac_id: the lmac id the phy context belongs to 3380 * @ci: channel info 3381 * @rxchain_info: ??? 3382 * @dsp_cfg_flags: set to 0 3383 * @reserved: reserved to align to 64 bit 3384 */ 3385 struct iwx_phy_context_cmd_uhb { 3386 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3387 uint32_t id_and_color; 3388 uint32_t action; 3389 /* PHY_CONTEXT_DATA_API_S_VER_3 */ 3390 struct iwx_fw_channel_info ci; 3391 uint32_t lmac_id; 3392 uint32_t rxchain_info; 3393 uint32_t dsp_cfg_flags; 3394 uint32_t reserved; 3395 } __packed; /* PHY_CONTEXT_CMD_API_VER_3 */ 3396 struct iwx_phy_context_cmd { 3397 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3398 uint32_t id_and_color; 3399 uint32_t action; 3400 /* PHY_CONTEXT_DATA_API_S_VER_3, PHY_CONTEXT_DATA_API_S_VER_4 */ 3401 struct iwx_fw_channel_info_v1 ci; 3402 uint32_t lmac_id; 3403 uint32_t rxchain_info; /* reserved in _VER_4 */ 3404 uint32_t dsp_cfg_flags; 3405 uint32_t reserved; 3406 } __packed; /* PHY_CONTEXT_CMD_API_VER_3, PHY_CONTEXT_CMD_API_VER_4 */ 3407 3408 /* TODO: complete missing documentation */ 3409 /** 3410 * struct iwx_phy_context_cmd - config of the PHY context 3411 * ( IWX_PHY_CONTEXT_CMD = 0x8 ) 3412 * @id_and_color: ID and color of the relevant Binding 3413 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3414 * @apply_time: 0 means immediate apply and context switch. 3415 * other value means apply new params after X usecs 3416 * @tx_param_color: ??? 3417 * @channel_info: 3418 * @txchain_info: ??? 3419 * @rxchain_info: ??? 3420 * @acquisition_data: ??? 3421 * @dsp_cfg_flags: set to 0 3422 */ 3423 /* 3424 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased 3425 * the size of fw_channel_info from v1 to v2. 3426 * To keep things simple we define two versions of this struct, and both 3427 * are labeled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark 3428 * magic with pointers to struct members instead.) 3429 */ 3430 /* This version must be used if IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */ 3431 struct iwx_phy_context_cmd_uhb_v1 { 3432 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3433 uint32_t id_and_color; 3434 uint32_t action; 3435 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */ 3436 uint32_t apply_time; 3437 uint32_t tx_param_color; 3438 struct iwx_fw_channel_info ci; 3439 uint32_t txchain_info; 3440 uint32_t rxchain_info; 3441 uint32_t acquisition_data; 3442 uint32_t dsp_cfg_flags; 3443 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */ 3444 /* This version must be used otherwise: */ 3445 struct iwx_phy_context_cmd_v1 { 3446 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3447 uint32_t id_and_color; 3448 uint32_t action; 3449 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */ 3450 uint32_t apply_time; 3451 uint32_t tx_param_color; 3452 struct iwx_fw_channel_info_v1 ci; 3453 uint32_t txchain_info; 3454 uint32_t rxchain_info; 3455 uint32_t acquisition_data; 3456 uint32_t dsp_cfg_flags; 3457 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */ 3458 3459 3460 #define IWX_RX_INFO_PHY_CNT 8 3461 #define IWX_RX_INFO_ENERGY_ANT_ABC_IDX 1 3462 #define IWX_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 3463 #define IWX_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 3464 #define IWX_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 3465 #define IWX_RX_INFO_ENERGY_ANT_A_POS 0 3466 #define IWX_RX_INFO_ENERGY_ANT_B_POS 8 3467 #define IWX_RX_INFO_ENERGY_ANT_C_POS 16 3468 3469 #define IWX_RX_INFO_AGC_IDX 1 3470 #define IWX_RX_INFO_RSSI_AB_IDX 2 3471 #define IWX_OFDM_AGC_A_MSK 0x0000007f 3472 #define IWX_OFDM_AGC_A_POS 0 3473 #define IWX_OFDM_AGC_B_MSK 0x00003f80 3474 #define IWX_OFDM_AGC_B_POS 7 3475 #define IWX_OFDM_AGC_CODE_MSK 0x3fe00000 3476 #define IWX_OFDM_AGC_CODE_POS 20 3477 #define IWX_OFDM_RSSI_INBAND_A_MSK 0x00ff 3478 #define IWX_OFDM_RSSI_A_POS 0 3479 #define IWX_OFDM_RSSI_ALLBAND_A_MSK 0xff00 3480 #define IWX_OFDM_RSSI_ALLBAND_A_POS 8 3481 #define IWX_OFDM_RSSI_INBAND_B_MSK 0xff0000 3482 #define IWX_OFDM_RSSI_B_POS 16 3483 #define IWX_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 3484 #define IWX_OFDM_RSSI_ALLBAND_B_POS 24 3485 3486 /** 3487 * struct iwx_rx_phy_info - phy info 3488 * (IWX_REPLY_RX_PHY_CMD = 0xc0) 3489 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 3490 * @cfg_phy_cnt: configurable DSP phy data byte count 3491 * @stat_id: configurable DSP phy data set ID 3492 * @reserved1: 3493 * @system_timestamp: GP2 at on air rise 3494 * @timestamp: TSF at on air rise 3495 * @beacon_time_stamp: beacon at on-air rise 3496 * @phy_flags: general phy flags: band, modulation, ... 3497 * @channel: channel number 3498 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 3499 * @rate_n_flags: IWX_RATE_MCS_* 3500 * @byte_count: frame's byte-count 3501 * @frame_time: frame's time on the air, based on byte count and frame rate 3502 * calculation 3503 * @mac_active_msk: what MACs were active when the frame was received 3504 * 3505 * Before each Rx, the device sends this data. It contains PHY information 3506 * about the reception of the packet. 3507 */ 3508 struct iwx_rx_phy_info { 3509 uint8_t non_cfg_phy_cnt; 3510 uint8_t cfg_phy_cnt; 3511 uint8_t stat_id; 3512 uint8_t reserved1; 3513 uint32_t system_timestamp; 3514 uint64_t timestamp; 3515 uint32_t beacon_time_stamp; 3516 uint16_t phy_flags; 3517 #define IWX_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 3518 uint16_t channel; 3519 uint32_t non_cfg_phy[IWX_RX_INFO_PHY_CNT]; 3520 uint32_t rate_n_flags; 3521 uint32_t byte_count; 3522 uint16_t mac_active_msk; 3523 uint16_t frame_time; 3524 } __packed; 3525 3526 struct iwx_rx_mpdu_res_start { 3527 uint16_t byte_count; 3528 uint16_t reserved; 3529 } __packed; 3530 3531 /** 3532 * Values to parse %iwx_rx_phy_info phy_flags 3533 * @IWX_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 3534 * @IWX_RX_RES_PHY_FLAGS_MOD_CCK: 3535 * @IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 3536 * @IWX_RX_RES_PHY_FLAGS_NARROW_BAND: 3537 * @IWX_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 3538 * @IWX_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 3539 * @IWX_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 3540 * @IWX_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 3541 * @IWX_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 3542 */ 3543 #define IWX_RX_RES_PHY_FLAGS_BAND_24 (1 << 0) 3544 #define IWX_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1) 3545 #define IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2) 3546 #define IWX_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3) 3547 #define IWX_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4) 3548 #define IWX_RX_RES_PHY_FLAGS_ANTENNA_POS 4 3549 #define IWX_RX_RES_PHY_FLAGS_AGG (1 << 7) 3550 #define IWX_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8) 3551 #define IWX_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9) 3552 #define IWX_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10) 3553 3554 /** 3555 * Values written by fw for each Rx packet 3556 * @IWX_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 3557 * @IWX_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 3558 * @IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 3559 * @IWX_RX_MPDU_RES_STATUS_KEY_VALID: 3560 * @IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 3561 * @IWX_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 3562 * @IWX_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 3563 * in the driver. 3564 * @IWX_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 3565 * @IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 3566 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 3567 * %IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 3568 * @IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 3569 * @IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 3570 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 3571 * @IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 3572 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 3573 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 3574 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 3575 * @IWX_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 3576 * @IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 3577 * @IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 3578 * @IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 3579 * @IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 3580 * @IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 3581 * @IWX_RX_MPDU_RES_STATUS_STA_ID_MSK: 3582 * @IWX_RX_MPDU_RES_STATUS_RRF_KILL: 3583 * @IWX_RX_MPDU_RES_STATUS_FILTERING_MSK: 3584 * @IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK: 3585 */ 3586 #define IWX_RX_MPDU_RES_STATUS_CRC_OK (1 << 0) 3587 #define IWX_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1) 3588 #define IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2) 3589 #define IWX_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3) 3590 #define IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4) 3591 #define IWX_RX_MPDU_RES_STATUS_ICV_OK (1 << 5) 3592 #define IWX_RX_MPDU_RES_STATUS_MIC_OK (1 << 6) 3593 #define IWX_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7) 3594 #define IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7) 3595 #define IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8) 3596 #define IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8) 3597 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8) 3598 #define IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8) 3599 #define IWX_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8) 3600 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8) 3601 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8) 3602 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8) 3603 #define IWX_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11) 3604 #define IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12) 3605 #define IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13) 3606 #define IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14) 3607 #define IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15) 3608 #define IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000) 3609 #define IWX_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000) 3610 #define IWX_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29) 3611 #define IWX_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000) 3612 #define IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000) 3613 3614 #define IWX_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03 3615 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0 3616 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3 3617 3618 #define IWX_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f 3619 #define IWX_RX_MPDU_MFLG2_PAD 0x20 3620 #define IWX_RX_MPDU_MFLG2_AMSDU 0x40 3621 3622 #define IWX_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f 3623 #define IWX_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80 3624 3625 #define IWX_RX_MPDU_PHY_AMPDU (1 << 5) 3626 #define IWX_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6) 3627 #define IWX_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7) 3628 #define IWX_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7) 3629 #define IWX_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8) 3630 3631 struct iwx_rx_mpdu_desc_v3 { 3632 union { 3633 uint32_t filter_match; 3634 uint32_t phy_data3; 3635 }; 3636 union { 3637 uint32_t rss_hash; 3638 uint32_t phy_data2; 3639 }; 3640 uint32_t partial_hash; /* ip/tcp header hash w/o some fields */ 3641 uint16_t raw_xsum; 3642 uint16_t reserved_xsum; 3643 uint32_t rate_n_flags; 3644 uint8_t energy_a; 3645 uint8_t energy_b; 3646 uint8_t channel; 3647 uint8_t mac_context; 3648 uint32_t gp2_on_air_rise; 3649 union { 3650 /* 3651 * TSF value on air rise (INA), only valid if 3652 * IWX_RX_MPDU_PHY_TSF_OVERLOAD isn't set 3653 */ 3654 struct { 3655 uint32_t tsf_on_air_rise0; 3656 uint32_t tsf_on_air_rise1; 3657 }; 3658 3659 struct { 3660 uint32_t phy_data0; 3661 3662 /* Only valid if IWX_RX_MPDU_PHY_TSF_OVERLOAD is set. */ 3663 uint32_t phy_data1; 3664 }; 3665 }; 3666 uint32_t reserved[2]; 3667 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 3668 RX_MPDU_RES_START_API_S_VER_5 */ 3669 3670 struct iwx_rx_mpdu_desc_v1 { 3671 union { 3672 uint32_t rss_hash; 3673 uint32_t phy_data2; 3674 }; 3675 union { 3676 uint32_t filter_match; 3677 uint32_t phy_data3; 3678 }; 3679 uint32_t rate_n_flags; 3680 uint8_t energy_a; 3681 uint8_t energy_b; 3682 uint8_t channel; 3683 uint8_t mac_context; 3684 uint32_t gp2_on_air_rise; 3685 union { 3686 struct { 3687 uint32_t tsf_on_air_rise0; 3688 uint32_t tsf_on_air_rise1; 3689 }; 3690 struct { 3691 uint32_t phy_data0; 3692 uint32_t phy_data1; 3693 }; 3694 }; 3695 } __packed; 3696 3697 #define IWX_RX_REORDER_DATA_INVALID_BAID 0x7f 3698 3699 #define IWX_RX_MPDU_REORDER_NSSN_MASK 0x00000fff 3700 #define IWX_RX_MPDU_REORDER_SN_MASK 0x00fff000 3701 #define IWX_RX_MPDU_REORDER_SN_SHIFT 12 3702 #define IWX_RX_MPDU_REORDER_BAID_MASK 0x7f000000 3703 #define IWX_RX_MPDU_REORDER_BAID_SHIFT 24 3704 #define IWX_RX_MPDU_REORDER_BA_OLD_SN 0x80000000 3705 3706 struct iwx_rx_mpdu_desc { 3707 uint16_t mpdu_len; 3708 uint8_t mac_flags1; 3709 uint8_t mac_flags2; 3710 uint8_t amsdu_info; 3711 uint16_t phy_info; 3712 uint8_t mac_phy_idx; 3713 uint16_t raw_csum; 3714 union { 3715 uint16_t l3l4_flags; 3716 uint16_t phy_data4; 3717 }; 3718 uint16_t status; 3719 uint8_t hash_filter; 3720 uint8_t sta_id_flags; 3721 uint32_t reorder_data; 3722 union { 3723 struct iwx_rx_mpdu_desc_v1 v1; 3724 struct iwx_rx_mpdu_desc_v3 v3; 3725 }; 3726 } __packed; /* RX_MPDU_RES_START_API_S_VER_3, 3727 RX_MPDU_RES_START_API_S_VER_4, 3728 RX_MPDU_RES_START_API_S_VER_5 */ 3729 3730 #define IWX_RX_DESC_SIZE_V1 ((sizeof(struct iwx_rx_mpdu_desc) - \ 3731 sizeof(struct iwx_rx_mpdu_desc_v3)) + sizeof(struct iwx_rx_mpdu_desc_v1)) 3732 3733 struct iwx_frame_release { 3734 uint8_t baid; 3735 uint8_t reserved; 3736 uint16_t nssn; 3737 }; 3738 3739 /** 3740 * enum iwx_bar_frame_release_sta_tid - STA/TID information for BAR release 3741 * @IWX_BAR_FRAME_RELEASE_TID_MASK: TID mask 3742 * @IWX_BAR_FRAME_RELEASE_STA_MASK: STA mask 3743 */ 3744 #define IWX_BAR_FRAME_RELEASE_TID_MASK 0x0000000f 3745 #define IWX_BAR_FRAME_RELEASE_STA_MASK 0x000001f0 3746 #define IWX_BAR_FRAME_RELEASE_STA_SHIFT 4 3747 3748 /** 3749 * enum iwx_bar_frame_release_ba_info - BA information for BAR release 3750 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 3751 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 3752 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 3753 */ 3754 #define IWX_BAR_FRAME_RELEASE_NSSN_MASK 0x00000fff 3755 #define IWX_BAR_FRAME_RELEASE_SN_MASK 0x00fff000 3756 #define IWX_BAR_FRAME_RELEASE_SN_SHIFT 12 3757 #define IWX_BAR_FRAME_RELEASE_BAID_MASK 0x3f000000 3758 #define IWX_BAR_FRAME_RELEASE_BAID_SHIFT 24 3759 3760 /** 3761 * struct iwx_bar_frame_release - frame release from BAR info 3762 * @sta_tid: STA & TID information, see &enum iwx_bar_frame_release_sta_tid. 3763 * @ba_info: BA information, see &enum iwx_bar_frame_release_ba_info. 3764 */ 3765 struct iwx_bar_frame_release { 3766 uint32_t sta_tid; 3767 uint32_t ba_info; 3768 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 3769 3770 /** 3771 * struct iwx_radio_version_notif - information on the radio version 3772 * ( IWX_RADIO_VERSION_NOTIFICATION = 0x68 ) 3773 * @radio_flavor: 3774 * @radio_step: 3775 * @radio_dash: 3776 */ 3777 struct iwx_radio_version_notif { 3778 uint32_t radio_flavor; 3779 uint32_t radio_step; 3780 uint32_t radio_dash; 3781 } __packed; /* IWX_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 3782 3783 #define IWX_CARD_ENABLED 0x00 3784 #define IWX_HW_CARD_DISABLED 0x01 3785 #define IWX_SW_CARD_DISABLED 0x02 3786 #define IWX_CT_KILL_CARD_DISABLED 0x04 3787 #define IWX_HALT_CARD_DISABLED 0x08 3788 #define IWX_CARD_DISABLED_MSK 0x0f 3789 #define IWX_CARD_IS_RX_ON 0x10 3790 3791 /** 3792 * struct iwx_radio_version_notif - information on the radio version 3793 * (IWX_CARD_STATE_NOTIFICATION = 0xa1 ) 3794 * @flags: %iwx_card_state_flags 3795 */ 3796 struct iwx_card_state_notif { 3797 uint32_t flags; 3798 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 3799 3800 /** 3801 * struct iwx_missed_beacons_notif - information on missed beacons 3802 * ( IWX_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 3803 * @mac_id: interface ID 3804 * @consec_missed_beacons_since_last_rx: number of consecutive missed 3805 * beacons since last RX. 3806 * @consec_missed_beacons: number of consecutive missed beacons 3807 * @num_expected_beacons: 3808 * @num_recvd_beacons: 3809 */ 3810 struct iwx_missed_beacons_notif { 3811 uint32_t mac_id; 3812 uint32_t consec_missed_beacons_since_last_rx; 3813 uint32_t consec_missed_beacons; 3814 uint32_t num_expected_beacons; 3815 uint32_t num_recvd_beacons; 3816 } __packed; /* IWX_MISSED_BEACON_NTFY_API_S_VER_3 */ 3817 3818 /** 3819 * struct iwx_mfuart_load_notif - mfuart image version & status 3820 * ( IWX_MFUART_LOAD_NOTIFICATION = 0xb1 ) 3821 * @installed_ver: installed image version 3822 * @external_ver: external image version 3823 * @status: MFUART loading status 3824 * @duration: MFUART loading time 3825 */ 3826 struct iwx_mfuart_load_notif { 3827 uint32_t installed_ver; 3828 uint32_t external_ver; 3829 uint32_t status; 3830 uint32_t duration; 3831 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 3832 3833 /** 3834 * struct iwx_set_calib_default_cmd - set default value for calibration. 3835 * ( IWX_SET_CALIB_DEFAULT_CMD = 0x8e ) 3836 * @calib_index: the calibration to set value for 3837 * @length: of data 3838 * @data: the value to set for the calibration result 3839 */ 3840 struct iwx_set_calib_default_cmd { 3841 uint16_t calib_index; 3842 uint16_t length; 3843 uint8_t data[0]; 3844 } __packed; /* IWX_PHY_CALIB_OVERRIDE_VALUES_S */ 3845 3846 #define IWX_MAX_PORT_ID_NUM 2 3847 #define IWX_MAX_MCAST_FILTERING_ADDRESSES 256 3848 3849 /** 3850 * struct iwx_mcast_filter_cmd - configure multicast filter. 3851 * @filter_own: Set 1 to filter out multicast packets sent by station itself 3852 * @port_id: Multicast MAC addresses array specifier. This is a strange way 3853 * to identify network interface adopted in host-device IF. 3854 * It is used by FW as index in array of addresses. This array has 3855 * IWX_MAX_PORT_ID_NUM members. 3856 * @count: Number of MAC addresses in the array 3857 * @pass_all: Set 1 to pass all multicast packets. 3858 * @bssid: current association BSSID. 3859 * @addr_list: Place holder for array of MAC addresses. 3860 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 3861 */ 3862 struct iwx_mcast_filter_cmd { 3863 uint8_t filter_own; 3864 uint8_t port_id; 3865 uint8_t count; 3866 uint8_t pass_all; 3867 uint8_t bssid[6]; 3868 uint8_t reserved[2]; 3869 uint8_t addr_list[0]; 3870 } __packed; /* IWX_MCAST_FILTERING_CMD_API_S_VER_1 */ 3871 3872 struct iwx_statistics_dbg { 3873 uint32_t burst_check; 3874 uint32_t burst_count; 3875 uint32_t wait_for_silence_timeout_cnt; 3876 uint32_t reserved[3]; 3877 } __packed; /* IWX_STATISTICS_DEBUG_API_S_VER_2 */ 3878 3879 struct iwx_statistics_div { 3880 uint32_t tx_on_a; 3881 uint32_t tx_on_b; 3882 uint32_t exec_time; 3883 uint32_t probe_time; 3884 uint32_t rssi_ant; 3885 uint32_t reserved2; 3886 } __packed; /* IWX_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3887 3888 struct iwx_statistics_bt_activity { 3889 uint32_t hi_priority_tx_req_cnt; 3890 uint32_t hi_priority_tx_denied_cnt; 3891 uint32_t lo_priority_tx_req_cnt; 3892 uint32_t lo_priority_tx_denied_cnt; 3893 uint32_t hi_priority_rx_req_cnt; 3894 uint32_t hi_priority_rx_denied_cnt; 3895 uint32_t lo_priority_rx_req_cnt; 3896 uint32_t lo_priority_rx_denied_cnt; 3897 } __packed; /* IWX_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3898 3899 struct iwx_statistics_general_common { 3900 uint32_t radio_temperature; 3901 struct iwx_statistics_dbg dbg; 3902 uint32_t sleep_time; 3903 uint32_t slots_out; 3904 uint32_t slots_idle; 3905 uint32_t ttl_timestamp; 3906 struct iwx_statistics_div slow_div; 3907 uint32_t rx_enable_counter; 3908 /* 3909 * num_of_sos_states: 3910 * count the number of times we have to re-tune 3911 * in order to get out of bad PHY status 3912 */ 3913 uint32_t num_of_sos_states; 3914 uint32_t beacon_filtered; 3915 uint32_t missed_beacons; 3916 uint8_t beacon_filter_average_energy; 3917 uint8_t beacon_filter_reason; 3918 uint8_t beacon_filter_current_energy; 3919 uint8_t beacon_filter_reserved; 3920 uint32_t beacon_filter_delta_time; 3921 struct iwx_statistics_bt_activity bt_activity; 3922 uint64_t rx_time; 3923 uint64_t on_time_rf; 3924 uint64_t on_time_scan; 3925 uint64_t tx_time; 3926 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */ 3927 3928 struct iwx_statistics_rx_non_phy { 3929 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3930 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3931 uint32_t non_bssid_frames; /* number of frames with BSSID that 3932 * doesn't belong to the STA BSSID */ 3933 uint32_t filtered_frames; /* count frames that were dumped in the 3934 * filtering process */ 3935 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3936 * our serving channel */ 3937 uint32_t channel_beacons; /* beacons with our bss id and in our 3938 * serving channel */ 3939 uint32_t num_missed_bcon; /* number of missed beacons */ 3940 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3941 * ADC was in saturation */ 3942 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3943 * for INA */ 3944 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3945 uint32_t interference_data_flag; /* flag for interference data 3946 * availability. 1 when data is 3947 * available. */ 3948 uint32_t channel_load; /* counts RX Enable time in uSec */ 3949 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3950 * and CCK) counter */ 3951 uint32_t beacon_rssi_a; 3952 uint32_t beacon_rssi_b; 3953 uint32_t beacon_rssi_c; 3954 uint32_t beacon_energy_a; 3955 uint32_t beacon_energy_b; 3956 uint32_t beacon_energy_c; 3957 uint32_t num_bt_kills; 3958 uint32_t mac_id; 3959 uint32_t directed_data_mpdu; 3960 } __packed; /* IWX_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3961 3962 struct iwx_statistics_rx_phy { 3963 uint32_t ina_cnt; 3964 uint32_t fina_cnt; 3965 uint32_t plcp_err; 3966 uint32_t crc32_err; 3967 uint32_t overrun_err; 3968 uint32_t early_overrun_err; 3969 uint32_t crc32_good; 3970 uint32_t false_alarm_cnt; 3971 uint32_t fina_sync_err_cnt; 3972 uint32_t sfd_timeout; 3973 uint32_t fina_timeout; 3974 uint32_t unresponded_rts; 3975 uint32_t rxe_frame_limit_overrun; 3976 uint32_t sent_ack_cnt; 3977 uint32_t sent_cts_cnt; 3978 uint32_t sent_ba_rsp_cnt; 3979 uint32_t dsp_self_kill; 3980 uint32_t mh_format_err; 3981 uint32_t re_acq_main_rssi_sum; 3982 uint32_t reserved; 3983 } __packed; /* IWX_STATISTICS_RX_PHY_API_S_VER_2 */ 3984 3985 struct iwx_statistics_rx_ht_phy { 3986 uint32_t plcp_err; 3987 uint32_t overrun_err; 3988 uint32_t early_overrun_err; 3989 uint32_t crc32_good; 3990 uint32_t crc32_err; 3991 uint32_t mh_format_err; 3992 uint32_t agg_crc32_good; 3993 uint32_t agg_mpdu_cnt; 3994 uint32_t agg_cnt; 3995 uint32_t unsupport_mcs; 3996 } __packed; /* IWX_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3997 3998 /* 3999 * The first MAC indices (starting from 0) 4000 * are available to the driver, AUX follows 4001 */ 4002 #define IWX_MAC_INDEX_AUX 4 4003 #define IWX_MAC_INDEX_MIN_DRIVER 0 4004 #define IWX_NUM_MAC_INDEX_DRIVER IWX_MAC_INDEX_AUX 4005 4006 #define IWX_STATION_COUNT 16 4007 4008 #define IWX_MAX_CHAINS 3 4009 4010 struct iwx_statistics_tx_non_phy_agg { 4011 uint32_t ba_timeout; 4012 uint32_t ba_reschedule_frames; 4013 uint32_t scd_query_agg_frame_cnt; 4014 uint32_t scd_query_no_agg; 4015 uint32_t scd_query_agg; 4016 uint32_t scd_query_mismatch; 4017 uint32_t frame_not_ready; 4018 uint32_t underrun; 4019 uint32_t bt_prio_kill; 4020 uint32_t rx_ba_rsp_cnt; 4021 int8_t txpower[IWX_MAX_CHAINS]; 4022 int8_t reserved; 4023 uint32_t reserved2; 4024 } __packed; /* IWX_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 4025 4026 struct iwx_statistics_tx_channel_width { 4027 uint32_t ext_cca_narrow_ch20[1]; 4028 uint32_t ext_cca_narrow_ch40[2]; 4029 uint32_t ext_cca_narrow_ch80[3]; 4030 uint32_t ext_cca_narrow_ch160[4]; 4031 uint32_t last_tx_ch_width_indx; 4032 uint32_t rx_detected_per_ch_width[4]; 4033 uint32_t success_per_ch_width[4]; 4034 uint32_t fail_per_ch_width[4]; 4035 }; /* IWX_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 4036 4037 struct iwx_statistics_tx { 4038 uint32_t preamble_cnt; 4039 uint32_t rx_detected_cnt; 4040 uint32_t bt_prio_defer_cnt; 4041 uint32_t bt_prio_kill_cnt; 4042 uint32_t few_bytes_cnt; 4043 uint32_t cts_timeout; 4044 uint32_t ack_timeout; 4045 uint32_t expected_ack_cnt; 4046 uint32_t actual_ack_cnt; 4047 uint32_t dump_msdu_cnt; 4048 uint32_t burst_abort_next_frame_mismatch_cnt; 4049 uint32_t burst_abort_missing_next_frame_cnt; 4050 uint32_t cts_timeout_collision; 4051 uint32_t ack_or_ba_timeout_collision; 4052 struct iwx_statistics_tx_non_phy_agg agg; 4053 struct iwx_statistics_tx_channel_width channel_width; 4054 } __packed; /* IWX_STATISTICS_TX_API_S_VER_4 */ 4055 4056 struct iwx_statistics_general { 4057 struct iwx_statistics_general_common common; 4058 uint32_t beacon_counter[IWX_MAC_INDEX_AUX]; 4059 uint8_t beacon_average_energy[IWX_MAC_INDEX_AUX]; 4060 uint8_t reserved[8 - IWX_MAC_INDEX_AUX]; 4061 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */ 4062 4063 struct iwx_statistics_rx { 4064 struct iwx_statistics_rx_phy ofdm; 4065 struct iwx_statistics_rx_phy cck; 4066 struct iwx_statistics_rx_non_phy general; 4067 struct iwx_statistics_rx_ht_phy ofdm_ht; 4068 } __packed; /* IWX_STATISTICS_RX_API_S_VER_3 */ 4069 4070 /* 4071 * IWX_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 4072 * 4073 * By default, uCode issues this notification after receiving a beacon 4074 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 4075 * IWX_REPLY_STATISTICS_CMD 0x9c, above. 4076 * 4077 * Statistics counters continue to increment beacon after beacon, but are 4078 * cleared when changing channels or when driver issues IWX_REPLY_STATISTICS_CMD 4079 * 0x9c with CLEAR_STATS bit set (see above). 4080 * 4081 * uCode also issues this notification during scans. uCode clears statistics 4082 * appropriately so that each notification contains statistics for only the 4083 * one channel that has just been scanned. 4084 */ 4085 4086 /** 4087 * struct iwx_statistics_load - RX statistics for multi-queue devices 4088 * @air_time: accumulated air time, per mac 4089 * @byte_count: accumulated byte count, per mac 4090 * @pkt_count: accumulated packet count, per mac 4091 * @avg_energy: average RSSI, per station 4092 */ 4093 struct iwx_statistics_load { 4094 uint32_t air_time[IWX_MAC_INDEX_AUX]; 4095 uint32_t byte_count[IWX_MAC_INDEX_AUX]; 4096 uint32_t pkt_count[IWX_MAC_INDEX_AUX]; 4097 uint8_t avg_energy[IWX_STATION_COUNT]; 4098 } __packed; /* STATISTICS_RX_MAC_STATION_S_VER_3 */ 4099 4100 struct iwx_notif_statistics { 4101 uint32_t flag; 4102 struct iwx_statistics_rx rx; 4103 struct iwx_statistics_tx tx; 4104 struct iwx_statistics_general general; 4105 struct iwx_statistics_load load_stats; 4106 } __packed; /* STATISTICS_NTFY_API_S_VER_13 */ 4107 4108 4109 /** 4110 * flags used in statistics notification 4111 * @IWX_STATISTICS_REPLY_FLG_CLEAR: statistics were cleared after this report 4112 */ 4113 #define IWX_STATISTICS_REPLY_FLG_CLEAR 0x01 4114 4115 /** 4116 * flags used in statistics command 4117 * @IWX_STATISTICS_FLG_CLEAR: request to clear statistics after the report 4118 * that's sent after this command 4119 * @IWX_STATISTICS_FLG_DISABLE_NOTIF: disable unilateral statistics 4120 * notifications 4121 */ 4122 #define IWX_STATISTICS_FLG_CLEAR 0x01 4123 #define IWX_STATISTICS_FLG_DISABLE_NOTIF 0x02 4124 4125 /** 4126 * struct iwx_statistics_cmd - statistics config command 4127 * @flags: IWX_STATISTICS_* flags 4128 */ 4129 struct iwx_statistics_cmd { 4130 uint32_t flags; 4131 } __packed; /* STATISTICS_CMD_API_S_VER_1 */ 4132 4133 4134 /*********************************** 4135 * Smart Fifo API 4136 ***********************************/ 4137 /* Smart Fifo state */ 4138 #define IWX_SF_LONG_DELAY_ON 0 /* should never be called by driver */ 4139 #define IWX_SF_FULL_ON 1 4140 #define IWX_SF_UNINIT 2 4141 #define IWX_SF_INIT_OFF 3 4142 #define IWX_SF_HW_NUM_STATES 4 4143 4144 /* Smart Fifo possible scenario */ 4145 #define IWX_SF_SCENARIO_SINGLE_UNICAST 0 4146 #define IWX_SF_SCENARIO_AGG_UNICAST 1 4147 #define IWX_SF_SCENARIO_MULTICAST 2 4148 #define IWX_SF_SCENARIO_BA_RESP 3 4149 #define IWX_SF_SCENARIO_TX_RESP 4 4150 #define IWX_SF_NUM_SCENARIO 5 4151 4152 #define IWX_SF_TRANSIENT_STATES_NUMBER 2 /* IWX_SF_LONG_DELAY_ON and IWX_SF_FULL_ON */ 4153 #define IWX_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 4154 4155 /* smart FIFO default values */ 4156 #define IWX_SF_W_MARK_SISO 4096 4157 #define IWX_SF_W_MARK_MIMO2 8192 4158 #define IWX_SF_W_MARK_MIMO3 6144 4159 #define IWX_SF_W_MARK_LEGACY 4096 4160 #define IWX_SF_W_MARK_SCAN 4096 4161 4162 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 4163 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 4164 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4165 #define IWX_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 4166 #define IWX_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4167 #define IWX_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 4168 #define IWX_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4169 #define IWX_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 4170 #define IWX_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4171 #define IWX_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 4172 #define IWX_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 4173 4174 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 4175 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 4176 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 4177 #define IWX_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 4178 #define IWX_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 4179 #define IWX_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 4180 #define IWX_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 4181 #define IWX_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 4182 #define IWX_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 4183 #define IWX_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 4184 #define IWX_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 4185 4186 #define IWX_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 4187 4188 #define IWX_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 4189 4190 /** 4191 * Smart Fifo configuration command. 4192 * @state: smart fifo state, types listed in enum %iwx_sf_state. 4193 * @watermark: Minimum allowed available free space in RXF for transient state. 4194 * @long_delay_timeouts: aging and idle timer values for each scenario 4195 * in long delay state. 4196 * @full_on_timeouts: timer values for each scenario in full on state. 4197 */ 4198 struct iwx_sf_cfg_cmd { 4199 uint32_t state; 4200 uint32_t watermark[IWX_SF_TRANSIENT_STATES_NUMBER]; 4201 uint32_t long_delay_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES]; 4202 uint32_t full_on_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES]; 4203 } __packed; /* IWX_SF_CFG_API_S_VER_2 */ 4204 4205 #define IWX_AC_BK 0 4206 #define IWX_AC_BE 1 4207 #define IWX_AC_VI 2 4208 #define IWX_AC_VO 3 4209 #define IWX_AC_NUM 4 4210 4211 /** 4212 * MAC context flags 4213 * @IWX_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 4214 * this will require CCK RTS/CTS2self. 4215 * RTS/CTS will protect full burst time. 4216 * @IWX_MAC_PROT_FLG_HT_PROT: enable HT protection 4217 * @IWX_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 4218 * @IWX_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 4219 */ 4220 #define IWX_MAC_PROT_FLG_TGG_PROTECT (1 << 3) 4221 #define IWX_MAC_PROT_FLG_HT_PROT (1 << 23) 4222 #define IWX_MAC_PROT_FLG_FAT_PROT (1 << 24) 4223 #define IWX_MAC_PROT_FLG_SELF_CTS_EN (1 << 30) 4224 4225 #define IWX_MAC_FLG_SHORT_SLOT (1 << 4) 4226 #define IWX_MAC_FLG_SHORT_PREAMBLE (1 << 5) 4227 4228 /** 4229 * Supported MAC types 4230 * @IWX_FW_MAC_TYPE_FIRST: lowest supported MAC type 4231 * @IWX_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 4232 * @IWX_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 4233 * @IWX_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 4234 * @IWX_FW_MAC_TYPE_IBSS: IBSS 4235 * @IWX_FW_MAC_TYPE_BSS_STA: BSS (managed) station 4236 * @IWX_FW_MAC_TYPE_P2P_DEVICE: P2P Device 4237 * @IWX_FW_MAC_TYPE_P2P_STA: P2P client 4238 * @IWX_FW_MAC_TYPE_GO: P2P GO 4239 * @IWX_FW_MAC_TYPE_TEST: ? 4240 * @IWX_FW_MAC_TYPE_MAX: highest support MAC type 4241 */ 4242 #define IWX_FW_MAC_TYPE_FIRST 1 4243 #define IWX_FW_MAC_TYPE_AUX IWX_FW_MAC_TYPE_FIRST 4244 #define IWX_FW_MAC_TYPE_LISTENER 2 4245 #define IWX_FW_MAC_TYPE_PIBSS 3 4246 #define IWX_FW_MAC_TYPE_IBSS 4 4247 #define IWX_FW_MAC_TYPE_BSS_STA 5 4248 #define IWX_FW_MAC_TYPE_P2P_DEVICE 6 4249 #define IWX_FW_MAC_TYPE_P2P_STA 7 4250 #define IWX_FW_MAC_TYPE_GO 8 4251 #define IWX_FW_MAC_TYPE_TEST 9 4252 #define IWX_FW_MAC_TYPE_MAX IWX_FW_MAC_TYPE_TEST 4253 /* IWX_MAC_CONTEXT_TYPE_API_E_VER_1 */ 4254 4255 /** 4256 * TSF hw timer ID 4257 * @IWX_TSF_ID_A: use TSF A 4258 * @IWX_TSF_ID_B: use TSF B 4259 * @IWX_TSF_ID_C: use TSF C 4260 * @IWX_TSF_ID_D: use TSF D 4261 * @IWX_NUM_TSF_IDS: number of TSF timers available 4262 */ 4263 #define IWX_TSF_ID_A 0 4264 #define IWX_TSF_ID_B 1 4265 #define IWX_TSF_ID_C 2 4266 #define IWX_TSF_ID_D 3 4267 #define IWX_NUM_TSF_IDS 4 4268 /* IWX_TSF_ID_API_E_VER_1 */ 4269 4270 /** 4271 * struct iwx_mac_data_ap - configuration data for AP MAC context 4272 * @beacon_time: beacon transmit time in system time 4273 * @beacon_tsf: beacon transmit time in TSF 4274 * @bi: beacon interval in TU 4275 * @bi_reciprocal: 2^32 / bi 4276 * @dtim_interval: dtim transmit time in TU 4277 * @dtim_reciprocal: 2^32 / dtim_interval 4278 * @mcast_qid: queue ID for multicast traffic 4279 * NOTE: obsolete from VER2 and on 4280 * @beacon_template: beacon template ID 4281 */ 4282 struct iwx_mac_data_ap { 4283 uint32_t beacon_time; 4284 uint64_t beacon_tsf; 4285 uint32_t bi; 4286 uint32_t bi_reciprocal; 4287 uint32_t dtim_interval; 4288 uint32_t dtim_reciprocal; 4289 uint32_t mcast_qid; 4290 uint32_t beacon_template; 4291 } __packed; /* AP_MAC_DATA_API_S_VER_2 */ 4292 4293 /** 4294 * struct iwx_mac_data_ibss - configuration data for IBSS MAC context 4295 * @beacon_time: beacon transmit time in system time 4296 * @beacon_tsf: beacon transmit time in TSF 4297 * @bi: beacon interval in TU 4298 * @bi_reciprocal: 2^32 / bi 4299 * @beacon_template: beacon template ID 4300 */ 4301 struct iwx_mac_data_ibss { 4302 uint32_t beacon_time; 4303 uint64_t beacon_tsf; 4304 uint32_t bi; 4305 uint32_t bi_reciprocal; 4306 uint32_t beacon_template; 4307 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 4308 4309 /** 4310 * enum iwx_mac_data_policy - policy of the data path for this MAC 4311 * @TWT_SUPPORTED: twt is supported 4312 * @MORE_DATA_ACK_SUPPORTED: AP supports More Data Ack according to 4313 * paragraph 9.4.1.17 in P802.11ax_D4 specification. Used for TWT 4314 * early termination detection. 4315 * @FLEXIBLE_TWT_SUPPORTED: AP supports flexible TWT schedule 4316 * @PROTECTED_TWT_SUPPORTED: AP supports protected TWT frames (with 11w) 4317 * @BROADCAST_TWT_SUPPORTED: AP and STA support broadcast TWT 4318 * @COEX_HIGH_PRIORITY_ENABLE: high priority mode for BT coex, to be used 4319 * during 802.1X negotiation (and allowed during 4-way-HS) 4320 */ 4321 #define IWX_TWT_SUPPORTED BIT (1 << 0) 4322 #define IWX_MORE_DATA_ACK_SUPPORTED (1 << 1) 4323 #define IWX_FLEXIBLE_TWT_SUPPORTED (1 << 2) 4324 #define IWX_PROTECTED_TWT_SUPPORTED (1 << 3) 4325 #define IWX_BROADCAST_TWT_SUPPORTED (1 << 4) 4326 #define IWX_COEX_HIGH_PRIORITY_ENABLE (1 << 5) 4327 4328 /** 4329 * struct iwx_mac_data_sta - configuration data for station MAC context 4330 * @is_assoc: 1 for associated state, 0 otherwise 4331 * @dtim_time: DTIM arrival time in system time 4332 * @dtim_tsf: DTIM arrival time in TSF 4333 * @bi: beacon interval in TU, applicable only when associated 4334 * @data_policy: see &enum iwl_mac_data_policy 4335 * @dtim_interval: DTIM interval in TU, applicable only when associated 4336 * @listen_interval: in beacon intervals, applicable only when associated 4337 * @assoc_id: unique ID assigned by the AP during association 4338 */ 4339 struct iwx_mac_data_sta { 4340 uint32_t is_assoc; 4341 uint32_t dtim_time; 4342 uint64_t dtim_tsf; 4343 uint32_t bi; 4344 uint32_t reserved1; 4345 uint32_t dtim_interval; 4346 uint32_t data_policy; 4347 uint32_t listen_interval; 4348 uint32_t assoc_id; 4349 uint32_t assoc_beacon_arrive_time; 4350 } __packed; /* IWX_STA_MAC_DATA_API_S_VER_2 */ 4351 4352 /** 4353 * struct iwx_mac_data_go - configuration data for P2P GO MAC context 4354 * @ap: iwx_mac_data_ap struct with most config data 4355 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 4356 * 0 indicates that there is no CT window. 4357 * @opp_ps_enabled: indicate that opportunistic PS allowed 4358 */ 4359 struct iwx_mac_data_go { 4360 struct iwx_mac_data_ap ap; 4361 uint32_t ctwin; 4362 uint32_t opp_ps_enabled; 4363 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 4364 4365 /** 4366 * struct iwx_mac_data_p2p_sta - configuration data for P2P client MAC context 4367 * @sta: iwx_mac_data_sta struct with most config data 4368 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 4369 * 0 indicates that there is no CT window. 4370 */ 4371 struct iwx_mac_data_p2p_sta { 4372 struct iwx_mac_data_sta sta; 4373 uint32_t ctwin; 4374 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 4375 4376 /** 4377 * struct iwx_mac_data_pibss - Pseudo IBSS config data 4378 * @stats_interval: interval in TU between statistics notifications to host. 4379 */ 4380 struct iwx_mac_data_pibss { 4381 uint32_t stats_interval; 4382 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 4383 4384 /* 4385 * struct iwx_mac_data_p2p_dev - configuration data for the P2P Device MAC 4386 * context. 4387 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 4388 * other channels as well. This should be to true only in case that the 4389 * device is discoverable and there is an active GO. Note that setting this 4390 * field when not needed, will increase the number of interrupts and have 4391 * effect on the platform power, as this setting opens the Rx filters on 4392 * all macs. 4393 */ 4394 struct iwx_mac_data_p2p_dev { 4395 uint32_t is_disc_extended; 4396 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 4397 4398 /** 4399 * MAC context filter flags 4400 * @IWX_MAC_FILTER_IN_PROMISC: accept all data frames 4401 * @IWX_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all management and 4402 * control frames to the host 4403 * @IWX_MAC_FILTER_ACCEPT_GRP: accept multicast frames 4404 * @IWX_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 4405 * @IWX_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 4406 * @IWX_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 4407 * (in station mode when associated) 4408 * @IWX_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 4409 * @IWX_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 4410 * @IWX_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 4411 */ 4412 #define IWX_MAC_FILTER_IN_PROMISC (1 << 0) 4413 #define IWX_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1) 4414 #define IWX_MAC_FILTER_ACCEPT_GRP (1 << 2) 4415 #define IWX_MAC_FILTER_DIS_DECRYPT (1 << 3) 4416 #define IWX_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4) 4417 #define IWX_MAC_FILTER_IN_BEACON (1 << 6) 4418 #define IWX_MAC_FILTER_OUT_BCAST (1 << 8) 4419 #define IWX_MAC_FILTER_IN_CRC32 (1 << 11) 4420 #define IWX_MAC_FILTER_IN_PROBE_REQUEST (1 << 12) 4421 4422 /** 4423 * QoS flags 4424 * @IWX_MAC_QOS_FLG_UPDATE_EDCA: ? 4425 * @IWX_MAC_QOS_FLG_TGN: HT is enabled 4426 * @IWX_MAC_QOS_FLG_TXOP_TYPE: ? 4427 * 4428 */ 4429 #define IWX_MAC_QOS_FLG_UPDATE_EDCA (1 << 0) 4430 #define IWX_MAC_QOS_FLG_TGN (1 << 1) 4431 #define IWX_MAC_QOS_FLG_TXOP_TYPE (1 << 4) 4432 4433 /** 4434 * struct iwx_ac_qos - QOS timing params for IWX_MAC_CONTEXT_CMD 4435 * @cw_min: Contention window, start value in numbers of slots. 4436 * Should be a power-of-2, minus 1. Device's default is 0x0f. 4437 * @cw_max: Contention window, max value in numbers of slots. 4438 * Should be a power-of-2, minus 1. Device's default is 0x3f. 4439 * @aifsn: Number of slots in Arbitration Interframe Space (before 4440 * performing random backoff timing prior to Tx). Device default 1. 4441 * @fifos_mask: FIFOs used by this MAC for this AC 4442 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 4443 * 4444 * One instance of this config struct for each of 4 EDCA access categories 4445 * in struct iwx_qosparam_cmd. 4446 * 4447 * Device will automatically increase contention window by (2*CW) + 1 for each 4448 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 4449 * value, to cap the CW value. 4450 */ 4451 struct iwx_ac_qos { 4452 uint16_t cw_min; 4453 uint16_t cw_max; 4454 uint8_t aifsn; 4455 uint8_t fifos_mask; 4456 uint16_t edca_txop; 4457 } __packed; /* IWX_AC_QOS_API_S_VER_2 */ 4458 4459 /** 4460 * struct iwx_mac_ctx_cmd - command structure to configure MAC contexts 4461 * ( IWX_MAC_CONTEXT_CMD = 0x28 ) 4462 * @id_and_color: ID and color of the MAC 4463 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 4464 * @mac_type: one of IWX_FW_MAC_TYPE_* 4465 * @tsf_id: TSF HW timer, one of IWX_TSF_ID_* 4466 * @node_addr: MAC address 4467 * @bssid_addr: BSSID 4468 * @cck_rates: basic rates available for CCK 4469 * @ofdm_rates: basic rates available for OFDM 4470 * @protection_flags: combination of IWX_MAC_PROT_FLG_FLAG_* 4471 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 4472 * @short_slot: 0x10 for enabling short slots, 0 otherwise 4473 * @filter_flags: combination of IWX_MAC_FILTER_* 4474 * @qos_flags: from IWX_MAC_QOS_FLG_* 4475 * @ac: one iwx_mac_qos configuration for each AC 4476 * @mac_specific: one of struct iwx_mac_data_*, according to mac_type 4477 */ 4478 struct iwx_mac_ctx_cmd { 4479 /* COMMON_INDEX_HDR_API_S_VER_1 */ 4480 uint32_t id_and_color; 4481 uint32_t action; 4482 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 4483 uint32_t mac_type; 4484 uint32_t tsf_id; 4485 uint8_t node_addr[6]; 4486 uint16_t reserved_for_node_addr; 4487 uint8_t bssid_addr[6]; 4488 uint16_t reserved_for_bssid_addr; 4489 uint32_t cck_rates; 4490 uint32_t ofdm_rates; 4491 uint32_t protection_flags; 4492 uint32_t cck_short_preamble; 4493 uint32_t short_slot; 4494 uint32_t filter_flags; 4495 /* IWX_MAC_QOS_PARAM_API_S_VER_1 */ 4496 uint32_t qos_flags; 4497 struct iwx_ac_qos ac[IWX_AC_NUM+1]; 4498 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S */ 4499 union { 4500 struct iwx_mac_data_ap ap; 4501 struct iwx_mac_data_go go; 4502 struct iwx_mac_data_sta sta; 4503 struct iwx_mac_data_p2p_sta p2p_sta; 4504 struct iwx_mac_data_p2p_dev p2p_dev; 4505 struct iwx_mac_data_pibss pibss; 4506 struct iwx_mac_data_ibss ibss; 4507 }; 4508 } __packed; /* IWX_MAC_CONTEXT_CMD_API_S_VER_1 */ 4509 4510 static inline uint32_t iwx_reciprocal(uint32_t v) 4511 { 4512 if (!v) 4513 return 0; 4514 return 0xFFFFFFFF / v; 4515 } 4516 4517 /* Power Management Commands, Responses, Notifications */ 4518 4519 /** 4520 * masks for LTR config command flags 4521 * @IWX_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 4522 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 4523 * memory access 4524 * @IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 4525 * reg change 4526 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 4527 * D0 to D3 4528 * @IWX_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 4529 * @IWX_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 4530 * @IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 4531 */ 4532 #define IWX_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001 4533 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002 4534 #define IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004 4535 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008 4536 #define IWX_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010 4537 #define IWX_LTR_CFG_FLAG_SW_SET_LONG 0x00000020 4538 #define IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040 4539 4540 #define IWX_LTR_VALID_STATES_NUM 4 4541 4542 /** 4543 * struct iwx_ltr_config_cmd - configures the LTR 4544 * @flags: See %enum iwx_ltr_config_flags 4545 * @static_long: 4546 * @static_short: 4547 * @ltr_cfg_values: 4548 * @ltr_short_idle_timeout: 4549 */ 4550 struct iwx_ltr_config_cmd { 4551 uint32_t flags; 4552 uint32_t static_long; 4553 uint32_t static_short; 4554 uint32_t ltr_cfg_values[IWX_LTR_VALID_STATES_NUM]; 4555 uint32_t ltr_short_idle_timeout; 4556 } __packed; /* LTR_CAPABLE_API_S_VER_2 */ 4557 4558 /* Radio LP RX Energy Threshold measured in dBm */ 4559 #define IWX_POWER_LPRX_RSSI_THRESHOLD 75 4560 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MAX 94 4561 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MIN 30 4562 4563 /** 4564 * Masks for iwx_mac_power_cmd command flags 4565 * @IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 4566 * receiver and transmitter. '0' - does not allow. 4567 * @IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 4568 * '1' Driver enables PM (use rest of parameters) 4569 * @IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 4570 * '1' PM could sleep over DTIM till listen Interval. 4571 * @IWX_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 4572 * access categories are both delivery and trigger enabled. 4573 * @IWX_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 4574 * PBW Snoozing enabled 4575 * @IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 4576 * @IWX_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 4577 * @IWX_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 4578 * detection enablement 4579 */ 4580 #define IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 4581 #define IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1) 4582 #define IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2) 4583 #define IWX_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5) 4584 #define IWX_POWER_FLAGS_BT_SCO_ENA (1 << 8) 4585 #define IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9) 4586 #define IWX_POWER_FLAGS_LPRX_ENA_MSK (1 << 11) 4587 #define IWX_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12) 4588 4589 #define IWX_POWER_VEC_SIZE 5 4590 4591 /** 4592 * Masks for device power command flags 4593 * @IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 4594 * '1' Allow to save power by turning off receiver and transmitter. 4595 * '0' Do not allow. This flag should be always set to '1' unless 4596 * one needs to disable actual power down for debug purposes. 4597 * @IWX_DEVICE_POWER_FLAGS_CAM_MSK: 4598 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 4599 * '0' Power management is enabled, one of the power schemes is applied. 4600 */ 4601 #define IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 4602 #define IWX_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13) 4603 4604 /** 4605 * struct iwx_device_power_cmd - device wide power command. 4606 * IWX_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 4607 * 4608 * @flags: Power table command flags from IWX_DEVICE_POWER_FLAGS_* 4609 */ 4610 struct iwx_device_power_cmd { 4611 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 4612 uint16_t flags; 4613 uint16_t reserved; 4614 } __packed; 4615 4616 /** 4617 * struct iwx_mac_power_cmd - New power command containing uAPSD support 4618 * IWX_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 4619 * @id_and_color: MAC context identifier 4620 * @flags: Power table command flags from POWER_FLAGS_* 4621 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 4622 * Minimum allowed:- 3 * DTIM. Keep alive period must be 4623 * set regardless of power scheme or current power state. 4624 * FW use this value also when PM is disabled. 4625 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 4626 * PSM transition - legacy PM 4627 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 4628 * PSM transition - legacy PM 4629 * @sleep_interval: not in use 4630 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 4631 * is set. For example, if it is required to skip over 4632 * one DTIM, this value need to be set to 2 (DTIM periods). 4633 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 4634 * PSM transition - uAPSD 4635 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 4636 * PSM transition - uAPSD 4637 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 4638 * Default: 80dbm 4639 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 4640 * @snooze_interval: Maximum time between attempts to retrieve buffered data 4641 * from the AP [msec] 4642 * @snooze_window: A window of time in which PBW snoozing insures that all 4643 * packets received. It is also the minimum time from last 4644 * received unicast RX packet, before client stops snoozing 4645 * for data. [msec] 4646 * @snooze_step: TBD 4647 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 4648 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 4649 * each corresponding AC. 4650 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 4651 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 4652 * values. 4653 * @heavy_tx_thld_packets: TX threshold measured in number of packets 4654 * @heavy_rx_thld_packets: RX threshold measured in number of packets 4655 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 4656 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 4657 * @limited_ps_threshold: 4658 */ 4659 struct iwx_mac_power_cmd { 4660 /* CONTEXT_DESC_API_T_VER_1 */ 4661 uint32_t id_and_color; 4662 4663 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 4664 uint16_t flags; 4665 uint16_t keep_alive_seconds; 4666 uint32_t rx_data_timeout; 4667 uint32_t tx_data_timeout; 4668 uint32_t rx_data_timeout_uapsd; 4669 uint32_t tx_data_timeout_uapsd; 4670 uint8_t lprx_rssi_threshold; 4671 uint8_t skip_dtim_periods; 4672 uint16_t snooze_interval; 4673 uint16_t snooze_window; 4674 uint8_t snooze_step; 4675 uint8_t qndp_tid; 4676 uint8_t uapsd_ac_flags; 4677 uint8_t uapsd_max_sp; 4678 uint8_t heavy_tx_thld_packets; 4679 uint8_t heavy_rx_thld_packets; 4680 uint8_t heavy_tx_thld_percentage; 4681 uint8_t heavy_rx_thld_percentage; 4682 uint8_t limited_ps_threshold; 4683 uint8_t reserved; 4684 } __packed; 4685 4686 #define IWX_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 4687 #define IWX_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 4688 4689 /* 4690 * struct iwx_uapsd_misbehaving_ap_notif - FW sends this notification when 4691 * associated AP is identified as improperly implementing uAPSD protocol. 4692 * IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 4693 * @sta_id: index of station in uCode's station table - associated AP ID in 4694 * this context. 4695 */ 4696 struct iwx_uapsd_misbehaving_ap_notif { 4697 uint32_t sta_id; 4698 uint8_t mac_id; 4699 uint8_t reserved[3]; 4700 } __packed; 4701 4702 /** 4703 * struct iwx_beacon_filter_cmd 4704 * IWX_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 4705 * @id_and_color: MAC context identifier 4706 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 4707 * to driver if delta in Energy values calculated for this and last 4708 * passed beacon is greater than this threshold. Zero value means that 4709 * the Energy change is ignored for beacon filtering, and beacon will 4710 * not be forced to be sent to driver regardless of this delta. Typical 4711 * energy delta 5dB. 4712 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 4713 * Send beacon to driver if delta in Energy values calculated for this 4714 * and last passed beacon is greater than this threshold. Zero value 4715 * means that the Energy change is ignored for beacon filtering while in 4716 * Roaming state, typical energy delta 1dB. 4717 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 4718 * calculated for current beacon is less than the threshold, use 4719 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 4720 * Threshold. Typical energy threshold is -72dBm. 4721 * @bf_temp_threshold: This threshold determines the type of temperature 4722 * filtering (Slow or Fast) that is selected (Units are in Celsius): 4723 * If the current temperature is above this threshold - Fast filter 4724 * will be used, If the current temperature is below this threshold - 4725 * Slow filter will be used. 4726 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 4727 * calculated for this and the last passed beacon is greater than this 4728 * threshold. Zero value means that the temperature change is ignored for 4729 * beacon filtering; beacons will not be forced to be sent to driver 4730 * regardless of whether its temperature has been changed. 4731 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 4732 * calculated for this and the last passed beacon is greater than this 4733 * threshold. Zero value means that the temperature change is ignored for 4734 * beacon filtering; beacons will not be forced to be sent to driver 4735 * regardless of whether its temperature has been changed. 4736 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 4737 * @bf_escape_timer: Send beacons to driver if no beacons were passed 4738 * for a specific period of time. Units: Beacons. 4739 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 4740 * for a longer period of time then this escape-timeout. Units: Beacons. 4741 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 4742 * @bf_threshold_absolute_low: See below. 4743 * @bf_threshold_absolute_high: Send Beacon to driver if Energy value calculated 4744 * for this beacon crossed this absolute threshold. For the 'Increase' 4745 * direction the bf_energy_absolute_low[i] is used. For the 'Decrease' 4746 * direction the bf_energy_absolute_high[i] is used. Zero value means 4747 * that this specific threshold is ignored for beacon filtering, and 4748 * beacon will not be forced to be sent to driver due to this setting. 4749 */ 4750 struct iwx_beacon_filter_cmd { 4751 uint32_t bf_energy_delta; 4752 uint32_t bf_roaming_energy_delta; 4753 uint32_t bf_roaming_state; 4754 uint32_t bf_temp_threshold; 4755 uint32_t bf_temp_fast_filter; 4756 uint32_t bf_temp_slow_filter; 4757 uint32_t bf_enable_beacon_filter; 4758 uint32_t bf_debug_flag; 4759 uint32_t bf_escape_timer; 4760 uint32_t ba_escape_timer; 4761 uint32_t ba_enable_beacon_abort; 4762 uint32_t bf_threshold_absolute_low[2]; 4763 uint32_t bf_threshold_absolute_high[2]; 4764 } __packed; /* BEACON_FILTER_CONFIG_API_S_VER_4 */ 4765 4766 /* Beacon filtering and beacon abort */ 4767 #define IWX_BF_ENERGY_DELTA_DEFAULT 5 4768 #define IWX_BF_ENERGY_DELTA_MAX 255 4769 #define IWX_BF_ENERGY_DELTA_MIN 0 4770 4771 #define IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 4772 #define IWX_BF_ROAMING_ENERGY_DELTA_MAX 255 4773 #define IWX_BF_ROAMING_ENERGY_DELTA_MIN 0 4774 4775 #define IWX_BF_ROAMING_STATE_DEFAULT 72 4776 #define IWX_BF_ROAMING_STATE_MAX 255 4777 #define IWX_BF_ROAMING_STATE_MIN 0 4778 4779 #define IWX_BF_TEMP_THRESHOLD_DEFAULT 112 4780 #define IWX_BF_TEMP_THRESHOLD_MAX 255 4781 #define IWX_BF_TEMP_THRESHOLD_MIN 0 4782 4783 #define IWX_BF_TEMP_FAST_FILTER_DEFAULT 1 4784 #define IWX_BF_TEMP_FAST_FILTER_MAX 255 4785 #define IWX_BF_TEMP_FAST_FILTER_MIN 0 4786 4787 #define IWX_BF_TEMP_SLOW_FILTER_DEFAULT 5 4788 #define IWX_BF_TEMP_SLOW_FILTER_MAX 255 4789 #define IWX_BF_TEMP_SLOW_FILTER_MIN 0 4790 4791 #define IWX_BF_ENABLE_BEACON_FILTER_DEFAULT 1 4792 4793 #define IWX_BF_DEBUG_FLAG_DEFAULT 0 4794 4795 #define IWX_BF_ESCAPE_TIMER_DEFAULT 50 4796 #define IWX_BF_ESCAPE_TIMER_MAX 1024 4797 #define IWX_BF_ESCAPE_TIMER_MIN 0 4798 4799 #define IWX_BA_ESCAPE_TIMER_DEFAULT 6 4800 #define IWX_BA_ESCAPE_TIMER_D3 9 4801 #define IWX_BA_ESCAPE_TIMER_MAX 1024 4802 #define IWX_BA_ESCAPE_TIMER_MIN 0 4803 4804 #define IWX_BA_ENABLE_BEACON_ABORT_DEFAULT 1 4805 4806 #define IWX_BF_CMD_CONFIG_DEFAULTS \ 4807 .bf_energy_delta = htole32(IWX_BF_ENERGY_DELTA_DEFAULT), \ 4808 .bf_roaming_energy_delta = \ 4809 htole32(IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 4810 .bf_roaming_state = htole32(IWX_BF_ROAMING_STATE_DEFAULT), \ 4811 .bf_temp_threshold = htole32(IWX_BF_TEMP_THRESHOLD_DEFAULT), \ 4812 .bf_temp_fast_filter = htole32(IWX_BF_TEMP_FAST_FILTER_DEFAULT), \ 4813 .bf_temp_slow_filter = htole32(IWX_BF_TEMP_SLOW_FILTER_DEFAULT), \ 4814 .bf_debug_flag = htole32(IWX_BF_DEBUG_FLAG_DEFAULT), \ 4815 .bf_escape_timer = htole32(IWX_BF_ESCAPE_TIMER_DEFAULT), \ 4816 .ba_escape_timer = htole32(IWX_BA_ESCAPE_TIMER_DEFAULT) 4817 4818 /* uCode API values for HT/VHT bit rates */ 4819 #define IWX_RATE_HT_SISO_MCS_0_PLCP 0 4820 #define IWX_RATE_HT_SISO_MCS_1_PLCP 1 4821 #define IWX_RATE_HT_SISO_MCS_2_PLCP 2 4822 #define IWX_RATE_HT_SISO_MCS_3_PLCP 3 4823 #define IWX_RATE_HT_SISO_MCS_4_PLCP 4 4824 #define IWX_RATE_HT_SISO_MCS_5_PLCP 5 4825 #define IWX_RATE_HT_SISO_MCS_6_PLCP 6 4826 #define IWX_RATE_HT_SISO_MCS_7_PLCP 7 4827 #define IWX_RATE_HT_MIMO2_MCS_8_PLCP 0x8 4828 #define IWX_RATE_HT_MIMO2_MCS_9_PLCP 0x9 4829 #define IWX_RATE_HT_MIMO2_MCS_10_PLCP 0xA 4830 #define IWX_RATE_HT_MIMO2_MCS_11_PLCP 0xB 4831 #define IWX_RATE_HT_MIMO2_MCS_12_PLCP 0xC 4832 #define IWX_RATE_HT_MIMO2_MCS_13_PLCP 0xD 4833 #define IWX_RATE_HT_MIMO2_MCS_14_PLCP 0xE 4834 #define IWX_RATE_HT_MIMO2_MCS_15_PLCP 0xF 4835 #define IWX_RATE_VHT_SISO_MCS_0_PLCP 0 4836 #define IWX_RATE_VHT_SISO_MCS_1_PLCP 1 4837 #define IWX_RATE_VHT_SISO_MCS_2_PLCP 2 4838 #define IWX_RATE_VHT_SISO_MCS_3_PLCP 3 4839 #define IWX_RATE_VHT_SISO_MCS_4_PLCP 4 4840 #define IWX_RATE_VHT_SISO_MCS_5_PLCP 5 4841 #define IWX_RATE_VHT_SISO_MCS_6_PLCP 6 4842 #define IWX_RATE_VHT_SISO_MCS_7_PLCP 7 4843 #define IWX_RATE_VHT_SISO_MCS_8_PLCP 8 4844 #define IWX_RATE_VHT_SISO_MCS_9_PLCP 9 4845 #define IWX_RATE_VHT_MIMO2_MCS_0_PLCP 0x10 4846 #define IWX_RATE_VHT_MIMO2_MCS_1_PLCP 0x11 4847 #define IWX_RATE_VHT_MIMO2_MCS_2_PLCP 0x12 4848 #define IWX_RATE_VHT_MIMO2_MCS_3_PLCP 0x13 4849 #define IWX_RATE_VHT_MIMO2_MCS_4_PLCP 0x14 4850 #define IWX_RATE_VHT_MIMO2_MCS_5_PLCP 0x15 4851 #define IWX_RATE_VHT_MIMO2_MCS_6_PLCP 0x16 4852 #define IWX_RATE_VHT_MIMO2_MCS_7_PLCP 0x17 4853 #define IWX_RATE_VHT_MIMO2_MCS_8_PLCP 0x18 4854 #define IWX_RATE_VHT_MIMO2_MCS_9_PLCP 0x19 4855 #define IWX_RATE_HT_SISO_MCS_INV_PLCP 0x20 4856 #define IWX_RATE_HT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4857 #define IWX_RATE_VHT_SISO_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4858 #define IWX_RATE_VHT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4859 #define IWX_RATE_HT_SISO_MCS_8_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4860 #define IWX_RATE_HT_SISO_MCS_9_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4861 4862 /* 4863 * These serve as indexes into struct iwx_rate iwx_rates[IWX_RIDX_MAX]. 4864 */ 4865 enum { 4866 IWX_RATE_1M_INDEX = 0, 4867 IWX_FIRST_CCK_RATE = IWX_RATE_1M_INDEX, 4868 IWX_RATE_2M_INDEX, 4869 IWX_RATE_5M_INDEX, 4870 IWX_RATE_11M_INDEX, 4871 IWX_LAST_CCK_RATE = IWX_RATE_11M_INDEX, 4872 IWX_RATE_6M_INDEX, 4873 IWX_FIRST_OFDM_RATE = IWX_RATE_6M_INDEX, 4874 IWX_RATE_MCS_0_INDEX = IWX_RATE_6M_INDEX, 4875 IWX_FIRST_HT_RATE = IWX_RATE_MCS_0_INDEX, 4876 IWX_FIRST_VHT_RATE = IWX_RATE_MCS_0_INDEX, 4877 IWX_RATE_9M_INDEX, 4878 IWX_RATE_12M_INDEX, 4879 IWX_RATE_MCS_1_INDEX = IWX_RATE_12M_INDEX, 4880 IWX_RATE_MCS_8_INDEX, 4881 IWX_FIRST_HT_MIMO2_RATE = IWX_RATE_MCS_8_INDEX, 4882 IWX_RATE_18M_INDEX, 4883 IWX_RATE_MCS_2_INDEX = IWX_RATE_18M_INDEX, 4884 IWX_RATE_24M_INDEX, 4885 IWX_RATE_MCS_3_INDEX = IWX_RATE_24M_INDEX, 4886 IWX_RATE_MCS_9_INDEX, 4887 IWX_RATE_36M_INDEX, 4888 IWX_RATE_MCS_4_INDEX = IWX_RATE_36M_INDEX, 4889 IWX_RATE_MCS_10_INDEX, 4890 IWX_RATE_48M_INDEX, 4891 IWX_RATE_MCS_5_INDEX = IWX_RATE_48M_INDEX, 4892 IWX_RATE_MCS_11_INDEX, 4893 IWX_RATE_54M_INDEX, 4894 IWX_RATE_MCS_6_INDEX = IWX_RATE_54M_INDEX, 4895 IWX_LAST_NON_HT_RATE = IWX_RATE_54M_INDEX, 4896 IWX_RATE_MCS_7_INDEX, 4897 IWX_LAST_HT_SISO_RATE = IWX_RATE_MCS_7_INDEX, 4898 IWX_RATE_MCS_12_INDEX, 4899 IWX_RATE_MCS_13_INDEX, 4900 IWX_RATE_MCS_14_INDEX, 4901 IWX_RATE_MCS_15_INDEX, 4902 IWX_LAST_HT_RATE = IWX_RATE_MCS_15_INDEX, 4903 IWX_LAST_VHT_RATE = IWX_RATE_MCS_9_INDEX, 4904 IWX_RATE_COUNT_LEGACY = IWX_LAST_NON_HT_RATE + 1, 4905 IWX_RATE_COUNT = IWX_LAST_HT_RATE + 1, 4906 }; 4907 4908 #define IWX_RATE_BIT_MSK(r) (1 << (IWX_RATE_##r##M_INDEX)) 4909 4910 /* fw API values for legacy bit rates, both OFDM and CCK */ 4911 #define IWX_RATE_6M_PLCP 13 4912 #define IWX_RATE_9M_PLCP 15 4913 #define IWX_RATE_12M_PLCP 5 4914 #define IWX_RATE_18M_PLCP 7 4915 #define IWX_RATE_24M_PLCP 9 4916 #define IWX_RATE_36M_PLCP 11 4917 #define IWX_RATE_48M_PLCP 1 4918 #define IWX_RATE_54M_PLCP 3 4919 #define IWX_RATE_1M_PLCP 10 4920 #define IWX_RATE_2M_PLCP 20 4921 #define IWX_RATE_5M_PLCP 55 4922 #define IWX_RATE_11M_PLCP 110 4923 #define IWX_RATE_INVM_PLCP 0xff 4924 4925 /* 4926 * rate_n_flags bit fields version 1 4927 * 4928 * The 32-bit value has different layouts in the low 8 bites depending on the 4929 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 4930 * for CCK and OFDM). 4931 * 4932 * High-throughput (HT) rate format 4933 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 4934 * Very High-throughput (VHT) rate format 4935 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 4936 * Legacy OFDM rate format for bits 7:0 4937 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 4938 * Legacy CCK rate format for bits 7:0: 4939 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 4940 */ 4941 4942 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 4943 #define IWX_RATE_MCS_HT_POS 8 4944 #define IWX_RATE_MCS_HT_MSK_V1 (1 << IWX_RATE_MCS_HT_POS) 4945 4946 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 4947 #define IWX_RATE_MCS_CCK_POS_V1 9 4948 #define IWX_RATE_MCS_CCK_MSK_V1 (1 << IWX_RATE_MCS_CCK_POS_V1) 4949 4950 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 4951 #define IWX_RATE_MCS_VHT_POS_V1 26 4952 #define IWX_RATE_MCS_VHT_MSK_V1 (1 << IWX_RATE_MCS_VHT_POS_V1) 4953 4954 4955 /* 4956 * High-throughput (HT) rate format for bits 7:0 4957 * 4958 * 2-0: MCS rate base 4959 * 0) 6 Mbps 4960 * 1) 12 Mbps 4961 * 2) 18 Mbps 4962 * 3) 24 Mbps 4963 * 4) 36 Mbps 4964 * 5) 48 Mbps 4965 * 6) 54 Mbps 4966 * 7) 60 Mbps 4967 * 4-3: 0) Single stream (SISO) 4968 * 1) Dual stream (MIMO) 4969 * 2) Triple stream (MIMO) 4970 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4971 * (bits 7-6 are zero) 4972 * 4973 * Together the low 5 bits work out to the MCS index because we don't 4974 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4975 * streams and 16-23 have three streams. We could also support MCS 32 4976 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4977 */ 4978 #define IWX_RATE_HT_MCS_RATE_CODE_MSK_V1 0x7 4979 #define IWX_RATE_HT_MCS_NSS_POS_V1 3 4980 #define IWX_RATE_HT_MCS_NSS_MSK_V1 (3 << IWX_RATE_HT_MCS_NSS_POS_V1) 4981 #define IWX_RATE_HT_MCS_MIMO2_MSK_V1 (1 << IWX_RATE_HT_MCS_NSS_POS_V1) 4982 4983 /* Bit 10: (1) Use Green Field preamble */ 4984 #define IWX_RATE_HT_MCS_GF_POS 10 4985 #define IWX_RATE_HT_MCS_GF_MSK (1 << IWX_RATE_HT_MCS_GF_POS) 4986 4987 #define IWX_RATE_HT_MCS_INDEX_MSK_V1 0x3f 4988 4989 /* 4990 * Very High-throughput (VHT) rate format for bits 7:0 4991 * 4992 * 3-0: VHT MCS (0-9) 4993 * 5-4: number of streams - 1: 4994 * 0) Single stream (SISO) 4995 * 1) Dual stream (MIMO) 4996 * 2) Triple stream (MIMO) 4997 */ 4998 4999 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 5000 #define IWX_RATE_VHT_MCS_RATE_CODE_MSK 0xf 5001 #define IWX_RATE_VHT_MCS_NSS_POS 4 5002 #define IWX_RATE_VHT_MCS_NSS_MSK (3 << IWX_RATE_VHT_MCS_NSS_POS) 5003 #define IWX_RATE_VHT_MCS_MIMO2_MSK (1 << IWX_RATE_VHT_MCS_NSS_POS) 5004 5005 /* 5006 * Legacy OFDM rate format for bits 7:0 5007 * 5008 * 3-0: 0xD) 6 Mbps 5009 * 0xF) 9 Mbps 5010 * 0x5) 12 Mbps 5011 * 0x7) 18 Mbps 5012 * 0x9) 24 Mbps 5013 * 0xB) 36 Mbps 5014 * 0x1) 48 Mbps 5015 * 0x3) 54 Mbps 5016 * (bits 7-4 are 0) 5017 * 5018 * Legacy CCK rate format for bits 7:0: 5019 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 5020 * 5021 * 6-0: 10) 1 Mbps 5022 * 20) 2 Mbps 5023 * 55) 5.5 Mbps 5024 * 110) 11 Mbps 5025 * (bit 7 is 0) 5026 */ 5027 #define IWX_RATE_LEGACY_RATE_MSK_V1 0xff 5028 5029 /* Bit 10 - OFDM HE */ 5030 #define IWX_RATE_MCS_HE_POS_V1 10 5031 #define IWX_RATE_MCS_HE_MSK_V1 (1 << RATE_MCS_HE_POS_V1) 5032 5033 /* 5034 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 5035 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 5036 */ 5037 #define IWX_RATE_MCS_CHAN_WIDTH_POS 11 5038 #define IWX_RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5039 #define IWX_RATE_MCS_CHAN_WIDTH_20_V1 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5040 #define IWX_RATE_MCS_CHAN_WIDTH_40_V1 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5041 #define IWX_RATE_MCS_CHAN_WIDTH_80_V1 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5042 #define IWX_RATE_MCS_CHAN_WIDTH_160_V1 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5043 5044 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 5045 #define IWX_RATE_MCS_SGI_POS_V1 13 5046 #define IWX_RATE_MCS_SGI_MSK_V1 (1 << IWX_RATE_MCS_SGI_POS_V1) 5047 5048 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C (unused) */ 5049 #define IWX_RATE_MCS_ANT_POS 14 5050 #define IWX_RATE_MCS_ANT_A_MSK (1 << IWX_RATE_MCS_ANT_POS) 5051 #define IWX_RATE_MCS_ANT_B_MSK (2 << IWX_RATE_MCS_ANT_POS) 5052 #define IWX_RATE_MCS_ANT_AB_MSK (IWX_RATE_MCS_ANT_A_MSK | \ 5053 IWX_RATE_MCS_ANT_B_MSK) 5054 #define IWX_RATE_MCS_ANT_MSK IWX_RATE_MCS_ANT_ABC_MSK 5055 #define IWX_RATE_MCS_ANT_NUM 2 5056 5057 /* Bit 17: (0) SS, (1) SS*2 */ 5058 #define IWX_RATE_MCS_STBC_POS 17 5059 #define IWX_RATE_MCS_STBC_MSK (1 << IWX_RATE_MCS_STBC_POS) 5060 5061 /* Bit 18: OFDM-HE dual carrier mode */ 5062 #define IWX_RATE_HE_DUAL_CARRIER_MODE 18 5063 #define IWX_RATE_HE_DUAL_CARRIER_MODE_MSK (1 << IWX_RATE_HE_DUAL_CARRIER_MODE) 5064 5065 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 5066 #define IWX_RATE_MCS_BF_POS 19 5067 #define IWX_RATE_MCS_BF_MSK (1 << IWX_RATE_MCS_BF_POS) 5068 5069 /* 5070 * Bit 20-21: HE LTF type and guard interval 5071 * HE (ext) SU: 5072 * 0 1xLTF+0.8us 5073 * 1 2xLTF+0.8us 5074 * 2 2xLTF+1.6us 5075 * 3 & SGI (bit 13) clear 4xLTF+3.2us 5076 * 3 & SGI (bit 13) set 4xLTF+0.8us 5077 * HE MU: 5078 * 0 4xLTF+0.8us 5079 * 1 2xLTF+0.8us 5080 * 2 2xLTF+1.6us 5081 * 3 4xLTF+3.2us 5082 * HE TRIG: 5083 * 0 1xLTF+1.6us 5084 * 1 2xLTF+1.6us 5085 * 2 4xLTF+3.2us 5086 * 3 (does not occur) 5087 */ 5088 #define IWX_RATE_MCS_HE_GI_LTF_POS 20 5089 #define IWX_RATE_MCS_HE_GI_LTF_MSK_V1 (3 << IWX_RATE_MCS_HE_GI_LTF_POS) 5090 5091 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 5092 #define IWX_RATE_MCS_HE_TYPE_POS_V1 22 5093 #define IWX_RATE_MCS_HE_TYPE_SU_V1 (0 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5094 #define IWX_RATE_MCS_HE_TYPE_EXT_SU_V1 (1 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5095 #define IWX_RATE_MCS_HE_TYPE_MU_V1 (2 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5096 #define IWX_RATE_MCS_HE_TYPE_TRIG_V1 (3 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5097 #define IWX_RATE_MCS_HE_TYPE_MSK_V1 (3 << IWX_RATE_MCS_HE_TYPE_POS_V1) 5098 5099 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 5100 #define IWX_RATE_MCS_DUP_POS_V1 24 5101 #define IWX_RATE_MCS_DUP_MSK_V1 (3 << IWX_RATE_MCS_DUP_POS_V1) 5102 5103 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 5104 #define IWX_RATE_MCS_LDPC_POS_V1 27 5105 #define IWX_RATE_MCS_LDPC_MSK_V1 (1 << IWX_RATE_MCS_LDPC_POS_V1) 5106 5107 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 5108 #define IWX_RATE_MCS_HE_106T_POS_V1 28 5109 #define IWX_RATE_MCS_HE_106T_MSK_V1 (1 << IWX_RATE_MCS_HE_106T_POS_V1) 5110 5111 /* Bit 30-31: (1) RTS, (2) CTS */ 5112 #define IWX_RATE_MCS_RTS_REQUIRED_POS (30) 5113 #define IWX_RATE_MCS_RTS_REQUIRED_MSK (1 << IWX_RATE_MCS_RTS_REQUIRED_POS) 5114 #define IWX_RATE_MCS_CTS_REQUIRED_POS (31) 5115 #define IWX_RATE_MCS_CTS_REQUIRED_MSK (1 << IWX_RATE_MCS_CTS_REQUIRED_POS) 5116 5117 5118 /* rate_n_flags bit field version 2 5119 * 5120 * The 32-bit value has different layouts in the low 8 bits depending on the 5121 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 5122 * for CCK and OFDM). 5123 * 5124 */ 5125 5126 /* Bits 10-8: rate format 5127 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT) 5128 * (3) Very High-throughput (VHT) (4) High-efficiency (HE) 5129 * (5) Extremely High-throughput (EHT) 5130 */ 5131 #define IWX_RATE_MCS_MOD_TYPE_POS 8 5132 #define IWX_RATE_MCS_MOD_TYPE_MSK (0x7 << IWX_RATE_MCS_MOD_TYPE_POS) 5133 #define IWX_RATE_MCS_CCK_MSK (0 << IWX_RATE_MCS_MOD_TYPE_POS) 5134 #define IWX_RATE_MCS_LEGACY_OFDM_MSK (1 << IWX_RATE_MCS_MOD_TYPE_POS) 5135 #define IWX_RATE_MCS_HT_MSK (2 << IWX_RATE_MCS_MOD_TYPE_POS) 5136 #define IWX_RATE_MCS_VHT_MSK (3 << IWX_RATE_MCS_MOD_TYPE_POS) 5137 #define IWX_RATE_MCS_HE_MSK (4 << IWX_RATE_MCS_MOD_TYPE_POS) 5138 #define IWX_RATE_MCS_EHT_MSK (5 << IWX_RATE_MCS_MOD_TYPE_POS) 5139 5140 /* 5141 * Legacy CCK rate format for bits 0:3: 5142 * 5143 * (0) 0xa - 1 Mbps 5144 * (1) 0x14 - 2 Mbps 5145 * (2) 0x37 - 5.5 Mbps 5146 * (3) 0x6e - 11 nbps 5147 * 5148 * Legacy OFDM rate format for bits 0:3: 5149 * 5150 * (0) 6 Mbps 5151 * (1) 9 Mbps 5152 * (2) 12 Mbps 5153 * (3) 18 Mbps 5154 * (4) 24 Mbps 5155 * (5) 36 Mbps 5156 * (6) 48 Mbps 5157 * (7) 54 Mbps 5158 * 5159 */ 5160 #define IWX_RATE_LEGACY_RATE_MSK 0x7 5161 5162 /* 5163 * HT, VHT, HE, EHT rate format for bits 3:0 5164 * 3-0: MCS 5165 * 5166 */ 5167 #define IWX_RATE_HT_MCS_CODE_MSK 0x7 5168 #define IWX_RATE_MCS_NSS_POS 4 5169 #define IWX_RATE_MCS_NSS_MSK (1 << IWX_RATE_MCS_NSS_POS) 5170 #define IWX_RATE_MCS_CODE_MSK 0xf 5171 #define IWX_RATE_HT_MCS_INDEX(r) ((((r) & IWX_RATE_MCS_NSS_MSK) >> 1) | \ 5172 ((r) & IWX_RATE_HT_MCS_CODE_MSK)) 5173 5174 /* Bits 7-5: reserved */ 5175 5176 /* 5177 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz 5178 */ 5179 #define IWX_RATE_MCS_CHAN_WIDTH_MSK (0x7 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5180 #define IWX_RATE_MCS_CHAN_WIDTH_20 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5181 #define IWX_RATE_MCS_CHAN_WIDTH_40 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5182 #define IWX_RATE_MCS_CHAN_WIDTH_80 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5183 #define IWX_RATE_MCS_CHAN_WIDTH_160 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5184 #define IWX_RATE_MCS_CHAN_WIDTH_320 (4 << IWX_RATE_MCS_CHAN_WIDTH_POS) 5185 5186 /* Bit 15-14: Antenna selection: 5187 * Bit 14: Ant A active 5188 * Bit 15: Ant B active 5189 * 5190 * All relevant definitions are same as in v1 5191 */ 5192 5193 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */ 5194 #define IWX_RATE_MCS_LDPC_POS 16 5195 #define IWX_RATE_MCS_LDPC_MSK (1 << IWX_RATE_MCS_LDPC_POS) 5196 5197 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */ 5198 5199 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */ 5200 5201 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */ 5202 5203 /* 5204 * Bit 22-20: HE LTF type and guard interval 5205 * CCK: 5206 * 0 long preamble 5207 * 1 short preamble 5208 * HT/VHT: 5209 * 0 0.8us 5210 * 1 0.4us 5211 * HE (ext) SU: 5212 * 0 1xLTF+0.8us 5213 * 1 2xLTF+0.8us 5214 * 2 2xLTF+1.6us 5215 * 3 4xLTF+3.2us 5216 * 4 4xLTF+0.8us 5217 * HE MU: 5218 * 0 4xLTF+0.8us 5219 * 1 2xLTF+0.8us 5220 * 2 2xLTF+1.6us 5221 * 3 4xLTF+3.2us 5222 * HE TRIG: 5223 * 0 1xLTF+1.6us 5224 * 1 2xLTF+1.6us 5225 * 2 4xLTF+3.2us 5226 * */ 5227 #define IWX_RATE_MCS_HE_GI_LTF_MSK (0x7 << IWX_RATE_MCS_HE_GI_LTF_POS) 5228 #define IWX_RATE_MCS_SGI_POS IWX_RATE_MCS_HE_GI_LTF_POS 5229 #define IWX_RATE_MCS_SGI_MSK (1 << IWX_RATE_MCS_SGI_POS) 5230 #define IWX_RATE_MCS_HE_SU_4_LTF 3 5231 #define IWX_RATE_MCS_HE_SU_4_LTF_08_GI 4 5232 5233 /* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */ 5234 #define IWX_RATE_MCS_HE_TYPE_POS 23 5235 #define IWX_RATE_MCS_HE_TYPE_SU (0 << IWX_RATE_MCS_HE_TYPE_POS) 5236 #define IWX_RATE_MCS_HE_TYPE_EXT_SU (1 << IWX_RATE_MCS_HE_TYPE_POS) 5237 #define IWX_RATE_MCS_HE_TYPE_MU (2 << IWX_RATE_MCS_HE_TYPE_POS) 5238 #define IWX_RATE_MCS_HE_TYPE_TRIG (3 << IWX_RATE_MCS_HE_TYPE_POS) 5239 #define IWX_RATE_MCS_HE_TYPE_MSK (3 << IWX_RATE_MCS_HE_TYPE_POS) 5240 5241 /* Bit 25: duplicate channel enabled 5242 * 5243 * if this bit is set, duplicate is according to BW (bits 11-13): 5244 * 5245 * CCK: 2x 20MHz 5246 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16) 5247 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160) 5248 * */ 5249 #define IWX_RATE_MCS_DUP_POS 25 5250 #define IWX_RATE_MCS_DUP_MSK (1 << IWX_RATE_MCS_DUP_POS) 5251 5252 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */ 5253 #define IWX_RATE_MCS_HE_106T_POS 26 5254 #define IWX_RATE_MCS_HE_106T_MSK (1 << IWX_RATE_MCS_HE_106T_POS) 5255 5256 /* Bit 27: EHT extra LTF: 5257 * instead of 1 LTF for SISO use 2 LTFs, 5258 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/ 5259 #define IWX_RATE_MCS_EHT_EXTRA_LTF_POS 27 5260 #define IWX_RATE_MCS_EHT_EXTRA_LTF_MSK (1 << IWX_RATE_MCS_EHT_EXTRA_LTF_POS) 5261 5262 /* Bit 31-28: reserved */ 5263 5264 5265 /* Link Quality definitions */ 5266 5267 /* # entries in rate scale table to support Tx retries */ 5268 #define IWX_LQ_MAX_RETRY_NUM 16 5269 5270 /* Link quality command flags bit fields */ 5271 5272 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 5273 #define IWX_LQ_FLAG_USE_RTS_POS 0 5274 #define IWX_LQ_FLAG_USE_RTS_MSK (1 << IWX_LQ_FLAG_USE_RTS_POS) 5275 5276 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 5277 #define IWX_LQ_FLAG_COLOR_POS 1 5278 #define IWX_LQ_FLAG_COLOR_MSK (7 << IWX_LQ_FLAG_COLOR_POS) 5279 5280 /* Bit 4-5: Tx RTS BW Signalling 5281 * (0) No RTS BW signalling 5282 * (1) Static BW signalling 5283 * (2) Dynamic BW signalling 5284 */ 5285 #define IWX_LQ_FLAG_RTS_BW_SIG_POS 4 5286 #define IWX_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 5287 #define IWX_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 5288 #define IWX_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 5289 5290 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 5291 * Dynamic BW selection allows Tx with narrower BW then requested in rates 5292 */ 5293 #define IWX_LQ_FLAG_DYNAMIC_BW_POS 6 5294 #define IWX_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWX_LQ_FLAG_DYNAMIC_BW_POS) 5295 5296 #define IWX_RLC_CHAIN_INFO_DRIVER_FORCE (1 << 0) 5297 #define IWL_RLC_CHAIN_INFO_VALID 0x000e 5298 #define IWL_RLC_CHAIN_INFO_FORCE 0x0070 5299 #define IWL_RLC_CHAIN_INFO_FORCE_MIMO 0x0380 5300 #define IWL_RLC_CHAIN_INFO_COUNT 0x0c00 5301 #define IWL_RLC_CHAIN_INFO_MIMO_COUNT 0x3000 5302 5303 /** 5304 * struct iwx_rlc_properties - RLC properties 5305 * @rx_chain_info: RX chain info, IWX_RLC_CHAIN_INFO_* 5306 * @reserved: reserved 5307 */ 5308 struct iwx_rlc_properties { 5309 uint32_t rx_chain_info; 5310 uint32_t reserved; 5311 } __packed; /* RLC_PROPERTIES_S_VER_1 */ 5312 5313 #define IWX_SAD_MODE_ENABLED (1 << 0) 5314 #define IWX_SAD_MODE_DEFAULT_ANT_MSK 0x6 5315 #define IWX_SAD_MODE_DEFAULT_ANT_FW 0x0 5316 #define IWX_SAD_MODE_DEFAULT_ANT_A 0x2 5317 #define IWX_SAD_MODE_DEFAULT_ANT_B 0x4 5318 5319 /** 5320 * struct iwx_sad_properties - SAD properties 5321 * @chain_a_sad_mode: chain A SAD mode, IWX_SAD_MODE_* 5322 * @chain_b_sad_mode: chain B SAD mode, IWX_SAD_MODE_* 5323 * @mac_id: MAC index 5324 * @reserved: reserved 5325 */ 5326 struct iwx_sad_properties { 5327 uint32_t chain_a_sad_mode; 5328 uint32_t chain_b_sad_mode; 5329 uint32_t mac_id; 5330 uint32_t reserved; 5331 } __packed; 5332 5333 /** 5334 * struct iwx_rlc_config_cmd - RLC configuration 5335 * @phy_id: PHY index 5336 * @rlc: RLC properties, &struct iwx_rlc_properties 5337 * @sad: SAD (single antenna diversity) options, &struct iwx_sad_properties 5338 * @flags: flags, IWX_RLC_FLAGS_* 5339 * @reserved: reserved 5340 */ 5341 struct iwx_rlc_config_cmd { 5342 uint32_t phy_id; 5343 struct iwx_rlc_properties rlc; 5344 struct iwx_sad_properties sad; 5345 uint8_t flags; 5346 uint8_t reserved[3]; 5347 } __packed; /* RLC_CONFIG_CMD_API_S_VER_2 */ 5348 5349 #define IWX_MAX_BAID_OLD 16 /* MAX_IMMEDIATE_BA_API_D_VER_2 */ 5350 #define IWX_MAX_BAID 32 /* MAX_IMMEDIATE_BA_API_D_VER_3 */ 5351 5352 /** 5353 * BAID allocation/config action 5354 * @IWX_RX_BAID_ACTION_ADD: add a new BAID session 5355 * @IWX_RX_BAID_ACTION_MODIFY: modify the BAID session 5356 * @IWX_RX_BAID_ACTION_REMOVE: remove the BAID session 5357 */ 5358 #define IWX_RX_BAID_ACTION_ADD 0 5359 #define IWX_RX_BAID_ACTION_MODIFY 1 5360 #define IWX_RX_BAID_ACTION_REMOVE 2 5361 /* RX_BAID_ALLOCATION_ACTION_E_VER_1 */ 5362 5363 /** 5364 * struct iwx_rx_baid_cfg_cmd_alloc - BAID allocation data 5365 * @sta_id_mask: station ID mask 5366 * @tid: the TID for this session 5367 * @reserved: reserved 5368 * @ssn: the starting sequence number 5369 * @win_size: RX BA session window size 5370 */ 5371 struct iwx_rx_baid_cfg_cmd_alloc { 5372 uint32_t sta_id_mask; 5373 uint8_t tid; 5374 uint8_t reserved[3]; 5375 uint16_t ssn; 5376 uint16_t win_size; 5377 } __packed; /* RX_BAID_ALLOCATION_ADD_CMD_API_S_VER_1 */ 5378 5379 /** 5380 * struct iwx_rx_baid_cfg_cmd_modify - BAID modification data 5381 * @old_sta_id_mask: old station ID mask 5382 * @new_sta_id_mask: new station ID mask 5383 * @tid: TID of the BAID 5384 */ 5385 struct iwx_rx_baid_cfg_cmd_modify { 5386 uint32_t old_sta_id_mask; 5387 uint32_t new_sta_id_mask; 5388 uint32_t tid; 5389 } __packed; /* RX_BAID_ALLOCATION_MODIFY_CMD_API_S_VER_2 */ 5390 5391 /** 5392 * struct iwx_rx_baid_cfg_cmd_remove_v1 - BAID removal data 5393 * @baid: the BAID to remove 5394 */ 5395 struct iwx_rx_baid_cfg_cmd_remove_v1 { 5396 uint32_t baid; 5397 } __packed; /* RX_BAID_ALLOCATION_REMOVE_CMD_API_S_VER_1 */ 5398 5399 /** 5400 * struct iwx_rx_baid_cfg_cmd_remove - BAID removal data 5401 * @sta_id_mask: the station mask of the BAID to remove 5402 * @tid: the TID of the BAID to remove 5403 */ 5404 struct iwx_rx_baid_cfg_cmd_remove { 5405 uint32_t sta_id_mask; 5406 uint32_t tid; 5407 } __packed; /* RX_BAID_ALLOCATION_REMOVE_CMD_API_S_VER_2 */ 5408 5409 /** 5410 * struct iwx_rx_baid_cfg_cmd - BAID allocation/config command 5411 * @action: the action, from &enum iwx_rx_baid_action 5412 */ 5413 struct iwx_rx_baid_cfg_cmd { 5414 uint32_t action; 5415 union { 5416 struct iwx_rx_baid_cfg_cmd_alloc alloc; 5417 struct iwx_rx_baid_cfg_cmd_modify modify; 5418 struct iwx_rx_baid_cfg_cmd_remove_v1 remove_v1; 5419 struct iwx_rx_baid_cfg_cmd_remove remove; 5420 }; /* RX_BAID_ALLOCATION_OPERATION_API_U_VER_2 */ 5421 } __packed; /* RX_BAID_ALLOCATION_CONFIG_CMD_API_S_VER_2 */ 5422 5423 /** 5424 * struct iwx_rx_baid_cfg_resp - BAID allocation response 5425 * @baid: the allocated BAID 5426 */ 5427 struct iwx_rx_baid_cfg_resp { 5428 uint32_t baid; 5429 }; /* RX_BAID_ALLOCATION_RESPONSE_API_S_VER_1 */ 5430 5431 /** 5432 * Options for TLC config flags 5433 * @IWX_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for 5434 * bandwidths <= 80MHz 5435 * @IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC 5436 * @IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz 5437 * bandwidth 5438 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation 5439 * for BPSK (MCS 0) with 1 spatial 5440 * stream 5441 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation 5442 * for BPSK (MCS 0) with 2 spatial 5443 * streams 5444 */ 5445 #define IWX_TLC_MNG_CFG_FLAGS_STBC_MSK (1 << 0) 5446 #define IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK (1 << 1) 5447 #define IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK (1 << 2) 5448 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK (1 << 3) 5449 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK (1 << 4) 5450 5451 /** 5452 * enum iwx_tlc_mng_cfg_cw - channel width options 5453 * @IWX_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel 5454 * @IWX_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel 5455 * @IWX_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel 5456 * @IWX_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel 5457 * @IWX_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel 5458 */ 5459 enum iwx_tlc_mng_cfg_cw { 5460 IWX_TLC_MNG_CH_WIDTH_20MHZ, 5461 IWX_TLC_MNG_CH_WIDTH_40MHZ, 5462 IWX_TLC_MNG_CH_WIDTH_80MHZ, 5463 IWX_TLC_MNG_CH_WIDTH_160MHZ, 5464 IWX_TLC_MNG_CH_WIDTH_320MHZ, 5465 }; 5466 5467 /** 5468 * @IWX_TLC_MNG_CHAIN_A_MSK: chain A 5469 * @IWX_TLC_MNG_CHAIN_B_MSK: chain B 5470 */ 5471 #define IWX_TLC_MNG_CHAIN_A_MSK (1 << 0) 5472 #define IWX_TLC_MNG_CHAIN_B_MSK (1 << 1) 5473 5474 /** 5475 * enum iwx_tlc_mng_cfg_mode - supported modes 5476 * @IWX_TLC_MNG_MODE_CCK: enable CCK 5477 * @IWX_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT) 5478 * @IWX_TLC_MNG_MODE_NON_HT: enable non HT 5479 * @IWX_TLC_MNG_MODE_HT: enable HT 5480 * @IWX_TLC_MNG_MODE_VHT: enable VHT 5481 * @IWX_TLC_MNG_MODE_HE: enable HE 5482 * @IWX_TLC_MNG_MODE_EHT: enable EHT 5483 */ 5484 enum iwx_tlc_mng_cfg_mode { 5485 IWX_TLC_MNG_MODE_CCK = 0, 5486 IWX_TLC_MNG_MODE_OFDM_NON_HT = IWX_TLC_MNG_MODE_CCK, 5487 IWX_TLC_MNG_MODE_NON_HT = IWX_TLC_MNG_MODE_CCK, 5488 IWX_TLC_MNG_MODE_HT, 5489 IWX_TLC_MNG_MODE_VHT, 5490 IWX_TLC_MNG_MODE_HE, 5491 IWX_TLC_MNG_MODE_EHT, 5492 }; 5493 5494 /** 5495 * @IWX_TLC_MNG_HT_RATE_MCS0: index of MCS0 5496 * @IWX_TLC_MNG_HT_RATE_MCS1: index of MCS1 5497 * @IWX_TLC_MNG_HT_RATE_MCS2: index of MCS2 5498 * @IWX_TLC_MNG_HT_RATE_MCS3: index of MCS3 5499 * @IWX_TLC_MNG_HT_RATE_MCS4: index of MCS4 5500 * @IWX_TLC_MNG_HT_RATE_MCS5: index of MCS5 5501 * @IWX_TLC_MNG_HT_RATE_MCS6: index of MCS6 5502 * @IWX_TLC_MNG_HT_RATE_MCS7: index of MCS7 5503 * @IWX_TLC_MNG_HT_RATE_MCS8: index of MCS8 5504 * @IWX_TLC_MNG_HT_RATE_MCS9: index of MCS9 5505 * @IWX_TLC_MNG_HT_RATE_MCS10: index of MCS10 5506 * @IWX_TLC_MNG_HT_RATE_MCS11: index of MCS11 5507 * @IWX_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT 5508 */ 5509 enum iwx_tlc_mng_ht_rates { 5510 IWX_TLC_MNG_HT_RATE_MCS0 = 0, 5511 IWX_TLC_MNG_HT_RATE_MCS1, 5512 IWX_TLC_MNG_HT_RATE_MCS2, 5513 IWX_TLC_MNG_HT_RATE_MCS3, 5514 IWX_TLC_MNG_HT_RATE_MCS4, 5515 IWX_TLC_MNG_HT_RATE_MCS5, 5516 IWX_TLC_MNG_HT_RATE_MCS6, 5517 IWX_TLC_MNG_HT_RATE_MCS7, 5518 IWX_TLC_MNG_HT_RATE_MCS8, 5519 IWX_TLC_MNG_HT_RATE_MCS9, 5520 IWX_TLC_MNG_HT_RATE_MCS10, 5521 IWX_TLC_MNG_HT_RATE_MCS11, 5522 IWX_TLC_MNG_HT_RATE_MAX = IWX_TLC_MNG_HT_RATE_MCS11, 5523 }; 5524 5525 #define IWX_TLC_NSS_1 0 5526 #define IWX_TLC_NSS_2 1 5527 #define IWX_TLC_NSS_MAX 2 5528 5529 5530 /** 5531 * IWX_TLC_MCS_PER_BW - mcs index per BW 5532 * @IWX_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz 5533 * @IWX_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz 5534 * @IWX_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz 5535 * @IWX_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3 5536 * @IWX_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4 5537 */ 5538 #define IWX_TLC_MCS_PER_BW_80 0 5539 #define IWX_TLC_MCS_PER_BW_160 1 5540 #define IWX_TLC_MCS_PER_BW_320 2 5541 #define IWX_TLC_MCS_PER_BW_NUM_V3 (IWX_TLC_MCS_PER_BW_160 + 1) 5542 #define IWX_TLC_MCS_PER_BW_NUM_V4 (IWX_TLC_MCS_PER_BW_320 + 1) 5543 5544 /** 5545 * struct iwx_tlc_config_cmd_v3 - TLC configuration version 3 5546 * @sta_id: station id 5547 * @reserved1: reserved 5548 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw 5549 * @mode: &enum iwx_tlc_mng_cfg_mode 5550 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK 5551 * @amsdu: 1 = TX amsdu is supported, 0 = not supported 5552 * @flags: bitmask of IWX_TLC_MNG_CFG_* 5553 * @non_ht_rates: bitmap of supported legacy rates 5554 * @ht_rates: MCS index 0 - 11, per <nss, channel-width> 5555 * pair (0 - 80mhz width and below, 1 - 160mhz). 5556 * @max_mpdu_len: max MPDU length, in bytes 5557 * @sgi_ch_width_supp: bitmap of SGI support per channel width 5558 * use (1 << IWX_TLC_MNG_CFG_CW_*) 5559 * @reserved2: reserved 5560 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 5561 * set zero for no limit. 5562 */ 5563 struct iwx_tlc_config_cmd_v3 { 5564 uint8_t sta_id; 5565 uint8_t reserved1[3]; 5566 uint8_t max_ch_width; 5567 uint8_t mode; 5568 uint8_t chains; 5569 uint8_t amsdu; 5570 uint16_t flags; 5571 uint16_t non_ht_rates; 5572 uint16_t ht_rates[IWX_TLC_NSS_MAX][IWX_TLC_MCS_PER_BW_NUM_V3]; 5573 uint16_t max_mpdu_len; 5574 uint8_t sgi_ch_width_supp; 5575 uint8_t reserved2; 5576 uint32_t max_tx_op; 5577 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */ 5578 5579 /** 5580 * struct iwx_tlc_config_cmd_v4 - TLC configuration 5581 * @sta_id: station id 5582 * @reserved1: reserved 5583 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw 5584 * @mode: &enum iwx_tlc_mng_cfg_mode 5585 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK 5586 * @sgi_ch_width_supp: bitmap of SGI support per channel width 5587 * use (1 << IWX_TLC_MNG_CFG_CW_*) 5588 * @flags: bitmask of IWX_TLC_MNG_CFG_* 5589 * @non_ht_rates: bitmap of supported legacy rates 5590 * @ht_rates: MCS index 0 - 11, per <nss, channel-width> 5591 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz). 5592 * @max_mpdu_len: max MPDU length, in bytes 5593 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI), 5594 * set zero for no limit. 5595 */ 5596 struct iwx_tlc_config_cmd_v4 { 5597 uint8_t sta_id; 5598 uint8_t reserved1[3]; 5599 uint8_t max_ch_width; 5600 uint8_t mode; 5601 uint8_t chains; 5602 uint8_t sgi_ch_width_supp; 5603 uint16_t flags; 5604 uint16_t non_ht_rates; 5605 uint16_t ht_rates[IWX_TLC_NSS_MAX][IWX_TLC_MCS_PER_BW_NUM_V4]; 5606 uint16_t max_mpdu_len; 5607 uint16_t max_tx_op; 5608 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */ 5609 5610 /** 5611 * @IWX_TLC_NOTIF_FLAG_RATE: last initial rate update 5612 * @IWX_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update 5613 */ 5614 #define IWX_TLC_NOTIF_FLAG_RATE (1 << 0) 5615 #define IWX_TLC_NOTIF_FLAG_AMSDU (1 << 1) 5616 5617 /** 5618 * struct iwx_tlc_update_notif - TLC notification from FW 5619 * @sta_id: station id 5620 * @reserved: reserved 5621 * @flags: bitmap of notifications reported 5622 * @rate: current initial rate; using rate_n_flags version 1 if notification 5623 * version is < 3 at run-time, else rate_n_flags version 2 5624 * @amsdu_size: Max AMSDU size, in bytes 5625 * @amsdu_enabled: bitmap for per-TID AMSDU enablement 5626 */ 5627 struct iwx_tlc_update_notif { 5628 uint8_t sta_id; 5629 uint8_t reserved[3]; 5630 uint32_t flags; 5631 uint32_t rate; 5632 uint32_t amsdu_size; 5633 uint32_t amsdu_enabled; 5634 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */ 5635 5636 /* Antenna flags. */ 5637 #define IWX_ANT_A (1 << 0) 5638 #define IWX_ANT_B (1 << 1) 5639 #define IWX_ANT_C (1 << 2) 5640 /* Shortcuts. */ 5641 #define IWX_ANT_AB (IWX_ANT_A | IWX_ANT_B) 5642 #define IWX_ANT_BC (IWX_ANT_B | IWX_ANT_C) 5643 #define IWX_ANT_ABC (IWX_ANT_A | IWX_ANT_B | IWX_ANT_C) 5644 5645 /* 5646 * TX command security control 5647 */ 5648 #define IWX_TX_CMD_SEC_WEP 0x01 5649 #define IWX_TX_CMD_SEC_CCM 0x02 5650 #define IWX_TX_CMD_SEC_TKIP 0x03 5651 #define IWX_TX_CMD_SEC_EXT 0x04 5652 #define IWX_TX_CMD_SEC_MSK 0x07 5653 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_POS 6 5654 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 5655 #define IWX_TX_CMD_SEC_KEY128 0x08 5656 5657 /* TODO: how does these values are OK with only 16 bit variable??? */ 5658 /* 5659 * TX command next frame info 5660 * 5661 * bits 0:2 - security control (IWX_TX_CMD_SEC_*) 5662 * bit 3 - immediate ACK required 5663 * bit 4 - rate is taken from STA table 5664 * bit 5 - frame belongs to BA stream 5665 * bit 6 - immediate BA response expected 5666 * bit 7 - unused 5667 * bits 8:15 - Station ID 5668 * bits 16:31 - rate 5669 */ 5670 #define IWX_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 5671 #define IWX_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 5672 #define IWX_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 5673 #define IWX_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 5674 #define IWX_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 5675 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 5676 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 5677 #define IWX_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 5678 #define IWX_TX_CMD_NEXT_FRAME_RATE_POS (16) 5679 5680 /* 5681 * TX command Frame life time in us - to be written in pm_frame_timeout 5682 */ 5683 #define IWX_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 5684 #define IWX_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 5685 #define IWX_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 5686 #define IWX_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 5687 5688 /* 5689 * TID for non QoS frames - to be written in tid_tspec 5690 */ 5691 #define IWX_TID_NON_QOS 0 5692 5693 /* 5694 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 5695 */ 5696 #define IWX_DEFAULT_TX_RETRY 15 5697 #define IWX_MGMT_DFAULT_RETRY_LIMIT 3 5698 #define IWX_RTS_DFAULT_RETRY_LIMIT 3 5699 #define IWX_BAR_DFAULT_RETRY_LIMIT 60 5700 #define IWX_LOW_RETRY_LIMIT 7 5701 5702 /* 5703 * The FH will write back to the first TB only, so we need to copy some data 5704 * into the buffer regardless of whether it should be mapped or not. 5705 * This indicates how big the first TB must be to include the scratch buffer 5706 * and the assigned PN. 5707 * Since PN location is 8 bytes at offset 12, it's 20 now. 5708 * If we make it bigger then allocations will be bigger and copy slower, so 5709 * that's probably not useful. 5710 */ 5711 #define IWX_FIRST_TB_SIZE 20 5712 #define IWX_FIRST_TB_SIZE_ALIGN ((IWX_FIRST_TB_SIZE + (64 - 1)) & ~(64 - 1)) 5713 5714 /** 5715 * %iwx_tx_cmd offload_assist values 5716 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words) 5717 * from mac header end. For normal case it is 4 words for SNAP. 5718 * note: tx_cmd, mac header and pad are not counted in the offset. 5719 * This is used to help the offload in case there is tunneling such as 5720 * IPv6 in IPv4, in such case the ip header offset should point to the 5721 * inner ip header and IPv4 checksum of the external header should be 5722 * calculated by driver. 5723 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum 5724 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum 5725 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV 5726 * field. Doesn't include the pad. 5727 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for 5728 * alignment 5729 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU 5730 */ 5731 #define IWX_TX_CMD_OFFLD_IP_HDR(x) ((x) << 0) 5732 #define IWX_TX_CMD_OFFLD_L4_EN (1 << 6) 5733 #define IWX_TX_CMD_OFFLD_L3_EN (1 << 7) 5734 #define IWX_TX_CMD_OFFLD_MH_SIZE(x) ((x) << 8) 5735 #define IWX_TX_CMD_OFFLD_PAD (1 << 13) 5736 #define IWX_TX_CMD_OFFLD_AMSDU (1 << 14) 5737 #define IWX_TX_CMD_OFFLD_MH_MASK 0x1f 5738 #define IWX_TX_CMD_OFFLD_IP_HDR_MASK 0x3f 5739 5740 struct iwx_dram_sec_info { 5741 uint32_t pn_low; 5742 uint16_t pn_high; 5743 uint16_t aux_info; 5744 } __packed; /* DRAM_SEC_INFO_API_S_VER_1 */ 5745 5746 /** 5747 * bitmasks for tx_flags in TX command for 22000 5748 * @IWX_TX_FLAGS_CMD_RATE: use rate from the TX command 5749 * @IWX_TX_FLAGS_ENCRYPT_DIS: frame should not be encrypted, even if it belongs 5750 * to a secured STA 5751 * @IWX_TX_FLAGS_HIGH_PRI: high priority frame (like EAPOL) - can affect rate 5752 * selection, retry limits and BT kill 5753 */ 5754 /* Valid for TX_FLAGS_BITS_API_S_VER_3: */ 5755 #define IWX_TX_FLAGS_CMD_RATE (1 << 0) 5756 #define IWX_TX_FLAGS_ENCRYPT_DIS (1 << 1) 5757 #define IWX_TX_FLAGS_HIGH_PRI (1 << 2) 5758 /* Valid for TX_FLAGS_BITS_API_S_VER_4 and above: */ 5759 #define IWX_TX_FLAGS_RTS (1 << 3) 5760 #define IWX_TX_FLAGS_CTS (1 << 4) 5761 /* TX_FLAGS_BITS_API_S_VER_4 */ 5762 5763 /** 5764 * struct iwx_tx_cmd_gen2 - TX command struct to FW for 22000 devices 5765 * ( TX_CMD = 0x1c ) 5766 * @len: in bytes of the payload, see below for details 5767 * @offload_assist: TX offload configuration 5768 * @flags: combination of TX_FLAGS_* 5769 * @dram_info: FW internal DRAM storage 5770 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5771 * cleared. Combination of RATE_MCS_* 5772 * @hdr: 802.11 header 5773 */ 5774 struct iwx_tx_cmd_gen2 { 5775 uint16_t len; 5776 uint16_t offload_assist; 5777 uint32_t flags; 5778 struct iwx_dram_sec_info dram_info; 5779 uint32_t rate_n_flags; 5780 struct ieee80211_frame hdr[0]; 5781 } __packed; /* TX_CMD_API_S_VER_7, 5782 TX_CMD_API_S_VER_9 */ 5783 5784 /** 5785 * struct iwx_tx_cmd_gen3 - TX command struct to FW for AX210+ devices 5786 * ( TX_CMD = 0x1c ) 5787 * @len: in bytes of the payload, see below for details 5788 * @flags: combination of TX_FLAGS_* 5789 * @offload_assist: TX offload configuration 5790 * @dram_info: FW internal DRAM storage 5791 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5792 * cleared. Combination of RATE_MCS_* 5793 * @reserved: reserved 5794 * @hdr: 802.11 header 5795 */ 5796 struct iwx_tx_cmd_gen3 { 5797 uint16_t len; 5798 uint16_t flags; 5799 uint32_t offload_assist; 5800 struct iwx_dram_sec_info dram_info; 5801 uint32_t rate_n_flags; 5802 uint8_t reserved[8]; 5803 struct ieee80211_frame hdr[]; 5804 } __packed; /* TX_CMD_API_S_VER_8, 5805 TX_CMD_API_S_VER_10 */ 5806 5807 /* 5808 * TX response related data 5809 */ 5810 5811 /* 5812 * status that is returned by the fw after attempts to Tx 5813 * @IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 5814 * STA table 5815 * Valid only if frame_count =1 5816 */ 5817 #define IWX_TX_STATUS_MSK 0x000000ff 5818 #define IWX_TX_STATUS_SUCCESS 0x01 5819 #define IWX_TX_STATUS_DIRECT_DONE 0x02 5820 /* postpone TX */ 5821 #define IWX_TX_STATUS_POSTPONE_DELAY 0x40 5822 #define IWX_TX_STATUS_POSTPONE_FEW_BYTES 0x41 5823 #define IWX_TX_STATUS_POSTPONE_BT_PRIO 0x42 5824 #define IWX_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 5825 #define IWX_TX_STATUS_POSTPONE_CALC_TTAK 0x44 5826 /* abort TX */ 5827 #define IWX_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 5828 #define IWX_TX_STATUS_FAIL_SHORT_LIMIT 0x82 5829 #define IWX_TX_STATUS_FAIL_LONG_LIMIT 0x83 5830 #define IWX_TX_STATUS_FAIL_UNDERRUN 0x84 5831 #define IWX_TX_STATUS_FAIL_DRAIN_FLOW 0x85 5832 #define IWX_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 5833 #define IWX_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 5834 #define IWX_TX_STATUS_FAIL_DEST_PS 0x88 5835 #define IWX_TX_STATUS_FAIL_HOST_ABORTED 0x89 5836 #define IWX_TX_STATUS_FAIL_BT_RETRY 0x8a 5837 #define IWX_TX_STATUS_FAIL_STA_INVALID 0x8b 5838 #define IWX_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 5839 #define IWX_TX_STATUS_FAIL_TID_DISABLE 0x8d 5840 #define IWX_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 5841 #define IWX_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f 5842 #define IWX_TX_STATUS_FAIL_FW_DROP 0x90 5843 #define IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91 5844 #define IWX_TX_STATUS_INTERNAL_ABORT 0x92 5845 #define IWX_TX_MODE_MSK 0x00000f00 5846 #define IWX_TX_MODE_NO_BURST 0x00000000 5847 #define IWX_TX_MODE_IN_BURST_SEQ 0x00000100 5848 #define IWX_TX_MODE_FIRST_IN_BURST 0x00000200 5849 #define IWX_TX_QUEUE_NUM_MSK 0x0001f000 5850 #define IWX_TX_NARROW_BW_MSK 0x00060000 5851 #define IWX_TX_NARROW_BW_1DIV2 0x00020000 5852 #define IWX_TX_NARROW_BW_1DIV4 0x00040000 5853 #define IWX_TX_NARROW_BW_1DIV8 0x00060000 5854 5855 /* 5856 * TX aggregation status 5857 * @IWX_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 5858 * occur if tx failed for this frame when it was a member of a previous 5859 * aggregation block). If rate scaling is used, retry count indicates the 5860 * rate table entry used for all frames in the new agg. 5861 * @IWX_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 5862 * this frame 5863 */ 5864 #define IWX_AGG_TX_STATE_STATUS_MSK 0x0fff 5865 #define IWX_AGG_TX_STATE_TRANSMITTED 0x0000 5866 #define IWX_AGG_TX_STATE_UNDERRUN 0x0001 5867 #define IWX_AGG_TX_STATE_BT_PRIO 0x0002 5868 #define IWX_AGG_TX_STATE_FEW_BYTES 0x0004 5869 #define IWX_AGG_TX_STATE_ABORT 0x0008 5870 #define IWX_AGG_TX_STATE_LAST_SENT_TTL 0x0010 5871 #define IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 5872 #define IWX_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 5873 #define IWX_AGG_TX_STATE_SCD_QUERY 0x0080 5874 #define IWX_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 5875 #define IWX_AGG_TX_STATE_RESPONSE 0x01ff 5876 #define IWX_AGG_TX_STATE_DUMP_TX 0x0200 5877 #define IWX_AGG_TX_STATE_DELAY_TX 0x0400 5878 #define IWX_AGG_TX_STATE_TRY_CNT_POS 12 5879 #define IWX_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWX_AGG_TX_STATE_TRY_CNT_POS) 5880 5881 #define IWX_AGG_TX_STATE_LAST_SENT_MSK (IWX_AGG_TX_STATE_LAST_SENT_TTL| \ 5882 IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 5883 IWX_AGG_TX_STATE_LAST_SENT_BT_KILL) 5884 5885 /* 5886 * The mask below describes a status where we are absolutely sure that the MPDU 5887 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 5888 * written the bytes to the TXE, but we know nothing about what the DSP did. 5889 */ 5890 #define IWX_AGG_TX_STAT_FRAME_NOT_SENT (IWX_AGG_TX_STATE_FEW_BYTES | \ 5891 IWX_AGG_TX_STATE_ABORT | \ 5892 IWX_AGG_TX_STATE_SCD_QUERY) 5893 5894 /* 5895 * IWX_REPLY_TX = 0x1c (response) 5896 * 5897 * This response may be in one of two slightly different formats, indicated 5898 * by the frame_count field: 5899 * 5900 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 5901 * frame. Multiple attempts, at various bit rates, may have been made for 5902 * this frame. 5903 * 5904 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 5905 * frames that used block-acknowledge. All frames were transmitted at 5906 * same rate. Rate scaling may have been used if first frame in this new 5907 * agg block failed in previous agg block(s). 5908 * 5909 * Note that, for aggregation, ACK (block-ack) status is not delivered 5910 * here; block-ack has not been received by the time the device records 5911 * this status. 5912 * This status relates to reasons the tx might have been blocked or aborted 5913 * within the device, rather than whether it was received successfully by 5914 * the destination station. 5915 */ 5916 5917 /** 5918 * struct iwx_agg_tx_status - per packet TX aggregation status 5919 * @status: enum iwx_tx_agg_status 5920 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 5921 */ 5922 struct iwx_agg_tx_status { 5923 uint16_t status; 5924 uint16_t sequence; 5925 } __packed; 5926 5927 /* 5928 * definitions for initial rate index field 5929 * bits [3:0] initial rate index 5930 * bits [6:4] rate table color, used for the initial rate 5931 * bit-7 invalid rate indication 5932 */ 5933 #define IWX_TX_RES_INIT_RATE_INDEX_MSK 0x0f 5934 #define IWX_TX_RES_RATE_TABLE_COLOR_MSK 0x70 5935 #define IWX_TX_RES_INV_RATE_INDEX_MSK 0x80 5936 5937 #define IWX_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 5938 #define IWX_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 5939 5940 /** 5941 * struct iwx_tx_resp_v3 - notifies that fw is TXing a packet 5942 * ( IWX_REPLY_TX = 0x1c ) 5943 * @frame_count: 1 no aggregation, >1 aggregation 5944 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 5945 * @failure_rts: num of failures due to unsuccessful RTS 5946 * @failure_frame: num failures due to no ACK (unused for agg) 5947 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 5948 * Tx of all the batch. IWX_RATE_MCS_* 5949 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 5950 * for agg: RTS + CTS + aggregation tx time + block-ack time. 5951 * in usec. 5952 * @pa_status: tx power info 5953 * @pa_integ_res_a: tx power info 5954 * @pa_integ_res_b: tx power info 5955 * @pa_integ_res_c: tx power info 5956 * @measurement_req_id: tx power info 5957 * @tfd_info: TFD information set by the FH 5958 * @seq_ctl: sequence control from the Tx cmd 5959 * @byte_cnt: byte count from the Tx cmd 5960 * @tlc_info: TLC rate info 5961 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 5962 * @frame_ctrl: frame control 5963 * @status: for non-agg: frame status IWX_TX_STATUS_* 5964 * for agg: status of 1st frame, IWX_AGG_TX_STATE_*; other frame status fields 5965 * follow this one, up to frame_count. 5966 * 5967 * After the array of statuses comes the SSN of the SCD. Look at 5968 * %iwx_get_scd_ssn for more details. 5969 */ 5970 struct iwx_tx_resp_v3 { 5971 uint8_t frame_count; 5972 uint8_t bt_kill_count; 5973 uint8_t failure_rts; 5974 uint8_t failure_frame; 5975 uint32_t initial_rate; 5976 uint16_t wireless_media_time; 5977 5978 uint8_t pa_status; 5979 uint8_t pa_integ_res_a[3]; 5980 uint8_t pa_integ_res_b[3]; 5981 uint8_t pa_integ_res_c[3]; 5982 uint16_t measurement_req_id; 5983 uint16_t reserved; 5984 5985 uint32_t tfd_info; 5986 uint16_t seq_ctl; 5987 uint16_t byte_cnt; 5988 uint8_t tlc_info; 5989 uint8_t ra_tid; 5990 uint16_t frame_ctrl; 5991 5992 struct iwx_agg_tx_status status; 5993 } __packed; /* IWX_TX_RSP_API_S_VER_3 */ 5994 5995 /** 5996 * struct iwx_tx_resp - notifies that fw is TXing a packet 5997 * ( REPLY_TX = 0x1c ) 5998 * @frame_count: 1 no aggregation, >1 aggregation 5999 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 6000 * @failure_rts: num of failures due to unsuccessful RTS 6001 * @failure_frame: num failures due to no ACK (unused for agg) 6002 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 6003 * Tx of all the batch. RATE_MCS_* 6004 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 6005 * for agg: RTS + CTS + aggregation tx time + block-ack time. 6006 * in usec. 6007 * @pa_status: tx power info 6008 * @pa_integ_res_a: tx power info 6009 * @pa_integ_res_b: tx power info 6010 * @pa_integ_res_c: tx power info 6011 * @measurement_req_id: tx power info 6012 * @reduced_tpc: transmit power reduction used 6013 * @reserved: reserved 6014 * @tfd_info: TFD information set by the FH 6015 * @seq_ctl: sequence control from the Tx cmd 6016 * @byte_cnt: byte count from the Tx cmd 6017 * @tlc_info: TLC rate info 6018 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 6019 * @frame_ctrl: frame control 6020 * @tx_queue: TX queue for this response 6021 * @reserved2: reserved for padding/alignment 6022 * @status: for non-agg: frame status TX_STATUS_* 6023 * For version 6 TX response isn't received for aggregation at all. 6024 * 6025 * After the array of statuses comes the SSN of the SCD. Look at 6026 * %iwl_mvm_get_scd_ssn for more details. 6027 */ 6028 struct iwx_tx_resp { 6029 uint8_t frame_count; 6030 uint8_t bt_kill_count; 6031 uint8_t failure_rts; 6032 uint8_t failure_frame; 6033 uint32_t initial_rate; 6034 uint16_t wireless_media_time; 6035 6036 uint8_t pa_status; 6037 uint8_t pa_integ_res_a[3]; 6038 uint8_t pa_integ_res_b[3]; 6039 uint8_t pa_integ_res_c[3]; 6040 uint16_t measurement_req_id; 6041 uint8_t reduced_tpc; 6042 uint8_t reserved; 6043 6044 uint32_t tfd_info; 6045 uint16_t seq_ctl; 6046 uint16_t byte_cnt; 6047 uint8_t tlc_info; 6048 uint8_t ra_tid; 6049 uint16_t frame_ctrl; 6050 uint16_t tx_queue; 6051 uint16_t reserved2; 6052 struct iwx_agg_tx_status status; 6053 } __packed; /* TX_RSP_API_S_VER_6 */ 6054 6055 /** 6056 * struct iwx_compressed_ba_tfd - progress of a TFD queue 6057 * @q_num: TFD queue number 6058 * @tfd_index: Index of first un-acked frame in the TFD queue 6059 * @scd_queue: For debug only - the physical queue the TFD queue is bound to 6060 * @tid: TID of the queue (0-7) 6061 * @reserved: reserved for alignment 6062 */ 6063 struct iwx_compressed_ba_tfd { 6064 uint16_t q_num; 6065 uint16_t tfd_index; 6066 uint8_t scd_queue; 6067 uint8_t tid; 6068 uint8_t reserved[2]; 6069 } __packed; /* COMPRESSED_BA_TFD_API_S_VER_1 */ 6070 6071 /** 6072 * struct iwx_compressed_ba_ratid - progress of a RA TID queue 6073 * @q_num: RA TID queue number 6074 * @tid: TID of the queue 6075 * @ssn: BA window current SSN 6076 */ 6077 struct iwx_compressed_ba_ratid { 6078 uint8_t q_num; 6079 uint8_t tid; 6080 uint16_t ssn; 6081 } __packed; /* COMPRESSED_BA_RATID_API_S_VER_1 */ 6082 6083 /* 6084 * enum iwx_ba_resp_flags - TX aggregation status 6085 * @IWX_MVM_BA_RESP_TX_AGG: generated due to BA 6086 * @IWX_MVM_BA_RESP_TX_BAR: generated due to BA after BAR 6087 * @IWX_MVM_BA_RESP_TX_AGG_FAIL: aggregation didn't receive BA 6088 * @IWX_MVM_BA_RESP_TX_UNDERRUN: aggregation got underrun 6089 * @IWX_MVM_BA_RESP_TX_BT_KILL: aggregation got BT-kill 6090 * @IWX_MVM_BA_RESP_TX_DSP_TIMEOUT: aggregation didn't finish within the 6091 * expected time 6092 */ 6093 enum iwx_ba_resp_flags { 6094 IWX_MVM_BA_RESP_TX_AGG, 6095 IWX_MVM_BA_RESP_TX_BAR, 6096 IWX_MVM_BA_RESP_TX_AGG_FAIL, 6097 IWX_MVM_BA_RESP_TX_UNDERRUN, 6098 IWX_MVM_BA_RESP_TX_BT_KILL, 6099 IWX_MVM_BA_RESP_TX_DSP_TIMEOUT 6100 }; 6101 6102 /** 6103 * struct iwx_compressed_ba_notif - notifies about reception of BA 6104 * ( BA_NOTIF = 0xc5 ) 6105 * @flags: status flag, see the &iwx_ba_resp_flags 6106 * @sta_id: Index of recipient (BA-sending) station in fw's station table 6107 * @reduced_txp: power reduced according to TPC. This is the actual value and 6108 * not a copy from the LQ command. Thus, if not the first rate was used 6109 * for Tx-ing then this value will be set to 0 by FW. 6110 * @tlc_rate_info: TLC rate info, initial rate index, TLC table color 6111 * @retry_cnt: retry count 6112 * @query_byte_cnt: SCD query byte count 6113 * @query_frame_cnt: SCD query frame count 6114 * @txed: number of frames sent in the aggregation (all-TIDs) 6115 * @done: number of frames that were Acked by the BA (all-TIDs) 6116 * @reserved: reserved (for alignment) 6117 * @wireless_time: Wireless-media time 6118 * @tx_rate: the rate the aggregation was sent at 6119 * @tfd_cnt: number of TFD-Q elements 6120 * @ra_tid_cnt: number of RATID-Q elements 6121 * @tfd: array of TFD queue status updates. See &iwx_compressed_ba_tfd 6122 * for details. Length in @tfd_cnt. 6123 * @ra_tid: array of RA-TID queue status updates. For debug purposes only. See 6124 * &iwx_compressed_ba_ratid for more details. Length in @ra_tid_cnt. 6125 */ 6126 struct iwx_compressed_ba_notif { 6127 uint32_t flags; 6128 uint8_t sta_id; 6129 uint8_t reduced_txp; 6130 uint8_t tlc_rate_info; 6131 uint8_t retry_cnt; 6132 uint32_t query_byte_cnt; 6133 uint16_t query_frame_cnt; 6134 uint16_t txed; 6135 uint16_t done; 6136 uint16_t reserved; 6137 uint32_t wireless_time; 6138 uint32_t tx_rate; 6139 uint16_t tfd_cnt; 6140 uint16_t ra_tid_cnt; 6141 struct iwx_compressed_ba_ratid ra_tid[0]; 6142 struct iwx_compressed_ba_tfd tfd[]; 6143 } __packed; /* COMPRESSED_BA_RES_API_S_VER_4 */ 6144 6145 6146 struct iwx_beacon_notif { 6147 struct iwx_tx_resp_v3 beacon_notify_hdr; 6148 uint64_t tsf; 6149 uint32_t ibss_mgr_status; 6150 } __packed; 6151 6152 /** 6153 * dump (flush) control flags 6154 * @IWX_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 6155 * and the TFD queues are empty. 6156 */ 6157 #define IWX_DUMP_TX_FIFO_FLUSH (1 << 1) 6158 6159 /** 6160 * struct iwx_tx_path_flush_cmd -- queue/FIFO flush command 6161 * @queues_ctl: bitmap of queues to flush 6162 * @flush_ctl: control flags 6163 * @reserved: reserved 6164 */ 6165 struct iwx_tx_path_flush_cmd_v1 { 6166 uint32_t queues_ctl; 6167 uint16_t flush_ctl; 6168 uint16_t reserved; 6169 } __packed; /* IWX_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 6170 6171 /** 6172 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command 6173 * @sta_id: station ID to flush 6174 * @tid_mask: TID mask to flush 6175 * @reserved: reserved 6176 */ 6177 struct iwx_tx_path_flush_cmd { 6178 uint32_t sta_id; 6179 uint16_t tid_mask; 6180 uint16_t reserved; 6181 } __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */ 6182 6183 #define IWX_TX_FLUSH_QUEUE_RSP 16 6184 6185 /** 6186 * struct iwx_flush_queue_info - virtual flush queue info 6187 * @queue_num: virtual queue id 6188 * @read_before_flush: read pointer before flush 6189 * @read_after_flush: read pointer after flush 6190 */ 6191 struct iwx_flush_queue_info { 6192 uint16_t tid; 6193 uint16_t queue_num; 6194 uint16_t read_before_flush; 6195 uint16_t read_after_flush; 6196 } __packed; /* TFDQ_FLUSH_INFO_API_S_VER_1 */ 6197 6198 /** 6199 * struct iwx_tx_path_flush_cmd_rsp -- queue/FIFO flush command response 6200 * @num_flushed_queues: number of queues in queues array 6201 * @queues: all flushed queues 6202 */ 6203 struct iwx_tx_path_flush_cmd_rsp { 6204 uint16_t sta_id; 6205 uint16_t num_flushed_queues; 6206 struct iwx_flush_queue_info queues[IWX_TX_FLUSH_QUEUE_RSP]; 6207 } __packed; /* TX_PATH_FLUSH_CMD_RSP_API_S_VER_1 */ 6208 6209 6210 /** 6211 * iwx_get_scd_ssn - returns the SSN of the SCD 6212 * @tx_resp: the Tx response from the fw (agg or non-agg) 6213 * 6214 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 6215 * it can't know that everything will go well until the end of the AMPDU, it 6216 * can't know in advance the number of MPDUs that will be sent in the current 6217 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 6218 * Hence, it can't know in advance what the SSN of the SCD will be at the end 6219 * of the batch. This is why the SSN of the SCD is written at the end of the 6220 * whole struct at a variable offset. This function knows how to cope with the 6221 * variable offset and returns the SSN of the SCD. 6222 */ 6223 static inline uint32_t iwx_get_scd_ssn(struct iwx_tx_resp *tx_resp) 6224 { 6225 return le32_to_cpup((uint32_t *)&tx_resp->status + 6226 tx_resp->frame_count) & 0xfff; 6227 } 6228 6229 /** 6230 * struct iwx_scd_txq_cfg_cmd - New txq hw scheduler config command 6231 * @token: 6232 * @sta_id: station id 6233 * @tid: 6234 * @scd_queue: scheduler queue to config 6235 * @enable: 1 queue enable, 0 queue disable 6236 * @aggregate: 1 aggregated queue, 0 otherwise 6237 * @tx_fifo: %enum iwx_tx_fifo 6238 * @window: BA window size 6239 * @ssn: SSN for the BA agreement 6240 */ 6241 struct iwx_scd_txq_cfg_cmd { 6242 uint8_t token; 6243 uint8_t sta_id; 6244 uint8_t tid; 6245 uint8_t scd_queue; 6246 uint8_t enable; 6247 uint8_t aggregate; 6248 uint8_t tx_fifo; 6249 uint8_t window; 6250 uint16_t ssn; 6251 uint16_t reserved; 6252 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 6253 6254 /** 6255 * struct iwx_scd_txq_cfg_rsp 6256 * @token: taken from the command 6257 * @sta_id: station id from the command 6258 * @tid: tid from the command 6259 * @scd_queue: scd_queue from the command 6260 */ 6261 struct iwx_scd_txq_cfg_rsp { 6262 uint8_t token; 6263 uint8_t sta_id; 6264 uint8_t tid; 6265 uint8_t scd_queue; 6266 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 6267 6268 6269 /* Scan Commands, Responses, Notifications */ 6270 6271 /* Max number of IEs for direct SSID scans in a command */ 6272 #define IWX_PROBE_OPTION_MAX 20 6273 6274 /** 6275 * struct iwx_ssid_ie - directed scan network information element 6276 * 6277 * Up to 20 of these may appear in IWX_REPLY_SCAN_CMD, 6278 * selected by "type" bit field in struct iwx_scan_channel; 6279 * each channel may select different ssids from among the 20 entries. 6280 * SSID IEs get transmitted in reverse order of entry. 6281 */ 6282 struct iwx_ssid_ie { 6283 uint8_t id; 6284 uint8_t len; 6285 uint8_t ssid[IEEE80211_NWID_LEN]; 6286 } __packed; /* IWX_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 6287 6288 /* scan offload */ 6289 #define IWX_SCAN_MAX_BLACKLIST_LEN 64 6290 #define IWX_SCAN_SHORT_BLACKLIST_LEN 16 6291 #define IWX_SCAN_MAX_PROFILES 11 6292 #define IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 6293 6294 /* Default watchdog (in MS) for scheduled scan iteration */ 6295 #define IWX_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 6296 6297 #define IWX_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 6298 #define IWX_CAN_ABORT_STATUS 1 6299 6300 #define IWX_FULL_SCAN_MULTIPLIER 5 6301 #define IWX_FAST_SCHED_SCAN_ITERATIONS 3 6302 #define IWX_MAX_SCHED_SCAN_PLANS 2 6303 6304 /** 6305 * iwx_scan_schedule_lmac - schedule of scan offload 6306 * @delay: delay between iterations, in seconds. 6307 * @iterations: num of scan iterations 6308 * @full_scan_mul: number of partial scans before each full scan 6309 */ 6310 struct iwx_scan_schedule_lmac { 6311 uint16_t delay; 6312 uint8_t iterations; 6313 uint8_t full_scan_mul; 6314 } __packed; /* SCAN_SCHEDULE_API_S */ 6315 6316 /** 6317 * iwx_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 6318 * @tx_flags: combination of TX_CMD_FLG_* 6319 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 6320 * cleared. Combination of RATE_MCS_* 6321 * @sta_id: index of destination station in FW station table 6322 * @reserved: for alignment and future use 6323 */ 6324 struct iwx_scan_req_tx_cmd { 6325 uint32_t tx_flags; 6326 uint32_t rate_n_flags; 6327 uint8_t sta_id; 6328 uint8_t reserved[3]; 6329 } __packed; 6330 6331 #define IWX_UNIFIED_SCAN_CHANNEL_FULL (1 << 27) 6332 #define IWX_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28) 6333 6334 /** 6335 * iwx_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 6336 * @flags: bits 1-20: directed scan to i'th ssid 6337 * other bits &enum iwx_scan_channel_flags_lmac 6338 * @channel_number: channel number 1-13 etc 6339 * @iter_count: scan iteration on this channel 6340 * @iter_interval: interval in seconds between iterations on one channel 6341 */ 6342 struct iwx_scan_channel_cfg_lmac { 6343 uint32_t flags; 6344 uint16_t channel_num; 6345 uint16_t iter_count; 6346 uint32_t iter_interval; 6347 } __packed; 6348 6349 /* 6350 * iwx_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 6351 * @offset: offset in the data block 6352 * @len: length of the segment 6353 */ 6354 struct iwx_scan_probe_segment { 6355 uint16_t offset; 6356 uint16_t len; 6357 } __packed; 6358 6359 /* iwx_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 6360 * @mac_header: first (and common) part of the probe 6361 * @band_data: band specific data 6362 * @common_data: last (and common) part of the probe 6363 * @buf: raw data block 6364 */ 6365 struct iwx_scan_probe_req_v1 { 6366 struct iwx_scan_probe_segment mac_header; 6367 struct iwx_scan_probe_segment band_data[2]; 6368 struct iwx_scan_probe_segment common_data; 6369 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 6370 } __packed; 6371 6372 /* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2 6373 * @mac_header: first (and common) part of the probe 6374 * @band_data: band specific data 6375 * @common_data: last (and common) part of the probe 6376 * @buf: raw data block 6377 */ 6378 struct iwx_scan_probe_req { 6379 struct iwx_scan_probe_segment mac_header; 6380 struct iwx_scan_probe_segment band_data[3]; 6381 struct iwx_scan_probe_segment common_data; 6382 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 6383 } __packed; 6384 6385 6386 #define IWX_SCAN_CHANNEL_FLAG_EBS (1 << 0) 6387 #define IWX_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1) 6388 #define IWX_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2) 6389 #define IWX_SCAN_CHANNEL_FLAG_EBS_FRAG (1 << 3) 6390 #define IWX_SCAN_CHANNEL_FLAG_FORCE_EBS (1 << 4) 6391 #define IWX_SCAN_CHANNEL_FLAG_ENABLE_CHAN_ORDER (1 << 5) 6392 #define IWX_SCAN_CHANNEL_FLAG_6G_PSC_NO_FILTER (1 << 6) 6393 6394 /* iwx_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 6395 * @flags: enum iwx_scan_channel_flags 6396 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 6397 * involved. 6398 * 1 - EBS is disabled. 6399 * 2 - every second scan will be full scan(and so on). 6400 */ 6401 struct iwx_scan_channel_opt { 6402 uint16_t flags; 6403 uint16_t non_ebs_ratio; 6404 } __packed; 6405 6406 #define IWX_SCAN_PRIORITY_LOW 0 6407 #define IWX_SCAN_PRIORITY_MEDIUM 1 6408 #define IWX_SCAN_PRIORITY_HIGH 2 6409 6410 enum iwx_scan_priority_ext { 6411 IWX_SCAN_PRIORITY_EXT_0_LOWEST, 6412 IWX_SCAN_PRIORITY_EXT_1, 6413 IWX_SCAN_PRIORITY_EXT_2, 6414 IWX_SCAN_PRIORITY_EXT_3, 6415 IWX_SCAN_PRIORITY_EXT_4, 6416 IWX_SCAN_PRIORITY_EXT_5, 6417 IWX_SCAN_PRIORITY_EXT_6, 6418 IWX_SCAN_PRIORITY_EXT_7_HIGHEST, 6419 }; 6420 6421 /** 6422 * iwx_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 6423 * @last_schedule_line: last schedule line executed (fast or regular) 6424 * @last_schedule_iteration: last scan iteration executed before scan abort 6425 * @status: enum iwx_scan_offload_complete_status 6426 * @ebs_status: EBS success status &enum iwx_scan_ebs_status 6427 * @time_after_last_iter; time in seconds elapsed after last iteration 6428 */ 6429 struct iwx_periodic_scan_complete { 6430 uint8_t last_schedule_line; 6431 uint8_t last_schedule_iteration; 6432 uint8_t status; 6433 uint8_t ebs_status; 6434 uint32_t time_after_last_iter; 6435 uint32_t reserved; 6436 } __packed; 6437 6438 /** 6439 * struct iwx_scan_results_notif - scan results for one channel - 6440 * SCAN_RESULT_NTF_API_S_VER_3 6441 * @channel: which channel the results are from 6442 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 6443 * @probe_status: IWX_SCAN_PROBE_STATUS_*, indicates success of probe request 6444 * @num_probe_not_sent: # of request that weren't sent due to not enough time 6445 * @duration: duration spent in channel, in usecs 6446 */ 6447 struct iwx_scan_results_notif { 6448 uint8_t channel; 6449 uint8_t band; 6450 uint8_t probe_status; 6451 uint8_t num_probe_not_sent; 6452 uint32_t duration; 6453 } __packed; 6454 6455 #define IWX_SCAN_CLIENT_SCHED_SCAN (1 << 0) 6456 #define IWX_SCAN_CLIENT_NETDETECT (1 << 1) 6457 #define IWX_SCAN_CLIENT_ASSET_TRACKING (1 << 2) 6458 6459 /** 6460 * iwx_scan_offload_blacklist - IWX_SCAN_OFFLOAD_BLACKLIST_S 6461 * @ssid: MAC address to filter out 6462 * @reported_rssi: AP rssi reported to the host 6463 * @client_bitmap: clients ignore this entry - enum scan_framework_client 6464 */ 6465 struct iwx_scan_offload_blacklist { 6466 uint8_t ssid[ETHER_ADDR_LEN]; 6467 uint8_t reported_rssi; 6468 uint8_t client_bitmap; 6469 } __packed; 6470 6471 #define IWX_NETWORK_TYPE_BSS 1 6472 #define IWX_NETWORK_TYPE_IBSS 2 6473 #define IWX_NETWORK_TYPE_ANY 3 6474 6475 #define IWX_SCAN_OFFLOAD_SELECT_2_4 0x4 6476 #define IWX_SCAN_OFFLOAD_SELECT_5_2 0x8 6477 #define IWX_SCAN_OFFLOAD_SELECT_ANY 0xc 6478 6479 /** 6480 * iwx_scan_offload_profile - IWX_SCAN_OFFLOAD_PROFILE_S 6481 * @ssid_index: index to ssid list in fixed part 6482 * @unicast_cipher: encryption algorithm to match - bitmap 6483 * @aut_alg: authentication algorithm to match - bitmap 6484 * @network_type: enum iwx_scan_offload_network_type 6485 * @band_selection: enum iwx_scan_offload_band_selection 6486 * @client_bitmap: clients waiting for match - enum scan_framework_client 6487 */ 6488 struct iwx_scan_offload_profile { 6489 uint8_t ssid_index; 6490 uint8_t unicast_cipher; 6491 uint8_t auth_alg; 6492 uint8_t network_type; 6493 uint8_t band_selection; 6494 uint8_t client_bitmap; 6495 uint8_t reserved[2]; 6496 } __packed; 6497 6498 /** 6499 * iwx_scan_offload_profile_cfg - IWX_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 6500 * @blacklist: AP list to filter off from scan results 6501 * @profiles: profiles to search for match 6502 * @blacklist_len: length of blacklist 6503 * @num_profiles: num of profiles in the list 6504 * @match_notify: clients waiting for match found notification 6505 * @pass_match: clients waiting for the results 6506 * @active_clients: active clients bitmap - enum scan_framework_client 6507 * @any_beacon_notify: clients waiting for match notification without match 6508 */ 6509 struct iwx_scan_offload_profile_cfg { 6510 struct iwx_scan_offload_profile profiles[IWX_SCAN_MAX_PROFILES]; 6511 uint8_t blacklist_len; 6512 uint8_t num_profiles; 6513 uint8_t match_notify; 6514 uint8_t pass_match; 6515 uint8_t active_clients; 6516 uint8_t any_beacon_notify; 6517 uint8_t reserved[2]; 6518 } __packed; 6519 6520 #define IWX_SCAN_OFFLOAD_COMPLETED 1 6521 #define IWX_SCAN_OFFLOAD_ABORTED 2 6522 6523 /* UMAC Scan API */ 6524 6525 #define IWX_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0) 6526 #define IWX_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1) 6527 #define IWX_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2) 6528 #define IWX_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3) 6529 #define IWX_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8) 6530 #define IWX_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9) 6531 #define IWX_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10) 6532 #define IWX_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11) 6533 #define IWX_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12) 6534 #define IWX_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13) 6535 #define IWX_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14) 6536 #define IWX_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15) 6537 #define IWX_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16) 6538 #define IWX_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17) 6539 #define IWX_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18) 6540 #define IWX_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19) 6541 #define IWX_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20) 6542 #define IWX_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21) 6543 6544 /* Bits 26-31 are for num of channels in channel_array */ 6545 #define IWX_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 6546 6547 /* OFDM basic rates */ 6548 #define IWX_SCAN_CONFIG_RATE_6M (1 << 0) 6549 #define IWX_SCAN_CONFIG_RATE_9M (1 << 1) 6550 #define IWX_SCAN_CONFIG_RATE_12M (1 << 2) 6551 #define IWX_SCAN_CONFIG_RATE_18M (1 << 3) 6552 #define IWX_SCAN_CONFIG_RATE_24M (1 << 4) 6553 #define IWX_SCAN_CONFIG_RATE_36M (1 << 5) 6554 #define IWX_SCAN_CONFIG_RATE_48M (1 << 6) 6555 #define IWX_SCAN_CONFIG_RATE_54M (1 << 7) 6556 /* CCK basic rates */ 6557 #define IWX_SCAN_CONFIG_RATE_1M (1 << 8) 6558 #define IWX_SCAN_CONFIG_RATE_2M (1 << 9) 6559 #define IWX_SCAN_CONFIG_RATE_5M (1 << 10) 6560 #define IWX_SCAN_CONFIG_RATE_11M (1 << 11) 6561 6562 /* Bits 16-27 are for supported rates */ 6563 #define IWX_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 6564 6565 #define IWX_CHANNEL_FLAG_EBS (1 << 0) 6566 #define IWX_CHANNEL_FLAG_ACCURATE_EBS (1 << 1) 6567 #define IWX_CHANNEL_FLAG_EBS_ADD (1 << 2) 6568 #define IWX_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3) 6569 6570 /** 6571 * struct iwx_scan_dwell 6572 * @active: default dwell time for active scan 6573 * @passive: default dwell time for passive scan 6574 * @fragmented: default dwell time for fragmented scan 6575 * @extended: default dwell time for channels 1, 6 and 11 6576 */ 6577 struct iwx_scan_dwell { 6578 uint8_t active; 6579 uint8_t passive; 6580 uint8_t fragmented; 6581 uint8_t extended; 6582 } __packed; 6583 6584 6585 #define IWX_SCAN_TWO_LMACS 2 6586 #define IWX_SCAN_LB_LMAC_IDX 0 /* low-band */ 6587 #define IWX_SCAN_HB_LMAC_IDX 1 /* high-band */ 6588 6589 /** 6590 * struct iwl_scan_config 6591 * @enable_cam_mode: whether to enable CAM mode. 6592 * @enable_promiscuous_mode: whether to enable promiscuous mode 6593 * @bcast_sta_id: the index of the station in the fw. Deprecated starting with 6594 * API version 5. 6595 * @reserved: reserved 6596 * @tx_chains: valid_tx antenna - ANT_* definitions 6597 * @rx_chains: valid_rx antenna - ANT_* definitions 6598 */ 6599 struct iwx_scan_config { 6600 uint8_t enable_cam_mode; 6601 uint8_t enable_promiscuous_mode; 6602 uint8_t bcast_sta_id; 6603 uint8_t reserved; 6604 uint32_t tx_chains; 6605 uint32_t rx_chains; 6606 } __packed; /* SCAN_CONFIG_DB_CMD_API_S_5 */ 6607 6608 /** 6609 * struct iwx_scan_config_v2 6610 * @flags: enum scan_config_flags 6611 * @tx_chains: valid_tx antenna - ANT_* definitions 6612 * @rx_chains: valid_rx antenna - ANT_* definitions 6613 * @legacy_rates: default legacy rates - enum scan_config_rates 6614 * @out_of_channel_time: default max out of serving channel time 6615 * @suspend_time: default max suspend time 6616 * @dwell_active: default dwell time for active scan 6617 * @dwell_passive: default dwell time for passive scan 6618 * @dwell_fragmented: default dwell time for fragmented scan 6619 * @dwell_extended: default dwell time for channels 1, 6 and 11 6620 * @mac_addr: default mac address to be used in probes 6621 * @bcast_sta_id: the index of the station in the fw 6622 * @channel_flags: default channel flags - enum iwx_channel_flags 6623 * scan_config_channel_flag 6624 * @channel_array: default supported channels 6625 */ 6626 struct iwx_scan_config_v2 { 6627 uint32_t flags; 6628 uint32_t tx_chains; 6629 uint32_t rx_chains; 6630 uint32_t legacy_rates; 6631 uint32_t out_of_channel_time[IWX_SCAN_TWO_LMACS]; 6632 uint32_t suspend_time[IWX_SCAN_TWO_LMACS]; 6633 struct iwx_scan_dwell dwell; 6634 uint8_t mac_addr[ETHER_ADDR_LEN]; 6635 uint8_t bcast_sta_id; 6636 uint8_t channel_flags; 6637 uint8_t channel_array[]; 6638 } __packed; /* SCAN_CONFIG_DB_CMD_API_S_2 */ 6639 6640 /** 6641 * iwx_umac_scan_flags 6642 *@IWX_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 6643 * can be preempted by other scan requests with higher priority. 6644 * The low priority scan will be resumed when the higher priority scan is 6645 * completed. 6646 *@IWX_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 6647 * when scan starts. 6648 */ 6649 #define IWX_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0) 6650 #define IWX_UMAC_SCAN_FLAG_START_NOTIF (1 << 1) 6651 6652 #define IWX_UMAC_SCAN_UID_TYPE_OFFSET 0 6653 #define IWX_UMAC_SCAN_UID_SEQ_OFFSET 8 6654 6655 #define IWX_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0) 6656 #define IWX_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1) 6657 #define IWX_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2) 6658 #define IWX_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3) 6659 #define IWX_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4) 6660 #define IWX_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5) 6661 #define IWX_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6) 6662 #define IWX_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7) 6663 #define IWX_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8) 6664 #define IWX_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9) 6665 #define IWX_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10) 6666 /* Extended dwell is obsolete when adaptive dwell is used, making this 6667 * bit reusable. Hence, probe request defer is used only when adaptive 6668 * dwell is supported. */ 6669 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10) 6670 #define IWX_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11) 6671 #define IWX_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13) 6672 #define IWX_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14) 6673 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15) 6674 6675 /** 6676 * UMAC scan general flags #2 6677 * @IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete 6678 * notification per channel or not. 6679 * @IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel 6680 * reorder optimization or not. 6681 */ 6682 #define IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0) 6683 #define IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1) 6684 6685 /** 6686 * UMAC scan general flags version 2 6687 * 6688 * The FW flags were reordered and hence the driver introduce version 2 6689 * 6690 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC: periodic or scheduled 6691 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL: pass all probe responses and beacons 6692 * during scan iterations 6693 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE: send complete notification 6694 * on every iteration instead of only once after the last iteration 6695 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1: fragmented scan LMAC1 6696 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2: fragmented scan LMAC2 6697 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH: does this scan check for profile matching 6698 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS: use all valid chains for RX 6699 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL: works with adaptive dwell 6700 * for active channel 6701 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE: can be preempted by other requests 6702 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START: send notification of scan start 6703 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID: matching on multiple SSIDs 6704 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE: all the channels scanned 6705 * as passive 6706 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN: at the end of 2.4GHz and 6707 * 5.2Ghz bands scan, trigger scan on 6GHz band to discover 6708 * the reported collocated APs 6709 */ 6710 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC (1 << 0) 6711 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL (1 << 1) 6712 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE (1 << 2) 6713 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1 (1 << 3) 6714 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2 (1 << 4) 6715 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH (1 << 5) 6716 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS (1 << 6) 6717 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL (1 << 7) 6718 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE (1 << 8) 6719 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START (1 << 9) 6720 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID (1 << 10) 6721 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE (1 << 11) 6722 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN (1 << 12) 6723 6724 /** 6725 * struct iwx_scan_channel_cfg_umac 6726 * @flags: bitmap - 0-19: directed scan to i'th ssid. 6727 * @channel_num: channel number 1-13 etc. 6728 * @iter_count: repetition count for the channel. 6729 * @iter_interval: interval between two scan iterations on one channel. 6730 */ 6731 struct iwx_scan_channel_cfg_umac { 6732 uint32_t flags; 6733 union { 6734 struct { 6735 uint8_t channel_num; 6736 uint8_t iter_count; 6737 uint16_t iter_interval; 6738 } v1; /* SCAN_CHANNEL_CFG_S_VER1 */ 6739 struct { 6740 uint8_t channel_num; 6741 uint8_t band; 6742 uint8_t iter_count; 6743 uint8_t iter_interval; 6744 } v2; /* SCAN_CHANNEL_CFG_S_VER{2,3,4} */ 6745 }; 6746 } __packed; 6747 6748 /** 6749 * struct iwx_scan_umac_schedule 6750 * @interval: interval in seconds between scan iterations 6751 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 6752 * @reserved: for alignment and future use 6753 */ 6754 struct iwx_scan_umac_schedule { 6755 uint16_t interval; 6756 uint8_t iter_count; 6757 uint8_t reserved; 6758 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 6759 6760 /** 6761 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command 6762 * parameters following channels configuration array. 6763 * @schedule: two scheduling plans. 6764 * @delay: delay in TUs before starting the first scan iteration 6765 * @reserved: for future use and alignment 6766 * @preq: probe request with IEs blocks 6767 * @direct_scan: list of SSIDs for directed active scan 6768 */ 6769 struct iwx_scan_req_umac_tail_v1 { 6770 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 6771 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 6772 uint16_t delay; 6773 uint16_t reserved; 6774 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 6775 struct iwx_scan_probe_req_v1 preq; 6776 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 6777 } __packed; 6778 6779 /** 6780 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command 6781 * parameters following channels configuration array. 6782 * @schedule: two scheduling plans. 6783 * @delay: delay in TUs before starting the first scan iteration 6784 * @reserved: for future use and alignment 6785 * @preq: probe request with IEs blocks 6786 * @direct_scan: list of SSIDs for directed active scan 6787 */ 6788 struct iwx_scan_req_umac_tail_v2 { 6789 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 6790 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 6791 uint16_t delay; 6792 uint16_t reserved; 6793 /* SCAN_PROBE_PARAMS_API_S_VER_2 */ 6794 struct iwx_scan_probe_req preq; 6795 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 6796 } __packed; 6797 6798 /** 6799 * struct iwx_scan_umac_chan_param 6800 * @flags: channel flags &enum iwl_scan_channel_flags 6801 * @count: num of channels in scan request 6802 * @reserved: for future use and alignment 6803 */ 6804 struct iwx_scan_umac_chan_param { 6805 uint8_t flags; 6806 uint8_t count; 6807 uint16_t reserved; 6808 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 6809 6810 #define IWX_SCAN_LB_LMAC_IDX 0 6811 #define IWX_SCAN_HB_LMAC_IDX 1 6812 6813 /** 6814 * struct iwx_scan_req_umac 6815 * @flags: &enum iwl_umac_scan_flags 6816 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 6817 * @ooc_priority: out of channel priority - &enum iwl_scan_priority 6818 * @general_flags: &enum iwl_umac_scan_general_flags 6819 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 6820 * @extended_dwell: dwell time for channels 1, 6 and 11 6821 * @active_dwell: dwell time for active scan per LMAC 6822 * @passive_dwell: dwell time for passive scan per LMAC 6823 * @fragmented_dwell: dwell time for fragmented passive scan 6824 * @adwell_default_n_aps: for adaptive dwell the default number of APs 6825 * per channel 6826 * @adwell_default_n_aps_social: for adaptive dwell the default 6827 * number of APs per social (1,6,11) channel 6828 * @general_flags2: &enum iwl_umac_scan_general_flags2 6829 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added 6830 * to total scan time 6831 * @max_out_time: max out of serving channel time, per LMAC - for CDB there 6832 * are 2 LMACs (high band and low band) 6833 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs 6834 * @scan_priority: scan internal prioritization &enum iwl_scan_priority 6835 * @num_of_fragments: Number of fragments needed for full coverage per band. 6836 * Relevant only for fragmented scan. 6837 * @channel: &struct iwx_scan_umac_chan_param 6838 * @reserved: for future use and alignment 6839 * @reserved3: for future use and alignment 6840 * @data: &struct iwx_scan_channel_cfg_umac and 6841 * &struct iwx_scan_req_umac_tail 6842 */ 6843 struct iwx_scan_req_umac { 6844 uint32_t flags; 6845 uint32_t uid; 6846 uint32_t ooc_priority; 6847 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 6848 uint16_t general_flags; 6849 uint8_t reserved; 6850 uint8_t scan_start_mac_id; 6851 union { 6852 struct { 6853 uint8_t extended_dwell; 6854 uint8_t active_dwell; 6855 uint8_t passive_dwell; 6856 uint8_t fragmented_dwell; 6857 uint32_t max_out_time; 6858 uint32_t suspend_time; 6859 uint32_t scan_priority; 6860 struct iwx_scan_umac_chan_param channel; 6861 uint8_t data[]; 6862 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 6863 struct { 6864 uint8_t extended_dwell; 6865 uint8_t active_dwell; 6866 uint8_t passive_dwell; 6867 uint8_t fragmented_dwell; 6868 uint32_t max_out_time[2]; 6869 uint32_t suspend_time[2]; 6870 uint32_t scan_priority; 6871 struct iwx_scan_umac_chan_param channel; 6872 uint8_t data[]; 6873 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */ 6874 struct { 6875 uint8_t active_dwell; 6876 uint8_t passive_dwell; 6877 uint8_t fragmented_dwell; 6878 uint8_t adwell_default_n_aps; 6879 uint8_t adwell_default_n_aps_social; 6880 uint8_t reserved3; 6881 uint16_t adwell_max_budget; 6882 uint32_t max_out_time[2]; 6883 uint32_t suspend_time[2]; 6884 uint32_t scan_priority; 6885 struct iwx_scan_umac_chan_param channel; 6886 uint8_t data[]; 6887 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */ 6888 struct { 6889 uint8_t active_dwell[2]; 6890 uint8_t reserved2; 6891 uint8_t adwell_default_n_aps; 6892 uint8_t adwell_default_n_aps_social; 6893 uint8_t general_flags2; 6894 uint16_t adwell_max_budget; 6895 uint32_t max_out_time[2]; 6896 uint32_t suspend_time[2]; 6897 uint32_t scan_priority; 6898 uint8_t passive_dwell[2]; 6899 uint8_t num_of_fragments[2]; 6900 struct iwx_scan_umac_chan_param channel; 6901 uint8_t data[]; 6902 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */ 6903 struct { 6904 uint8_t active_dwell[2]; 6905 uint8_t adwell_default_hb_n_aps; 6906 uint8_t adwell_default_lb_n_aps; 6907 uint8_t adwell_default_n_aps_social; 6908 uint8_t general_flags2; 6909 uint16_t adwell_max_budget; 6910 uint32_t max_out_time[2]; 6911 uint32_t suspend_time[2]; 6912 uint32_t scan_priority; 6913 uint8_t passive_dwell[2]; 6914 uint8_t num_of_fragments[2]; 6915 struct iwx_scan_umac_chan_param channel; 6916 uint8_t data[]; 6917 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */ 6918 }; 6919 } __packed; 6920 6921 #define IWX_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwx_scan_req_umac) 6922 #define IWX_SCAN_REQ_UMAC_SIZE_V7 48 6923 #define IWX_SCAN_REQ_UMAC_SIZE_V6 44 6924 #define IWX_SCAN_REQ_UMAC_SIZE_V1 36 6925 6926 /** 6927 * struct iwx_scan_general_params_v10 6928 * @flags: &enum iwx_umac_scan_flags 6929 * @reserved: reserved for future 6930 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 6931 * @active_dwell: dwell time for active scan per LMAC 6932 * @adwell_default_2g: adaptive dwell default number of APs 6933 * for 2.4GHz channel 6934 * @adwell_default_5g: adaptive dwell default number of APs 6935 * for 5GHz channels 6936 * @adwell_default_social_chn: adaptive dwell default number of 6937 * APs per social channel 6938 * @reserved1: reserved for future 6939 * @adwell_max_budget: the maximal number of TUs that adaptive dwell 6940 * can add to the total scan time 6941 * @max_out_of_time: max out of serving channel time, per LMAC 6942 * @suspend_time: max suspend time, per LMAC 6943 * @scan_priority: priority of the request 6944 * @passive_dwell: continues dwell time for passive channel 6945 * (without adaptive dwell) 6946 * @num_of_fragments: number of fragments needed for full fragmented 6947 * scan coverage. 6948 */ 6949 struct iwx_scan_general_params_v10 { 6950 uint16_t flags; 6951 uint8_t reserved; 6952 uint8_t scan_start_mac_id; 6953 uint8_t active_dwell[IWX_SCAN_TWO_LMACS]; 6954 uint8_t adwell_default_2g; 6955 uint8_t adwell_default_5g; 6956 uint8_t adwell_default_social_chn; 6957 uint8_t reserved1; 6958 uint16_t adwell_max_budget; 6959 uint32_t max_out_of_time[IWX_SCAN_TWO_LMACS]; 6960 uint32_t suspend_time[IWX_SCAN_TWO_LMACS]; 6961 uint32_t scan_priority; 6962 uint8_t passive_dwell[IWX_SCAN_TWO_LMACS]; 6963 uint8_t num_of_fragments[IWX_SCAN_TWO_LMACS]; 6964 } __packed; /* SCAN_GENERAL_PARAMS_API_S_VER_10 */ 6965 6966 /** 6967 * struct iwx_scan_channel_params_v6 6968 * @flags: channel flags &enum iwl_scan_channel_flags 6969 * @count: num of channels in scan request 6970 * @n_aps_override: override the number of APs the FW uses to calculate dwell 6971 * time when adaptive dwell is used. 6972 * Channel k will use n_aps_override[i] when BIT(20 + i) is set in 6973 * channel_config[k].flags 6974 * @channel_config: array of explicit channel configurations 6975 * for 2.4Ghz and 5.2Ghz bands 6976 */ 6977 struct iwx_scan_channel_params_v6 { 6978 uint8_t flags; 6979 uint8_t count; 6980 uint8_t n_aps_override[2]; 6981 struct iwx_scan_channel_cfg_umac channel_config[67]; 6982 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_6 */ 6983 6984 /** 6985 * struct iwx_scan_periodic_parms_v1 6986 * @schedule: can scheduling parameter 6987 * @delay: initial delay of the periodic scan in seconds 6988 * @reserved: reserved for future 6989 */ 6990 struct iwx_scan_periodic_parms_v1 { 6991 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 6992 uint16_t delay; 6993 uint16_t reserved; 6994 } __packed; /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 6995 6996 #define IWX_SCAN_SHORT_SSID_MAX_SIZE 8 6997 #define IWX_SCAN_BSSID_MAX_SIZE 16 6998 6999 /** 7000 * struct iwx_scan_probe_params_v4 7001 * @preq: scan probe request params 7002 * @short_ssid_num: number of valid short SSIDs in short ssid array 7003 * @bssid_num: number of valid bssid in bssids array 7004 * @reserved: reserved 7005 * @direct_scan: list of ssids 7006 * @short_ssid: array of short ssids 7007 * @bssid_array: array of bssids 7008 */ 7009 struct iwx_scan_probe_params_v4 { 7010 struct iwx_scan_probe_req preq; 7011 uint8_t short_ssid_num; 7012 uint8_t bssid_num; 7013 uint16_t reserved; 7014 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 7015 uint32_t short_ssid[IWX_SCAN_SHORT_SSID_MAX_SIZE]; 7016 uint8_t bssid_array[IWX_SCAN_BSSID_MAX_SIZE][ETHER_ADDR_LEN]; 7017 } __packed; /* SCAN_PROBE_PARAMS_API_S_VER_4 */ 7018 7019 /** 7020 * struct iwx_scan_req_params_v14 7021 * @general_params: &struct iwx_scan_general_params_v10 7022 * @channel_params: &struct iwx_scan_channel_params_v6 7023 * @periodic_params: &struct iwx_scan_periodic_parms_v1 7024 * @probe_params: &struct iwx_scan_probe_params_v4 7025 */ 7026 struct iwx_scan_req_params_v14 { 7027 struct iwx_scan_general_params_v10 general_params; 7028 struct iwx_scan_channel_params_v6 channel_params; 7029 struct iwx_scan_periodic_parms_v1 periodic_params; 7030 struct iwx_scan_probe_params_v4 probe_params; 7031 } __packed; /* SCAN_REQUEST_PARAMS_API_S_VER_14 */ 7032 7033 /** 7034 * struct iwx_scan_req_umac_v14 7035 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 7036 * @ooc_priority: out of channel priority - &enum iwx_scan_priority 7037 * @scan_params: scan parameters 7038 */ 7039 struct iwx_scan_req_umac_v14 { 7040 uint32_t uid; 7041 uint32_t ooc_priority; 7042 struct iwx_scan_req_params_v14 scan_params; 7043 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_14 */ 7044 7045 /** 7046 * struct iwx_umac_scan_abort 7047 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 7048 * @flags: reserved 7049 */ 7050 struct iwx_umac_scan_abort { 7051 uint32_t uid; 7052 uint32_t flags; 7053 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 7054 7055 /** 7056 * struct iwx_umac_scan_complete 7057 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 7058 * @last_schedule: last scheduling line 7059 * @last_iter: last scan iteration number 7060 * @scan status: &enum iwx_scan_offload_complete_status 7061 * @ebs_status: &enum iwx_scan_ebs_status 7062 * @time_from_last_iter: time elapsed from last iteration 7063 * @reserved: for future use 7064 */ 7065 struct iwx_umac_scan_complete { 7066 uint32_t uid; 7067 uint8_t last_schedule; 7068 uint8_t last_iter; 7069 uint8_t status; 7070 uint8_t ebs_status; 7071 uint32_t time_from_last_iter; 7072 uint32_t reserved; 7073 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 7074 7075 #define IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 7076 /** 7077 * struct iwx_scan_offload_profile_match - match information 7078 * @bssid: matched bssid 7079 * @channel: channel where the match occurred 7080 * @energy: 7081 * @matching_feature: 7082 * @matching_channels: bitmap of channels that matched, referencing 7083 * the channels passed in tue scan offload request 7084 */ 7085 struct iwx_scan_offload_profile_match { 7086 uint8_t bssid[ETHER_ADDR_LEN]; 7087 uint16_t reserved; 7088 uint8_t channel; 7089 uint8_t energy; 7090 uint8_t matching_feature; 7091 uint8_t matching_channels[IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 7092 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 7093 7094 /** 7095 * struct iwx_scan_offload_profiles_query - match results query response 7096 * @matched_profiles: bitmap of matched profiles, referencing the 7097 * matches passed in the scan offload request 7098 * @last_scan_age: age of the last offloaded scan 7099 * @n_scans_done: number of offloaded scans done 7100 * @gp2_d0u: GP2 when D0U occurred 7101 * @gp2_invoked: GP2 when scan offload was invoked 7102 * @resume_while_scanning: not used 7103 * @self_recovery: obsolete 7104 * @reserved: reserved 7105 * @matches: array of match information, one for each match 7106 */ 7107 struct iwx_scan_offload_profiles_query { 7108 uint32_t matched_profiles; 7109 uint32_t last_scan_age; 7110 uint32_t n_scans_done; 7111 uint32_t gp2_d0u; 7112 uint32_t gp2_invoked; 7113 uint8_t resume_while_scanning; 7114 uint8_t self_recovery; 7115 uint16_t reserved; 7116 struct iwx_scan_offload_profile_match matches[IWX_SCAN_MAX_PROFILES]; 7117 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 7118 7119 /** 7120 * struct iwx_umac_scan_iter_complete_notif - notifies end of scanning iteration 7121 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 7122 * @scanned_channels: number of channels scanned and number of valid elements in 7123 * results array 7124 * @status: one of SCAN_COMP_STATUS_* 7125 * @bt_status: BT on/off status 7126 * @last_channel: last channel that was scanned 7127 * @tsf_low: TSF timer (lower half) in usecs 7128 * @tsf_high: TSF timer (higher half) in usecs 7129 * @results: array of scan results, only "scanned_channels" of them are valid 7130 */ 7131 struct iwx_umac_scan_iter_complete_notif { 7132 uint32_t uid; 7133 uint8_t scanned_channels; 7134 uint8_t status; 7135 uint8_t bt_status; 7136 uint8_t last_channel; 7137 uint32_t tsf_low; 7138 uint32_t tsf_high; 7139 struct iwx_scan_results_notif results[]; 7140 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 7141 7142 #define IWX_GSCAN_START_CMD 0x0 7143 #define IWX_GSCAN_STOP_CMD 0x1 7144 #define IWX_GSCAN_SET_HOTLIST_CMD 0x2 7145 #define IWX_GSCAN_RESET_HOTLIST_CMD 0x3 7146 #define IWX_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4 7147 #define IWX_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5 7148 #define IWX_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD 7149 #define IWX_GSCAN_HOTLIST_CHANGE_EVENT 0xFE 7150 #define IWX_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF 7151 7152 /* STA API */ 7153 7154 /** 7155 * flags for the ADD_STA host command 7156 * @IWX_STA_FLG_REDUCED_TX_PWR_CTRL: 7157 * @IWX_STA_FLG_REDUCED_TX_PWR_DATA: 7158 * @IWX_STA_FLG_DISABLE_TX: set if TX should be disabled 7159 * @IWX_STA_FLG_PS: set if STA is in Power Save 7160 * @IWX_STA_FLG_INVALID: set if STA is invalid 7161 * @IWX_STA_FLG_DLP_EN: Direct Link Protocol is enabled 7162 * @IWX_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 7163 * @IWX_STA_FLG_DRAIN_FLOW: drain flow 7164 * @IWX_STA_FLG_PAN: STA is for PAN interface 7165 * @IWX_STA_FLG_CLASS_AUTH: 7166 * @IWX_STA_FLG_CLASS_ASSOC: 7167 * @IWX_STA_FLG_CLASS_MIMO_PROT: 7168 * @IWX_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 7169 * @IWX_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 7170 * @IWX_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 7171 * initialised by driver and can be updated by fw upon reception of 7172 * action frames that can change the channel width. When cleared the fw 7173 * will send all the frames in 20MHz even when FAT channel is requested. 7174 * @IWX_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 7175 * driver and can be updated by fw upon reception of action frames. 7176 * @IWX_STA_FLG_MFP_EN: Management Frame Protection 7177 */ 7178 #define IWX_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3) 7179 #define IWX_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6) 7180 7181 #define IWX_STA_FLG_DISABLE_TX (1 << 4) 7182 7183 #define IWX_STA_FLG_PS (1 << 8) 7184 #define IWX_STA_FLG_DRAIN_FLOW (1 << 12) 7185 #define IWX_STA_FLG_PAN (1 << 13) 7186 #define IWX_STA_FLG_CLASS_AUTH (1 << 14) 7187 #define IWX_STA_FLG_CLASS_ASSOC (1 << 15) 7188 #define IWX_STA_FLG_RTS_MIMO_PROT (1 << 17) 7189 7190 #define IWX_STA_FLG_MAX_AGG_SIZE_SHIFT 19 7191 #define IWX_STA_FLG_MAX_AGG_SIZE_8K (0 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7192 #define IWX_STA_FLG_MAX_AGG_SIZE_16K (1 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7193 #define IWX_STA_FLG_MAX_AGG_SIZE_32K (2 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7194 #define IWX_STA_FLG_MAX_AGG_SIZE_64K (3 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7195 #define IWX_STA_FLG_MAX_AGG_SIZE_128K (4 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7196 #define IWX_STA_FLG_MAX_AGG_SIZE_256K (5 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7197 #define IWX_STA_FLG_MAX_AGG_SIZE_512K (6 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7198 #define IWX_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7199 #define IWX_STA_FLG_MAX_AGG_SIZE_2M (8 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7200 #define IWX_STA_FLG_MAX_AGG_SIZE_4M (9 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7201 #define IWX_STA_FLG_MAX_AGG_SIZE_MSK (0xf << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 7202 7203 #define IWX_STA_FLG_AGG_MPDU_DENS_SHIFT 23 7204 #define IWX_STA_FLG_AGG_MPDU_DENS_2US (4 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7205 #define IWX_STA_FLG_AGG_MPDU_DENS_4US (5 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7206 #define IWX_STA_FLG_AGG_MPDU_DENS_8US (6 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7207 #define IWX_STA_FLG_AGG_MPDU_DENS_16US (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7208 #define IWX_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 7209 7210 #define IWX_STA_FLG_FAT_EN_20MHZ (0 << 26) 7211 #define IWX_STA_FLG_FAT_EN_40MHZ (1 << 26) 7212 #define IWX_STA_FLG_FAT_EN_80MHZ (2 << 26) 7213 #define IWX_STA_FLG_FAT_EN_160MHZ (3 << 26) 7214 #define IWX_STA_FLG_FAT_EN_MSK (3 << 26) 7215 7216 #define IWX_STA_FLG_MIMO_EN_SISO (0 << 28) 7217 #define IWX_STA_FLG_MIMO_EN_MIMO2 (1 << 28) 7218 #define IWX_STA_FLG_MIMO_EN_MIMO3 (2 << 28) 7219 #define IWX_STA_FLG_MIMO_EN_MSK (3 << 28) 7220 7221 /** 7222 * key flags for the ADD_STA host command 7223 * @IWX_STA_KEY_FLG_NO_ENC: no encryption 7224 * @IWX_STA_KEY_FLG_WEP: WEP encryption algorithm 7225 * @IWX_STA_KEY_FLG_CCM: CCMP encryption algorithm 7226 * @IWX_STA_KEY_FLG_TKIP: TKIP encryption algorithm 7227 * @IWX_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 7228 * @IWX_STA_KEY_FLG_CMAC: CMAC encryption algorithm 7229 * @IWX_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 7230 * @IWX_STA_KEY_FLG_EN_MSK: mask for encryption algorithm value 7231 * @IWX_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 7232 * station info array (1 - n 1X mode) 7233 * @IWX_STA_KEY_FLG_KEYID_MSK: the index of the key 7234 * @IWX_STA_KEY_NOT_VALID: key is invalid 7235 * @IWX_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 7236 * @IWX_STA_KEY_MULTICAST: set for multicast key 7237 * @IWX_STA_KEY_MFP: key is used for Management Frame Protection 7238 */ 7239 #define IWX_STA_KEY_FLG_NO_ENC (0 << 0) 7240 #define IWX_STA_KEY_FLG_WEP (1 << 0) 7241 #define IWX_STA_KEY_FLG_CCM (2 << 0) 7242 #define IWX_STA_KEY_FLG_TKIP (3 << 0) 7243 #define IWX_STA_KEY_FLG_EXT (4 << 0) 7244 #define IWX_STA_KEY_FLG_CMAC (6 << 0) 7245 #define IWX_STA_KEY_FLG_ENC_UNKNOWN (7 << 0) 7246 #define IWX_STA_KEY_FLG_EN_MSK (7 << 0) 7247 #define IWX_STA_KEY_FLG_WEP_KEY_MAP (1 << 3) 7248 #define IWX_STA_KEY_FLG_KEYID_POS 8 7249 #define IWX_STA_KEY_FLG_KEYID_MSK (3 << IWX_STA_KEY_FLG_KEYID_POS) 7250 #define IWX_STA_KEY_NOT_VALID (1 << 11) 7251 #define IWX_STA_KEY_FLG_WEP_13BYTES (1 << 12) 7252 #define IWX_STA_KEY_MULTICAST (1 << 14) 7253 #define IWX_STA_KEY_MFP (1 << 15) 7254 7255 /** 7256 * indicate to the fw what flag are being changed 7257 * @IWX_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 7258 * @IWX_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 7259 * @IWX_STA_MODIFY_TX_RATE: unused 7260 * @IWX_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 7261 * @IWX_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 7262 * @IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 7263 * @IWX_STA_MODIFY_PROT_TH: 7264 * @IWX_STA_MODIFY_QUEUES: modify the queues used by this station 7265 */ 7266 #define IWX_STA_MODIFY_QUEUE_REMOVAL (1 << 0) 7267 #define IWX_STA_MODIFY_TID_DISABLE_TX (1 << 1) 7268 #define IWX_STA_MODIFY_TX_RATE (1 << 2) 7269 #define IWX_STA_MODIFY_ADD_BA_TID (1 << 3) 7270 #define IWX_STA_MODIFY_REMOVE_BA_TID (1 << 4) 7271 #define IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5) 7272 #define IWX_STA_MODIFY_PROT_TH (1 << 6) 7273 #define IWX_STA_MODIFY_QUEUES (1 << 7) 7274 7275 #define IWX_STA_MODE_MODIFY 1 7276 7277 /** 7278 * type of sleep of the station 7279 * @IWX_STA_SLEEP_STATE_AWAKE: 7280 * @IWX_STA_SLEEP_STATE_PS_POLL: 7281 * @IWX_STA_SLEEP_STATE_UAPSD: 7282 * @IWX_STA_SLEEP_STATE_MOREDATA: set more-data bit on 7283 * (last) released frame 7284 */ 7285 #define IWX_STA_SLEEP_STATE_AWAKE 0 7286 #define IWX_STA_SLEEP_STATE_PS_POLL (1 << 0) 7287 #define IWX_STA_SLEEP_STATE_UAPSD (1 << 1) 7288 #define IWX_STA_SLEEP_STATE_MOREDATA (1 << 2) 7289 7290 /* STA ID and color bits definitions */ 7291 #define IWX_STA_ID_SEED (0x0f) 7292 #define IWX_STA_ID_POS (0) 7293 #define IWX_STA_ID_MSK (IWX_STA_ID_SEED << IWX_STA_ID_POS) 7294 7295 #define IWX_STA_COLOR_SEED (0x7) 7296 #define IWX_STA_COLOR_POS (4) 7297 #define IWX_STA_COLOR_MSK (IWX_STA_COLOR_SEED << IWX_STA_COLOR_POS) 7298 7299 #define IWX_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 7300 (((id_n_color) & IWX_STA_COLOR_MSK) >> IWX_STA_COLOR_POS) 7301 #define IWX_STA_ID_N_COLOR_GET_ID(id_n_color) \ 7302 (((id_n_color) & IWX_STA_ID_MSK) >> IWX_STA_ID_POS) 7303 7304 #define IWX_STA_KEY_MAX_NUM (16) 7305 #define IWX_STA_KEY_IDX_INVALID (0xff) 7306 #define IWX_STA_KEY_MAX_DATA_KEY_NUM (4) 7307 #define IWX_MAX_GLOBAL_KEYS (4) 7308 #define IWX_STA_KEY_LEN_WEP40 (5) 7309 #define IWX_STA_KEY_LEN_WEP104 (13) 7310 7311 /** 7312 * struct iwx_keyinfo - key information 7313 * @key_flags: type %iwx_sta_key_flag 7314 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 7315 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 7316 * @key_offset: key offset in the fw's key table 7317 * @key: 16-byte unicast decryption key 7318 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 7319 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 7320 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 7321 */ 7322 struct iwx_keyinfo { 7323 uint16_t key_flags; 7324 uint8_t tkip_rx_tsc_byte2; 7325 uint8_t reserved1; 7326 uint16_t tkip_rx_ttak[5]; 7327 uint8_t key_offset; 7328 uint8_t reserved2; 7329 uint8_t key[16]; 7330 uint64_t tx_secur_seq_cnt; 7331 uint64_t hw_tkip_mic_rx_key; 7332 uint64_t hw_tkip_mic_tx_key; 7333 } __packed; 7334 7335 #define IWX_ADD_STA_STATUS_MASK 0xFF 7336 #define IWX_ADD_STA_BAID_VALID_MASK 0x8000 7337 #define IWX_ADD_STA_BAID_MASK 0x7F00 7338 #define IWX_ADD_STA_BAID_SHIFT 8 7339 7340 /** 7341 * struct iwx_add_sta_cmd - Add/modify a station in the fw's sta table. 7342 * ( REPLY_ADD_STA = 0x18 ) 7343 * @add_modify: see &enum iwl_sta_mode 7344 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD) 7345 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 7346 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field. 7347 * @mac_id_n_color: the Mac context this station belongs to, 7348 * see &enum iwl_ctxt_id_and_color 7349 * @addr: station's MAC address 7350 * @reserved2: reserved 7351 * @sta_id: index of station in uCode's station table 7352 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave 7353 * alone. 1 - modify, 0 - don't change. 7354 * @reserved3: reserved 7355 * @station_flags: look at &enum iwl_sta_flags 7356 * @station_flags_msk: what of %station_flags have changed, 7357 * also &enum iwl_sta_flags 7358 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 7359 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set 7360 * add_immediate_ba_ssn. 7361 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 7362 * Set %STA_MODIFY_REMOVE_BA_TID to use this field 7363 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 7364 * add_immediate_ba_tid. 7365 * @sleep_tx_count: number of packets to transmit to station even though it is 7366 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 7367 * keeps track of STA sleep state. 7368 * @station_type: type of this station. See &enum iwl_sta_type. 7369 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag. 7370 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 7371 * mac-addr. 7372 * @beamform_flags: beam forming controls 7373 * @tfd_queue_msk: tfd queues used by this station. 7374 * Obsolete for new TX API (9 and above). 7375 * @rx_ba_window: aggregation window size 7376 * @sp_length: the size of the SP in actual number of frames 7377 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver 7378 * enabled ACs. 7379 * 7380 * The device contains an internal table of per-station information, with info 7381 * on security keys, aggregation parameters, and Tx rates for initial Tx 7382 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD). 7383 * 7384 * ADD_STA sets up the table entry for one station, either creating a new 7385 * entry, or modifying a pre-existing one. 7386 */ 7387 struct iwx_add_sta_cmd { 7388 uint8_t add_modify; 7389 uint8_t awake_acs; 7390 uint16_t tid_disable_tx; 7391 uint32_t mac_id_n_color; 7392 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 7393 uint16_t reserved2; 7394 uint8_t sta_id; 7395 uint8_t modify_mask; 7396 uint16_t reserved3; 7397 uint32_t station_flags; 7398 uint32_t station_flags_msk; 7399 uint8_t add_immediate_ba_tid; 7400 uint8_t remove_immediate_ba_tid; 7401 uint16_t add_immediate_ba_ssn; 7402 uint16_t sleep_tx_count; 7403 uint8_t sleep_state_flags; 7404 uint8_t station_type; 7405 uint16_t assoc_id; 7406 uint16_t beamform_flags; 7407 uint32_t tfd_queue_msk; 7408 uint16_t rx_ba_window; 7409 uint8_t sp_length; 7410 uint8_t uapsd_acs; 7411 } __packed; /* ADD_STA_CMD_API_S_VER_10 */ 7412 7413 /** 7414 * FW station types 7415 * ( REPLY_ADD_STA = 0x18 ) 7416 * @IWX_STA_LINK: Link station - normal RX and TX traffic. 7417 * @IWX_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons 7418 * and probe responses. 7419 * @IWX_STA_MULTICAST: multicast traffic, 7420 * @IWX_STA_TDLS_LINK: TDLS link station 7421 * @IWX_STA_AUX_ACTIVITY: auxiliary station (scan, ROC and so on). 7422 */ 7423 #define IWX_STA_LINK 0 7424 #define IWX_STA_GENERAL_PURPOSE 1 7425 #define IWX_STA_MULTICAST 2 7426 #define IWX_STA_TDLS_LINK 3 7427 #define IWX_STA_AUX_ACTIVITY 4 7428 7429 /** 7430 * struct iwx_add_sta_key_common - add/modify sta key common part 7431 * ( REPLY_ADD_STA_KEY = 0x17 ) 7432 * @sta_id: index of station in uCode's station table 7433 * @key_offset: key offset in key storage 7434 * @key_flags: IWX_STA_KEY_FLG_* 7435 * @key: key material data 7436 * @rx_secur_seq_cnt: RX security sequence counter for the key 7437 */ 7438 struct iwx_add_sta_key_common { 7439 uint8_t sta_id; 7440 uint8_t key_offset; 7441 uint16_t key_flags; 7442 uint8_t key[32]; 7443 uint8_t rx_secur_seq_cnt[16]; 7444 } __packed; 7445 7446 /** 7447 * struct iwx_add_sta_key_cmd_v1 - add/modify sta key 7448 * @common: see &struct iwx_add_sta_key_common 7449 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 7450 * @reserved: reserved 7451 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 7452 */ 7453 struct iwx_add_sta_key_cmd_v1 { 7454 struct iwx_add_sta_key_common common; 7455 uint8_t tkip_rx_tsc_byte2; 7456 uint8_t reserved; 7457 uint16_t tkip_rx_ttak[5]; 7458 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */ 7459 7460 /** 7461 * struct iwx_add_sta_key_cmd - add/modify sta key 7462 * @common: see &struct iwx_add_sta_key_common 7463 * @rx_mic_key: TKIP RX unicast or multicast key 7464 * @tx_mic_key: TKIP TX key 7465 * @transmit_seq_cnt: TSC, transmit packet number 7466 */ 7467 struct iwx_add_sta_key_cmd { 7468 struct iwx_add_sta_key_common common; 7469 uint64_t rx_mic_key; 7470 uint64_t tx_mic_key; 7471 uint64_t transmit_seq_cnt; 7472 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */ 7473 7474 /** 7475 * status in the response to ADD_STA command 7476 * @IWX_ADD_STA_SUCCESS: operation was executed successfully 7477 * @IWX_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 7478 * @IWX_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 7479 * @IWX_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 7480 * that doesn't exist. 7481 */ 7482 #define IWX_ADD_STA_SUCCESS 0x1 7483 #define IWX_ADD_STA_STATIONS_OVERLOAD 0x2 7484 #define IWX_ADD_STA_IMMEDIATE_BA_FAILURE 0x4 7485 #define IWX_ADD_STA_MODIFY_NON_EXISTING_STA 0x8 7486 7487 /** 7488 * struct iwx_rm_sta_cmd - Add / modify a station in the fw's station table 7489 * ( IWX_REMOVE_STA = 0x19 ) 7490 * @sta_id: the station id of the station to be removed 7491 */ 7492 struct iwx_rm_sta_cmd { 7493 uint8_t sta_id; 7494 uint8_t reserved[3]; 7495 } __packed; /* IWX_REMOVE_STA_CMD_API_S_VER_2 */ 7496 7497 /** 7498 * struct iwx_mgmt_mcast_key_cmd 7499 * ( IWX_MGMT_MCAST_KEY = 0x1f ) 7500 * @ctrl_flags: %iwx_sta_key_flag 7501 * @IGTK: 7502 * @K1: IGTK master key 7503 * @K2: IGTK sub key 7504 * @sta_id: station ID that support IGTK 7505 * @key_id: 7506 * @receive_seq_cnt: initial RSC/PN needed for replay check 7507 */ 7508 struct iwx_mgmt_mcast_key_cmd { 7509 uint32_t ctrl_flags; 7510 uint8_t IGTK[16]; 7511 uint8_t K1[16]; 7512 uint8_t K2[16]; 7513 uint32_t key_id; 7514 uint32_t sta_id; 7515 uint64_t receive_seq_cnt; 7516 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 7517 7518 struct iwx_wep_key { 7519 uint8_t key_index; 7520 uint8_t key_offset; 7521 uint16_t reserved1; 7522 uint8_t key_size; 7523 uint8_t reserved2[3]; 7524 uint8_t key[16]; 7525 } __packed; 7526 7527 struct iwx_wep_key_cmd { 7528 uint32_t mac_id_n_color; 7529 uint8_t num_keys; 7530 uint8_t decryption_type; 7531 uint8_t flags; 7532 uint8_t reserved; 7533 struct iwx_wep_key wep_key[0]; 7534 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 7535 7536 /* 7537 * BT coex 7538 */ 7539 7540 #define IWX_BT_COEX_DISABLE 0x0 7541 #define IWX_BT_COEX_NW 0x1 7542 #define IWX_BT_COEX_BT 0x2 7543 #define IWX_BT_COEX_WIFI 0x3 7544 /* BT_COEX_MODES_E */ 7545 7546 #define IWX_BT_COEX_MPLUT_ENABLED (1 << 0) 7547 #define IWX_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1) 7548 #define IWX_BT_COEX_SYNC2SCO_ENABLED (1 << 2) 7549 #define IWX_BT_COEX_CORUN_ENABLED (1 << 3) 7550 #define IWX_BT_COEX_HIGH_BAND_RET (1 << 4) 7551 /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 7552 7553 /** 7554 * struct iwx_bt_coex_cmd - bt coex configuration command 7555 * @mode: enum %iwx_bt_coex_mode 7556 * @enabled_modules: enum %iwx_bt_coex_enabled_modules 7557 * 7558 * The structure is used for the BT_COEX command. 7559 */ 7560 struct iwx_bt_coex_cmd { 7561 uint32_t mode; 7562 uint32_t enabled_modules; 7563 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 7564 7565 7566 /* 7567 * Location Aware Regulatory (LAR) API - MCC updates 7568 */ 7569 7570 /** 7571 * struct iwx_mcc_update_cmd - Request the device to update geographic 7572 * regulatory profile according to the given MCC (Mobile Country Code). 7573 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 7574 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 7575 * MCC in the cmd response will be the relevant MCC in the NVM. 7576 * @mcc: given mobile country code 7577 * @source_id: the source from where we got the MCC, see IWX_MCC_SOURCE_* 7578 * @reserved: reserved for alignment 7579 * @key: integrity key for MCC API OEM testing 7580 * @reserved2: reserved 7581 */ 7582 struct iwx_mcc_update_cmd { 7583 uint16_t mcc; 7584 uint8_t source_id; 7585 uint8_t reserved; 7586 uint32_t key; 7587 uint32_t reserved2[5]; 7588 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 7589 7590 /** 7591 * iwx_mcc_update_resp_v3 - response to MCC_UPDATE_CMD. 7592 * Contains the new channel control profile map, if changed, and the new MCC 7593 * (mobile country code). 7594 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 7595 * @status: see &enum iwx_mcc_update_status 7596 * @mcc: the new applied MCC 7597 * @cap: capabilities for all channels which matches the MCC 7598 * @source_id: the MCC source, see IWX_MCC_SOURCE_* 7599 * @time: time elapsed from the MCC test start (in 30 seconds TU) 7600 * @reserved: reserved. 7601 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 7602 * channels, depending on platform) 7603 * @channels: channel control data map, DWORD for each channel. Only the first 7604 * 16bits are used. 7605 */ 7606 struct iwx_mcc_update_resp_v3 { 7607 uint32_t status; 7608 uint16_t mcc; 7609 uint8_t cap; 7610 uint8_t source_id; 7611 uint16_t time; 7612 uint16_t geo_info; 7613 uint32_t n_channels; 7614 uint32_t channels[0]; 7615 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */ 7616 7617 /** 7618 * geographic information. 7619 * @GEO_NO_INFO: no special info for this geo profile. 7620 * @GEO_WMM_ETSI_5GHZ_INFO: this geo profile limits the WMM params 7621 * for the 5 GHz band. 7622 */ 7623 #define IWX_GEO_NO_INFO 0 7624 #define IWX_GEO_WMM_ETSI_5GHZ_INFO (1 << 0) 7625 7626 /** 7627 * struct iwx_mcc_update_resp - response to MCC_UPDATE_CMD. 7628 * Contains the new channel control profile map, if changed, and the new MCC 7629 * (mobile country code). 7630 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 7631 * @status: see &enum iwl_mcc_update_status 7632 * @mcc: the new applied MCC 7633 * @cap: capabilities for all channels which matches the MCC 7634 * @time: time elapsed from the MCC test start (in units of 30 seconds) 7635 * @geo_info: geographic specific profile information 7636 * see IWX_GEO_* 7637 * @source_id: the MCC source, see IWX_MCC_SOURCE_* 7638 * @reserved: for four bytes alignment. 7639 * @n_channels: number of channels in @channels_data. 7640 * @channels: channel control data map, DWORD for each channel. Only the first 7641 * 16bits are used. 7642 */ 7643 struct iwx_mcc_update_resp { 7644 uint32_t status; 7645 uint16_t mcc; 7646 uint16_t cap; 7647 uint16_t time; 7648 uint16_t geo_info; 7649 uint8_t source_id; 7650 uint8_t reserved[3]; 7651 uint32_t n_channels; 7652 uint32_t channels[0]; 7653 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_4 */ 7654 7655 /** 7656 * struct iwx_mcc_chub_notif - chub notifies of mcc change 7657 * (MCC_CHUB_UPDATE_CMD = 0xc9) 7658 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 7659 * the cellular and connectivity cores that gets updates of the mcc, and 7660 * notifies the ucode directly of any mcc change. 7661 * The ucode requests the driver to request the device to update geographic 7662 * regulatory profile according to the given MCC (Mobile Country Code). 7663 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 7664 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 7665 * MCC in the cmd response will be the relevant MCC in the NVM. 7666 * @mcc: given mobile country code 7667 * @source_id: identity of the change originator, see IWX_MCC_SOURCE_* 7668 * @reserved1: reserved for alignment 7669 */ 7670 struct iwx_mcc_chub_notif { 7671 uint16_t mcc; 7672 uint8_t source_id; 7673 uint8_t reserved1; 7674 } __packed; /* LAR_MCC_NOTIFY_S */ 7675 7676 enum iwx_mcc_update_status { 7677 IWX_MCC_RESP_NEW_CHAN_PROFILE, 7678 IWX_MCC_RESP_SAME_CHAN_PROFILE, 7679 IWX_MCC_RESP_INVALID, 7680 IWX_MCC_RESP_NVM_DISABLED, 7681 IWX_MCC_RESP_ILLEGAL, 7682 IWX_MCC_RESP_LOW_PRIORITY, 7683 IWX_MCC_RESP_TEST_MODE_ACTIVE, 7684 IWX_MCC_RESP_TEST_MODE_NOT_ACTIVE, 7685 IWX_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 7686 }; 7687 7688 #define IWX_MCC_SOURCE_OLD_FW 0 7689 #define IWX_MCC_SOURCE_ME 1 7690 #define IWX_MCC_SOURCE_BIOS 2 7691 #define IWX_MCC_SOURCE_3G_LTE_HOST 3 7692 #define IWX_MCC_SOURCE_3G_LTE_DEVICE 4 7693 #define IWX_MCC_SOURCE_WIFI 5 7694 #define IWX_MCC_SOURCE_RESERVED 6 7695 #define IWX_MCC_SOURCE_DEFAULT 7 7696 #define IWX_MCC_SOURCE_UNINITIALIZED 8 7697 #define IWX_MCC_SOURCE_MCC_API 9 7698 #define IWX_MCC_SOURCE_GET_CURRENT 0x10 7699 #define IWX_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11 7700 7701 /* 7702 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 7703 * As the firmware is slowly running out of command IDs and grouping of 7704 * commands is desirable anyway, the firmware is extending the command 7705 * header from 4 bytes to 8 bytes to introduce a group (in place of the 7706 * former flags field, since that's always 0 on commands and thus can 7707 * be easily used to distinguish between the two). 7708 * 7709 * These functions retrieve specific information from the id field in 7710 * the iwx_host_cmd struct which contains the command id, the group id, 7711 * and the version of the command. 7712 */ 7713 static inline uint8_t 7714 iwx_cmd_opcode(uint32_t cmdid) 7715 { 7716 return cmdid & 0xff; 7717 } 7718 7719 static inline uint8_t 7720 iwx_cmd_groupid(uint32_t cmdid) 7721 { 7722 return ((cmdid & 0Xff00) >> 8); 7723 } 7724 7725 static inline uint8_t 7726 iwx_cmd_version(uint32_t cmdid) 7727 { 7728 return ((cmdid & 0xff0000) >> 16); 7729 } 7730 7731 static inline uint32_t 7732 iwx_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 7733 { 7734 return opcode + (groupid << 8) + (version << 16); 7735 } 7736 7737 /* make uint16_t wide id out of uint8_t group and opcode */ 7738 #define IWX_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 7739 7740 struct iwx_cmd_header { 7741 uint8_t code; 7742 uint8_t flags; 7743 uint8_t idx; 7744 uint8_t qid; 7745 } __packed; 7746 7747 struct iwx_cmd_header_wide { 7748 uint8_t opcode; 7749 uint8_t group_id; 7750 uint8_t idx; 7751 uint8_t qid; 7752 uint16_t length; 7753 uint8_t reserved; 7754 uint8_t version; 7755 } __packed; 7756 7757 #define IWX_POWER_SCHEME_CAM 1 7758 #define IWX_POWER_SCHEME_BPS 2 7759 #define IWX_POWER_SCHEME_LP 3 7760 7761 #define IWX_DEF_CMD_PAYLOAD_SIZE 320 7762 #define IWX_MAX_CMD_PAYLOAD_SIZE (4096 - sizeof(struct iwx_cmd_header_wide)) 7763 #define IWX_CMD_FAILED_MSK 0x40 7764 7765 /** 7766 * struct iwx_device_cmd 7767 * 7768 * For allocation of the command and tx queues, this establishes the overall 7769 * size of the largest command we send to uCode, except for commands that 7770 * aren't fully copied and use other TFD space. 7771 */ 7772 struct iwx_device_cmd { 7773 union { 7774 struct { 7775 struct iwx_cmd_header hdr; 7776 uint8_t data[IWX_DEF_CMD_PAYLOAD_SIZE]; 7777 }; 7778 struct { 7779 struct iwx_cmd_header_wide hdr_wide; 7780 uint8_t data_wide[IWX_DEF_CMD_PAYLOAD_SIZE - 7781 sizeof(struct iwx_cmd_header_wide) + 7782 sizeof(struct iwx_cmd_header)]; 7783 }; 7784 }; 7785 } __packed; 7786 7787 struct iwx_rx_packet { 7788 /* 7789 * The first 4 bytes of the RX frame header contain both the RX frame 7790 * size and some flags. 7791 * Bit fields: 7792 * 31: flag flush RB request 7793 * 30: flag ignore TC (terminal counter) request 7794 * 29: flag fast IRQ request 7795 * 28-26: Reserved 7796 * 25: Offload enabled 7797 * 24: RPF enabled 7798 * 23: RSS enabled 7799 * 22: Checksum enabled 7800 * 21-16: RX queue 7801 * 15-14: Reserved 7802 * 13-00: RX frame size 7803 */ 7804 uint32_t len_n_flags; 7805 struct iwx_cmd_header hdr; 7806 uint8_t data[]; 7807 } __packed; 7808 7809 #define IWX_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 7810 #define IWX_FH_RSCSR_FRAME_INVALID 0x55550000 7811 #define IWX_FH_RSCSR_FRAME_ALIGN 0x40 7812 #define IWX_FH_RSCSR_RPA_EN (1 << 25) 7813 #define IWX_FH_RSCSR_RADA_EN (1 << 26) 7814 #define IWX_FH_RSCSR_RXQ_POS 16 7815 #define IWX_FH_RSCSR_RXQ_MASK 0x3F0000 7816 7817 static uint32_t 7818 iwx_rx_packet_len(const struct iwx_rx_packet *pkt) 7819 { 7820 7821 return le32toh(pkt->len_n_flags) & IWX_FH_RSCSR_FRAME_SIZE_MSK; 7822 } 7823 7824 static uint32_t 7825 iwx_rx_packet_payload_len(const struct iwx_rx_packet *pkt) 7826 { 7827 7828 return iwx_rx_packet_len(pkt) - sizeof(pkt->hdr); 7829 } 7830 7831 7832 #define IWX_MIN_DBM -100 7833 #define IWX_MAX_DBM -33 /* realistic guess */ 7834 7835 #define IWX_READ(sc, reg) \ 7836 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 7837 7838 #define IWX_WRITE(sc, reg, val) \ 7839 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 7840 7841 #define IWX_WRITE_1(sc, reg, val) \ 7842 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 7843 7844 #define IWX_SETBITS(sc, reg, mask) \ 7845 IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask)) 7846 7847 #define IWX_CLRBITS(sc, reg, mask) \ 7848 IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask)) 7849 7850 #define IWX_BARRIER_WRITE(sc) \ 7851 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 7852 BUS_SPACE_BARRIER_WRITE) 7853 7854 #define IWX_BARRIER_READ_WRITE(sc) \ 7855 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 7856 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 7857