1 /* $OpenBSD: if_iwxreg.h,v 1.17 2020/08/01 16:14:05 stsp Exp $ */ 2 3 /*- 4 * Based on BSD-licensed source modules in the Linux iwlwifi driver, 5 * which were used as the reference documentation for this implementation. 6 * 7 ****************************************************************************** 8 * 9 * This file is provided under a dual BSD/GPLv2 license. When using or 10 * redistributing this file, you may do so under either license. 11 * 12 * GPL LICENSE SUMMARY 13 * 14 * Copyright(c) 2017 Intel Deutschland GmbH 15 * Copyright(c) 2018 - 2019 Intel Corporation 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of version 2 of the GNU General Public License as 19 * published by the Free Software Foundation. 20 * 21 * This program is distributed in the hope that it will be useful, but 22 * WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 24 * General Public License for more details. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2017 Intel Deutschland GmbH 29 * Copyright(c) 2018 - 2019 Intel Corporation 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 36 * * Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * * Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in 40 * the documentation and/or other materials provided with the 41 * distribution. 42 * * Neither the name Intel Corporation nor the names of its 43 * contributors may be used to endorse or promote products derived 44 * from this software without specific prior written permission. 45 * 46 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 47 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 48 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 49 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 50 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 51 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 56 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 ***************************************************************************** 59 */ 60 61 62 /* maximmum number of DRAM map entries supported by FW */ 63 #define IWX_MAX_DRAM_ENTRY 64 64 #define IWX_CSR_CTXT_INFO_BA 0x40 65 66 /** 67 * enum iwx_context_info_flags - Context information control flags 68 * @IWX_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting 69 * the init done for driver command that configures several system modes 70 * @IWX_CTXT_INFO_EARLY_DEBUG: enable early debug 71 * @IWX_CTXT_INFO_ENABLE_CDMP: enable core dump 72 * @IWX_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size 73 * exponent, the actual size is 2**value, valid sizes are 8-2048. 74 * The value is four bits long. Maximum valid exponent is 12 75 * @IWX_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the 76 * default is short format - not supported by the driver) 77 * @IWX_CTXT_INFO_RB_SIZE_POS: RB size position 78 * (values are IWX_CTXT_INFO_RB_SIZE_*K) 79 * @IWX_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size 80 * @IWX_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size 81 * @IWX_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size 82 * @IWX_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size 83 * @IWX_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size 84 * @IWX_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size 85 * @IWX_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size 86 * @IWX_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size 87 * @IWX_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size 88 * @IWX_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size 89 */ 90 enum iwx_context_info_flags { 91 IWX_CTXT_INFO_AUTO_FUNC_INIT = (1 << 0), 92 IWX_CTXT_INFO_EARLY_DEBUG = (1 << 1), 93 IWX_CTXT_INFO_ENABLE_CDMP = (1 << 2), 94 IWX_CTXT_INFO_RB_CB_SIZE_POS = 4, 95 IWX_CTXT_INFO_TFD_FORMAT_LONG = (1 << 8), 96 IWX_CTXT_INFO_RB_SIZE_POS = 9, 97 IWX_CTXT_INFO_RB_SIZE_1K = 0x1, 98 IWX_CTXT_INFO_RB_SIZE_2K = 0x2, 99 IWX_CTXT_INFO_RB_SIZE_4K = 0x4, 100 IWX_CTXT_INFO_RB_SIZE_8K = 0x8, 101 IWX_CTXT_INFO_RB_SIZE_12K = 0x9, 102 IWX_CTXT_INFO_RB_SIZE_16K = 0xa, 103 IWX_CTXT_INFO_RB_SIZE_20K = 0xb, 104 IWX_CTXT_INFO_RB_SIZE_24K = 0xc, 105 IWX_CTXT_INFO_RB_SIZE_28K = 0xd, 106 IWX_CTXT_INFO_RB_SIZE_32K = 0xe, 107 }; 108 109 /* 110 * struct iwx_context_info_version - version structure 111 * @mac_id: SKU and revision id 112 * @version: context information version id 113 * @size: the size of the context information in DWs 114 */ 115 struct iwx_context_info_version { 116 uint16_t mac_id; 117 uint16_t version; 118 uint16_t size; 119 uint16_t reserved; 120 } __packed; 121 122 /* 123 * struct iwx_context_info_control - version structure 124 * @control_flags: context information flags see &enum iwx_context_info_flags 125 */ 126 struct iwx_context_info_control { 127 uint32_t control_flags; 128 uint32_t reserved; 129 } __packed; 130 131 /* 132 * struct iwx_context_info_dram - images DRAM map 133 * each entry in the map represents a DRAM chunk of up to 32 KB 134 * @umac_img: UMAC image DRAM map 135 * @lmac_img: LMAC image DRAM map 136 * @virtual_img: paged image DRAM map 137 */ 138 struct iwx_context_info_dram { 139 uint64_t umac_img[IWX_MAX_DRAM_ENTRY]; 140 uint64_t lmac_img[IWX_MAX_DRAM_ENTRY]; 141 uint64_t virtual_img[IWX_MAX_DRAM_ENTRY]; 142 } __packed; 143 144 /* 145 * struct iwx_context_info_rbd_cfg - RBDs configuration 146 * @free_rbd_addr: default queue free RB CB base address 147 * @used_rbd_addr: default queue used RB CB base address 148 * @status_wr_ptr: default queue used RB status write pointer 149 */ 150 struct iwx_context_info_rbd_cfg { 151 uint64_t free_rbd_addr; 152 uint64_t used_rbd_addr; 153 uint64_t status_wr_ptr; 154 } __packed; 155 156 /* 157 * struct iwx_context_info_hcmd_cfg - command queue configuration 158 * @cmd_queue_addr: address of command queue 159 * @cmd_queue_size: number of entries 160 */ 161 struct iwx_context_info_hcmd_cfg { 162 uint64_t cmd_queue_addr; 163 uint8_t cmd_queue_size; 164 uint8_t reserved[7]; 165 } __packed; 166 167 /* 168 * struct iwx_context_info_dump_cfg - Core Dump configuration 169 * @core_dump_addr: core dump (debug DRAM address) start address 170 * @core_dump_size: size, in DWs 171 */ 172 struct iwx_context_info_dump_cfg { 173 uint64_t core_dump_addr; 174 uint32_t core_dump_size; 175 uint32_t reserved; 176 } __packed; 177 178 /* 179 * struct iwx_context_info_pnvm_cfg - platform NVM data configuration 180 * @platform_nvm_addr: Platform NVM data start address 181 * @platform_nvm_size: size in DWs 182 */ 183 struct iwx_context_info_pnvm_cfg { 184 uint64_t platform_nvm_addr; 185 uint32_t platform_nvm_size; 186 uint32_t reserved; 187 } __packed; 188 189 /* 190 * struct iwx_context_info_early_dbg_cfg - early debug configuration for 191 * dumping DRAM addresses 192 * @early_debug_addr: early debug start address 193 * @early_debug_size: size in DWs 194 */ 195 struct iwx_context_info_early_dbg_cfg { 196 uint64_t early_debug_addr; 197 uint32_t early_debug_size; 198 uint32_t reserved; 199 } __packed; 200 201 /* 202 * struct iwx_context_info - device INIT configuration 203 * @version: version information of context info and HW 204 * @control: control flags of FH configurations 205 * @rbd_cfg: default RX queue configuration 206 * @hcmd_cfg: command queue configuration 207 * @dump_cfg: core dump data 208 * @edbg_cfg: early debug configuration 209 * @pnvm_cfg: platform nvm configuration 210 * @dram: firmware image addresses in DRAM 211 */ 212 struct iwx_context_info { 213 struct iwx_context_info_version version; 214 struct iwx_context_info_control control; 215 uint64_t reserved0; 216 struct iwx_context_info_rbd_cfg rbd_cfg; 217 struct iwx_context_info_hcmd_cfg hcmd_cfg; 218 uint32_t reserved1[4]; 219 struct iwx_context_info_dump_cfg dump_cfg; 220 struct iwx_context_info_early_dbg_cfg edbg_cfg; 221 struct iwx_context_info_pnvm_cfg pnvm_cfg; 222 uint32_t reserved2[16]; 223 struct iwx_context_info_dram dram; 224 uint32_t reserved3[16]; 225 } __packed; 226 227 #define IWX_MGMT_TID 15 228 229 #define IWX_MQ_RX_TABLE_SIZE 512 230 231 /* cb size is the exponent */ 232 #define IWX_RX_QUEUE_CB_SIZE(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1)) 233 234 /* 235 * CSR (control and status registers) 236 * 237 * CSR registers are mapped directly into PCI bus space, and are accessible 238 * whenever platform supplies power to device, even when device is in 239 * low power states due to driver-invoked device resets 240 * (e.g. IWX_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. 241 * 242 * Use iwl_write32() and iwl_read32() family to access these registers; 243 * these provide simple PCI bus access, without waking up the MAC. 244 * Do not use iwl_write_direct32() family for these registers; 245 * no need to "grab nic access" via IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. 246 * The MAC (uCode processor, etc.) does not need to be powered up for accessing 247 * the CSR registers. 248 * 249 * NOTE: Device does need to be awake in order to read this memory 250 * via IWX_CSR_EEPROM and IWX_CSR_OTP registers 251 */ 252 #define IWX_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */ 253 #define IWX_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */ 254 #define IWX_CSR_INT (0x008) /* host interrupt status/ack */ 255 #define IWX_CSR_INT_MASK (0x00c) /* host interrupt enable */ 256 #define IWX_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/ 257 #define IWX_CSR_GPIO_IN (0x018) /* read external chip pins */ 258 #define IWX_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/ 259 #define IWX_CSR_GP_CNTRL (0x024) 260 261 /* 2nd byte of IWX_CSR_INT_COALESCING, not accessible via iwl_write32()! */ 262 #define IWX_CSR_INT_PERIODIC_REG (0x005) 263 264 /* 265 * Hardware revision info 266 * Bit fields: 267 * 31-16: Reserved 268 * 15-4: Type of device: see IWX_CSR_HW_REV_TYPE_xxx definitions 269 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D 270 * 1-0: "Dash" (-) value, as in A-1, etc. 271 */ 272 #define IWX_CSR_HW_REV (0x028) 273 274 #define IWX_CSR_GIO_REG (0x03C) 275 276 /* 277 * UCODE-DRIVER GP (general purpose) mailbox registers. 278 * SET/CLR registers set/clear bit(s) if "1" is written. 279 */ 280 #define IWX_CSR_UCODE_DRV_GP1 (0x054) 281 #define IWX_CSR_UCODE_DRV_GP1_SET (0x058) 282 #define IWX_CSR_UCODE_DRV_GP1_CLR (0x05c) 283 #define IWX_CSR_UCODE_DRV_GP2 (0x060) 284 285 #define IWX_CSR_MBOX_SET_REG (0x088) 286 #define IWX_CSR_MBOX_SET_REG_OS_ALIVE 0x20 287 288 #define IWX_CSR_DRAM_INT_TBL_REG (0x0A0) 289 #define IWX_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */ 290 291 292 /* GIO Chicken Bits (PCI Express bus link power management) */ 293 #define IWX_CSR_GIO_CHICKEN_BITS (0x100) 294 295 #define IWX_CSR_DBG_HPET_MEM_REG (0x240) 296 #define IWX_CSR_DBG_LINK_PWR_MGMT_REG (0x250) 297 298 /* Bits for IWX_CSR_HW_IF_CONFIG_REG */ 299 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003) 300 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C) 301 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) 302 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) 303 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) 304 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) 305 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) 306 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) 307 308 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) 309 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) 310 #define IWX_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) 311 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) 312 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) 313 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) 314 315 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) 316 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) 317 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ 318 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ 319 #define IWX_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ 320 #define IWX_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) 321 #define IWX_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ 322 323 #define IWX_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ 324 #define IWX_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ 325 326 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), 327 * acknowledged (reset) by host writing "1" to flagged bits. */ 328 #define IWX_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ 329 #define IWX_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ 330 #define IWX_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ 331 #define IWX_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ 332 #define IWX_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ 333 #define IWX_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ 334 #define IWX_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ 335 #define IWX_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ 336 #define IWX_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ 337 #define IWX_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ 338 #define IWX_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ 339 340 #define IWX_CSR_INI_SET_MASK (IWX_CSR_INT_BIT_FH_RX | \ 341 IWX_CSR_INT_BIT_HW_ERR | \ 342 IWX_CSR_INT_BIT_FH_TX | \ 343 IWX_CSR_INT_BIT_SW_ERR | \ 344 IWX_CSR_INT_BIT_RF_KILL | \ 345 IWX_CSR_INT_BIT_SW_RX | \ 346 IWX_CSR_INT_BIT_WAKEUP | \ 347 IWX_CSR_INT_BIT_ALIVE | \ 348 IWX_CSR_INT_BIT_RX_PERIODIC) 349 350 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ 351 #define IWX_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */ 352 #define IWX_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ 353 #define IWX_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ 354 #define IWX_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ 355 #define IWX_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ 356 #define IWX_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ 357 358 #define IWX_CSR_FH_INT_RX_MASK (IWX_CSR_FH_INT_BIT_HI_PRIOR | \ 359 IWX_CSR_FH_INT_BIT_RX_CHNL1 | \ 360 IWX_CSR_FH_INT_BIT_RX_CHNL0) 361 362 #define IWX_CSR_FH_INT_TX_MASK (IWX_CSR_FH_INT_BIT_TX_CHNL1 | \ 363 IWX_CSR_FH_INT_BIT_TX_CHNL0) 364 365 /* RESET */ 366 #define IWX_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) 367 #define IWX_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) 368 #define IWX_CSR_RESET_REG_FLAG_SW_RESET (0x00000080) 369 #define IWX_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) 370 #define IWX_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) 371 #define IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) 372 373 /* 374 * GP (general purpose) CONTROL REGISTER 375 * Bit fields: 376 * 27: HW_RF_KILL_SW 377 * Indicates state of (platform's) hardware RF-Kill switch 378 * 26-24: POWER_SAVE_TYPE 379 * Indicates current power-saving mode: 380 * 000 -- No power saving 381 * 001 -- MAC power-down 382 * 010 -- PHY (radio) power-down 383 * 011 -- Error 384 * 9-6: SYS_CONFIG 385 * Indicates current system configuration, reflecting pins on chip 386 * as forced high/low by device circuit board. 387 * 4: GOING_TO_SLEEP 388 * Indicates MAC is entering a power-saving sleep power-down. 389 * Not a good time to access device-internal resources. 390 * 3: MAC_ACCESS_REQ 391 * Host sets this to request and maintain MAC wakeup, to allow host 392 * access to device-internal resources. Host must wait for 393 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR 394 * device registers. 395 * 2: INIT_DONE 396 * Host sets this to put device into fully operational D0 power mode. 397 * Host resets this after SW_RESET to put device into low power mode. 398 * 0: MAC_CLOCK_READY 399 * Indicates MAC (ucode processor, etc.) is powered up and can run. 400 * Internal resources are accessible. 401 * NOTE: This does not indicate that the processor is actually running. 402 * NOTE: This does not indicate that device has completed 403 * init or post-power-down restore of internal SRAM memory. 404 * Use IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that 405 * SRAM is restored and uCode is in normal operation mode. 406 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 407 * do not need to save/restore it. 408 * NOTE: After device reset, this bit remains "0" until host sets 409 * INIT_DONE 410 */ 411 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) 412 #define IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) 413 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) 414 #define IWX_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) 415 416 #define IWX_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) 417 418 #define IWX_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) 419 #define IWX_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) 420 #define IWX_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) 421 422 423 /* HW REV */ 424 #define IWX_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0) 425 #define IWX_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2) 426 427 #define IWX_CSR_HW_REV_TYPE_MSK (0x000FFF0) 428 429 /* CSR GIO */ 430 #define IWX_CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) 431 432 /* 433 * UCODE-DRIVER GP (general purpose) mailbox register 1 434 * Host driver and uCode write and/or read this register to communicate with 435 * each other. 436 * Bit fields: 437 * 4: UCODE_DISABLE 438 * Host sets this to request permanent halt of uCode, same as 439 * sending CARD_STATE command with "halt" bit set. 440 * 3: CT_KILL_EXIT 441 * Host sets this to request exit from CT_KILL state, i.e. host thinks 442 * device temperature is low enough to continue normal operation. 443 * 2: CMD_BLOCKED 444 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) 445 * to release uCode to clear all Tx and command queues, enter 446 * unassociated mode, and power down. 447 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. 448 * 1: SW_BIT_RFKILL 449 * Host sets this when issuing CARD_STATE command to request 450 * device sleep. 451 * 0: MAC_SLEEP 452 * uCode sets this when preparing a power-saving power-down. 453 * uCode resets this when power-up is complete and SRAM is sane. 454 * NOTE: device saves internal SRAM data to host when powering down, 455 * and must restore this data after powering back up. 456 * MAC_SLEEP is the best indication that restore is complete. 457 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and 458 * do not need to save/restore it. 459 */ 460 #define IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) 461 #define IWX_CSR_UCODE_SW_BIT_RFKILL (0x00000002) 462 #define IWX_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 463 #define IWX_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 464 #define IWX_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) 465 466 /* GIO Chicken Bits (PCI Express bus link power management) */ 467 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) 468 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) 469 470 /* HPET MEM debug */ 471 #define IWX_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) 472 473 /* DRAM INT TABLE */ 474 #define IWX_CSR_DRAM_INT_TBL_ENABLE (1U << 31) 475 #define IWX_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) 476 #define IWX_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) 477 478 /* 22000 configuration registers */ 479 480 /* 481 * TFH Configuration register. 482 * 483 * BIT fields: 484 * 485 * Bits 3:0: 486 * Define the maximum number of pending read requests. 487 * Maximum configration value allowed is 0xC 488 * Bits 9:8: 489 * Define the maximum transfer size. (64 / 128 / 256) 490 * Bit 10: 491 * When bit is set and transfer size is set to 128B, the TFH will enable 492 * reading chunks of more than 64B only if the read address is aligned to 128B. 493 * In case of DRAM read address which is not aligned to 128B, the TFH will 494 * enable transfer size which doesn't cross 64B DRAM address boundary. 495 */ 496 #define IWX_TFH_TRANSFER_MODE (0x1F40) 497 #define IWX_TFH_TRANSFER_MAX_PENDING_REQ 0xc 498 #define IWX_TFH_CHUNK_SIZE_128 (1 << 8) 499 #define IWX_TFH_CHUNK_SPLIT_MODE (1 << 10) 500 501 /* 502 * Defines the offset address in dwords referring from the beginning of the 503 * Tx CMD which will be updated in DRAM. 504 * Note that the TFH offset address for Tx CMD update is always referring to 505 * the start of the TFD first TB. 506 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID 507 */ 508 #define IWX_TFH_TXCMD_UPDATE_CFG (0x1F48) 509 510 /* 511 * Controls TX DMA operation 512 * 513 * BIT fields: 514 * 515 * Bits 31:30: Enable the SRAM DMA channel. 516 * Turning on bit 31 will kick the SRAM2DRAM DMA. 517 * Note that the sram2dram may be enabled only after configuring the DRAM and 518 * SRAM addresses registers and the byte count register. 519 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When 520 * set to 1 - interrupt is sent to the driver 521 * Bit 0: Indicates the snoop configuration 522 */ 523 #define IWX_TFH_SRV_DMA_CHNL0_CTRL (0x1F60) 524 #define IWX_TFH_SRV_DMA_SNOOP (1 << 0) 525 #define IWX_TFH_SRV_DMA_TO_DRIVER (1 << 24) 526 #define IWX_TFH_SRV_DMA_START (1U << 31) 527 528 /* Defines the DMA SRAM write start address to transfer a data block */ 529 #define IWX_TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64) 530 531 /* Defines the 64bits DRAM start address to read the DMA data block from */ 532 #define IWX_TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68) 533 534 /* 535 * Defines the number of bytes to transfer from DRAM to SRAM. 536 * Note that this register may be configured with non-dword aligned size. 537 */ 538 #define IWX_TFH_SRV_DMA_CHNL0_BC (0x1F70) 539 540 /* 9000 rx series registers */ 541 542 #define IWX_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ 543 #define IWX_RFH_Q_FRBDCB_BA_LSB(q) (IWX_RFH_Q0_FRBDCB_BA_LSB + (q) * 8) 544 /* Write index table */ 545 #define IWX_RFH_Q0_FRBDCB_WIDX 0xA08080 546 #define IWX_RFH_Q_FRBDCB_WIDX(q) (IWX_RFH_Q0_FRBDCB_WIDX + (q) * 4) 547 /* Write index table - shadow registers */ 548 #define IWX_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80 549 #define IWX_RFH_Q_FRBDCB_WIDX_TRG(q) (IWX_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4) 550 /* Read index table */ 551 #define IWX_RFH_Q0_FRBDCB_RIDX 0xA080C0 552 #define IWX_RFH_Q_FRBDCB_RIDX(q) (IWX_RFH_Q0_FRBDCB_RIDX + (q) * 4) 553 /* Used list table */ 554 #define IWX_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ 555 #define IWX_RFH_Q_URBDCB_BA_LSB(q) (IWX_RFH_Q0_URBDCB_BA_LSB + (q) * 8) 556 /* Write index table */ 557 #define IWX_RFH_Q0_URBDCB_WIDX 0xA08180 558 #define IWX_RFH_Q_URBDCB_WIDX(q) (IWX_RFH_Q0_URBDCB_WIDX + (q) * 4) 559 #define IWX_RFH_Q0_URBDCB_VAID 0xA081C0 560 #define IWX_RFH_Q_URBDCB_VAID(q) (IWX_RFH_Q0_URBDCB_VAID + (q) * 4) 561 /* stts */ 562 #define IWX_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ 563 #define IWX_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWX_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) 564 565 #define IWX_RFH_Q0_ORB_WPTR_LSB 0xA08280 566 #define IWX_RFH_Q_ORB_WPTR_LSB(q) (IWX_RFH_Q0_ORB_WPTR_LSB + (q) * 8) 567 #define IWX_RFH_RBDBUF_RBD0_LSB 0xA08300 568 #define IWX_RFH_RBDBUF_RBD_LSB(q) (IWX_RFH_RBDBUF_RBD0_LSB + (q) * 8) 569 570 /** 571 * RFH Status Register 572 * 573 * Bit fields: 574 * 575 * Bit 29: RBD_FETCH_IDLE 576 * This status flag is set by the RFH when there is no active RBD fetch from 577 * DRAM. 578 * Once the RFH RBD controller starts fetching (or when there is a pending 579 * RBD read response from DRAM), this flag is immediately turned off. 580 * 581 * Bit 30: SRAM_DMA_IDLE 582 * This status flag is set by the RFH when there is no active transaction from 583 * SRAM to DRAM. 584 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off. 585 * 586 * Bit 31: RXF_DMA_IDLE 587 * This status flag is set by the RFH when there is no active transaction from 588 * RXF to DRAM. 589 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off. 590 */ 591 #define IWX_RFH_GEN_STATUS 0xA09808 592 #define IWX_RFH_GEN_STATUS_GEN3 0xA07824 593 #define IWX_RBD_FETCH_IDLE (1 << 29) 594 #define IWX_SRAM_DMA_IDLE (1 << 30) 595 #define IWX_RXF_DMA_IDLE (1U << 31) 596 597 /* DMA configuration */ 598 #define IWX_RFH_RXF_DMA_CFG 0xA09820 599 #define IWX_RFH_RXF_DMA_CFG_GEN3 0xA07880 600 /* RB size */ 601 #define IWX_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ 602 #define IWX_RFH_RXF_DMA_RB_SIZE_POS 16 603 #define IWX_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 604 #define IWX_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 605 #define IWX_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 606 #define IWX_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 607 #define IWX_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWX_RFH_RXF_DMA_RB_SIZE_POS) 608 #define IWX_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWX_RFH_RXF_DMA_RB_SIZE_POS) 609 #define IWX_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWX_RFH_RXF_DMA_RB_SIZE_POS) 610 #define IWX_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWX_RFH_RXF_DMA_RB_SIZE_POS) 611 #define IWX_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWX_RFH_RXF_DMA_RB_SIZE_POS) 612 #define IWX_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWX_RFH_RXF_DMA_RB_SIZE_POS) 613 /* RB Circular Buffer size:defines the table sizes in RBD units */ 614 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ 615 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_POS 20 616 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 617 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 618 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 619 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 620 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 621 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 622 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 623 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 624 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS) 625 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ 626 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS 24 627 #define IWX_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS) 628 #define IWX_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ 629 #define IWX_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ 630 #define IWX_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ 631 #define IWX_RFH_DMA_EN_ENABLE_VAL (1U << 31) 632 633 #define IWX_RFH_RXF_RXQ_ACTIVE 0xA0980C 634 635 #define IWX_RFH_GEN_CFG 0xA09800 636 #define IWX_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0) 637 #define IWX_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1) 638 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010 639 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000 640 /* the driver assumes everywhere that the default RXQ is 0 */ 641 #define IWX_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00 642 643 /* end of 9000 rx series registers */ 644 645 /* 646 * This register is writen by driver and is read by uCode during boot flow. 647 * Note this address is cleared after MAC reset. 648 */ 649 #define IWX_UREG_UCODE_LOAD_STATUS (0xa05c40) 650 #define IWX_UREG_CPU_INIT_RUN (0xa05c44) 651 652 /* 653 * HBUS (Host-side Bus) 654 * 655 * HBUS registers are mapped directly into PCI bus space, but are used 656 * to indirectly access device's internal memory or registers that 657 * may be powered-down. 658 * 659 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; 660 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ 661 * to make sure the MAC (uCode processor, etc.) is powered up for accessing 662 * internal resources. 663 * 664 * Do not use iwl_write32()/iwl_read32() family to access these registers; 665 * these provide only simple PCI bus access, without waking up the MAC. 666 */ 667 #define IWX_HBUS_BASE (0x400) 668 669 /* 670 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM 671 * structures, error log, event log, verifying uCode load). 672 * First write to address register, then read from or write to data register 673 * to complete the job. Once the address register is set up, accesses to 674 * data registers auto-increment the address by one dword. 675 * Bit usage for address registers (read or write): 676 * 0-31: memory address within device 677 */ 678 #define IWX_HBUS_TARG_MEM_RADDR (IWX_HBUS_BASE+0x00c) 679 #define IWX_HBUS_TARG_MEM_WADDR (IWX_HBUS_BASE+0x010) 680 #define IWX_HBUS_TARG_MEM_WDAT (IWX_HBUS_BASE+0x018) 681 #define IWX_HBUS_TARG_MEM_RDAT (IWX_HBUS_BASE+0x01c) 682 683 /* 684 * Registers for accessing device's internal peripheral registers 685 * (e.g. SCD, BSM, etc.). First write to address register, 686 * then read from or write to data register to complete the job. 687 * Bit usage for address registers (read or write): 688 * 0-15: register address (offset) within device 689 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) 690 */ 691 #define IWX_HBUS_TARG_PRPH_WADDR (IWX_HBUS_BASE+0x044) 692 #define IWX_HBUS_TARG_PRPH_RADDR (IWX_HBUS_BASE+0x048) 693 #define IWX_HBUS_TARG_PRPH_WDAT (IWX_HBUS_BASE+0x04c) 694 #define IWX_HBUS_TARG_PRPH_RDAT (IWX_HBUS_BASE+0x050) 695 696 /* enable the ID buf for read */ 697 #define IWX_WFPM_PS_CTL_CLR 0xa0300c 698 #define IWX_WFMP_MAC_ADDR_0 0xa03080 699 #define IWX_WFMP_MAC_ADDR_1 0xa03084 700 #define IWX_LMPM_PMG_EN 0xa01cec 701 #define IWX_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078 702 #define IWX_RFIC_REG_RD 0xad0470 703 #define IWX_WFPM_CTRL_REG 0xa03030 704 #define IWX_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000 705 #define IWX_ENABLE_WFPM 0x80000000 706 707 #define IWX_AUX_MISC_REG 0xa200b0 708 #define IWX_HW_STEP_LOCATION_BITS 24 709 710 #define IWX_AUX_MISC_MASTER1_EN 0xa20818 711 #define IWX_AUX_MISC_MASTER1_EN_SBE_MSK 0x1 712 #define IWX_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800 713 #define IWX_RSA_ENABLE 0xa24b08 714 #define IWX_PREG_AUX_BUS_WPROT_0 0xa04cc0 715 #define IWX_PREG_PRPH_WPROT_9000 0xa04ce0 716 #define IWX_PREG_PRPH_WPROT_22000 0xa04d00 717 #define IWX_SB_CFG_OVERRIDE_ADDR 0xa26c78 718 #define IWX_SB_CFG_OVERRIDE_ENABLE 0x8000 719 #define IWX_SB_CFG_BASE_OVERRIDE 0xa20000 720 #define IWX_SB_MODIFY_CFG_FLAG 0xa03088 721 #define IWX_UMAG_SB_CPU_1_STATUS 0xa038c0 722 #define IWX_UMAG_SB_CPU_2_STATUS 0xa038c4 723 724 #define IWX_UREG_CHICK 0xa05c00 725 #define IWX_UREG_CHICK_MSI_ENABLE (1 << 24) 726 #define IWX_UREG_CHICK_MSIX_ENABLE (1 << 25) 727 728 #define IWX_HPM_DEBUG 0xa03440 729 #define IWX_PERSISTENCE_BIT (1 << 12) 730 #define IWX_PREG_WFPM_ACCESS (1 << 12) 731 732 #define IWX_HPM_HIPM_GEN_CFG 0xa03458 733 #define IWX_HPM_HIPM_GEN_CFG_CR_PG_EN (1 << 0) 734 #define IWX_HPM_HIPM_GEN_CFG_CR_SLP_EN (1 << 1) 735 #define IWX_HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE (1 << 10) 736 737 /* 738 * Per-Tx-queue write pointer (index, really!) 739 * Indicates index to next TFD that driver will fill (1 past latest filled). 740 * Bit usage: 741 * 0-7: queue write index 742 * 11-8: queue selector 743 */ 744 #define IWX_HBUS_TARG_WRPTR (IWX_HBUS_BASE+0x060) 745 746 /********************************************************** 747 * CSR values 748 **********************************************************/ 749 /* 750 * host interrupt timeout value 751 * used with setting interrupt coalescing timer 752 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 753 * 754 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 755 */ 756 #define IWX_HOST_INT_TIMEOUT_MAX (0xFF) 757 #define IWX_HOST_INT_TIMEOUT_DEF (0x40) 758 #define IWX_HOST_INT_TIMEOUT_MIN (0x0) 759 #define IWX_HOST_INT_OPER_MODE (1U << 31) 760 761 /***************************************************************************** 762 * MSIX related registers * 763 *****************************************************************************/ 764 765 #define IWX_CSR_MSIX_BASE (0x2000) 766 #define IWX_CSR_MSIX_FH_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x800) 767 #define IWX_CSR_MSIX_FH_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x804) 768 #define IWX_CSR_MSIX_HW_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x808) 769 #define IWX_CSR_MSIX_HW_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x80C) 770 #define IWX_CSR_MSIX_AUTOMASK_ST_AD (IWX_CSR_MSIX_BASE + 0x810) 771 #define IWX_CSR_MSIX_RX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x880) 772 #define IWX_CSR_MSIX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x890) 773 #define IWX_CSR_MSIX_PENDING_PBA_AD (IWX_CSR_MSIX_BASE + 0x1000) 774 #define IWX_CSR_MSIX_RX_IVAR(cause) (IWX_CSR_MSIX_RX_IVAR_AD_REG + (cause)) 775 #define IWX_CSR_MSIX_IVAR(cause) (IWX_CSR_MSIX_IVAR_AD_REG + (cause)) 776 777 /* 778 * Causes for the FH register interrupts 779 */ 780 enum msix_fh_int_causes { 781 IWX_MSIX_FH_INT_CAUSES_Q0 = (1 << 0), 782 IWX_MSIX_FH_INT_CAUSES_Q1 = (1 << 1), 783 IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16), 784 IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17), 785 IWX_MSIX_FH_INT_CAUSES_S2D = (1 << 19), 786 IWX_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21), 787 }; 788 789 /* 790 * Causes for the HW register interrupts 791 */ 792 enum msix_hw_int_causes { 793 IWX_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0), 794 IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1), 795 IWX_MSIX_HW_INT_CAUSES_REG_IPC = (1 << 1), 796 IWX_MSIX_HW_INT_CAUSES_REG_IML = (1 << 2), 797 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5), 798 IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6), 799 IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7), 800 IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8), 801 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25), 802 IWX_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26), 803 IWX_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27), 804 IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29), 805 IWX_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30), 806 }; 807 808 /* 809 * Registers to map causes to vectors 810 */ 811 enum msix_ivar_for_cause { 812 IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0, 813 IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1, 814 IWX_MSIX_IVAR_CAUSE_S2D = 0x3, 815 IWX_MSIX_IVAR_CAUSE_FH_ERR = 0x5, 816 IWX_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10, 817 IWX_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11, 818 IWX_MSIX_IVAR_CAUSE_REG_IML = 0x12, 819 IWX_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16, 820 IWX_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17, 821 IWX_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18, 822 IWX_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29, 823 IWX_MSIX_IVAR_CAUSE_REG_SCD = 0x2a, 824 IWX_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b, 825 IWX_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d, 826 IWX_MSIX_IVAR_CAUSE_REG_HAP = 0x2e, 827 }; 828 829 #define IWX_MSIX_AUTO_CLEAR_CAUSE (0 << 7) 830 #define IWX_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7) 831 832 /** 833 * uCode API flags 834 * @IWX_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously 835 * was a separate TLV but moved here to save space. 836 * @IWX_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, 837 * treats good CRC threshold as a boolean 838 * @IWX_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). 839 * @IWX_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. 840 * @IWX_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS 841 * @IWX_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD 842 * @IWX_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan 843 * offload profile config command. 844 * @IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six 845 * (rather than two) IPv6 addresses 846 * @IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element 847 * from the probe request template. 848 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) 849 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) 850 * @IWX_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a 851 * single bound interface). 852 * @IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD 853 * @IWX_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. 854 * @IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save 855 * @IWX_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. 856 * @IWX_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients 857 * 858 */ 859 #define IWX_UCODE_TLV_FLAGS_PAN (1 << 0) 860 #define IWX_UCODE_TLV_FLAGS_NEWSCAN (1 << 1) 861 #define IWX_UCODE_TLV_FLAGS_MFP (1 << 2) 862 #define IWX_UCODE_TLV_FLAGS_P2P (1 << 3) 863 #define IWX_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4) 864 #define IWX_UCODE_TLV_FLAGS_SHORT_BL (1 << 7) 865 #define IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10) 866 #define IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12) 867 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15) 868 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16) 869 #define IWX_UCODE_TLV_FLAGS_P2P_PS (1 << 21) 870 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22) 871 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23) 872 #define IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24) 873 #define IWX_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25) 874 #define IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26) 875 #define IWX_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29) 876 #define IWX_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30) 877 #define IWX_UCODE_TLV_FLAGS_LTE_COEX (1U << 31) 878 879 #define IWX_UCODE_TLV_FLAG_BITS \ 880 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX" 881 882 /** 883 * uCode TLV api 884 * @IWX_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time 885 * longer than the passive one, which is essential for fragmented scan. 886 * @IWX_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. 887 * @IWX_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header 888 * @IWX_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params 889 * @IWX_UCODE_TLV_API_NEW_VERSION: new versioning format 890 * @IWX_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size 891 * (command version 3) that supports per-chain limits 892 * @IWX_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan 893 * iteration complete notification, and the timestamp reported for RX 894 * received during scan, are reported in TSF of the mac specified in the 895 * scan request. 896 * @IWX_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of 897 * ADD_MODIFY_STA_KEY_API_S_VER_2. 898 * @IWX_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement. 899 * @IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority 900 * instead of 3. 901 * @IWX_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used 902 * @IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG: This ucode supports v3 of 903 * SCAN_CONFIG_DB_CMD_API_S. 904 * 905 * @IWX_NUM_UCODE_TLV_API: number of bits used 906 */ 907 #define IWX_UCODE_TLV_API_FRAGMENTED_SCAN 8 908 #define IWX_UCODE_TLV_API_WIFI_MCC_UPDATE 9 909 #define IWX_UCODE_TLV_API_WIDE_CMD_HDR 14 910 #define IWX_UCODE_TLV_API_LQ_SS_PARAMS 18 911 #define IWX_UCODE_TLV_API_NEW_VERSION 20 912 #define IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY 24 913 #define IWX_UCODE_TLV_API_TX_POWER_CHAIN 27 914 #define IWX_UCODE_TLV_API_SCAN_TSF_REPORT 28 915 #define IWX_UCODE_TLV_API_TKIP_MIC_KEYS 29 916 #define IWX_UCODE_TLV_API_STA_TYPE 30 917 #define IWX_UCODE_TLV_API_NAN2_VER2 31 918 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL 32 919 #define IWX_UCODE_TLV_API_NEW_RX_STATS 35 920 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42 921 #define IWX_UCODE_TLV_API_BEACON_FILTER_V4 47 922 #define IWX_UCODE_TLV_API_REGULATORY_NVM_INFO 48 923 #define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56 924 #define IWX_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58 925 #define IWX_NUM_UCODE_TLV_API 128 926 927 #define IWX_UCODE_TLV_API_BITS \ 928 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS" 929 930 /** 931 * uCode capabilities 932 * @IWX_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 933 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory 934 * @IWX_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. 935 * @IWX_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer 936 * @IWX_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) 937 * @IWX_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality 938 * @IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current 939 * tx power value into TPC Report action frame and Link Measurement Report 940 * action frame 941 * @IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current 942 * channel in DS parameter set element in probe requests. 943 * @IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in 944 * probe requests. 945 * @IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests 946 * @IWX_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), 947 * which also implies support for the scheduler configuration command 948 * @IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching 949 * @IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image 950 * @IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command 951 * @IWX_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command 952 * @IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command 953 * @IWX_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload 954 * @IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics 955 * @IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD 956 * @IWX_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running 957 * @IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different 958 * sources for the MCC. This TLV bit is a future replacement to 959 * IWX_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR 960 * is supported. 961 * @IWX_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC 962 * @IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan 963 * @IWX_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN 964 * @IWX_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 965 * 0=no support) 966 * @IWx_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS: firmware supports ultra high band 967 * (6 GHz). 968 * @IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement 969 * @IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts 970 * @IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT 971 * @IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what 972 * antenna the beacon should be transmitted 973 * @IWX_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon 974 * from AP and will send it upon d0i3 exit. 975 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 976 * @IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill 977 * @IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature 978 * thresholds reporting 979 * @IWX_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command 980 * @IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in 981 * regular image. 982 * @IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared 983 * memory addresses from the firmware. 984 * @IWX_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement 985 * @IWX_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 986 * 0=no support) 987 * 988 * @IWX_NUM_UCODE_TLV_CAPA: number of bits used 989 */ 990 #define IWX_UCODE_TLV_CAPA_D0I3_SUPPORT 0 991 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT 1 992 #define IWX_UCODE_TLV_CAPA_UMAC_SCAN 2 993 #define IWX_UCODE_TLV_CAPA_BEAMFORMER 3 994 #define IWX_UCODE_TLV_CAPA_TOF_SUPPORT 5 995 #define IWX_UCODE_TLV_CAPA_TDLS_SUPPORT 6 996 #define IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8 997 #define IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9 998 #define IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10 999 #define IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11 1000 #define IWX_UCODE_TLV_CAPA_DQA_SUPPORT 12 1001 #define IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13 1002 #define IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17 1003 #define IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18 1004 #define IWX_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19 1005 #define IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20 1006 #define IWX_UCODE_TLV_CAPA_CSUM_SUPPORT 21 1007 #define IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22 1008 #define IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26 1009 #define IWX_UCODE_TLV_CAPA_BT_COEX_PLCR 28 1010 #define IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC 29 1011 #define IWX_UCODE_TLV_CAPA_BT_COEX_RRC 30 1012 #define IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT 31 1013 #define IWX_UCODE_TLV_CAPA_NAN_SUPPORT 34 1014 #define IWX_UCODE_TLV_CAPA_UMAC_UPLOAD 35 1015 #define IWX_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39 1016 #define IWX_UCODE_TLV_CAPA_CDB_SUPPORT 40 1017 #define IWX_UCODE_TLV_CAPA_TLC_OFFLOAD 43 1018 #define IWX_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44 1019 #define IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48 1020 #define IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64 1021 #define IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65 1022 #define IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67 1023 #define IWX_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68 1024 #define IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71 1025 #define IWX_UCODE_TLV_CAPA_BEACON_STORING 72 1026 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73 1027 #define IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW 74 1028 #define IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75 1029 #define IWX_UCODE_TLV_CAPA_CTDP_SUPPORT 76 1030 #define IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77 1031 #define IWX_UCODE_TLV_CAPA_LMAC_UPLOAD 79 1032 #define IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80 1033 #define IWX_UCODE_TLV_CAPA_LQM_SUPPORT 81 1034 #define IWX_UCODE_TLV_CAPA_LED_CMD_SUPPORT 88 1035 1036 #define IWX_NUM_UCODE_TLV_CAPA 128 1037 1038 /* 1039 * For 16.0 uCode and above, there is no differentiation between sections, 1040 * just an offset to the HW address. 1041 */ 1042 #define IWX_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC 1043 #define IWX_PAGING_SEPARATOR_SECTION 0xAAAABBBB 1044 1045 /* uCode version contains 4 values: Major/Minor/API/Serial */ 1046 #define IWX_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24) 1047 #define IWX_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16) 1048 #define IWX_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8) 1049 #define IWX_UCODE_SERIAL(ver) ((ver) & 0x000000FF) 1050 1051 /* 1052 * Calibration control struct. 1053 * Sent as part of the phy configuration command. 1054 * @flow_trigger: bitmap for which calibrations to perform according to 1055 * flow triggers. 1056 * @event_trigger: bitmap for which calibrations to perform according to 1057 * event triggers. 1058 */ 1059 struct iwx_tlv_calib_ctrl { 1060 uint32_t flow_trigger; 1061 uint32_t event_trigger; 1062 } __packed; 1063 1064 #define IWX_FW_PHY_CFG_RADIO_TYPE_POS 0 1065 #define IWX_FW_PHY_CFG_RADIO_TYPE (0x3 << IWX_FW_PHY_CFG_RADIO_TYPE_POS) 1066 #define IWX_FW_PHY_CFG_RADIO_STEP_POS 2 1067 #define IWX_FW_PHY_CFG_RADIO_STEP (0x3 << IWX_FW_PHY_CFG_RADIO_STEP_POS) 1068 #define IWX_FW_PHY_CFG_RADIO_DASH_POS 4 1069 #define IWX_FW_PHY_CFG_RADIO_DASH (0x3 << IWX_FW_PHY_CFG_RADIO_DASH_POS) 1070 #define IWX_FW_PHY_CFG_TX_CHAIN_POS 16 1071 #define IWX_FW_PHY_CFG_TX_CHAIN (0xf << IWX_FW_PHY_CFG_TX_CHAIN_POS) 1072 #define IWX_FW_PHY_CFG_RX_CHAIN_POS 20 1073 #define IWX_FW_PHY_CFG_RX_CHAIN (0xf << IWX_FW_PHY_CFG_RX_CHAIN_POS) 1074 1075 /** 1076 * struct iwx_fw_cipher_scheme - a cipher scheme supported by FW. 1077 * @cipher: a cipher suite selector 1078 * @flags: cipher scheme flags (currently reserved for a future use) 1079 * @hdr_len: a size of MPDU security header 1080 * @pn_len: a size of PN 1081 * @pn_off: an offset of pn from the beginning of the security header 1082 * @key_idx_off: an offset of key index byte in the security header 1083 * @key_idx_mask: a bit mask of key_idx bits 1084 * @key_idx_shift: bit shift needed to get key_idx 1085 * @mic_len: mic length in bytes 1086 * @hw_cipher: a HW cipher index used in host commands 1087 */ 1088 struct iwx_fw_cipher_scheme { 1089 uint32_t cipher; 1090 uint8_t flags; 1091 uint8_t hdr_len; 1092 uint8_t pn_len; 1093 uint8_t pn_off; 1094 uint8_t key_idx_off; 1095 uint8_t key_idx_mask; 1096 uint8_t key_idx_shift; 1097 uint8_t mic_len; 1098 uint8_t hw_cipher; 1099 } __packed; 1100 1101 /** 1102 * struct iwx_fw_cscheme_list - a cipher scheme list 1103 * @size: a number of entries 1104 * @cs: cipher scheme entries 1105 */ 1106 struct iwx_fw_cscheme_list { 1107 uint8_t size; 1108 struct iwx_fw_cipher_scheme cs[]; 1109 } __packed; 1110 1111 /* v1/v2 uCode file layout */ 1112 struct iwx_ucode_header { 1113 uint32_t ver; /* major/minor/API/serial */ 1114 union { 1115 struct { 1116 uint32_t inst_size; /* bytes of runtime code */ 1117 uint32_t data_size; /* bytes of runtime data */ 1118 uint32_t init_size; /* bytes of init code */ 1119 uint32_t init_data_size; /* bytes of init data */ 1120 uint32_t boot_size; /* bytes of bootstrap code */ 1121 uint8_t data[0]; /* in same order as sizes */ 1122 } v1; 1123 struct { 1124 uint32_t build; /* build number */ 1125 uint32_t inst_size; /* bytes of runtime code */ 1126 uint32_t data_size; /* bytes of runtime data */ 1127 uint32_t init_size; /* bytes of init code */ 1128 uint32_t init_data_size; /* bytes of init data */ 1129 uint32_t boot_size; /* bytes of bootstrap code */ 1130 uint8_t data[0]; /* in same order as sizes */ 1131 } v2; 1132 } u; 1133 }; 1134 1135 /* 1136 * new TLV uCode file layout 1137 * 1138 * The new TLV file format contains TLVs, that each specify 1139 * some piece of data. 1140 */ 1141 1142 #define IWX_UCODE_TLV_INVALID 0 /* unused */ 1143 #define IWX_UCODE_TLV_INST 1 1144 #define IWX_UCODE_TLV_DATA 2 1145 #define IWX_UCODE_TLV_INIT 3 1146 #define IWX_UCODE_TLV_INIT_DATA 4 1147 #define IWX_UCODE_TLV_BOOT 5 1148 #define IWX_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */ 1149 #define IWX_UCODE_TLV_PAN 7 1150 #define IWX_UCODE_TLV_RUNT_EVTLOG_PTR 8 1151 #define IWX_UCODE_TLV_RUNT_EVTLOG_SIZE 9 1152 #define IWX_UCODE_TLV_RUNT_ERRLOG_PTR 10 1153 #define IWX_UCODE_TLV_INIT_EVTLOG_PTR 11 1154 #define IWX_UCODE_TLV_INIT_EVTLOG_SIZE 12 1155 #define IWX_UCODE_TLV_INIT_ERRLOG_PTR 13 1156 #define IWX_UCODE_TLV_ENHANCE_SENS_TBL 14 1157 #define IWX_UCODE_TLV_PHY_CALIBRATION_SIZE 15 1158 #define IWX_UCODE_TLV_WOWLAN_INST 16 1159 #define IWX_UCODE_TLV_WOWLAN_DATA 17 1160 #define IWX_UCODE_TLV_FLAGS 18 1161 #define IWX_UCODE_TLV_SEC_RT 19 1162 #define IWX_UCODE_TLV_SEC_INIT 20 1163 #define IWX_UCODE_TLV_SEC_WOWLAN 21 1164 #define IWX_UCODE_TLV_DEF_CALIB 22 1165 #define IWX_UCODE_TLV_PHY_SKU 23 1166 #define IWX_UCODE_TLV_SECURE_SEC_RT 24 1167 #define IWX_UCODE_TLV_SECURE_SEC_INIT 25 1168 #define IWX_UCODE_TLV_SECURE_SEC_WOWLAN 26 1169 #define IWX_UCODE_TLV_NUM_OF_CPU 27 1170 #define IWX_UCODE_TLV_CSCHEME 28 1171 #define IWX_UCODE_TLV_API_CHANGES_SET 29 1172 #define IWX_UCODE_TLV_ENABLED_CAPABILITIES 30 1173 #define IWX_UCODE_TLV_N_SCAN_CHANNELS 31 1174 #define IWX_UCODE_TLV_PAGING 32 1175 #define IWX_UCODE_TLV_SEC_RT_USNIFFER 34 1176 #define IWX_UCODE_TLV_SDIO_ADMA_ADDR 35 1177 #define IWX_UCODE_TLV_FW_VERSION 36 1178 #define IWX_UCODE_TLV_FW_DBG_DEST 38 1179 #define IWX_UCODE_TLV_FW_DBG_CONF 39 1180 #define IWX_UCODE_TLV_FW_DBG_TRIGGER 40 1181 #define IWX_UCODE_TLV_CMD_VERSIONS 48 1182 #define IWX_UCODE_TLV_FW_GSCAN_CAPA 50 1183 #define IWX_UCODE_TLV_FW_MEM_SEG 51 1184 #define IWX_UCODE_TLV_IML 52 1185 #define IWX_UCODE_TLV_FW_FMAC_API_VERSION 53 1186 #define IWX_UCODE_TLV_UMAC_DEBUG_ADDRS 54 1187 #define IWX_UCODE_TLV_LMAC_DEBUG_ADDRS 55 1188 #define IWX_UCODE_TLV_FW_RECOVERY_INFO 57 1189 #define IWX_UCODE_TLV_FW_FMAC_RECOVERY_INFO 59 1190 #define IWX_UCODE_TLV_FW_FSEQ_VERSION 60 1191 1192 #define IWX_UCODE_TLV_DEBUG_BASE 0x1000005 1193 #define IWX_UCODE_TLV_TYPE_DEBUG_INFO (IWX_UCODE_TLV_DEBUG_BASE + 0) 1194 #define IWX_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWX_UCODE_TLV_DEBUG_BASE + 1) 1195 #define IWX_UCODE_TLV_TYPE_HCMD (IWX_UCODE_TLV_DEBUG_BASE + 2) 1196 #define IWX_UCODE_TLV_TYPE_REGIONS (IWX_UCODE_TLV_DEBUG_BASE + 3) 1197 #define IWX_UCODE_TLV_TYPE_TRIGGERS (IWX_UCODE_TLV_DEBUG_BASE + 4) 1198 #define IWX_UCODE_TLV_DEBUG_MAX IWX_UCODE_TLV_TYPE_TRIGGERS 1199 1200 1201 struct iwx_ucode_tlv { 1202 uint32_t type; /* see above */ 1203 uint32_t length; /* not including type/length fields */ 1204 uint8_t data[0]; 1205 }; 1206 1207 struct iwx_ucode_api { 1208 uint32_t api_index; 1209 uint32_t api_flags; 1210 } __packed; 1211 1212 struct iwx_ucode_capa { 1213 uint32_t api_index; 1214 uint32_t api_capa; 1215 } __packed; 1216 1217 #define IWX_TLV_UCODE_MAGIC 0x0a4c5749 1218 1219 struct iwx_tlv_ucode_header { 1220 /* 1221 * The TLV style ucode header is distinguished from 1222 * the v1/v2 style header by first four bytes being 1223 * zero, as such is an invalid combination of 1224 * major/minor/API/serial versions. 1225 */ 1226 uint32_t zero; 1227 uint32_t magic; 1228 uint8_t human_readable[64]; 1229 uint32_t ver; /* major/minor/API/serial */ 1230 uint32_t build; 1231 uint64_t ignore; 1232 /* 1233 * The data contained herein has a TLV layout, 1234 * see above for the TLV header and types. 1235 * Note that each TLV is padded to a length 1236 * that is a multiple of 4 for alignment. 1237 */ 1238 uint8_t data[0]; 1239 }; 1240 1241 /* 1242 * Registers in this file are internal, not PCI bus memory mapped. 1243 * Driver accesses these via IWX_HBUS_TARG_PRPH_* registers. 1244 */ 1245 #define IWX_PRPH_BASE (0x00000) 1246 #define IWX_PRPH_END (0xFFFFF) 1247 1248 /****************************/ 1249 /* Flow Handler Definitions */ 1250 /****************************/ 1251 1252 /** 1253 * struct iwx_rb_status - receive buffer status 1254 * host memory mapped FH registers 1255 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 1256 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 1257 * @finished_rb_num [0:11] - Indicates the index of the current RB 1258 * in which the last frame was written to 1259 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 1260 * which was transferred 1261 */ 1262 struct iwx_rb_status { 1263 uint16_t closed_rb_num; 1264 uint16_t closed_fr_num; 1265 uint16_t finished_rb_num; 1266 uint16_t finished_fr_nam; 1267 uint32_t unused; 1268 } __packed; 1269 1270 1271 #define IWX_TFD_QUEUE_SIZE_MAX (256) 1272 #define IWX_TFD_QUEUE_SIZE_MAX_GEN3 (65536) 1273 /* cb size is the exponent - 3 */ 1274 #define IWX_TFD_QUEUE_CB_SIZE(x) (IWX_RX_QUEUE_CB_SIZE(x) - 3) 1275 #define IWX_TFD_QUEUE_SIZE_BC_DUP (64) 1276 #define IWX_TFD_QUEUE_BC_SIZE (IWX_TFD_QUEUE_SIZE_MAX + \ 1277 IWX_TFD_QUEUE_SIZE_BC_DUP) 1278 #define IWX_TFD_QUEUE_BC_SIZE_GEN3 (IWX_TFD_QUEUE_SIZE_MAX_GEN3 + \ 1279 IWX_TFD_QUEUE_SIZE_BC_DUP) 1280 #define IWX_TFH_NUM_TBS 25 1281 1282 /** 1283 * struct iwx_tfh_tb transmit buffer descriptor within transmit frame descriptor 1284 * 1285 * This structure contains dma address and length of transmission address 1286 * 1287 * @tb_len length of the tx buffer 1288 * @addr 64 bits dma address 1289 */ 1290 struct iwx_tfh_tb { 1291 uint16_t tb_len; 1292 uint64_t addr; 1293 } __packed; 1294 1295 /** 1296 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 1297 * Both driver and device share these circular buffers, each of which must be 1298 * contiguous 256 TFDs. 1299 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes 1300 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes 1301 * 1302 * Each TFD contains pointer/size information for up to 25 data buffers 1303 * in host DRAM. These buffers collectively contain the (one) frame described 1304 * by the TFD. Each buffer must be a single contiguous block of memory within 1305 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 1306 * of (4K - 4). The concatenates all of a TFD's buffers into a single 1307 * Tx frame, up to 8 KBytes in size. 1308 * 1309 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 1310 */ 1311 1312 /** 1313 * struct iwx_tfh_tfd - Transmit Frame Descriptor (TFD) 1314 * @ num_tbs 0-4 number of active tbs 1315 * 5 -15 reserved 1316 * @ tbs[25] transmit frame buffer descriptors 1317 * @ __pad padding 1318 */ 1319 struct iwx_tfh_tfd { 1320 uint16_t num_tbs; 1321 struct iwx_tfh_tb tbs[IWX_TFH_NUM_TBS]; 1322 uint32_t __pad; 1323 } __packed; 1324 1325 /* Fixed (non-configurable) rx data from phy */ 1326 1327 /** 1328 * struct iwx_agn_schedq_bc_tbl scheduler byte count table 1329 * base physical address provided by IWX_SCD_DRAM_BASE_ADDR 1330 * @tfd_offset 0-12 - tx command byte count 1331 * 12-16 - station index 1332 */ 1333 struct iwx_agn_scd_bc_tbl { 1334 uint16_t tfd_offset[IWX_TFD_QUEUE_BC_SIZE]; 1335 } __packed; 1336 1337 /** 1338 * struct iwx_gen3_bc_tbl scheduler byte count table gen3 1339 * For 22560 and on: 1340 * @tfd_offset: 0-12 - tx command byte count 1341 * 12-13 - number of 64 byte chunks 1342 * 14-16 - reserved 1343 */ 1344 struct iwx_gen3_bc_tbl { 1345 uint16_t tfd_offset[IWX_TFD_QUEUE_BC_SIZE_GEN3]; 1346 } __packed; 1347 1348 /* Maximum number of Tx queues. */ 1349 #define IWX_MAX_QUEUES 31 1350 1351 /** 1352 * DQA - Dynamic Queue Allocation -introduction 1353 * 1354 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi 1355 * to allow dynamic allocation of queues on-demand, rather than allocate them 1356 * statically ahead of time. Ideally, we would like to allocate one queue 1357 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2 1358 * even if it also needs to send traffic to a sleeping STA1, without being 1359 * blocked by the sleeping station. 1360 * 1361 * Although the queues in DQA mode are dynamically allocated, there are still 1362 * some queues that are statically allocated: 1363 * TXQ #0 - command queue 1364 * TXQ #1 - aux frames 1365 * TXQ #2 - P2P device frames 1366 * TXQ #3 - P2P GO/SoftAP GCAST/BCAST frames 1367 * TXQ #4 - BSS DATA frames queue 1368 * TXQ #5-8 - non-QoS data, QoS no-data, and MGMT frames queue pool 1369 * TXQ #9 - P2P GO/SoftAP probe responses 1370 * TXQ #10-31 - QoS DATA frames queue pool (for Tx aggregation) 1371 */ 1372 1373 /* static DQA Tx queue numbers */ 1374 #define IWX_DQA_CMD_QUEUE 0 1375 #define IWX_DQA_AUX_QUEUE 1 1376 #define IWX_DQA_P2P_DEVICE_QUEUE 2 1377 #define IWX_DQA_INJECT_MONITOR_QUEUE 2 1378 #define IWX_DQA_GCAST_QUEUE 3 1379 #define IWX_DQA_BSS_CLIENT_QUEUE 4 1380 #define IWX_DQA_MIN_MGMT_QUEUE 5 1381 #define IWX_DQA_MAX_MGMT_QUEUE 8 1382 #define IWX_DQA_AP_PROBE_RESP_QUEUE 9 1383 #define IWX_DQA_MIN_DATA_QUEUE 10 1384 #define IWX_DQA_MAX_DATA_QUEUE 31 1385 1386 #define IWX_TX_FIFO_BK 0 1387 #define IWX_TX_FIFO_BE 1 1388 #define IWX_TX_FIFO_VI 2 1389 #define IWX_TX_FIFO_VO 3 1390 #define IWX_TX_FIFO_MCAST 5 1391 #define IWX_TX_FIFO_CMD 7 1392 1393 enum iwx_gen2_tx_fifo { 1394 IWX_GEN2_TX_FIFO_CMD = 0, 1395 IWX_GEN2_EDCA_TX_FIFO_BK, 1396 IWX_GEN2_EDCA_TX_FIFO_BE, 1397 IWX_GEN2_EDCA_TX_FIFO_VI, 1398 IWX_GEN2_EDCA_TX_FIFO_VO, 1399 IWX_GEN2_TRIG_TX_FIFO_BK, 1400 IWX_GEN2_TRIG_TX_FIFO_BE, 1401 IWX_GEN2_TRIG_TX_FIFO_VI, 1402 IWX_GEN2_TRIG_TX_FIFO_VO, 1403 }; 1404 1405 /** 1406 * TXQ config options 1407 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue 1408 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format 1409 */ 1410 #define IWX_TX_QUEUE_CFG_ENABLE_QUEUE (1 << 0) 1411 #define IWX_TX_QUEUE_CFG_TFD_SHORT_FORMAT (1 << 1) 1412 1413 #define IWX_DEFAULT_QUEUE_SIZE IWX_TFD_QUEUE_SIZE_MAX 1414 1415 /** 1416 * struct iwx_tx_queue_cfg_cmd - txq hw scheduler config command 1417 * @sta_id: station id 1418 * @tid: tid of the queue 1419 * @flags: see &enum iwl_tx_queue_cfg_actions 1420 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3. 1421 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs) 1422 * @byte_cnt_addr: address of byte count table 1423 * @tfdq_addr: address of TFD circular buffer 1424 */ 1425 struct iwx_tx_queue_cfg_cmd { 1426 uint8_t sta_id; 1427 uint8_t tid; 1428 uint16_t flags; 1429 uint32_t cb_size; 1430 uint64_t byte_cnt_addr; 1431 uint64_t tfdq_addr; 1432 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */ 1433 1434 /** 1435 * struct iwx_tx_queue_cfg_rsp - response to txq hw scheduler config 1436 * @queue_number: queue number assigned to this RA -TID 1437 * @flags: set on failure 1438 * @write_pointer: initial value for write pointer 1439 * @reserved: reserved 1440 */ 1441 struct iwx_tx_queue_cfg_rsp { 1442 uint16_t queue_number; 1443 uint16_t flags; 1444 uint16_t write_pointer; 1445 uint16_t reserved; 1446 } __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */ 1447 1448 1449 /* 1450 * Commands 1451 */ 1452 #define IWX_ALIVE 0x1 1453 #define IWX_REPLY_ERROR 0x2 1454 #define IWX_INIT_COMPLETE_NOTIF 0x4 1455 1456 /* PHY context commands */ 1457 #define IWX_PHY_CONTEXT_CMD 0x8 1458 #define IWX_DBG_CFG 0x9 1459 1460 /* UMAC scan commands */ 1461 #define IWX_SCAN_ITERATION_COMPLETE_UMAC 0xb5 1462 #define IWX_SCAN_CFG_CMD 0xc 1463 #define IWX_SCAN_REQ_UMAC 0xd 1464 #define IWX_SCAN_ABORT_UMAC 0xe 1465 #define IWX_SCAN_COMPLETE_UMAC 0xf 1466 1467 /* station table */ 1468 #define IWX_ADD_STA_KEY 0x17 1469 #define IWX_ADD_STA 0x18 1470 #define IWX_REMOVE_STA 0x19 1471 1472 /* TX */ 1473 #define IWX_TX_CMD 0x1c 1474 #define IWX_TXPATH_FLUSH 0x1e 1475 #define IWX_MGMT_MCAST_KEY 0x1f 1476 1477 /* scheduler config */ 1478 #define IWX_SCD_QUEUE_CFG 0x1d 1479 1480 /* global key */ 1481 #define IWX_WEP_KEY 0x20 1482 1483 /* MAC and Binding commands */ 1484 #define IWX_MAC_CONTEXT_CMD 0x28 1485 #define IWX_TIME_EVENT_CMD 0x29 /* both CMD and response */ 1486 #define IWX_TIME_EVENT_NOTIFICATION 0x2a 1487 #define IWX_BINDING_CONTEXT_CMD 0x2b 1488 #define IWX_TIME_QUOTA_CMD 0x2c 1489 #define IWX_NON_QOS_TX_COUNTER_CMD 0x2d 1490 1491 /* Calibration */ 1492 #define IWX_TEMPERATURE_NOTIFICATION 0x62 1493 #define IWX_CALIBRATION_CFG_CMD 0x65 1494 #define IWX_CALIBRATION_RES_NOTIFICATION 0x66 1495 #define IWX_CALIBRATION_COMPLETE_NOTIFICATION 0x67 1496 #define IWX_RADIO_VERSION_NOTIFICATION 0x68 1497 1498 /* Phy */ 1499 #define IWX_PHY_CONFIGURATION_CMD 0x6a 1500 1501 /* Power - legacy power table command */ 1502 #define IWX_POWER_TABLE_CMD 0x77 1503 #define IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78 1504 #define IWX_LTR_CONFIG 0xee 1505 1506 /* NVM */ 1507 #define IWX_NVM_ACCESS_CMD 0x88 1508 1509 #define IWX_SET_CALIB_DEFAULT_CMD 0x8e 1510 1511 #define IWX_BEACON_NOTIFICATION 0x90 1512 #define IWX_BEACON_TEMPLATE_CMD 0x91 1513 #define IWX_TX_ANT_CONFIGURATION_CMD 0x98 1514 #define IWX_BT_CONFIG 0x9b 1515 #define IWX_STATISTICS_CMD 0x9c 1516 #define IWX_STATISTICS_NOTIFICATION 0x9d 1517 #define IWX_REDUCE_TX_POWER_CMD 0x9f 1518 1519 /* RF-KILL commands and notifications */ 1520 #define IWX_CARD_STATE_CMD 0xa0 1521 #define IWX_CARD_STATE_NOTIFICATION 0xa1 1522 1523 #define IWX_MISSED_BEACONS_NOTIFICATION 0xa2 1524 1525 #define IWX_MFUART_LOAD_NOTIFICATION 0xb1 1526 1527 /* Power - new power table command */ 1528 #define IWX_MAC_PM_POWER_TABLE 0xa9 1529 1530 #define IWX_REPLY_RX_PHY_CMD 0xc0 1531 #define IWX_REPLY_RX_MPDU_CMD 0xc1 1532 #define IWX_BA_NOTIF 0xc5 1533 1534 /* Location Aware Regulatory */ 1535 #define IWX_MCC_UPDATE_CMD 0xc8 1536 #define IWX_MCC_CHUB_UPDATE_CMD 0xc9 1537 1538 /* BT Coex */ 1539 #define IWX_BT_COEX_PRIO_TABLE 0xcc 1540 #define IWX_BT_COEX_PROT_ENV 0xcd 1541 #define IWX_BT_PROFILE_NOTIFICATION 0xce 1542 #define IWX_BT_COEX_CI 0x5d 1543 1544 #define IWX_REPLY_SF_CFG_CMD 0xd1 1545 #define IWX_REPLY_BEACON_FILTERING_CMD 0xd2 1546 1547 /* DTS measurements */ 1548 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER 0xdc 1549 #define IWX_DTS_MEASUREMENT_NOTIFICATION 0xdd 1550 1551 #define IWX_REPLY_DEBUG_CMD 0xf0 1552 #define IWX_DEBUG_LOG_MSG 0xf7 1553 1554 #define IWX_MCAST_FILTER_CMD 0xd0 1555 1556 /* D3 commands/notifications */ 1557 #define IWX_D3_CONFIG_CMD 0xd3 1558 #define IWX_PROT_OFFLOAD_CONFIG_CMD 0xd4 1559 #define IWX_OFFLOADS_QUERY_CMD 0xd5 1560 #define IWX_REMOTE_WAKE_CONFIG_CMD 0xd6 1561 1562 /* for WoWLAN in particular */ 1563 #define IWX_WOWLAN_PATTERNS 0xe0 1564 #define IWX_WOWLAN_CONFIGURATION 0xe1 1565 #define IWX_WOWLAN_TSC_RSC_PARAM 0xe2 1566 #define IWX_WOWLAN_TKIP_PARAM 0xe3 1567 #define IWX_WOWLAN_KEK_KCK_MATERIAL 0xe4 1568 #define IWX_WOWLAN_GET_STATUSES 0xe5 1569 #define IWX_WOWLAN_TX_POWER_PER_DB 0xe6 1570 1571 /* and for NetDetect */ 1572 #define IWX_NET_DETECT_CONFIG_CMD 0x54 1573 #define IWX_NET_DETECT_PROFILES_QUERY_CMD 0x56 1574 #define IWX_NET_DETECT_PROFILES_CMD 0x57 1575 #define IWX_NET_DETECT_HOTSPOTS_CMD 0x58 1576 #define IWX_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59 1577 1578 /* system group command IDs */ 1579 #define IWX_FSEQ_VER_MISMATCH_NOTIFICATION 0xff 1580 1581 #define IWX_REPLY_MAX 0xff 1582 1583 /* PHY_OPS subcommand IDs */ 1584 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0 1585 #define IWX_CTDP_CONFIG_CMD 0x03 1586 #define IWX_TEMP_REPORTING_THRESHOLDS_CMD 0x04 1587 #define IWX_CT_KILL_NOTIFICATION 0xFE 1588 #define IWX_DTS_MEASUREMENT_NOTIF_WIDE 0xFF 1589 1590 /* command groups */ 1591 #define IWX_LEGACY_GROUP 0x0 1592 #define IWX_LONG_GROUP 0x1 1593 #define IWX_SYSTEM_GROUP 0x2 1594 #define IWX_MAC_CONF_GROUP 0x3 1595 #define IWX_PHY_OPS_GROUP 0x4 1596 #define IWX_DATA_PATH_GROUP 0x5 1597 #define IWX_PROT_OFFLOAD_GROUP 0xb 1598 #define IWX_REGULATORY_AND_NVM_GROUP 0xc 1599 1600 /* SYSTEM_GROUP group subcommand IDs */ 1601 1602 #define IWX_SHARED_MEM_CFG_CMD 0x00 1603 #define IWX_SOC_CONFIGURATION_CMD 0x01 1604 #define IWX_INIT_EXTENDED_CFG_CMD 0x03 1605 #define IWX_FW_ERROR_RECOVERY_CMD 0x07 1606 1607 /* DATA_PATH group subcommand IDs */ 1608 #define IWX_DQA_ENABLE_CMD 0x00 1609 #define IWX_TLC_MNG_CONFIG_CMD 0x0f 1610 #define IWX_RX_NO_DATA_NOTIF 0xf5 1611 #define IWX_TLC_MNG_UPDATE_NOTIF 0xf7 1612 1613 /* REGULATORY_AND_NVM group subcommand IDs */ 1614 #define IWX_NVM_ACCESS_COMPLETE 0x00 1615 #define IWX_NVM_GET_INFO 0x02 1616 1617 /* 1618 * struct iwx_dqa_enable_cmd 1619 * @cmd_queue: the TXQ number of the command queue 1620 */ 1621 struct iwx_dqa_enable_cmd { 1622 uint32_t cmd_queue; 1623 } __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */ 1624 1625 /** 1626 * struct iwx_cmd_response - generic response struct for most commands 1627 * @status: status of the command asked, changes for each one 1628 */ 1629 struct iwx_cmd_response { 1630 uint32_t status; 1631 }; 1632 1633 /* 1634 * struct iwx_tx_ant_cfg_cmd 1635 * @valid: valid antenna configuration 1636 */ 1637 struct iwx_tx_ant_cfg_cmd { 1638 uint32_t valid; 1639 } __packed; 1640 1641 /* 1642 * Calibration control struct. 1643 * Sent as part of the phy configuration command. 1644 * @flow_trigger: bitmap for which calibrations to perform according to 1645 * flow triggers. 1646 * @event_trigger: bitmap for which calibrations to perform according to 1647 * event triggers. 1648 */ 1649 struct iwx_calib_ctrl { 1650 uint32_t flow_trigger; 1651 uint32_t event_trigger; 1652 } __packed; 1653 1654 /* This defines the bitmap of various calibrations to enable in both 1655 * init ucode and runtime ucode through IWX_CALIBRATION_CFG_CMD. 1656 */ 1657 #define IWX_CALIB_CFG_XTAL_IDX (1 << 0) 1658 #define IWX_CALIB_CFG_TEMPERATURE_IDX (1 << 1) 1659 #define IWX_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2) 1660 #define IWX_CALIB_CFG_PAPD_IDX (1 << 3) 1661 #define IWX_CALIB_CFG_TX_PWR_IDX (1 << 4) 1662 #define IWX_CALIB_CFG_DC_IDX (1 << 5) 1663 #define IWX_CALIB_CFG_BB_FILTER_IDX (1 << 6) 1664 #define IWX_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7) 1665 #define IWX_CALIB_CFG_TX_IQ_IDX (1 << 8) 1666 #define IWX_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9) 1667 #define IWX_CALIB_CFG_RX_IQ_IDX (1 << 10) 1668 #define IWX_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11) 1669 #define IWX_CALIB_CFG_SENSITIVITY_IDX (1 << 12) 1670 #define IWX_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13) 1671 #define IWX_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14) 1672 #define IWX_CALIB_CFG_ANT_COUPLING_IDX (1 << 15) 1673 #define IWX_CALIB_CFG_DAC_IDX (1 << 16) 1674 #define IWX_CALIB_CFG_ABS_IDX (1 << 17) 1675 #define IWX_CALIB_CFG_AGC_IDX (1 << 18) 1676 1677 /* 1678 * Phy configuration command. 1679 */ 1680 struct iwx_phy_cfg_cmd { 1681 uint32_t phy_cfg; 1682 struct iwx_calib_ctrl calib_control; 1683 } __packed; 1684 1685 #define IWX_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1)) 1686 #define IWX_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3)) 1687 #define IWX_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5)) 1688 #define IWX_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7)) 1689 #define IWX_PHY_CFG_TX_CHAIN_A (1 << 8) 1690 #define IWX_PHY_CFG_TX_CHAIN_B (1 << 9) 1691 #define IWX_PHY_CFG_TX_CHAIN_C (1 << 10) 1692 #define IWX_PHY_CFG_RX_CHAIN_A (1 << 12) 1693 #define IWX_PHY_CFG_RX_CHAIN_B (1 << 13) 1694 #define IWX_PHY_CFG_RX_CHAIN_C (1 << 14) 1695 1696 #define IWX_MAX_DTS_TRIPS 8 1697 1698 /** 1699 * struct iwx_ct_kill_notif - CT-kill entry notification 1700 * 1701 * @temperature: the current temperature in celsius 1702 * @reserved: reserved 1703 */ 1704 struct iwx_ct_kill_notif { 1705 uint16_t temperature; 1706 uint16_t reserved; 1707 } __packed; /* GRP_PHY_CT_KILL_NTF */ 1708 1709 /** 1710 * struct iwx_temp_report_ths_cmd - set temperature thresholds 1711 * (IWX_TEMP_REPORTING_THRESHOLDS_CMD) 1712 * 1713 * @num_temps: number of temperature thresholds passed 1714 * @thresholds: array with the thresholds to be configured 1715 */ 1716 struct iwx_temp_report_ths_cmd { 1717 uint32_t num_temps; 1718 uint16_t thresholds[IWX_MAX_DTS_TRIPS]; 1719 } __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */ 1720 1721 /* 1722 * channel flags in NVM 1723 * @IWX_NVM_CHANNEL_VALID: channel is usable for this SKU/geo 1724 * @IWX_NVM_CHANNEL_IBSS: usable as an IBSS channel 1725 * @IWX_NVM_CHANNEL_ACTIVE: active scanning allowed 1726 * @IWX_NVM_CHANNEL_RADAR: radar detection required 1727 * @IWX_NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed 1728 * @IWX_NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS 1729 * on same channel on 2.4 or same UNII band on 5.2 1730 * @IWX_NVM_CHANNEL_DFS: dynamic freq selection candidate 1731 * @IWX_NVM_CHANNEL_WIDE: 20 MHz channel okay (?) 1732 * @IWX_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?) 1733 * @IWX_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?) 1734 * @IWX_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?) 1735 * @IWX_NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?) 1736 */ 1737 #define IWX_NVM_CHANNEL_VALID (1 << 0) 1738 #define IWX_NVM_CHANNEL_IBSS (1 << 1) 1739 #define IWX_NVM_CHANNEL_ACTIVE (1 << 3) 1740 #define IWX_NVM_CHANNEL_RADAR (1 << 4) 1741 #define IWX_NVM_CHANNEL_INDOOR_ONLY (1 << 5) 1742 #define IWX_NVM_CHANNEL_GO_CONCURRENT (1 << 6) 1743 #define IWX_NVM_CHANNEL_DFS (1 << 7) 1744 #define IWX_NVM_CHANNEL_WIDE (1 << 8) 1745 #define IWX_NVM_CHANNEL_40MHZ (1 << 9) 1746 #define IWX_NVM_CHANNEL_80MHZ (1 << 10) 1747 #define IWX_NVM_CHANNEL_160MHZ (1 << 11) 1748 #define IWX_NVM_CHANNEL_DC_HIGH (1 << 12) 1749 1750 /** 1751 * struct iwx_nvm_access_complete_cmd - NVM_ACCESS commands are completed 1752 * @reserved: reserved 1753 */ 1754 struct iwx_nvm_access_complete_cmd { 1755 uint32_t reserved; 1756 } __packed; /* NVM_ACCESS_COMPLETE_CMD_API_S_VER_1 */ 1757 1758 /* 1759 * struct iwx_nvm_get_info - request to get NVM data 1760 */ 1761 struct iwx_nvm_get_info { 1762 uint32_t reserved; 1763 } __packed; /* REGULATORY_NVM_GET_INFO_CMD_API_S_VER_1 */ 1764 1765 /** 1766 * enum iwx_nvm_info_general_flags - flags in NVM_GET_INFO resp 1767 * @NVM_GENERAL_FLAGS_EMPTY_OTP: 1 if OTP is empty 1768 */ 1769 #define IWX_NVM_GENERAL_FLAGS_EMPTY_OTP (1 << 0) 1770 1771 /** 1772 * struct iwx_nvm_get_info_general - general NVM data 1773 * @flags: bit 0: 1 - empty, 0 - non-empty 1774 * @nvm_version: nvm version 1775 * @board_type: board type 1776 * @n_hw_addrs: number of reserved MAC addresses 1777 */ 1778 struct iwx_nvm_get_info_general { 1779 uint32_t flags; 1780 uint16_t nvm_version; 1781 uint8_t board_type; 1782 uint8_t n_hw_addrs; 1783 } __packed; /* REGULATORY_NVM_GET_INFO_GENERAL_S_VER_2 */ 1784 1785 /** 1786 * iwx_nvm_mac_sku_flags - flags in &iwl_nvm_get_info_sku 1787 * @NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED: true if 2.4 band enabled 1788 * @NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED: true if 5.2 band enabled 1789 * @NVM_MAC_SKU_FLAGS_802_11N_ENABLED: true if 11n enabled 1790 * @NVM_MAC_SKU_FLAGS_802_11AC_ENABLED: true if 11ac enabled 1791 * @NVM_MAC_SKU_FLAGS_802_11AX_ENABLED: true if 11ax enabled 1792 * @NVM_MAC_SKU_FLAGS_MIMO_DISABLED: true if MIMO disabled 1793 * @NVM_MAC_SKU_FLAGS_WAPI_ENABLED: true if WAPI enabled 1794 * @NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED: true if regulatory checker enabled 1795 * @NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED: true if API lock enabled 1796 */ 1797 #define IWX_NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED (1 << 0) 1798 #define IWX_NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED (1 << 1) 1799 #define IWX_NVM_MAC_SKU_FLAGS_802_11N_ENABLED (1 << 2) 1800 #define IWX_NVM_MAC_SKU_FLAGS_802_11AC_ENABLED (1 << 3) 1801 #define IWX_NVM_MAC_SKU_FLAGS_802_11AX_ENABLED (1 << 4) 1802 #define IWX_NVM_MAC_SKU_FLAGS_MIMO_DISABLED (1 << 5) 1803 #define IWX_NVM_MAC_SKU_FLAGS_WAPI_ENABLED (1 << 8) 1804 #define IWX_NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED (1 << 14) 1805 #define IWX_NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED (1 << 15) 1806 1807 /** 1808 * struct iwx_nvm_get_info_sku - mac information 1809 * @mac_sku_flags: flags for SKU, see &enum iwl_nvm_mac_sku_flags 1810 */ 1811 struct iwx_nvm_get_info_sku { 1812 uint32_t mac_sku_flags; 1813 } __packed; /* REGULATORY_NVM_GET_INFO_MAC_SKU_SECTION_S_VER_2 */ 1814 1815 /** 1816 * struct iwx_nvm_get_info_phy - phy information 1817 * @tx_chains: BIT 0 chain A, BIT 1 chain B 1818 * @rx_chains: BIT 0 chain A, BIT 1 chain B 1819 */ 1820 struct iwx_nvm_get_info_phy { 1821 uint32_t tx_chains; 1822 uint32_t rx_chains; 1823 } __packed; /* REGULATORY_NVM_GET_INFO_PHY_SKU_SECTION_S_VER_1 */ 1824 1825 #define IWX_NUM_CHANNELS_V1 51 1826 #define IWX_NUM_CHANNELS 110 1827 1828 /** 1829 * struct iwx_nvm_get_info_regulatory - regulatory information 1830 * @lar_enabled: is LAR enabled 1831 * @channel_profile: regulatory data of this channel 1832 * @reserved: reserved 1833 */ 1834 struct iwx_nvm_get_info_regulatory_v1 { 1835 uint32_t lar_enabled; 1836 uint16_t channel_profile[IWX_NUM_CHANNELS_V1]; 1837 uint16_t reserved; 1838 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_1 */ 1839 1840 /** 1841 * struct iwx_nvm_get_info_regulatory - regulatory information 1842 * @lar_enabled: is LAR enabled 1843 * @n_channels: number of valid channels in the array 1844 * @channel_profile: regulatory data of this channel 1845 */ 1846 struct iwx_nvm_get_info_regulatory { 1847 uint32_t lar_enabled; 1848 uint32_t n_channels; 1849 uint32_t channel_profile[IWX_NUM_CHANNELS]; 1850 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_2 */ 1851 1852 /** 1853 * struct iwx_nvm_get_info_rsp_v3 - response to get NVM data 1854 * @general: general NVM data 1855 * @mac_sku: data relating to MAC sku 1856 * @phy_sku: data relating to PHY sku 1857 * @regulatory: regulatory data 1858 */ 1859 struct iwx_nvm_get_info_rsp_v3 { 1860 struct iwx_nvm_get_info_general general; 1861 struct iwx_nvm_get_info_sku mac_sku; 1862 struct iwx_nvm_get_info_phy phy_sku; 1863 struct iwx_nvm_get_info_regulatory_v1 regulatory; 1864 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_3 */ 1865 1866 /** 1867 * struct iwx_nvm_get_info_rsp - response to get NVM data 1868 * @general: general NVM data 1869 * @mac_sku: data relating to MAC sku 1870 * @phy_sku: data relating to PHY sku 1871 * @regulatory: regulatory data 1872 */ 1873 struct iwx_nvm_get_info_rsp { 1874 struct iwx_nvm_get_info_general general; 1875 struct iwx_nvm_get_info_sku mac_sku; 1876 struct iwx_nvm_get_info_phy phy_sku; 1877 struct iwx_nvm_get_info_regulatory regulatory; 1878 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_4 */ 1879 1880 1881 #define IWX_ALIVE_STATUS_ERR 0xDEAD 1882 #define IWX_ALIVE_STATUS_OK 0xCAFE 1883 1884 struct iwx_lmac_debug_addrs { 1885 uint32_t error_event_table_ptr; /* SRAM address for error log */ 1886 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */ 1887 uint32_t cpu_register_ptr; 1888 uint32_t dbgm_config_ptr; 1889 uint32_t alive_counter_ptr; 1890 uint32_t scd_base_ptr; /* SRAM address for SCD */ 1891 uint32_t st_fwrd_addr; /* pointer to Store and forward */ 1892 uint32_t st_fwrd_size; 1893 } __packed; /* UCODE_DEBUG_ADDRS_API_S_VER_2 */ 1894 1895 struct iwx_lmac_alive { 1896 uint32_t ucode_major; 1897 uint32_t ucode_minor; 1898 uint8_t ver_subtype; 1899 uint8_t ver_type; 1900 uint8_t mac; 1901 uint8_t opt; 1902 uint32_t timestamp; 1903 struct iwx_lmac_debug_addrs dbg_ptrs; 1904 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */ 1905 1906 struct iwx_umac_debug_addrs { 1907 uint32_t error_info_addr; /* SRAM address for UMAC error log */ 1908 uint32_t dbg_print_buff_addr; 1909 } __packed; /* UMAC_DEBUG_ADDRS_API_S_VER_1 */ 1910 1911 struct iwx_umac_alive { 1912 uint32_t umac_major; /* UMAC version: major */ 1913 uint32_t umac_minor; /* UMAC version: minor */ 1914 struct iwx_umac_debug_addrs dbg_ptrs; 1915 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */ 1916 1917 struct iwx_alive_resp_v4 { 1918 uint16_t status; 1919 uint16_t flags; 1920 struct iwx_lmac_alive lmac_data[2]; 1921 struct iwx_umac_alive umac_data; 1922 } __packed; /* ALIVE_RES_API_S_VER_4 */ 1923 1924 #define IWX_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0) 1925 #define IWX_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1) 1926 1927 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc 1928 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0 1929 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_200 1 1930 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_2500 2 1931 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_1820 3 1932 1933 /** 1934 * struct iwx_soc_configuration_cmd - Set device stabilization latency 1935 * 1936 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE 1937 * flag, because the FW treats the whole value as an integer. In 1938 * VER_2, we can set the bits independently. 1939 * @latency: time for SOC to ensure stable power & XTAL 1940 */ 1941 struct iwx_soc_configuration_cmd { 1942 uint32_t flags; 1943 uint32_t latency; 1944 } __packed; /* 1945 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above) 1946 * SOC_CONFIGURATION_CMD_S_VER_2 1947 */ 1948 1949 /** 1950 * commands driver may send before finishing init flow 1951 * @IWX_INIT_DEBUG_CFG: driver is going to send debug config command 1952 * @IWX_INIT_NVM: driver is going to send NVM_ACCESS commands 1953 */ 1954 #define IWX_INIT_DEBUG_CFG (1 << 0) 1955 #define IWX_INIT_NVM (1 << 1) 1956 1957 /** 1958 * struct iwx_extended_cfg_cmd - mark what commands ucode should wait for 1959 * before finishing init flows 1960 * @init_flags: IWX_INIT_* flag bits 1961 */ 1962 struct iwx_init_extended_cfg_cmd { 1963 uint32_t init_flags; 1964 } __packed; /* INIT_EXTENDED_CFG_CMD_API_S_VER_1 */ 1965 1966 /* Error response/notification */ 1967 #define IWX_FW_ERR_UNKNOWN_CMD 0x0 1968 #define IWX_FW_ERR_INVALID_CMD_PARAM 0x1 1969 #define IWX_FW_ERR_SERVICE 0x2 1970 #define IWX_FW_ERR_ARC_MEMORY 0x3 1971 #define IWX_FW_ERR_ARC_CODE 0x4 1972 #define IWX_FW_ERR_WATCH_DOG 0x5 1973 #define IWX_FW_ERR_WEP_GRP_KEY_INDX 0x10 1974 #define IWX_FW_ERR_WEP_KEY_SIZE 0x11 1975 #define IWX_FW_ERR_OBSOLETE_FUNC 0x12 1976 #define IWX_FW_ERR_UNEXPECTED 0xFE 1977 #define IWX_FW_ERR_FATAL 0xFF 1978 1979 /** 1980 * struct iwx_error_resp - FW error indication 1981 * ( IWX_REPLY_ERROR = 0x2 ) 1982 * @error_type: one of IWX_FW_ERR_* 1983 * @cmd_id: the command ID for which the error occured 1984 * @bad_cmd_seq_num: sequence number of the erroneous command 1985 * @error_service: which service created the error, applicable only if 1986 * error_type = 2, otherwise 0 1987 * @timestamp: TSF in usecs. 1988 */ 1989 struct iwx_error_resp { 1990 uint32_t error_type; 1991 uint8_t cmd_id; 1992 uint8_t reserved1; 1993 uint16_t bad_cmd_seq_num; 1994 uint32_t error_service; 1995 uint64_t timestamp; 1996 } __packed; 1997 1998 enum iwx_fw_dbg_reg_operator { 1999 CSR_ASSIGN, 2000 CSR_SETBIT, 2001 CSR_CLEARBIT, 2002 2003 PRPH_ASSIGN, 2004 PRPH_SETBIT, 2005 PRPH_CLEARBIT, 2006 2007 INDIRECT_ASSIGN, 2008 INDIRECT_SETBIT, 2009 INDIRECT_CLEARBIT, 2010 2011 PRPH_BLOCKBIT, 2012 }; 2013 2014 /** 2015 * struct iwx_fw_dbg_reg_op - an operation on a register 2016 * 2017 * @op: &enum iwx_fw_dbg_reg_operator 2018 * @addr: offset of the register 2019 * @val: value 2020 */ 2021 struct iwx_fw_dbg_reg_op { 2022 uint8_t op; 2023 uint8_t reserved[3]; 2024 uint32_t addr; 2025 uint32_t val; 2026 } __packed; 2027 2028 /** 2029 * enum iwx_fw_dbg_monitor_mode - available monitor recording modes 2030 * 2031 * @SMEM_MODE: monitor stores the data in SMEM 2032 * @EXTERNAL_MODE: monitor stores the data in allocated DRAM 2033 * @MARBH_MODE: monitor stores the data in MARBH buffer 2034 * @MIPI_MODE: monitor outputs the data through the MIPI interface 2035 */ 2036 enum iwx_fw_dbg_monitor_mode { 2037 SMEM_MODE = 0, 2038 EXTERNAL_MODE = 1, 2039 MARBH_MODE = 2, 2040 MIPI_MODE = 3, 2041 }; 2042 2043 /** 2044 * struct iwx_fw_dbg_mem_seg_tlv - configures the debug data memory segments 2045 * 2046 * @data_type: the memory segment type to record 2047 * @ofs: the memory segment offset 2048 * @len: the memory segment length, in bytes 2049 * 2050 * This parses IWX_UCODE_TLV_FW_MEM_SEG 2051 */ 2052 struct iwx_fw_dbg_mem_seg_tlv { 2053 uint32_t data_type; 2054 uint32_t ofs; 2055 uint32_t len; 2056 } __packed; 2057 2058 /** 2059 * struct iwx_fw_dbg_dest_tlv_v1 - configures the destination of the debug data 2060 * 2061 * @version: version of the TLV - currently 0 2062 * @monitor_mode: &enum iwx_fw_dbg_monitor_mode 2063 * @size_power: buffer size will be 2^(size_power + 11) 2064 * @base_reg: addr of the base addr register (PRPH) 2065 * @end_reg: addr of the end addr register (PRPH) 2066 * @write_ptr_reg: the addr of the reg of the write pointer 2067 * @wrap_count: the addr of the reg of the wrap_count 2068 * @base_shift: shift right of the base addr reg 2069 * @end_shift: shift right of the end addr reg 2070 * @reg_ops: array of registers operations 2071 * 2072 * This parses IWX_UCODE_TLV_FW_DBG_DEST 2073 */ 2074 struct iwx_fw_dbg_dest_tlv_v1 { 2075 uint8_t version; 2076 uint8_t monitor_mode; 2077 uint8_t size_power; 2078 uint8_t reserved; 2079 uint32_t base_reg; 2080 uint32_t end_reg; 2081 uint32_t write_ptr_reg; 2082 uint32_t wrap_count; 2083 uint8_t base_shift; 2084 uint8_t end_shift; 2085 struct iwx_fw_dbg_reg_op reg_ops[0]; 2086 } __packed; 2087 2088 /* Mask of the register for defining the LDBG MAC2SMEM buffer SMEM size */ 2089 #define IWX_LDBG_M2S_BUF_SIZE_MSK 0x0fff0000 2090 /* Mask of the register for defining the LDBG MAC2SMEM SMEM base address */ 2091 #define IWX_LDBG_M2S_BUF_BA_MSK 0x00000fff 2092 /* The smem buffer chunks are in units of 256 bits */ 2093 #define IWX_M2S_UNIT_SIZE 0x100 2094 2095 struct iwx_fw_dbg_dest_tlv { 2096 uint8_t version; 2097 uint8_t monitor_mode; 2098 uint8_t size_power; 2099 uint8_t reserved; 2100 uint32_t cfg_reg; 2101 uint32_t write_ptr_reg; 2102 uint32_t wrap_count; 2103 uint8_t base_shift; 2104 uint8_t size_shift; 2105 struct iwx_fw_dbg_reg_op reg_ops[0]; 2106 } __packed; 2107 2108 struct iwx_fw_dbg_conf_hcmd { 2109 uint8_t id; 2110 uint8_t reserved; 2111 uint16_t len; 2112 uint8_t data[0]; 2113 } __packed; 2114 2115 /** 2116 * enum iwx_fw_dbg_trigger_mode - triggers functionalities 2117 * 2118 * @IWX_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism 2119 * @IWX_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data 2120 * @IWX_FW_DBG_TRIGGER_MONITOR_ONLY: when trigger occurs trigger is set to 2121 * collect only monitor data 2122 */ 2123 enum iwx_fw_dbg_trigger_mode { 2124 IWX_FW_DBG_TRIGGER_START = (1 << 0), 2125 IWX_FW_DBG_TRIGGER_STOP = (1 << 1), 2126 IWX_FW_DBG_TRIGGER_MONITOR_ONLY = (1 << 2), 2127 }; 2128 2129 /** 2130 * enum iwx_fw_dbg_trigger_flags - the flags supported by wrt triggers 2131 * @IWX_FW_DBG_FORCE_RESTART: force a firmware restart 2132 */ 2133 enum iwx_fw_dbg_trigger_flags { 2134 IWX_FW_DBG_FORCE_RESTART = (1 << 0), 2135 }; 2136 2137 /** 2138 * enum iwx_fw_dbg_trigger_vif_type - define the VIF type for a trigger 2139 * @IWX_FW_DBG_CONF_VIF_ANY: any vif type 2140 * @IWX_FW_DBG_CONF_VIF_IBSS: IBSS mode 2141 * @IWX_FW_DBG_CONF_VIF_STATION: BSS mode 2142 * @IWX_FW_DBG_CONF_VIF_AP: AP mode 2143 * @IWX_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode 2144 * @IWX_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode 2145 * @IWX_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device 2146 * @IWX_FW_DBG_CONF_VIF_NAN: NAN device 2147 */ 2148 enum iwx_fw_dbg_trigger_vif_type { 2149 IWX_FW_DBG_CONF_VIF_ANY = 0, 2150 IWX_FW_DBG_CONF_VIF_IBSS = 1, 2151 IWX_FW_DBG_CONF_VIF_STATION = 2, 2152 IWX_FW_DBG_CONF_VIF_AP = 3, 2153 IWX_FW_DBG_CONF_VIF_P2P_CLIENT = 8, 2154 IWX_FW_DBG_CONF_VIF_P2P_GO = 9, 2155 IWX_FW_DBG_CONF_VIF_P2P_DEVICE = 10, 2156 IWX_FW_DBG_CONF_VIF_NAN = 12, 2157 }; 2158 2159 /** 2160 * enum iwl_fw_dbg_trigger - triggers available 2161 * 2162 * @FW_DBG_TRIGGER_USER: trigger log collection by user 2163 * This should not be defined as a trigger to the driver, but a value the 2164 * driver should set to indicate that the trigger was initiated by the 2165 * user. 2166 * @FW_DBG_TRIGGER_FW_ASSERT: trigger log collection when the firmware asserts 2167 * @FW_DBG_TRIGGER_MISSED_BEACONS: trigger log collection when beacons are 2168 * missed. 2169 * @FW_DBG_TRIGGER_CHANNEL_SWITCH: trigger log collection upon channel switch. 2170 * @FW_DBG_TRIGGER_FW_NOTIF: trigger log collection when the firmware sends a 2171 * command response or a notification. 2172 * @FW_DBG_TRIGGER_MLME: trigger log collection upon MLME event. 2173 * @FW_DBG_TRIGGER_STATS: trigger log collection upon statistics threshold. 2174 * @FW_DBG_TRIGGER_RSSI: trigger log collection when the rssi of the beacon 2175 * goes below a threshold. 2176 * @FW_DBG_TRIGGER_TXQ_TIMERS: configures the timers for the Tx queue hang 2177 * detection. 2178 * @FW_DBG_TRIGGER_TIME_EVENT: trigger log collection upon time events related 2179 * events. 2180 * @FW_DBG_TRIGGER_BA: trigger log collection upon BlockAck related events. 2181 * @FW_DBG_TX_LATENCY: trigger log collection when the tx latency goes above a 2182 * threshold. 2183 * @FW_DBG_TDLS: trigger log collection upon TDLS related events. 2184 * @FW_DBG_TRIGGER_TX_STATUS: trigger log collection upon tx status when 2185 * the firmware sends a tx reply. 2186 * @FW_DBG_TRIGGER_USER_EXTENDED: trigger log collection upon user space 2187 * request. 2188 * @FW_DBG_TRIGGER_ALIVE_TIMEOUT: trigger log collection if alive flow timeouts 2189 * @FW_DBG_TRIGGER_DRIVER: trigger log collection upon a flow failure 2190 * in the driver. 2191 */ 2192 enum iwx_fw_dbg_trigger { 2193 IWX_FW_DBG_TRIGGER_INVALID = 0, 2194 IWX_FW_DBG_TRIGGER_USER, 2195 IWX_FW_DBG_TRIGGER_FW_ASSERT, 2196 IWX_FW_DBG_TRIGGER_MISSED_BEACONS, 2197 IWX_FW_DBG_TRIGGER_CHANNEL_SWITCH, 2198 IWX_FW_DBG_TRIGGER_FW_NOTIF, 2199 IWX_FW_DBG_TRIGGER_MLME, 2200 IWX_FW_DBG_TRIGGER_STATS, 2201 IWX_FW_DBG_TRIGGER_RSSI, 2202 IWX_FW_DBG_TRIGGER_TXQ_TIMERS, 2203 IWX_FW_DBG_TRIGGER_TIME_EVENT, 2204 IWX_FW_DBG_TRIGGER_BA, 2205 IWX_FW_DBG_TRIGGER_TX_LATENCY, 2206 IWX_FW_DBG_TRIGGER_TDLS, 2207 IWX_FW_DBG_TRIGGER_TX_STATUS, 2208 IWX_FW_DBG_TRIGGER_USER_EXTENDED, 2209 IWX_FW_DBG_TRIGGER_ALIVE_TIMEOUT, 2210 IWX_FW_DBG_TRIGGER_DRIVER, 2211 2212 /* must be last */ 2213 IWX_FW_DBG_TRIGGER_MAX, 2214 }; 2215 2216 2217 /** 2218 * struct iwx_fw_dbg_trigger_tlv - a TLV that describes the trigger 2219 * @id: &enum iwx_fw_dbg_trigger 2220 * @vif_type: &enum iwx_fw_dbg_trigger_vif_type 2221 * @stop_conf_ids: bitmap of configurations this trigger relates to. 2222 * if the mode is %IWX_FW_DBG_TRIGGER_STOP, then if the bit corresponding 2223 * to the currently running configuration is set, the data should be 2224 * collected. 2225 * @stop_delay: how many milliseconds to wait before collecting the data 2226 * after the STOP trigger fires. 2227 * @mode: &enum iwx_fw_dbg_trigger_mode - can be stop / start of both 2228 * @start_conf_id: if mode is %IWX_FW_DBG_TRIGGER_START, this defines what 2229 * configuration should be applied when the triggers kicks in. 2230 * @occurrences: number of occurrences. 0 means the trigger will never fire. 2231 * @trig_dis_ms: the time, in milliseconds, after an occurrence of this 2232 * trigger in which another occurrence should be ignored. 2233 * @flags: &enum iwx_fw_dbg_trigger_flags 2234 */ 2235 struct iwx_fw_dbg_trigger_tlv { 2236 uint32_t id; 2237 uint32_t vif_type; 2238 uint32_t stop_conf_ids; 2239 uint32_t stop_delay; 2240 uint8_t mode; 2241 uint8_t start_conf_id; 2242 uint16_t occurrences; 2243 uint16_t trig_dis_ms; 2244 uint8_t flags; 2245 uint8_t reserved[5]; 2246 2247 uint8_t data[0]; 2248 } __packed; 2249 2250 #define IWX_FW_DBG_START_FROM_ALIVE 0 2251 #define IWX_FW_DBG_CONF_MAX 32 2252 #define IWX_FW_DBG_INVALID 0xff 2253 2254 /** 2255 * struct iwx_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons 2256 * @stop_consec_missed_bcon: stop recording if threshold is crossed. 2257 * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed. 2258 * @start_consec_missed_bcon: start recording if threshold is crossed. 2259 * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed. 2260 * @reserved1: reserved 2261 * @reserved2: reserved 2262 */ 2263 struct iwx_fw_dbg_trigger_missed_bcon { 2264 uint32_t stop_consec_missed_bcon; 2265 uint32_t stop_consec_missed_bcon_since_rx; 2266 uint32_t reserved2[2]; 2267 uint32_t start_consec_missed_bcon; 2268 uint32_t start_consec_missed_bcon_since_rx; 2269 uint32_t reserved1[2]; 2270 } __packed; 2271 2272 /** 2273 * struct iwx_fw_dbg_trigger_cmd - configures trigger for messages from FW. 2274 * cmds: the list of commands to trigger the collection on 2275 */ 2276 struct iwx_fw_dbg_trigger_cmd { 2277 struct cmd { 2278 uint8_t cmd_id; 2279 uint8_t group_id; 2280 } __packed cmds[16]; 2281 } __packed; 2282 2283 /** 2284 * iwx_fw_dbg_trigger_stats - configures trigger for statistics 2285 * @stop_offset: the offset of the value to be monitored 2286 * @stop_threshold: the threshold above which to collect 2287 * @start_offset: the offset of the value to be monitored 2288 * @start_threshold: the threshold above which to start recording 2289 */ 2290 struct iwx_fw_dbg_trigger_stats { 2291 uint32_t stop_offset; 2292 uint32_t stop_threshold; 2293 uint32_t start_offset; 2294 uint32_t start_threshold; 2295 } __packed; 2296 2297 /** 2298 * struct iwx_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI 2299 * @rssi: RSSI value to trigger at 2300 */ 2301 struct iwx_fw_dbg_trigger_low_rssi { 2302 uint32_t rssi; 2303 } __packed; 2304 2305 /** 2306 * struct iwx_fw_dbg_trigger_mlme - configures trigger for mlme events 2307 * @stop_auth_denied: number of denied authentication to collect 2308 * @stop_auth_timeout: number of authentication timeout to collect 2309 * @stop_rx_deauth: number of Rx deauth before to collect 2310 * @stop_tx_deauth: number of Tx deauth before to collect 2311 * @stop_assoc_denied: number of denied association to collect 2312 * @stop_assoc_timeout: number of association timeout to collect 2313 * @stop_connection_loss: number of connection loss to collect 2314 * @start_auth_denied: number of denied authentication to start recording 2315 * @start_auth_timeout: number of authentication timeout to start recording 2316 * @start_rx_deauth: number of Rx deauth to start recording 2317 * @start_tx_deauth: number of Tx deauth to start recording 2318 * @start_assoc_denied: number of denied association to start recording 2319 * @start_assoc_timeout: number of association timeout to start recording 2320 * @start_connection_loss: number of connection loss to start recording 2321 */ 2322 struct iwx_fw_dbg_trigger_mlme { 2323 uint8_t stop_auth_denied; 2324 uint8_t stop_auth_timeout; 2325 uint8_t stop_rx_deauth; 2326 uint8_t stop_tx_deauth; 2327 2328 uint8_t stop_assoc_denied; 2329 uint8_t stop_assoc_timeout; 2330 uint8_t stop_connection_loss; 2331 uint8_t reserved; 2332 2333 uint8_t start_auth_denied; 2334 uint8_t start_auth_timeout; 2335 uint8_t start_rx_deauth; 2336 uint8_t start_tx_deauth; 2337 2338 uint8_t start_assoc_denied; 2339 uint8_t start_assoc_timeout; 2340 uint8_t start_connection_loss; 2341 uint8_t reserved2; 2342 } __packed; 2343 2344 /** 2345 * struct iwx_fw_dbg_trigger_txq_timer - configures the Tx queue's timer 2346 * @command_queue: timeout for the command queue in ms 2347 * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms 2348 * @softap: timeout for the queues of a softAP in ms 2349 * @p2p_go: timeout for the queues of a P2P GO in ms 2350 * @p2p_client: timeout for the queues of a P2P client in ms 2351 * @p2p_device: timeout for the queues of a P2P device in ms 2352 * @ibss: timeout for the queues of an IBSS in ms 2353 * @tdls: timeout for the queues of a TDLS station in ms 2354 */ 2355 struct iwx_fw_dbg_trigger_txq_timer { 2356 uint32_t command_queue; 2357 uint32_t bss; 2358 uint32_t softap; 2359 uint32_t p2p_go; 2360 uint32_t p2p_client; 2361 uint32_t p2p_device; 2362 uint32_t ibss; 2363 uint32_t tdls; 2364 uint32_t reserved[4]; 2365 } __packed; 2366 2367 /** 2368 * struct iwx_fw_dbg_trigger_time_event - configures a time event trigger 2369 * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a 2370 * trigger each time a time event notification that relates to time event 2371 * id with one of the actions in the bitmap is received and 2372 * BIT(notif->status) is set in status_bitmap. 2373 * 2374 */ 2375 struct iwx_fw_dbg_trigger_time_event { 2376 struct { 2377 uint32_t id; 2378 uint32_t action_bitmap; 2379 uint32_t status_bitmap; 2380 } __packed time_events[16]; 2381 } __packed; 2382 2383 /** 2384 * struct iwx_fw_dbg_trigger_ba - configures BlockAck related trigger 2385 * rx_ba_start: tid bitmap to configure on what tid the trigger should occur 2386 * when an Rx BlockAck session is started. 2387 * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur 2388 * when an Rx BlockAck session is stopped. 2389 * tx_ba_start: tid bitmap to configure on what tid the trigger should occur 2390 * when a Tx BlockAck session is started. 2391 * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur 2392 * when a Tx BlockAck session is stopped. 2393 * rx_bar: tid bitmap to configure on what tid the trigger should occur 2394 * when a BAR is received (for a Tx BlockAck session). 2395 * tx_bar: tid bitmap to configure on what tid the trigger should occur 2396 * when a BAR is send (for an Rx BlocAck session). 2397 * frame_timeout: tid bitmap to configure on what tid the trigger should occur 2398 * when a frame times out in the reodering buffer. 2399 */ 2400 struct iwx_fw_dbg_trigger_ba { 2401 uint16_t rx_ba_start; 2402 uint16_t rx_ba_stop; 2403 uint16_t tx_ba_start; 2404 uint16_t tx_ba_stop; 2405 uint16_t rx_bar; 2406 uint16_t tx_bar; 2407 uint16_t frame_timeout; 2408 } __packed; 2409 2410 /** 2411 * struct iwx_fw_dbg_trigger_tx_latency - configures tx latency related trigger 2412 * @thrshold: the wanted threshold. 2413 * @tid_bitmap: the tid to apply the threshold on 2414 * @mode: recording mode (Internal buffer or continues recording) 2415 * @window: the size of the window before collecting. 2416 * @reserved: reserved. 2417 */ 2418 struct iwx_fw_dbg_trigger_tx_latency { 2419 uint32_t thrshold; 2420 uint16_t tid_bitmap; 2421 uint16_t mode; 2422 uint32_t window; 2423 uint32_t reserved[4]; 2424 } __packed; 2425 2426 /** 2427 * struct iwx_fw_dbg_trigger_tdls - configures trigger for TDLS events. 2428 * @action_bitmap: the TDLS action to trigger the collection upon 2429 * @peer_mode: trigger on specific peer or all 2430 * @peer: the TDLS peer to trigger the collection on 2431 */ 2432 struct iwx_fw_dbg_trigger_tdls { 2433 uint8_t action_bitmap; 2434 uint8_t peer_mode; 2435 uint8_t peer[ETHER_ADDR_LEN]; 2436 uint8_t reserved[4]; 2437 } __packed; 2438 2439 /** 2440 * struct iwx_fw_dbg_trigger_tx_status - configures trigger for tx response 2441 * status. 2442 * @statuses: the list of statuses to trigger the collection on 2443 */ 2444 struct iwx_fw_dbg_trigger_tx_status { 2445 struct tx_status { 2446 uint8_t status; 2447 uint8_t reserved[3]; 2448 } __packed statuses[16]; 2449 uint32_t reserved[2]; 2450 } __packed; 2451 2452 /** 2453 * struct iwx_fw_dbg_conf_tlv - a TLV that describes a debug configuration. 2454 * @id: conf id 2455 * @usniffer: should the uSniffer image be used 2456 * @num_of_hcmds: how many HCMDs to send are present here 2457 * @hcmd: a variable length host command to be sent to apply the configuration. 2458 * If there is more than one HCMD to send, they will appear one after the 2459 * other and be sent in the order that they appear in. 2460 * This parses IWX_UCODE_TLV_FW_DBG_CONF. The user can add up-to 2461 * %IWX_FW_DBG_CONF_MAX configuration per run. 2462 */ 2463 struct iwx_fw_dbg_conf_tlv { 2464 uint8_t id; 2465 uint8_t usniffer; 2466 uint8_t reserved; 2467 uint8_t num_of_hcmds; 2468 struct iwx_fw_dbg_conf_hcmd hcmd; 2469 } __packed; 2470 2471 #define IWX_FW_CMD_VER_UNKNOWN 99 2472 2473 /** 2474 * struct iwx_fw_cmd_version - firmware command version entry 2475 * @cmd: command ID 2476 * @group: group ID 2477 * @cmd_ver: command version 2478 * @notif_ver: notification version 2479 */ 2480 struct iwx_fw_cmd_version { 2481 uint8_t cmd; 2482 uint8_t group; 2483 uint8_t cmd_ver; 2484 uint8_t notif_ver; 2485 } __packed; 2486 2487 /* Common PHY, MAC and Bindings definitions */ 2488 2489 #define IWX_MAX_MACS_IN_BINDING (3) 2490 #define IWX_MAX_BINDINGS (4) 2491 #define IWX_AUX_BINDING_INDEX (3) 2492 #define IWX_MAX_PHYS (4) 2493 2494 /* Used to extract ID and color from the context dword */ 2495 #define IWX_FW_CTXT_ID_POS (0) 2496 #define IWX_FW_CTXT_ID_MSK (0xff << IWX_FW_CTXT_ID_POS) 2497 #define IWX_FW_CTXT_COLOR_POS (8) 2498 #define IWX_FW_CTXT_COLOR_MSK (0xff << IWX_FW_CTXT_COLOR_POS) 2499 #define IWX_FW_CTXT_INVALID (0xffffffff) 2500 2501 #define IWX_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWX_FW_CTXT_ID_POS) |\ 2502 (_color << IWX_FW_CTXT_COLOR_POS)) 2503 2504 /* Possible actions on PHYs, MACs and Bindings */ 2505 #define IWX_FW_CTXT_ACTION_STUB 0 2506 #define IWX_FW_CTXT_ACTION_ADD 1 2507 #define IWX_FW_CTXT_ACTION_MODIFY 2 2508 #define IWX_FW_CTXT_ACTION_REMOVE 3 2509 #define IWX_FW_CTXT_ACTION_NUM 4 2510 /* COMMON_CONTEXT_ACTION_API_E_VER_1 */ 2511 2512 /* Time Events */ 2513 2514 /* Time Event types, according to MAC type */ 2515 2516 /* BSS Station Events */ 2517 #define IWX_TE_BSS_STA_AGGRESSIVE_ASSOC 0 2518 #define IWX_TE_BSS_STA_ASSOC 1 2519 #define IWX_TE_BSS_EAP_DHCP_PROT 2 2520 #define IWX_TE_BSS_QUIET_PERIOD 3 2521 2522 /* P2P Device Events */ 2523 #define IWX_TE_P2P_DEVICE_DISCOVERABLE 4 2524 #define IWX_TE_P2P_DEVICE_LISTEN 5 2525 #define IWX_TE_P2P_DEVICE_ACTION_SCAN 6 2526 #define IWX_TE_P2P_DEVICE_FULL_SCAN 7 2527 2528 /* P2P Client Events */ 2529 #define IWX_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8 2530 #define IWX_TE_P2P_CLIENT_ASSOC 9 2531 #define IWX_TE_P2P_CLIENT_QUIET_PERIOD 10 2532 2533 /* P2P GO Events */ 2534 #define IWX_TE_P2P_GO_ASSOC_PROT 11 2535 #define IWX_TE_P2P_GO_REPETITIVE_NOA 12 2536 #define IWX_TE_P2P_GO_CT_WINDOW 13 2537 2538 /* WiDi Sync Events */ 2539 #define IWX_TE_WIDI_TX_SYNC 14 2540 2541 /* Time event - defines for command API */ 2542 2543 /** 2544 * DOC: Time Events - what is it? 2545 * 2546 * Time Events are a fw feature that allows the driver to control the presence 2547 * of the device on the channel. Since the fw supports multiple channels 2548 * concurrently, the fw may choose to jump to another channel at any time. 2549 * In order to make sure that the fw is on a specific channel at a certain time 2550 * and for a certain duration, the driver needs to issue a time event. 2551 * 2552 * The simplest example is for BSS association. The driver issues a time event, 2553 * waits for it to start, and only then tells mac80211 that we can start the 2554 * association. This way, we make sure that the association will be done 2555 * smoothly and won't be interrupted by channel switch decided within the fw. 2556 */ 2557 2558 /** 2559 * DOC: The flow against the fw 2560 * 2561 * When the driver needs to make sure we are in a certain channel, at a certain 2562 * time and for a certain duration, it sends a Time Event. The flow against the 2563 * fw goes like this: 2564 * 1) Driver sends a TIME_EVENT_CMD to the fw 2565 * 2) Driver gets the response for that command. This response contains the 2566 * Unique ID (UID) of the event. 2567 * 3) The fw sends notification when the event starts. 2568 * 2569 * Of course the API provides various options that allow to cover parameters 2570 * of the flow. 2571 * What is the duration of the event? 2572 * What is the start time of the event? 2573 * Is there an end-time for the event? 2574 * How much can the event be delayed? 2575 * Can the event be split? 2576 * If yes what is the maximal number of chunks? 2577 * etc... 2578 */ 2579 2580 /* 2581 * @IWX_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed. 2582 * @IWX_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only 2583 * the first fragment is scheduled. 2584 * @IWX_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only 2585 * the first 2 fragments are scheduled. 2586 * @IWX_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any 2587 * number of fragments are valid. 2588 * 2589 * Other than the constant defined above, specifying a fragmentation value 'x' 2590 * means that the event can be fragmented but only the first 'x' will be 2591 * scheduled. 2592 */ 2593 #define IWX_TE_V2_FRAG_NONE 0 2594 #define IWX_TE_V2_FRAG_SINGLE 1 2595 #define IWX_TE_V2_FRAG_DUAL 2 2596 #define IWX_TE_V2_FRAG_MAX 0xfe 2597 #define IWX_TE_V2_FRAG_ENDLESS 0xff 2598 2599 /* Repeat the time event endlessly (until removed) */ 2600 #define IWX_TE_V2_REPEAT_ENDLESS 0xff 2601 /* If a Time Event has bounded repetitions, this is the maximal value */ 2602 #define IWX_TE_V2_REPEAT_MAX 0xfe 2603 2604 #define IWX_TE_V2_PLACEMENT_POS 12 2605 #define IWX_TE_V2_ABSENCE_POS 15 2606 2607 /* Time event policy values 2608 * A notification (both event and fragment) includes a status indicating weather 2609 * the FW was able to schedule the event or not. For fragment start/end 2610 * notification the status is always success. There is no start/end fragment 2611 * notification for monolithic events. 2612 * 2613 * @IWX_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable 2614 * @IWX_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start 2615 * @IWX_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end 2616 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use 2617 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use. 2618 * @IWX_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start 2619 * @IWX_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end 2620 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use. 2621 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use. 2622 * @IWX_TE_V2_DEP_OTHER: depends on another time event 2623 * @IWX_TE_V2_DEP_TSF: depends on a specific time 2624 * @IWX_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC 2625 * @IWX_TE_V2_ABSENCE: are we present or absent during the Time Event. 2626 */ 2627 #define IWX_TE_V2_DEFAULT_POLICY 0x0 2628 2629 /* notifications (event start/stop, fragment start/stop) */ 2630 #define IWX_TE_V2_NOTIF_HOST_EVENT_START (1 << 0) 2631 #define IWX_TE_V2_NOTIF_HOST_EVENT_END (1 << 1) 2632 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2) 2633 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3) 2634 2635 #define IWX_TE_V2_NOTIF_HOST_FRAG_START (1 << 4) 2636 #define IWX_TE_V2_NOTIF_HOST_FRAG_END (1 << 5) 2637 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6) 2638 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7) 2639 #define IWX_T2_V2_START_IMMEDIATELY (1 << 11) 2640 2641 #define IWX_TE_V2_NOTIF_MSK 0xff 2642 2643 /* placement characteristics */ 2644 #define IWX_TE_V2_DEP_OTHER (1 << IWX_TE_V2_PLACEMENT_POS) 2645 #define IWX_TE_V2_DEP_TSF (1 << (IWX_TE_V2_PLACEMENT_POS + 1)) 2646 #define IWX_TE_V2_EVENT_SOCIOPATHIC (1 << (IWX_TE_V2_PLACEMENT_POS + 2)) 2647 2648 /* are we present or absent during the Time Event. */ 2649 #define IWX_TE_V2_ABSENCE (1 << IWX_TE_V2_ABSENCE_POS) 2650 2651 /** 2652 * struct iwx_time_event_cmd_api - configuring Time Events 2653 * with struct IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also 2654 * with version 1. determined by IWX_UCODE_TLV_FLAGS) 2655 * ( IWX_TIME_EVENT_CMD = 0x29 ) 2656 * @id_and_color: ID and color of the relevant MAC 2657 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 2658 * @id: this field has two meanings, depending on the action: 2659 * If the action is ADD, then it means the type of event to add. 2660 * For all other actions it is the unique event ID assigned when the 2661 * event was added by the FW. 2662 * @apply_time: When to start the Time Event (in GP2) 2663 * @max_delay: maximum delay to event's start (apply time), in TU 2664 * @depends_on: the unique ID of the event we depend on (if any) 2665 * @interval: interval between repetitions, in TU 2666 * @duration: duration of event in TU 2667 * @repeat: how many repetitions to do, can be IWX_TE_REPEAT_ENDLESS 2668 * @max_frags: maximal number of fragments the Time Event can be divided to 2669 * @policy: defines whether uCode shall notify the host or other uCode modules 2670 * on event and/or fragment start and/or end 2671 * using one of IWX_TE_INDEPENDENT, IWX_TE_DEP_OTHER, IWX_TE_DEP_TSF 2672 * IWX_TE_EVENT_SOCIOPATHIC 2673 * using IWX_TE_ABSENCE and using IWX_TE_NOTIF_* 2674 */ 2675 struct iwx_time_event_cmd { 2676 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2677 uint32_t id_and_color; 2678 uint32_t action; 2679 uint32_t id; 2680 /* IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 */ 2681 uint32_t apply_time; 2682 uint32_t max_delay; 2683 uint32_t depends_on; 2684 uint32_t interval; 2685 uint32_t duration; 2686 uint8_t repeat; 2687 uint8_t max_frags; 2688 uint16_t policy; 2689 } __packed; /* IWX_MAC_TIME_EVENT_CMD_API_S_VER_2 */ 2690 2691 /** 2692 * struct iwx_time_event_resp - response structure to iwx_time_event_cmd 2693 * @status: bit 0 indicates success, all others specify errors 2694 * @id: the Time Event type 2695 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE 2696 * @id_and_color: ID and color of the relevant MAC 2697 */ 2698 struct iwx_time_event_resp { 2699 uint32_t status; 2700 uint32_t id; 2701 uint32_t unique_id; 2702 uint32_t id_and_color; 2703 } __packed; /* IWX_MAC_TIME_EVENT_RSP_API_S_VER_1 */ 2704 2705 /** 2706 * struct iwx_time_event_notif - notifications of time event start/stop 2707 * ( IWX_TIME_EVENT_NOTIFICATION = 0x2a ) 2708 * @timestamp: action timestamp in GP2 2709 * @session_id: session's unique id 2710 * @unique_id: unique id of the Time Event itself 2711 * @id_and_color: ID and color of the relevant MAC 2712 * @action: one of IWX_TE_NOTIF_START or IWX_TE_NOTIF_END 2713 * @status: true if scheduled, false otherwise (not executed) 2714 */ 2715 struct iwx_time_event_notif { 2716 uint32_t timestamp; 2717 uint32_t session_id; 2718 uint32_t unique_id; 2719 uint32_t id_and_color; 2720 uint32_t action; 2721 uint32_t status; 2722 } __packed; /* IWX_MAC_TIME_EVENT_NTFY_API_S_VER_1 */ 2723 2724 2725 /* Bindings and Time Quota */ 2726 2727 /** 2728 * struct iwx_binding_cmd - configuring bindings 2729 * ( IWX_BINDING_CONTEXT_CMD = 0x2b ) 2730 * @id_and_color: ID and color of the relevant Binding 2731 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 2732 * @macs: array of MAC id and colors which belong to the binding 2733 * @phy: PHY id and color which belongs to the binding 2734 * @lmac_id: the lmac id the binding belongs to 2735 */ 2736 struct iwx_binding_cmd { 2737 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2738 uint32_t id_and_color; 2739 uint32_t action; 2740 /* IWX_BINDING_DATA_API_S_VER_1 */ 2741 uint32_t macs[IWX_MAX_MACS_IN_BINDING]; 2742 uint32_t phy; 2743 uint32_t lmac_id; 2744 } __packed; /* IWX_BINDING_CMD_API_S_VER_2 */ 2745 2746 #define IWX_LMAC_24G_INDEX 0 2747 #define IWX_LMAC_5G_INDEX 1 2748 2749 /* The maximal number of fragments in the FW's schedule session */ 2750 #define IWX_MAX_QUOTA 128 2751 2752 /** 2753 * struct iwx_time_quota_data - configuration of time quota per binding 2754 * @id_and_color: ID and color of the relevant Binding 2755 * @quota: absolute time quota in TU. The scheduler will try to divide the 2756 * remainig quota (after Time Events) according to this quota. 2757 * @max_duration: max uninterrupted context duration in TU 2758 */ 2759 struct iwx_time_quota_data { 2760 uint32_t id_and_color; 2761 uint32_t quota; 2762 uint32_t max_duration; 2763 } __packed; /* IWX_TIME_QUOTA_DATA_API_S_VER_1 */ 2764 2765 /** 2766 * struct iwx_time_quota_cmd - configuration of time quota between bindings 2767 * ( IWX_TIME_QUOTA_CMD = 0x2c ) 2768 * @quotas: allocations per binding 2769 */ 2770 struct iwx_time_quota_cmd { 2771 struct iwx_time_quota_data quotas[IWX_MAX_BINDINGS]; 2772 } __packed; /* IWX_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */ 2773 2774 2775 /* PHY context */ 2776 2777 /* Supported bands */ 2778 #define IWX_PHY_BAND_5 (0) 2779 #define IWX_PHY_BAND_24 (1) 2780 2781 /* Supported channel width, vary if there is VHT support */ 2782 #define IWX_PHY_VHT_CHANNEL_MODE20 (0x0) 2783 #define IWX_PHY_VHT_CHANNEL_MODE40 (0x1) 2784 #define IWX_PHY_VHT_CHANNEL_MODE80 (0x2) 2785 #define IWX_PHY_VHT_CHANNEL_MODE160 (0x3) 2786 2787 /* 2788 * Control channel position: 2789 * For legacy set bit means upper channel, otherwise lower. 2790 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 2791 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 2792 * center_freq 2793 * | 2794 * 40Mhz |_______|_______| 2795 * 80Mhz |_______|_______|_______|_______| 2796 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 2797 * code 011 010 001 000 | 100 101 110 111 2798 */ 2799 #define IWX_PHY_VHT_CTRL_POS_1_BELOW (0x0) 2800 #define IWX_PHY_VHT_CTRL_POS_2_BELOW (0x1) 2801 #define IWX_PHY_VHT_CTRL_POS_3_BELOW (0x2) 2802 #define IWX_PHY_VHT_CTRL_POS_4_BELOW (0x3) 2803 #define IWX_PHY_VHT_CTRL_POS_1_ABOVE (0x4) 2804 #define IWX_PHY_VHT_CTRL_POS_2_ABOVE (0x5) 2805 #define IWX_PHY_VHT_CTRL_POS_3_ABOVE (0x6) 2806 #define IWX_PHY_VHT_CTRL_POS_4_ABOVE (0x7) 2807 2808 /* 2809 * @band: IWX_PHY_BAND_* 2810 * @channel: channel number 2811 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2812 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2813 */ 2814 struct iwx_fw_channel_info_v1 { 2815 uint8_t band; 2816 uint8_t channel; 2817 uint8_t width; 2818 uint8_t ctrl_pos; 2819 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */ 2820 2821 /* 2822 * struct iwx_fw_channel_info - channel information 2823 * 2824 * @channel: channel number 2825 * @band: PHY_BAND_* 2826 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 2827 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 2828 * @reserved: for future use and alignment 2829 */ 2830 struct iwx_fw_channel_info { 2831 uint32_t channel; 2832 uint8_t band; 2833 uint8_t width; 2834 uint8_t ctrl_pos; 2835 uint8_t reserved; 2836 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */ 2837 2838 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 2839 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 2840 (0x1 << IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS) 2841 #define IWX_PHY_RX_CHAIN_VALID_POS (1) 2842 #define IWX_PHY_RX_CHAIN_VALID_MSK \ 2843 (0x7 << IWX_PHY_RX_CHAIN_VALID_POS) 2844 #define IWX_PHY_RX_CHAIN_FORCE_SEL_POS (4) 2845 #define IWX_PHY_RX_CHAIN_FORCE_SEL_MSK \ 2846 (0x7 << IWX_PHY_RX_CHAIN_FORCE_SEL_POS) 2847 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 2848 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 2849 (0x7 << IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 2850 #define IWX_PHY_RX_CHAIN_CNT_POS (10) 2851 #define IWX_PHY_RX_CHAIN_CNT_MSK \ 2852 (0x3 << IWX_PHY_RX_CHAIN_CNT_POS) 2853 #define IWX_PHY_RX_CHAIN_MIMO_CNT_POS (12) 2854 #define IWX_PHY_RX_CHAIN_MIMO_CNT_MSK \ 2855 (0x3 << IWX_PHY_RX_CHAIN_MIMO_CNT_POS) 2856 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_POS (14) 2857 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_MSK \ 2858 (0x1 << IWX_PHY_RX_CHAIN_MIMO_FORCE_POS) 2859 2860 /* TODO: fix the value, make it depend on firmware at runtime? */ 2861 #define IWX_NUM_PHY_CTX 3 2862 2863 /* TODO: complete missing documentation */ 2864 /** 2865 * struct iwx_phy_context_cmd - config of the PHY context 2866 * ( IWX_PHY_CONTEXT_CMD = 0x8 ) 2867 * @id_and_color: ID and color of the relevant Binding 2868 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 2869 * @apply_time: 0 means immediate apply and context switch. 2870 * other value means apply new params after X usecs 2871 * @tx_param_color: ??? 2872 * @channel_info: 2873 * @txchain_info: ??? 2874 * @rxchain_info: ??? 2875 * @acquisition_data: ??? 2876 * @dsp_cfg_flags: set to 0 2877 */ 2878 /* 2879 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased 2880 * the size of fw_channel_info from v1 to v2. 2881 * To keep things simple we define two versions of this struct, and both 2882 * are labled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark 2883 * magic with pointers to struct members instead.) 2884 */ 2885 /* This version must be used if IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */ 2886 struct iwx_phy_context_cmd_uhb { 2887 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2888 uint32_t id_and_color; 2889 uint32_t action; 2890 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */ 2891 uint32_t apply_time; 2892 uint32_t tx_param_color; 2893 struct iwx_fw_channel_info ci; 2894 uint32_t txchain_info; 2895 uint32_t rxchain_info; 2896 uint32_t acquisition_data; 2897 uint32_t dsp_cfg_flags; 2898 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */ 2899 /* This version must be used otherwise: */ 2900 struct iwx_phy_context_cmd { 2901 /* COMMON_INDEX_HDR_API_S_VER_1 */ 2902 uint32_t id_and_color; 2903 uint32_t action; 2904 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */ 2905 uint32_t apply_time; 2906 uint32_t tx_param_color; 2907 struct iwx_fw_channel_info_v1 ci; 2908 uint32_t txchain_info; 2909 uint32_t rxchain_info; 2910 uint32_t acquisition_data; 2911 uint32_t dsp_cfg_flags; 2912 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */ 2913 2914 2915 #define IWX_RX_INFO_PHY_CNT 8 2916 #define IWX_RX_INFO_ENERGY_ANT_ABC_IDX 1 2917 #define IWX_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 2918 #define IWX_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 2919 #define IWX_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 2920 #define IWX_RX_INFO_ENERGY_ANT_A_POS 0 2921 #define IWX_RX_INFO_ENERGY_ANT_B_POS 8 2922 #define IWX_RX_INFO_ENERGY_ANT_C_POS 16 2923 2924 #define IWX_RX_INFO_AGC_IDX 1 2925 #define IWX_RX_INFO_RSSI_AB_IDX 2 2926 #define IWX_OFDM_AGC_A_MSK 0x0000007f 2927 #define IWX_OFDM_AGC_A_POS 0 2928 #define IWX_OFDM_AGC_B_MSK 0x00003f80 2929 #define IWX_OFDM_AGC_B_POS 7 2930 #define IWX_OFDM_AGC_CODE_MSK 0x3fe00000 2931 #define IWX_OFDM_AGC_CODE_POS 20 2932 #define IWX_OFDM_RSSI_INBAND_A_MSK 0x00ff 2933 #define IWX_OFDM_RSSI_A_POS 0 2934 #define IWX_OFDM_RSSI_ALLBAND_A_MSK 0xff00 2935 #define IWX_OFDM_RSSI_ALLBAND_A_POS 8 2936 #define IWX_OFDM_RSSI_INBAND_B_MSK 0xff0000 2937 #define IWX_OFDM_RSSI_B_POS 16 2938 #define IWX_OFDM_RSSI_ALLBAND_B_MSK 0xff000000 2939 #define IWX_OFDM_RSSI_ALLBAND_B_POS 24 2940 2941 /** 2942 * struct iwx_rx_phy_info - phy info 2943 * (IWX_REPLY_RX_PHY_CMD = 0xc0) 2944 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 2945 * @cfg_phy_cnt: configurable DSP phy data byte count 2946 * @stat_id: configurable DSP phy data set ID 2947 * @reserved1: 2948 * @system_timestamp: GP2 at on air rise 2949 * @timestamp: TSF at on air rise 2950 * @beacon_time_stamp: beacon at on-air rise 2951 * @phy_flags: general phy flags: band, modulation, ... 2952 * @channel: channel number 2953 * @non_cfg_phy_buf: for various implementations of non_cfg_phy 2954 * @rate_n_flags: IWX_RATE_MCS_* 2955 * @byte_count: frame's byte-count 2956 * @frame_time: frame's time on the air, based on byte count and frame rate 2957 * calculation 2958 * @mac_active_msk: what MACs were active when the frame was received 2959 * 2960 * Before each Rx, the device sends this data. It contains PHY information 2961 * about the reception of the packet. 2962 */ 2963 struct iwx_rx_phy_info { 2964 uint8_t non_cfg_phy_cnt; 2965 uint8_t cfg_phy_cnt; 2966 uint8_t stat_id; 2967 uint8_t reserved1; 2968 uint32_t system_timestamp; 2969 uint64_t timestamp; 2970 uint32_t beacon_time_stamp; 2971 uint16_t phy_flags; 2972 #define IWX_PHY_INFO_FLAG_SHPREAMBLE (1 << 2) 2973 uint16_t channel; 2974 uint32_t non_cfg_phy[IWX_RX_INFO_PHY_CNT]; 2975 uint32_t rate_n_flags; 2976 uint32_t byte_count; 2977 uint16_t mac_active_msk; 2978 uint16_t frame_time; 2979 } __packed; 2980 2981 struct iwx_rx_mpdu_res_start { 2982 uint16_t byte_count; 2983 uint16_t reserved; 2984 } __packed; 2985 2986 /** 2987 * Values to parse %iwx_rx_phy_info phy_flags 2988 * @IWX_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 2989 * @IWX_RX_RES_PHY_FLAGS_MOD_CCK: 2990 * @IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 2991 * @IWX_RX_RES_PHY_FLAGS_NARROW_BAND: 2992 * @IWX_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 2993 * @IWX_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 2994 * @IWX_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 2995 * @IWX_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 2996 * @IWX_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 2997 */ 2998 #define IWX_RX_RES_PHY_FLAGS_BAND_24 (1 << 0) 2999 #define IWX_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1) 3000 #define IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2) 3001 #define IWX_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3) 3002 #define IWX_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4) 3003 #define IWX_RX_RES_PHY_FLAGS_ANTENNA_POS 4 3004 #define IWX_RX_RES_PHY_FLAGS_AGG (1 << 7) 3005 #define IWX_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8) 3006 #define IWX_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9) 3007 #define IWX_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10) 3008 3009 /** 3010 * Values written by fw for each Rx packet 3011 * @IWX_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 3012 * @IWX_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 3013 * @IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND: 3014 * @IWX_RX_MPDU_RES_STATUS_KEY_VALID: 3015 * @IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK: 3016 * @IWX_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 3017 * @IWX_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 3018 * in the driver. 3019 * @IWX_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 3020 * @IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 3021 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 3022 * %IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 3023 * @IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 3024 * @IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 3025 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 3026 * @IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 3027 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC 3028 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 3029 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 3030 * @IWX_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 3031 * @IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: 3032 * @IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: 3033 * @IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: 3034 * @IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 3035 * @IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: 3036 * @IWX_RX_MPDU_RES_STATUS_STA_ID_MSK: 3037 * @IWX_RX_MPDU_RES_STATUS_RRF_KILL: 3038 * @IWX_RX_MPDU_RES_STATUS_FILTERING_MSK: 3039 * @IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK: 3040 */ 3041 #define IWX_RX_MPDU_RES_STATUS_CRC_OK (1 << 0) 3042 #define IWX_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1) 3043 #define IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2) 3044 #define IWX_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3) 3045 #define IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4) 3046 #define IWX_RX_MPDU_RES_STATUS_ICV_OK (1 << 5) 3047 #define IWX_RX_MPDU_RES_STATUS_MIC_OK (1 << 6) 3048 #define IWX_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7) 3049 #define IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7) 3050 #define IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8) 3051 #define IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8) 3052 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8) 3053 #define IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8) 3054 #define IWX_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8) 3055 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8) 3056 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8) 3057 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8) 3058 #define IWX_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11) 3059 #define IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12) 3060 #define IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13) 3061 #define IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14) 3062 #define IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15) 3063 #define IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000) 3064 #define IWX_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000) 3065 #define IWX_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29) 3066 #define IWX_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000) 3067 #define IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000) 3068 3069 #define IWX_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03 3070 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0 3071 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3 3072 3073 #define IWX_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f 3074 #define IWX_RX_MPDU_MFLG2_PAD 0x20 3075 #define IWX_RX_MPDU_MFLG2_AMSDU 0x40 3076 3077 #define IWX_RX_MPDU_PHY_AMPDU (1 << 5) 3078 #define IWX_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6) 3079 #define IWX_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7) 3080 #define IWX_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7) 3081 #define IWX_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8) 3082 3083 struct iwx_rx_mpdu_desc_v1 { 3084 union { 3085 uint32_t rss_hash; 3086 uint32_t phy_data2; 3087 }; 3088 union { 3089 uint32_t filter_match; 3090 uint32_t phy_data3; 3091 }; 3092 uint32_t rate_n_flags; 3093 uint8_t energy_a; 3094 uint8_t energy_b; 3095 uint8_t channel; 3096 uint8_t mac_context; 3097 uint32_t gp2_on_air_rise; 3098 union { 3099 uint64_t tsf_on_air_rise; 3100 struct { 3101 uint32_t phy_data0; 3102 uint32_t phy_data1; 3103 }; 3104 }; 3105 } __packed; 3106 3107 struct iwx_rx_mpdu_desc { 3108 uint16_t mpdu_len; 3109 uint8_t mac_flags1; 3110 uint8_t mac_flags2; 3111 uint8_t amsdu_info; 3112 uint16_t phy_info; 3113 uint8_t mac_phy_idx; 3114 uint16_t raw_csum; 3115 union { 3116 uint16_t l3l4_flags; 3117 uint16_t phy_data4; 3118 }; 3119 uint16_t status; 3120 uint8_t hash_filter; 3121 uint8_t sta_id_flags; 3122 uint32_t reorder_data; 3123 struct iwx_rx_mpdu_desc_v1 v1; 3124 } __packed; 3125 3126 /** 3127 * struct iwx_radio_version_notif - information on the radio version 3128 * ( IWX_RADIO_VERSION_NOTIFICATION = 0x68 ) 3129 * @radio_flavor: 3130 * @radio_step: 3131 * @radio_dash: 3132 */ 3133 struct iwx_radio_version_notif { 3134 uint32_t radio_flavor; 3135 uint32_t radio_step; 3136 uint32_t radio_dash; 3137 } __packed; /* IWX_RADIO_VERSION_NOTOFICATION_S_VER_1 */ 3138 3139 #define IWX_CARD_ENABLED 0x00 3140 #define IWX_HW_CARD_DISABLED 0x01 3141 #define IWX_SW_CARD_DISABLED 0x02 3142 #define IWX_CT_KILL_CARD_DISABLED 0x04 3143 #define IWX_HALT_CARD_DISABLED 0x08 3144 #define IWX_CARD_DISABLED_MSK 0x0f 3145 #define IWX_CARD_IS_RX_ON 0x10 3146 3147 /** 3148 * struct iwx_radio_version_notif - information on the radio version 3149 * (IWX_CARD_STATE_NOTIFICATION = 0xa1 ) 3150 * @flags: %iwx_card_state_flags 3151 */ 3152 struct iwx_card_state_notif { 3153 uint32_t flags; 3154 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */ 3155 3156 /** 3157 * struct iwx_missed_beacons_notif - information on missed beacons 3158 * ( IWX_MISSED_BEACONS_NOTIFICATION = 0xa2 ) 3159 * @mac_id: interface ID 3160 * @consec_missed_beacons_since_last_rx: number of consecutive missed 3161 * beacons since last RX. 3162 * @consec_missed_beacons: number of consecutive missed beacons 3163 * @num_expected_beacons: 3164 * @num_recvd_beacons: 3165 */ 3166 struct iwx_missed_beacons_notif { 3167 uint32_t mac_id; 3168 uint32_t consec_missed_beacons_since_last_rx; 3169 uint32_t consec_missed_beacons; 3170 uint32_t num_expected_beacons; 3171 uint32_t num_recvd_beacons; 3172 } __packed; /* IWX_MISSED_BEACON_NTFY_API_S_VER_3 */ 3173 3174 /** 3175 * struct iwx_mfuart_load_notif - mfuart image version & status 3176 * ( IWX_MFUART_LOAD_NOTIFICATION = 0xb1 ) 3177 * @installed_ver: installed image version 3178 * @external_ver: external image version 3179 * @status: MFUART loading status 3180 * @duration: MFUART loading time 3181 */ 3182 struct iwx_mfuart_load_notif { 3183 uint32_t installed_ver; 3184 uint32_t external_ver; 3185 uint32_t status; 3186 uint32_t duration; 3187 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/ 3188 3189 /** 3190 * struct iwx_set_calib_default_cmd - set default value for calibration. 3191 * ( IWX_SET_CALIB_DEFAULT_CMD = 0x8e ) 3192 * @calib_index: the calibration to set value for 3193 * @length: of data 3194 * @data: the value to set for the calibration result 3195 */ 3196 struct iwx_set_calib_default_cmd { 3197 uint16_t calib_index; 3198 uint16_t length; 3199 uint8_t data[0]; 3200 } __packed; /* IWX_PHY_CALIB_OVERRIDE_VALUES_S */ 3201 3202 #define IWX_MAX_PORT_ID_NUM 2 3203 #define IWX_MAX_MCAST_FILTERING_ADDRESSES 256 3204 3205 /** 3206 * struct iwx_mcast_filter_cmd - configure multicast filter. 3207 * @filter_own: Set 1 to filter out multicast packets sent by station itself 3208 * @port_id: Multicast MAC addresses array specifier. This is a strange way 3209 * to identify network interface adopted in host-device IF. 3210 * It is used by FW as index in array of addresses. This array has 3211 * IWX_MAX_PORT_ID_NUM members. 3212 * @count: Number of MAC addresses in the array 3213 * @pass_all: Set 1 to pass all multicast packets. 3214 * @bssid: current association BSSID. 3215 * @addr_list: Place holder for array of MAC addresses. 3216 * IMPORTANT: add padding if necessary to ensure DWORD alignment. 3217 */ 3218 struct iwx_mcast_filter_cmd { 3219 uint8_t filter_own; 3220 uint8_t port_id; 3221 uint8_t count; 3222 uint8_t pass_all; 3223 uint8_t bssid[6]; 3224 uint8_t reserved[2]; 3225 uint8_t addr_list[0]; 3226 } __packed; /* IWX_MCAST_FILTERING_CMD_API_S_VER_1 */ 3227 3228 struct iwx_statistics_dbg { 3229 uint32_t burst_check; 3230 uint32_t burst_count; 3231 uint32_t wait_for_silence_timeout_cnt; 3232 uint32_t reserved[3]; 3233 } __packed; /* IWX_STATISTICS_DEBUG_API_S_VER_2 */ 3234 3235 struct iwx_statistics_div { 3236 uint32_t tx_on_a; 3237 uint32_t tx_on_b; 3238 uint32_t exec_time; 3239 uint32_t probe_time; 3240 uint32_t rssi_ant; 3241 uint32_t reserved2; 3242 } __packed; /* IWX_STATISTICS_SLOW_DIV_API_S_VER_2 */ 3243 3244 struct iwx_statistics_bt_activity { 3245 uint32_t hi_priority_tx_req_cnt; 3246 uint32_t hi_priority_tx_denied_cnt; 3247 uint32_t lo_priority_tx_req_cnt; 3248 uint32_t lo_priority_tx_denied_cnt; 3249 uint32_t hi_priority_rx_req_cnt; 3250 uint32_t hi_priority_rx_denied_cnt; 3251 uint32_t lo_priority_rx_req_cnt; 3252 uint32_t lo_priority_rx_denied_cnt; 3253 } __packed; /* IWX_STATISTICS_BT_ACTIVITY_API_S_VER_1 */ 3254 3255 struct iwx_statistics_general_common { 3256 uint32_t radio_temperature; 3257 struct iwx_statistics_dbg dbg; 3258 uint32_t sleep_time; 3259 uint32_t slots_out; 3260 uint32_t slots_idle; 3261 uint32_t ttl_timestamp; 3262 struct iwx_statistics_div slow_div; 3263 uint32_t rx_enable_counter; 3264 /* 3265 * num_of_sos_states: 3266 * count the number of times we have to re-tune 3267 * in order to get out of bad PHY status 3268 */ 3269 uint32_t num_of_sos_states; 3270 uint32_t beacon_filtered; 3271 uint32_t missed_beacons; 3272 uint8_t beacon_filter_average_energy; 3273 uint8_t beacon_filter_reason; 3274 uint8_t beacon_filter_current_energy; 3275 uint8_t beacon_filter_reserved; 3276 uint32_t beacon_filter_delta_time; 3277 struct iwx_statistics_bt_activity bt_activity; 3278 uint64_t rx_time; 3279 uint64_t on_time_rf; 3280 uint64_t on_time_scan; 3281 uint64_t tx_time; 3282 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */ 3283 3284 struct iwx_statistics_rx_non_phy { 3285 uint32_t bogus_cts; /* CTS received when not expecting CTS */ 3286 uint32_t bogus_ack; /* ACK received when not expecting ACK */ 3287 uint32_t non_bssid_frames; /* number of frames with BSSID that 3288 * doesn't belong to the STA BSSID */ 3289 uint32_t filtered_frames; /* count frames that were dumped in the 3290 * filtering process */ 3291 uint32_t non_channel_beacons; /* beacons with our bss id but not on 3292 * our serving channel */ 3293 uint32_t channel_beacons; /* beacons with our bss id and in our 3294 * serving channel */ 3295 uint32_t num_missed_bcon; /* number of missed beacons */ 3296 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the 3297 * ADC was in saturation */ 3298 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched 3299 * for INA */ 3300 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */ 3301 uint32_t interference_data_flag; /* flag for interference data 3302 * availability. 1 when data is 3303 * available. */ 3304 uint32_t channel_load; /* counts RX Enable time in uSec */ 3305 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM 3306 * and CCK) counter */ 3307 uint32_t beacon_rssi_a; 3308 uint32_t beacon_rssi_b; 3309 uint32_t beacon_rssi_c; 3310 uint32_t beacon_energy_a; 3311 uint32_t beacon_energy_b; 3312 uint32_t beacon_energy_c; 3313 uint32_t num_bt_kills; 3314 uint32_t mac_id; 3315 uint32_t directed_data_mpdu; 3316 } __packed; /* IWX_STATISTICS_RX_NON_PHY_API_S_VER_3 */ 3317 3318 struct iwx_statistics_rx_phy { 3319 uint32_t ina_cnt; 3320 uint32_t fina_cnt; 3321 uint32_t plcp_err; 3322 uint32_t crc32_err; 3323 uint32_t overrun_err; 3324 uint32_t early_overrun_err; 3325 uint32_t crc32_good; 3326 uint32_t false_alarm_cnt; 3327 uint32_t fina_sync_err_cnt; 3328 uint32_t sfd_timeout; 3329 uint32_t fina_timeout; 3330 uint32_t unresponded_rts; 3331 uint32_t rxe_frame_limit_overrun; 3332 uint32_t sent_ack_cnt; 3333 uint32_t sent_cts_cnt; 3334 uint32_t sent_ba_rsp_cnt; 3335 uint32_t dsp_self_kill; 3336 uint32_t mh_format_err; 3337 uint32_t re_acq_main_rssi_sum; 3338 uint32_t reserved; 3339 } __packed; /* IWX_STATISTICS_RX_PHY_API_S_VER_2 */ 3340 3341 struct iwx_statistics_rx_ht_phy { 3342 uint32_t plcp_err; 3343 uint32_t overrun_err; 3344 uint32_t early_overrun_err; 3345 uint32_t crc32_good; 3346 uint32_t crc32_err; 3347 uint32_t mh_format_err; 3348 uint32_t agg_crc32_good; 3349 uint32_t agg_mpdu_cnt; 3350 uint32_t agg_cnt; 3351 uint32_t unsupport_mcs; 3352 } __packed; /* IWX_STATISTICS_HT_RX_PHY_API_S_VER_1 */ 3353 3354 /* 3355 * The first MAC indices (starting from 0) 3356 * are available to the driver, AUX follows 3357 */ 3358 #define IWX_MAC_INDEX_AUX 4 3359 #define IWX_MAC_INDEX_MIN_DRIVER 0 3360 #define IWX_NUM_MAC_INDEX_DRIVER IWX_MAC_INDEX_AUX 3361 3362 #define IWX_STATION_COUNT 16 3363 3364 #define IWX_MAX_CHAINS 3 3365 3366 struct iwx_statistics_tx_non_phy_agg { 3367 uint32_t ba_timeout; 3368 uint32_t ba_reschedule_frames; 3369 uint32_t scd_query_agg_frame_cnt; 3370 uint32_t scd_query_no_agg; 3371 uint32_t scd_query_agg; 3372 uint32_t scd_query_mismatch; 3373 uint32_t frame_not_ready; 3374 uint32_t underrun; 3375 uint32_t bt_prio_kill; 3376 uint32_t rx_ba_rsp_cnt; 3377 int8_t txpower[IWX_MAX_CHAINS]; 3378 int8_t reserved; 3379 uint32_t reserved2; 3380 } __packed; /* IWX_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */ 3381 3382 struct iwx_statistics_tx_channel_width { 3383 uint32_t ext_cca_narrow_ch20[1]; 3384 uint32_t ext_cca_narrow_ch40[2]; 3385 uint32_t ext_cca_narrow_ch80[3]; 3386 uint32_t ext_cca_narrow_ch160[4]; 3387 uint32_t last_tx_ch_width_indx; 3388 uint32_t rx_detected_per_ch_width[4]; 3389 uint32_t success_per_ch_width[4]; 3390 uint32_t fail_per_ch_width[4]; 3391 }; /* IWX_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */ 3392 3393 struct iwx_statistics_tx { 3394 uint32_t preamble_cnt; 3395 uint32_t rx_detected_cnt; 3396 uint32_t bt_prio_defer_cnt; 3397 uint32_t bt_prio_kill_cnt; 3398 uint32_t few_bytes_cnt; 3399 uint32_t cts_timeout; 3400 uint32_t ack_timeout; 3401 uint32_t expected_ack_cnt; 3402 uint32_t actual_ack_cnt; 3403 uint32_t dump_msdu_cnt; 3404 uint32_t burst_abort_next_frame_mismatch_cnt; 3405 uint32_t burst_abort_missing_next_frame_cnt; 3406 uint32_t cts_timeout_collision; 3407 uint32_t ack_or_ba_timeout_collision; 3408 struct iwx_statistics_tx_non_phy_agg agg; 3409 struct iwx_statistics_tx_channel_width channel_width; 3410 } __packed; /* IWX_STATISTICS_TX_API_S_VER_4 */ 3411 3412 struct iwx_statistics_general { 3413 struct iwx_statistics_general_common common; 3414 uint32_t beacon_counter[IWX_MAC_INDEX_AUX]; 3415 uint8_t beacon_average_energy[IWX_MAC_INDEX_AUX]; 3416 uint8_t reserved[8 - IWX_MAC_INDEX_AUX]; 3417 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */ 3418 3419 struct iwx_statistics_rx { 3420 struct iwx_statistics_rx_phy ofdm; 3421 struct iwx_statistics_rx_phy cck; 3422 struct iwx_statistics_rx_non_phy general; 3423 struct iwx_statistics_rx_ht_phy ofdm_ht; 3424 } __packed; /* IWX_STATISTICS_RX_API_S_VER_3 */ 3425 3426 /* 3427 * IWX_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command) 3428 * 3429 * By default, uCode issues this notification after receiving a beacon 3430 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the 3431 * IWX_REPLY_STATISTICS_CMD 0x9c, above. 3432 * 3433 * Statistics counters continue to increment beacon after beacon, but are 3434 * cleared when changing channels or when driver issues IWX_REPLY_STATISTICS_CMD 3435 * 0x9c with CLEAR_STATS bit set (see above). 3436 * 3437 * uCode also issues this notification during scans. uCode clears statistics 3438 * appropriately so that each notification contains statistics for only the 3439 * one channel that has just been scanned. 3440 */ 3441 3442 /** 3443 * struct iwx_statistics_load - RX statistics for multi-queue devices 3444 * @air_time: accumulated air time, per mac 3445 * @byte_count: accumulated byte count, per mac 3446 * @pkt_count: accumulated packet count, per mac 3447 * @avg_energy: average RSSI, per station 3448 */ 3449 struct iwx_statistics_load { 3450 uint32_t air_time[IWX_MAC_INDEX_AUX]; 3451 uint32_t byte_count[IWX_MAC_INDEX_AUX]; 3452 uint32_t pkt_count[IWX_MAC_INDEX_AUX]; 3453 uint8_t avg_energy[IWX_STATION_COUNT]; 3454 } __packed; /* STATISTICS_RX_MAC_STATION_S_VER_3 */ 3455 3456 struct iwx_notif_statistics { 3457 uint32_t flag; 3458 struct iwx_statistics_rx rx; 3459 struct iwx_statistics_tx tx; 3460 struct iwx_statistics_general general; 3461 struct iwx_statistics_load load_stats; 3462 } __packed; /* STATISTICS_NTFY_API_S_VER_13 */ 3463 3464 3465 /** 3466 * flags used in statistics notification 3467 * @IWX_STATISTICS_REPLY_FLG_CLEAR: statistics were cleared after this report 3468 */ 3469 #define IWX_STATISTICS_REPLY_FLG_CLEAR 0x01 3470 3471 /** 3472 * flags used in statistics command 3473 * @IWX_STATISTICS_FLG_CLEAR: request to clear statistics after the report 3474 * that's sent after this command 3475 * @IWX_STATISTICS_FLG_DISABLE_NOTIF: disable unilateral statistics 3476 * notifications 3477 */ 3478 #define IWX_STATISTICS_FLG_CLEAR 0x01 3479 #define IWX_STATISTICS_FLG_DISABLE_NOTIF 0x02 3480 3481 /** 3482 * struct iwx_statistics_cmd - statistics config command 3483 * @flags: IWX_STATISTICS_* flags 3484 */ 3485 struct iwx_statistics_cmd { 3486 uint32_t flags; 3487 } __packed; /* STATISTICS_CMD_API_S_VER_1 */ 3488 3489 3490 /*********************************** 3491 * Smart Fifo API 3492 ***********************************/ 3493 /* Smart Fifo state */ 3494 #define IWX_SF_LONG_DELAY_ON 0 /* should never be called by driver */ 3495 #define IWX_SF_FULL_ON 1 3496 #define IWX_SF_UNINIT 2 3497 #define IWX_SF_INIT_OFF 3 3498 #define IWX_SF_HW_NUM_STATES 4 3499 3500 /* Smart Fifo possible scenario */ 3501 #define IWX_SF_SCENARIO_SINGLE_UNICAST 0 3502 #define IWX_SF_SCENARIO_AGG_UNICAST 1 3503 #define IWX_SF_SCENARIO_MULTICAST 2 3504 #define IWX_SF_SCENARIO_BA_RESP 3 3505 #define IWX_SF_SCENARIO_TX_RESP 4 3506 #define IWX_SF_NUM_SCENARIO 5 3507 3508 #define IWX_SF_TRANSIENT_STATES_NUMBER 2 /* IWX_SF_LONG_DELAY_ON and IWX_SF_FULL_ON */ 3509 #define IWX_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */ 3510 3511 /* smart FIFO default values */ 3512 #define IWX_SF_W_MARK_SISO 4096 3513 #define IWX_SF_W_MARK_MIMO2 8192 3514 #define IWX_SF_W_MARK_MIMO3 6144 3515 #define IWX_SF_W_MARK_LEGACY 4096 3516 #define IWX_SF_W_MARK_SCAN 4096 3517 3518 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */ 3519 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3520 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3521 #define IWX_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */ 3522 #define IWX_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3523 #define IWX_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */ 3524 #define IWX_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3525 #define IWX_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */ 3526 #define IWX_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3527 #define IWX_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */ 3528 #define IWX_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */ 3529 3530 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */ 3531 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3532 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3533 #define IWX_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */ 3534 #define IWX_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */ 3535 #define IWX_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */ 3536 #define IWX_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */ 3537 #define IWX_SF_BA_IDLE_TIMER 320 /* 300 uSec */ 3538 #define IWX_SF_BA_AGING_TIMER 2016 /* 2 mSec */ 3539 #define IWX_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */ 3540 #define IWX_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */ 3541 3542 #define IWX_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */ 3543 3544 #define IWX_SF_CFG_DUMMY_NOTIF_OFF (1 << 16) 3545 3546 /** 3547 * Smart Fifo configuration command. 3548 * @state: smart fifo state, types listed in enum %iwx_sf_state. 3549 * @watermark: Minimum allowed availabe free space in RXF for transient state. 3550 * @long_delay_timeouts: aging and idle timer values for each scenario 3551 * in long delay state. 3552 * @full_on_timeouts: timer values for each scenario in full on state. 3553 */ 3554 struct iwx_sf_cfg_cmd { 3555 uint32_t state; 3556 uint32_t watermark[IWX_SF_TRANSIENT_STATES_NUMBER]; 3557 uint32_t long_delay_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES]; 3558 uint32_t full_on_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES]; 3559 } __packed; /* IWX_SF_CFG_API_S_VER_2 */ 3560 3561 #define IWX_AC_BK 0 3562 #define IWX_AC_BE 1 3563 #define IWX_AC_VI 2 3564 #define IWX_AC_VO 3 3565 #define IWX_AC_NUM 4 3566 3567 /** 3568 * MAC context flags 3569 * @IWX_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, 3570 * this will require CCK RTS/CTS2self. 3571 * RTS/CTS will protect full burst time. 3572 * @IWX_MAC_PROT_FLG_HT_PROT: enable HT protection 3573 * @IWX_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions 3574 * @IWX_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self 3575 */ 3576 #define IWX_MAC_PROT_FLG_TGG_PROTECT (1 << 3) 3577 #define IWX_MAC_PROT_FLG_HT_PROT (1 << 23) 3578 #define IWX_MAC_PROT_FLG_FAT_PROT (1 << 24) 3579 #define IWX_MAC_PROT_FLG_SELF_CTS_EN (1 << 30) 3580 3581 #define IWX_MAC_FLG_SHORT_SLOT (1 << 4) 3582 #define IWX_MAC_FLG_SHORT_PREAMBLE (1 << 5) 3583 3584 /** 3585 * Supported MAC types 3586 * @IWX_FW_MAC_TYPE_FIRST: lowest supported MAC type 3587 * @IWX_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) 3588 * @IWX_FW_MAC_TYPE_LISTENER: monitor MAC type (?) 3589 * @IWX_FW_MAC_TYPE_PIBSS: Pseudo-IBSS 3590 * @IWX_FW_MAC_TYPE_IBSS: IBSS 3591 * @IWX_FW_MAC_TYPE_BSS_STA: BSS (managed) station 3592 * @IWX_FW_MAC_TYPE_P2P_DEVICE: P2P Device 3593 * @IWX_FW_MAC_TYPE_P2P_STA: P2P client 3594 * @IWX_FW_MAC_TYPE_GO: P2P GO 3595 * @IWX_FW_MAC_TYPE_TEST: ? 3596 * @IWX_FW_MAC_TYPE_MAX: highest support MAC type 3597 */ 3598 #define IWX_FW_MAC_TYPE_FIRST 1 3599 #define IWX_FW_MAC_TYPE_AUX IWX_FW_MAC_TYPE_FIRST 3600 #define IWX_FW_MAC_TYPE_LISTENER 2 3601 #define IWX_FW_MAC_TYPE_PIBSS 3 3602 #define IWX_FW_MAC_TYPE_IBSS 4 3603 #define IWX_FW_MAC_TYPE_BSS_STA 5 3604 #define IWX_FW_MAC_TYPE_P2P_DEVICE 6 3605 #define IWX_FW_MAC_TYPE_P2P_STA 7 3606 #define IWX_FW_MAC_TYPE_GO 8 3607 #define IWX_FW_MAC_TYPE_TEST 9 3608 #define IWX_FW_MAC_TYPE_MAX IWX_FW_MAC_TYPE_TEST 3609 /* IWX_MAC_CONTEXT_TYPE_API_E_VER_1 */ 3610 3611 /** 3612 * TSF hw timer ID 3613 * @IWX_TSF_ID_A: use TSF A 3614 * @IWX_TSF_ID_B: use TSF B 3615 * @IWX_TSF_ID_C: use TSF C 3616 * @IWX_TSF_ID_D: use TSF D 3617 * @IWX_NUM_TSF_IDS: number of TSF timers available 3618 */ 3619 #define IWX_TSF_ID_A 0 3620 #define IWX_TSF_ID_B 1 3621 #define IWX_TSF_ID_C 2 3622 #define IWX_TSF_ID_D 3 3623 #define IWX_NUM_TSF_IDS 4 3624 /* IWX_TSF_ID_API_E_VER_1 */ 3625 3626 /** 3627 * struct iwx_mac_data_ap - configuration data for AP MAC context 3628 * @beacon_time: beacon transmit time in system time 3629 * @beacon_tsf: beacon transmit time in TSF 3630 * @bi: beacon interval in TU 3631 * @bi_reciprocal: 2^32 / bi 3632 * @dtim_interval: dtim transmit time in TU 3633 * @dtim_reciprocal: 2^32 / dtim_interval 3634 * @mcast_qid: queue ID for multicast traffic 3635 * NOTE: obsolete from VER2 and on 3636 * @beacon_template: beacon template ID 3637 */ 3638 struct iwx_mac_data_ap { 3639 uint32_t beacon_time; 3640 uint64_t beacon_tsf; 3641 uint32_t bi; 3642 uint32_t bi_reciprocal; 3643 uint32_t dtim_interval; 3644 uint32_t dtim_reciprocal; 3645 uint32_t mcast_qid; 3646 uint32_t beacon_template; 3647 } __packed; /* AP_MAC_DATA_API_S_VER_2 */ 3648 3649 /** 3650 * struct iwx_mac_data_ibss - configuration data for IBSS MAC context 3651 * @beacon_time: beacon transmit time in system time 3652 * @beacon_tsf: beacon transmit time in TSF 3653 * @bi: beacon interval in TU 3654 * @bi_reciprocal: 2^32 / bi 3655 * @beacon_template: beacon template ID 3656 */ 3657 struct iwx_mac_data_ibss { 3658 uint32_t beacon_time; 3659 uint64_t beacon_tsf; 3660 uint32_t bi; 3661 uint32_t bi_reciprocal; 3662 uint32_t beacon_template; 3663 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */ 3664 3665 /** 3666 * struct iwx_mac_data_sta - configuration data for station MAC context 3667 * @is_assoc: 1 for associated state, 0 otherwise 3668 * @dtim_time: DTIM arrival time in system time 3669 * @dtim_tsf: DTIM arrival time in TSF 3670 * @bi: beacon interval in TU, applicable only when associated 3671 * @bi_reciprocal: 2^32 / bi , applicable only when associated 3672 * @dtim_interval: DTIM interval in TU, applicable only when associated 3673 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated 3674 * @listen_interval: in beacon intervals, applicable only when associated 3675 * @assoc_id: unique ID assigned by the AP during association 3676 */ 3677 struct iwx_mac_data_sta { 3678 uint32_t is_assoc; 3679 uint32_t dtim_time; 3680 uint64_t dtim_tsf; 3681 uint32_t bi; 3682 uint32_t bi_reciprocal; 3683 uint32_t dtim_interval; 3684 uint32_t dtim_reciprocal; 3685 uint32_t listen_interval; 3686 uint32_t assoc_id; 3687 uint32_t assoc_beacon_arrive_time; 3688 } __packed; /* IWX_STA_MAC_DATA_API_S_VER_1 */ 3689 3690 /** 3691 * struct iwx_mac_data_go - configuration data for P2P GO MAC context 3692 * @ap: iwx_mac_data_ap struct with most config data 3693 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3694 * 0 indicates that there is no CT window. 3695 * @opp_ps_enabled: indicate that opportunistic PS allowed 3696 */ 3697 struct iwx_mac_data_go { 3698 struct iwx_mac_data_ap ap; 3699 uint32_t ctwin; 3700 uint32_t opp_ps_enabled; 3701 } __packed; /* GO_MAC_DATA_API_S_VER_1 */ 3702 3703 /** 3704 * struct iwx_mac_data_p2p_sta - configuration data for P2P client MAC context 3705 * @sta: iwx_mac_data_sta struct with most config data 3706 * @ctwin: client traffic window in TU (period after TBTT when GO is present). 3707 * 0 indicates that there is no CT window. 3708 */ 3709 struct iwx_mac_data_p2p_sta { 3710 struct iwx_mac_data_sta sta; 3711 uint32_t ctwin; 3712 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */ 3713 3714 /** 3715 * struct iwx_mac_data_pibss - Pseudo IBSS config data 3716 * @stats_interval: interval in TU between statistics notifications to host. 3717 */ 3718 struct iwx_mac_data_pibss { 3719 uint32_t stats_interval; 3720 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */ 3721 3722 /* 3723 * struct iwx_mac_data_p2p_dev - configuration data for the P2P Device MAC 3724 * context. 3725 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on 3726 * other channels as well. This should be to true only in case that the 3727 * device is discoverable and there is an active GO. Note that setting this 3728 * field when not needed, will increase the number of interrupts and have 3729 * effect on the platform power, as this setting opens the Rx filters on 3730 * all macs. 3731 */ 3732 struct iwx_mac_data_p2p_dev { 3733 uint32_t is_disc_extended; 3734 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */ 3735 3736 /** 3737 * MAC context filter flags 3738 * @IWX_MAC_FILTER_IN_PROMISC: accept all data frames 3739 * @IWX_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and 3740 * control frames to the host 3741 * @IWX_MAC_FILTER_ACCEPT_GRP: accept multicast frames 3742 * @IWX_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames 3743 * @IWX_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames 3744 * @IWX_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host 3745 * (in station mode when associated) 3746 * @IWX_MAC_FILTER_OUT_BCAST: filter out all broadcast frames 3747 * @IWX_MAC_FILTER_IN_CRC32: extract FCS and append it to frames 3748 * @IWX_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host 3749 */ 3750 #define IWX_MAC_FILTER_IN_PROMISC (1 << 0) 3751 #define IWX_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1) 3752 #define IWX_MAC_FILTER_ACCEPT_GRP (1 << 2) 3753 #define IWX_MAC_FILTER_DIS_DECRYPT (1 << 3) 3754 #define IWX_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4) 3755 #define IWX_MAC_FILTER_IN_BEACON (1 << 6) 3756 #define IWX_MAC_FILTER_OUT_BCAST (1 << 8) 3757 #define IWX_MAC_FILTER_IN_CRC32 (1 << 11) 3758 #define IWX_MAC_FILTER_IN_PROBE_REQUEST (1 << 12) 3759 3760 /** 3761 * QoS flags 3762 * @IWX_MAC_QOS_FLG_UPDATE_EDCA: ? 3763 * @IWX_MAC_QOS_FLG_TGN: HT is enabled 3764 * @IWX_MAC_QOS_FLG_TXOP_TYPE: ? 3765 * 3766 */ 3767 #define IWX_MAC_QOS_FLG_UPDATE_EDCA (1 << 0) 3768 #define IWX_MAC_QOS_FLG_TGN (1 << 1) 3769 #define IWX_MAC_QOS_FLG_TXOP_TYPE (1 << 4) 3770 3771 /** 3772 * struct iwx_ac_qos - QOS timing params for IWX_MAC_CONTEXT_CMD 3773 * @cw_min: Contention window, start value in numbers of slots. 3774 * Should be a power-of-2, minus 1. Device's default is 0x0f. 3775 * @cw_max: Contention window, max value in numbers of slots. 3776 * Should be a power-of-2, minus 1. Device's default is 0x3f. 3777 * @aifsn: Number of slots in Arbitration Interframe Space (before 3778 * performing random backoff timing prior to Tx). Device default 1. 3779 * @fifos_mask: FIFOs used by this MAC for this AC 3780 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0. 3781 * 3782 * One instance of this config struct for each of 4 EDCA access categories 3783 * in struct iwx_qosparam_cmd. 3784 * 3785 * Device will automatically increase contention window by (2*CW) + 1 for each 3786 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW 3787 * value, to cap the CW value. 3788 */ 3789 struct iwx_ac_qos { 3790 uint16_t cw_min; 3791 uint16_t cw_max; 3792 uint8_t aifsn; 3793 uint8_t fifos_mask; 3794 uint16_t edca_txop; 3795 } __packed; /* IWX_AC_QOS_API_S_VER_2 */ 3796 3797 /** 3798 * struct iwx_mac_ctx_cmd - command structure to configure MAC contexts 3799 * ( IWX_MAC_CONTEXT_CMD = 0x28 ) 3800 * @id_and_color: ID and color of the MAC 3801 * @action: action to perform, one of IWX_FW_CTXT_ACTION_* 3802 * @mac_type: one of IWX_FW_MAC_TYPE_* 3803 * @tsf_id: TSF HW timer, one of IWX_TSF_ID_* 3804 * @node_addr: MAC address 3805 * @bssid_addr: BSSID 3806 * @cck_rates: basic rates available for CCK 3807 * @ofdm_rates: basic rates available for OFDM 3808 * @protection_flags: combination of IWX_MAC_PROT_FLG_FLAG_* 3809 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise 3810 * @short_slot: 0x10 for enabling short slots, 0 otherwise 3811 * @filter_flags: combination of IWX_MAC_FILTER_* 3812 * @qos_flags: from IWX_MAC_QOS_FLG_* 3813 * @ac: one iwx_mac_qos configuration for each AC 3814 * @mac_specific: one of struct iwx_mac_data_*, according to mac_type 3815 */ 3816 struct iwx_mac_ctx_cmd { 3817 /* COMMON_INDEX_HDR_API_S_VER_1 */ 3818 uint32_t id_and_color; 3819 uint32_t action; 3820 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */ 3821 uint32_t mac_type; 3822 uint32_t tsf_id; 3823 uint8_t node_addr[6]; 3824 uint16_t reserved_for_node_addr; 3825 uint8_t bssid_addr[6]; 3826 uint16_t reserved_for_bssid_addr; 3827 uint32_t cck_rates; 3828 uint32_t ofdm_rates; 3829 uint32_t protection_flags; 3830 uint32_t cck_short_preamble; 3831 uint32_t short_slot; 3832 uint32_t filter_flags; 3833 /* IWX_MAC_QOS_PARAM_API_S_VER_1 */ 3834 uint32_t qos_flags; 3835 struct iwx_ac_qos ac[IWX_AC_NUM+1]; 3836 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S */ 3837 union { 3838 struct iwx_mac_data_ap ap; 3839 struct iwx_mac_data_go go; 3840 struct iwx_mac_data_sta sta; 3841 struct iwx_mac_data_p2p_sta p2p_sta; 3842 struct iwx_mac_data_p2p_dev p2p_dev; 3843 struct iwx_mac_data_pibss pibss; 3844 struct iwx_mac_data_ibss ibss; 3845 }; 3846 } __packed; /* IWX_MAC_CONTEXT_CMD_API_S_VER_1 */ 3847 3848 static inline uint32_t iwx_reciprocal(uint32_t v) 3849 { 3850 if (!v) 3851 return 0; 3852 return 0xFFFFFFFF / v; 3853 } 3854 3855 /* Power Management Commands, Responses, Notifications */ 3856 3857 /** 3858 * masks for LTR config command flags 3859 * @IWX_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status 3860 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow 3861 * memory access 3862 * @IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR 3863 * reg change 3864 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from 3865 * D0 to D3 3866 * @IWX_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register 3867 * @IWX_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register 3868 * @IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD 3869 */ 3870 #define IWX_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001 3871 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002 3872 #define IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004 3873 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008 3874 #define IWX_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010 3875 #define IWX_LTR_CFG_FLAG_SW_SET_LONG 0x00000020 3876 #define IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040 3877 3878 #define IWX_LTR_VALID_STATES_NUM 4 3879 3880 /** 3881 * struct iwx_ltr_config_cmd - configures the LTR 3882 * @flags: See %enum iwx_ltr_config_flags 3883 * @static_long: 3884 * @static_short: 3885 * @ltr_cfg_values: 3886 * @ltr_short_idle_timeout: 3887 */ 3888 struct iwx_ltr_config_cmd { 3889 uint32_t flags; 3890 uint32_t static_long; 3891 uint32_t static_short; 3892 uint32_t ltr_cfg_values[IWX_LTR_VALID_STATES_NUM]; 3893 uint32_t ltr_short_idle_timeout; 3894 } __packed; /* LTR_CAPABLE_API_S_VER_2 */ 3895 3896 /* Radio LP RX Energy Threshold measured in dBm */ 3897 #define IWX_POWER_LPRX_RSSI_THRESHOLD 75 3898 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MAX 94 3899 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MIN 30 3900 3901 /** 3902 * Masks for iwx_mac_power_cmd command flags 3903 * @IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off 3904 * receiver and transmitter. '0' - does not allow. 3905 * @IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, 3906 * '1' Driver enables PM (use rest of parameters) 3907 * @IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, 3908 * '1' PM could sleep over DTIM till listen Interval. 3909 * @IWX_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all 3910 * access categories are both delivery and trigger enabled. 3911 * @IWX_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and 3912 * PBW Snoozing enabled 3913 * @IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask 3914 * @IWX_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. 3915 * @IWX_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving 3916 * detection enablement 3917 */ 3918 #define IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 3919 #define IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1) 3920 #define IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2) 3921 #define IWX_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5) 3922 #define IWX_POWER_FLAGS_BT_SCO_ENA (1 << 8) 3923 #define IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9) 3924 #define IWX_POWER_FLAGS_LPRX_ENA_MSK (1 << 11) 3925 #define IWX_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12) 3926 3927 #define IWX_POWER_VEC_SIZE 5 3928 3929 /** 3930 * Masks for device power command flags 3931 * @IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: 3932 * '1' Allow to save power by turning off receiver and transmitter. 3933 * '0' Do not allow. This flag should be always set to '1' unless 3934 * one needs to disable actual power down for debug purposes. 3935 * @IWX_DEVICE_POWER_FLAGS_CAM_MSK: 3936 * '1' CAM (Continuous Active Mode) is set, power management is disabled. 3937 * '0' Power management is enabled, one of the power schemes is applied. 3938 */ 3939 #define IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0) 3940 #define IWX_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13) 3941 3942 /** 3943 * struct iwx_device_power_cmd - device wide power command. 3944 * IWX_POWER_TABLE_CMD = 0x77 (command, has simple generic response) 3945 * 3946 * @flags: Power table command flags from IWX_DEVICE_POWER_FLAGS_* 3947 */ 3948 struct iwx_device_power_cmd { 3949 /* PM_POWER_TABLE_CMD_API_S_VER_6 */ 3950 uint16_t flags; 3951 uint16_t reserved; 3952 } __packed; 3953 3954 /** 3955 * struct iwx_mac_power_cmd - New power command containing uAPSD support 3956 * IWX_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response) 3957 * @id_and_color: MAC contex identifier 3958 * @flags: Power table command flags from POWER_FLAGS_* 3959 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec. 3960 * Minimum allowed:- 3 * DTIM. Keep alive period must be 3961 * set regardless of power scheme or current power state. 3962 * FW use this value also when PM is disabled. 3963 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to 3964 * PSM transition - legacy PM 3965 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to 3966 * PSM transition - legacy PM 3967 * @sleep_interval: not in use 3968 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag 3969 * is set. For example, if it is required to skip over 3970 * one DTIM, this value need to be set to 2 (DTIM periods). 3971 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to 3972 * PSM transition - uAPSD 3973 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to 3974 * PSM transition - uAPSD 3975 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled. 3976 * Default: 80dbm 3977 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set 3978 * @snooze_interval: Maximum time between attempts to retrieve buffered data 3979 * from the AP [msec] 3980 * @snooze_window: A window of time in which PBW snoozing insures that all 3981 * packets received. It is also the minimum time from last 3982 * received unicast RX packet, before client stops snoozing 3983 * for data. [msec] 3984 * @snooze_step: TBD 3985 * @qndp_tid: TID client shall use for uAPSD QNDP triggers 3986 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for 3987 * each corresponding AC. 3988 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values. 3989 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct 3990 * values. 3991 * @heavy_tx_thld_packets: TX threshold measured in number of packets 3992 * @heavy_rx_thld_packets: RX threshold measured in number of packets 3993 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage 3994 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage 3995 * @limited_ps_threshold: 3996 */ 3997 struct iwx_mac_power_cmd { 3998 /* CONTEXT_DESC_API_T_VER_1 */ 3999 uint32_t id_and_color; 4000 4001 /* CLIENT_PM_POWER_TABLE_S_VER_1 */ 4002 uint16_t flags; 4003 uint16_t keep_alive_seconds; 4004 uint32_t rx_data_timeout; 4005 uint32_t tx_data_timeout; 4006 uint32_t rx_data_timeout_uapsd; 4007 uint32_t tx_data_timeout_uapsd; 4008 uint8_t lprx_rssi_threshold; 4009 uint8_t skip_dtim_periods; 4010 uint16_t snooze_interval; 4011 uint16_t snooze_window; 4012 uint8_t snooze_step; 4013 uint8_t qndp_tid; 4014 uint8_t uapsd_ac_flags; 4015 uint8_t uapsd_max_sp; 4016 uint8_t heavy_tx_thld_packets; 4017 uint8_t heavy_rx_thld_packets; 4018 uint8_t heavy_tx_thld_percentage; 4019 uint8_t heavy_rx_thld_percentage; 4020 uint8_t limited_ps_threshold; 4021 uint8_t reserved; 4022 } __packed; 4023 4024 #define IWX_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000) 4025 #define IWX_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000) 4026 4027 /* 4028 * struct iwx_uapsd_misbehaving_ap_notif - FW sends this notification when 4029 * associated AP is identified as improperly implementing uAPSD protocol. 4030 * IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78 4031 * @sta_id: index of station in uCode's station table - associated AP ID in 4032 * this context. 4033 */ 4034 struct iwx_uapsd_misbehaving_ap_notif { 4035 uint32_t sta_id; 4036 uint8_t mac_id; 4037 uint8_t reserved[3]; 4038 } __packed; 4039 4040 /** 4041 * struct iwx_beacon_filter_cmd 4042 * IWX_REPLY_BEACON_FILTERING_CMD = 0xd2 (command) 4043 * @id_and_color: MAC contex identifier 4044 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon 4045 * to driver if delta in Energy values calculated for this and last 4046 * passed beacon is greater than this threshold. Zero value means that 4047 * the Energy change is ignored for beacon filtering, and beacon will 4048 * not be forced to be sent to driver regardless of this delta. Typical 4049 * energy delta 5dB. 4050 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state. 4051 * Send beacon to driver if delta in Energy values calculated for this 4052 * and last passed beacon is greater than this threshold. Zero value 4053 * means that the Energy change is ignored for beacon filtering while in 4054 * Roaming state, typical energy delta 1dB. 4055 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values 4056 * calculated for current beacon is less than the threshold, use 4057 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta 4058 * Threshold. Typical energy threshold is -72dBm. 4059 * @bf_temp_threshold: This threshold determines the type of temperature 4060 * filtering (Slow or Fast) that is selected (Units are in Celsuis): 4061 * If the current temperature is above this threshold - Fast filter 4062 * will be used, If the current temperature is below this threshold - 4063 * Slow filter will be used. 4064 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values 4065 * calculated for this and the last passed beacon is greater than this 4066 * threshold. Zero value means that the temperature change is ignored for 4067 * beacon filtering; beacons will not be forced to be sent to driver 4068 * regardless of whether its temerature has been changed. 4069 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values 4070 * calculated for this and the last passed beacon is greater than this 4071 * threshold. Zero value means that the temperature change is ignored for 4072 * beacon filtering; beacons will not be forced to be sent to driver 4073 * regardless of whether its temerature has been changed. 4074 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled. 4075 * @bf_escape_timer: Send beacons to driver if no beacons were passed 4076 * for a specific period of time. Units: Beacons. 4077 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed 4078 * for a longer period of time then this escape-timeout. Units: Beacons. 4079 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled. 4080 * @bf_threshold_absolute_low: See below. 4081 * @bf_threshold_absolute_high: Send Beacon to driver if Energy value calculated 4082 * for this beacon crossed this absolute threshold. For the 'Increase' 4083 * direction the bf_energy_absolute_low[i] is used. For the 'Decrease' 4084 * direction the bf_energy_absolute_high[i] is used. Zero value means 4085 * that this specific threshold is ignored for beacon filtering, and 4086 * beacon will not be forced to be sent to driver due to this setting. 4087 */ 4088 struct iwx_beacon_filter_cmd { 4089 uint32_t bf_energy_delta; 4090 uint32_t bf_roaming_energy_delta; 4091 uint32_t bf_roaming_state; 4092 uint32_t bf_temp_threshold; 4093 uint32_t bf_temp_fast_filter; 4094 uint32_t bf_temp_slow_filter; 4095 uint32_t bf_enable_beacon_filter; 4096 uint32_t bf_debug_flag; 4097 uint32_t bf_escape_timer; 4098 uint32_t ba_escape_timer; 4099 uint32_t ba_enable_beacon_abort; 4100 uint32_t bf_threshold_absolute_low[2]; 4101 uint32_t bf_threshold_absolute_high[2]; 4102 } __packed; /* BEACON_FILTER_CONFIG_API_S_VER_4 */ 4103 4104 /* Beacon filtering and beacon abort */ 4105 #define IWX_BF_ENERGY_DELTA_DEFAULT 5 4106 #define IWX_BF_ENERGY_DELTA_MAX 255 4107 #define IWX_BF_ENERGY_DELTA_MIN 0 4108 4109 #define IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT 1 4110 #define IWX_BF_ROAMING_ENERGY_DELTA_MAX 255 4111 #define IWX_BF_ROAMING_ENERGY_DELTA_MIN 0 4112 4113 #define IWX_BF_ROAMING_STATE_DEFAULT 72 4114 #define IWX_BF_ROAMING_STATE_MAX 255 4115 #define IWX_BF_ROAMING_STATE_MIN 0 4116 4117 #define IWX_BF_TEMP_THRESHOLD_DEFAULT 112 4118 #define IWX_BF_TEMP_THRESHOLD_MAX 255 4119 #define IWX_BF_TEMP_THRESHOLD_MIN 0 4120 4121 #define IWX_BF_TEMP_FAST_FILTER_DEFAULT 1 4122 #define IWX_BF_TEMP_FAST_FILTER_MAX 255 4123 #define IWX_BF_TEMP_FAST_FILTER_MIN 0 4124 4125 #define IWX_BF_TEMP_SLOW_FILTER_DEFAULT 5 4126 #define IWX_BF_TEMP_SLOW_FILTER_MAX 255 4127 #define IWX_BF_TEMP_SLOW_FILTER_MIN 0 4128 4129 #define IWX_BF_ENABLE_BEACON_FILTER_DEFAULT 1 4130 4131 #define IWX_BF_DEBUG_FLAG_DEFAULT 0 4132 4133 #define IWX_BF_ESCAPE_TIMER_DEFAULT 50 4134 #define IWX_BF_ESCAPE_TIMER_MAX 1024 4135 #define IWX_BF_ESCAPE_TIMER_MIN 0 4136 4137 #define IWX_BA_ESCAPE_TIMER_DEFAULT 6 4138 #define IWX_BA_ESCAPE_TIMER_D3 9 4139 #define IWX_BA_ESCAPE_TIMER_MAX 1024 4140 #define IWX_BA_ESCAPE_TIMER_MIN 0 4141 4142 #define IWX_BA_ENABLE_BEACON_ABORT_DEFAULT 1 4143 4144 #define IWX_BF_CMD_CONFIG_DEFAULTS \ 4145 .bf_energy_delta = htole32(IWX_BF_ENERGY_DELTA_DEFAULT), \ 4146 .bf_roaming_energy_delta = \ 4147 htole32(IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT), \ 4148 .bf_roaming_state = htole32(IWX_BF_ROAMING_STATE_DEFAULT), \ 4149 .bf_temp_threshold = htole32(IWX_BF_TEMP_THRESHOLD_DEFAULT), \ 4150 .bf_temp_fast_filter = htole32(IWX_BF_TEMP_FAST_FILTER_DEFAULT), \ 4151 .bf_temp_slow_filter = htole32(IWX_BF_TEMP_SLOW_FILTER_DEFAULT), \ 4152 .bf_debug_flag = htole32(IWX_BF_DEBUG_FLAG_DEFAULT), \ 4153 .bf_escape_timer = htole32(IWX_BF_ESCAPE_TIMER_DEFAULT), \ 4154 .ba_escape_timer = htole32(IWX_BA_ESCAPE_TIMER_DEFAULT) 4155 4156 /* uCode API values for HT/VHT bit rates */ 4157 #define IWX_RATE_HT_SISO_MCS_0_PLCP 0 4158 #define IWX_RATE_HT_SISO_MCS_1_PLCP 1 4159 #define IWX_RATE_HT_SISO_MCS_2_PLCP 2 4160 #define IWX_RATE_HT_SISO_MCS_3_PLCP 3 4161 #define IWX_RATE_HT_SISO_MCS_4_PLCP 4 4162 #define IWX_RATE_HT_SISO_MCS_5_PLCP 5 4163 #define IWX_RATE_HT_SISO_MCS_6_PLCP 6 4164 #define IWX_RATE_HT_SISO_MCS_7_PLCP 7 4165 #define IWX_RATE_HT_MIMO2_MCS_8_PLCP 0x8 4166 #define IWX_RATE_HT_MIMO2_MCS_9_PLCP 0x9 4167 #define IWX_RATE_HT_MIMO2_MCS_10_PLCP 0xA 4168 #define IWX_RATE_HT_MIMO2_MCS_11_PLCP 0xB 4169 #define IWX_RATE_HT_MIMO2_MCS_12_PLCP 0xC 4170 #define IWX_RATE_HT_MIMO2_MCS_13_PLCP 0xD 4171 #define IWX_RATE_HT_MIMO2_MCS_14_PLCP 0xE 4172 #define IWX_RATE_HT_MIMO2_MCS_15_PLCP 0xF 4173 #define IWX_RATE_VHT_SISO_MCS_0_PLCP 0 4174 #define IWX_RATE_VHT_SISO_MCS_1_PLCP 1 4175 #define IWX_RATE_VHT_SISO_MCS_2_PLCP 2 4176 #define IWX_RATE_VHT_SISO_MCS_3_PLCP 3 4177 #define IWX_RATE_VHT_SISO_MCS_4_PLCP 4 4178 #define IWX_RATE_VHT_SISO_MCS_5_PLCP 5 4179 #define IWX_RATE_VHT_SISO_MCS_6_PLCP 6 4180 #define IWX_RATE_VHT_SISO_MCS_7_PLCP 7 4181 #define IWX_RATE_VHT_SISO_MCS_8_PLCP 8 4182 #define IWX_RATE_VHT_SISO_MCS_9_PLCP 9 4183 #define IWX_RATE_VHT_MIMO2_MCS_0_PLCP 0x10 4184 #define IWX_RATE_VHT_MIMO2_MCS_1_PLCP 0x11 4185 #define IWX_RATE_VHT_MIMO2_MCS_2_PLCP 0x12 4186 #define IWX_RATE_VHT_MIMO2_MCS_3_PLCP 0x13 4187 #define IWX_RATE_VHT_MIMO2_MCS_4_PLCP 0x14 4188 #define IWX_RATE_VHT_MIMO2_MCS_5_PLCP 0x15 4189 #define IWX_RATE_VHT_MIMO2_MCS_6_PLCP 0x16 4190 #define IWX_RATE_VHT_MIMO2_MCS_7_PLCP 0x17 4191 #define IWX_RATE_VHT_MIMO2_MCS_8_PLCP 0x18 4192 #define IWX_RATE_VHT_MIMO2_MCS_9_PLCP 0x19 4193 #define IWX_RATE_HT_SISO_MCS_INV_PLCP 0x20 4194 #define IWX_RATE_HT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4195 #define IWX_RATE_VHT_SISO_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4196 #define IWX_RATE_VHT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4197 #define IWX_RATE_HT_SISO_MCS_8_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4198 #define IWX_RATE_HT_SISO_MCS_9_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP 4199 4200 /* 4201 * These serve as indexes into struct iwx_rate iwx_rates[IWX_RIDX_MAX]. 4202 */ 4203 enum { 4204 IWX_RATE_1M_INDEX = 0, 4205 IWX_FIRST_CCK_RATE = IWX_RATE_1M_INDEX, 4206 IWX_RATE_2M_INDEX, 4207 IWX_RATE_5M_INDEX, 4208 IWX_RATE_11M_INDEX, 4209 IWX_LAST_CCK_RATE = IWX_RATE_11M_INDEX, 4210 IWX_RATE_6M_INDEX, 4211 IWX_FIRST_OFDM_RATE = IWX_RATE_6M_INDEX, 4212 IWX_RATE_MCS_0_INDEX = IWX_RATE_6M_INDEX, 4213 IWX_FIRST_HT_RATE = IWX_RATE_MCS_0_INDEX, 4214 IWX_FIRST_VHT_RATE = IWX_RATE_MCS_0_INDEX, 4215 IWX_RATE_9M_INDEX, 4216 IWX_RATE_12M_INDEX, 4217 IWX_RATE_MCS_1_INDEX = IWX_RATE_12M_INDEX, 4218 IWX_RATE_MCS_8_INDEX, 4219 IWX_FIRST_HT_MIMO2_RATE = IWX_RATE_MCS_8_INDEX, 4220 IWX_RATE_18M_INDEX, 4221 IWX_RATE_MCS_2_INDEX = IWX_RATE_18M_INDEX, 4222 IWX_RATE_24M_INDEX, 4223 IWX_RATE_MCS_3_INDEX = IWX_RATE_24M_INDEX, 4224 IWX_RATE_MCS_9_INDEX, 4225 IWX_RATE_36M_INDEX, 4226 IWX_RATE_MCS_4_INDEX = IWX_RATE_36M_INDEX, 4227 IWX_RATE_MCS_10_INDEX, 4228 IWX_RATE_48M_INDEX, 4229 IWX_RATE_MCS_5_INDEX = IWX_RATE_48M_INDEX, 4230 IWX_RATE_MCS_11_INDEX, 4231 IWX_RATE_54M_INDEX, 4232 IWX_RATE_MCS_6_INDEX = IWX_RATE_54M_INDEX, 4233 IWX_LAST_NON_HT_RATE = IWX_RATE_54M_INDEX, 4234 IWX_RATE_MCS_7_INDEX, 4235 IWX_LAST_HT_SISO_RATE = IWX_RATE_MCS_7_INDEX, 4236 IWX_RATE_MCS_12_INDEX, 4237 IWX_RATE_MCS_13_INDEX, 4238 IWX_RATE_MCS_14_INDEX, 4239 IWX_RATE_MCS_15_INDEX, 4240 IWX_LAST_HT_RATE = IWX_RATE_MCS_15_INDEX, 4241 IWX_LAST_VHT_RATE = IWX_RATE_MCS_9_INDEX, 4242 IWX_RATE_COUNT_LEGACY = IWX_LAST_NON_HT_RATE + 1, 4243 IWX_RATE_COUNT = IWX_LAST_HT_RATE + 1, 4244 }; 4245 4246 #define IWX_RATE_BIT_MSK(r) (1 << (IWX_RATE_##r##M_INDEX)) 4247 4248 /* fw API values for legacy bit rates, both OFDM and CCK */ 4249 #define IWX_RATE_6M_PLCP 13 4250 #define IWX_RATE_9M_PLCP 15 4251 #define IWX_RATE_12M_PLCP 5 4252 #define IWX_RATE_18M_PLCP 7 4253 #define IWX_RATE_24M_PLCP 9 4254 #define IWX_RATE_36M_PLCP 11 4255 #define IWX_RATE_48M_PLCP 1 4256 #define IWX_RATE_54M_PLCP 3 4257 #define IWX_RATE_1M_PLCP 10 4258 #define IWX_RATE_2M_PLCP 20 4259 #define IWX_RATE_5M_PLCP 55 4260 #define IWX_RATE_11M_PLCP 110 4261 #define IWX_RATE_INVM_PLCP 0xff 4262 4263 /* 4264 * rate_n_flags bit fields 4265 * 4266 * The 32-bit value has different layouts in the low 8 bites depending on the 4267 * format. There are three formats, HT, VHT and legacy (11abg, with subformats 4268 * for CCK and OFDM). 4269 * 4270 * High-throughput (HT) rate format 4271 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM) 4272 * Very High-throughput (VHT) rate format 4273 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM) 4274 * Legacy OFDM rate format for bits 7:0 4275 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM) 4276 * Legacy CCK rate format for bits 7:0: 4277 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK) 4278 */ 4279 4280 /* Bit 8: (1) HT format, (0) legacy or VHT format */ 4281 #define IWX_RATE_MCS_HT_POS 8 4282 #define IWX_RATE_MCS_HT_MSK (1 << IWX_RATE_MCS_HT_POS) 4283 4284 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */ 4285 #define IWX_RATE_MCS_CCK_POS 9 4286 #define IWX_RATE_MCS_CCK_MSK (1 << IWX_RATE_MCS_CCK_POS) 4287 4288 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */ 4289 #define IWX_RATE_MCS_VHT_POS 26 4290 #define IWX_RATE_MCS_VHT_MSK (1 << IWX_RATE_MCS_VHT_POS) 4291 4292 4293 /* 4294 * High-throughput (HT) rate format for bits 7:0 4295 * 4296 * 2-0: MCS rate base 4297 * 0) 6 Mbps 4298 * 1) 12 Mbps 4299 * 2) 18 Mbps 4300 * 3) 24 Mbps 4301 * 4) 36 Mbps 4302 * 5) 48 Mbps 4303 * 6) 54 Mbps 4304 * 7) 60 Mbps 4305 * 4-3: 0) Single stream (SISO) 4306 * 1) Dual stream (MIMO) 4307 * 2) Triple stream (MIMO) 4308 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data 4309 * (bits 7-6 are zero) 4310 * 4311 * Together the low 5 bits work out to the MCS index because we don't 4312 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two 4313 * streams and 16-23 have three streams. We could also support MCS 32 4314 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.) 4315 */ 4316 #define IWX_RATE_HT_MCS_RATE_CODE_MSK 0x7 4317 #define IWX_RATE_HT_MCS_NSS_POS 3 4318 #define IWX_RATE_HT_MCS_NSS_MSK (3 << IWX_RATE_HT_MCS_NSS_POS) 4319 4320 /* Bit 10: (1) Use Green Field preamble */ 4321 #define IWX_RATE_HT_MCS_GF_POS 10 4322 #define IWX_RATE_HT_MCS_GF_MSK (1 << IWX_RATE_HT_MCS_GF_POS) 4323 4324 #define IWX_RATE_HT_MCS_INDEX_MSK 0x3f 4325 4326 /* 4327 * Very High-throughput (VHT) rate format for bits 7:0 4328 * 4329 * 3-0: VHT MCS (0-9) 4330 * 5-4: number of streams - 1: 4331 * 0) Single stream (SISO) 4332 * 1) Dual stream (MIMO) 4333 * 2) Triple stream (MIMO) 4334 */ 4335 4336 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */ 4337 #define IWX_RATE_VHT_MCS_RATE_CODE_MSK 0xf 4338 #define IWX_RATE_VHT_MCS_NSS_POS 4 4339 #define IWX_RATE_VHT_MCS_NSS_MSK (3 << IWX_RATE_VHT_MCS_NSS_POS) 4340 4341 /* 4342 * Legacy OFDM rate format for bits 7:0 4343 * 4344 * 3-0: 0xD) 6 Mbps 4345 * 0xF) 9 Mbps 4346 * 0x5) 12 Mbps 4347 * 0x7) 18 Mbps 4348 * 0x9) 24 Mbps 4349 * 0xB) 36 Mbps 4350 * 0x1) 48 Mbps 4351 * 0x3) 54 Mbps 4352 * (bits 7-4 are 0) 4353 * 4354 * Legacy CCK rate format for bits 7:0: 4355 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK): 4356 * 4357 * 6-0: 10) 1 Mbps 4358 * 20) 2 Mbps 4359 * 55) 5.5 Mbps 4360 * 110) 11 Mbps 4361 * (bit 7 is 0) 4362 */ 4363 #define IWX_RATE_LEGACY_RATE_MSK 0xff 4364 4365 4366 /* 4367 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz 4368 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT 4369 */ 4370 #define IWX_RATE_MCS_CHAN_WIDTH_POS 11 4371 #define IWX_RATE_MCS_CHAN_WIDTH_MSK (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4372 #define IWX_RATE_MCS_CHAN_WIDTH_20 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4373 #define IWX_RATE_MCS_CHAN_WIDTH_40 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4374 #define IWX_RATE_MCS_CHAN_WIDTH_80 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4375 #define IWX_RATE_MCS_CHAN_WIDTH_160 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS) 4376 4377 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */ 4378 #define IWX_RATE_MCS_SGI_POS 13 4379 #define IWX_RATE_MCS_SGI_MSK (1 << IWX_RATE_MCS_SGI_POS) 4380 4381 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */ 4382 #define IWX_RATE_MCS_ANT_POS 14 4383 #define IWX_RATE_MCS_ANT_A_MSK (1 << IWX_RATE_MCS_ANT_POS) 4384 #define IWX_RATE_MCS_ANT_B_MSK (2 << IWX_RATE_MCS_ANT_POS) 4385 #define IWX_RATE_MCS_ANT_C_MSK (4 << IWX_RATE_MCS_ANT_POS) 4386 #define IWX_RATE_MCS_ANT_AB_MSK (IWX_RATE_MCS_ANT_A_MSK | \ 4387 IWX_RATE_MCS_ANT_B_MSK) 4388 #define IWX_RATE_MCS_ANT_ABC_MSK (IWX_RATE_MCS_ANT_AB_MSK | \ 4389 IWX_RATE_MCS_ANT_C_MSK) 4390 #define IWX_RATE_MCS_ANT_MSK IWX_RATE_MCS_ANT_ABC_MSK 4391 #define IWX_RATE_MCS_ANT_NUM 3 4392 4393 /* Bit 17-18: (0) SS, (1) SS*2 */ 4394 #define IWX_RATE_MCS_STBC_POS 17 4395 #define IWX_RATE_MCS_STBC_MSK (1 << IWX_RATE_MCS_STBC_POS) 4396 4397 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */ 4398 #define IWX_RATE_MCS_BF_POS 19 4399 #define IWX_RATE_MCS_BF_MSK (1 << IWX_RATE_MCS_BF_POS) 4400 4401 /* Bit 20: (0) ZLF is off, (1) ZLF is on */ 4402 #define IWX_RATE_MCS_ZLF_POS 20 4403 #define IWX_RATE_MCS_ZLF_MSK (1 << IWX_RATE_MCS_ZLF_POS) 4404 4405 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */ 4406 #define IWX_RATE_MCS_DUP_POS 24 4407 #define IWX_RATE_MCS_DUP_MSK (3 << IWX_RATE_MCS_DUP_POS) 4408 4409 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */ 4410 #define IWX_RATE_MCS_LDPC_POS 27 4411 #define IWX_RATE_MCS_LDPC_MSK (1 << IWX_RATE_MCS_LDPC_POS) 4412 4413 4414 /* Link Quality definitions */ 4415 4416 /* # entries in rate scale table to support Tx retries */ 4417 #define IWX_LQ_MAX_RETRY_NUM 16 4418 4419 /* Link quality command flags bit fields */ 4420 4421 /* Bit 0: (0) Don't use RTS (1) Use RTS */ 4422 #define IWX_LQ_FLAG_USE_RTS_POS 0 4423 #define IWX_LQ_FLAG_USE_RTS_MSK (1 << IWX_LQ_FLAG_USE_RTS_POS) 4424 4425 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */ 4426 #define IWX_LQ_FLAG_COLOR_POS 1 4427 #define IWX_LQ_FLAG_COLOR_MSK (7 << IWX_LQ_FLAG_COLOR_POS) 4428 4429 /* Bit 4-5: Tx RTS BW Signalling 4430 * (0) No RTS BW signalling 4431 * (1) Static BW signalling 4432 * (2) Dynamic BW signalling 4433 */ 4434 #define IWX_LQ_FLAG_RTS_BW_SIG_POS 4 4435 #define IWX_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 4436 #define IWX_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 4437 #define IWX_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWX_LQ_FLAG_RTS_BW_SIG_POS) 4438 4439 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection 4440 * Dyanmic BW selection allows Tx with narrower BW then requested in rates 4441 */ 4442 #define IWX_LQ_FLAG_DYNAMIC_BW_POS 6 4443 #define IWX_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWX_LQ_FLAG_DYNAMIC_BW_POS) 4444 4445 /** 4446 * Options for TLC config flags 4447 * @IWX_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for 4448 * bandwidths <= 80MHz 4449 * @IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC 4450 * @IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz 4451 * bandwidth 4452 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation 4453 * for BPSK (MCS 0) with 1 spatial 4454 * stream 4455 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation 4456 * for BPSK (MCS 0) with 2 spatial 4457 * streams 4458 */ 4459 #define IWX_TLC_MNG_CFG_FLAGS_STBC_MSK (1 << 0) 4460 #define IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK (1 << 1) 4461 #define IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK (1 << 2) 4462 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK (1 << 3) 4463 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK (1 << 4) 4464 4465 /** 4466 * enum iwx_tlc_mng_cfg_cw - channel width options 4467 * @IWX_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel 4468 * @IWX_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel 4469 * @IWX_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel 4470 * @IWX_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel 4471 * @IWX_TLC_MNG_CH_WIDTH_LAST: maximum value 4472 */ 4473 enum iwx_tlc_mng_cfg_cw { 4474 IWX_TLC_MNG_CH_WIDTH_20MHZ, 4475 IWX_TLC_MNG_CH_WIDTH_40MHZ, 4476 IWX_TLC_MNG_CH_WIDTH_80MHZ, 4477 IWX_TLC_MNG_CH_WIDTH_160MHZ, 4478 IWX_TLC_MNG_CH_WIDTH_LAST = IWX_TLC_MNG_CH_WIDTH_160MHZ, 4479 }; 4480 4481 /** 4482 * @IWX_TLC_MNG_CHAIN_A_MSK: chain A 4483 * @IWX_TLC_MNG_CHAIN_B_MSK: chain B 4484 */ 4485 #define IWX_TLC_MNG_CHAIN_A_MSK (1 << 0) 4486 #define IWX_TLC_MNG_CHAIN_B_MSK (1 << 1) 4487 4488 /** 4489 * enum iwx_tlc_mng_cfg_mode - supported modes 4490 * @IWX_TLC_MNG_MODE_CCK: enable CCK 4491 * @IWX_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT) 4492 * @IWX_TLC_MNG_MODE_NON_HT: enable non HT 4493 * @IWX_TLC_MNG_MODE_HT: enable HT 4494 * @IWX_TLC_MNG_MODE_VHT: enable VHT 4495 * @IWX_TLC_MNG_MODE_HE: enable HE 4496 * @IWX_TLC_MNG_MODE_INVALID: invalid value 4497 * @IWX_TLC_MNG_MODE_NUM: a count of possible modes 4498 */ 4499 enum iwx_tlc_mng_cfg_mode { 4500 IWX_TLC_MNG_MODE_CCK = 0, 4501 IWX_TLC_MNG_MODE_OFDM_NON_HT = IWX_TLC_MNG_MODE_CCK, 4502 IWX_TLC_MNG_MODE_NON_HT = IWX_TLC_MNG_MODE_CCK, 4503 IWX_TLC_MNG_MODE_HT, 4504 IWX_TLC_MNG_MODE_VHT, 4505 IWX_TLC_MNG_MODE_HE, 4506 IWX_TLC_MNG_MODE_INVALID, 4507 IWX_TLC_MNG_MODE_NUM = IWX_TLC_MNG_MODE_INVALID, 4508 }; 4509 4510 /** 4511 * @IWX_TLC_MNG_HT_RATE_MCS0: index of MCS0 4512 * @IWX_TLC_MNG_HT_RATE_MCS1: index of MCS1 4513 * @IWX_TLC_MNG_HT_RATE_MCS2: index of MCS2 4514 * @IWX_TLC_MNG_HT_RATE_MCS3: index of MCS3 4515 * @IWX_TLC_MNG_HT_RATE_MCS4: index of MCS4 4516 * @IWX_TLC_MNG_HT_RATE_MCS5: index of MCS5 4517 * @IWX_TLC_MNG_HT_RATE_MCS6: index of MCS6 4518 * @IWX_TLC_MNG_HT_RATE_MCS7: index of MCS7 4519 * @IWX_TLC_MNG_HT_RATE_MCS8: index of MCS8 4520 * @IWX_TLC_MNG_HT_RATE_MCS9: index of MCS9 4521 * @IWX_TLC_MNG_HT_RATE_MCS10: index of MCS10 4522 * @IWX_TLC_MNG_HT_RATE_MCS11: index of MCS11 4523 * @IWX_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT 4524 */ 4525 enum iwx_tlc_mng_ht_rates { 4526 IWX_TLC_MNG_HT_RATE_MCS0 = 0, 4527 IWX_TLC_MNG_HT_RATE_MCS1, 4528 IWX_TLC_MNG_HT_RATE_MCS2, 4529 IWX_TLC_MNG_HT_RATE_MCS3, 4530 IWX_TLC_MNG_HT_RATE_MCS4, 4531 IWX_TLC_MNG_HT_RATE_MCS5, 4532 IWX_TLC_MNG_HT_RATE_MCS6, 4533 IWX_TLC_MNG_HT_RATE_MCS7, 4534 IWX_TLC_MNG_HT_RATE_MCS8, 4535 IWX_TLC_MNG_HT_RATE_MCS9, 4536 IWX_TLC_MNG_HT_RATE_MCS10, 4537 IWX_TLC_MNG_HT_RATE_MCS11, 4538 IWX_TLC_MNG_HT_RATE_MAX = IWX_TLC_MNG_HT_RATE_MCS11, 4539 }; 4540 4541 #define IWX_TLC_NSS_1 0 4542 #define IWX_TLC_NSS_2 1 4543 #define IWX_TLC_NSS_MAX 2 4544 4545 #define IWX_TLC_HT_BW_NONE_160 0 4546 #define IWX_TLC_HT_BW_160 1 4547 4548 /** 4549 * struct iwx_tlc_config_cmd - TLC configuration 4550 * @sta_id: station id 4551 * @reserved1: reserved 4552 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw 4553 * @mode: &enum iwx_tlc_mng_cfg_mode 4554 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK 4555 * @amsdu: 1 = TX amsdu is supported, 0 = not supported 4556 * @flags: bitmask of IWX_TLC_MNG_CFG_* 4557 * @non_ht_rates: bitmap of supported legacy rates 4558 * @ht_rates: bitmap of &enum iwx_tlc_mng_ht_rates, per <nss, channel-width> 4559 * pair (0 - 80mhz width and below, 1 - 160mhz). 4560 * @max_mpdu_len: max MPDU length, in bytes 4561 * @sgi_ch_width_supp: bitmap of SGI support per channel width 4562 * use (1 << @enum iwx_tlc_mng_cfg_cw) 4563 * @reserved2: reserved 4564 */ 4565 struct iwx_tlc_config_cmd { 4566 uint8_t sta_id; 4567 uint8_t reserved1[3]; 4568 uint8_t max_ch_width; 4569 uint8_t mode; 4570 uint8_t chains; 4571 uint8_t amsdu; 4572 uint16_t flags; 4573 uint16_t non_ht_rates; 4574 uint16_t ht_rates[IWX_TLC_NSS_MAX][2]; 4575 uint16_t max_mpdu_len; 4576 uint8_t sgi_ch_width_supp; 4577 uint8_t reserved2[1]; 4578 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_2 */ 4579 4580 /** 4581 * @IWX_TLC_NOTIF_FLAG_RATE: last initial rate update 4582 * @IWX_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update 4583 */ 4584 #define IWX_TLC_NOTIF_FLAG_RATE (1 << 0) 4585 #define IWX_TLC_NOTIF_FLAG_AMSDU (1 << 1) 4586 4587 /** 4588 * struct iwx_tlc_update_notif - TLC notification from FW 4589 * @sta_id: station id 4590 * @reserved: reserved 4591 * @flags: bitmap of notifications reported 4592 * @rate: current initial rate 4593 * @amsdu_size: Max AMSDU size, in bytes 4594 * @amsdu_enabled: bitmap for per-TID AMSDU enablement 4595 */ 4596 struct iwx_tlc_update_notif { 4597 uint8_t sta_id; 4598 uint8_t reserved[3]; 4599 uint32_t flags; 4600 uint32_t rate; 4601 uint32_t amsdu_size; 4602 uint32_t amsdu_enabled; 4603 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */ 4604 4605 /* Antenna flags. */ 4606 #define IWX_ANT_A (1 << 0) 4607 #define IWX_ANT_B (1 << 1) 4608 #define IWX_ANT_C (1 << 2) 4609 /* Shortcuts. */ 4610 #define IWX_ANT_AB (IWX_ANT_A | IWX_ANT_B) 4611 #define IWX_ANT_BC (IWX_ANT_B | IWX_ANT_C) 4612 #define IWX_ANT_ABC (IWX_ANT_A | IWX_ANT_B | IWX_ANT_C) 4613 4614 /** 4615 * bitmasks for tx_flags in TX command 4616 * @IWX_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame 4617 * @IWX_TX_CMD_FLG_ACK: expect ACK from receiving station 4618 * @IWX_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. 4619 * Otherwise, use rate_n_flags from the TX command 4620 * @IWX_TX_CMD_FLG_BA: this frame is a block ack 4621 * @IWX_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected 4622 * Must set IWX_TX_CMD_FLG_ACK with this flag. 4623 * @IWX_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection 4624 * @IWX_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence 4625 * @IWX_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence 4626 * @IWX_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) 4627 * @IWX_TX_CMD_FLG_BT_DIS: disable BT priority for this frame 4628 * @IWX_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. 4629 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command 4630 * @IWX_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU 4631 * @IWX_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame 4632 * @IWX_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame 4633 * Should be set for beacons and probe responses 4634 * @IWX_TX_CMD_FLG_CALIB: activate PA TX power calibrations 4635 * @IWX_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count 4636 * @IWX_TX_CMD_FLG_AGG_START: allow this frame to start aggregation 4637 * @IWX_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. 4638 * Should be set for 26/30 length MAC headers 4639 * @IWX_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW 4640 * @IWX_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration 4641 * @IWX_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation 4642 * @IWX_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id 4643 * @IWX_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped 4644 * @IWX_TX_CMD_FLG_EXEC_PAPD: execute PAPD 4645 * @IWX_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power 4646 * @IWX_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk 4647 */ 4648 #define IWX_TX_CMD_FLG_PROT_REQUIRE (1 << 0) 4649 #define IWX_TX_CMD_FLG_ACK (1 << 3) 4650 #define IWX_TX_CMD_FLG_STA_RATE (1 << 4) 4651 #define IWX_TX_CMD_FLG_BA (1 << 5) 4652 #define IWX_TX_CMD_FLG_BAR (1 << 6) 4653 #define IWX_TX_CMD_FLG_TXOP_PROT (1 << 7) 4654 #define IWX_TX_CMD_FLG_VHT_NDPA (1 << 8) 4655 #define IWX_TX_CMD_FLG_HT_NDPA (1 << 9) 4656 #define IWX_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10) 4657 #define IWX_TX_CMD_FLG_BT_DIS (1 << 12) 4658 #define IWX_TX_CMD_FLG_SEQ_CTL (1 << 13) 4659 #define IWX_TX_CMD_FLG_MORE_FRAG (1 << 14) 4660 #define IWX_TX_CMD_FLG_NEXT_FRAME (1 << 15) 4661 #define IWX_TX_CMD_FLG_TSF (1 << 16) 4662 #define IWX_TX_CMD_FLG_CALIB (1 << 17) 4663 #define IWX_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18) 4664 #define IWX_TX_CMD_FLG_AGG_START (1 << 19) 4665 #define IWX_TX_CMD_FLG_MH_PAD (1 << 20) 4666 #define IWX_TX_CMD_FLG_RESP_TO_DRV (1 << 21) 4667 #define IWX_TX_CMD_FLG_CCMP_AGG (1 << 22) 4668 #define IWX_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23) 4669 #define IWX_TX_CMD_FLG_DUR (1 << 25) 4670 #define IWX_TX_CMD_FLG_FW_DROP (1 << 26) 4671 #define IWX_TX_CMD_FLG_EXEC_PAPD (1 << 27) 4672 #define IWX_TX_CMD_FLG_PAPD_TYPE (1 << 28) 4673 #define IWX_TX_CMD_FLG_HCCA_CHUNK (1U << 31) 4674 /* IWX_TX_FLAGS_BITS_API_S_VER_1 */ 4675 4676 /* 4677 * TX command security control 4678 */ 4679 #define IWX_TX_CMD_SEC_WEP 0x01 4680 #define IWX_TX_CMD_SEC_CCM 0x02 4681 #define IWX_TX_CMD_SEC_TKIP 0x03 4682 #define IWX_TX_CMD_SEC_EXT 0x04 4683 #define IWX_TX_CMD_SEC_MSK 0x07 4684 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_POS 6 4685 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0 4686 #define IWX_TX_CMD_SEC_KEY128 0x08 4687 4688 /* TODO: how does these values are OK with only 16 bit variable??? */ 4689 /* 4690 * TX command next frame info 4691 * 4692 * bits 0:2 - security control (IWX_TX_CMD_SEC_*) 4693 * bit 3 - immediate ACK required 4694 * bit 4 - rate is taken from STA table 4695 * bit 5 - frame belongs to BA stream 4696 * bit 6 - immediate BA response expected 4697 * bit 7 - unused 4698 * bits 8:15 - Station ID 4699 * bits 16:31 - rate 4700 */ 4701 #define IWX_TX_CMD_NEXT_FRAME_ACK_MSK (0x8) 4702 #define IWX_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10) 4703 #define IWX_TX_CMD_NEXT_FRAME_BA_MSK (0x20) 4704 #define IWX_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40) 4705 #define IWX_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8) 4706 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00) 4707 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_POS (8) 4708 #define IWX_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000) 4709 #define IWX_TX_CMD_NEXT_FRAME_RATE_POS (16) 4710 4711 /* 4712 * TX command Frame life time in us - to be written in pm_frame_timeout 4713 */ 4714 #define IWX_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF 4715 #define IWX_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/ 4716 #define IWX_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */ 4717 #define IWX_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0 4718 4719 /* 4720 * TID for non QoS frames - to be written in tid_tspec 4721 */ 4722 #define IWX_TID_NON_QOS 0 4723 4724 /* 4725 * Limits on the retransmissions - to be written in {data,rts}_retry_limit 4726 */ 4727 #define IWX_DEFAULT_TX_RETRY 15 4728 #define IWX_MGMT_DFAULT_RETRY_LIMIT 3 4729 #define IWX_RTS_DFAULT_RETRY_LIMIT 3 4730 #define IWX_BAR_DFAULT_RETRY_LIMIT 60 4731 #define IWX_LOW_RETRY_LIMIT 7 4732 4733 /* 4734 * The FH will write back to the first TB only, so we need to copy some data 4735 * into the buffer regardless of whether it should be mapped or not. 4736 * This indicates how big the first TB must be to include the scratch buffer 4737 * and the assigned PN. 4738 * Since PN location is 8 bytes at offset 12, it's 20 now. 4739 * If we make it bigger then allocations will be bigger and copy slower, so 4740 * that's probably not useful. 4741 */ 4742 #define IWX_FIRST_TB_SIZE 20 4743 #define IWX_FIRST_TB_SIZE_ALIGN ((IWX_FIRST_TB_SIZE + (64 - 1)) & ~(64 - 1)) 4744 4745 /** 4746 * %iwl_tx_cmd offload_assist values 4747 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words) 4748 * from mac header end. For normal case it is 4 words for SNAP. 4749 * note: tx_cmd, mac header and pad are not counted in the offset. 4750 * This is used to help the offload in case there is tunneling such as 4751 * IPv6 in IPv4, in such case the ip header offset should point to the 4752 * inner ip header and IPv4 checksum of the external header should be 4753 * calculated by driver. 4754 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum 4755 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum 4756 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV 4757 * field. Doesn't include the pad. 4758 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for 4759 * alignment 4760 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU 4761 */ 4762 #define IWX_TX_CMD_OFFLD_IP_HDR(x) ((x) << 0) 4763 #define IWX_TX_CMD_OFFLD_L4_EN (1 << 6) 4764 #define IWX_TX_CMD_OFFLD_L3_EN (1 << 7) 4765 #define IWX_TX_CMD_OFFLD_MH_SIZE(x) ((x) << 8) 4766 #define IWX_TX_CMD_OFFLD_PAD (1 << 13) 4767 #define IWX_TX_CMD_OFFLD_AMSDU (1 << 14) 4768 #define IWX_TX_CMD_OFFLD_MH_MASK 0x1f 4769 #define IWX_TX_CMD_OFFLD_IP_HDR_MASK 0x3f 4770 4771 struct iwx_dram_sec_info { 4772 uint32_t pn_low; 4773 uint16_t pn_high; 4774 uint16_t aux_info; 4775 } __packed; /* DRAM_SEC_INFO_API_S_VER_1 */ 4776 4777 /** 4778 * bitmasks for tx_flags in TX command for 22000 4779 * @IWX_TX_FLAGS_CMD_RATE: use rate from the TX command 4780 * @IWX_TX_FLAGS_ENCRYPT_DIS: frame should not be encrypted, even if it belongs 4781 * to a secured STA 4782 * @IWX_TX_FLAGS_HIGH_PRI: high priority frame (like EAPOL) - can affect rate 4783 * selection, retry limits and BT kill 4784 */ 4785 #define IWX_TX_FLAGS_CMD_RATE (1 << 0) 4786 #define IWX_TX_FLAGS_ENCRYPT_DIS (1 << 1) 4787 #define IWX_TX_FLAGS_HIGH_PRI (1 << 2) 4788 /* TX_FLAGS_BITS_API_S_VER_3 */ 4789 4790 /** 4791 * struct iwx_tx_cmd_gen2 - TX command struct to FW for 22000 devices 4792 * ( TX_CMD = 0x1c ) 4793 * @len: in bytes of the payload, see below for details 4794 * @offload_assist: TX offload configuration 4795 * @flags: combination of TX_CMD_FLG_* 4796 * @dram_info: FW internal DRAM storage 4797 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 4798 * cleared. Combination of RATE_MCS_* 4799 * @hdr: 802.11 header 4800 */ 4801 struct iwx_tx_cmd_gen2 { 4802 uint16_t len; 4803 uint16_t offload_assist; 4804 uint32_t flags; 4805 struct iwx_dram_sec_info dram_info; 4806 uint32_t rate_n_flags; 4807 struct ieee80211_frame hdr[0]; 4808 } __packed; /* TX_CMD_API_S_VER_7 */ 4809 4810 /* 4811 * TX response related data 4812 */ 4813 4814 /* 4815 * status that is returned by the fw after attempts to Tx 4816 * @IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and 4817 * STA table 4818 * Valid only if frame_count =1 4819 */ 4820 #define IWX_TX_STATUS_MSK 0x000000ff 4821 #define IWX_TX_STATUS_SUCCESS 0x01 4822 #define IWX_TX_STATUS_DIRECT_DONE 0x02 4823 /* postpone TX */ 4824 #define IWX_TX_STATUS_POSTPONE_DELAY 0x40 4825 #define IWX_TX_STATUS_POSTPONE_FEW_BYTES 0x41 4826 #define IWX_TX_STATUS_POSTPONE_BT_PRIO 0x42 4827 #define IWX_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43 4828 #define IWX_TX_STATUS_POSTPONE_CALC_TTAK 0x44 4829 /* abort TX */ 4830 #define IWX_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81 4831 #define IWX_TX_STATUS_FAIL_SHORT_LIMIT 0x82 4832 #define IWX_TX_STATUS_FAIL_LONG_LIMIT 0x83 4833 #define IWX_TX_STATUS_FAIL_UNDERRUN 0x84 4834 #define IWX_TX_STATUS_FAIL_DRAIN_FLOW 0x85 4835 #define IWX_TX_STATUS_FAIL_RFKILL_FLUSH 0x86 4836 #define IWX_TX_STATUS_FAIL_LIFE_EXPIRE 0x87 4837 #define IWX_TX_STATUS_FAIL_DEST_PS 0x88 4838 #define IWX_TX_STATUS_FAIL_HOST_ABORTED 0x89 4839 #define IWX_TX_STATUS_FAIL_BT_RETRY 0x8a 4840 #define IWX_TX_STATUS_FAIL_STA_INVALID 0x8b 4841 #define IWX_TX_STATUS_FAIL_FRAG_DROPPED 0x8c 4842 #define IWX_TX_STATUS_FAIL_TID_DISABLE 0x8d 4843 #define IWX_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e 4844 #define IWX_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f 4845 #define IWX_TX_STATUS_FAIL_FW_DROP 0x90 4846 #define IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91 4847 #define IWX_TX_STATUS_INTERNAL_ABORT 0x92 4848 #define IWX_TX_MODE_MSK 0x00000f00 4849 #define IWX_TX_MODE_NO_BURST 0x00000000 4850 #define IWX_TX_MODE_IN_BURST_SEQ 0x00000100 4851 #define IWX_TX_MODE_FIRST_IN_BURST 0x00000200 4852 #define IWX_TX_QUEUE_NUM_MSK 0x0001f000 4853 #define IWX_TX_NARROW_BW_MSK 0x00060000 4854 #define IWX_TX_NARROW_BW_1DIV2 0x00020000 4855 #define IWX_TX_NARROW_BW_1DIV4 0x00040000 4856 #define IWX_TX_NARROW_BW_1DIV8 0x00060000 4857 4858 /* 4859 * TX aggregation status 4860 * @IWX_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries 4861 * occur if tx failed for this frame when it was a member of a previous 4862 * aggregation block). If rate scaling is used, retry count indicates the 4863 * rate table entry used for all frames in the new agg. 4864 * @IWX_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for 4865 * this frame 4866 */ 4867 #define IWX_AGG_TX_STATE_STATUS_MSK 0x0fff 4868 #define IWX_AGG_TX_STATE_TRANSMITTED 0x0000 4869 #define IWX_AGG_TX_STATE_UNDERRUN 0x0001 4870 #define IWX_AGG_TX_STATE_BT_PRIO 0x0002 4871 #define IWX_AGG_TX_STATE_FEW_BYTES 0x0004 4872 #define IWX_AGG_TX_STATE_ABORT 0x0008 4873 #define IWX_AGG_TX_STATE_LAST_SENT_TTL 0x0010 4874 #define IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020 4875 #define IWX_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040 4876 #define IWX_AGG_TX_STATE_SCD_QUERY 0x0080 4877 #define IWX_AGG_TX_STATE_TEST_BAD_CRC32 0x0100 4878 #define IWX_AGG_TX_STATE_RESPONSE 0x01ff 4879 #define IWX_AGG_TX_STATE_DUMP_TX 0x0200 4880 #define IWX_AGG_TX_STATE_DELAY_TX 0x0400 4881 #define IWX_AGG_TX_STATE_TRY_CNT_POS 12 4882 #define IWX_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWX_AGG_TX_STATE_TRY_CNT_POS) 4883 4884 #define IWX_AGG_TX_STATE_LAST_SENT_MSK (IWX_AGG_TX_STATE_LAST_SENT_TTL| \ 4885 IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT| \ 4886 IWX_AGG_TX_STATE_LAST_SENT_BT_KILL) 4887 4888 /* 4889 * The mask below describes a status where we are absolutely sure that the MPDU 4890 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've 4891 * written the bytes to the TXE, but we know nothing about what the DSP did. 4892 */ 4893 #define IWX_AGG_TX_STAT_FRAME_NOT_SENT (IWX_AGG_TX_STATE_FEW_BYTES | \ 4894 IWX_AGG_TX_STATE_ABORT | \ 4895 IWX_AGG_TX_STATE_SCD_QUERY) 4896 4897 /* 4898 * IWX_REPLY_TX = 0x1c (response) 4899 * 4900 * This response may be in one of two slightly different formats, indicated 4901 * by the frame_count field: 4902 * 4903 * 1) No aggregation (frame_count == 1). This reports Tx results for a single 4904 * frame. Multiple attempts, at various bit rates, may have been made for 4905 * this frame. 4906 * 4907 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more 4908 * frames that used block-acknowledge. All frames were transmitted at 4909 * same rate. Rate scaling may have been used if first frame in this new 4910 * agg block failed in previous agg block(s). 4911 * 4912 * Note that, for aggregation, ACK (block-ack) status is not delivered 4913 * here; block-ack has not been received by the time the device records 4914 * this status. 4915 * This status relates to reasons the tx might have been blocked or aborted 4916 * within the device, rather than whether it was received successfully by 4917 * the destination station. 4918 */ 4919 4920 /** 4921 * struct iwx_agg_tx_status - per packet TX aggregation status 4922 * @status: enum iwx_tx_agg_status 4923 * @sequence: Sequence # for this frame's Tx cmd (not SSN!) 4924 */ 4925 struct iwx_agg_tx_status { 4926 uint16_t status; 4927 uint16_t sequence; 4928 } __packed; 4929 4930 /* 4931 * definitions for initial rate index field 4932 * bits [3:0] initial rate index 4933 * bits [6:4] rate table color, used for the initial rate 4934 * bit-7 invalid rate indication 4935 */ 4936 #define IWX_TX_RES_INIT_RATE_INDEX_MSK 0x0f 4937 #define IWX_TX_RES_RATE_TABLE_COLOR_MSK 0x70 4938 #define IWX_TX_RES_INV_RATE_INDEX_MSK 0x80 4939 4940 #define IWX_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f) 4941 #define IWX_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4) 4942 4943 /** 4944 * struct iwx_tx_resp_v3 - notifies that fw is TXing a packet 4945 * ( IWX_REPLY_TX = 0x1c ) 4946 * @frame_count: 1 no aggregation, >1 aggregation 4947 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 4948 * @failure_rts: num of failures due to unsuccessful RTS 4949 * @failure_frame: num failures due to no ACK (unused for agg) 4950 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 4951 * Tx of all the batch. IWX_RATE_MCS_* 4952 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 4953 * for agg: RTS + CTS + aggregation tx time + block-ack time. 4954 * in usec. 4955 * @pa_status: tx power info 4956 * @pa_integ_res_a: tx power info 4957 * @pa_integ_res_b: tx power info 4958 * @pa_integ_res_c: tx power info 4959 * @measurement_req_id: tx power info 4960 * @tfd_info: TFD information set by the FH 4961 * @seq_ctl: sequence control from the Tx cmd 4962 * @byte_cnt: byte count from the Tx cmd 4963 * @tlc_info: TLC rate info 4964 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 4965 * @frame_ctrl: frame control 4966 * @status: for non-agg: frame status IWX_TX_STATUS_* 4967 * for agg: status of 1st frame, IWX_AGG_TX_STATE_*; other frame status fields 4968 * follow this one, up to frame_count. 4969 * 4970 * After the array of statuses comes the SSN of the SCD. Look at 4971 * %iwx_get_scd_ssn for more details. 4972 */ 4973 struct iwx_tx_resp_v3 { 4974 uint8_t frame_count; 4975 uint8_t bt_kill_count; 4976 uint8_t failure_rts; 4977 uint8_t failure_frame; 4978 uint32_t initial_rate; 4979 uint16_t wireless_media_time; 4980 4981 uint8_t pa_status; 4982 uint8_t pa_integ_res_a[3]; 4983 uint8_t pa_integ_res_b[3]; 4984 uint8_t pa_integ_res_c[3]; 4985 uint16_t measurement_req_id; 4986 uint16_t reserved; 4987 4988 uint32_t tfd_info; 4989 uint16_t seq_ctl; 4990 uint16_t byte_cnt; 4991 uint8_t tlc_info; 4992 uint8_t ra_tid; 4993 uint16_t frame_ctrl; 4994 4995 struct iwx_agg_tx_status status; 4996 } __packed; /* IWX_TX_RSP_API_S_VER_3 */ 4997 4998 /** 4999 * struct iwx_tx_resp - notifies that fw is TXing a packet 5000 * ( REPLY_TX = 0x1c ) 5001 * @frame_count: 1 no aggregation, >1 aggregation 5002 * @bt_kill_count: num of times blocked by bluetooth (unused for agg) 5003 * @failure_rts: num of failures due to unsuccessful RTS 5004 * @failure_frame: num failures due to no ACK (unused for agg) 5005 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the 5006 * Tx of all the batch. RATE_MCS_* 5007 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK. 5008 * for agg: RTS + CTS + aggregation tx time + block-ack time. 5009 * in usec. 5010 * @pa_status: tx power info 5011 * @pa_integ_res_a: tx power info 5012 * @pa_integ_res_b: tx power info 5013 * @pa_integ_res_c: tx power info 5014 * @measurement_req_id: tx power info 5015 * @reduced_tpc: transmit power reduction used 5016 * @reserved: reserved 5017 * @tfd_info: TFD information set by the FH 5018 * @seq_ctl: sequence control from the Tx cmd 5019 * @byte_cnt: byte count from the Tx cmd 5020 * @tlc_info: TLC rate info 5021 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid 5022 * @frame_ctrl: frame control 5023 * @tx_queue: TX queue for this response 5024 * @reserved2: reserved for padding/alignment 5025 * @status: for non-agg: frame status TX_STATUS_* 5026 * For version 6 TX response isn't received for aggregation at all. 5027 * 5028 * After the array of statuses comes the SSN of the SCD. Look at 5029 * %iwl_mvm_get_scd_ssn for more details. 5030 */ 5031 struct iwx_tx_resp { 5032 uint8_t frame_count; 5033 uint8_t bt_kill_count; 5034 uint8_t failure_rts; 5035 uint8_t failure_frame; 5036 uint32_t initial_rate; 5037 uint16_t wireless_media_time; 5038 5039 uint8_t pa_status; 5040 uint8_t pa_integ_res_a[3]; 5041 uint8_t pa_integ_res_b[3]; 5042 uint8_t pa_integ_res_c[3]; 5043 uint16_t measurement_req_id; 5044 uint8_t reduced_tpc; 5045 uint8_t reserved; 5046 5047 uint32_t tfd_info; 5048 uint16_t seq_ctl; 5049 uint16_t byte_cnt; 5050 uint8_t tlc_info; 5051 uint8_t ra_tid; 5052 uint16_t frame_ctrl; 5053 uint16_t tx_queue; 5054 uint16_t reserved2; 5055 struct iwx_agg_tx_status status; 5056 } __packed; /* TX_RSP_API_S_VER_6 */ 5057 5058 /** 5059 * struct iwx_ba_notif - notifies about reception of BA 5060 * ( IWX_BA_NOTIF = 0xc5 ) 5061 * @sta_addr_lo32: lower 32 bits of the MAC address 5062 * @sta_addr_hi16: upper 16 bits of the MAC address 5063 * @sta_id: Index of recipient (BA-sending) station in fw's station table 5064 * @tid: tid of the session 5065 * @seq_ctl: 5066 * @bitmap: the bitmap of the BA notification as seen in the air 5067 * @scd_flow: the tx queue this BA relates to 5068 * @scd_ssn: the index of the last contiguously sent packet 5069 * @txed: number of Txed frames in this batch 5070 * @txed_2_done: number of Acked frames in this batch 5071 */ 5072 struct iwx_ba_notif { 5073 uint32_t sta_addr_lo32; 5074 uint16_t sta_addr_hi16; 5075 uint16_t reserved; 5076 5077 uint8_t sta_id; 5078 uint8_t tid; 5079 uint16_t seq_ctl; 5080 uint64_t bitmap; 5081 uint16_t scd_flow; 5082 uint16_t scd_ssn; 5083 uint8_t txed; 5084 uint8_t txed_2_done; 5085 uint16_t reserved1; 5086 } __packed; 5087 5088 struct iwx_beacon_notif { 5089 struct iwx_tx_resp_v3 beacon_notify_hdr; 5090 uint64_t tsf; 5091 uint32_t ibss_mgr_status; 5092 } __packed; 5093 5094 /** 5095 * dump (flush) control flags 5096 * @IWX_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty 5097 * and the TFD queues are empty. 5098 */ 5099 #define IWX_DUMP_TX_FIFO_FLUSH (1 << 1) 5100 5101 /** 5102 * struct iwx_tx_path_flush_cmd -- queue/FIFO flush command 5103 * @queues_ctl: bitmap of queues to flush 5104 * @flush_ctl: control flags 5105 * @reserved: reserved 5106 */ 5107 struct iwx_tx_path_flush_cmd_v1 { 5108 uint32_t queues_ctl; 5109 uint16_t flush_ctl; 5110 uint16_t reserved; 5111 } __packed; /* IWX_TX_PATH_FLUSH_CMD_API_S_VER_1 */ 5112 5113 /** 5114 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command 5115 * @sta_id: station ID to flush 5116 * @tid_mask: TID mask to flush 5117 * @reserved: reserved 5118 */ 5119 struct iwx_tx_path_flush_cmd { 5120 uint32_t sta_id; 5121 uint16_t tid_mask; 5122 uint16_t reserved; 5123 } __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */ 5124 5125 /** 5126 * iwx_get_scd_ssn - returns the SSN of the SCD 5127 * @tx_resp: the Tx response from the fw (agg or non-agg) 5128 * 5129 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since 5130 * it can't know that everything will go well until the end of the AMPDU, it 5131 * can't know in advance the number of MPDUs that will be sent in the current 5132 * batch. This is why it writes the agg Tx response while it fetches the MPDUs. 5133 * Hence, it can't know in advance what the SSN of the SCD will be at the end 5134 * of the batch. This is why the SSN of the SCD is written at the end of the 5135 * whole struct at a variable offset. This function knows how to cope with the 5136 * variable offset and returns the SSN of the SCD. 5137 */ 5138 static inline uint32_t iwx_get_scd_ssn(struct iwx_tx_resp *tx_resp) 5139 { 5140 return le32_to_cpup((uint32_t *)&tx_resp->status + 5141 tx_resp->frame_count) & 0xfff; 5142 } 5143 5144 /** 5145 * struct iwx_scd_txq_cfg_cmd - New txq hw scheduler config command 5146 * @token: 5147 * @sta_id: station id 5148 * @tid: 5149 * @scd_queue: scheduler queue to confiug 5150 * @enable: 1 queue enable, 0 queue disable 5151 * @aggregate: 1 aggregated queue, 0 otherwise 5152 * @tx_fifo: %enum iwx_tx_fifo 5153 * @window: BA window size 5154 * @ssn: SSN for the BA agreement 5155 */ 5156 struct iwx_scd_txq_cfg_cmd { 5157 uint8_t token; 5158 uint8_t sta_id; 5159 uint8_t tid; 5160 uint8_t scd_queue; 5161 uint8_t enable; 5162 uint8_t aggregate; 5163 uint8_t tx_fifo; 5164 uint8_t window; 5165 uint16_t ssn; 5166 uint16_t reserved; 5167 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */ 5168 5169 /** 5170 * struct iwx_scd_txq_cfg_rsp 5171 * @token: taken from the command 5172 * @sta_id: station id from the command 5173 * @tid: tid from the command 5174 * @scd_queue: scd_queue from the command 5175 */ 5176 struct iwx_scd_txq_cfg_rsp { 5177 uint8_t token; 5178 uint8_t sta_id; 5179 uint8_t tid; 5180 uint8_t scd_queue; 5181 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */ 5182 5183 5184 /* Scan Commands, Responses, Notifications */ 5185 5186 /* Max number of IEs for direct SSID scans in a command */ 5187 #define IWX_PROBE_OPTION_MAX 20 5188 5189 /** 5190 * struct iwx_ssid_ie - directed scan network information element 5191 * 5192 * Up to 20 of these may appear in IWX_REPLY_SCAN_CMD, 5193 * selected by "type" bit field in struct iwx_scan_channel; 5194 * each channel may select different ssids from among the 20 entries. 5195 * SSID IEs get transmitted in reverse order of entry. 5196 */ 5197 struct iwx_ssid_ie { 5198 uint8_t id; 5199 uint8_t len; 5200 uint8_t ssid[IEEE80211_NWID_LEN]; 5201 } __packed; /* IWX_SCAN_DIRECT_SSID_IE_API_S_VER_1 */ 5202 5203 /* scan offload */ 5204 #define IWX_SCAN_MAX_BLACKLIST_LEN 64 5205 #define IWX_SCAN_SHORT_BLACKLIST_LEN 16 5206 #define IWX_SCAN_MAX_PROFILES 11 5207 #define IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE 512 5208 5209 /* Default watchdog (in MS) for scheduled scan iteration */ 5210 #define IWX_SCHED_SCAN_WATCHDOG cpu_to_le16(15000) 5211 5212 #define IWX_GOOD_CRC_TH_DEFAULT cpu_to_le16(1) 5213 #define IWX_CAN_ABORT_STATUS 1 5214 5215 #define IWX_FULL_SCAN_MULTIPLIER 5 5216 #define IWX_FAST_SCHED_SCAN_ITERATIONS 3 5217 #define IWX_MAX_SCHED_SCAN_PLANS 2 5218 5219 /** 5220 * iwx_scan_schedule_lmac - schedule of scan offload 5221 * @delay: delay between iterations, in seconds. 5222 * @iterations: num of scan iterations 5223 * @full_scan_mul: number of partial scans before each full scan 5224 */ 5225 struct iwx_scan_schedule_lmac { 5226 uint16_t delay; 5227 uint8_t iterations; 5228 uint8_t full_scan_mul; 5229 } __packed; /* SCAN_SCHEDULE_API_S */ 5230 5231 /** 5232 * iwx_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S 5233 * @tx_flags: combination of TX_CMD_FLG_* 5234 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is 5235 * cleared. Combination of RATE_MCS_* 5236 * @sta_id: index of destination station in FW station table 5237 * @reserved: for alignment and future use 5238 */ 5239 struct iwx_scan_req_tx_cmd { 5240 uint32_t tx_flags; 5241 uint32_t rate_n_flags; 5242 uint8_t sta_id; 5243 uint8_t reserved[3]; 5244 } __packed; 5245 5246 #define IWX_UNIFIED_SCAN_CHANNEL_FULL (1 << 27) 5247 #define IWX_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28) 5248 5249 /** 5250 * iwx_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2 5251 * @flags: bits 1-20: directed scan to i'th ssid 5252 * other bits &enum iwx_scan_channel_flags_lmac 5253 * @channel_number: channel number 1-13 etc 5254 * @iter_count: scan iteration on this channel 5255 * @iter_interval: interval in seconds between iterations on one channel 5256 */ 5257 struct iwx_scan_channel_cfg_lmac { 5258 uint32_t flags; 5259 uint16_t channel_num; 5260 uint16_t iter_count; 5261 uint32_t iter_interval; 5262 } __packed; 5263 5264 /* 5265 * iwx_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1 5266 * @offset: offset in the data block 5267 * @len: length of the segment 5268 */ 5269 struct iwx_scan_probe_segment { 5270 uint16_t offset; 5271 uint16_t len; 5272 } __packed; 5273 5274 /* iwx_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2 5275 * @mac_header: first (and common) part of the probe 5276 * @band_data: band specific data 5277 * @common_data: last (and common) part of the probe 5278 * @buf: raw data block 5279 */ 5280 struct iwx_scan_probe_req_v1 { 5281 struct iwx_scan_probe_segment mac_header; 5282 struct iwx_scan_probe_segment band_data[2]; 5283 struct iwx_scan_probe_segment common_data; 5284 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5285 } __packed; 5286 5287 /* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2 5288 * @mac_header: first (and common) part of the probe 5289 * @band_data: band specific data 5290 * @common_data: last (and common) part of the probe 5291 * @buf: raw data block 5292 */ 5293 struct iwx_scan_probe_req { 5294 struct iwx_scan_probe_segment mac_header; 5295 struct iwx_scan_probe_segment band_data[3]; 5296 struct iwx_scan_probe_segment common_data; 5297 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE]; 5298 } __packed; 5299 5300 5301 #define IWX_SCAN_CHANNEL_FLAG_EBS (1 << 0) 5302 #define IWX_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1) 5303 #define IWX_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2) 5304 5305 /* iwx_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S 5306 * @flags: enum iwx_scan_channel_flags 5307 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is 5308 * involved. 5309 * 1 - EBS is disabled. 5310 * 2 - every second scan will be full scan(and so on). 5311 */ 5312 struct iwx_scan_channel_opt { 5313 uint16_t flags; 5314 uint16_t non_ebs_ratio; 5315 } __packed; 5316 5317 #define IWX_SCAN_PRIORITY_LOW 0 5318 #define IWX_SCAN_PRIORITY_MEDIUM 1 5319 #define IWX_SCAN_PRIORITY_HIGH 2 5320 5321 /** 5322 * iwx_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2 5323 * @last_schedule_line: last schedule line executed (fast or regular) 5324 * @last_schedule_iteration: last scan iteration executed before scan abort 5325 * @status: enum iwx_scan_offload_complete_status 5326 * @ebs_status: EBS success status &enum iwx_scan_ebs_status 5327 * @time_after_last_iter; time in seconds elapsed after last iteration 5328 */ 5329 struct iwx_periodic_scan_complete { 5330 uint8_t last_schedule_line; 5331 uint8_t last_schedule_iteration; 5332 uint8_t status; 5333 uint8_t ebs_status; 5334 uint32_t time_after_last_iter; 5335 uint32_t reserved; 5336 } __packed; 5337 5338 /** 5339 * struct iwx_scan_results_notif - scan results for one channel - 5340 * SCAN_RESULT_NTF_API_S_VER_3 5341 * @channel: which channel the results are from 5342 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz 5343 * @probe_status: IWX_SCAN_PROBE_STATUS_*, indicates success of probe request 5344 * @num_probe_not_sent: # of request that weren't sent due to not enough time 5345 * @duration: duration spent in channel, in usecs 5346 */ 5347 struct iwx_scan_results_notif { 5348 uint8_t channel; 5349 uint8_t band; 5350 uint8_t probe_status; 5351 uint8_t num_probe_not_sent; 5352 uint32_t duration; 5353 } __packed; 5354 5355 #define IWX_SCAN_CLIENT_SCHED_SCAN (1 << 0) 5356 #define IWX_SCAN_CLIENT_NETDETECT (1 << 1) 5357 #define IWX_SCAN_CLIENT_ASSET_TRACKING (1 << 2) 5358 5359 /** 5360 * iwx_scan_offload_blacklist - IWX_SCAN_OFFLOAD_BLACKLIST_S 5361 * @ssid: MAC address to filter out 5362 * @reported_rssi: AP rssi reported to the host 5363 * @client_bitmap: clients ignore this entry - enum scan_framework_client 5364 */ 5365 struct iwx_scan_offload_blacklist { 5366 uint8_t ssid[ETHER_ADDR_LEN]; 5367 uint8_t reported_rssi; 5368 uint8_t client_bitmap; 5369 } __packed; 5370 5371 #define IWX_NETWORK_TYPE_BSS 1 5372 #define IWX_NETWORK_TYPE_IBSS 2 5373 #define IWX_NETWORK_TYPE_ANY 3 5374 5375 #define IWX_SCAN_OFFLOAD_SELECT_2_4 0x4 5376 #define IWX_SCAN_OFFLOAD_SELECT_5_2 0x8 5377 #define IWX_SCAN_OFFLOAD_SELECT_ANY 0xc 5378 5379 /** 5380 * iwx_scan_offload_profile - IWX_SCAN_OFFLOAD_PROFILE_S 5381 * @ssid_index: index to ssid list in fixed part 5382 * @unicast_cipher: encryption olgorithm to match - bitmap 5383 * @aut_alg: authentication olgorithm to match - bitmap 5384 * @network_type: enum iwx_scan_offload_network_type 5385 * @band_selection: enum iwx_scan_offload_band_selection 5386 * @client_bitmap: clients waiting for match - enum scan_framework_client 5387 */ 5388 struct iwx_scan_offload_profile { 5389 uint8_t ssid_index; 5390 uint8_t unicast_cipher; 5391 uint8_t auth_alg; 5392 uint8_t network_type; 5393 uint8_t band_selection; 5394 uint8_t client_bitmap; 5395 uint8_t reserved[2]; 5396 } __packed; 5397 5398 /** 5399 * iwx_scan_offload_profile_cfg - IWX_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1 5400 * @blaclist: AP list to filter off from scan results 5401 * @profiles: profiles to search for match 5402 * @blacklist_len: length of blacklist 5403 * @num_profiles: num of profiles in the list 5404 * @match_notify: clients waiting for match found notification 5405 * @pass_match: clients waiting for the results 5406 * @active_clients: active clients bitmap - enum scan_framework_client 5407 * @any_beacon_notify: clients waiting for match notification without match 5408 */ 5409 struct iwx_scan_offload_profile_cfg { 5410 struct iwx_scan_offload_profile profiles[IWX_SCAN_MAX_PROFILES]; 5411 uint8_t blacklist_len; 5412 uint8_t num_profiles; 5413 uint8_t match_notify; 5414 uint8_t pass_match; 5415 uint8_t active_clients; 5416 uint8_t any_beacon_notify; 5417 uint8_t reserved[2]; 5418 } __packed; 5419 5420 #define IWX_SCAN_OFFLOAD_COMPLETED 1 5421 #define IWX_SCAN_OFFLOAD_ABORTED 2 5422 5423 /* UMAC Scan API */ 5424 5425 #define IWX_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0) 5426 #define IWX_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1) 5427 #define IWX_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2) 5428 #define IWX_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3) 5429 #define IWX_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8) 5430 #define IWX_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9) 5431 #define IWX_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10) 5432 #define IWX_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11) 5433 #define IWX_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12) 5434 #define IWX_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13) 5435 #define IWX_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14) 5436 #define IWX_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15) 5437 #define IWX_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16) 5438 #define IWX_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17) 5439 #define IWX_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18) 5440 #define IWX_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19) 5441 #define IWX_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20) 5442 #define IWX_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21) 5443 5444 /* Bits 26-31 are for num of channels in channel_array */ 5445 #define IWX_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26) 5446 5447 /* OFDM basic rates */ 5448 #define IWX_SCAN_CONFIG_RATE_6M (1 << 0) 5449 #define IWX_SCAN_CONFIG_RATE_9M (1 << 1) 5450 #define IWX_SCAN_CONFIG_RATE_12M (1 << 2) 5451 #define IWX_SCAN_CONFIG_RATE_18M (1 << 3) 5452 #define IWX_SCAN_CONFIG_RATE_24M (1 << 4) 5453 #define IWX_SCAN_CONFIG_RATE_36M (1 << 5) 5454 #define IWX_SCAN_CONFIG_RATE_48M (1 << 6) 5455 #define IWX_SCAN_CONFIG_RATE_54M (1 << 7) 5456 /* CCK basic rates */ 5457 #define IWX_SCAN_CONFIG_RATE_1M (1 << 8) 5458 #define IWX_SCAN_CONFIG_RATE_2M (1 << 9) 5459 #define IWX_SCAN_CONFIG_RATE_5M (1 << 10) 5460 #define IWX_SCAN_CONFIG_RATE_11M (1 << 11) 5461 5462 /* Bits 16-27 are for supported rates */ 5463 #define IWX_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16) 5464 5465 #define IWX_CHANNEL_FLAG_EBS (1 << 0) 5466 #define IWX_CHANNEL_FLAG_ACCURATE_EBS (1 << 1) 5467 #define IWX_CHANNEL_FLAG_EBS_ADD (1 << 2) 5468 #define IWX_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3) 5469 5470 /** 5471 * struct iwx_scan_dwell 5472 * @active: default dwell time for active scan 5473 * @passive: default dwell time for passive scan 5474 * @fragmented: default dwell time for fragmented scan 5475 * @extended: default dwell time for channels 1, 6 and 11 5476 */ 5477 struct iwx_scan_dwell { 5478 uint8_t active; 5479 uint8_t passive; 5480 uint8_t fragmented; 5481 uint8_t extended; 5482 } __packed; 5483 5484 5485 #define IWX_SCAN_TWO_LMACS 2 5486 #define IWX_SCAN_LB_LMAC_IDX 0 /* low-band */ 5487 #define IWX_SCAN_HB_LMAC_IDX 1 /* high-band */ 5488 5489 /** 5490 * struct iwx_scan_config 5491 * @flags: enum scan_config_flags 5492 * @tx_chains: valid_tx antenna - ANT_* definitions 5493 * @rx_chains: valid_rx antenna - ANT_* definitions 5494 * @legacy_rates: default legacy rates - enum scan_config_rates 5495 * @out_of_channel_time: default max out of serving channel time 5496 * @suspend_time: default max suspend time 5497 * @dwell_active: default dwell time for active scan 5498 * @dwell_passive: default dwell time for passive scan 5499 * @dwell_fragmented: default dwell time for fragmented scan 5500 * @dwell_extended: default dwell time for channels 1, 6 and 11 5501 * @mac_addr: default mac address to be used in probes 5502 * @bcast_sta_id: the index of the station in the fw 5503 * @channel_flags: default channel flags - enum iwx_channel_flags 5504 * scan_config_channel_flag 5505 * @channel_array: default supported channels 5506 */ 5507 struct iwx_scan_config { 5508 uint32_t flags; 5509 uint32_t tx_chains; 5510 uint32_t rx_chains; 5511 uint32_t legacy_rates; 5512 uint32_t out_of_channel_time[IWX_SCAN_TWO_LMACS]; 5513 uint32_t suspend_time[IWX_SCAN_TWO_LMACS]; 5514 struct iwx_scan_dwell dwell; 5515 uint8_t mac_addr[ETHER_ADDR_LEN]; 5516 uint8_t bcast_sta_id; 5517 uint8_t channel_flags; 5518 uint8_t channel_array[]; 5519 } __packed; /* SCAN_CONFIG_DB_CMD_API_S_2 */ 5520 5521 /** 5522 * iwx_umac_scan_flags 5523 *@IWX_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request 5524 * can be preempted by other scan requests with higher priority. 5525 * The low priority scan will be resumed when the higher proirity scan is 5526 * completed. 5527 *@IWX_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver 5528 * when scan starts. 5529 */ 5530 #define IWX_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0) 5531 #define IWX_UMAC_SCAN_FLAG_START_NOTIF (1 << 1) 5532 5533 #define IWX_UMAC_SCAN_UID_TYPE_OFFSET 0 5534 #define IWX_UMAC_SCAN_UID_SEQ_OFFSET 8 5535 5536 #define IWX_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0) 5537 #define IWX_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1) 5538 #define IWX_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2) 5539 #define IWX_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3) 5540 #define IWX_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4) 5541 #define IWX_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5) 5542 #define IWX_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6) 5543 #define IWX_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7) 5544 #define IWX_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8) 5545 #define IWX_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9) 5546 #define IWX_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10) 5547 /* Extended dwell is obselete when adaptive dwell is used, making this 5548 * bit reusable. Hence, probe request defer is used only when adaptive 5549 * dwell is supported. */ 5550 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10) 5551 #define IWX_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11) 5552 #define IWX_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13) 5553 #define IWX_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14) 5554 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15) 5555 5556 /** 5557 * UMAC scan general flags #2 5558 * @IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete 5559 * notification per channel or not. 5560 * @IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel 5561 * reorder optimization or not. 5562 */ 5563 #define IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0) 5564 #define IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1) 5565 5566 /** 5567 * UMAC scan general flags version 2 5568 * 5569 * The FW flags were reordered and hence the driver introduce version 2 5570 * 5571 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC: periodic or scheduled 5572 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL: pass all probe responses and beacons 5573 * during scan iterations 5574 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE: send complete notification 5575 * on every iteration instead of only once after the last iteration 5576 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1: fragmented scan LMAC1 5577 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2: fragmented scan LMAC2 5578 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH: does this scan check for profile matching 5579 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS: use all valid chains for RX 5580 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL: works with adaptive dwell 5581 * for active channel 5582 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE: can be preempted by other requests 5583 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START: send notification of scan start 5584 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID: matching on multiple SSIDs 5585 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE: all the channels scanned 5586 * as passive 5587 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN: at the end of 2.4GHz and 5588 * 5.2Ghz bands scan, trigger scan on 6GHz band to discover 5589 * the reported collocated APs 5590 */ 5591 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC (1 << 0) 5592 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL (1 << 1) 5593 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE (1 << 2) 5594 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1 (1 << 3) 5595 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2 (1 << 4) 5596 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH (1 << 5) 5597 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS (1 << 6) 5598 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL (1 << 7) 5599 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE (1 << 8) 5600 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START (1 << 9) 5601 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID (1 << 10) 5602 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE (1 << 11) 5603 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN (1 << 12) 5604 5605 /** 5606 * struct iwx_scan_channel_cfg_umac 5607 * @flags: bitmap - 0-19: directed scan to i'th ssid. 5608 * @channel_num: channel number 1-13 etc. 5609 * @iter_count: repetition count for the channel. 5610 * @iter_interval: interval between two scan iterations on one channel. 5611 */ 5612 struct iwx_scan_channel_cfg_umac { 5613 uint32_t flags; 5614 union { 5615 struct { 5616 uint8_t channel_num; 5617 uint8_t iter_count; 5618 uint16_t iter_interval; 5619 } v1; /* SCAN_CHANNEL_CFG_S_VER1 */ 5620 struct { 5621 uint8_t channel_num; 5622 uint8_t band; 5623 uint8_t iter_count; 5624 uint8_t iter_interval; 5625 } v2; /* SCAN_CHANNEL_CFG_S_VER{2,3,4} */ 5626 }; 5627 } __packed; 5628 5629 /** 5630 * struct iwx_scan_umac_schedule 5631 * @interval: interval in seconds between scan iterations 5632 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop 5633 * @reserved: for alignment and future use 5634 */ 5635 struct iwx_scan_umac_schedule { 5636 uint16_t interval; 5637 uint8_t iter_count; 5638 uint8_t reserved; 5639 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */ 5640 5641 /** 5642 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command 5643 * parameters following channels configuration array. 5644 * @schedule: two scheduling plans. 5645 * @delay: delay in TUs before starting the first scan iteration 5646 * @reserved: for future use and alignment 5647 * @preq: probe request with IEs blocks 5648 * @direct_scan: list of SSIDs for directed active scan 5649 */ 5650 struct iwx_scan_req_umac_tail_v1 { 5651 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5652 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 5653 uint16_t delay; 5654 uint16_t reserved; 5655 /* SCAN_PROBE_PARAMS_API_S_VER_1 */ 5656 struct iwx_scan_probe_req_v1 preq; 5657 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 5658 } __packed; 5659 5660 /** 5661 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command 5662 * parameters following channels configuration array. 5663 * @schedule: two scheduling plans. 5664 * @delay: delay in TUs before starting the first scan iteration 5665 * @reserved: for future use and alignment 5666 * @preq: probe request with IEs blocks 5667 * @direct_scan: list of SSIDs for directed active scan 5668 */ 5669 struct iwx_scan_req_umac_tail_v2 { 5670 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */ 5671 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS]; 5672 uint16_t delay; 5673 uint16_t reserved; 5674 /* SCAN_PROBE_PARAMS_API_S_VER_2 */ 5675 struct iwx_scan_probe_req preq; 5676 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX]; 5677 } __packed; 5678 5679 /** 5680 * struct iwx_scan_umac_chan_param 5681 * @flags: channel flags &enum iwl_scan_channel_flags 5682 * @count: num of channels in scan request 5683 * @reserved: for future use and alignment 5684 */ 5685 struct iwx_scan_umac_chan_param { 5686 uint8_t flags; 5687 uint8_t count; 5688 uint16_t reserved; 5689 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */ 5690 5691 #define IWX_SCAN_LB_LMAC_IDX 0 5692 #define IWX_SCAN_HB_LMAC_IDX 1 5693 5694 /** 5695 * struct iwx_scan_req_umac 5696 * @flags: &enum iwl_umac_scan_flags 5697 * @uid: scan id, &enum iwl_umac_scan_uid_offsets 5698 * @ooc_priority: out of channel priority - &enum iwl_scan_priority 5699 * @general_flags: &enum iwl_umac_scan_general_flags 5700 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF 5701 * @extended_dwell: dwell time for channels 1, 6 and 11 5702 * @active_dwell: dwell time for active scan per LMAC 5703 * @passive_dwell: dwell time for passive scan per LMAC 5704 * @fragmented_dwell: dwell time for fragmented passive scan 5705 * @adwell_default_n_aps: for adaptive dwell the default number of APs 5706 * per channel 5707 * @adwell_default_n_aps_social: for adaptive dwell the default 5708 * number of APs per social (1,6,11) channel 5709 * @general_flags2: &enum iwl_umac_scan_general_flags2 5710 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added 5711 * to total scan time 5712 * @max_out_time: max out of serving channel time, per LMAC - for CDB there 5713 * are 2 LMACs (high band and low band) 5714 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs 5715 * @scan_priority: scan internal prioritization &enum iwl_scan_priority 5716 * @num_of_fragments: Number of fragments needed for full coverage per band. 5717 * Relevant only for fragmented scan. 5718 * @channel: &struct iwx_scan_umac_chan_param 5719 * @reserved: for future use and alignment 5720 * @reserved3: for future use and alignment 5721 * @data: &struct iwx_scan_channel_cfg_umac and 5722 * &struct iwx_scan_req_umac_tail 5723 */ 5724 struct iwx_scan_req_umac { 5725 uint32_t flags; 5726 uint32_t uid; 5727 uint32_t ooc_priority; 5728 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */ 5729 uint16_t general_flags; 5730 uint8_t reserved; 5731 uint8_t scan_start_mac_id; 5732 union { 5733 struct { 5734 uint8_t extended_dwell; 5735 uint8_t active_dwell; 5736 uint8_t passive_dwell; 5737 uint8_t fragmented_dwell; 5738 uint32_t max_out_time; 5739 uint32_t suspend_time; 5740 uint32_t scan_priority; 5741 struct iwx_scan_umac_chan_param channel; 5742 uint8_t data[]; 5743 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */ 5744 struct { 5745 uint8_t extended_dwell; 5746 uint8_t active_dwell; 5747 uint8_t passive_dwell; 5748 uint8_t fragmented_dwell; 5749 uint32_t max_out_time[2]; 5750 uint32_t suspend_time[2]; 5751 uint32_t scan_priority; 5752 struct iwx_scan_umac_chan_param channel; 5753 uint8_t data[]; 5754 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */ 5755 struct { 5756 uint8_t active_dwell; 5757 uint8_t passive_dwell; 5758 uint8_t fragmented_dwell; 5759 uint8_t adwell_default_n_aps; 5760 uint8_t adwell_default_n_aps_social; 5761 uint8_t reserved3; 5762 uint16_t adwell_max_budget; 5763 uint32_t max_out_time[2]; 5764 uint32_t suspend_time[2]; 5765 uint32_t scan_priority; 5766 struct iwx_scan_umac_chan_param channel; 5767 uint8_t data[]; 5768 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */ 5769 struct { 5770 uint8_t active_dwell[2]; 5771 uint8_t reserved2; 5772 uint8_t adwell_default_n_aps; 5773 uint8_t adwell_default_n_aps_social; 5774 uint8_t general_flags2; 5775 uint16_t adwell_max_budget; 5776 uint32_t max_out_time[2]; 5777 uint32_t suspend_time[2]; 5778 uint32_t scan_priority; 5779 uint8_t passive_dwell[2]; 5780 uint8_t num_of_fragments[2]; 5781 struct iwx_scan_umac_chan_param channel; 5782 uint8_t data[]; 5783 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */ 5784 struct { 5785 uint8_t active_dwell[2]; 5786 uint8_t adwell_default_hb_n_aps; 5787 uint8_t adwell_default_lb_n_aps; 5788 uint8_t adwell_default_n_aps_social; 5789 uint8_t general_flags2; 5790 uint16_t adwell_max_budget; 5791 uint32_t max_out_time[2]; 5792 uint32_t suspend_time[2]; 5793 uint32_t scan_priority; 5794 uint8_t passive_dwell[2]; 5795 uint8_t num_of_fragments[2]; 5796 struct iwx_scan_umac_chan_param channel; 5797 uint8_t data[]; 5798 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */ 5799 }; 5800 } __packed; 5801 5802 #define IWX_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwx_scan_req_umac) 5803 #define IWX_SCAN_REQ_UMAC_SIZE_V7 48 5804 #define IWX_SCAN_REQ_UMAC_SIZE_V6 44 5805 #define IWX_SCAN_REQ_UMAC_SIZE_V1 36 5806 5807 /** 5808 * struct iwx_umac_scan_abort 5809 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 5810 * @flags: reserved 5811 */ 5812 struct iwx_umac_scan_abort { 5813 uint32_t uid; 5814 uint32_t flags; 5815 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */ 5816 5817 /** 5818 * struct iwx_umac_scan_complete 5819 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 5820 * @last_schedule: last scheduling line 5821 * @last_iter: last scan iteration number 5822 * @scan status: &enum iwx_scan_offload_complete_status 5823 * @ebs_status: &enum iwx_scan_ebs_status 5824 * @time_from_last_iter: time elapsed from last iteration 5825 * @reserved: for future use 5826 */ 5827 struct iwx_umac_scan_complete { 5828 uint32_t uid; 5829 uint8_t last_schedule; 5830 uint8_t last_iter; 5831 uint8_t status; 5832 uint8_t ebs_status; 5833 uint32_t time_from_last_iter; 5834 uint32_t reserved; 5835 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5836 5837 #define IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5 5838 /** 5839 * struct iwx_scan_offload_profile_match - match information 5840 * @bssid: matched bssid 5841 * @channel: channel where the match occurred 5842 * @energy: 5843 * @matching_feature: 5844 * @matching_channels: bitmap of channels that matched, referencing 5845 * the channels passed in tue scan offload request 5846 */ 5847 struct iwx_scan_offload_profile_match { 5848 uint8_t bssid[ETHER_ADDR_LEN]; 5849 uint16_t reserved; 5850 uint8_t channel; 5851 uint8_t energy; 5852 uint8_t matching_feature; 5853 uint8_t matching_channels[IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN]; 5854 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */ 5855 5856 /** 5857 * struct iwx_scan_offload_profiles_query - match results query response 5858 * @matched_profiles: bitmap of matched profiles, referencing the 5859 * matches passed in the scan offload request 5860 * @last_scan_age: age of the last offloaded scan 5861 * @n_scans_done: number of offloaded scans done 5862 * @gp2_d0u: GP2 when D0U occurred 5863 * @gp2_invoked: GP2 when scan offload was invoked 5864 * @resume_while_scanning: not used 5865 * @self_recovery: obsolete 5866 * @reserved: reserved 5867 * @matches: array of match information, one for each match 5868 */ 5869 struct iwx_scan_offload_profiles_query { 5870 uint32_t matched_profiles; 5871 uint32_t last_scan_age; 5872 uint32_t n_scans_done; 5873 uint32_t gp2_d0u; 5874 uint32_t gp2_invoked; 5875 uint8_t resume_while_scanning; 5876 uint8_t self_recovery; 5877 uint16_t reserved; 5878 struct iwx_scan_offload_profile_match matches[IWX_SCAN_MAX_PROFILES]; 5879 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */ 5880 5881 /** 5882 * struct iwx_umac_scan_iter_complete_notif - notifies end of scanning iteration 5883 * @uid: scan id, &enum iwx_umac_scan_uid_offsets 5884 * @scanned_channels: number of channels scanned and number of valid elements in 5885 * results array 5886 * @status: one of SCAN_COMP_STATUS_* 5887 * @bt_status: BT on/off status 5888 * @last_channel: last channel that was scanned 5889 * @tsf_low: TSF timer (lower half) in usecs 5890 * @tsf_high: TSF timer (higher half) in usecs 5891 * @results: array of scan results, only "scanned_channels" of them are valid 5892 */ 5893 struct iwx_umac_scan_iter_complete_notif { 5894 uint32_t uid; 5895 uint8_t scanned_channels; 5896 uint8_t status; 5897 uint8_t bt_status; 5898 uint8_t last_channel; 5899 uint32_t tsf_low; 5900 uint32_t tsf_high; 5901 struct iwx_scan_results_notif results[]; 5902 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */ 5903 5904 #define IWX_GSCAN_START_CMD 0x0 5905 #define IWX_GSCAN_STOP_CMD 0x1 5906 #define IWX_GSCAN_SET_HOTLIST_CMD 0x2 5907 #define IWX_GSCAN_RESET_HOTLIST_CMD 0x3 5908 #define IWX_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4 5909 #define IWX_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5 5910 #define IWX_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD 5911 #define IWX_GSCAN_HOTLIST_CHANGE_EVENT 0xFE 5912 #define IWX_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF 5913 5914 /* STA API */ 5915 5916 /** 5917 * flags for the ADD_STA host command 5918 * @IWX_STA_FLG_REDUCED_TX_PWR_CTRL: 5919 * @IWX_STA_FLG_REDUCED_TX_PWR_DATA: 5920 * @IWX_STA_FLG_DISABLE_TX: set if TX should be disabled 5921 * @IWX_STA_FLG_PS: set if STA is in Power Save 5922 * @IWX_STA_FLG_INVALID: set if STA is invalid 5923 * @IWX_STA_FLG_DLP_EN: Direct Link Protocol is enabled 5924 * @IWX_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs 5925 * @IWX_STA_FLG_DRAIN_FLOW: drain flow 5926 * @IWX_STA_FLG_PAN: STA is for PAN interface 5927 * @IWX_STA_FLG_CLASS_AUTH: 5928 * @IWX_STA_FLG_CLASS_ASSOC: 5929 * @IWX_STA_FLG_CLASS_MIMO_PROT: 5930 * @IWX_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU 5931 * @IWX_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation 5932 * @IWX_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is 5933 * initialised by driver and can be updated by fw upon reception of 5934 * action frames that can change the channel width. When cleared the fw 5935 * will send all the frames in 20MHz even when FAT channel is requested. 5936 * @IWX_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the 5937 * driver and can be updated by fw upon reception of action frames. 5938 * @IWX_STA_FLG_MFP_EN: Management Frame Protection 5939 */ 5940 #define IWX_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3) 5941 #define IWX_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6) 5942 5943 #define IWX_STA_FLG_DISABLE_TX (1 << 4) 5944 5945 #define IWX_STA_FLG_PS (1 << 8) 5946 #define IWX_STA_FLG_DRAIN_FLOW (1 << 12) 5947 #define IWX_STA_FLG_PAN (1 << 13) 5948 #define IWX_STA_FLG_CLASS_AUTH (1 << 14) 5949 #define IWX_STA_FLG_CLASS_ASSOC (1 << 15) 5950 #define IWX_STA_FLG_RTS_MIMO_PROT (1 << 17) 5951 5952 #define IWX_STA_FLG_MAX_AGG_SIZE_SHIFT 19 5953 #define IWX_STA_FLG_MAX_AGG_SIZE_8K (0 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5954 #define IWX_STA_FLG_MAX_AGG_SIZE_16K (1 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5955 #define IWX_STA_FLG_MAX_AGG_SIZE_32K (2 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5956 #define IWX_STA_FLG_MAX_AGG_SIZE_64K (3 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5957 #define IWX_STA_FLG_MAX_AGG_SIZE_128K (4 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5958 #define IWX_STA_FLG_MAX_AGG_SIZE_256K (5 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5959 #define IWX_STA_FLG_MAX_AGG_SIZE_512K (6 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5960 #define IWX_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5961 #define IWX_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT) 5962 5963 #define IWX_STA_FLG_AGG_MPDU_DENS_SHIFT 23 5964 #define IWX_STA_FLG_AGG_MPDU_DENS_2US (4 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5965 #define IWX_STA_FLG_AGG_MPDU_DENS_4US (5 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5966 #define IWX_STA_FLG_AGG_MPDU_DENS_8US (6 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5967 #define IWX_STA_FLG_AGG_MPDU_DENS_16US (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5968 #define IWX_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT) 5969 5970 #define IWX_STA_FLG_FAT_EN_20MHZ (0 << 26) 5971 #define IWX_STA_FLG_FAT_EN_40MHZ (1 << 26) 5972 #define IWX_STA_FLG_FAT_EN_80MHZ (2 << 26) 5973 #define IWX_STA_FLG_FAT_EN_160MHZ (3 << 26) 5974 #define IWX_STA_FLG_FAT_EN_MSK (3 << 26) 5975 5976 #define IWX_STA_FLG_MIMO_EN_SISO (0 << 28) 5977 #define IWX_STA_FLG_MIMO_EN_MIMO2 (1 << 28) 5978 #define IWX_STA_FLG_MIMO_EN_MIMO3 (2 << 28) 5979 #define IWX_STA_FLG_MIMO_EN_MSK (3 << 28) 5980 5981 /** 5982 * key flags for the ADD_STA host command 5983 * @IWX_STA_KEY_FLG_NO_ENC: no encryption 5984 * @IWX_STA_KEY_FLG_WEP: WEP encryption algorithm 5985 * @IWX_STA_KEY_FLG_CCM: CCMP encryption algorithm 5986 * @IWX_STA_KEY_FLG_TKIP: TKIP encryption algorithm 5987 * @IWX_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) 5988 * @IWX_STA_KEY_FLG_CMAC: CMAC encryption algorithm 5989 * @IWX_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm 5990 * @IWX_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value 5991 * @IWX_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from 5992 * station info array (1 - n 1X mode) 5993 * @IWX_STA_KEY_FLG_KEYID_MSK: the index of the key 5994 * @IWX_STA_KEY_NOT_VALID: key is invalid 5995 * @IWX_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key 5996 * @IWX_STA_KEY_MULTICAST: set for multicast key 5997 * @IWX_STA_KEY_MFP: key is used for Management Frame Protection 5998 */ 5999 #define IWX_STA_KEY_FLG_NO_ENC (0 << 0) 6000 #define IWX_STA_KEY_FLG_WEP (1 << 0) 6001 #define IWX_STA_KEY_FLG_CCM (2 << 0) 6002 #define IWX_STA_KEY_FLG_TKIP (3 << 0) 6003 #define IWX_STA_KEY_FLG_EXT (4 << 0) 6004 #define IWX_STA_KEY_FLG_CMAC (6 << 0) 6005 #define IWX_STA_KEY_FLG_ENC_UNKNOWN (7 << 0) 6006 #define IWX_STA_KEY_FLG_EN_MSK (7 << 0) 6007 #define IWX_STA_KEY_FLG_WEP_KEY_MAP (1 << 3) 6008 #define IWX_STA_KEY_FLG_KEYID_POS 8 6009 #define IWX_STA_KEY_FLG_KEYID_MSK (3 << IWX_STA_KEY_FLG_KEYID_POS) 6010 #define IWX_STA_KEY_NOT_VALID (1 << 11) 6011 #define IWX_STA_KEY_FLG_WEP_13BYTES (1 << 12) 6012 #define IWX_STA_KEY_MULTICAST (1 << 14) 6013 #define IWX_STA_KEY_MFP (1 << 15) 6014 6015 /** 6016 * indicate to the fw what flag are being changed 6017 * @IWX_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue 6018 * @IWX_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx 6019 * @IWX_STA_MODIFY_TX_RATE: unused 6020 * @IWX_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid 6021 * @IWX_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid 6022 * @IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count 6023 * @IWX_STA_MODIFY_PROT_TH: 6024 * @IWX_STA_MODIFY_QUEUES: modify the queues used by this station 6025 */ 6026 #define IWX_STA_MODIFY_QUEUE_REMOVAL (1 << 0) 6027 #define IWX_STA_MODIFY_TID_DISABLE_TX (1 << 1) 6028 #define IWX_STA_MODIFY_TX_RATE (1 << 2) 6029 #define IWX_STA_MODIFY_ADD_BA_TID (1 << 3) 6030 #define IWX_STA_MODIFY_REMOVE_BA_TID (1 << 4) 6031 #define IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5) 6032 #define IWX_STA_MODIFY_PROT_TH (1 << 6) 6033 #define IWX_STA_MODIFY_QUEUES (1 << 7) 6034 6035 #define IWX_STA_MODE_MODIFY 1 6036 6037 /** 6038 * type of sleep of the station 6039 * @IWX_STA_SLEEP_STATE_AWAKE: 6040 * @IWX_STA_SLEEP_STATE_PS_POLL: 6041 * @IWX_STA_SLEEP_STATE_UAPSD: 6042 * @IWX_STA_SLEEP_STATE_MOREDATA: set more-data bit on 6043 * (last) released frame 6044 */ 6045 #define IWX_STA_SLEEP_STATE_AWAKE 0 6046 #define IWX_STA_SLEEP_STATE_PS_POLL (1 << 0) 6047 #define IWX_STA_SLEEP_STATE_UAPSD (1 << 1) 6048 #define IWX_STA_SLEEP_STATE_MOREDATA (1 << 2) 6049 6050 /* STA ID and color bits definitions */ 6051 #define IWX_STA_ID_SEED (0x0f) 6052 #define IWX_STA_ID_POS (0) 6053 #define IWX_STA_ID_MSK (IWX_STA_ID_SEED << IWX_STA_ID_POS) 6054 6055 #define IWX_STA_COLOR_SEED (0x7) 6056 #define IWX_STA_COLOR_POS (4) 6057 #define IWX_STA_COLOR_MSK (IWX_STA_COLOR_SEED << IWX_STA_COLOR_POS) 6058 6059 #define IWX_STA_ID_N_COLOR_GET_COLOR(id_n_color) \ 6060 (((id_n_color) & IWX_STA_COLOR_MSK) >> IWX_STA_COLOR_POS) 6061 #define IWX_STA_ID_N_COLOR_GET_ID(id_n_color) \ 6062 (((id_n_color) & IWX_STA_ID_MSK) >> IWX_STA_ID_POS) 6063 6064 #define IWX_STA_KEY_MAX_NUM (16) 6065 #define IWX_STA_KEY_IDX_INVALID (0xff) 6066 #define IWX_STA_KEY_MAX_DATA_KEY_NUM (4) 6067 #define IWX_MAX_GLOBAL_KEYS (4) 6068 #define IWX_STA_KEY_LEN_WEP40 (5) 6069 #define IWX_STA_KEY_LEN_WEP104 (13) 6070 6071 /** 6072 * struct iwx_keyinfo - key information 6073 * @key_flags: type %iwx_sta_key_flag 6074 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6075 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6076 * @key_offset: key offset in the fw's key table 6077 * @key: 16-byte unicast decryption key 6078 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check 6079 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only 6080 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only 6081 */ 6082 struct iwx_keyinfo { 6083 uint16_t key_flags; 6084 uint8_t tkip_rx_tsc_byte2; 6085 uint8_t reserved1; 6086 uint16_t tkip_rx_ttak[5]; 6087 uint8_t key_offset; 6088 uint8_t reserved2; 6089 uint8_t key[16]; 6090 uint64_t tx_secur_seq_cnt; 6091 uint64_t hw_tkip_mic_rx_key; 6092 uint64_t hw_tkip_mic_tx_key; 6093 } __packed; 6094 6095 #define IWX_ADD_STA_STATUS_MASK 0xFF 6096 #define IWX_ADD_STA_BAID_VALID_MASK 0x8000 6097 #define IWX_ADD_STA_BAID_MASK 0x7F00 6098 #define IWX_ADD_STA_BAID_SHIFT 8 6099 6100 /** 6101 * struct iwx_add_sta_cmd - Add/modify a station in the fw's sta table. 6102 * ( REPLY_ADD_STA = 0x18 ) 6103 * @add_modify: see &enum iwl_sta_mode 6104 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD) 6105 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable 6106 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field. 6107 * @mac_id_n_color: the Mac context this station belongs to, 6108 * see &enum iwl_ctxt_id_and_color 6109 * @addr: station's MAC address 6110 * @reserved2: reserved 6111 * @sta_id: index of station in uCode's station table 6112 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave 6113 * alone. 1 - modify, 0 - don't change. 6114 * @reserved3: reserved 6115 * @station_flags: look at &enum iwl_sta_flags 6116 * @station_flags_msk: what of %station_flags have changed, 6117 * also &enum iwl_sta_flags 6118 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx) 6119 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set 6120 * add_immediate_ba_ssn. 6121 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx) 6122 * Set %STA_MODIFY_REMOVE_BA_TID to use this field 6123 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with 6124 * add_immediate_ba_tid. 6125 * @sleep_tx_count: number of packets to transmit to station even though it is 6126 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode 6127 * keeps track of STA sleep state. 6128 * @station_type: type of this station. See &enum iwl_sta_type. 6129 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag. 6130 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP 6131 * mac-addr. 6132 * @beamform_flags: beam forming controls 6133 * @tfd_queue_msk: tfd queues used by this station. 6134 * Obselete for new TX API (9 and above). 6135 * @rx_ba_window: aggregation window size 6136 * @sp_length: the size of the SP in actual number of frames 6137 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver 6138 * enabled ACs. 6139 * 6140 * The device contains an internal table of per-station information, with info 6141 * on security keys, aggregation parameters, and Tx rates for initial Tx 6142 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD). 6143 * 6144 * ADD_STA sets up the table entry for one station, either creating a new 6145 * entry, or modifying a pre-existing one. 6146 */ 6147 struct iwx_add_sta_cmd { 6148 uint8_t add_modify; 6149 uint8_t awake_acs; 6150 uint16_t tid_disable_tx; 6151 uint32_t mac_id_n_color; 6152 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */ 6153 uint16_t reserved2; 6154 uint8_t sta_id; 6155 uint8_t modify_mask; 6156 uint16_t reserved3; 6157 uint32_t station_flags; 6158 uint32_t station_flags_msk; 6159 uint8_t add_immediate_ba_tid; 6160 uint8_t remove_immediate_ba_tid; 6161 uint16_t add_immediate_ba_ssn; 6162 uint16_t sleep_tx_count; 6163 uint8_t sleep_state_flags; 6164 uint8_t station_type; 6165 uint16_t assoc_id; 6166 uint16_t beamform_flags; 6167 uint32_t tfd_queue_msk; 6168 uint16_t rx_ba_window; 6169 uint8_t sp_length; 6170 uint8_t uapsd_acs; 6171 } __packed; /* ADD_STA_CMD_API_S_VER_10 */ 6172 6173 /** 6174 * FW station types 6175 * ( REPLY_ADD_STA = 0x18 ) 6176 * @IWX_STA_LINK: Link station - normal RX and TX traffic. 6177 * @IWX_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons 6178 * and probe responses. 6179 * @IWX_STA_MULTICAST: multicast traffic, 6180 * @IWX_STA_TDLS_LINK: TDLS link station 6181 * @IWX_STA_AUX_ACTIVITY: auxilary station (scan, ROC and so on). 6182 */ 6183 #define IWX_STA_LINK 0 6184 #define IWX_STA_GENERAL_PURPOSE 1 6185 #define IWX_STA_MULTICAST 2 6186 #define IWX_STA_TDLS_LINK 3 6187 #define IWX_STA_AUX_ACTIVITY 4 6188 6189 /** 6190 * struct iwx_add_sta_key_common - add/modify sta key common part 6191 * ( REPLY_ADD_STA_KEY = 0x17 ) 6192 * @sta_id: index of station in uCode's station table 6193 * @key_offset: key offset in key storage 6194 * @key_flags: IWX_STA_KEY_FLG_* 6195 * @key: key material data 6196 * @rx_secur_seq_cnt: RX security sequence counter for the key 6197 */ 6198 struct iwx_add_sta_key_common { 6199 uint8_t sta_id; 6200 uint8_t key_offset; 6201 uint16_t key_flags; 6202 uint8_t key[32]; 6203 uint8_t rx_secur_seq_cnt[16]; 6204 } __packed; 6205 6206 /** 6207 * struct iwx_add_sta_key_cmd_v1 - add/modify sta key 6208 * @common: see &struct iwx_add_sta_key_common 6209 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection 6210 * @reserved: reserved 6211 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx 6212 */ 6213 struct iwx_add_sta_key_cmd_v1 { 6214 struct iwx_add_sta_key_common common; 6215 uint8_t tkip_rx_tsc_byte2; 6216 uint8_t reserved; 6217 uint16_t tkip_rx_ttak[5]; 6218 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */ 6219 6220 /** 6221 * struct iwx_add_sta_key_cmd - add/modify sta key 6222 * @common: see &struct iwx_add_sta_key_common 6223 * @rx_mic_key: TKIP RX unicast or multicast key 6224 * @tx_mic_key: TKIP TX key 6225 * @transmit_seq_cnt: TSC, transmit packet number 6226 */ 6227 struct iwx_add_sta_key_cmd { 6228 struct iwx_add_sta_key_common common; 6229 uint64_t rx_mic_key; 6230 uint64_t tx_mic_key; 6231 uint64_t transmit_seq_cnt; 6232 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */ 6233 6234 /** 6235 * status in the response to ADD_STA command 6236 * @IWX_ADD_STA_SUCCESS: operation was executed successfully 6237 * @IWX_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table 6238 * @IWX_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session 6239 * @IWX_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station 6240 * that doesn't exist. 6241 */ 6242 #define IWX_ADD_STA_SUCCESS 0x1 6243 #define IWX_ADD_STA_STATIONS_OVERLOAD 0x2 6244 #define IWX_ADD_STA_IMMEDIATE_BA_FAILURE 0x4 6245 #define IWX_ADD_STA_MODIFY_NON_EXISTING_STA 0x8 6246 6247 /** 6248 * struct iwx_rm_sta_cmd - Add / modify a station in the fw's station table 6249 * ( IWX_REMOVE_STA = 0x19 ) 6250 * @sta_id: the station id of the station to be removed 6251 */ 6252 struct iwx_rm_sta_cmd { 6253 uint8_t sta_id; 6254 uint8_t reserved[3]; 6255 } __packed; /* IWX_REMOVE_STA_CMD_API_S_VER_2 */ 6256 6257 /** 6258 * struct iwx_mgmt_mcast_key_cmd 6259 * ( IWX_MGMT_MCAST_KEY = 0x1f ) 6260 * @ctrl_flags: %iwx_sta_key_flag 6261 * @IGTK: 6262 * @K1: IGTK master key 6263 * @K2: IGTK sub key 6264 * @sta_id: station ID that support IGTK 6265 * @key_id: 6266 * @receive_seq_cnt: initial RSC/PN needed for replay check 6267 */ 6268 struct iwx_mgmt_mcast_key_cmd { 6269 uint32_t ctrl_flags; 6270 uint8_t IGTK[16]; 6271 uint8_t K1[16]; 6272 uint8_t K2[16]; 6273 uint32_t key_id; 6274 uint32_t sta_id; 6275 uint64_t receive_seq_cnt; 6276 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */ 6277 6278 struct iwx_wep_key { 6279 uint8_t key_index; 6280 uint8_t key_offset; 6281 uint16_t reserved1; 6282 uint8_t key_size; 6283 uint8_t reserved2[3]; 6284 uint8_t key[16]; 6285 } __packed; 6286 6287 struct iwx_wep_key_cmd { 6288 uint32_t mac_id_n_color; 6289 uint8_t num_keys; 6290 uint8_t decryption_type; 6291 uint8_t flags; 6292 uint8_t reserved; 6293 struct iwx_wep_key wep_key[0]; 6294 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ 6295 6296 /* 6297 * BT coex 6298 */ 6299 6300 #define IWX_BT_COEX_DISABLE 0x0 6301 #define IWX_BT_COEX_NW 0x1 6302 #define IWX_BT_COEX_BT 0x2 6303 #define IWX_BT_COEX_WIFI 0x3 6304 /* BT_COEX_MODES_E */ 6305 6306 #define IWX_BT_COEX_MPLUT_ENABLED (1 << 0) 6307 #define IWX_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1) 6308 #define IWX_BT_COEX_SYNC2SCO_ENABLED (1 << 2) 6309 #define IWX_BT_COEX_CORUN_ENABLED (1 << 3) 6310 #define IWX_BT_COEX_HIGH_BAND_RET (1 << 4) 6311 /* BT_COEX_MODULES_ENABLE_E_VER_1 */ 6312 6313 /** 6314 * struct iwx_bt_coex_cmd - bt coex configuration command 6315 * @mode: enum %iwx_bt_coex_mode 6316 * @enabled_modules: enum %iwx_bt_coex_enabled_modules 6317 * 6318 * The structure is used for the BT_COEX command. 6319 */ 6320 struct iwx_bt_coex_cmd { 6321 uint32_t mode; 6322 uint32_t enabled_modules; 6323 } __packed; /* BT_COEX_CMD_API_S_VER_6 */ 6324 6325 6326 /* 6327 * Location Aware Regulatory (LAR) API - MCC updates 6328 */ 6329 6330 /** 6331 * struct iwx_mcc_update_cmd - Request the device to update geographic 6332 * regulatory profile according to the given MCC (Mobile Country Code). 6333 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6334 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6335 * MCC in the cmd response will be the relevant MCC in the NVM. 6336 * @mcc: given mobile country code 6337 * @source_id: the source from where we got the MCC, see IWX_MCC_SOURCE_* 6338 * @reserved: reserved for alignment 6339 * @key: integrity key for MCC API OEM testing 6340 * @reserved2: reserved 6341 */ 6342 struct iwx_mcc_update_cmd { 6343 uint16_t mcc; 6344 uint8_t source_id; 6345 uint8_t reserved; 6346 uint32_t key; 6347 uint32_t reserved2[5]; 6348 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */ 6349 6350 /** 6351 * iwx_mcc_update_resp_v3 - response to MCC_UPDATE_CMD. 6352 * Contains the new channel control profile map, if changed, and the new MCC 6353 * (mobile country code). 6354 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6355 * @status: see &enum iwx_mcc_update_status 6356 * @mcc: the new applied MCC 6357 * @cap: capabilities for all channels which matches the MCC 6358 * @source_id: the MCC source, see IWX_MCC_SOURCE_* 6359 * @time: time elapsed from the MCC test start (in 30 seconds TU) 6360 * @reserved: reserved. 6361 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51 6362 * channels, depending on platform) 6363 * @channels: channel control data map, DWORD for each channel. Only the first 6364 * 16bits are used. 6365 */ 6366 struct iwx_mcc_update_resp_v3 { 6367 uint32_t status; 6368 uint16_t mcc; 6369 uint8_t cap; 6370 uint8_t source_id; 6371 uint16_t time; 6372 uint16_t geo_info; 6373 uint32_t n_channels; 6374 uint32_t channels[0]; 6375 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */ 6376 6377 /** 6378 * geographic information. 6379 * @GEO_NO_INFO: no special info for this geo profile. 6380 * @GEO_WMM_ETSI_5GHZ_INFO: this geo profile limits the WMM params 6381 * for the 5 GHz band. 6382 */ 6383 #define IWX_GEO_NO_INFO 0 6384 #define IWX_GEO_WMM_ETSI_5GHZ_INFO (1 << 0) 6385 6386 /** 6387 * struct iwx_mcc_update_resp - response to MCC_UPDATE_CMD. 6388 * Contains the new channel control profile map, if changed, and the new MCC 6389 * (mobile country code). 6390 * The new MCC may be different than what was requested in MCC_UPDATE_CMD. 6391 * @status: see &enum iwl_mcc_update_status 6392 * @mcc: the new applied MCC 6393 * @cap: capabilities for all channels which matches the MCC 6394 * @time: time elapsed from the MCC test start (in units of 30 seconds) 6395 * @geo_info: geographic specific profile information 6396 * see IWX_GEO_* 6397 * @source_id: the MCC source, see IWX_MCC_SOURCE_* 6398 * @reserved: for four bytes alignment. 6399 * @n_channels: number of channels in @channels_data. 6400 * @channels: channel control data map, DWORD for each channel. Only the first 6401 * 16bits are used. 6402 */ 6403 struct iwx_mcc_update_resp { 6404 uint32_t status; 6405 uint16_t mcc; 6406 uint16_t cap; 6407 uint16_t time; 6408 uint16_t geo_info; 6409 uint8_t source_id; 6410 uint8_t reserved[3]; 6411 uint32_t n_channels; 6412 uint32_t channels[0]; 6413 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_4 */ 6414 6415 /** 6416 * struct iwx_mcc_chub_notif - chub notifies of mcc change 6417 * (MCC_CHUB_UPDATE_CMD = 0xc9) 6418 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to 6419 * the cellular and connectivity cores that gets updates of the mcc, and 6420 * notifies the ucode directly of any mcc change. 6421 * The ucode requests the driver to request the device to update geographic 6422 * regulatory profile according to the given MCC (Mobile Country Code). 6423 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain. 6424 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the 6425 * MCC in the cmd response will be the relevant MCC in the NVM. 6426 * @mcc: given mobile country code 6427 * @source_id: identity of the change originator, see IWX_MCC_SOURCE_* 6428 * @reserved1: reserved for alignment 6429 */ 6430 struct iwx_mcc_chub_notif { 6431 uint16_t mcc; 6432 uint8_t source_id; 6433 uint8_t reserved1; 6434 } __packed; /* LAR_MCC_NOTIFY_S */ 6435 6436 enum iwx_mcc_update_status { 6437 IWX_MCC_RESP_NEW_CHAN_PROFILE, 6438 IWX_MCC_RESP_SAME_CHAN_PROFILE, 6439 IWX_MCC_RESP_INVALID, 6440 IWX_MCC_RESP_NVM_DISABLED, 6441 IWX_MCC_RESP_ILLEGAL, 6442 IWX_MCC_RESP_LOW_PRIORITY, 6443 IWX_MCC_RESP_TEST_MODE_ACTIVE, 6444 IWX_MCC_RESP_TEST_MODE_NOT_ACTIVE, 6445 IWX_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE, 6446 }; 6447 6448 #define IWX_MCC_SOURCE_OLD_FW 0 6449 #define IWX_MCC_SOURCE_ME 1 6450 #define IWX_MCC_SOURCE_BIOS 2 6451 #define IWX_MCC_SOURCE_3G_LTE_HOST 3 6452 #define IWX_MCC_SOURCE_3G_LTE_DEVICE 4 6453 #define IWX_MCC_SOURCE_WIFI 5 6454 #define IWX_MCC_SOURCE_RESERVED 6 6455 #define IWX_MCC_SOURCE_DEFAULT 7 6456 #define IWX_MCC_SOURCE_UNINITIALIZED 8 6457 #define IWX_MCC_SOURCE_MCC_API 9 6458 #define IWX_MCC_SOURCE_GET_CURRENT 0x10 6459 #define IWX_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11 6460 6461 /* 6462 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811: 6463 * As the firmware is slowly running out of command IDs and grouping of 6464 * commands is desirable anyway, the firmware is extending the command 6465 * header from 4 bytes to 8 bytes to introduce a group (in place of the 6466 * former flags field, since that's always 0 on commands and thus can 6467 * be easily used to distinguish between the two). 6468 * 6469 * These functions retrieve specific information from the id field in 6470 * the iwx_host_cmd struct which contains the command id, the group id, 6471 * and the version of the command. 6472 */ 6473 static inline uint8_t 6474 iwx_cmd_opcode(uint32_t cmdid) 6475 { 6476 return cmdid & 0xff; 6477 } 6478 6479 static inline uint8_t 6480 iwx_cmd_groupid(uint32_t cmdid) 6481 { 6482 return ((cmdid & 0Xff00) >> 8); 6483 } 6484 6485 static inline uint8_t 6486 iwx_cmd_version(uint32_t cmdid) 6487 { 6488 return ((cmdid & 0xff0000) >> 16); 6489 } 6490 6491 static inline uint32_t 6492 iwx_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version) 6493 { 6494 return opcode + (groupid << 8) + (version << 16); 6495 } 6496 6497 /* make uint16_t wide id out of uint8_t group and opcode */ 6498 #define IWX_WIDE_ID(grp, opcode) ((grp << 8) | opcode) 6499 6500 struct iwx_cmd_header { 6501 uint8_t code; 6502 uint8_t flags; 6503 uint8_t idx; 6504 uint8_t qid; 6505 } __packed; 6506 6507 struct iwx_cmd_header_wide { 6508 uint8_t opcode; 6509 uint8_t group_id; 6510 uint8_t idx; 6511 uint8_t qid; 6512 uint16_t length; 6513 uint8_t reserved; 6514 uint8_t version; 6515 } __packed; 6516 6517 #define IWX_POWER_SCHEME_CAM 1 6518 #define IWX_POWER_SCHEME_BPS 2 6519 #define IWX_POWER_SCHEME_LP 3 6520 6521 #define IWX_DEF_CMD_PAYLOAD_SIZE 320 6522 #define IWX_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwx_cmd_header)) 6523 #define IWX_CMD_FAILED_MSK 0x40 6524 6525 /** 6526 * struct iwx_device_cmd 6527 * 6528 * For allocation of the command and tx queues, this establishes the overall 6529 * size of the largest command we send to uCode, except for commands that 6530 * aren't fully copied and use other TFD space. 6531 */ 6532 struct iwx_device_cmd { 6533 union { 6534 struct { 6535 struct iwx_cmd_header hdr; 6536 uint8_t data[IWX_DEF_CMD_PAYLOAD_SIZE]; 6537 }; 6538 struct { 6539 struct iwx_cmd_header_wide hdr_wide; 6540 uint8_t data_wide[IWX_DEF_CMD_PAYLOAD_SIZE - 6541 sizeof(struct iwx_cmd_header_wide) + 6542 sizeof(struct iwx_cmd_header)]; 6543 }; 6544 }; 6545 } __packed; 6546 6547 struct iwx_rx_packet { 6548 /* 6549 * The first 4 bytes of the RX frame header contain both the RX frame 6550 * size and some flags. 6551 * Bit fields: 6552 * 31: flag flush RB request 6553 * 30: flag ignore TC (terminal counter) request 6554 * 29: flag fast IRQ request 6555 * 28-26: Reserved 6556 * 25: Offload enabled 6557 * 24: RPF enabled 6558 * 23: RSS enabled 6559 * 22: Checksum enabled 6560 * 21-16: RX queue 6561 * 15-14: Reserved 6562 * 13-00: RX frame size 6563 */ 6564 uint32_t len_n_flags; 6565 struct iwx_cmd_header hdr; 6566 uint8_t data[]; 6567 } __packed; 6568 6569 #define IWX_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff 6570 #define IWX_FH_RSCSR_FRAME_INVALID 0x55550000 6571 #define IWX_FH_RSCSR_FRAME_ALIGN 0x40 6572 #define IWX_FH_RSCSR_RPA_EN (1 << 25) 6573 #define IWX_FH_RSCSR_RADA_EN (1 << 26) 6574 #define IWX_FH_RSCSR_RXQ_POS 16 6575 #define IWX_FH_RSCSR_RXQ_MASK 0x3F0000 6576 6577 static uint32_t 6578 iwx_rx_packet_len(const struct iwx_rx_packet *pkt) 6579 { 6580 6581 return le32toh(pkt->len_n_flags) & IWX_FH_RSCSR_FRAME_SIZE_MSK; 6582 } 6583 6584 static uint32_t 6585 iwx_rx_packet_payload_len(const struct iwx_rx_packet *pkt) 6586 { 6587 6588 return iwx_rx_packet_len(pkt) - sizeof(pkt->hdr); 6589 } 6590 6591 6592 #define IWX_MIN_DBM -100 6593 #define IWX_MAX_DBM -33 /* realistic guess */ 6594 6595 #define IWX_READ(sc, reg) \ 6596 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 6597 6598 #define IWX_WRITE(sc, reg, val) \ 6599 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6600 6601 #define IWX_WRITE_1(sc, reg, val) \ 6602 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 6603 6604 #define IWX_SETBITS(sc, reg, mask) \ 6605 IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask)) 6606 6607 #define IWX_CLRBITS(sc, reg, mask) \ 6608 IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask)) 6609 6610 #define IWX_BARRIER_WRITE(sc) \ 6611 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6612 BUS_SPACE_BARRIER_WRITE) 6613 6614 #define IWX_BARRIER_READ_WRITE(sc) \ 6615 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \ 6616 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 6617