1 /* $OpenBSD: if_ix.h,v 1.10 2010/03/22 17:09:27 jsg Exp $ */ 2 3 /****************************************************************************** 4 5 Copyright (c) 2001-2008, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe.h,v 1.4 2008/05/16 18:46:30 jfv Exp $*/ 36 37 #ifndef _IX_H_ 38 #define _IX_H_ 39 40 #include <dev/pci/ixgbe.h> 41 42 #if 0 43 #include "tcp_lro.h" 44 #endif 45 46 /* Tunables */ 47 48 /* 49 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 50 * number of transmit descriptors allocated by the driver. Increasing this 51 * value allows the driver to queue more transmits. Each descriptor is 16 52 * bytes. Performance tests have show the 2K value to be optimal for top 53 * performance. 54 */ 55 #define DEFAULT_TXD 256 56 #define PERFORM_TXD 2048 57 #define MAX_TXD 4096 58 #define MIN_TXD 64 59 60 /* 61 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 62 * number of receive descriptors allocated for each RX queue. Increasing this 63 * value allows the driver to buffer more incoming packets. Each descriptor 64 * is 16 bytes. A receive buffer is also allocated for each descriptor. 65 * 66 * Note: with 8 rings and a dual port card, it is possible to bump up 67 * against the system mbuf pool limit, you can tune nmbclusters 68 * to adjust for this. 69 */ 70 #define DEFAULT_RXD 256 71 #define PERFORM_RXD 2048 72 #define MAX_RXD 4096 73 #define MIN_RXD 64 74 75 /* Alignment for rings */ 76 #define DBA_ALIGN 128 77 78 /* 79 * This parameter controls the maximum no of times the driver will loop in 80 * the isr. Minimum Value = 1 81 */ 82 #define MAX_INTR 10 83 84 /* 85 * This parameter controls the duration of transmit watchdog timer. 86 */ 87 #define IXGBE_TX_TIMEOUT 5 /* set to 5 seconds */ 88 89 /* 90 * This parameters control when the driver calls the routine to reclaim 91 * transmit descriptors. 92 */ 93 #define IXGBE_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) 94 #define IXGBE_TX_OP_THRESHOLD (sc->num_tx_desc / 32) 95 96 #define IXGBE_MAX_FRAME_SIZE 0x3F00 97 98 /* Flow control constants */ 99 #define IXGBE_FC_PAUSE 0x680 100 #define IXGBE_FC_HI 0x20000 101 #define IXGBE_FC_LO 0x10000 102 103 /* Defines for printing debug information */ 104 #define DEBUG_INIT 0 105 #define DEBUG_IOCTL 0 106 #define DEBUG_HW 0 107 108 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 109 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 110 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 111 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 112 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 113 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 114 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 115 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 116 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 117 118 #define MAX_NUM_MULTICAST_ADDRESSES 128 119 #define IXGBE_82598_SCATTER 100 120 #define IXGBE_82599_SCATTER 32 121 #define IXGBE_MSIX_BAR 3 122 #if 0 123 #define IXGBE_TSO_SIZE 65535 124 #else 125 #define IXGBE_TSO_SIZE IXGBE_MAX_FRAME_SIZE 126 #endif 127 #define IXGBE_TX_BUFFER_SIZE ((uint32_t) 1514) 128 #define IXGBE_RX_HDR_SIZE ((uint32_t) 256) 129 #define CSUM_OFFLOAD 7 /* Bits in csum flags */ 130 131 /* The number of MSIX messages the 82598 supports */ 132 #define IXGBE_MSGS 18 133 134 /* For 6.X code compatibility */ 135 #if __FreeBSD_version < 700000 136 #define ETHER_BPF_MTAP BPF_MTAP 137 #define CSUM_TSO 0 138 #define IFCAP_TSO4 0 139 #define FILTER_STRAY 140 #define FILTER_HANDLED 141 #endif 142 143 /* 144 * Interrupt Moderation parameters 145 * for now we hardcode, later 146 * it would be nice to do dynamic 147 */ 148 #define MAX_IRQ_SEC 8000 149 #define DEFAULT_ITR 1000000000/(MAX_IRQ_SEC * 256) 150 #define LINK_ITR 1000000000/(1950 * 256) 151 152 /* Used for auto RX queue configuration */ 153 extern int mp_ncpus; 154 155 struct ixgbe_tx_buf { 156 struct mbuf *m_head; 157 bus_dmamap_t map; 158 }; 159 160 struct ixgbe_rx_buf { 161 struct mbuf *m_head; 162 bus_dmamap_t map; 163 }; 164 165 /* 166 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 167 */ 168 struct ixgbe_dma_alloc { 169 caddr_t dma_vaddr; 170 bus_dma_tag_t dma_tag; 171 bus_dmamap_t dma_map; 172 bus_dma_segment_t dma_seg; 173 bus_size_t dma_size; 174 int dma_nseg; 175 }; 176 177 /* 178 * The transmit ring, one per tx queue 179 */ 180 struct tx_ring { 181 struct ix_softc *sc; 182 struct mutex tx_mtx; 183 uint32_t me; 184 uint32_t msix; 185 uint32_t eims; 186 uint32_t watchdog_timer; 187 union ixgbe_adv_tx_desc *tx_base; 188 uint32_t *tx_hwb; 189 struct ixgbe_dma_alloc txdma; 190 struct ixgbe_dma_alloc txwbdma; 191 uint32_t next_avail_tx_desc; 192 uint32_t next_tx_to_clean; 193 struct ixgbe_tx_buf *tx_buffers; 194 volatile uint16_t tx_avail; 195 uint32_t txd_cmd; 196 bus_dma_tag_t txtag; 197 /* Soft Stats */ 198 uint32_t no_tx_desc_avail; 199 uint32_t no_tx_desc_late; 200 uint64_t tx_irq; 201 uint64_t tx_packets; 202 }; 203 204 205 /* 206 * The Receive ring, one per rx queue 207 */ 208 struct rx_ring { 209 struct ix_softc *sc; 210 struct mutex rx_mtx; 211 uint32_t me; 212 uint32_t msix; 213 uint32_t eims; 214 uint32_t payload; 215 union ixgbe_adv_rx_desc *rx_base; 216 struct ixgbe_dma_alloc rxdma; 217 #if 0 218 struct lro_ctrl lro; 219 #endif 220 unsigned int last_rx_desc_filled; 221 unsigned int next_to_check; 222 int rx_ndescs; 223 struct ixgbe_rx_buf *rx_buffers; 224 bus_dma_tag_t rxtag; 225 struct mbuf *fmp; 226 struct mbuf *lmp; 227 /* Soft stats */ 228 uint64_t rx_irq; 229 uint64_t packet_count; 230 uint64_t byte_count; 231 }; 232 233 /* Our adapter structure */ 234 struct ix_softc { 235 struct device dev; 236 struct arpcom arpcom; 237 238 struct ixgbe_hw hw; 239 struct ixgbe_osdep osdep; 240 void *powerhook; 241 242 struct resource *pci_mem; 243 struct resource *msix_mem; 244 245 /* 246 * Interrupt resources: 247 * Oplin has 20 MSIX messages 248 * so allocate that for now. 249 */ 250 void *tag[IXGBE_MSGS]; 251 struct resource *res[IXGBE_MSGS]; 252 int rid[IXGBE_MSGS]; 253 uint32_t eims_mask; 254 255 struct ifmedia media; 256 struct timeout timer; 257 int msix; 258 int if_flags; 259 260 struct mutex core_mtx; 261 262 /* Legacy Fast Intr handling */ 263 int sfp_probe; 264 workq_fn link_task; 265 266 /* Info about the board itself */ 267 uint32_t part_num; 268 int link_active; 269 uint16_t max_frame_size; 270 uint32_t link_speed; 271 uint32_t tx_int_delay; 272 uint32_t tx_abs_int_delay; 273 uint32_t rx_int_delay; 274 uint32_t rx_abs_int_delay; 275 276 /* Indicates the cluster size to use */ 277 int bigbufs; 278 279 /* 280 * Transmit rings: 281 * Allocated at run time, an array of rings. 282 */ 283 struct tx_ring *tx_rings; 284 int num_tx_desc; 285 int num_tx_queues; 286 287 /* 288 * Receive rings: 289 * Allocated at run time, an array of rings. 290 */ 291 struct rx_ring *rx_rings; 292 int num_rx_desc; 293 int num_rx_queues; 294 uint32_t rx_process_limit; 295 uint optics; 296 297 /* Misc stats maintained by the driver */ 298 unsigned long dropped_pkts; 299 unsigned long mbuf_alloc_failed; 300 unsigned long mbuf_cluster_failed; 301 unsigned long no_tx_map_avail; 302 unsigned long no_tx_dma_setup; 303 unsigned long watchdog_events; 304 unsigned long tso_tx; 305 unsigned long linkvec; 306 unsigned long link_irq; 307 308 struct ixgbe_hw_stats stats; 309 }; 310 311 #endif /* _IX_H_ */ 312