1 /************************************************************************** 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /* $OpenBSD: if_ixgb.h,v 1.1 2005/11/14 23:25:43 brad Exp $ */ 35 36 #ifndef _IXGB_H_DEFINED_ 37 #define _IXGB_H_DEFINED_ 38 39 #include "bpfilter.h" 40 #include "vlan.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/device.h> 49 #include <sys/socket.h> 50 51 #include <net/if.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 55 #ifdef INET 56 #include <netinet/in.h> 57 #include <netinet/in_systm.h> 58 #include <netinet/in_var.h> 59 #include <netinet/ip.h> 60 #include <netinet/if_ether.h> 61 #include <netinet/tcp.h> 62 #include <netinet/udp.h> 63 #endif 64 65 #if NVLAN > 0 66 #include <net/if_types.h> 67 #include <net/if_vlan_var.h> 68 #endif 69 70 #if NBPFILTER > 0 71 #include <net/bpf.h> 72 #endif 73 74 #include <uvm/uvm_extern.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcidevs.h> 79 80 #include <dev/pci/ixgb_hw.h> 81 #include <dev/pci/ixgb_ee.h> 82 #include <dev/pci/ixgb_ids.h> 83 84 /* Tunables */ 85 86 /* 87 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 88 * number of transmit descriptors allocated by the driver. Increasing this 89 * value allows the driver to queue more transmits. Each descriptor is 16 90 * bytes. 91 */ 92 #define IXGB_MAX_TXD 256 93 94 /* 95 * RxDescriptors Valid Range: 64-512 Default Value: 512 This value is the 96 * number of receive descriptors allocated by the driver. Increasing this 97 * value allows the driver to buffer more incoming packets. Each descriptor 98 * is 16 bytes. A receive buffer is also allocated for each descriptor. The 99 * maximum MTU size is 16110. 100 * Note: Maximum number of receive descriptors is limited to 512 to avoid a 101 * hardware descriptor cache issue under heavy receive traffic. 102 */ 103 #define IXGB_MAX_RXD 512 104 105 /* 106 * TxIntDelay Valid Range: 0-65535 (0=off) Default Value: 32 This value 107 * delays the generation of transmit interrupts in units of 1.024 108 * microseconds. Transmit interrupt reduction can improve CPU efficiency if 109 * properly tuned for specific network traffic. If the system is reporting 110 * dropped transmits, this value may be set too high causing the driver to 111 * run out of available transmit descriptors. 112 */ 113 #define TIDV 32 114 115 /* 116 * RxIntDelay Valid Range: 0-65535 (0=off) Default Value: 72 This value 117 * delays the generation of receive interrupts in units of 1.024 118 * microseconds. Receive interrupt reduction can improve CPU efficiency if 119 * properly tuned for specific network traffic. Increasing this value adds 120 * extra latency to frame reception and can end up decreasing the throughput 121 * of TCP traffic. If the system is reporting dropped receives, this value 122 * may be set too high, causing the driver to run out of available receive 123 * descriptors. 124 * 125 */ 126 #define RDTR 72 127 128 /* 129 * This parameter controls the maximum no of times the driver will loop in 130 * the isr. Minimum Value = 1 131 */ 132 #define IXGB_MAX_INTR 3 133 134 /* 135 * This parameter controls the duration of transmit watchdog timer. 136 */ 137 #define IXGB_TX_TIMEOUT 5 /* set to 5 seconds */ 138 139 /* 140 * This parameter controls when the driver calls the routine to reclaim 141 * transmit descriptors. 142 */ 143 #define IXGB_TX_CLEANUP_THRESHOLD IXGB_MAX_TXD / 8 144 145 /* 146 * Flow Control Types. 147 * 1. ixgb_fc_none - Flow Control Disabled 148 * 2. ixgb_fc_rx_pause - Flow Control Receive Only 149 * 3. ixgb_fc_tx_pause - Flow Control Transmit Only 150 * 4. ixgb_fc_full - Flow Control Enabled 151 */ 152 #define FLOW_CONTROL_NONE ixgb_fc_none 153 #define FLOW_CONTROL_RX_PAUSE ixgb_fc_rx_pause 154 #define FLOW_CONTROL_TX_PAUSE ixgb_fc_tx_pause 155 #define FLOW_CONTROL_FULL ixgb_fc_full 156 157 /* 158 * Set the flow control type. Assign one of the above flow control types to be enabled. 159 * Default Value: FLOW_CONTROL_FULL 160 */ 161 #define FLOW_CONTROL FLOW_CONTROL_FULL 162 163 /* 164 * Receive Flow control low threshold (when we send a resume frame) (FCRTL) 165 * Valid Range: 64 - 262,136 (0x40 - 0x3FFF8, 8 byte granularity) must be 166 * less than high threshold by at least 8 bytes Default Value: 163,840 167 * (0x28000) 168 */ 169 #define FCRTL 0x28000 170 171 /* 172 * Receive Flow control high threshold (when we send a pause frame) (FCRTH) 173 * Valid Range: 1,536 - 262,136 (0x600 - 0x3FFF8, 8 byte granularity) Default 174 * Value: 196,608 (0x30000) 175 */ 176 #define FCRTH 0x30000 177 178 /* 179 * Flow control request timeout (how long to pause the link partner's tx) 180 * (PAP 15:0) Valid Range: 1 - 65535 Default Value: 256 (0x100) 181 */ 182 #define FCPAUSE 0x100 183 184 /* Tunables -- End */ 185 186 187 #define IXGB_VENDOR_ID 0x8086 188 #define IXGB_MMBA 0x0010 /* Mem base address */ 189 #define IXGB_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1)) 190 191 #define IOCTL_CMD_TYPE u_long 192 #define MAX_NUM_MULTICAST_ADDRESSES 128 193 #define PCI_ANY_ID (~0U) 194 #define ETHER_ALIGN 2 195 196 /* Defines for printing debug information */ 197 #define DEBUG_INIT 0 198 #define DEBUG_IOCTL 0 199 #define DEBUG_HW 0 200 201 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 202 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 203 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 204 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 205 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 206 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 207 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 208 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 209 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 210 211 212 /* Supported RX Buffer Sizes */ 213 #define IXGB_RXBUFFER_2048 2048 214 #define IXGB_RXBUFFER_4096 4096 215 #define IXGB_RXBUFFER_8192 8192 216 #define IXGB_RXBUFFER_16384 16384 217 218 #define IXGB_MAX_SCATTER 100 219 220 struct ixgb_buffer { 221 struct mbuf *m_head; 222 bus_dmamap_t map; /* bus_dma map for packet */ 223 }; 224 225 struct ixgb_q { 226 bus_dmamap_t map; /* bus_dma map for packet */ 227 }; 228 229 /* 230 * Bus dma allocation structure used by ixgb_dma_malloc and ixgb_dma_free. 231 */ 232 struct ixgb_dma_alloc { 233 bus_addr_t dma_paddr; 234 caddr_t dma_vaddr; 235 bus_dma_tag_t dma_tag; 236 bus_dmamap_t dma_map; 237 bus_dma_segment_t dma_seg; 238 bus_size_t dma_size; 239 int dma_nseg; 240 }; 241 242 typedef enum _XSUM_CONTEXT_T { 243 OFFLOAD_NONE, 244 OFFLOAD_TCP_IP, 245 OFFLOAD_UDP_IP 246 } XSUM_CONTEXT_T; 247 248 /* Our adapter structure */ 249 struct ixgb_softc { 250 struct device sc_dv; 251 struct arpcom interface_data; 252 struct ixgb_hw hw; 253 254 /* OpenBSD operating-system-specific structures */ 255 struct ixgb_osdep osdep; 256 struct ifmedia media; 257 int io_rid; 258 259 void *sc_intrhand; 260 struct timeout ixgb_intr_enable; 261 struct timeout timer_handle; 262 void *sc_powerhook; 263 264 /* Info about the board itself */ 265 u_int32_t part_num; 266 u_int8_t link_active; 267 u_int16_t link_speed; 268 u_int16_t link_duplex; 269 u_int32_t tx_int_delay; 270 u_int32_t tx_abs_int_delay; 271 u_int32_t rx_int_delay; 272 u_int32_t rx_abs_int_delay; 273 274 int raidc; 275 276 XSUM_CONTEXT_T active_checksum_context; 277 278 /* 279 * Transmit definitions 280 * 281 * We have an array of num_tx_desc descriptors (handled by the 282 * controller) paired with an array of tx_buffers (at 283 * tx_buffer_area). The index of the next available descriptor is 284 * next_avail_tx_desc. The number of remaining tx_desc is 285 * num_tx_desc_avail. 286 */ 287 struct ixgb_dma_alloc txdma; /* bus_dma glue for tx desc */ 288 struct ixgb_tx_desc *tx_desc_base; 289 u_int32_t next_avail_tx_desc; 290 u_int32_t oldest_used_tx_desc; 291 volatile u_int16_t num_tx_desc_avail; 292 u_int16_t num_tx_desc; 293 u_int32_t txd_cmd; 294 struct ixgb_buffer *tx_buffer_area; 295 bus_dma_tag_t txtag; /* dma tag for tx */ 296 297 /* 298 * Receive definitions 299 * 300 * we have an array of num_rx_desc rx_desc (handled by the controller), 301 * and paired with an array of rx_buffers (at rx_buffer_area). The 302 * next pair to check on receive is at offset next_rx_desc_to_check 303 */ 304 struct ixgb_dma_alloc rxdma; /* bus_dma glue for rx desc */ 305 struct ixgb_rx_desc *rx_desc_base; 306 u_int32_t next_rx_desc_to_check; 307 u_int16_t num_rx_desc; 308 u_int32_t rx_buffer_len; 309 struct ixgb_buffer *rx_buffer_area; 310 bus_dma_tag_t rxtag; /* dma tag for Rx */ 311 u_int32_t next_rx_desc_to_use; 312 313 /* Jumbo frame */ 314 struct mbuf *fmp; 315 struct mbuf *lmp; 316 317 /* Misc stats maintained by the driver */ 318 unsigned long dropped_pkts; 319 unsigned long mbuf_alloc_failed; 320 unsigned long mbuf_cluster_failed; 321 unsigned long no_tx_desc_avail1; 322 unsigned long no_tx_desc_avail2; 323 unsigned long no_tx_map_avail; 324 unsigned long no_tx_dma_setup; 325 unsigned long watchdog_events; 326 327 boolean_t in_detach; 328 329 struct ixgb_hw_stats stats; 330 }; 331 332 #endif /* _IXGB_H_DEFINED_ */ 333