1 /* $OpenBSD: if_ixl.c,v 1.72 2021/01/25 11:11:22 dlg Exp $ */ 2 3 /* 4 * Copyright (c) 2013-2015, Intel Corporation 5 * All rights reserved. 6 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Intel Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 2016,2017 David Gwynne <dlg@openbsd.org> 36 * 37 * Permission to use, copy, modify, and distribute this software for any 38 * purpose with or without fee is hereby granted, provided that the above 39 * copyright notice and this permission notice appear in all copies. 40 * 41 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 42 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 43 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 44 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 45 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 46 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 47 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 48 */ 49 50 #include "bpfilter.h" 51 #include "kstat.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/proc.h> 56 #include <sys/sockio.h> 57 #include <sys/mbuf.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/device.h> 61 #include <sys/pool.h> 62 #include <sys/queue.h> 63 #include <sys/timeout.h> 64 #include <sys/task.h> 65 #include <sys/syslog.h> 66 #include <sys/intrmap.h> 67 68 #include <machine/bus.h> 69 #include <machine/intr.h> 70 71 #include <net/if.h> 72 #include <net/if_dl.h> 73 #include <net/if_media.h> 74 #include <net/toeplitz.h> 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #endif 79 80 #if NKSTAT > 0 81 #include <sys/kstat.h> 82 #endif 83 84 #include <netinet/in.h> 85 #include <netinet/if_ether.h> 86 87 #include <dev/pci/pcireg.h> 88 #include <dev/pci/pcivar.h> 89 #include <dev/pci/pcidevs.h> 90 91 #ifdef __sparc64__ 92 #include <dev/ofw/openfirm.h> 93 #endif 94 95 #ifndef CACHE_LINE_SIZE 96 #define CACHE_LINE_SIZE 64 97 #endif 98 99 #define IXL_MAX_VECTORS 8 /* XXX this is pretty arbitrary */ 100 101 #define I40E_MASK(mask, shift) ((mask) << (shift)) 102 #define I40E_PF_RESET_WAIT_COUNT 200 103 #define I40E_AQ_LARGE_BUF 512 104 105 /* bitfields for Tx queue mapping in QTX_CTL */ 106 #define I40E_QTX_CTL_VF_QUEUE 0x0 107 #define I40E_QTX_CTL_VM_QUEUE 0x1 108 #define I40E_QTX_CTL_PF_QUEUE 0x2 109 110 #define I40E_QUEUE_TYPE_EOL 0x7ff 111 #define I40E_INTR_NOTX_QUEUE 0 112 113 #define I40E_QUEUE_TYPE_RX 0x0 114 #define I40E_QUEUE_TYPE_TX 0x1 115 #define I40E_QUEUE_TYPE_PE_CEQ 0x2 116 #define I40E_QUEUE_TYPE_UNKNOWN 0x3 117 118 #define I40E_ITR_INDEX_RX 0x0 119 #define I40E_ITR_INDEX_TX 0x1 120 #define I40E_ITR_INDEX_OTHER 0x2 121 #define I40E_ITR_INDEX_NONE 0x3 122 123 #include <dev/pci/if_ixlreg.h> 124 125 #define I40E_INTR_NOTX_QUEUE 0 126 #define I40E_INTR_NOTX_INTR 0 127 #define I40E_INTR_NOTX_RX_QUEUE 0 128 #define I40E_INTR_NOTX_TX_QUEUE 1 129 #define I40E_INTR_NOTX_RX_MASK I40E_PFINT_ICR0_QUEUE_0_MASK 130 #define I40E_INTR_NOTX_TX_MASK I40E_PFINT_ICR0_QUEUE_1_MASK 131 132 struct ixl_aq_desc { 133 uint16_t iaq_flags; 134 #define IXL_AQ_DD (1U << 0) 135 #define IXL_AQ_CMP (1U << 1) 136 #define IXL_AQ_ERR (1U << 2) 137 #define IXL_AQ_VFE (1U << 3) 138 #define IXL_AQ_LB (1U << 9) 139 #define IXL_AQ_RD (1U << 10) 140 #define IXL_AQ_VFC (1U << 11) 141 #define IXL_AQ_BUF (1U << 12) 142 #define IXL_AQ_SI (1U << 13) 143 #define IXL_AQ_EI (1U << 14) 144 #define IXL_AQ_FE (1U << 15) 145 146 #define IXL_AQ_FLAGS_FMT "\020" "\020FE" "\017EI" "\016SI" "\015BUF" \ 147 "\014VFC" "\013DB" "\012LB" "\004VFE" \ 148 "\003ERR" "\002CMP" "\001DD" 149 150 uint16_t iaq_opcode; 151 152 uint16_t iaq_datalen; 153 uint16_t iaq_retval; 154 155 uint64_t iaq_cookie; 156 157 uint32_t iaq_param[4]; 158 /* iaq_data_hi iaq_param[2] */ 159 /* iaq_data_lo iaq_param[3] */ 160 } __packed __aligned(8); 161 162 /* aq commands */ 163 #define IXL_AQ_OP_GET_VERSION 0x0001 164 #define IXL_AQ_OP_DRIVER_VERSION 0x0002 165 #define IXL_AQ_OP_QUEUE_SHUTDOWN 0x0003 166 #define IXL_AQ_OP_SET_PF_CONTEXT 0x0004 167 #define IXL_AQ_OP_GET_AQ_ERR_REASON 0x0005 168 #define IXL_AQ_OP_REQUEST_RESOURCE 0x0008 169 #define IXL_AQ_OP_RELEASE_RESOURCE 0x0009 170 #define IXL_AQ_OP_LIST_FUNC_CAP 0x000a 171 #define IXL_AQ_OP_LIST_DEV_CAP 0x000b 172 #define IXL_AQ_OP_MAC_ADDRESS_READ 0x0107 173 #define IXL_AQ_OP_CLEAR_PXE_MODE 0x0110 174 #define IXL_AQ_OP_SWITCH_GET_CONFIG 0x0200 175 #define IXL_AQ_OP_RX_CTL_READ 0x0206 176 #define IXL_AQ_OP_RX_CTL_WRITE 0x0207 177 #define IXL_AQ_OP_ADD_VSI 0x0210 178 #define IXL_AQ_OP_UPD_VSI_PARAMS 0x0211 179 #define IXL_AQ_OP_GET_VSI_PARAMS 0x0212 180 #define IXL_AQ_OP_ADD_VEB 0x0230 181 #define IXL_AQ_OP_UPD_VEB_PARAMS 0x0231 182 #define IXL_AQ_OP_GET_VEB_PARAMS 0x0232 183 #define IXL_AQ_OP_ADD_MACVLAN 0x0250 184 #define IXL_AQ_OP_REMOVE_MACVLAN 0x0251 185 #define IXL_AQ_OP_SET_VSI_PROMISC 0x0254 186 #define IXL_AQ_OP_PHY_GET_ABILITIES 0x0600 187 #define IXL_AQ_OP_PHY_SET_CONFIG 0x0601 188 #define IXL_AQ_OP_PHY_SET_MAC_CONFIG 0x0603 189 #define IXL_AQ_OP_PHY_RESTART_AN 0x0605 190 #define IXL_AQ_OP_PHY_LINK_STATUS 0x0607 191 #define IXL_AQ_OP_PHY_SET_EVENT_MASK 0x0613 192 #define IXL_AQ_OP_PHY_SET_REGISTER 0x0628 193 #define IXL_AQ_OP_PHY_GET_REGISTER 0x0629 194 #define IXL_AQ_OP_LLDP_GET_MIB 0x0a00 195 #define IXL_AQ_OP_LLDP_MIB_CHG_EV 0x0a01 196 #define IXL_AQ_OP_LLDP_ADD_TLV 0x0a02 197 #define IXL_AQ_OP_LLDP_UPD_TLV 0x0a03 198 #define IXL_AQ_OP_LLDP_DEL_TLV 0x0a04 199 #define IXL_AQ_OP_LLDP_STOP_AGENT 0x0a05 200 #define IXL_AQ_OP_LLDP_START_AGENT 0x0a06 201 #define IXL_AQ_OP_LLDP_GET_CEE_DCBX 0x0a07 202 #define IXL_AQ_OP_LLDP_SPECIFIC_AGENT 0x0a09 203 #define IXL_AQ_OP_SET_RSS_KEY 0x0b02 /* 722 only */ 204 #define IXL_AQ_OP_SET_RSS_LUT 0x0b03 /* 722 only */ 205 #define IXL_AQ_OP_GET_RSS_KEY 0x0b04 /* 722 only */ 206 #define IXL_AQ_OP_GET_RSS_LUT 0x0b05 /* 722 only */ 207 208 struct ixl_aq_mac_addresses { 209 uint8_t pf_lan[ETHER_ADDR_LEN]; 210 uint8_t pf_san[ETHER_ADDR_LEN]; 211 uint8_t port[ETHER_ADDR_LEN]; 212 uint8_t pf_wol[ETHER_ADDR_LEN]; 213 } __packed; 214 215 #define IXL_AQ_MAC_PF_LAN_VALID (1U << 4) 216 #define IXL_AQ_MAC_PF_SAN_VALID (1U << 5) 217 #define IXL_AQ_MAC_PORT_VALID (1U << 6) 218 #define IXL_AQ_MAC_PF_WOL_VALID (1U << 7) 219 220 struct ixl_aq_capability { 221 uint16_t cap_id; 222 #define IXL_AQ_CAP_SWITCH_MODE 0x0001 223 #define IXL_AQ_CAP_MNG_MODE 0x0002 224 #define IXL_AQ_CAP_NPAR_ACTIVE 0x0003 225 #define IXL_AQ_CAP_OS2BMC_CAP 0x0004 226 #define IXL_AQ_CAP_FUNCTIONS_VALID 0x0005 227 #define IXL_AQ_CAP_ALTERNATE_RAM 0x0006 228 #define IXL_AQ_CAP_WOL_AND_PROXY 0x0008 229 #define IXL_AQ_CAP_SRIOV 0x0012 230 #define IXL_AQ_CAP_VF 0x0013 231 #define IXL_AQ_CAP_VMDQ 0x0014 232 #define IXL_AQ_CAP_8021QBG 0x0015 233 #define IXL_AQ_CAP_8021QBR 0x0016 234 #define IXL_AQ_CAP_VSI 0x0017 235 #define IXL_AQ_CAP_DCB 0x0018 236 #define IXL_AQ_CAP_FCOE 0x0021 237 #define IXL_AQ_CAP_ISCSI 0x0022 238 #define IXL_AQ_CAP_RSS 0x0040 239 #define IXL_AQ_CAP_RXQ 0x0041 240 #define IXL_AQ_CAP_TXQ 0x0042 241 #define IXL_AQ_CAP_MSIX 0x0043 242 #define IXL_AQ_CAP_VF_MSIX 0x0044 243 #define IXL_AQ_CAP_FLOW_DIRECTOR 0x0045 244 #define IXL_AQ_CAP_1588 0x0046 245 #define IXL_AQ_CAP_IWARP 0x0051 246 #define IXL_AQ_CAP_LED 0x0061 247 #define IXL_AQ_CAP_SDP 0x0062 248 #define IXL_AQ_CAP_MDIO 0x0063 249 #define IXL_AQ_CAP_WSR_PROT 0x0064 250 #define IXL_AQ_CAP_NVM_MGMT 0x0080 251 #define IXL_AQ_CAP_FLEX10 0x00F1 252 #define IXL_AQ_CAP_CEM 0x00F2 253 uint8_t major_rev; 254 uint8_t minor_rev; 255 uint32_t number; 256 uint32_t logical_id; 257 uint32_t phys_id; 258 uint8_t _reserved[16]; 259 } __packed __aligned(4); 260 261 #define IXL_LLDP_SHUTDOWN 0x1 262 263 struct ixl_aq_switch_config { 264 uint16_t num_reported; 265 uint16_t num_total; 266 uint8_t _reserved[12]; 267 } __packed __aligned(4); 268 269 struct ixl_aq_switch_config_element { 270 uint8_t type; 271 #define IXL_AQ_SW_ELEM_TYPE_MAC 1 272 #define IXL_AQ_SW_ELEM_TYPE_PF 2 273 #define IXL_AQ_SW_ELEM_TYPE_VF 3 274 #define IXL_AQ_SW_ELEM_TYPE_EMP 4 275 #define IXL_AQ_SW_ELEM_TYPE_BMC 5 276 #define IXL_AQ_SW_ELEM_TYPE_PV 16 277 #define IXL_AQ_SW_ELEM_TYPE_VEB 17 278 #define IXL_AQ_SW_ELEM_TYPE_PA 18 279 #define IXL_AQ_SW_ELEM_TYPE_VSI 19 280 uint8_t revision; 281 #define IXL_AQ_SW_ELEM_REV_1 1 282 uint16_t seid; 283 284 uint16_t uplink_seid; 285 uint16_t downlink_seid; 286 287 uint8_t _reserved[3]; 288 uint8_t connection_type; 289 #define IXL_AQ_CONN_TYPE_REGULAR 0x1 290 #define IXL_AQ_CONN_TYPE_DEFAULT 0x2 291 #define IXL_AQ_CONN_TYPE_CASCADED 0x3 292 293 uint16_t scheduler_id; 294 uint16_t element_info; 295 } __packed __aligned(4); 296 297 #define IXL_PHY_TYPE_SGMII 0x00 298 #define IXL_PHY_TYPE_1000BASE_KX 0x01 299 #define IXL_PHY_TYPE_10GBASE_KX4 0x02 300 #define IXL_PHY_TYPE_10GBASE_KR 0x03 301 #define IXL_PHY_TYPE_40GBASE_KR4 0x04 302 #define IXL_PHY_TYPE_XAUI 0x05 303 #define IXL_PHY_TYPE_XFI 0x06 304 #define IXL_PHY_TYPE_SFI 0x07 305 #define IXL_PHY_TYPE_XLAUI 0x08 306 #define IXL_PHY_TYPE_XLPPI 0x09 307 #define IXL_PHY_TYPE_40GBASE_CR4_CU 0x0a 308 #define IXL_PHY_TYPE_10GBASE_CR1_CU 0x0b 309 #define IXL_PHY_TYPE_10GBASE_AOC 0x0c 310 #define IXL_PHY_TYPE_40GBASE_AOC 0x0d 311 #define IXL_PHY_TYPE_100BASE_TX 0x11 312 #define IXL_PHY_TYPE_1000BASE_T 0x12 313 #define IXL_PHY_TYPE_10GBASE_T 0x13 314 #define IXL_PHY_TYPE_10GBASE_SR 0x14 315 #define IXL_PHY_TYPE_10GBASE_LR 0x15 316 #define IXL_PHY_TYPE_10GBASE_SFPP_CU 0x16 317 #define IXL_PHY_TYPE_10GBASE_CR1 0x17 318 #define IXL_PHY_TYPE_40GBASE_CR4 0x18 319 #define IXL_PHY_TYPE_40GBASE_SR4 0x19 320 #define IXL_PHY_TYPE_40GBASE_LR4 0x1a 321 #define IXL_PHY_TYPE_1000BASE_SX 0x1b 322 #define IXL_PHY_TYPE_1000BASE_LX 0x1c 323 #define IXL_PHY_TYPE_1000BASE_T_OPTICAL 0x1d 324 #define IXL_PHY_TYPE_20GBASE_KR2 0x1e 325 326 #define IXL_PHY_TYPE_25GBASE_KR 0x1f 327 #define IXL_PHY_TYPE_25GBASE_CR 0x20 328 #define IXL_PHY_TYPE_25GBASE_SR 0x21 329 #define IXL_PHY_TYPE_25GBASE_LR 0x22 330 #define IXL_PHY_TYPE_25GBASE_AOC 0x23 331 #define IXL_PHY_TYPE_25GBASE_ACC 0x24 332 333 struct ixl_aq_module_desc { 334 uint8_t oui[3]; 335 uint8_t _reserved1; 336 uint8_t part_number[16]; 337 uint8_t revision[4]; 338 uint8_t _reserved2[8]; 339 } __packed __aligned(4); 340 341 struct ixl_aq_phy_abilities { 342 uint32_t phy_type; 343 344 uint8_t link_speed; 345 #define IXL_AQ_PHY_LINK_SPEED_100MB (1 << 1) 346 #define IXL_AQ_PHY_LINK_SPEED_1000MB (1 << 2) 347 #define IXL_AQ_PHY_LINK_SPEED_10GB (1 << 3) 348 #define IXL_AQ_PHY_LINK_SPEED_40GB (1 << 4) 349 #define IXL_AQ_PHY_LINK_SPEED_20GB (1 << 5) 350 #define IXL_AQ_PHY_LINK_SPEED_25GB (1 << 6) 351 uint8_t abilities; 352 uint16_t eee_capability; 353 354 uint32_t eeer_val; 355 356 uint8_t d3_lpan; 357 uint8_t phy_type_ext; 358 #define IXL_AQ_PHY_TYPE_EXT_25G_KR 0x01 359 #define IXL_AQ_PHY_TYPE_EXT_25G_CR 0x02 360 #define IXL_AQ_PHY_TYPE_EXT_25G_SR 0x04 361 #define IXL_AQ_PHY_TYPE_EXT_25G_LR 0x08 362 uint8_t fec_cfg_curr_mod_ext_info; 363 #define IXL_AQ_ENABLE_FEC_KR 0x01 364 #define IXL_AQ_ENABLE_FEC_RS 0x02 365 #define IXL_AQ_REQUEST_FEC_KR 0x04 366 #define IXL_AQ_REQUEST_FEC_RS 0x08 367 #define IXL_AQ_ENABLE_FEC_AUTO 0x10 368 #define IXL_AQ_MODULE_TYPE_EXT_MASK 0xe0 369 #define IXL_AQ_MODULE_TYPE_EXT_SHIFT 5 370 uint8_t ext_comp_code; 371 372 uint8_t phy_id[4]; 373 374 uint8_t module_type[3]; 375 #define IXL_SFF8024_ID_SFP 0x03 376 #define IXL_SFF8024_ID_QSFP 0x0c 377 #define IXL_SFF8024_ID_QSFP_PLUS 0x0d 378 #define IXL_SFF8024_ID_QSFP28 0x11 379 uint8_t qualified_module_count; 380 #define IXL_AQ_PHY_MAX_QMS 16 381 struct ixl_aq_module_desc 382 qualified_module[IXL_AQ_PHY_MAX_QMS]; 383 } __packed __aligned(4); 384 385 struct ixl_aq_link_param { 386 uint8_t notify; 387 #define IXL_AQ_LINK_NOTIFY 0x03 388 uint8_t _reserved1; 389 uint8_t phy; 390 uint8_t speed; 391 uint8_t status; 392 uint8_t _reserved2[11]; 393 } __packed __aligned(4); 394 395 struct ixl_aq_vsi_param { 396 uint16_t uplink_seid; 397 uint8_t connect_type; 398 #define IXL_AQ_VSI_CONN_TYPE_NORMAL (0x1) 399 #define IXL_AQ_VSI_CONN_TYPE_DEFAULT (0x2) 400 #define IXL_AQ_VSI_CONN_TYPE_CASCADED (0x3) 401 uint8_t _reserved1; 402 403 uint8_t vf_id; 404 uint8_t _reserved2; 405 uint16_t vsi_flags; 406 #define IXL_AQ_VSI_TYPE_SHIFT 0x0 407 #define IXL_AQ_VSI_TYPE_MASK (0x3 << IXL_AQ_VSI_TYPE_SHIFT) 408 #define IXL_AQ_VSI_TYPE_VF 0x0 409 #define IXL_AQ_VSI_TYPE_VMDQ2 0x1 410 #define IXL_AQ_VSI_TYPE_PF 0x2 411 #define IXL_AQ_VSI_TYPE_EMP_MNG 0x3 412 #define IXL_AQ_VSI_FLAG_CASCADED_PV 0x4 413 414 uint32_t addr_hi; 415 uint32_t addr_lo; 416 } __packed __aligned(16); 417 418 struct ixl_aq_add_macvlan { 419 uint16_t num_addrs; 420 uint16_t seid0; 421 uint16_t seid1; 422 uint16_t seid2; 423 uint32_t addr_hi; 424 uint32_t addr_lo; 425 } __packed __aligned(16); 426 427 struct ixl_aq_add_macvlan_elem { 428 uint8_t macaddr[6]; 429 uint16_t vlan; 430 uint16_t flags; 431 #define IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH 0x0001 432 #define IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN 0x0004 433 uint16_t queue; 434 uint32_t _reserved; 435 } __packed __aligned(16); 436 437 struct ixl_aq_remove_macvlan { 438 uint16_t num_addrs; 439 uint16_t seid0; 440 uint16_t seid1; 441 uint16_t seid2; 442 uint32_t addr_hi; 443 uint32_t addr_lo; 444 } __packed __aligned(16); 445 446 struct ixl_aq_remove_macvlan_elem { 447 uint8_t macaddr[6]; 448 uint16_t vlan; 449 uint8_t flags; 450 #define IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH 0x0001 451 #define IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN 0x0008 452 uint8_t _reserved[7]; 453 } __packed __aligned(16); 454 455 struct ixl_aq_vsi_reply { 456 uint16_t seid; 457 uint16_t vsi_number; 458 459 uint16_t vsis_used; 460 uint16_t vsis_free; 461 462 uint32_t addr_hi; 463 uint32_t addr_lo; 464 } __packed __aligned(16); 465 466 struct ixl_aq_vsi_data { 467 /* first 96 byte are written by SW */ 468 uint16_t valid_sections; 469 #define IXL_AQ_VSI_VALID_SWITCH (1 << 0) 470 #define IXL_AQ_VSI_VALID_SECURITY (1 << 1) 471 #define IXL_AQ_VSI_VALID_VLAN (1 << 2) 472 #define IXL_AQ_VSI_VALID_CAS_PV (1 << 3) 473 #define IXL_AQ_VSI_VALID_INGRESS_UP (1 << 4) 474 #define IXL_AQ_VSI_VALID_EGRESS_UP (1 << 5) 475 #define IXL_AQ_VSI_VALID_QUEUE_MAP (1 << 6) 476 #define IXL_AQ_VSI_VALID_QUEUE_OPT (1 << 7) 477 #define IXL_AQ_VSI_VALID_OUTER_UP (1 << 8) 478 #define IXL_AQ_VSI_VALID_SCHED (1 << 9) 479 /* switch section */ 480 uint16_t switch_id; 481 #define IXL_AQ_VSI_SWITCH_ID_SHIFT 0 482 #define IXL_AQ_VSI_SWITCH_ID_MASK (0xfff << IXL_AQ_VSI_SWITCH_ID_SHIFT) 483 #define IXL_AQ_VSI_SWITCH_NOT_STAG (1 << 12) 484 #define IXL_AQ_VSI_SWITCH_LOCAL_LB (1 << 14) 485 486 uint8_t _reserved1[2]; 487 /* security section */ 488 uint8_t sec_flags; 489 #define IXL_AQ_VSI_SEC_ALLOW_DEST_OVRD (1 << 0) 490 #define IXL_AQ_VSI_SEC_ENABLE_VLAN_CHK (1 << 1) 491 #define IXL_AQ_VSI_SEC_ENABLE_MAC_CHK (1 << 2) 492 uint8_t _reserved2; 493 494 /* vlan section */ 495 uint16_t pvid; 496 uint16_t fcoe_pvid; 497 498 uint8_t port_vlan_flags; 499 #define IXL_AQ_VSI_PVLAN_MODE_SHIFT 0 500 #define IXL_AQ_VSI_PVLAN_MODE_MASK (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 501 #define IXL_AQ_VSI_PVLAN_MODE_TAGGED (0x1 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 502 #define IXL_AQ_VSI_PVLAN_MODE_UNTAGGED (0x2 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 503 #define IXL_AQ_VSI_PVLAN_MODE_ALL (0x3 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 504 #define IXL_AQ_VSI_PVLAN_INSERT_PVID (0x4 << IXL_AQ_VSI_PVLAN_MODE_SHIFT) 505 #define IXL_AQ_VSI_PVLAN_EMOD_SHIFT 0x3 506 #define IXL_AQ_VSI_PVLAN_EMOD_MASK (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 507 #define IXL_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 508 #define IXL_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 509 #define IXL_AQ_VSI_PVLAN_EMOD_STR (0x2 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 510 #define IXL_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << IXL_AQ_VSI_PVLAN_EMOD_SHIFT) 511 uint8_t _reserved3[3]; 512 513 /* ingress egress up section */ 514 uint32_t ingress_table; 515 #define IXL_AQ_VSI_UP_SHIFT(_up) ((_up) * 3) 516 #define IXL_AQ_VSI_UP_MASK(_up) (0x7 << (IXL_AQ_VSI_UP_SHIFT(_up)) 517 uint32_t egress_table; 518 519 /* cascaded pv section */ 520 uint16_t cas_pv_tag; 521 uint8_t cas_pv_flags; 522 #define IXL_AQ_VSI_CAS_PV_TAGX_SHIFT 0 523 #define IXL_AQ_VSI_CAS_PV_TAGX_MASK (0x3 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 524 #define IXL_AQ_VSI_CAS_PV_TAGX_LEAVE (0x0 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 525 #define IXL_AQ_VSI_CAS_PV_TAGX_REMOVE (0x1 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 526 #define IXL_AQ_VSI_CAS_PV_TAGX_COPY (0x2 << IXL_AQ_VSI_CAS_PV_TAGX_SHIFT) 527 #define IXL_AQ_VSI_CAS_PV_INSERT_TAG (1 << 4) 528 #define IXL_AQ_VSI_CAS_PV_ETAG_PRUNE (1 << 5) 529 #define IXL_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG \ 530 (1 << 6) 531 uint8_t _reserved4; 532 533 /* queue mapping section */ 534 uint16_t mapping_flags; 535 #define IXL_AQ_VSI_QUE_MAP_MASK 0x1 536 #define IXL_AQ_VSI_QUE_MAP_CONTIG 0x0 537 #define IXL_AQ_VSI_QUE_MAP_NONCONTIG 0x1 538 uint16_t queue_mapping[16]; 539 #define IXL_AQ_VSI_QUEUE_SHIFT 0x0 540 #define IXL_AQ_VSI_QUEUE_MASK (0x7ff << IXL_AQ_VSI_QUEUE_SHIFT) 541 uint16_t tc_mapping[8]; 542 #define IXL_AQ_VSI_TC_Q_OFFSET_SHIFT 0 543 #define IXL_AQ_VSI_TC_Q_OFFSET_MASK (0x1ff << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) 544 #define IXL_AQ_VSI_TC_Q_NUMBER_SHIFT 9 545 #define IXL_AQ_VSI_TC_Q_NUMBER_MASK (0x7 << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT) 546 547 /* queueing option section */ 548 uint8_t queueing_opt_flags; 549 #define IXL_AQ_VSI_QUE_OPT_MCAST_UDP_EN (1 << 2) 550 #define IXL_AQ_VSI_QUE_OPT_UCAST_UDP_EN (1 << 3) 551 #define IXL_AQ_VSI_QUE_OPT_TCP_EN (1 << 4) 552 #define IXL_AQ_VSI_QUE_OPT_FCOE_EN (1 << 5) 553 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_PF 0 554 #define IXL_AQ_VSI_QUE_OPT_RSS_LUT_VSI (1 << 6) 555 uint8_t _reserved5[3]; 556 557 /* scheduler section */ 558 uint8_t up_enable_bits; 559 uint8_t _reserved6; 560 561 /* outer up section */ 562 uint32_t outer_up_table; /* same as ingress/egress tables */ 563 uint8_t _reserved7[8]; 564 565 /* last 32 bytes are written by FW */ 566 uint16_t qs_handle[8]; 567 #define IXL_AQ_VSI_QS_HANDLE_INVALID 0xffff 568 uint16_t stat_counter_idx; 569 uint16_t sched_id; 570 571 uint8_t _reserved8[12]; 572 } __packed __aligned(8); 573 574 CTASSERT(sizeof(struct ixl_aq_vsi_data) == 128); 575 576 struct ixl_aq_vsi_promisc_param { 577 uint16_t flags; 578 uint16_t valid_flags; 579 #define IXL_AQ_VSI_PROMISC_FLAG_UCAST (1 << 0) 580 #define IXL_AQ_VSI_PROMISC_FLAG_MCAST (1 << 1) 581 #define IXL_AQ_VSI_PROMISC_FLAG_BCAST (1 << 2) 582 #define IXL_AQ_VSI_PROMISC_FLAG_DFLT (1 << 3) 583 #define IXL_AQ_VSI_PROMISC_FLAG_VLAN (1 << 4) 584 #define IXL_AQ_VSI_PROMISC_FLAG_RXONLY (1 << 15) 585 586 uint16_t seid; 587 #define IXL_AQ_VSI_PROMISC_SEID_VALID (1 << 15) 588 uint16_t vlan; 589 #define IXL_AQ_VSI_PROMISC_VLAN_VALID (1 << 15) 590 uint32_t reserved[2]; 591 } __packed __aligned(8); 592 593 struct ixl_aq_veb_param { 594 uint16_t uplink_seid; 595 uint16_t downlink_seid; 596 uint16_t veb_flags; 597 #define IXL_AQ_ADD_VEB_FLOATING (1 << 0) 598 #define IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT 1 599 #define IXL_AQ_ADD_VEB_PORT_TYPE_MASK (0x3 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 600 #define IXL_AQ_ADD_VEB_PORT_TYPE_DEFAULT \ 601 (0x2 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 602 #define IXL_AQ_ADD_VEB_PORT_TYPE_DATA (0x4 << IXL_AQ_ADD_VEB_PORT_TYPE_SHIFT) 603 #define IXL_AQ_ADD_VEB_ENABLE_L2_FILTER (1 << 3) /* deprecated */ 604 #define IXL_AQ_ADD_VEB_DISABLE_STATS (1 << 4) 605 uint8_t enable_tcs; 606 uint8_t _reserved[9]; 607 } __packed __aligned(16); 608 609 struct ixl_aq_veb_reply { 610 uint16_t _reserved1; 611 uint16_t _reserved2; 612 uint16_t _reserved3; 613 uint16_t switch_seid; 614 uint16_t veb_seid; 615 #define IXL_AQ_VEB_ERR_FLAG_NO_VEB (1 << 0) 616 #define IXL_AQ_VEB_ERR_FLAG_NO_SCHED (1 << 1) 617 #define IXL_AQ_VEB_ERR_FLAG_NO_COUNTER (1 << 2) 618 #define IXL_AQ_VEB_ERR_FLAG_NO_ENTRY (1 << 3); 619 uint16_t statistic_index; 620 uint16_t vebs_used; 621 uint16_t vebs_free; 622 } __packed __aligned(16); 623 624 /* GET PHY ABILITIES param[0] */ 625 #define IXL_AQ_PHY_REPORT_QUAL (1 << 0) 626 #define IXL_AQ_PHY_REPORT_INIT (1 << 1) 627 628 struct ixl_aq_phy_reg_access { 629 uint8_t phy_iface; 630 #define IXL_AQ_PHY_IF_INTERNAL 0 631 #define IXL_AQ_PHY_IF_EXTERNAL 1 632 #define IXL_AQ_PHY_IF_MODULE 2 633 uint8_t dev_addr; 634 uint16_t recall; 635 #define IXL_AQ_PHY_QSFP_DEV_ADDR 0 636 #define IXL_AQ_PHY_QSFP_LAST 1 637 uint32_t reg; 638 uint32_t val; 639 uint32_t _reserved2; 640 } __packed __aligned(16); 641 642 /* RESTART_AN param[0] */ 643 #define IXL_AQ_PHY_RESTART_AN (1 << 1) 644 #define IXL_AQ_PHY_LINK_ENABLE (1 << 2) 645 646 struct ixl_aq_link_status { /* this occupies the iaq_param space */ 647 uint16_t command_flags; /* only field set on command */ 648 #define IXL_AQ_LSE_MASK 0x3 649 #define IXL_AQ_LSE_NOP 0x0 650 #define IXL_AQ_LSE_DISABLE 0x2 651 #define IXL_AQ_LSE_ENABLE 0x3 652 #define IXL_AQ_LSE_IS_ENABLED 0x1 /* only set in response */ 653 uint8_t phy_type; 654 uint8_t link_speed; 655 #define IXL_AQ_LINK_SPEED_1GB (1 << 2) 656 #define IXL_AQ_LINK_SPEED_10GB (1 << 3) 657 #define IXL_AQ_LINK_SPEED_40GB (1 << 4) 658 #define IXL_AQ_LINK_SPEED_25GB (1 << 6) 659 uint8_t link_info; 660 #define IXL_AQ_LINK_UP_FUNCTION 0x01 661 #define IXL_AQ_LINK_FAULT 0x02 662 #define IXL_AQ_LINK_FAULT_TX 0x04 663 #define IXL_AQ_LINK_FAULT_RX 0x08 664 #define IXL_AQ_LINK_FAULT_REMOTE 0x10 665 #define IXL_AQ_LINK_UP_PORT 0x20 666 #define IXL_AQ_MEDIA_AVAILABLE 0x40 667 #define IXL_AQ_SIGNAL_DETECT 0x80 668 uint8_t an_info; 669 #define IXL_AQ_AN_COMPLETED 0x01 670 #define IXL_AQ_LP_AN_ABILITY 0x02 671 #define IXL_AQ_PD_FAULT 0x04 672 #define IXL_AQ_FEC_EN 0x08 673 #define IXL_AQ_PHY_LOW_POWER 0x10 674 #define IXL_AQ_LINK_PAUSE_TX 0x20 675 #define IXL_AQ_LINK_PAUSE_RX 0x40 676 #define IXL_AQ_QUALIFIED_MODULE 0x80 677 678 uint8_t ext_info; 679 #define IXL_AQ_LINK_PHY_TEMP_ALARM 0x01 680 #define IXL_AQ_LINK_XCESSIVE_ERRORS 0x02 681 #define IXL_AQ_LINK_TX_SHIFT 0x02 682 #define IXL_AQ_LINK_TX_MASK (0x03 << IXL_AQ_LINK_TX_SHIFT) 683 #define IXL_AQ_LINK_TX_ACTIVE 0x00 684 #define IXL_AQ_LINK_TX_DRAINED 0x01 685 #define IXL_AQ_LINK_TX_FLUSHED 0x03 686 #define IXL_AQ_LINK_FORCED_40G 0x10 687 /* 25G Error Codes */ 688 #define IXL_AQ_25G_NO_ERR 0X00 689 #define IXL_AQ_25G_NOT_PRESENT 0X01 690 #define IXL_AQ_25G_NVM_CRC_ERR 0X02 691 #define IXL_AQ_25G_SBUS_UCODE_ERR 0X03 692 #define IXL_AQ_25G_SERDES_UCODE_ERR 0X04 693 #define IXL_AQ_25G_NIMB_UCODE_ERR 0X05 694 uint8_t loopback; 695 uint16_t max_frame_size; 696 697 uint8_t config; 698 #define IXL_AQ_CONFIG_FEC_KR_ENA 0x01 699 #define IXL_AQ_CONFIG_FEC_RS_ENA 0x02 700 #define IXL_AQ_CONFIG_CRC_ENA 0x04 701 #define IXL_AQ_CONFIG_PACING_MASK 0x78 702 uint8_t power_desc; 703 #define IXL_AQ_LINK_POWER_CLASS_1 0x00 704 #define IXL_AQ_LINK_POWER_CLASS_2 0x01 705 #define IXL_AQ_LINK_POWER_CLASS_3 0x02 706 #define IXL_AQ_LINK_POWER_CLASS_4 0x03 707 #define IXL_AQ_PWR_CLASS_MASK 0x03 708 709 uint8_t reserved[4]; 710 } __packed __aligned(4); 711 /* event mask command flags for param[2] */ 712 #define IXL_AQ_PHY_EV_MASK 0x3ff 713 #define IXL_AQ_PHY_EV_LINK_UPDOWN (1 << 1) 714 #define IXL_AQ_PHY_EV_MEDIA_NA (1 << 2) 715 #define IXL_AQ_PHY_EV_LINK_FAULT (1 << 3) 716 #define IXL_AQ_PHY_EV_PHY_TEMP_ALARM (1 << 4) 717 #define IXL_AQ_PHY_EV_EXCESS_ERRORS (1 << 5) 718 #define IXL_AQ_PHY_EV_SIGNAL_DETECT (1 << 6) 719 #define IXL_AQ_PHY_EV_AN_COMPLETED (1 << 7) 720 #define IXL_AQ_PHY_EV_MODULE_QUAL_FAIL (1 << 8) 721 #define IXL_AQ_PHY_EV_PORT_TX_SUSPENDED (1 << 9) 722 723 struct ixl_aq_rss_lut { /* 722 */ 724 #define IXL_AQ_SET_RSS_LUT_VSI_VALID (1 << 15) 725 #define IXL_AQ_SET_RSS_LUT_VSI_ID_SHIFT 0 726 #define IXL_AQ_SET_RSS_LUT_VSI_ID_MASK \ 727 (0x3FF << IXL_AQ_SET_RSS_LUT_VSI_ID_SHIFT) 728 729 uint16_t vsi_number; 730 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 731 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_MASK \ 732 (0x1 << IXL_AQ_SET_RSS_LUT_TABLE_TYPE_SHIFT) 733 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_VSI 0 734 #define IXL_AQ_SET_RSS_LUT_TABLE_TYPE_PF 1 735 uint16_t flags; 736 uint8_t _reserved[4]; 737 uint32_t addr_hi; 738 uint32_t addr_lo; 739 } __packed __aligned(16); 740 741 struct ixl_aq_get_set_rss_key { /* 722 */ 742 #define IXL_AQ_SET_RSS_KEY_VSI_VALID (1 << 15) 743 #define IXL_AQ_SET_RSS_KEY_VSI_ID_SHIFT 0 744 #define IXL_AQ_SET_RSS_KEY_VSI_ID_MASK \ 745 (0x3FF << IXL_AQ_SET_RSS_KEY_VSI_ID_SHIFT) 746 uint16_t vsi_number; 747 uint8_t _reserved[6]; 748 uint32_t addr_hi; 749 uint32_t addr_lo; 750 } __packed __aligned(16); 751 752 /* aq response codes */ 753 #define IXL_AQ_RC_OK 0 /* success */ 754 #define IXL_AQ_RC_EPERM 1 /* Operation not permitted */ 755 #define IXL_AQ_RC_ENOENT 2 /* No such element */ 756 #define IXL_AQ_RC_ESRCH 3 /* Bad opcode */ 757 #define IXL_AQ_RC_EINTR 4 /* operation interrupted */ 758 #define IXL_AQ_RC_EIO 5 /* I/O error */ 759 #define IXL_AQ_RC_ENXIO 6 /* No such resource */ 760 #define IXL_AQ_RC_E2BIG 7 /* Arg too long */ 761 #define IXL_AQ_RC_EAGAIN 8 /* Try again */ 762 #define IXL_AQ_RC_ENOMEM 9 /* Out of memory */ 763 #define IXL_AQ_RC_EACCES 10 /* Permission denied */ 764 #define IXL_AQ_RC_EFAULT 11 /* Bad address */ 765 #define IXL_AQ_RC_EBUSY 12 /* Device or resource busy */ 766 #define IXL_AQ_RC_EEXIST 13 /* object already exists */ 767 #define IXL_AQ_RC_EINVAL 14 /* invalid argument */ 768 #define IXL_AQ_RC_ENOTTY 15 /* not a typewriter */ 769 #define IXL_AQ_RC_ENOSPC 16 /* No space or alloc failure */ 770 #define IXL_AQ_RC_ENOSYS 17 /* function not implemented */ 771 #define IXL_AQ_RC_ERANGE 18 /* parameter out of range */ 772 #define IXL_AQ_RC_EFLUSHED 19 /* cmd flushed due to prev error */ 773 #define IXL_AQ_RC_BAD_ADDR 20 /* contains a bad pointer */ 774 #define IXL_AQ_RC_EMODE 21 /* not allowed in current mode */ 775 #define IXL_AQ_RC_EFBIG 22 /* file too large */ 776 777 struct ixl_tx_desc { 778 uint64_t addr; 779 uint64_t cmd; 780 #define IXL_TX_DESC_DTYPE_SHIFT 0 781 #define IXL_TX_DESC_DTYPE_MASK (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 782 #define IXL_TX_DESC_DTYPE_DATA (0x0ULL << IXL_TX_DESC_DTYPE_SHIFT) 783 #define IXL_TX_DESC_DTYPE_NOP (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 784 #define IXL_TX_DESC_DTYPE_CONTEXT (0x1ULL << IXL_TX_DESC_DTYPE_SHIFT) 785 #define IXL_TX_DESC_DTYPE_FCOE_CTX (0x2ULL << IXL_TX_DESC_DTYPE_SHIFT) 786 #define IXL_TX_DESC_DTYPE_FD (0x8ULL << IXL_TX_DESC_DTYPE_SHIFT) 787 #define IXL_TX_DESC_DTYPE_DDP_CTX (0x9ULL << IXL_TX_DESC_DTYPE_SHIFT) 788 #define IXL_TX_DESC_DTYPE_FLEX_DATA (0xbULL << IXL_TX_DESC_DTYPE_SHIFT) 789 #define IXL_TX_DESC_DTYPE_FLEX_CTX_1 (0xcULL << IXL_TX_DESC_DTYPE_SHIFT) 790 #define IXL_TX_DESC_DTYPE_FLEX_CTX_2 (0xdULL << IXL_TX_DESC_DTYPE_SHIFT) 791 #define IXL_TX_DESC_DTYPE_DONE (0xfULL << IXL_TX_DESC_DTYPE_SHIFT) 792 793 #define IXL_TX_DESC_CMD_SHIFT 4 794 #define IXL_TX_DESC_CMD_MASK (0x3ffULL << IXL_TX_DESC_CMD_SHIFT) 795 #define IXL_TX_DESC_CMD_EOP (0x001 << IXL_TX_DESC_CMD_SHIFT) 796 #define IXL_TX_DESC_CMD_RS (0x002 << IXL_TX_DESC_CMD_SHIFT) 797 #define IXL_TX_DESC_CMD_ICRC (0x004 << IXL_TX_DESC_CMD_SHIFT) 798 #define IXL_TX_DESC_CMD_IL2TAG1 (0x008 << IXL_TX_DESC_CMD_SHIFT) 799 #define IXL_TX_DESC_CMD_DUMMY (0x010 << IXL_TX_DESC_CMD_SHIFT) 800 #define IXL_TX_DESC_CMD_IIPT_MASK (0x060 << IXL_TX_DESC_CMD_SHIFT) 801 #define IXL_TX_DESC_CMD_IIPT_NONIP (0x000 << IXL_TX_DESC_CMD_SHIFT) 802 #define IXL_TX_DESC_CMD_IIPT_IPV6 (0x020 << IXL_TX_DESC_CMD_SHIFT) 803 #define IXL_TX_DESC_CMD_IIPT_IPV4 (0x040 << IXL_TX_DESC_CMD_SHIFT) 804 #define IXL_TX_DESC_CMD_IIPT_IPV4_CSUM (0x060 << IXL_TX_DESC_CMD_SHIFT) 805 #define IXL_TX_DESC_CMD_FCOET (0x080 << IXL_TX_DESC_CMD_SHIFT) 806 #define IXL_TX_DESC_CMD_L4T_EOFT_MASK (0x300 << IXL_TX_DESC_CMD_SHIFT) 807 #define IXL_TX_DESC_CMD_L4T_EOFT_UNK (0x000 << IXL_TX_DESC_CMD_SHIFT) 808 #define IXL_TX_DESC_CMD_L4T_EOFT_TCP (0x100 << IXL_TX_DESC_CMD_SHIFT) 809 #define IXL_TX_DESC_CMD_L4T_EOFT_SCTP (0x200 << IXL_TX_DESC_CMD_SHIFT) 810 #define IXL_TX_DESC_CMD_L4T_EOFT_UDP (0x300 << IXL_TX_DESC_CMD_SHIFT) 811 812 #define IXL_TX_DESC_MACLEN_SHIFT 16 813 #define IXL_TX_DESC_MACLEN_MASK (0x7fULL << IXL_TX_DESC_MACLEN_SHIFT) 814 #define IXL_TX_DESC_IPLEN_SHIFT 23 815 #define IXL_TX_DESC_IPLEN_MASK (0x7fULL << IXL_TX_DESC_IPLEN_SHIFT) 816 #define IXL_TX_DESC_L4LEN_SHIFT 30 817 #define IXL_TX_DESC_L4LEN_MASK (0xfULL << IXL_TX_DESC_L4LEN_SHIFT) 818 #define IXL_TX_DESC_FCLEN_SHIFT 30 819 #define IXL_TX_DESC_FCLEN_MASK (0xfULL << IXL_TX_DESC_FCLEN_SHIFT) 820 821 #define IXL_TX_DESC_BSIZE_SHIFT 34 822 #define IXL_TX_DESC_BSIZE_MAX 0x3fffULL 823 #define IXL_TX_DESC_BSIZE_MASK \ 824 (IXL_TX_DESC_BSIZE_MAX << IXL_TX_DESC_BSIZE_SHIFT) 825 } __packed __aligned(16); 826 827 struct ixl_rx_rd_desc_16 { 828 uint64_t paddr; /* packet addr */ 829 uint64_t haddr; /* header addr */ 830 } __packed __aligned(16); 831 832 struct ixl_rx_rd_desc_32 { 833 uint64_t paddr; /* packet addr */ 834 uint64_t haddr; /* header addr */ 835 uint64_t _reserved1; 836 uint64_t _reserved2; 837 } __packed __aligned(16); 838 839 struct ixl_rx_wb_desc_16 { 840 uint32_t _reserved1; 841 uint32_t filter_status; 842 uint64_t qword1; 843 #define IXL_RX_DESC_DD (1 << 0) 844 #define IXL_RX_DESC_EOP (1 << 1) 845 #define IXL_RX_DESC_L2TAG1P (1 << 2) 846 #define IXL_RX_DESC_L3L4P (1 << 3) 847 #define IXL_RX_DESC_CRCP (1 << 4) 848 #define IXL_RX_DESC_TSYNINDX_SHIFT 5 /* TSYNINDX */ 849 #define IXL_RX_DESC_TSYNINDX_MASK (7 << IXL_RX_DESC_TSYNINDX_SHIFT) 850 #define IXL_RX_DESC_UMB_SHIFT 9 851 #define IXL_RX_DESC_UMB_MASK (0x3 << IXL_RX_DESC_UMB_SHIFT) 852 #define IXL_RX_DESC_UMB_UCAST (0x0 << IXL_RX_DESC_UMB_SHIFT) 853 #define IXL_RX_DESC_UMB_MCAST (0x1 << IXL_RX_DESC_UMB_SHIFT) 854 #define IXL_RX_DESC_UMB_BCAST (0x2 << IXL_RX_DESC_UMB_SHIFT) 855 #define IXL_RX_DESC_UMB_MIRROR (0x3 << IXL_RX_DESC_UMB_SHIFT) 856 #define IXL_RX_DESC_FLM (1 << 11) 857 #define IXL_RX_DESC_FLTSTAT_SHIFT 12 858 #define IXL_RX_DESC_FLTSTAT_MASK (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 859 #define IXL_RX_DESC_FLTSTAT_NODATA (0x0 << IXL_RX_DESC_FLTSTAT_SHIFT) 860 #define IXL_RX_DESC_FLTSTAT_FDFILTID (0x1 << IXL_RX_DESC_FLTSTAT_SHIFT) 861 #define IXL_RX_DESC_FLTSTAT_RSS (0x3 << IXL_RX_DESC_FLTSTAT_SHIFT) 862 #define IXL_RX_DESC_LPBK (1 << 14) 863 #define IXL_RX_DESC_IPV6EXTADD (1 << 15) 864 #define IXL_RX_DESC_INT_UDP_0 (1 << 18) 865 866 #define IXL_RX_DESC_RXE (1 << 19) 867 #define IXL_RX_DESC_HBO (1 << 21) 868 #define IXL_RX_DESC_IPE (1 << 22) 869 #define IXL_RX_DESC_L4E (1 << 23) 870 #define IXL_RX_DESC_EIPE (1 << 24) 871 #define IXL_RX_DESC_OVERSIZE (1 << 25) 872 873 #define IXL_RX_DESC_PTYPE_SHIFT 30 874 #define IXL_RX_DESC_PTYPE_MASK (0xffULL << IXL_RX_DESC_PTYPE_SHIFT) 875 876 #define IXL_RX_DESC_PLEN_SHIFT 38 877 #define IXL_RX_DESC_PLEN_MASK (0x3fffULL << IXL_RX_DESC_PLEN_SHIFT) 878 #define IXL_RX_DESC_HLEN_SHIFT 42 879 #define IXL_RX_DESC_HLEN_MASK (0x7ffULL << IXL_RX_DESC_HLEN_SHIFT) 880 } __packed __aligned(16); 881 882 struct ixl_rx_wb_desc_32 { 883 uint64_t qword0; 884 uint64_t qword1; 885 uint64_t qword2; 886 uint64_t qword3; 887 } __packed __aligned(16); 888 889 #define IXL_TX_PKT_DESCS 8 890 #define IXL_TX_QUEUE_ALIGN 128 891 #define IXL_RX_QUEUE_ALIGN 128 892 893 #define IXL_HARDMTU 9712 /* 9726 - ETHER_HDR_LEN */ 894 895 #define IXL_PCIREG PCI_MAPREG_START 896 897 #define IXL_ITR0 0x0 898 #define IXL_ITR1 0x1 899 #define IXL_ITR2 0x2 900 #define IXL_NOITR 0x2 901 902 #define IXL_AQ_NUM 256 903 #define IXL_AQ_MASK (IXL_AQ_NUM - 1) 904 #define IXL_AQ_ALIGN 64 /* lol */ 905 #define IXL_AQ_BUFLEN 4096 906 907 /* Packet Classifier Types for filters */ 908 /* bits 0-28 are reserved for future use */ 909 #define IXL_PCT_NONF_IPV4_UDP_UCAST (1ULL << 29) /* 722 */ 910 #define IXL_PCT_NONF_IPV4_UDP_MCAST (1ULL << 30) /* 722 */ 911 #define IXL_PCT_NONF_IPV4_UDP (1ULL << 31) 912 #define IXL_PCT_NONF_IPV4_TCP_SYN_NOACK (1ULL << 32) /* 722 */ 913 #define IXL_PCT_NONF_IPV4_TCP (1ULL << 33) 914 #define IXL_PCT_NONF_IPV4_SCTP (1ULL << 34) 915 #define IXL_PCT_NONF_IPV4_OTHER (1ULL << 35) 916 #define IXL_PCT_FRAG_IPV4 (1ULL << 36) 917 /* bits 37-38 are reserved for future use */ 918 #define IXL_PCT_NONF_IPV6_UDP_UCAST (1ULL << 39) /* 722 */ 919 #define IXL_PCT_NONF_IPV6_UDP_MCAST (1ULL << 40) /* 722 */ 920 #define IXL_PCT_NONF_IPV6_UDP (1ULL << 41) 921 #define IXL_PCT_NONF_IPV6_TCP_SYN_NOACK (1ULL << 42) /* 722 */ 922 #define IXL_PCT_NONF_IPV6_TCP (1ULL << 43) 923 #define IXL_PCT_NONF_IPV6_SCTP (1ULL << 44) 924 #define IXL_PCT_NONF_IPV6_OTHER (1ULL << 45) 925 #define IXL_PCT_FRAG_IPV6 (1ULL << 46) 926 /* bit 47 is reserved for future use */ 927 #define IXL_PCT_FCOE_OX (1ULL << 48) 928 #define IXL_PCT_FCOE_RX (1ULL << 49) 929 #define IXL_PCT_FCOE_OTHER (1ULL << 50) 930 /* bits 51-62 are reserved for future use */ 931 #define IXL_PCT_L2_PAYLOAD (1ULL << 63) 932 933 #define IXL_RSS_HENA_BASE_DEFAULT \ 934 IXL_PCT_NONF_IPV4_UDP | \ 935 IXL_PCT_NONF_IPV4_TCP | \ 936 IXL_PCT_NONF_IPV4_SCTP | \ 937 IXL_PCT_NONF_IPV4_OTHER | \ 938 IXL_PCT_FRAG_IPV4 | \ 939 IXL_PCT_NONF_IPV6_UDP | \ 940 IXL_PCT_NONF_IPV6_TCP | \ 941 IXL_PCT_NONF_IPV6_SCTP | \ 942 IXL_PCT_NONF_IPV6_OTHER | \ 943 IXL_PCT_FRAG_IPV6 | \ 944 IXL_PCT_L2_PAYLOAD 945 946 #define IXL_RSS_HENA_BASE_710 IXL_RSS_HENA_BASE_DEFAULT 947 #define IXL_RSS_HENA_BASE_722 IXL_RSS_HENA_BASE_DEFAULT | \ 948 IXL_PCT_NONF_IPV4_UDP_UCAST | \ 949 IXL_PCT_NONF_IPV4_UDP_MCAST | \ 950 IXL_PCT_NONF_IPV6_UDP_UCAST | \ 951 IXL_PCT_NONF_IPV6_UDP_MCAST | \ 952 IXL_PCT_NONF_IPV4_TCP_SYN_NOACK | \ 953 IXL_PCT_NONF_IPV6_TCP_SYN_NOACK 954 955 #define IXL_HMC_ROUNDUP 512 956 #define IXL_HMC_PGSIZE 4096 957 #define IXL_HMC_DVASZ sizeof(uint64_t) 958 #define IXL_HMC_PGS (IXL_HMC_PGSIZE / IXL_HMC_DVASZ) 959 #define IXL_HMC_L2SZ (IXL_HMC_PGSIZE * IXL_HMC_PGS) 960 #define IXL_HMC_PDVALID 1ULL 961 962 struct ixl_aq_regs { 963 bus_size_t atq_tail; 964 bus_size_t atq_head; 965 bus_size_t atq_len; 966 bus_size_t atq_bal; 967 bus_size_t atq_bah; 968 969 bus_size_t arq_tail; 970 bus_size_t arq_head; 971 bus_size_t arq_len; 972 bus_size_t arq_bal; 973 bus_size_t arq_bah; 974 975 uint32_t atq_len_enable; 976 uint32_t atq_tail_mask; 977 uint32_t atq_head_mask; 978 979 uint32_t arq_len_enable; 980 uint32_t arq_tail_mask; 981 uint32_t arq_head_mask; 982 }; 983 984 struct ixl_phy_type { 985 uint64_t phy_type; 986 uint64_t ifm_type; 987 }; 988 989 struct ixl_speed_type { 990 uint8_t dev_speed; 991 uint64_t net_speed; 992 }; 993 994 struct ixl_aq_buf { 995 SIMPLEQ_ENTRY(ixl_aq_buf) 996 aqb_entry; 997 void *aqb_data; 998 bus_dmamap_t aqb_map; 999 }; 1000 SIMPLEQ_HEAD(ixl_aq_bufs, ixl_aq_buf); 1001 1002 struct ixl_dmamem { 1003 bus_dmamap_t ixm_map; 1004 bus_dma_segment_t ixm_seg; 1005 int ixm_nsegs; 1006 size_t ixm_size; 1007 caddr_t ixm_kva; 1008 }; 1009 #define IXL_DMA_MAP(_ixm) ((_ixm)->ixm_map) 1010 #define IXL_DMA_DVA(_ixm) ((_ixm)->ixm_map->dm_segs[0].ds_addr) 1011 #define IXL_DMA_KVA(_ixm) ((void *)(_ixm)->ixm_kva) 1012 #define IXL_DMA_LEN(_ixm) ((_ixm)->ixm_size) 1013 1014 struct ixl_hmc_entry { 1015 uint64_t hmc_base; 1016 uint32_t hmc_count; 1017 uint32_t hmc_size; 1018 }; 1019 1020 #define IXL_HMC_LAN_TX 0 1021 #define IXL_HMC_LAN_RX 1 1022 #define IXL_HMC_FCOE_CTX 2 1023 #define IXL_HMC_FCOE_FILTER 3 1024 #define IXL_HMC_COUNT 4 1025 1026 struct ixl_hmc_pack { 1027 uint16_t offset; 1028 uint16_t width; 1029 uint16_t lsb; 1030 }; 1031 1032 /* 1033 * these hmc objects have weird sizes and alignments, so these are abstract 1034 * representations of them that are nice for c to populate. 1035 * 1036 * the packing code relies on little-endian values being stored in the fields, 1037 * no high bits in the fields being set, and the fields must be packed in the 1038 * same order as they are in the ctx structure. 1039 */ 1040 1041 struct ixl_hmc_rxq { 1042 uint16_t head; 1043 uint8_t cpuid; 1044 uint64_t base; 1045 #define IXL_HMC_RXQ_BASE_UNIT 128 1046 uint16_t qlen; 1047 uint16_t dbuff; 1048 #define IXL_HMC_RXQ_DBUFF_UNIT 128 1049 uint8_t hbuff; 1050 #define IXL_HMC_RXQ_HBUFF_UNIT 64 1051 uint8_t dtype; 1052 #define IXL_HMC_RXQ_DTYPE_NOSPLIT 0x0 1053 #define IXL_HMC_RXQ_DTYPE_HSPLIT 0x1 1054 #define IXL_HMC_RXQ_DTYPE_SPLIT_ALWAYS 0x2 1055 uint8_t dsize; 1056 #define IXL_HMC_RXQ_DSIZE_16 0 1057 #define IXL_HMC_RXQ_DSIZE_32 1 1058 uint8_t crcstrip; 1059 uint8_t fc_ena; 1060 uint8_t l2sel; 1061 uint8_t hsplit_0; 1062 uint8_t hsplit_1; 1063 uint8_t showiv; 1064 uint16_t rxmax; 1065 uint8_t tphrdesc_ena; 1066 uint8_t tphwdesc_ena; 1067 uint8_t tphdata_ena; 1068 uint8_t tphhead_ena; 1069 uint8_t lrxqthresh; 1070 uint8_t prefena; 1071 }; 1072 1073 static const struct ixl_hmc_pack ixl_hmc_pack_rxq[] = { 1074 { offsetof(struct ixl_hmc_rxq, head), 13, 0 }, 1075 { offsetof(struct ixl_hmc_rxq, cpuid), 8, 13 }, 1076 { offsetof(struct ixl_hmc_rxq, base), 57, 32 }, 1077 { offsetof(struct ixl_hmc_rxq, qlen), 13, 89 }, 1078 { offsetof(struct ixl_hmc_rxq, dbuff), 7, 102 }, 1079 { offsetof(struct ixl_hmc_rxq, hbuff), 5, 109 }, 1080 { offsetof(struct ixl_hmc_rxq, dtype), 2, 114 }, 1081 { offsetof(struct ixl_hmc_rxq, dsize), 1, 116 }, 1082 { offsetof(struct ixl_hmc_rxq, crcstrip), 1, 117 }, 1083 { offsetof(struct ixl_hmc_rxq, fc_ena), 1, 118 }, 1084 { offsetof(struct ixl_hmc_rxq, l2sel), 1, 119 }, 1085 { offsetof(struct ixl_hmc_rxq, hsplit_0), 4, 120 }, 1086 { offsetof(struct ixl_hmc_rxq, hsplit_1), 2, 124 }, 1087 { offsetof(struct ixl_hmc_rxq, showiv), 1, 127 }, 1088 { offsetof(struct ixl_hmc_rxq, rxmax), 14, 174 }, 1089 { offsetof(struct ixl_hmc_rxq, tphrdesc_ena), 1, 193 }, 1090 { offsetof(struct ixl_hmc_rxq, tphwdesc_ena), 1, 194 }, 1091 { offsetof(struct ixl_hmc_rxq, tphdata_ena), 1, 195 }, 1092 { offsetof(struct ixl_hmc_rxq, tphhead_ena), 1, 196 }, 1093 { offsetof(struct ixl_hmc_rxq, lrxqthresh), 3, 198 }, 1094 { offsetof(struct ixl_hmc_rxq, prefena), 1, 201 }, 1095 }; 1096 1097 #define IXL_HMC_RXQ_MINSIZE (201 + 1) 1098 1099 struct ixl_hmc_txq { 1100 uint16_t head; 1101 uint8_t new_context; 1102 uint64_t base; 1103 #define IXL_HMC_TXQ_BASE_UNIT 128 1104 uint8_t fc_ena; 1105 uint8_t timesync_ena; 1106 uint8_t fd_ena; 1107 uint8_t alt_vlan_ena; 1108 uint16_t thead_wb; 1109 uint8_t cpuid; 1110 uint8_t head_wb_ena; 1111 #define IXL_HMC_TXQ_DESC_WB 0 1112 #define IXL_HMC_TXQ_HEAD_WB 1 1113 uint16_t qlen; 1114 uint8_t tphrdesc_ena; 1115 uint8_t tphrpacket_ena; 1116 uint8_t tphwdesc_ena; 1117 uint64_t head_wb_addr; 1118 uint32_t crc; 1119 uint16_t rdylist; 1120 uint8_t rdylist_act; 1121 }; 1122 1123 static const struct ixl_hmc_pack ixl_hmc_pack_txq[] = { 1124 { offsetof(struct ixl_hmc_txq, head), 13, 0 }, 1125 { offsetof(struct ixl_hmc_txq, new_context), 1, 30 }, 1126 { offsetof(struct ixl_hmc_txq, base), 57, 32 }, 1127 { offsetof(struct ixl_hmc_txq, fc_ena), 1, 89 }, 1128 { offsetof(struct ixl_hmc_txq, timesync_ena), 1, 90 }, 1129 { offsetof(struct ixl_hmc_txq, fd_ena), 1, 91 }, 1130 { offsetof(struct ixl_hmc_txq, alt_vlan_ena), 1, 92 }, 1131 { offsetof(struct ixl_hmc_txq, cpuid), 8, 96 }, 1132 /* line 1 */ 1133 { offsetof(struct ixl_hmc_txq, thead_wb), 13, 0 + 128 }, 1134 { offsetof(struct ixl_hmc_txq, head_wb_ena), 1, 32 + 128 }, 1135 { offsetof(struct ixl_hmc_txq, qlen), 13, 33 + 128 }, 1136 { offsetof(struct ixl_hmc_txq, tphrdesc_ena), 1, 46 + 128 }, 1137 { offsetof(struct ixl_hmc_txq, tphrpacket_ena), 1, 47 + 128 }, 1138 { offsetof(struct ixl_hmc_txq, tphwdesc_ena), 1, 48 + 128 }, 1139 { offsetof(struct ixl_hmc_txq, head_wb_addr), 64, 64 + 128 }, 1140 /* line 7 */ 1141 { offsetof(struct ixl_hmc_txq, crc), 32, 0 + (7*128) }, 1142 { offsetof(struct ixl_hmc_txq, rdylist), 10, 84 + (7*128) }, 1143 { offsetof(struct ixl_hmc_txq, rdylist_act), 1, 94 + (7*128) }, 1144 }; 1145 1146 #define IXL_HMC_TXQ_MINSIZE (94 + (7*128) + 1) 1147 1148 struct ixl_rss_key { 1149 uint32_t key[13]; 1150 }; 1151 1152 struct ixl_rss_lut_128 { 1153 uint32_t entries[128 / sizeof(uint32_t)]; 1154 }; 1155 1156 struct ixl_rss_lut_512 { 1157 uint32_t entries[512 / sizeof(uint32_t)]; 1158 }; 1159 1160 /* driver structures */ 1161 1162 struct ixl_vector; 1163 struct ixl_chip; 1164 1165 struct ixl_tx_map { 1166 struct mbuf *txm_m; 1167 bus_dmamap_t txm_map; 1168 unsigned int txm_eop; 1169 }; 1170 1171 struct ixl_tx_ring { 1172 struct ixl_softc *txr_sc; 1173 struct ixl_vector *txr_vector; 1174 struct ifqueue *txr_ifq; 1175 1176 unsigned int txr_prod; 1177 unsigned int txr_cons; 1178 1179 struct ixl_tx_map *txr_maps; 1180 struct ixl_dmamem txr_mem; 1181 1182 bus_size_t txr_tail; 1183 unsigned int txr_qid; 1184 } __aligned(CACHE_LINE_SIZE); 1185 1186 struct ixl_rx_map { 1187 struct mbuf *rxm_m; 1188 bus_dmamap_t rxm_map; 1189 }; 1190 1191 struct ixl_rx_ring { 1192 struct ixl_softc *rxr_sc; 1193 struct ixl_vector *rxr_vector; 1194 struct ifiqueue *rxr_ifiq; 1195 1196 struct if_rxring rxr_acct; 1197 struct timeout rxr_refill; 1198 1199 unsigned int rxr_prod; 1200 unsigned int rxr_cons; 1201 1202 struct ixl_rx_map *rxr_maps; 1203 struct ixl_dmamem rxr_mem; 1204 1205 struct mbuf *rxr_m_head; 1206 struct mbuf **rxr_m_tail; 1207 1208 bus_size_t rxr_tail; 1209 unsigned int rxr_qid; 1210 } __aligned(CACHE_LINE_SIZE); 1211 1212 struct ixl_atq { 1213 struct ixl_aq_desc iatq_desc; 1214 void *iatq_arg; 1215 void (*iatq_fn)(struct ixl_softc *, void *); 1216 }; 1217 SIMPLEQ_HEAD(ixl_atq_list, ixl_atq); 1218 1219 struct ixl_vector { 1220 struct ixl_softc *iv_sc; 1221 struct ixl_rx_ring *iv_rxr; 1222 struct ixl_tx_ring *iv_txr; 1223 int iv_qid; 1224 void *iv_ihc; 1225 char iv_name[16]; 1226 } __aligned(CACHE_LINE_SIZE); 1227 1228 struct ixl_softc { 1229 struct device sc_dev; 1230 const struct ixl_chip *sc_chip; 1231 struct arpcom sc_ac; 1232 struct ifmedia sc_media; 1233 uint64_t sc_media_status; 1234 uint64_t sc_media_active; 1235 1236 pci_chipset_tag_t sc_pc; 1237 pci_intr_handle_t sc_ih; 1238 void *sc_ihc; 1239 pcitag_t sc_tag; 1240 1241 bus_dma_tag_t sc_dmat; 1242 bus_space_tag_t sc_memt; 1243 bus_space_handle_t sc_memh; 1244 bus_size_t sc_mems; 1245 1246 uint16_t sc_api_major; 1247 uint16_t sc_api_minor; 1248 uint8_t sc_pf_id; 1249 uint16_t sc_uplink_seid; /* le */ 1250 uint16_t sc_downlink_seid; /* le */ 1251 uint16_t sc_veb_seid; /* le */ 1252 uint16_t sc_vsi_number; /* le */ 1253 uint16_t sc_seid; 1254 unsigned int sc_base_queue; 1255 unsigned int sc_port; 1256 1257 struct ixl_dmamem sc_scratch; 1258 1259 const struct ixl_aq_regs * 1260 sc_aq_regs; 1261 1262 struct ixl_dmamem sc_atq; 1263 unsigned int sc_atq_prod; 1264 unsigned int sc_atq_cons; 1265 1266 struct ixl_dmamem sc_arq; 1267 struct task sc_arq_task; 1268 struct ixl_aq_bufs sc_arq_idle; 1269 struct ixl_aq_bufs sc_arq_live; 1270 struct if_rxring sc_arq_ring; 1271 unsigned int sc_arq_prod; 1272 unsigned int sc_arq_cons; 1273 1274 struct mutex sc_link_state_mtx; 1275 struct task sc_link_state_task; 1276 struct ixl_atq sc_link_state_atq; 1277 1278 struct ixl_dmamem sc_hmc_sd; 1279 struct ixl_dmamem sc_hmc_pd; 1280 struct ixl_hmc_entry sc_hmc_entries[IXL_HMC_COUNT]; 1281 1282 unsigned int sc_tx_ring_ndescs; 1283 unsigned int sc_rx_ring_ndescs; 1284 unsigned int sc_nqueues; /* 1 << sc_nqueues */ 1285 1286 struct intrmap *sc_intrmap; 1287 struct ixl_vector *sc_vectors; 1288 1289 struct rwlock sc_cfg_lock; 1290 unsigned int sc_dead; 1291 1292 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 1293 1294 #if NKSTAT > 0 1295 struct mutex sc_kstat_mtx; 1296 struct timeout sc_kstat_tmo; 1297 struct kstat *sc_port_kstat; 1298 struct kstat *sc_vsi_kstat; 1299 #endif 1300 }; 1301 #define DEVNAME(_sc) ((_sc)->sc_dev.dv_xname) 1302 1303 #define delaymsec(_ms) delay(1000 * (_ms)) 1304 1305 static void ixl_clear_hw(struct ixl_softc *); 1306 static int ixl_pf_reset(struct ixl_softc *); 1307 1308 static int ixl_dmamem_alloc(struct ixl_softc *, struct ixl_dmamem *, 1309 bus_size_t, u_int); 1310 static void ixl_dmamem_free(struct ixl_softc *, struct ixl_dmamem *); 1311 1312 static int ixl_arq_fill(struct ixl_softc *); 1313 static void ixl_arq_unfill(struct ixl_softc *); 1314 1315 static int ixl_atq_poll(struct ixl_softc *, struct ixl_aq_desc *, 1316 unsigned int); 1317 static void ixl_atq_set(struct ixl_atq *, 1318 void (*)(struct ixl_softc *, void *), void *); 1319 static void ixl_atq_post(struct ixl_softc *, struct ixl_atq *); 1320 static void ixl_atq_done(struct ixl_softc *); 1321 static void ixl_atq_exec(struct ixl_softc *, struct ixl_atq *, 1322 const char *); 1323 static int ixl_get_version(struct ixl_softc *); 1324 static int ixl_pxe_clear(struct ixl_softc *); 1325 static int ixl_lldp_shut(struct ixl_softc *); 1326 static int ixl_get_mac(struct ixl_softc *); 1327 static int ixl_get_switch_config(struct ixl_softc *); 1328 static int ixl_phy_mask_ints(struct ixl_softc *); 1329 static int ixl_get_phy_types(struct ixl_softc *, uint64_t *); 1330 static int ixl_restart_an(struct ixl_softc *); 1331 static int ixl_hmc(struct ixl_softc *); 1332 static void ixl_hmc_free(struct ixl_softc *); 1333 static int ixl_get_vsi(struct ixl_softc *); 1334 static int ixl_set_vsi(struct ixl_softc *); 1335 static int ixl_get_link_status(struct ixl_softc *); 1336 static int ixl_set_link_status(struct ixl_softc *, 1337 const struct ixl_aq_desc *); 1338 static int ixl_add_macvlan(struct ixl_softc *, uint8_t *, uint16_t, 1339 uint16_t); 1340 static int ixl_remove_macvlan(struct ixl_softc *, uint8_t *, uint16_t, 1341 uint16_t); 1342 static void ixl_link_state_update(void *); 1343 static void ixl_arq(void *); 1344 static void ixl_hmc_pack(void *, const void *, 1345 const struct ixl_hmc_pack *, unsigned int); 1346 1347 static int ixl_get_sffpage(struct ixl_softc *, struct if_sffpage *); 1348 static int ixl_sff_get_byte(struct ixl_softc *, uint8_t, uint32_t, 1349 uint8_t *); 1350 static int ixl_sff_set_byte(struct ixl_softc *, uint8_t, uint32_t, 1351 uint8_t); 1352 1353 static int ixl_match(struct device *, void *, void *); 1354 static void ixl_attach(struct device *, struct device *, void *); 1355 1356 static void ixl_media_add(struct ixl_softc *, uint64_t); 1357 static int ixl_media_change(struct ifnet *); 1358 static void ixl_media_status(struct ifnet *, struct ifmediareq *); 1359 static void ixl_watchdog(struct ifnet *); 1360 static int ixl_ioctl(struct ifnet *, u_long, caddr_t); 1361 static void ixl_start(struct ifqueue *); 1362 static int ixl_intr0(void *); 1363 static int ixl_intr_vector(void *); 1364 static int ixl_up(struct ixl_softc *); 1365 static int ixl_down(struct ixl_softc *); 1366 static int ixl_iff(struct ixl_softc *); 1367 1368 static struct ixl_tx_ring * 1369 ixl_txr_alloc(struct ixl_softc *, unsigned int); 1370 static void ixl_txr_qdis(struct ixl_softc *, struct ixl_tx_ring *, int); 1371 static void ixl_txr_config(struct ixl_softc *, struct ixl_tx_ring *); 1372 static int ixl_txr_enabled(struct ixl_softc *, struct ixl_tx_ring *); 1373 static int ixl_txr_disabled(struct ixl_softc *, struct ixl_tx_ring *); 1374 static void ixl_txr_unconfig(struct ixl_softc *, struct ixl_tx_ring *); 1375 static void ixl_txr_clean(struct ixl_softc *, struct ixl_tx_ring *); 1376 static void ixl_txr_free(struct ixl_softc *, struct ixl_tx_ring *); 1377 static int ixl_txeof(struct ixl_softc *, struct ixl_tx_ring *); 1378 1379 static struct ixl_rx_ring * 1380 ixl_rxr_alloc(struct ixl_softc *, unsigned int); 1381 static void ixl_rxr_config(struct ixl_softc *, struct ixl_rx_ring *); 1382 static int ixl_rxr_enabled(struct ixl_softc *, struct ixl_rx_ring *); 1383 static int ixl_rxr_disabled(struct ixl_softc *, struct ixl_rx_ring *); 1384 static void ixl_rxr_unconfig(struct ixl_softc *, struct ixl_rx_ring *); 1385 static void ixl_rxr_clean(struct ixl_softc *, struct ixl_rx_ring *); 1386 static void ixl_rxr_free(struct ixl_softc *, struct ixl_rx_ring *); 1387 static int ixl_rxeof(struct ixl_softc *, struct ixl_rx_ring *); 1388 static void ixl_rxfill(struct ixl_softc *, struct ixl_rx_ring *); 1389 static void ixl_rxrefill(void *); 1390 static int ixl_rxrinfo(struct ixl_softc *, struct if_rxrinfo *); 1391 1392 #if NKSTAT > 0 1393 static void ixl_kstat_attach(struct ixl_softc *); 1394 #endif 1395 1396 struct cfdriver ixl_cd = { 1397 NULL, 1398 "ixl", 1399 DV_IFNET, 1400 }; 1401 1402 struct cfattach ixl_ca = { 1403 sizeof(struct ixl_softc), 1404 ixl_match, 1405 ixl_attach, 1406 }; 1407 1408 static const struct ixl_phy_type ixl_phy_type_map[] = { 1409 { 1ULL << IXL_PHY_TYPE_SGMII, IFM_1000_SGMII }, 1410 { 1ULL << IXL_PHY_TYPE_1000BASE_KX, IFM_1000_KX }, 1411 { 1ULL << IXL_PHY_TYPE_10GBASE_KX4, IFM_10G_KX4 }, 1412 { 1ULL << IXL_PHY_TYPE_10GBASE_KR, IFM_10G_KR }, 1413 { 1ULL << IXL_PHY_TYPE_40GBASE_KR4, IFM_40G_KR4 }, 1414 { 1ULL << IXL_PHY_TYPE_XAUI | 1415 1ULL << IXL_PHY_TYPE_XFI, IFM_10G_CX4 }, 1416 { 1ULL << IXL_PHY_TYPE_SFI, IFM_10G_SFI }, 1417 { 1ULL << IXL_PHY_TYPE_XLAUI | 1418 1ULL << IXL_PHY_TYPE_XLPPI, IFM_40G_XLPPI }, 1419 { 1ULL << IXL_PHY_TYPE_40GBASE_CR4_CU | 1420 1ULL << IXL_PHY_TYPE_40GBASE_CR4, IFM_40G_CR4 }, 1421 { 1ULL << IXL_PHY_TYPE_10GBASE_CR1_CU | 1422 1ULL << IXL_PHY_TYPE_10GBASE_CR1, IFM_10G_CR1 }, 1423 { 1ULL << IXL_PHY_TYPE_10GBASE_AOC, IFM_10G_AOC }, 1424 { 1ULL << IXL_PHY_TYPE_40GBASE_AOC, IFM_40G_AOC }, 1425 { 1ULL << IXL_PHY_TYPE_100BASE_TX, IFM_100_TX }, 1426 { 1ULL << IXL_PHY_TYPE_1000BASE_T_OPTICAL | 1427 1ULL << IXL_PHY_TYPE_1000BASE_T, IFM_1000_T }, 1428 { 1ULL << IXL_PHY_TYPE_10GBASE_T, IFM_10G_T }, 1429 { 1ULL << IXL_PHY_TYPE_10GBASE_SR, IFM_10G_SR }, 1430 { 1ULL << IXL_PHY_TYPE_10GBASE_LR, IFM_10G_LR }, 1431 { 1ULL << IXL_PHY_TYPE_10GBASE_SFPP_CU, IFM_10G_SFP_CU }, 1432 { 1ULL << IXL_PHY_TYPE_40GBASE_SR4, IFM_40G_SR4 }, 1433 { 1ULL << IXL_PHY_TYPE_40GBASE_LR4, IFM_40G_LR4 }, 1434 { 1ULL << IXL_PHY_TYPE_1000BASE_SX, IFM_1000_SX }, 1435 { 1ULL << IXL_PHY_TYPE_1000BASE_LX, IFM_1000_LX }, 1436 { 1ULL << IXL_PHY_TYPE_20GBASE_KR2, IFM_20G_KR2 }, 1437 { 1ULL << IXL_PHY_TYPE_25GBASE_KR, IFM_25G_KR }, 1438 { 1ULL << IXL_PHY_TYPE_25GBASE_CR, IFM_25G_CR }, 1439 { 1ULL << IXL_PHY_TYPE_25GBASE_SR, IFM_25G_SR }, 1440 { 1ULL << IXL_PHY_TYPE_25GBASE_LR, IFM_25G_LR }, 1441 { 1ULL << IXL_PHY_TYPE_25GBASE_AOC, IFM_25G_AOC }, 1442 { 1ULL << IXL_PHY_TYPE_25GBASE_ACC, IFM_25G_CR }, 1443 }; 1444 1445 static const struct ixl_speed_type ixl_speed_type_map[] = { 1446 { IXL_AQ_LINK_SPEED_40GB, IF_Gbps(40) }, 1447 { IXL_AQ_LINK_SPEED_25GB, IF_Gbps(25) }, 1448 { IXL_AQ_LINK_SPEED_10GB, IF_Gbps(10) }, 1449 { IXL_AQ_LINK_SPEED_1GB, IF_Gbps(1) }, 1450 }; 1451 1452 static const struct ixl_aq_regs ixl_pf_aq_regs = { 1453 .atq_tail = I40E_PF_ATQT, 1454 .atq_tail_mask = I40E_PF_ATQT_ATQT_MASK, 1455 .atq_head = I40E_PF_ATQH, 1456 .atq_head_mask = I40E_PF_ATQH_ATQH_MASK, 1457 .atq_len = I40E_PF_ATQLEN, 1458 .atq_bal = I40E_PF_ATQBAL, 1459 .atq_bah = I40E_PF_ATQBAH, 1460 .atq_len_enable = I40E_PF_ATQLEN_ATQENABLE_MASK, 1461 1462 .arq_tail = I40E_PF_ARQT, 1463 .arq_tail_mask = I40E_PF_ARQT_ARQT_MASK, 1464 .arq_head = I40E_PF_ARQH, 1465 .arq_head_mask = I40E_PF_ARQH_ARQH_MASK, 1466 .arq_len = I40E_PF_ARQLEN, 1467 .arq_bal = I40E_PF_ARQBAL, 1468 .arq_bah = I40E_PF_ARQBAH, 1469 .arq_len_enable = I40E_PF_ARQLEN_ARQENABLE_MASK, 1470 }; 1471 1472 #define ixl_rd(_s, _r) \ 1473 bus_space_read_4((_s)->sc_memt, (_s)->sc_memh, (_r)) 1474 #define ixl_wr(_s, _r, _v) \ 1475 bus_space_write_4((_s)->sc_memt, (_s)->sc_memh, (_r), (_v)) 1476 #define ixl_barrier(_s, _r, _l, _o) \ 1477 bus_space_barrier((_s)->sc_memt, (_s)->sc_memh, (_r), (_l), (_o)) 1478 #define ixl_intr_enable(_s) \ 1479 ixl_wr((_s), I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_INTENA_MASK | \ 1480 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | \ 1481 (IXL_NOITR << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)) 1482 1483 #define ixl_nqueues(_sc) (1 << (_sc)->sc_nqueues) 1484 1485 #ifdef __LP64__ 1486 #define ixl_dmamem_hi(_ixm) (uint32_t)(IXL_DMA_DVA(_ixm) >> 32) 1487 #else 1488 #define ixl_dmamem_hi(_ixm) 0 1489 #endif 1490 1491 #define ixl_dmamem_lo(_ixm) (uint32_t)IXL_DMA_DVA(_ixm) 1492 1493 static inline void 1494 ixl_aq_dva(struct ixl_aq_desc *iaq, bus_addr_t addr) 1495 { 1496 #ifdef __LP64__ 1497 htolem32(&iaq->iaq_param[2], addr >> 32); 1498 #else 1499 iaq->iaq_param[2] = htole32(0); 1500 #endif 1501 htolem32(&iaq->iaq_param[3], addr); 1502 } 1503 1504 #if _BYTE_ORDER == _BIG_ENDIAN 1505 #define HTOLE16(_x) (uint16_t)(((_x) & 0xff) << 8 | ((_x) & 0xff00) >> 8) 1506 #else 1507 #define HTOLE16(_x) (_x) 1508 #endif 1509 1510 static struct rwlock ixl_sff_lock = RWLOCK_INITIALIZER("ixlsff"); 1511 1512 /* deal with differences between chips */ 1513 1514 struct ixl_chip { 1515 uint64_t ic_rss_hena; 1516 uint32_t (*ic_rd_ctl)(struct ixl_softc *, uint32_t); 1517 void (*ic_wr_ctl)(struct ixl_softc *, uint32_t, 1518 uint32_t); 1519 1520 int (*ic_set_rss_key)(struct ixl_softc *, 1521 const struct ixl_rss_key *); 1522 int (*ic_set_rss_lut)(struct ixl_softc *, 1523 const struct ixl_rss_lut_128 *); 1524 }; 1525 1526 static inline uint64_t 1527 ixl_rss_hena(struct ixl_softc *sc) 1528 { 1529 return (sc->sc_chip->ic_rss_hena); 1530 } 1531 1532 static inline uint32_t 1533 ixl_rd_ctl(struct ixl_softc *sc, uint32_t r) 1534 { 1535 return ((*sc->sc_chip->ic_rd_ctl)(sc, r)); 1536 } 1537 1538 static inline void 1539 ixl_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 1540 { 1541 (*sc->sc_chip->ic_wr_ctl)(sc, r, v); 1542 } 1543 1544 static inline int 1545 ixl_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 1546 { 1547 return ((*sc->sc_chip->ic_set_rss_key)(sc, rsskey)); 1548 } 1549 1550 static inline int 1551 ixl_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 1552 { 1553 return ((*sc->sc_chip->ic_set_rss_lut)(sc, lut)); 1554 } 1555 1556 /* 710 chip specifics */ 1557 1558 static uint32_t ixl_710_rd_ctl(struct ixl_softc *, uint32_t); 1559 static void ixl_710_wr_ctl(struct ixl_softc *, uint32_t, uint32_t); 1560 static int ixl_710_set_rss_key(struct ixl_softc *, 1561 const struct ixl_rss_key *); 1562 static int ixl_710_set_rss_lut(struct ixl_softc *, 1563 const struct ixl_rss_lut_128 *); 1564 1565 static const struct ixl_chip ixl_710 = { 1566 .ic_rss_hena = IXL_RSS_HENA_BASE_710, 1567 .ic_rd_ctl = ixl_710_rd_ctl, 1568 .ic_wr_ctl = ixl_710_wr_ctl, 1569 .ic_set_rss_key = ixl_710_set_rss_key, 1570 .ic_set_rss_lut = ixl_710_set_rss_lut, 1571 }; 1572 1573 /* 722 chip specifics */ 1574 1575 static uint32_t ixl_722_rd_ctl(struct ixl_softc *, uint32_t); 1576 static void ixl_722_wr_ctl(struct ixl_softc *, uint32_t, uint32_t); 1577 static int ixl_722_set_rss_key(struct ixl_softc *, 1578 const struct ixl_rss_key *); 1579 static int ixl_722_set_rss_lut(struct ixl_softc *, 1580 const struct ixl_rss_lut_128 *); 1581 1582 static const struct ixl_chip ixl_722 = { 1583 .ic_rss_hena = IXL_RSS_HENA_BASE_722, 1584 .ic_rd_ctl = ixl_722_rd_ctl, 1585 .ic_wr_ctl = ixl_722_wr_ctl, 1586 .ic_set_rss_key = ixl_722_set_rss_key, 1587 .ic_set_rss_lut = ixl_722_set_rss_lut, 1588 }; 1589 1590 /* 1591 * 710 chips using an older firmware/API use the same ctl ops as 1592 * 722 chips. or 722 chips use the same ctl ops as 710 chips in early 1593 * firmware/API versions? 1594 */ 1595 1596 static const struct ixl_chip ixl_710_decrepit = { 1597 .ic_rss_hena = IXL_RSS_HENA_BASE_710, 1598 .ic_rd_ctl = ixl_722_rd_ctl, 1599 .ic_wr_ctl = ixl_722_wr_ctl, 1600 .ic_set_rss_key = ixl_710_set_rss_key, 1601 .ic_set_rss_lut = ixl_710_set_rss_lut, 1602 }; 1603 1604 /* driver code */ 1605 1606 struct ixl_device { 1607 const struct ixl_chip *id_chip; 1608 pci_vendor_id_t id_vid; 1609 pci_product_id_t id_pid; 1610 }; 1611 1612 static const struct ixl_device ixl_devices[] = { 1613 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_SFP }, 1614 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_40G_BP }, 1615 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BP, }, 1616 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_1 }, 1617 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_QSFP_2 }, 1618 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_QSFP }, 1619 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_10G_BASET }, 1620 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_1 }, 1621 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XL710_20G_BP_2 }, 1622 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X710_T4_10G }, 1623 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_BP }, 1624 { &ixl_710, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_XXV710_25G_SFP28, }, 1625 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_KX }, 1626 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_QSFP }, 1627 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_SFP_1 }, 1628 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_1G }, 1629 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_T }, 1630 { &ixl_722, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_X722_10G_SFP_2 }, 1631 }; 1632 1633 static const struct ixl_device * 1634 ixl_device_lookup(struct pci_attach_args *pa) 1635 { 1636 pci_vendor_id_t vid = PCI_VENDOR(pa->pa_id); 1637 pci_product_id_t pid = PCI_PRODUCT(pa->pa_id); 1638 const struct ixl_device *id; 1639 unsigned int i; 1640 1641 for (i = 0; i < nitems(ixl_devices); i++) { 1642 id = &ixl_devices[i]; 1643 if (id->id_vid == vid && id->id_pid == pid) 1644 return (id); 1645 } 1646 1647 return (NULL); 1648 } 1649 1650 static int 1651 ixl_match(struct device *parent, void *match, void *aux) 1652 { 1653 return (ixl_device_lookup(aux) != NULL); 1654 } 1655 1656 void 1657 ixl_attach(struct device *parent, struct device *self, void *aux) 1658 { 1659 struct ixl_softc *sc = (struct ixl_softc *)self; 1660 struct ifnet *ifp = &sc->sc_ac.ac_if; 1661 struct pci_attach_args *pa = aux; 1662 pcireg_t memtype; 1663 uint32_t port, ari, func; 1664 uint64_t phy_types = 0; 1665 unsigned int nqueues, i; 1666 int tries; 1667 1668 rw_init(&sc->sc_cfg_lock, "ixlcfg"); 1669 1670 sc->sc_chip = ixl_device_lookup(pa)->id_chip; 1671 sc->sc_pc = pa->pa_pc; 1672 sc->sc_tag = pa->pa_tag; 1673 sc->sc_dmat = pa->pa_dmat; 1674 sc->sc_aq_regs = &ixl_pf_aq_regs; 1675 1676 sc->sc_nqueues = 0; /* 1 << 0 is 1 queue */ 1677 sc->sc_tx_ring_ndescs = 1024; 1678 sc->sc_rx_ring_ndescs = 1024; 1679 1680 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, IXL_PCIREG); 1681 if (pci_mapreg_map(pa, IXL_PCIREG, memtype, 0, 1682 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems, 0)) { 1683 printf(": unable to map registers\n"); 1684 return; 1685 } 1686 1687 sc->sc_base_queue = (ixl_rd(sc, I40E_PFLAN_QALLOC) & 1688 I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1689 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1690 1691 ixl_clear_hw(sc); 1692 if (ixl_pf_reset(sc) == -1) { 1693 /* error printed by ixl_pf_reset */ 1694 goto unmap; 1695 } 1696 1697 port = ixl_rd(sc, I40E_PFGEN_PORTNUM); 1698 port &= I40E_PFGEN_PORTNUM_PORT_NUM_MASK; 1699 port >>= I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 1700 sc->sc_port = port; 1701 printf(": port %u", port); 1702 1703 ari = ixl_rd(sc, I40E_GLPCI_CAPSUP); 1704 ari &= I40E_GLPCI_CAPSUP_ARI_EN_MASK; 1705 ari >>= I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 1706 1707 func = ixl_rd(sc, I40E_PF_FUNC_RID); 1708 sc->sc_pf_id = func & (ari ? 0xff : 0x7); 1709 1710 /* initialise the adminq */ 1711 1712 if (ixl_dmamem_alloc(sc, &sc->sc_atq, 1713 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1714 printf("\n" "%s: unable to allocate atq\n", DEVNAME(sc)); 1715 goto unmap; 1716 } 1717 1718 SIMPLEQ_INIT(&sc->sc_arq_idle); 1719 SIMPLEQ_INIT(&sc->sc_arq_live); 1720 if_rxr_init(&sc->sc_arq_ring, 2, IXL_AQ_NUM - 1); 1721 task_set(&sc->sc_arq_task, ixl_arq, sc); 1722 sc->sc_arq_cons = 0; 1723 sc->sc_arq_prod = 0; 1724 1725 if (ixl_dmamem_alloc(sc, &sc->sc_arq, 1726 sizeof(struct ixl_aq_desc) * IXL_AQ_NUM, IXL_AQ_ALIGN) != 0) { 1727 printf("\n" "%s: unable to allocate arq\n", DEVNAME(sc)); 1728 goto free_atq; 1729 } 1730 1731 if (!ixl_arq_fill(sc)) { 1732 printf("\n" "%s: unable to fill arq descriptors\n", 1733 DEVNAME(sc)); 1734 goto free_arq; 1735 } 1736 1737 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 1738 0, IXL_DMA_LEN(&sc->sc_atq), 1739 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1740 1741 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 1742 0, IXL_DMA_LEN(&sc->sc_arq), 1743 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1744 1745 for (tries = 0; tries < 10; tries++) { 1746 int rv; 1747 1748 sc->sc_atq_cons = 0; 1749 sc->sc_atq_prod = 0; 1750 1751 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 1752 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 1753 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 1754 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 1755 1756 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 1757 1758 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 1759 ixl_dmamem_lo(&sc->sc_atq)); 1760 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 1761 ixl_dmamem_hi(&sc->sc_atq)); 1762 ixl_wr(sc, sc->sc_aq_regs->atq_len, 1763 sc->sc_aq_regs->atq_len_enable | IXL_AQ_NUM); 1764 1765 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 1766 ixl_dmamem_lo(&sc->sc_arq)); 1767 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 1768 ixl_dmamem_hi(&sc->sc_arq)); 1769 ixl_wr(sc, sc->sc_aq_regs->arq_len, 1770 sc->sc_aq_regs->arq_len_enable | IXL_AQ_NUM); 1771 1772 rv = ixl_get_version(sc); 1773 if (rv == 0) 1774 break; 1775 if (rv != ETIMEDOUT) { 1776 printf(", unable to get firmware version\n"); 1777 goto shutdown; 1778 } 1779 1780 delaymsec(100); 1781 } 1782 1783 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 1784 1785 if (ixl_pxe_clear(sc) != 0) { 1786 /* error printed by ixl_pxe_clear */ 1787 goto shutdown; 1788 } 1789 1790 if (ixl_get_mac(sc) != 0) { 1791 /* error printed by ixl_get_mac */ 1792 goto shutdown; 1793 } 1794 1795 if (pci_intr_map_msix(pa, 0, &sc->sc_ih) == 0) { 1796 int nmsix = pci_intr_msix_count(pa->pa_pc, pa->pa_tag); 1797 if (nmsix > 1) { /* we used 1 (the 0th) for the adminq */ 1798 nmsix--; 1799 1800 sc->sc_intrmap = intrmap_create(&sc->sc_dev, 1801 nmsix, IXL_MAX_VECTORS, INTRMAP_POWEROF2); 1802 nqueues = intrmap_count(sc->sc_intrmap); 1803 KASSERT(nqueues > 0); 1804 KASSERT(powerof2(nqueues)); 1805 sc->sc_nqueues = fls(nqueues) - 1; 1806 } 1807 } else { 1808 if (pci_intr_map_msi(pa, &sc->sc_ih) != 0 && 1809 pci_intr_map(pa, &sc->sc_ih) != 0) { 1810 printf(", unable to map interrupt\n"); 1811 goto shutdown; 1812 } 1813 } 1814 1815 nqueues = ixl_nqueues(sc); 1816 1817 printf(", %s, %d queue%s, address %s\n", 1818 pci_intr_string(sc->sc_pc, sc->sc_ih), ixl_nqueues(sc), 1819 (nqueues > 1 ? "s" : ""), 1820 ether_sprintf(sc->sc_ac.ac_enaddr)); 1821 1822 if (ixl_hmc(sc) != 0) { 1823 /* error printed by ixl_hmc */ 1824 goto shutdown; 1825 } 1826 1827 if (ixl_lldp_shut(sc) != 0) { 1828 /* error printed by ixl_lldp_shut */ 1829 goto free_hmc; 1830 } 1831 1832 if (ixl_phy_mask_ints(sc) != 0) { 1833 /* error printed by ixl_phy_mask_ints */ 1834 goto free_hmc; 1835 } 1836 1837 if (ixl_restart_an(sc) != 0) { 1838 /* error printed by ixl_restart_an */ 1839 goto free_hmc; 1840 } 1841 1842 if (ixl_get_switch_config(sc) != 0) { 1843 /* error printed by ixl_get_switch_config */ 1844 goto free_hmc; 1845 } 1846 1847 if (ixl_get_phy_types(sc, &phy_types) != 0) { 1848 /* error printed by ixl_get_phy_abilities */ 1849 goto free_hmc; 1850 } 1851 1852 if (ixl_get_link_status(sc) != 0) { 1853 /* error printed by ixl_get_link_status */ 1854 goto free_hmc; 1855 } 1856 1857 if (ixl_dmamem_alloc(sc, &sc->sc_scratch, 1858 sizeof(struct ixl_aq_vsi_data), 8) != 0) { 1859 printf("%s: unable to allocate scratch buffer\n", DEVNAME(sc)); 1860 goto free_hmc; 1861 } 1862 1863 if (ixl_get_vsi(sc) != 0) { 1864 /* error printed by ixl_get_vsi */ 1865 goto free_hmc; 1866 } 1867 1868 if (ixl_set_vsi(sc) != 0) { 1869 /* error printed by ixl_set_vsi */ 1870 goto free_scratch; 1871 } 1872 1873 sc->sc_ihc = pci_intr_establish(sc->sc_pc, sc->sc_ih, 1874 IPL_NET | IPL_MPSAFE, ixl_intr0, sc, DEVNAME(sc)); 1875 if (sc->sc_ihc == NULL) { 1876 printf("%s: unable to establish interrupt handler\n", 1877 DEVNAME(sc)); 1878 goto free_scratch; 1879 } 1880 1881 sc->sc_vectors = mallocarray(sizeof(*sc->sc_vectors), nqueues, 1882 M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 1883 if (sc->sc_vectors == NULL) { 1884 printf("%s: unable to allocate vectors\n", DEVNAME(sc)); 1885 goto free_scratch; 1886 } 1887 1888 for (i = 0; i < nqueues; i++) { 1889 struct ixl_vector *iv = &sc->sc_vectors[i]; 1890 iv->iv_sc = sc; 1891 iv->iv_qid = i; 1892 snprintf(iv->iv_name, sizeof(iv->iv_name), 1893 "%s:%u", DEVNAME(sc), i); /* truncated? */ 1894 } 1895 1896 if (sc->sc_intrmap) { 1897 for (i = 0; i < nqueues; i++) { 1898 struct ixl_vector *iv = &sc->sc_vectors[i]; 1899 pci_intr_handle_t ih; 1900 int v = i + 1; /* 0 is used for adminq */ 1901 1902 if (pci_intr_map_msix(pa, v, &ih)) { 1903 printf("%s: unable to map msi-x vector %d\n", 1904 DEVNAME(sc), v); 1905 goto free_vectors; 1906 } 1907 1908 iv->iv_ihc = pci_intr_establish_cpu(sc->sc_pc, ih, 1909 IPL_NET | IPL_MPSAFE, 1910 intrmap_cpu(sc->sc_intrmap, i), 1911 ixl_intr_vector, iv, iv->iv_name); 1912 if (iv->iv_ihc == NULL) { 1913 printf("%s: unable to establish interrupt %d\n", 1914 DEVNAME(sc), v); 1915 goto free_vectors; 1916 } 1917 1918 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), 1919 I40E_PFINT_DYN_CTLN_INTENA_MASK | 1920 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 1921 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 1922 } 1923 } 1924 1925 /* fixup the chip ops for older fw releases */ 1926 if (sc->sc_chip == &ixl_710 && 1927 sc->sc_api_major == 1 && sc->sc_api_minor < 5) 1928 sc->sc_chip = &ixl_710_decrepit; 1929 1930 ifp->if_softc = sc; 1931 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1932 ifp->if_xflags = IFXF_MPSAFE; 1933 ifp->if_ioctl = ixl_ioctl; 1934 ifp->if_qstart = ixl_start; 1935 ifp->if_watchdog = ixl_watchdog; 1936 ifp->if_hardmtu = IXL_HARDMTU; 1937 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 1938 ifq_set_maxlen(&ifp->if_snd, sc->sc_tx_ring_ndescs); 1939 1940 ifp->if_capabilities = IFCAP_VLAN_MTU; 1941 #if 0 1942 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1943 ifp->if_capabilities |= IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | 1944 IFCAP_CSUM_UDPv4; 1945 #endif 1946 1947 ifmedia_init(&sc->sc_media, 0, ixl_media_change, ixl_media_status); 1948 1949 ixl_media_add(sc, phy_types); 1950 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); 1951 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); 1952 1953 if_attach(ifp); 1954 ether_ifattach(ifp); 1955 1956 if_attach_queues(ifp, nqueues); 1957 if_attach_iqueues(ifp, nqueues); 1958 1959 mtx_init(&sc->sc_link_state_mtx, IPL_NET); 1960 task_set(&sc->sc_link_state_task, ixl_link_state_update, sc); 1961 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 1962 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | 1963 I40E_PFINT_ICR0_ENA_ADMINQ_MASK); 1964 ixl_wr(sc, I40E_PFINT_STAT_CTL0, 1965 IXL_NOITR << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT); 1966 1967 /* remove default mac filter and replace it so we can see vlans */ 1968 ixl_remove_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 0); 1969 ixl_remove_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 1970 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 1971 ixl_add_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 1972 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1973 ixl_add_macvlan(sc, etherbroadcastaddr, 0, 1974 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 1975 memcpy(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 1976 1977 ixl_intr_enable(sc); 1978 1979 #if NKSTAT > 0 1980 ixl_kstat_attach(sc); 1981 #endif 1982 1983 return; 1984 free_vectors: 1985 if (sc->sc_intrmap != NULL) { 1986 for (i = 0; i < nqueues; i++) { 1987 struct ixl_vector *iv = &sc->sc_vectors[i]; 1988 if (iv->iv_ihc == NULL) 1989 continue; 1990 pci_intr_disestablish(sc->sc_pc, iv->iv_ihc); 1991 } 1992 } 1993 free(sc->sc_vectors, M_DEVBUF, nqueues * sizeof(*sc->sc_vectors)); 1994 free_scratch: 1995 ixl_dmamem_free(sc, &sc->sc_scratch); 1996 free_hmc: 1997 ixl_hmc_free(sc); 1998 shutdown: 1999 ixl_wr(sc, sc->sc_aq_regs->atq_head, 0); 2000 ixl_wr(sc, sc->sc_aq_regs->arq_head, 0); 2001 ixl_wr(sc, sc->sc_aq_regs->atq_tail, 0); 2002 ixl_wr(sc, sc->sc_aq_regs->arq_tail, 0); 2003 2004 ixl_wr(sc, sc->sc_aq_regs->atq_bal, 0); 2005 ixl_wr(sc, sc->sc_aq_regs->atq_bah, 0); 2006 ixl_wr(sc, sc->sc_aq_regs->atq_len, 0); 2007 2008 ixl_wr(sc, sc->sc_aq_regs->arq_bal, 0); 2009 ixl_wr(sc, sc->sc_aq_regs->arq_bah, 0); 2010 ixl_wr(sc, sc->sc_aq_regs->arq_len, 0); 2011 2012 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 2013 0, IXL_DMA_LEN(&sc->sc_arq), 2014 BUS_DMASYNC_POSTREAD); 2015 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 2016 0, IXL_DMA_LEN(&sc->sc_atq), 2017 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2018 2019 ixl_arq_unfill(sc); 2020 2021 free_arq: 2022 ixl_dmamem_free(sc, &sc->sc_arq); 2023 free_atq: 2024 ixl_dmamem_free(sc, &sc->sc_atq); 2025 unmap: 2026 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems); 2027 sc->sc_mems = 0; 2028 2029 if (sc->sc_intrmap != NULL) 2030 intrmap_destroy(sc->sc_intrmap); 2031 } 2032 2033 static void 2034 ixl_media_add(struct ixl_softc *sc, uint64_t phy_types) 2035 { 2036 struct ifmedia *ifm = &sc->sc_media; 2037 const struct ixl_phy_type *itype; 2038 unsigned int i; 2039 2040 for (i = 0; i < nitems(ixl_phy_type_map); i++) { 2041 itype = &ixl_phy_type_map[i]; 2042 2043 if (ISSET(phy_types, itype->phy_type)) 2044 ifmedia_add(ifm, IFM_ETHER | itype->ifm_type, 0, NULL); 2045 } 2046 } 2047 2048 static int 2049 ixl_media_change(struct ifnet *ifp) 2050 { 2051 /* ignore? */ 2052 return (EOPNOTSUPP); 2053 } 2054 2055 static void 2056 ixl_media_status(struct ifnet *ifp, struct ifmediareq *ifm) 2057 { 2058 struct ixl_softc *sc = ifp->if_softc; 2059 2060 NET_ASSERT_LOCKED(); 2061 2062 ifm->ifm_status = sc->sc_media_status; 2063 ifm->ifm_active = sc->sc_media_active; 2064 } 2065 2066 static void 2067 ixl_watchdog(struct ifnet *ifp) 2068 { 2069 2070 } 2071 2072 int 2073 ixl_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2074 { 2075 struct ixl_softc *sc = (struct ixl_softc *)ifp->if_softc; 2076 struct ifreq *ifr = (struct ifreq *)data; 2077 uint8_t addrhi[ETHER_ADDR_LEN], addrlo[ETHER_ADDR_LEN]; 2078 int aqerror, error = 0; 2079 2080 switch (cmd) { 2081 case SIOCSIFADDR: 2082 ifp->if_flags |= IFF_UP; 2083 /* FALLTHROUGH */ 2084 2085 case SIOCSIFFLAGS: 2086 if (ISSET(ifp->if_flags, IFF_UP)) { 2087 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2088 error = ENETRESET; 2089 else 2090 error = ixl_up(sc); 2091 } else { 2092 if (ISSET(ifp->if_flags, IFF_RUNNING)) 2093 error = ixl_down(sc); 2094 } 2095 break; 2096 2097 case SIOCGIFMEDIA: 2098 case SIOCSIFMEDIA: 2099 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2100 break; 2101 2102 case SIOCGIFRXR: 2103 error = ixl_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_data); 2104 break; 2105 2106 case SIOCADDMULTI: 2107 if (ether_addmulti(ifr, &sc->sc_ac) == ENETRESET) { 2108 error = ether_multiaddr(&ifr->ifr_addr, addrlo, addrhi); 2109 if (error != 0) 2110 return (error); 2111 2112 aqerror = ixl_add_macvlan(sc, addrlo, 0, 2113 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 2114 if (aqerror == IXL_AQ_RC_ENOSPC) { 2115 ether_delmulti(ifr, &sc->sc_ac); 2116 error = ENOSPC; 2117 } 2118 2119 if (sc->sc_ac.ac_multirangecnt > 0) { 2120 SET(ifp->if_flags, IFF_ALLMULTI); 2121 error = ENETRESET; 2122 } 2123 } 2124 break; 2125 2126 case SIOCDELMULTI: 2127 if (ether_delmulti(ifr, &sc->sc_ac) == ENETRESET) { 2128 error = ether_multiaddr(&ifr->ifr_addr, addrlo, addrhi); 2129 if (error != 0) 2130 return (error); 2131 2132 ixl_remove_macvlan(sc, addrlo, 0, 2133 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 2134 2135 if (ISSET(ifp->if_flags, IFF_ALLMULTI) && 2136 sc->sc_ac.ac_multirangecnt == 0) { 2137 CLR(ifp->if_flags, IFF_ALLMULTI); 2138 error = ENETRESET; 2139 } 2140 } 2141 break; 2142 2143 case SIOCGIFSFFPAGE: 2144 error = rw_enter(&ixl_sff_lock, RW_WRITE|RW_INTR); 2145 if (error != 0) 2146 break; 2147 2148 error = ixl_get_sffpage(sc, (struct if_sffpage *)data); 2149 rw_exit(&ixl_sff_lock); 2150 break; 2151 2152 default: 2153 error = ether_ioctl(ifp, &sc->sc_ac, cmd, data); 2154 break; 2155 } 2156 2157 if (error == ENETRESET) 2158 error = ixl_iff(sc); 2159 2160 return (error); 2161 } 2162 2163 static inline void * 2164 ixl_hmc_kva(struct ixl_softc *sc, unsigned int type, unsigned int i) 2165 { 2166 uint8_t *kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 2167 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 2168 2169 if (i >= e->hmc_count) 2170 return (NULL); 2171 2172 kva += e->hmc_base; 2173 kva += i * e->hmc_size; 2174 2175 return (kva); 2176 } 2177 2178 static inline size_t 2179 ixl_hmc_len(struct ixl_softc *sc, unsigned int type) 2180 { 2181 struct ixl_hmc_entry *e = &sc->sc_hmc_entries[type]; 2182 2183 return (e->hmc_size); 2184 } 2185 2186 static int 2187 ixl_configure_rss(struct ixl_softc *sc) 2188 { 2189 struct ixl_rss_key rsskey; 2190 struct ixl_rss_lut_128 lut; 2191 uint8_t *lute = (uint8_t *)&lut; 2192 uint64_t rss_hena; 2193 unsigned int i, nqueues; 2194 int error; 2195 2196 #if 0 2197 /* if we want to do a 512 entry LUT, do this. */ 2198 uint32_t v = ixl_rd_ctl(sc, I40E_PFQF_CTL_0); 2199 SET(v, I40E_PFQF_CTL_0_HASHLUTSIZE_MASK); 2200 ixl_wr_ctl(sc, I40E_PFQF_CTL_0, v); 2201 #endif 2202 2203 stoeplitz_to_key(&rsskey, sizeof(rsskey)); 2204 2205 nqueues = ixl_nqueues(sc); 2206 for (i = 0; i < sizeof(lut); i++) { 2207 /* 2208 * ixl must have a power of 2 rings, so using mod 2209 * to populate the table is fine. 2210 */ 2211 lute[i] = i % nqueues; 2212 } 2213 2214 error = ixl_set_rss_key(sc, &rsskey); 2215 if (error != 0) 2216 return (error); 2217 2218 rss_hena = (uint64_t)ixl_rd_ctl(sc, I40E_PFQF_HENA(0)); 2219 rss_hena |= (uint64_t)ixl_rd_ctl(sc, I40E_PFQF_HENA(1)) << 32; 2220 rss_hena |= ixl_rss_hena(sc); 2221 ixl_wr_ctl(sc, I40E_PFQF_HENA(0), rss_hena); 2222 ixl_wr_ctl(sc, I40E_PFQF_HENA(1), rss_hena >> 32); 2223 2224 error = ixl_set_rss_lut(sc, &lut); 2225 if (error != 0) 2226 return (error); 2227 2228 /* nothing to clena up :( */ 2229 2230 return (0); 2231 } 2232 2233 static int 2234 ixl_up(struct ixl_softc *sc) 2235 { 2236 struct ifnet *ifp = &sc->sc_ac.ac_if; 2237 struct ifqueue *ifq; 2238 struct ifiqueue *ifiq; 2239 struct ixl_vector *iv; 2240 struct ixl_rx_ring *rxr; 2241 struct ixl_tx_ring *txr; 2242 unsigned int nqueues, i; 2243 uint32_t reg; 2244 int rv = ENOMEM; 2245 2246 nqueues = ixl_nqueues(sc); 2247 2248 rw_enter_write(&sc->sc_cfg_lock); 2249 if (sc->sc_dead) { 2250 rw_exit_write(&sc->sc_cfg_lock); 2251 return (ENXIO); 2252 } 2253 2254 /* allocation is the only thing that can fail, so do it up front */ 2255 for (i = 0; i < nqueues; i++) { 2256 rxr = ixl_rxr_alloc(sc, i); 2257 if (rxr == NULL) 2258 goto free; 2259 2260 txr = ixl_txr_alloc(sc, i); 2261 if (txr == NULL) { 2262 ixl_rxr_free(sc, rxr); 2263 goto free; 2264 } 2265 2266 /* wire everything together */ 2267 iv = &sc->sc_vectors[i]; 2268 iv->iv_rxr = rxr; 2269 iv->iv_txr = txr; 2270 2271 ifq = ifp->if_ifqs[i]; 2272 ifq->ifq_softc = txr; 2273 txr->txr_ifq = ifq; 2274 2275 ifiq = ifp->if_iqs[i]; 2276 ifiq->ifiq_softc = rxr; 2277 rxr->rxr_ifiq = ifiq; 2278 } 2279 2280 /* XXX wait 50ms from completion of last RX queue disable */ 2281 2282 for (i = 0; i < nqueues; i++) { 2283 iv = &sc->sc_vectors[i]; 2284 rxr = iv->iv_rxr; 2285 txr = iv->iv_txr; 2286 2287 ixl_txr_qdis(sc, txr, 1); 2288 2289 ixl_rxr_config(sc, rxr); 2290 ixl_txr_config(sc, txr); 2291 2292 ixl_wr(sc, I40E_QTX_CTL(i), I40E_QTX_CTL_PF_QUEUE | 2293 (sc->sc_pf_id << I40E_QTX_CTL_PF_INDX_SHIFT)); 2294 2295 ixl_wr(sc, rxr->rxr_tail, 0); 2296 ixl_rxfill(sc, rxr); 2297 2298 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2299 SET(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2300 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2301 2302 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2303 SET(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2304 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2305 } 2306 2307 for (i = 0; i < nqueues; i++) { 2308 iv = &sc->sc_vectors[i]; 2309 rxr = iv->iv_rxr; 2310 txr = iv->iv_txr; 2311 2312 if (ixl_rxr_enabled(sc, rxr) != 0) 2313 goto down; 2314 2315 if (ixl_txr_enabled(sc, txr) != 0) 2316 goto down; 2317 } 2318 2319 ixl_configure_rss(sc); 2320 2321 SET(ifp->if_flags, IFF_RUNNING); 2322 2323 if (sc->sc_intrmap == NULL) { 2324 ixl_wr(sc, I40E_PFINT_LNKLST0, 2325 (I40E_INTR_NOTX_QUEUE << 2326 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) | 2327 (I40E_QUEUE_TYPE_RX << 2328 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2329 2330 ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), 2331 (I40E_INTR_NOTX_INTR << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2332 (I40E_ITR_INDEX_RX << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2333 (I40E_INTR_NOTX_RX_QUEUE << 2334 I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) | 2335 (I40E_INTR_NOTX_QUEUE << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2336 (I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 2337 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2338 2339 ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), 2340 (I40E_INTR_NOTX_INTR << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2341 (I40E_ITR_INDEX_TX << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2342 (I40E_INTR_NOTX_TX_QUEUE << 2343 I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) | 2344 (I40E_QUEUE_TYPE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2345 (I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 2346 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2347 } else { 2348 /* vector 0 has no queues */ 2349 ixl_wr(sc, I40E_PFINT_LNKLST0, 2350 I40E_QUEUE_TYPE_EOL << 2351 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT); 2352 2353 /* queue n is mapped to vector n+1 */ 2354 for (i = 0; i < nqueues; i++) { 2355 /* LNKLSTN(i) configures vector i+1 */ 2356 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), 2357 (i << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) | 2358 (I40E_QUEUE_TYPE_RX << 2359 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)); 2360 ixl_wr(sc, I40E_QINT_RQCTL(i), 2361 ((i+1) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | 2362 (I40E_ITR_INDEX_RX << 2363 I40E_QINT_RQCTL_ITR_INDX_SHIFT) | 2364 (i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | 2365 (I40E_QUEUE_TYPE_TX << 2366 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | 2367 I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2368 ixl_wr(sc, I40E_QINT_TQCTL(i), 2369 ((i+1) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | 2370 (I40E_ITR_INDEX_TX << 2371 I40E_QINT_TQCTL_ITR_INDX_SHIFT) | 2372 (I40E_QUEUE_TYPE_EOL << 2373 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | 2374 (I40E_QUEUE_TYPE_RX << 2375 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) | 2376 I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2377 2378 ixl_wr(sc, I40E_PFINT_ITRN(0, i), 0x7a); 2379 ixl_wr(sc, I40E_PFINT_ITRN(1, i), 0x7a); 2380 ixl_wr(sc, I40E_PFINT_ITRN(2, i), 0); 2381 } 2382 } 2383 2384 ixl_wr(sc, I40E_PFINT_ITR0(0), 0x7a); 2385 ixl_wr(sc, I40E_PFINT_ITR0(1), 0x7a); 2386 ixl_wr(sc, I40E_PFINT_ITR0(2), 0); 2387 2388 rw_exit_write(&sc->sc_cfg_lock); 2389 2390 return (ENETRESET); 2391 2392 free: 2393 for (i = 0; i < nqueues; i++) { 2394 iv = &sc->sc_vectors[i]; 2395 rxr = iv->iv_rxr; 2396 txr = iv->iv_txr; 2397 2398 if (rxr == NULL) { 2399 /* 2400 * tx and rx get set at the same time, so if one 2401 * is NULL, the other is too. 2402 */ 2403 continue; 2404 } 2405 2406 ixl_txr_free(sc, txr); 2407 ixl_rxr_free(sc, rxr); 2408 } 2409 rw_exit_write(&sc->sc_cfg_lock); 2410 return (rv); 2411 down: 2412 rw_exit_write(&sc->sc_cfg_lock); 2413 ixl_down(sc); 2414 return (ETIMEDOUT); 2415 } 2416 2417 static int 2418 ixl_iff(struct ixl_softc *sc) 2419 { 2420 struct ifnet *ifp = &sc->sc_ac.ac_if; 2421 struct ixl_atq iatq; 2422 struct ixl_aq_desc *iaq; 2423 struct ixl_aq_vsi_promisc_param *param; 2424 2425 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 2426 return (0); 2427 2428 memset(&iatq, 0, sizeof(iatq)); 2429 2430 iaq = &iatq.iatq_desc; 2431 iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC); 2432 2433 param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param; 2434 param->flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2435 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2436 if (ISSET(ifp->if_flags, IFF_PROMISC)) { 2437 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2438 IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2439 } else if (ISSET(ifp->if_flags, IFF_ALLMULTI)) { 2440 param->flags |= htole16(IXL_AQ_VSI_PROMISC_FLAG_MCAST); 2441 } 2442 param->valid_flags = htole16(IXL_AQ_VSI_PROMISC_FLAG_UCAST | 2443 IXL_AQ_VSI_PROMISC_FLAG_MCAST | IXL_AQ_VSI_PROMISC_FLAG_BCAST | 2444 IXL_AQ_VSI_PROMISC_FLAG_VLAN); 2445 param->seid = sc->sc_seid; 2446 2447 ixl_atq_exec(sc, &iatq, "ixliff"); 2448 2449 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) 2450 return (EIO); 2451 2452 if (memcmp(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) != 0) { 2453 ixl_remove_macvlan(sc, sc->sc_enaddr, 0, 2454 IXL_AQ_OP_REMOVE_MACVLAN_IGNORE_VLAN); 2455 ixl_add_macvlan(sc, sc->sc_ac.ac_enaddr, 0, 2456 IXL_AQ_OP_ADD_MACVLAN_IGNORE_VLAN); 2457 memcpy(sc->sc_enaddr, sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN); 2458 } 2459 return (0); 2460 } 2461 2462 static int 2463 ixl_down(struct ixl_softc *sc) 2464 { 2465 struct ifnet *ifp = &sc->sc_ac.ac_if; 2466 struct ixl_vector *iv; 2467 struct ixl_rx_ring *rxr; 2468 struct ixl_tx_ring *txr; 2469 unsigned int nqueues, i; 2470 uint32_t reg; 2471 int error = 0; 2472 2473 nqueues = ixl_nqueues(sc); 2474 2475 rw_enter_write(&sc->sc_cfg_lock); 2476 2477 CLR(ifp->if_flags, IFF_RUNNING); 2478 2479 NET_UNLOCK(); 2480 2481 /* mask interrupts */ 2482 reg = ixl_rd(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE)); 2483 CLR(reg, I40E_QINT_RQCTL_CAUSE_ENA_MASK); 2484 ixl_wr(sc, I40E_QINT_RQCTL(I40E_INTR_NOTX_QUEUE), reg); 2485 2486 reg = ixl_rd(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE)); 2487 CLR(reg, I40E_QINT_TQCTL_CAUSE_ENA_MASK); 2488 ixl_wr(sc, I40E_QINT_TQCTL(I40E_INTR_NOTX_QUEUE), reg); 2489 2490 ixl_wr(sc, I40E_PFINT_LNKLST0, I40E_QUEUE_TYPE_EOL); 2491 2492 /* make sure the no hw generated work is still in flight */ 2493 intr_barrier(sc->sc_ihc); 2494 if (sc->sc_intrmap != NULL) { 2495 for (i = 0; i < nqueues; i++) { 2496 iv = &sc->sc_vectors[i]; 2497 rxr = iv->iv_rxr; 2498 txr = iv->iv_txr; 2499 2500 ixl_txr_qdis(sc, txr, 0); 2501 2502 ifq_barrier(txr->txr_ifq); 2503 2504 timeout_del_barrier(&rxr->rxr_refill); 2505 2506 intr_barrier(iv->iv_ihc); 2507 } 2508 } 2509 2510 /* XXX wait at least 400 usec for all tx queues in one go */ 2511 delay(500); 2512 2513 for (i = 0; i < nqueues; i++) { 2514 reg = ixl_rd(sc, I40E_QTX_ENA(i)); 2515 CLR(reg, I40E_QTX_ENA_QENA_REQ_MASK); 2516 ixl_wr(sc, I40E_QTX_ENA(i), reg); 2517 2518 reg = ixl_rd(sc, I40E_QRX_ENA(i)); 2519 CLR(reg, I40E_QRX_ENA_QENA_REQ_MASK); 2520 ixl_wr(sc, I40E_QRX_ENA(i), reg); 2521 } 2522 2523 for (i = 0; i < nqueues; i++) { 2524 iv = &sc->sc_vectors[i]; 2525 rxr = iv->iv_rxr; 2526 txr = iv->iv_txr; 2527 2528 if (ixl_txr_disabled(sc, txr) != 0) 2529 goto die; 2530 2531 if (ixl_rxr_disabled(sc, rxr) != 0) 2532 goto die; 2533 } 2534 2535 for (i = 0; i < nqueues; i++) { 2536 iv = &sc->sc_vectors[i]; 2537 rxr = iv->iv_rxr; 2538 txr = iv->iv_txr; 2539 2540 ixl_txr_unconfig(sc, txr); 2541 ixl_rxr_unconfig(sc, rxr); 2542 2543 ixl_txr_clean(sc, txr); 2544 ixl_rxr_clean(sc, rxr); 2545 2546 ixl_txr_free(sc, txr); 2547 ixl_rxr_free(sc, rxr); 2548 2549 ifp->if_iqs[i]->ifiq_softc = NULL; 2550 ifp->if_ifqs[i]->ifq_softc = NULL; 2551 } 2552 2553 out: 2554 rw_exit_write(&sc->sc_cfg_lock); 2555 NET_LOCK(); 2556 return (error); 2557 die: 2558 sc->sc_dead = 1; 2559 log(LOG_CRIT, "%s: failed to shut down rings", DEVNAME(sc)); 2560 error = ETIMEDOUT; 2561 goto out; 2562 } 2563 2564 static struct ixl_tx_ring * 2565 ixl_txr_alloc(struct ixl_softc *sc, unsigned int qid) 2566 { 2567 struct ixl_tx_ring *txr; 2568 struct ixl_tx_map *maps, *txm; 2569 unsigned int i; 2570 2571 txr = malloc(sizeof(*txr), M_DEVBUF, M_WAITOK|M_CANFAIL); 2572 if (txr == NULL) 2573 return (NULL); 2574 2575 maps = mallocarray(sizeof(*maps), 2576 sc->sc_tx_ring_ndescs, M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 2577 if (maps == NULL) 2578 goto free; 2579 2580 if (ixl_dmamem_alloc(sc, &txr->txr_mem, 2581 sizeof(struct ixl_tx_desc) * sc->sc_tx_ring_ndescs, 2582 IXL_TX_QUEUE_ALIGN) != 0) 2583 goto freemap; 2584 2585 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2586 txm = &maps[i]; 2587 2588 if (bus_dmamap_create(sc->sc_dmat, 2589 IXL_HARDMTU, IXL_TX_PKT_DESCS, IXL_HARDMTU, 0, 2590 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 2591 &txm->txm_map) != 0) 2592 goto uncreate; 2593 2594 txm->txm_eop = -1; 2595 txm->txm_m = NULL; 2596 } 2597 2598 txr->txr_cons = txr->txr_prod = 0; 2599 txr->txr_maps = maps; 2600 2601 txr->txr_tail = I40E_QTX_TAIL(qid); 2602 txr->txr_qid = qid; 2603 2604 return (txr); 2605 2606 uncreate: 2607 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2608 txm = &maps[i]; 2609 2610 if (txm->txm_map == NULL) 2611 continue; 2612 2613 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2614 } 2615 2616 ixl_dmamem_free(sc, &txr->txr_mem); 2617 freemap: 2618 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_tx_ring_ndescs); 2619 free: 2620 free(txr, M_DEVBUF, sizeof(*txr)); 2621 return (NULL); 2622 } 2623 2624 static void 2625 ixl_txr_qdis(struct ixl_softc *sc, struct ixl_tx_ring *txr, int enable) 2626 { 2627 unsigned int qid; 2628 bus_size_t reg; 2629 uint32_t r; 2630 2631 qid = txr->txr_qid + sc->sc_base_queue; 2632 reg = I40E_GLLAN_TXPRE_QDIS(qid / 128); 2633 qid %= 128; 2634 2635 r = ixl_rd(sc, reg); 2636 CLR(r, I40E_GLLAN_TXPRE_QDIS_QINDX_MASK); 2637 SET(r, qid << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 2638 SET(r, enable ? I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK : 2639 I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK); 2640 ixl_wr(sc, reg, r); 2641 } 2642 2643 static void 2644 ixl_txr_config(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2645 { 2646 struct ixl_hmc_txq txq; 2647 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(&sc->sc_scratch); 2648 void *hmc; 2649 2650 memset(&txq, 0, sizeof(txq)); 2651 txq.head = htole16(0); 2652 txq.new_context = 1; 2653 htolem64(&txq.base, 2654 IXL_DMA_DVA(&txr->txr_mem) / IXL_HMC_TXQ_BASE_UNIT); 2655 txq.head_wb_ena = IXL_HMC_TXQ_DESC_WB; 2656 htolem16(&txq.qlen, sc->sc_tx_ring_ndescs); 2657 txq.tphrdesc_ena = 0; 2658 txq.tphrpacket_ena = 0; 2659 txq.tphwdesc_ena = 0; 2660 txq.rdylist = data->qs_handle[0]; 2661 2662 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2663 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2664 ixl_hmc_pack(hmc, &txq, ixl_hmc_pack_txq, nitems(ixl_hmc_pack_txq)); 2665 } 2666 2667 static void 2668 ixl_txr_unconfig(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2669 { 2670 void *hmc; 2671 2672 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_TX, txr->txr_qid); 2673 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_TX)); 2674 } 2675 2676 static void 2677 ixl_txr_clean(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2678 { 2679 struct ixl_tx_map *maps, *txm; 2680 bus_dmamap_t map; 2681 unsigned int i; 2682 2683 maps = txr->txr_maps; 2684 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2685 txm = &maps[i]; 2686 2687 if (txm->txm_m == NULL) 2688 continue; 2689 2690 map = txm->txm_map; 2691 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2692 BUS_DMASYNC_POSTWRITE); 2693 bus_dmamap_unload(sc->sc_dmat, map); 2694 2695 m_freem(txm->txm_m); 2696 txm->txm_m = NULL; 2697 } 2698 } 2699 2700 static int 2701 ixl_txr_enabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2702 { 2703 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2704 uint32_t reg; 2705 int i; 2706 2707 for (i = 0; i < 10; i++) { 2708 reg = ixl_rd(sc, ena); 2709 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK)) 2710 return (0); 2711 2712 delaymsec(10); 2713 } 2714 2715 return (ETIMEDOUT); 2716 } 2717 2718 static int 2719 ixl_txr_disabled(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2720 { 2721 bus_size_t ena = I40E_QTX_ENA(txr->txr_qid); 2722 uint32_t reg; 2723 int i; 2724 2725 for (i = 0; i < 20; i++) { 2726 reg = ixl_rd(sc, ena); 2727 if (ISSET(reg, I40E_QTX_ENA_QENA_STAT_MASK) == 0) 2728 return (0); 2729 2730 delaymsec(10); 2731 } 2732 2733 return (ETIMEDOUT); 2734 } 2735 2736 static void 2737 ixl_txr_free(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2738 { 2739 struct ixl_tx_map *maps, *txm; 2740 unsigned int i; 2741 2742 maps = txr->txr_maps; 2743 for (i = 0; i < sc->sc_tx_ring_ndescs; i++) { 2744 txm = &maps[i]; 2745 2746 bus_dmamap_destroy(sc->sc_dmat, txm->txm_map); 2747 } 2748 2749 ixl_dmamem_free(sc, &txr->txr_mem); 2750 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_tx_ring_ndescs); 2751 free(txr, M_DEVBUF, sizeof(*txr)); 2752 } 2753 2754 static inline int 2755 ixl_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf *m) 2756 { 2757 int error; 2758 2759 error = bus_dmamap_load_mbuf(dmat, map, m, 2760 BUS_DMA_STREAMING | BUS_DMA_NOWAIT); 2761 if (error != EFBIG) 2762 return (error); 2763 2764 error = m_defrag(m, M_DONTWAIT); 2765 if (error != 0) 2766 return (error); 2767 2768 return (bus_dmamap_load_mbuf(dmat, map, m, 2769 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)); 2770 } 2771 2772 static void 2773 ixl_start(struct ifqueue *ifq) 2774 { 2775 struct ifnet *ifp = ifq->ifq_if; 2776 struct ixl_softc *sc = ifp->if_softc; 2777 struct ixl_tx_ring *txr = ifq->ifq_softc; 2778 struct ixl_tx_desc *ring, *txd; 2779 struct ixl_tx_map *txm; 2780 bus_dmamap_t map; 2781 struct mbuf *m; 2782 uint64_t cmd; 2783 unsigned int prod, free, last, i; 2784 unsigned int mask; 2785 int post = 0; 2786 #if NBPFILTER > 0 2787 caddr_t if_bpf; 2788 #endif 2789 2790 if (!LINK_STATE_IS_UP(ifp->if_link_state)) { 2791 ifq_purge(ifq); 2792 return; 2793 } 2794 2795 prod = txr->txr_prod; 2796 free = txr->txr_cons; 2797 if (free <= prod) 2798 free += sc->sc_tx_ring_ndescs; 2799 free -= prod; 2800 2801 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2802 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTWRITE); 2803 2804 ring = IXL_DMA_KVA(&txr->txr_mem); 2805 mask = sc->sc_tx_ring_ndescs - 1; 2806 2807 for (;;) { 2808 if (free <= IXL_TX_PKT_DESCS) { 2809 ifq_set_oactive(ifq); 2810 break; 2811 } 2812 2813 m = ifq_dequeue(ifq); 2814 if (m == NULL) 2815 break; 2816 2817 txm = &txr->txr_maps[prod]; 2818 map = txm->txm_map; 2819 2820 if (ixl_load_mbuf(sc->sc_dmat, map, m) != 0) { 2821 ifq->ifq_errors++; 2822 m_freem(m); 2823 continue; 2824 } 2825 2826 bus_dmamap_sync(sc->sc_dmat, map, 0, 2827 map->dm_mapsize, BUS_DMASYNC_PREWRITE); 2828 2829 for (i = 0; i < map->dm_nsegs; i++) { 2830 txd = &ring[prod]; 2831 2832 cmd = (uint64_t)map->dm_segs[i].ds_len << 2833 IXL_TX_DESC_BSIZE_SHIFT; 2834 cmd |= IXL_TX_DESC_DTYPE_DATA | IXL_TX_DESC_CMD_ICRC; 2835 2836 htolem64(&txd->addr, map->dm_segs[i].ds_addr); 2837 htolem64(&txd->cmd, cmd); 2838 2839 last = prod; 2840 2841 prod++; 2842 prod &= mask; 2843 } 2844 cmd |= IXL_TX_DESC_CMD_EOP | IXL_TX_DESC_CMD_RS; 2845 htolem64(&txd->cmd, cmd); 2846 2847 txm->txm_m = m; 2848 txm->txm_eop = last; 2849 2850 #if NBPFILTER > 0 2851 if_bpf = ifp->if_bpf; 2852 if (if_bpf) 2853 bpf_mtap_ether(if_bpf, m, BPF_DIRECTION_OUT); 2854 #endif 2855 2856 free -= i; 2857 post = 1; 2858 } 2859 2860 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2861 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREWRITE); 2862 2863 if (post) { 2864 txr->txr_prod = prod; 2865 ixl_wr(sc, txr->txr_tail, prod); 2866 } 2867 } 2868 2869 static int 2870 ixl_txeof(struct ixl_softc *sc, struct ixl_tx_ring *txr) 2871 { 2872 struct ifqueue *ifq = txr->txr_ifq; 2873 struct ixl_tx_desc *ring, *txd; 2874 struct ixl_tx_map *txm; 2875 bus_dmamap_t map; 2876 unsigned int cons, prod, last; 2877 unsigned int mask; 2878 uint64_t dtype; 2879 int done = 0; 2880 2881 prod = txr->txr_prod; 2882 cons = txr->txr_cons; 2883 2884 if (cons == prod) 2885 return (0); 2886 2887 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2888 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_POSTREAD); 2889 2890 ring = IXL_DMA_KVA(&txr->txr_mem); 2891 mask = sc->sc_tx_ring_ndescs - 1; 2892 2893 do { 2894 txm = &txr->txr_maps[cons]; 2895 last = txm->txm_eop; 2896 txd = &ring[last]; 2897 2898 dtype = txd->cmd & htole64(IXL_TX_DESC_DTYPE_MASK); 2899 if (dtype != htole64(IXL_TX_DESC_DTYPE_DONE)) 2900 break; 2901 2902 map = txm->txm_map; 2903 2904 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 2905 BUS_DMASYNC_POSTWRITE); 2906 bus_dmamap_unload(sc->sc_dmat, map); 2907 m_freem(txm->txm_m); 2908 2909 txm->txm_m = NULL; 2910 txm->txm_eop = -1; 2911 2912 cons = last + 1; 2913 cons &= mask; 2914 2915 done = 1; 2916 } while (cons != prod); 2917 2918 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&txr->txr_mem), 2919 0, IXL_DMA_LEN(&txr->txr_mem), BUS_DMASYNC_PREREAD); 2920 2921 txr->txr_cons = cons; 2922 2923 //ixl_enable(sc, txr->txr_msix); 2924 2925 if (ifq_is_oactive(ifq)) 2926 ifq_restart(ifq); 2927 2928 return (done); 2929 } 2930 2931 static struct ixl_rx_ring * 2932 ixl_rxr_alloc(struct ixl_softc *sc, unsigned int qid) 2933 { 2934 struct ixl_rx_ring *rxr; 2935 struct ixl_rx_map *maps, *rxm; 2936 unsigned int i; 2937 2938 rxr = malloc(sizeof(*rxr), M_DEVBUF, M_WAITOK|M_CANFAIL); 2939 if (rxr == NULL) 2940 return (NULL); 2941 2942 maps = mallocarray(sizeof(*maps), 2943 sc->sc_rx_ring_ndescs, M_DEVBUF, M_WAITOK|M_CANFAIL|M_ZERO); 2944 if (maps == NULL) 2945 goto free; 2946 2947 if (ixl_dmamem_alloc(sc, &rxr->rxr_mem, 2948 sizeof(struct ixl_rx_rd_desc_16) * sc->sc_rx_ring_ndescs, 2949 IXL_RX_QUEUE_ALIGN) != 0) 2950 goto freemap; 2951 2952 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2953 rxm = &maps[i]; 2954 2955 if (bus_dmamap_create(sc->sc_dmat, 2956 IXL_HARDMTU, 1, IXL_HARDMTU, 0, 2957 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 2958 &rxm->rxm_map) != 0) 2959 goto uncreate; 2960 2961 rxm->rxm_m = NULL; 2962 } 2963 2964 rxr->rxr_sc = sc; 2965 if_rxr_init(&rxr->rxr_acct, 17, sc->sc_rx_ring_ndescs - 1); 2966 timeout_set(&rxr->rxr_refill, ixl_rxrefill, rxr); 2967 rxr->rxr_cons = rxr->rxr_prod = 0; 2968 rxr->rxr_m_head = NULL; 2969 rxr->rxr_m_tail = &rxr->rxr_m_head; 2970 rxr->rxr_maps = maps; 2971 2972 rxr->rxr_tail = I40E_QRX_TAIL(qid); 2973 rxr->rxr_qid = qid; 2974 2975 return (rxr); 2976 2977 uncreate: 2978 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 2979 rxm = &maps[i]; 2980 2981 if (rxm->rxm_map == NULL) 2982 continue; 2983 2984 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 2985 } 2986 2987 ixl_dmamem_free(sc, &rxr->rxr_mem); 2988 freemap: 2989 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_rx_ring_ndescs); 2990 free: 2991 free(rxr, M_DEVBUF, sizeof(*rxr)); 2992 return (NULL); 2993 } 2994 2995 static void 2996 ixl_rxr_clean(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 2997 { 2998 struct ixl_rx_map *maps, *rxm; 2999 bus_dmamap_t map; 3000 unsigned int i; 3001 3002 timeout_del_barrier(&rxr->rxr_refill); 3003 3004 maps = rxr->rxr_maps; 3005 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3006 rxm = &maps[i]; 3007 3008 if (rxm->rxm_m == NULL) 3009 continue; 3010 3011 map = rxm->rxm_map; 3012 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3013 BUS_DMASYNC_POSTWRITE); 3014 bus_dmamap_unload(sc->sc_dmat, map); 3015 3016 m_freem(rxm->rxm_m); 3017 rxm->rxm_m = NULL; 3018 } 3019 3020 m_freem(rxr->rxr_m_head); 3021 rxr->rxr_m_head = NULL; 3022 rxr->rxr_m_tail = &rxr->rxr_m_head; 3023 3024 rxr->rxr_prod = rxr->rxr_cons = 0; 3025 } 3026 3027 static int 3028 ixl_rxr_enabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3029 { 3030 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3031 uint32_t reg; 3032 int i; 3033 3034 for (i = 0; i < 10; i++) { 3035 reg = ixl_rd(sc, ena); 3036 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK)) 3037 return (0); 3038 3039 delaymsec(10); 3040 } 3041 3042 return (ETIMEDOUT); 3043 } 3044 3045 static int 3046 ixl_rxr_disabled(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3047 { 3048 bus_size_t ena = I40E_QRX_ENA(rxr->rxr_qid); 3049 uint32_t reg; 3050 int i; 3051 3052 for (i = 0; i < 20; i++) { 3053 reg = ixl_rd(sc, ena); 3054 if (ISSET(reg, I40E_QRX_ENA_QENA_STAT_MASK) == 0) 3055 return (0); 3056 3057 delaymsec(10); 3058 } 3059 3060 return (ETIMEDOUT); 3061 } 3062 3063 static void 3064 ixl_rxr_config(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3065 { 3066 struct ixl_hmc_rxq rxq; 3067 void *hmc; 3068 3069 memset(&rxq, 0, sizeof(rxq)); 3070 3071 rxq.head = htole16(0); 3072 htolem64(&rxq.base, 3073 IXL_DMA_DVA(&rxr->rxr_mem) / IXL_HMC_RXQ_BASE_UNIT); 3074 htolem16(&rxq.qlen, sc->sc_rx_ring_ndescs); 3075 rxq.dbuff = htole16(MCLBYTES / IXL_HMC_RXQ_DBUFF_UNIT); 3076 rxq.hbuff = 0; 3077 rxq.dtype = IXL_HMC_RXQ_DTYPE_NOSPLIT; 3078 rxq.dsize = IXL_HMC_RXQ_DSIZE_16; 3079 rxq.crcstrip = 1; 3080 rxq.l2sel = 0; 3081 rxq.showiv = 0; 3082 rxq.rxmax = htole16(IXL_HARDMTU); 3083 rxq.tphrdesc_ena = 0; 3084 rxq.tphwdesc_ena = 0; 3085 rxq.tphdata_ena = 0; 3086 rxq.tphhead_ena = 0; 3087 rxq.lrxqthresh = 0; 3088 rxq.prefena = 1; 3089 3090 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3091 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3092 ixl_hmc_pack(hmc, &rxq, ixl_hmc_pack_rxq, nitems(ixl_hmc_pack_rxq)); 3093 } 3094 3095 static void 3096 ixl_rxr_unconfig(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3097 { 3098 void *hmc; 3099 3100 hmc = ixl_hmc_kva(sc, IXL_HMC_LAN_RX, rxr->rxr_qid); 3101 memset(hmc, 0, ixl_hmc_len(sc, IXL_HMC_LAN_RX)); 3102 } 3103 3104 static void 3105 ixl_rxr_free(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3106 { 3107 struct ixl_rx_map *maps, *rxm; 3108 unsigned int i; 3109 3110 maps = rxr->rxr_maps; 3111 for (i = 0; i < sc->sc_rx_ring_ndescs; i++) { 3112 rxm = &maps[i]; 3113 3114 bus_dmamap_destroy(sc->sc_dmat, rxm->rxm_map); 3115 } 3116 3117 ixl_dmamem_free(sc, &rxr->rxr_mem); 3118 free(maps, M_DEVBUF, sizeof(*maps) * sc->sc_rx_ring_ndescs); 3119 free(rxr, M_DEVBUF, sizeof(*rxr)); 3120 } 3121 3122 static int 3123 ixl_rxeof(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3124 { 3125 struct ifiqueue *ifiq = rxr->rxr_ifiq; 3126 struct ifnet *ifp = &sc->sc_ac.ac_if; 3127 struct ixl_rx_wb_desc_16 *ring, *rxd; 3128 struct ixl_rx_map *rxm; 3129 bus_dmamap_t map; 3130 unsigned int cons, prod; 3131 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 3132 struct mbuf *m; 3133 uint64_t word; 3134 unsigned int len; 3135 unsigned int mask; 3136 int done = 0; 3137 3138 prod = rxr->rxr_prod; 3139 cons = rxr->rxr_cons; 3140 3141 if (cons == prod) 3142 return (0); 3143 3144 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3145 0, IXL_DMA_LEN(&rxr->rxr_mem), 3146 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3147 3148 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3149 mask = sc->sc_rx_ring_ndescs - 1; 3150 3151 do { 3152 rxd = &ring[cons]; 3153 3154 word = lemtoh64(&rxd->qword1); 3155 if (!ISSET(word, IXL_RX_DESC_DD)) 3156 break; 3157 3158 if_rxr_put(&rxr->rxr_acct, 1); 3159 3160 rxm = &rxr->rxr_maps[cons]; 3161 3162 map = rxm->rxm_map; 3163 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3164 BUS_DMASYNC_POSTREAD); 3165 bus_dmamap_unload(sc->sc_dmat, map); 3166 3167 m = rxm->rxm_m; 3168 rxm->rxm_m = NULL; 3169 3170 len = (word & IXL_RX_DESC_PLEN_MASK) >> IXL_RX_DESC_PLEN_SHIFT; 3171 m->m_len = len; 3172 m->m_pkthdr.len = 0; 3173 3174 m->m_next = NULL; 3175 *rxr->rxr_m_tail = m; 3176 rxr->rxr_m_tail = &m->m_next; 3177 3178 m = rxr->rxr_m_head; 3179 m->m_pkthdr.len += len; 3180 3181 if (ISSET(word, IXL_RX_DESC_EOP)) { 3182 if (!ISSET(word, 3183 IXL_RX_DESC_RXE | IXL_RX_DESC_OVERSIZE)) { 3184 if ((word & IXL_RX_DESC_FLTSTAT_MASK) == 3185 IXL_RX_DESC_FLTSTAT_RSS) { 3186 m->m_pkthdr.ph_flowid = 3187 lemtoh32(&rxd->filter_status); 3188 m->m_pkthdr.csum_flags |= M_FLOWID; 3189 } 3190 3191 ml_enqueue(&ml, m); 3192 } else { 3193 ifp->if_ierrors++; /* XXX */ 3194 m_freem(m); 3195 } 3196 3197 rxr->rxr_m_head = NULL; 3198 rxr->rxr_m_tail = &rxr->rxr_m_head; 3199 } 3200 3201 cons++; 3202 cons &= mask; 3203 3204 done = 1; 3205 } while (cons != prod); 3206 3207 if (done) { 3208 rxr->rxr_cons = cons; 3209 if (ifiq_input(ifiq, &ml)) 3210 if_rxr_livelocked(&rxr->rxr_acct); 3211 ixl_rxfill(sc, rxr); 3212 } 3213 3214 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&rxr->rxr_mem), 3215 0, IXL_DMA_LEN(&rxr->rxr_mem), 3216 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3217 3218 return (done); 3219 } 3220 3221 static void 3222 ixl_rxfill(struct ixl_softc *sc, struct ixl_rx_ring *rxr) 3223 { 3224 struct ixl_rx_rd_desc_16 *ring, *rxd; 3225 struct ixl_rx_map *rxm; 3226 bus_dmamap_t map; 3227 struct mbuf *m; 3228 unsigned int prod; 3229 unsigned int slots; 3230 unsigned int mask; 3231 int post = 0; 3232 3233 slots = if_rxr_get(&rxr->rxr_acct, sc->sc_rx_ring_ndescs); 3234 if (slots == 0) 3235 return; 3236 3237 prod = rxr->rxr_prod; 3238 3239 ring = IXL_DMA_KVA(&rxr->rxr_mem); 3240 mask = sc->sc_rx_ring_ndescs - 1; 3241 3242 do { 3243 rxm = &rxr->rxr_maps[prod]; 3244 3245 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES + ETHER_ALIGN); 3246 if (m == NULL) 3247 break; 3248 m->m_data += (m->m_ext.ext_size - (MCLBYTES + ETHER_ALIGN)); 3249 m->m_len = m->m_pkthdr.len = MCLBYTES + ETHER_ALIGN; 3250 3251 map = rxm->rxm_map; 3252 3253 if (bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 3254 BUS_DMA_NOWAIT) != 0) { 3255 m_freem(m); 3256 break; 3257 } 3258 3259 rxm->rxm_m = m; 3260 3261 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 3262 BUS_DMASYNC_PREREAD); 3263 3264 rxd = &ring[prod]; 3265 3266 htolem64(&rxd->paddr, map->dm_segs[0].ds_addr); 3267 rxd->haddr = htole64(0); 3268 3269 prod++; 3270 prod &= mask; 3271 3272 post = 1; 3273 } while (--slots); 3274 3275 if_rxr_put(&rxr->rxr_acct, slots); 3276 3277 if (if_rxr_inuse(&rxr->rxr_acct) == 0) 3278 timeout_add(&rxr->rxr_refill, 1); 3279 else if (post) { 3280 rxr->rxr_prod = prod; 3281 ixl_wr(sc, rxr->rxr_tail, prod); 3282 } 3283 } 3284 3285 void 3286 ixl_rxrefill(void *arg) 3287 { 3288 struct ixl_rx_ring *rxr = arg; 3289 struct ixl_softc *sc = rxr->rxr_sc; 3290 3291 ixl_rxfill(sc, rxr); 3292 } 3293 3294 static int 3295 ixl_rxrinfo(struct ixl_softc *sc, struct if_rxrinfo *ifri) 3296 { 3297 struct ifnet *ifp = &sc->sc_ac.ac_if; 3298 struct if_rxring_info *ifr; 3299 struct ixl_rx_ring *ring; 3300 int i, rv; 3301 3302 if (!ISSET(ifp->if_flags, IFF_RUNNING)) 3303 return (ENOTTY); 3304 3305 ifr = mallocarray(sizeof(*ifr), ixl_nqueues(sc), M_TEMP, 3306 M_WAITOK|M_CANFAIL|M_ZERO); 3307 if (ifr == NULL) 3308 return (ENOMEM); 3309 3310 for (i = 0; i < ixl_nqueues(sc); i++) { 3311 ring = ifp->if_iqs[i]->ifiq_softc; 3312 ifr[i].ifr_size = MCLBYTES; 3313 snprintf(ifr[i].ifr_name, sizeof(ifr[i].ifr_name), "%d", i); 3314 ifr[i].ifr_info = ring->rxr_acct; 3315 } 3316 3317 rv = if_rxr_info_ioctl(ifri, ixl_nqueues(sc), ifr); 3318 free(ifr, M_TEMP, ixl_nqueues(sc) * sizeof(*ifr)); 3319 3320 return (rv); 3321 } 3322 3323 static int 3324 ixl_intr0(void *xsc) 3325 { 3326 struct ixl_softc *sc = xsc; 3327 struct ifnet *ifp = &sc->sc_ac.ac_if; 3328 uint32_t icr; 3329 int rv = 0; 3330 3331 ixl_intr_enable(sc); 3332 icr = ixl_rd(sc, I40E_PFINT_ICR0); 3333 3334 if (ISSET(icr, I40E_PFINT_ICR0_ADMINQ_MASK)) { 3335 ixl_atq_done(sc); 3336 task_add(systq, &sc->sc_arq_task); 3337 rv = 1; 3338 } 3339 3340 if (ISSET(icr, I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK)) { 3341 task_add(systq, &sc->sc_link_state_task); 3342 rv = 1; 3343 } 3344 3345 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3346 struct ixl_vector *iv = sc->sc_vectors; 3347 if (ISSET(icr, I40E_INTR_NOTX_RX_MASK)) 3348 rv |= ixl_rxeof(sc, iv->iv_rxr); 3349 if (ISSET(icr, I40E_INTR_NOTX_TX_MASK)) 3350 rv |= ixl_txeof(sc, iv->iv_txr); 3351 } 3352 3353 return (rv); 3354 } 3355 3356 static int 3357 ixl_intr_vector(void *v) 3358 { 3359 struct ixl_vector *iv = v; 3360 struct ixl_softc *sc = iv->iv_sc; 3361 struct ifnet *ifp = &sc->sc_ac.ac_if; 3362 int rv = 0; 3363 3364 if (ISSET(ifp->if_flags, IFF_RUNNING)) { 3365 rv |= ixl_rxeof(sc, iv->iv_rxr); 3366 rv |= ixl_txeof(sc, iv->iv_txr); 3367 } 3368 3369 ixl_wr(sc, I40E_PFINT_DYN_CTLN(iv->iv_qid), 3370 I40E_PFINT_DYN_CTLN_INTENA_MASK | 3371 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK | 3372 (IXL_NOITR << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)); 3373 3374 return (rv); 3375 } 3376 3377 static void 3378 ixl_link_state_update_iaq(struct ixl_softc *sc, void *arg) 3379 { 3380 struct ifnet *ifp = &sc->sc_ac.ac_if; 3381 struct ixl_aq_desc *iaq = arg; 3382 uint16_t retval; 3383 int link_state; 3384 int change = 0; 3385 3386 retval = lemtoh16(&iaq->iaq_retval); 3387 if (retval != IXL_AQ_RC_OK) { 3388 printf("%s: LINK STATUS error %u\n", DEVNAME(sc), retval); 3389 return; 3390 } 3391 3392 link_state = ixl_set_link_status(sc, iaq); 3393 mtx_enter(&sc->sc_link_state_mtx); 3394 if (ifp->if_link_state != link_state) { 3395 ifp->if_link_state = link_state; 3396 change = 1; 3397 } 3398 mtx_leave(&sc->sc_link_state_mtx); 3399 3400 if (change) 3401 if_link_state_change(ifp); 3402 } 3403 3404 static void 3405 ixl_link_state_update(void *xsc) 3406 { 3407 struct ixl_softc *sc = xsc; 3408 struct ixl_aq_desc *iaq; 3409 struct ixl_aq_link_param *param; 3410 3411 memset(&sc->sc_link_state_atq, 0, sizeof(sc->sc_link_state_atq)); 3412 iaq = &sc->sc_link_state_atq.iatq_desc; 3413 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3414 param = (struct ixl_aq_link_param *)iaq->iaq_param; 3415 param->notify = IXL_AQ_LINK_NOTIFY; 3416 3417 ixl_atq_set(&sc->sc_link_state_atq, ixl_link_state_update_iaq, iaq); 3418 ixl_atq_post(sc, &sc->sc_link_state_atq); 3419 } 3420 3421 #if 0 3422 static void 3423 ixl_aq_dump(const struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 3424 { 3425 printf("%s: flags %b opcode %04x\n", DEVNAME(sc), 3426 lemtoh16(&iaq->iaq_flags), IXL_AQ_FLAGS_FMT, 3427 lemtoh16(&iaq->iaq_opcode)); 3428 printf("%s: datalen %u retval %u\n", DEVNAME(sc), 3429 lemtoh16(&iaq->iaq_datalen), lemtoh16(&iaq->iaq_retval)); 3430 printf("%s: cookie %016llx\n", DEVNAME(sc), iaq->iaq_cookie); 3431 printf("%s: %08x %08x %08x %08x\n", DEVNAME(sc), 3432 lemtoh32(&iaq->iaq_param[0]), lemtoh32(&iaq->iaq_param[1]), 3433 lemtoh32(&iaq->iaq_param[2]), lemtoh32(&iaq->iaq_param[3])); 3434 } 3435 #endif 3436 3437 static void 3438 ixl_arq(void *xsc) 3439 { 3440 struct ixl_softc *sc = xsc; 3441 struct ixl_aq_desc *arq, *iaq; 3442 struct ixl_aq_buf *aqb; 3443 unsigned int cons = sc->sc_arq_cons; 3444 unsigned int prod; 3445 int done = 0; 3446 3447 prod = ixl_rd(sc, sc->sc_aq_regs->arq_head) & 3448 sc->sc_aq_regs->arq_head_mask; 3449 3450 if (cons == prod) 3451 goto done; 3452 3453 arq = IXL_DMA_KVA(&sc->sc_arq); 3454 3455 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3456 0, IXL_DMA_LEN(&sc->sc_arq), 3457 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3458 3459 do { 3460 iaq = &arq[cons]; 3461 3462 aqb = SIMPLEQ_FIRST(&sc->sc_arq_live); 3463 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_live, aqb_entry); 3464 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 3465 BUS_DMASYNC_POSTREAD); 3466 3467 switch (iaq->iaq_opcode) { 3468 case HTOLE16(IXL_AQ_OP_PHY_LINK_STATUS): 3469 ixl_link_state_update_iaq(sc, iaq); 3470 break; 3471 } 3472 3473 memset(iaq, 0, sizeof(*iaq)); 3474 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_idle, aqb, aqb_entry); 3475 if_rxr_put(&sc->sc_arq_ring, 1); 3476 3477 cons++; 3478 cons &= IXL_AQ_MASK; 3479 3480 done = 1; 3481 } while (cons != prod); 3482 3483 if (done && ixl_arq_fill(sc)) 3484 ixl_wr(sc, sc->sc_aq_regs->arq_tail, sc->sc_arq_prod); 3485 3486 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_arq), 3487 0, IXL_DMA_LEN(&sc->sc_arq), 3488 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3489 3490 sc->sc_arq_cons = cons; 3491 3492 done: 3493 ixl_intr_enable(sc); 3494 } 3495 3496 static void 3497 ixl_atq_set(struct ixl_atq *iatq, 3498 void (*fn)(struct ixl_softc *, void *), void *arg) 3499 { 3500 iatq->iatq_fn = fn; 3501 iatq->iatq_arg = arg; 3502 } 3503 3504 static void 3505 ixl_atq_post(struct ixl_softc *sc, struct ixl_atq *iatq) 3506 { 3507 struct ixl_aq_desc *atq, *slot; 3508 unsigned int prod; 3509 3510 /* assert locked */ 3511 3512 atq = IXL_DMA_KVA(&sc->sc_atq); 3513 prod = sc->sc_atq_prod; 3514 slot = atq + prod; 3515 3516 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3517 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3518 3519 *slot = iatq->iatq_desc; 3520 slot->iaq_cookie = (uint64_t)iatq; 3521 3522 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3523 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3524 3525 prod++; 3526 prod &= IXL_AQ_MASK; 3527 sc->sc_atq_prod = prod; 3528 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3529 } 3530 3531 static void 3532 ixl_atq_done(struct ixl_softc *sc) 3533 { 3534 struct ixl_aq_desc *atq, *slot; 3535 struct ixl_atq *iatq; 3536 unsigned int cons; 3537 unsigned int prod; 3538 3539 prod = sc->sc_atq_prod; 3540 cons = sc->sc_atq_cons; 3541 3542 if (prod == cons) 3543 return; 3544 3545 atq = IXL_DMA_KVA(&sc->sc_atq); 3546 3547 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3548 0, IXL_DMA_LEN(&sc->sc_atq), 3549 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3550 3551 do { 3552 slot = &atq[cons]; 3553 if (!ISSET(slot->iaq_flags, htole16(IXL_AQ_DD))) 3554 break; 3555 3556 iatq = (struct ixl_atq *)slot->iaq_cookie; 3557 iatq->iatq_desc = *slot; 3558 3559 memset(slot, 0, sizeof(*slot)); 3560 3561 (*iatq->iatq_fn)(sc, iatq->iatq_arg); 3562 3563 cons++; 3564 cons &= IXL_AQ_MASK; 3565 } while (cons != prod); 3566 3567 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3568 0, IXL_DMA_LEN(&sc->sc_atq), 3569 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3570 3571 sc->sc_atq_cons = cons; 3572 } 3573 3574 static void 3575 ixl_wakeup(struct ixl_softc *sc, void *arg) 3576 { 3577 struct cond *c = arg; 3578 3579 cond_signal(c); 3580 } 3581 3582 static void 3583 ixl_atq_exec(struct ixl_softc *sc, struct ixl_atq *iatq, const char *wmesg) 3584 { 3585 struct cond c = COND_INITIALIZER(); 3586 3587 KASSERT(iatq->iatq_desc.iaq_cookie == 0); 3588 3589 ixl_atq_set(iatq, ixl_wakeup, &c); 3590 ixl_atq_post(sc, iatq); 3591 3592 cond_wait(&c, wmesg); 3593 } 3594 3595 static int 3596 ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm) 3597 { 3598 struct ixl_aq_desc *atq, *slot; 3599 unsigned int prod; 3600 unsigned int t = 0; 3601 3602 atq = IXL_DMA_KVA(&sc->sc_atq); 3603 prod = sc->sc_atq_prod; 3604 slot = atq + prod; 3605 3606 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3607 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTWRITE); 3608 3609 *slot = *iaq; 3610 slot->iaq_flags |= htole16(IXL_AQ_SI); 3611 3612 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3613 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREWRITE); 3614 3615 prod++; 3616 prod &= IXL_AQ_MASK; 3617 sc->sc_atq_prod = prod; 3618 ixl_wr(sc, sc->sc_aq_regs->atq_tail, prod); 3619 3620 while (ixl_rd(sc, sc->sc_aq_regs->atq_head) != prod) { 3621 delaymsec(1); 3622 3623 if (t++ > tm) 3624 return (ETIMEDOUT); 3625 } 3626 3627 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3628 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_POSTREAD); 3629 *iaq = *slot; 3630 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_atq), 3631 0, IXL_DMA_LEN(&sc->sc_atq), BUS_DMASYNC_PREREAD); 3632 3633 sc->sc_atq_cons = prod; 3634 3635 return (0); 3636 } 3637 3638 static int 3639 ixl_get_version(struct ixl_softc *sc) 3640 { 3641 struct ixl_aq_desc iaq; 3642 uint32_t fwbuild, fwver, apiver; 3643 3644 memset(&iaq, 0, sizeof(iaq)); 3645 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VERSION); 3646 3647 if (ixl_atq_poll(sc, &iaq, 2000) != 0) 3648 return (ETIMEDOUT); 3649 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) 3650 return (EIO); 3651 3652 fwbuild = lemtoh32(&iaq.iaq_param[1]); 3653 fwver = lemtoh32(&iaq.iaq_param[2]); 3654 apiver = lemtoh32(&iaq.iaq_param[3]); 3655 3656 sc->sc_api_major = apiver & 0xffff; 3657 sc->sc_api_minor = (apiver >> 16) & 0xffff; 3658 3659 printf(", FW %hu.%hu.%05u API %hu.%hu", (uint16_t)fwver, 3660 (uint16_t)(fwver >> 16), fwbuild, 3661 sc->sc_api_major, sc->sc_api_minor); 3662 3663 return (0); 3664 } 3665 3666 static int 3667 ixl_pxe_clear(struct ixl_softc *sc) 3668 { 3669 struct ixl_aq_desc iaq; 3670 3671 memset(&iaq, 0, sizeof(iaq)); 3672 iaq.iaq_opcode = htole16(IXL_AQ_OP_CLEAR_PXE_MODE); 3673 iaq.iaq_param[0] = htole32(0x2); 3674 3675 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3676 printf(", CLEAR PXE MODE timeout\n"); 3677 return (-1); 3678 } 3679 3680 switch (iaq.iaq_retval) { 3681 case HTOLE16(IXL_AQ_RC_OK): 3682 case HTOLE16(IXL_AQ_RC_EEXIST): 3683 break; 3684 default: 3685 printf(", CLEAR PXE MODE error\n"); 3686 return (-1); 3687 } 3688 3689 return (0); 3690 } 3691 3692 static int 3693 ixl_lldp_shut(struct ixl_softc *sc) 3694 { 3695 struct ixl_aq_desc iaq; 3696 3697 memset(&iaq, 0, sizeof(iaq)); 3698 iaq.iaq_opcode = htole16(IXL_AQ_OP_LLDP_STOP_AGENT); 3699 iaq.iaq_param[0] = htole32(IXL_LLDP_SHUTDOWN); 3700 3701 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3702 printf(", STOP LLDP AGENT timeout\n"); 3703 return (-1); 3704 } 3705 3706 switch (iaq.iaq_retval) { 3707 case HTOLE16(IXL_AQ_RC_EMODE): 3708 case HTOLE16(IXL_AQ_RC_EPERM): 3709 /* ignore silently */ 3710 default: 3711 break; 3712 } 3713 3714 return (0); 3715 } 3716 3717 static int 3718 ixl_get_mac(struct ixl_softc *sc) 3719 { 3720 struct ixl_dmamem idm; 3721 struct ixl_aq_desc iaq; 3722 struct ixl_aq_mac_addresses *addrs; 3723 int rv; 3724 3725 #ifdef __sparc64__ 3726 if (OF_getprop(PCITAG_NODE(sc->sc_tag), "local-mac-address", 3727 sc->sc_ac.ac_enaddr, ETHER_ADDR_LEN) == ETHER_ADDR_LEN) 3728 return (0); 3729 #endif 3730 3731 if (ixl_dmamem_alloc(sc, &idm, sizeof(*addrs), 0) != 0) { 3732 printf(", unable to allocate mac addresses\n"); 3733 return (-1); 3734 } 3735 3736 memset(&iaq, 0, sizeof(iaq)); 3737 iaq.iaq_flags = htole16(IXL_AQ_BUF); 3738 iaq.iaq_opcode = htole16(IXL_AQ_OP_MAC_ADDRESS_READ); 3739 iaq.iaq_datalen = htole16(sizeof(*addrs)); 3740 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 3741 3742 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3743 BUS_DMASYNC_PREREAD); 3744 3745 rv = ixl_atq_poll(sc, &iaq, 250); 3746 3747 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3748 BUS_DMASYNC_POSTREAD); 3749 3750 if (rv != 0) { 3751 printf(", MAC ADDRESS READ timeout\n"); 3752 rv = -1; 3753 goto done; 3754 } 3755 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3756 printf(", MAC ADDRESS READ error\n"); 3757 rv = -1; 3758 goto done; 3759 } 3760 3761 addrs = IXL_DMA_KVA(&idm); 3762 if (!ISSET(iaq.iaq_param[0], htole32(IXL_AQ_MAC_PORT_VALID))) { 3763 printf(", port address is not valid\n"); 3764 goto done; 3765 } 3766 3767 memcpy(sc->sc_ac.ac_enaddr, addrs->port, ETHER_ADDR_LEN); 3768 rv = 0; 3769 3770 done: 3771 ixl_dmamem_free(sc, &idm); 3772 return (rv); 3773 } 3774 3775 static int 3776 ixl_get_switch_config(struct ixl_softc *sc) 3777 { 3778 struct ixl_dmamem idm; 3779 struct ixl_aq_desc iaq; 3780 struct ixl_aq_switch_config *hdr; 3781 struct ixl_aq_switch_config_element *elms, *elm; 3782 unsigned int nelm; 3783 int rv; 3784 3785 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 3786 printf("%s: unable to allocate switch config buffer\n", 3787 DEVNAME(sc)); 3788 return (-1); 3789 } 3790 3791 memset(&iaq, 0, sizeof(iaq)); 3792 iaq.iaq_flags = htole16(IXL_AQ_BUF | 3793 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 3794 iaq.iaq_opcode = htole16(IXL_AQ_OP_SWITCH_GET_CONFIG); 3795 iaq.iaq_datalen = htole16(IXL_AQ_BUFLEN); 3796 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm)); 3797 3798 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3799 BUS_DMASYNC_PREREAD); 3800 3801 rv = ixl_atq_poll(sc, &iaq, 250); 3802 3803 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&idm), 0, IXL_DMA_LEN(&idm), 3804 BUS_DMASYNC_POSTREAD); 3805 3806 if (rv != 0) { 3807 printf("%s: GET SWITCH CONFIG timeout\n", DEVNAME(sc)); 3808 rv = -1; 3809 goto done; 3810 } 3811 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3812 printf("%s: GET SWITCH CONFIG error\n", DEVNAME(sc)); 3813 rv = -1; 3814 goto done; 3815 } 3816 3817 hdr = IXL_DMA_KVA(&idm); 3818 elms = (struct ixl_aq_switch_config_element *)(hdr + 1); 3819 3820 nelm = lemtoh16(&hdr->num_reported); 3821 if (nelm < 1) { 3822 printf("%s: no switch config available\n", DEVNAME(sc)); 3823 rv = -1; 3824 goto done; 3825 } 3826 3827 #if 0 3828 for (i = 0; i < nelm; i++) { 3829 elm = &elms[i]; 3830 3831 printf("%s: type %x revision %u seid %04x\n", DEVNAME(sc), 3832 elm->type, elm->revision, lemtoh16(&elm->seid)); 3833 printf("%s: uplink %04x downlink %04x\n", DEVNAME(sc), 3834 lemtoh16(&elm->uplink_seid), 3835 lemtoh16(&elm->downlink_seid)); 3836 printf("%s: conntype %x scheduler %04x extra %04x\n", 3837 DEVNAME(sc), elm->connection_type, 3838 lemtoh16(&elm->scheduler_id), 3839 lemtoh16(&elm->element_info)); 3840 } 3841 #endif 3842 3843 elm = &elms[0]; 3844 3845 sc->sc_uplink_seid = elm->uplink_seid; 3846 sc->sc_downlink_seid = elm->downlink_seid; 3847 sc->sc_seid = elm->seid; 3848 3849 if ((sc->sc_uplink_seid == htole16(0)) != 3850 (sc->sc_downlink_seid == htole16(0))) { 3851 printf("%s: SEIDs are misconfigured\n", DEVNAME(sc)); 3852 rv = -1; 3853 goto done; 3854 } 3855 3856 done: 3857 ixl_dmamem_free(sc, &idm); 3858 return (rv); 3859 } 3860 3861 static int 3862 ixl_phy_mask_ints(struct ixl_softc *sc) 3863 { 3864 struct ixl_aq_desc iaq; 3865 3866 memset(&iaq, 0, sizeof(iaq)); 3867 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_EVENT_MASK); 3868 iaq.iaq_param[2] = htole32(IXL_AQ_PHY_EV_MASK & 3869 ~(IXL_AQ_PHY_EV_LINK_UPDOWN | IXL_AQ_PHY_EV_MODULE_QUAL_FAIL | 3870 IXL_AQ_PHY_EV_MEDIA_NA)); 3871 3872 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3873 printf("%s: SET PHY EVENT MASK timeout\n", DEVNAME(sc)); 3874 return (-1); 3875 } 3876 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 3877 printf("%s: SET PHY EVENT MASK error\n", DEVNAME(sc)); 3878 return (-1); 3879 } 3880 3881 return (0); 3882 } 3883 3884 static int 3885 ixl_get_phy_abilities(struct ixl_softc *sc,struct ixl_dmamem *idm) 3886 { 3887 struct ixl_aq_desc iaq; 3888 int rv; 3889 3890 memset(&iaq, 0, sizeof(iaq)); 3891 iaq.iaq_flags = htole16(IXL_AQ_BUF | 3892 (IXL_DMA_LEN(idm) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 3893 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_ABILITIES); 3894 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(idm)); 3895 iaq.iaq_param[0] = htole32(IXL_AQ_PHY_REPORT_INIT); 3896 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm)); 3897 3898 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 3899 BUS_DMASYNC_PREREAD); 3900 3901 rv = ixl_atq_poll(sc, &iaq, 250); 3902 3903 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(idm), 0, IXL_DMA_LEN(idm), 3904 BUS_DMASYNC_POSTREAD); 3905 3906 if (rv != 0) 3907 return (-1); 3908 3909 return (lemtoh16(&iaq.iaq_retval)); 3910 } 3911 3912 static int 3913 ixl_get_phy_types(struct ixl_softc *sc, uint64_t *phy_types_ptr) 3914 { 3915 struct ixl_dmamem idm; 3916 struct ixl_aq_phy_abilities *phy; 3917 uint64_t phy_types; 3918 int rv; 3919 3920 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) { 3921 printf("%s: unable to allocate phy abilities buffer\n", 3922 DEVNAME(sc)); 3923 return (-1); 3924 } 3925 3926 rv = ixl_get_phy_abilities(sc, &idm); 3927 switch (rv) { 3928 case -1: 3929 printf("%s: GET PHY ABILITIES timeout\n", DEVNAME(sc)); 3930 goto err; 3931 case IXL_AQ_RC_OK: 3932 break; 3933 case IXL_AQ_RC_EIO: 3934 /* API is too old to handle this command */ 3935 phy_types = 0; 3936 goto done; 3937 default: 3938 printf("%s: GET PHY ABILITIIES error %u\n", DEVNAME(sc), rv); 3939 goto err; 3940 } 3941 3942 phy = IXL_DMA_KVA(&idm); 3943 3944 phy_types = lemtoh32(&phy->phy_type); 3945 phy_types |= (uint64_t)phy->phy_type_ext << 32; 3946 3947 done: 3948 *phy_types_ptr = phy_types; 3949 3950 rv = 0; 3951 3952 err: 3953 ixl_dmamem_free(sc, &idm); 3954 return (rv); 3955 } 3956 3957 /* 3958 * this returns -2 on software/driver failure, -1 for problems 3959 * talking to the hardware, or the sff module type. 3960 */ 3961 3962 static int 3963 ixl_get_module_type(struct ixl_softc *sc) 3964 { 3965 struct ixl_dmamem idm; 3966 struct ixl_aq_phy_abilities *phy; 3967 int rv; 3968 3969 if (ixl_dmamem_alloc(sc, &idm, IXL_AQ_BUFLEN, 0) != 0) 3970 return (-2); 3971 3972 rv = ixl_get_phy_abilities(sc, &idm); 3973 if (rv != IXL_AQ_RC_OK) { 3974 rv = -1; 3975 goto done; 3976 } 3977 3978 phy = IXL_DMA_KVA(&idm); 3979 3980 rv = phy->module_type[0]; 3981 3982 done: 3983 ixl_dmamem_free(sc, &idm); 3984 return (rv); 3985 } 3986 3987 static int 3988 ixl_get_link_status(struct ixl_softc *sc) 3989 { 3990 struct ixl_aq_desc iaq; 3991 struct ixl_aq_link_param *param; 3992 3993 memset(&iaq, 0, sizeof(iaq)); 3994 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS); 3995 param = (struct ixl_aq_link_param *)iaq.iaq_param; 3996 param->notify = IXL_AQ_LINK_NOTIFY; 3997 3998 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 3999 printf("%s: GET LINK STATUS timeout\n", DEVNAME(sc)); 4000 return (-1); 4001 } 4002 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4003 printf("%s: GET LINK STATUS error\n", DEVNAME(sc)); 4004 return (0); 4005 } 4006 4007 sc->sc_ac.ac_if.if_link_state = ixl_set_link_status(sc, &iaq); 4008 4009 return (0); 4010 } 4011 4012 struct ixl_sff_ops { 4013 int (*open)(struct ixl_softc *sc, struct if_sffpage *, uint8_t *); 4014 int (*get)(struct ixl_softc *sc, struct if_sffpage *, size_t); 4015 int (*close)(struct ixl_softc *sc, struct if_sffpage *, uint8_t); 4016 }; 4017 4018 static int 4019 ixl_sfp_open(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t *page) 4020 { 4021 int error; 4022 4023 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4024 return (0); 4025 4026 error = ixl_sff_get_byte(sc, IFSFF_ADDR_EEPROM, 127, page); 4027 if (error != 0) 4028 return (error); 4029 if (*page == sff->sff_page) 4030 return (0); 4031 error = ixl_sff_set_byte(sc, IFSFF_ADDR_EEPROM, 127, sff->sff_page); 4032 if (error != 0) 4033 return (error); 4034 4035 return (0); 4036 } 4037 4038 static int 4039 ixl_sfp_get(struct ixl_softc *sc, struct if_sffpage *sff, size_t i) 4040 { 4041 return (ixl_sff_get_byte(sc, sff->sff_addr, i, &sff->sff_data[i])); 4042 } 4043 4044 static int 4045 ixl_sfp_close(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t page) 4046 { 4047 int error; 4048 4049 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4050 return (0); 4051 4052 if (page == sff->sff_page) 4053 return (0); 4054 4055 error = ixl_sff_set_byte(sc, IFSFF_ADDR_EEPROM, 127, page); 4056 if (error != 0) 4057 return (error); 4058 4059 return (0); 4060 } 4061 4062 static const struct ixl_sff_ops ixl_sfp_ops = { 4063 ixl_sfp_open, 4064 ixl_sfp_get, 4065 ixl_sfp_close, 4066 }; 4067 4068 static int 4069 ixl_qsfp_open(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t *page) 4070 { 4071 if (sff->sff_addr != IFSFF_ADDR_EEPROM) 4072 return (EIO); 4073 4074 return (0); 4075 } 4076 4077 static int 4078 ixl_qsfp_get(struct ixl_softc *sc, struct if_sffpage *sff, size_t i) 4079 { 4080 return (ixl_sff_get_byte(sc, sff->sff_page, i, &sff->sff_data[i])); 4081 } 4082 4083 static int 4084 ixl_qsfp_close(struct ixl_softc *sc, struct if_sffpage *sff, uint8_t page) 4085 { 4086 return (0); 4087 } 4088 4089 static const struct ixl_sff_ops ixl_qsfp_ops = { 4090 ixl_qsfp_open, 4091 ixl_qsfp_get, 4092 ixl_qsfp_close, 4093 }; 4094 4095 static int 4096 ixl_get_sffpage(struct ixl_softc *sc, struct if_sffpage *sff) 4097 { 4098 const struct ixl_sff_ops *ops; 4099 uint8_t page; 4100 size_t i; 4101 int error; 4102 4103 switch (ixl_get_module_type(sc)) { 4104 case -2: 4105 return (ENOMEM); 4106 case -1: 4107 return (ENXIO); 4108 case IXL_SFF8024_ID_SFP: 4109 ops = &ixl_sfp_ops; 4110 break; 4111 case IXL_SFF8024_ID_QSFP: 4112 case IXL_SFF8024_ID_QSFP_PLUS: 4113 case IXL_SFF8024_ID_QSFP28: 4114 ops = &ixl_qsfp_ops; 4115 break; 4116 default: 4117 return (EOPNOTSUPP); 4118 } 4119 4120 error = (*ops->open)(sc, sff, &page); 4121 if (error != 0) 4122 return (error); 4123 4124 for (i = 0; i < sizeof(sff->sff_data); i++) { 4125 error = (*ops->get)(sc, sff, i); 4126 if (error != 0) 4127 return (error); 4128 } 4129 4130 error = (*ops->close)(sc, sff, page); 4131 4132 return (0); 4133 } 4134 4135 static int 4136 ixl_sff_get_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t *p) 4137 { 4138 struct ixl_atq iatq; 4139 struct ixl_aq_desc *iaq; 4140 struct ixl_aq_phy_reg_access *param; 4141 4142 memset(&iatq, 0, sizeof(iatq)); 4143 iaq = &iatq.iatq_desc; 4144 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_REGISTER); 4145 param = (struct ixl_aq_phy_reg_access *)iaq->iaq_param; 4146 param->phy_iface = IXL_AQ_PHY_IF_MODULE; 4147 param->dev_addr = dev; 4148 htolem32(¶m->reg, reg); 4149 4150 ixl_atq_exec(sc, &iatq, "ixlsffget"); 4151 4152 if (ISSET(sc->sc_ac.ac_if.if_flags, IFF_DEBUG)) { 4153 printf("%s: %s(dev 0x%02x, reg 0x%02x) -> %04x\n", 4154 DEVNAME(sc), __func__, 4155 dev, reg, lemtoh16(&iaq->iaq_retval)); 4156 } 4157 4158 switch (iaq->iaq_retval) { 4159 case htole16(IXL_AQ_RC_OK): 4160 break; 4161 case htole16(IXL_AQ_RC_EBUSY): 4162 return (EBUSY); 4163 case htole16(IXL_AQ_RC_ESRCH): 4164 return (ENODEV); 4165 case htole16(IXL_AQ_RC_EIO): 4166 case htole16(IXL_AQ_RC_EINVAL): 4167 default: 4168 return (EIO); 4169 } 4170 4171 *p = lemtoh32(¶m->val); 4172 4173 return (0); 4174 } 4175 4176 static int 4177 ixl_sff_set_byte(struct ixl_softc *sc, uint8_t dev, uint32_t reg, uint8_t v) 4178 { 4179 struct ixl_atq iatq; 4180 struct ixl_aq_desc *iaq; 4181 struct ixl_aq_phy_reg_access *param; 4182 4183 memset(&iatq, 0, sizeof(iatq)); 4184 iaq = &iatq.iatq_desc; 4185 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_REGISTER); 4186 param = (struct ixl_aq_phy_reg_access *)iaq->iaq_param; 4187 param->phy_iface = IXL_AQ_PHY_IF_MODULE; 4188 param->dev_addr = dev; 4189 htolem32(¶m->reg, reg); 4190 htolem32(¶m->val, v); 4191 4192 ixl_atq_exec(sc, &iatq, "ixlsffset"); 4193 4194 if (ISSET(sc->sc_ac.ac_if.if_flags, IFF_DEBUG)) { 4195 printf("%s: %s(dev 0x%02x, reg 0x%02x, val 0x%02x) -> %04x\n", 4196 DEVNAME(sc), __func__, 4197 dev, reg, v, lemtoh16(&iaq->iaq_retval)); 4198 } 4199 4200 switch (iaq->iaq_retval) { 4201 case htole16(IXL_AQ_RC_OK): 4202 break; 4203 case htole16(IXL_AQ_RC_EBUSY): 4204 return (EBUSY); 4205 case htole16(IXL_AQ_RC_ESRCH): 4206 return (ENODEV); 4207 case htole16(IXL_AQ_RC_EIO): 4208 case htole16(IXL_AQ_RC_EINVAL): 4209 default: 4210 return (EIO); 4211 } 4212 4213 return (0); 4214 } 4215 4216 static int 4217 ixl_get_vsi(struct ixl_softc *sc) 4218 { 4219 struct ixl_dmamem *vsi = &sc->sc_scratch; 4220 struct ixl_aq_desc iaq; 4221 struct ixl_aq_vsi_param *param; 4222 struct ixl_aq_vsi_reply *reply; 4223 int rv; 4224 4225 /* grumble, vsi info isn't "known" at compile time */ 4226 4227 memset(&iaq, 0, sizeof(iaq)); 4228 htolem16(&iaq.iaq_flags, IXL_AQ_BUF | 4229 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4230 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VSI_PARAMS); 4231 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(vsi)); 4232 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4233 4234 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4235 param->uplink_seid = sc->sc_seid; 4236 4237 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4238 BUS_DMASYNC_PREREAD); 4239 4240 rv = ixl_atq_poll(sc, &iaq, 250); 4241 4242 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4243 BUS_DMASYNC_POSTREAD); 4244 4245 if (rv != 0) { 4246 printf("%s: GET VSI timeout\n", DEVNAME(sc)); 4247 return (-1); 4248 } 4249 4250 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4251 printf("%s: GET VSI error %u\n", DEVNAME(sc), 4252 lemtoh16(&iaq.iaq_retval)); 4253 return (-1); 4254 } 4255 4256 reply = (struct ixl_aq_vsi_reply *)iaq.iaq_param; 4257 sc->sc_vsi_number = reply->vsi_number; 4258 4259 return (0); 4260 } 4261 4262 static int 4263 ixl_set_vsi(struct ixl_softc *sc) 4264 { 4265 struct ixl_dmamem *vsi = &sc->sc_scratch; 4266 struct ixl_aq_desc iaq; 4267 struct ixl_aq_vsi_param *param; 4268 struct ixl_aq_vsi_data *data = IXL_DMA_KVA(vsi); 4269 int rv; 4270 4271 data->valid_sections = htole16(IXL_AQ_VSI_VALID_QUEUE_MAP | 4272 IXL_AQ_VSI_VALID_VLAN); 4273 4274 CLR(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_MASK)); 4275 SET(data->mapping_flags, htole16(IXL_AQ_VSI_QUE_MAP_CONTIG)); 4276 data->queue_mapping[0] = htole16(0); 4277 data->tc_mapping[0] = htole16((0 << IXL_AQ_VSI_TC_Q_OFFSET_SHIFT) | 4278 (sc->sc_nqueues << IXL_AQ_VSI_TC_Q_NUMBER_SHIFT)); 4279 4280 CLR(data->port_vlan_flags, 4281 htole16(IXL_AQ_VSI_PVLAN_MODE_MASK | IXL_AQ_VSI_PVLAN_EMOD_MASK)); 4282 SET(data->port_vlan_flags, 4283 htole16(IXL_AQ_VSI_PVLAN_MODE_ALL | IXL_AQ_VSI_PVLAN_EMOD_NOTHING)); 4284 4285 /* grumble, vsi info isn't "known" at compile time */ 4286 4287 memset(&iaq, 0, sizeof(iaq)); 4288 htolem16(&iaq.iaq_flags, IXL_AQ_BUF | IXL_AQ_RD | 4289 (IXL_DMA_LEN(vsi) > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4290 iaq.iaq_opcode = htole16(IXL_AQ_OP_UPD_VSI_PARAMS); 4291 htolem16(&iaq.iaq_datalen, IXL_DMA_LEN(vsi)); 4292 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi)); 4293 4294 param = (struct ixl_aq_vsi_param *)iaq.iaq_param; 4295 param->uplink_seid = sc->sc_seid; 4296 4297 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4298 BUS_DMASYNC_PREWRITE); 4299 4300 rv = ixl_atq_poll(sc, &iaq, 250); 4301 4302 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(vsi), 0, IXL_DMA_LEN(vsi), 4303 BUS_DMASYNC_POSTWRITE); 4304 4305 if (rv != 0) { 4306 printf("%s: UPDATE VSI timeout\n", DEVNAME(sc)); 4307 return (-1); 4308 } 4309 4310 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4311 printf("%s: UPDATE VSI error %u\n", DEVNAME(sc), 4312 lemtoh16(&iaq.iaq_retval)); 4313 return (-1); 4314 } 4315 4316 return (0); 4317 } 4318 4319 static const struct ixl_phy_type * 4320 ixl_search_phy_type(uint8_t phy_type) 4321 { 4322 const struct ixl_phy_type *itype; 4323 uint64_t mask; 4324 unsigned int i; 4325 4326 if (phy_type >= 64) 4327 return (NULL); 4328 4329 mask = 1ULL << phy_type; 4330 4331 for (i = 0; i < nitems(ixl_phy_type_map); i++) { 4332 itype = &ixl_phy_type_map[i]; 4333 4334 if (ISSET(itype->phy_type, mask)) 4335 return (itype); 4336 } 4337 4338 return (NULL); 4339 } 4340 4341 static uint64_t 4342 ixl_search_link_speed(uint8_t link_speed) 4343 { 4344 const struct ixl_speed_type *type; 4345 unsigned int i; 4346 4347 for (i = 0; i < nitems(ixl_speed_type_map); i++) { 4348 type = &ixl_speed_type_map[i]; 4349 4350 if (ISSET(type->dev_speed, link_speed)) 4351 return (type->net_speed); 4352 } 4353 4354 return (0); 4355 } 4356 4357 static int 4358 ixl_set_link_status(struct ixl_softc *sc, const struct ixl_aq_desc *iaq) 4359 { 4360 const struct ixl_aq_link_status *status; 4361 const struct ixl_phy_type *itype; 4362 4363 uint64_t ifm_active = IFM_ETHER; 4364 uint64_t ifm_status = IFM_AVALID; 4365 int link_state = LINK_STATE_DOWN; 4366 uint64_t baudrate = 0; 4367 4368 status = (const struct ixl_aq_link_status *)iaq->iaq_param; 4369 if (!ISSET(status->link_info, IXL_AQ_LINK_UP_FUNCTION)) 4370 goto done; 4371 4372 ifm_active |= IFM_FDX; 4373 ifm_status |= IFM_ACTIVE; 4374 link_state = LINK_STATE_FULL_DUPLEX; 4375 4376 itype = ixl_search_phy_type(status->phy_type); 4377 if (itype != NULL) 4378 ifm_active |= itype->ifm_type; 4379 4380 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_TX)) 4381 ifm_active |= IFM_ETH_TXPAUSE; 4382 if (ISSET(status->an_info, IXL_AQ_LINK_PAUSE_RX)) 4383 ifm_active |= IFM_ETH_RXPAUSE; 4384 4385 baudrate = ixl_search_link_speed(status->link_speed); 4386 4387 done: 4388 /* NET_ASSERT_LOCKED() except during attach */ 4389 sc->sc_media_active = ifm_active; 4390 sc->sc_media_status = ifm_status; 4391 sc->sc_ac.ac_if.if_baudrate = baudrate; 4392 4393 return (link_state); 4394 } 4395 4396 static int 4397 ixl_restart_an(struct ixl_softc *sc) 4398 { 4399 struct ixl_aq_desc iaq; 4400 4401 memset(&iaq, 0, sizeof(iaq)); 4402 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_RESTART_AN); 4403 iaq.iaq_param[0] = 4404 htole32(IXL_AQ_PHY_RESTART_AN | IXL_AQ_PHY_LINK_ENABLE); 4405 4406 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4407 printf("%s: RESTART AN timeout\n", DEVNAME(sc)); 4408 return (-1); 4409 } 4410 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) { 4411 printf("%s: RESTART AN error\n", DEVNAME(sc)); 4412 return (-1); 4413 } 4414 4415 return (0); 4416 } 4417 4418 static int 4419 ixl_add_macvlan(struct ixl_softc *sc, uint8_t *macaddr, uint16_t vlan, uint16_t flags) 4420 { 4421 struct ixl_aq_desc iaq; 4422 struct ixl_aq_add_macvlan *param; 4423 struct ixl_aq_add_macvlan_elem *elem; 4424 4425 memset(&iaq, 0, sizeof(iaq)); 4426 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4427 iaq.iaq_opcode = htole16(IXL_AQ_OP_ADD_MACVLAN); 4428 iaq.iaq_datalen = htole16(sizeof(*elem)); 4429 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4430 4431 param = (struct ixl_aq_add_macvlan *)&iaq.iaq_param; 4432 param->num_addrs = htole16(1); 4433 param->seid0 = htole16(0x8000) | sc->sc_seid; 4434 param->seid1 = 0; 4435 param->seid2 = 0; 4436 4437 elem = IXL_DMA_KVA(&sc->sc_scratch); 4438 memset(elem, 0, sizeof(*elem)); 4439 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4440 elem->flags = htole16(IXL_AQ_OP_ADD_MACVLAN_PERFECT_MATCH | flags); 4441 elem->vlan = htole16(vlan); 4442 4443 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4444 printf("%s: ADD_MACVLAN timeout\n", DEVNAME(sc)); 4445 return (IXL_AQ_RC_EINVAL); 4446 } 4447 4448 return letoh16(iaq.iaq_retval); 4449 } 4450 4451 static int 4452 ixl_remove_macvlan(struct ixl_softc *sc, uint8_t *macaddr, uint16_t vlan, uint16_t flags) 4453 { 4454 struct ixl_aq_desc iaq; 4455 struct ixl_aq_remove_macvlan *param; 4456 struct ixl_aq_remove_macvlan_elem *elem; 4457 4458 memset(&iaq, 0, sizeof(iaq)); 4459 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD); 4460 iaq.iaq_opcode = htole16(IXL_AQ_OP_REMOVE_MACVLAN); 4461 iaq.iaq_datalen = htole16(sizeof(*elem)); 4462 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch)); 4463 4464 param = (struct ixl_aq_remove_macvlan *)&iaq.iaq_param; 4465 param->num_addrs = htole16(1); 4466 param->seid0 = htole16(0x8000) | sc->sc_seid; 4467 param->seid1 = 0; 4468 param->seid2 = 0; 4469 4470 elem = IXL_DMA_KVA(&sc->sc_scratch); 4471 memset(elem, 0, sizeof(*elem)); 4472 memcpy(elem->macaddr, macaddr, ETHER_ADDR_LEN); 4473 elem->flags = htole16(IXL_AQ_OP_REMOVE_MACVLAN_PERFECT_MATCH | flags); 4474 elem->vlan = htole16(vlan); 4475 4476 if (ixl_atq_poll(sc, &iaq, 250) != 0) { 4477 printf("%s: REMOVE_MACVLAN timeout\n", DEVNAME(sc)); 4478 return (IXL_AQ_RC_EINVAL); 4479 } 4480 4481 return letoh16(iaq.iaq_retval); 4482 } 4483 4484 static int 4485 ixl_hmc(struct ixl_softc *sc) 4486 { 4487 struct { 4488 uint32_t count; 4489 uint32_t minsize; 4490 bus_size_t maxcnt; 4491 bus_size_t setoff; 4492 bus_size_t setcnt; 4493 } regs[] = { 4494 { 4495 0, 4496 IXL_HMC_TXQ_MINSIZE, 4497 I40E_GLHMC_LANTXOBJSZ, 4498 I40E_GLHMC_LANTXBASE(sc->sc_pf_id), 4499 I40E_GLHMC_LANTXCNT(sc->sc_pf_id), 4500 }, 4501 { 4502 0, 4503 IXL_HMC_RXQ_MINSIZE, 4504 I40E_GLHMC_LANRXOBJSZ, 4505 I40E_GLHMC_LANRXBASE(sc->sc_pf_id), 4506 I40E_GLHMC_LANRXCNT(sc->sc_pf_id), 4507 }, 4508 { 4509 0, 4510 0, 4511 I40E_GLHMC_FCOEMAX, 4512 I40E_GLHMC_FCOEDDPBASE(sc->sc_pf_id), 4513 I40E_GLHMC_FCOEDDPCNT(sc->sc_pf_id), 4514 }, 4515 { 4516 0, 4517 0, 4518 I40E_GLHMC_FCOEFMAX, 4519 I40E_GLHMC_FCOEFBASE(sc->sc_pf_id), 4520 I40E_GLHMC_FCOEFCNT(sc->sc_pf_id), 4521 }, 4522 }; 4523 struct ixl_hmc_entry *e; 4524 uint64_t size, dva; 4525 uint8_t *kva; 4526 uint64_t *sdpage; 4527 unsigned int i; 4528 int npages, tables; 4529 4530 CTASSERT(nitems(regs) <= nitems(sc->sc_hmc_entries)); 4531 4532 regs[IXL_HMC_LAN_TX].count = regs[IXL_HMC_LAN_RX].count = 4533 ixl_rd(sc, I40E_GLHMC_LANQMAX); 4534 4535 size = 0; 4536 for (i = 0; i < nitems(regs); i++) { 4537 e = &sc->sc_hmc_entries[i]; 4538 4539 e->hmc_count = regs[i].count; 4540 e->hmc_size = 1U << ixl_rd(sc, regs[i].maxcnt); 4541 e->hmc_base = size; 4542 4543 if ((e->hmc_size * 8) < regs[i].minsize) { 4544 printf("%s: kernel hmc entry is too big\n", 4545 DEVNAME(sc)); 4546 return (-1); 4547 } 4548 4549 size += roundup(e->hmc_size * e->hmc_count, IXL_HMC_ROUNDUP); 4550 } 4551 size = roundup(size, IXL_HMC_PGSIZE); 4552 npages = size / IXL_HMC_PGSIZE; 4553 4554 tables = roundup(size, IXL_HMC_L2SZ) / IXL_HMC_L2SZ; 4555 4556 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_pd, size, IXL_HMC_PGSIZE) != 0) { 4557 printf("%s: unable to allocate hmc pd memory\n", DEVNAME(sc)); 4558 return (-1); 4559 } 4560 4561 if (ixl_dmamem_alloc(sc, &sc->sc_hmc_sd, tables * IXL_HMC_PGSIZE, 4562 IXL_HMC_PGSIZE) != 0) { 4563 printf("%s: unable to allocate hmc sd memory\n", DEVNAME(sc)); 4564 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 4565 return (-1); 4566 } 4567 4568 kva = IXL_DMA_KVA(&sc->sc_hmc_pd); 4569 memset(kva, 0, IXL_DMA_LEN(&sc->sc_hmc_pd)); 4570 4571 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_pd), 4572 0, IXL_DMA_LEN(&sc->sc_hmc_pd), 4573 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4574 4575 dva = IXL_DMA_DVA(&sc->sc_hmc_pd); 4576 sdpage = IXL_DMA_KVA(&sc->sc_hmc_sd); 4577 for (i = 0; i < npages; i++) { 4578 htolem64(sdpage++, dva | IXL_HMC_PDVALID); 4579 4580 dva += IXL_HMC_PGSIZE; 4581 } 4582 4583 bus_dmamap_sync(sc->sc_dmat, IXL_DMA_MAP(&sc->sc_hmc_sd), 4584 0, IXL_DMA_LEN(&sc->sc_hmc_sd), 4585 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4586 4587 dva = IXL_DMA_DVA(&sc->sc_hmc_sd); 4588 for (i = 0; i < tables; i++) { 4589 uint32_t count; 4590 4591 KASSERT(npages >= 0); 4592 4593 count = (npages > IXL_HMC_PGS) ? IXL_HMC_PGS : npages; 4594 4595 ixl_wr(sc, I40E_PFHMC_SDDATAHIGH, dva >> 32); 4596 ixl_wr(sc, I40E_PFHMC_SDDATALOW, dva | 4597 (count << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | 4598 (1U << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)); 4599 ixl_barrier(sc, 0, sc->sc_mems, BUS_SPACE_BARRIER_WRITE); 4600 ixl_wr(sc, I40E_PFHMC_SDCMD, 4601 (1U << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) | i); 4602 4603 npages -= IXL_HMC_PGS; 4604 dva += IXL_HMC_PGSIZE; 4605 } 4606 4607 for (i = 0; i < nitems(regs); i++) { 4608 e = &sc->sc_hmc_entries[i]; 4609 4610 ixl_wr(sc, regs[i].setoff, e->hmc_base / IXL_HMC_ROUNDUP); 4611 ixl_wr(sc, regs[i].setcnt, e->hmc_count); 4612 } 4613 4614 return (0); 4615 } 4616 4617 static void 4618 ixl_hmc_free(struct ixl_softc *sc) 4619 { 4620 ixl_dmamem_free(sc, &sc->sc_hmc_sd); 4621 ixl_dmamem_free(sc, &sc->sc_hmc_pd); 4622 } 4623 4624 static void 4625 ixl_hmc_pack(void *d, const void *s, const struct ixl_hmc_pack *packing, 4626 unsigned int npacking) 4627 { 4628 uint8_t *dst = d; 4629 const uint8_t *src = s; 4630 unsigned int i; 4631 4632 for (i = 0; i < npacking; i++) { 4633 const struct ixl_hmc_pack *pack = &packing[i]; 4634 unsigned int offset = pack->lsb / 8; 4635 unsigned int align = pack->lsb % 8; 4636 const uint8_t *in = src + pack->offset; 4637 uint8_t *out = dst + offset; 4638 int width = pack->width; 4639 unsigned int inbits = 0; 4640 4641 if (align) { 4642 inbits = (*in++) << align; 4643 *out++ |= (inbits & 0xff); 4644 inbits >>= 8; 4645 4646 width -= 8 - align; 4647 } 4648 4649 while (width >= 8) { 4650 inbits |= (*in++) << align; 4651 *out++ = (inbits & 0xff); 4652 inbits >>= 8; 4653 4654 width -= 8; 4655 } 4656 4657 if (width > 0) { 4658 inbits |= (*in) << align; 4659 *out |= (inbits & ((1 << width) - 1)); 4660 } 4661 } 4662 } 4663 4664 static struct ixl_aq_buf * 4665 ixl_aqb_alloc(struct ixl_softc *sc) 4666 { 4667 struct ixl_aq_buf *aqb; 4668 4669 aqb = malloc(sizeof(*aqb), M_DEVBUF, M_WAITOK); 4670 if (aqb == NULL) 4671 return (NULL); 4672 4673 aqb->aqb_data = dma_alloc(IXL_AQ_BUFLEN, PR_WAITOK); 4674 if (aqb->aqb_data == NULL) 4675 goto free; 4676 4677 if (bus_dmamap_create(sc->sc_dmat, IXL_AQ_BUFLEN, 1, 4678 IXL_AQ_BUFLEN, 0, 4679 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 4680 &aqb->aqb_map) != 0) 4681 goto dma_free; 4682 4683 if (bus_dmamap_load(sc->sc_dmat, aqb->aqb_map, aqb->aqb_data, 4684 IXL_AQ_BUFLEN, NULL, BUS_DMA_WAITOK) != 0) 4685 goto destroy; 4686 4687 return (aqb); 4688 4689 destroy: 4690 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 4691 dma_free: 4692 dma_free(aqb->aqb_data, IXL_AQ_BUFLEN); 4693 free: 4694 free(aqb, M_DEVBUF, sizeof(*aqb)); 4695 4696 return (NULL); 4697 } 4698 4699 static void 4700 ixl_aqb_free(struct ixl_softc *sc, struct ixl_aq_buf *aqb) 4701 { 4702 bus_dmamap_unload(sc->sc_dmat, aqb->aqb_map); 4703 bus_dmamap_destroy(sc->sc_dmat, aqb->aqb_map); 4704 dma_free(aqb->aqb_data, IXL_AQ_BUFLEN); 4705 free(aqb, M_DEVBUF, sizeof(*aqb)); 4706 } 4707 4708 static int 4709 ixl_arq_fill(struct ixl_softc *sc) 4710 { 4711 struct ixl_aq_buf *aqb; 4712 struct ixl_aq_desc *arq, *iaq; 4713 unsigned int prod = sc->sc_arq_prod; 4714 unsigned int n; 4715 int post = 0; 4716 4717 n = if_rxr_get(&sc->sc_arq_ring, IXL_AQ_NUM); 4718 arq = IXL_DMA_KVA(&sc->sc_arq); 4719 4720 while (n > 0) { 4721 aqb = SIMPLEQ_FIRST(&sc->sc_arq_idle); 4722 if (aqb != NULL) 4723 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_idle, aqb_entry); 4724 else if ((aqb = ixl_aqb_alloc(sc)) == NULL) 4725 break; 4726 4727 memset(aqb->aqb_data, 0, IXL_AQ_BUFLEN); 4728 4729 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 4730 BUS_DMASYNC_PREREAD); 4731 4732 iaq = &arq[prod]; 4733 iaq->iaq_flags = htole16(IXL_AQ_BUF | 4734 (IXL_AQ_BUFLEN > I40E_AQ_LARGE_BUF ? IXL_AQ_LB : 0)); 4735 iaq->iaq_opcode = 0; 4736 iaq->iaq_datalen = htole16(IXL_AQ_BUFLEN); 4737 iaq->iaq_retval = 0; 4738 iaq->iaq_cookie = 0; 4739 iaq->iaq_param[0] = 0; 4740 iaq->iaq_param[1] = 0; 4741 ixl_aq_dva(iaq, aqb->aqb_map->dm_segs[0].ds_addr); 4742 4743 SIMPLEQ_INSERT_TAIL(&sc->sc_arq_live, aqb, aqb_entry); 4744 4745 prod++; 4746 prod &= IXL_AQ_MASK; 4747 4748 post = 1; 4749 4750 n--; 4751 } 4752 4753 if_rxr_put(&sc->sc_arq_ring, n); 4754 sc->sc_arq_prod = prod; 4755 4756 return (post); 4757 } 4758 4759 static void 4760 ixl_arq_unfill(struct ixl_softc *sc) 4761 { 4762 struct ixl_aq_buf *aqb; 4763 4764 while ((aqb = SIMPLEQ_FIRST(&sc->sc_arq_live)) != NULL) { 4765 SIMPLEQ_REMOVE_HEAD(&sc->sc_arq_live, aqb_entry); 4766 4767 bus_dmamap_sync(sc->sc_dmat, aqb->aqb_map, 0, IXL_AQ_BUFLEN, 4768 BUS_DMASYNC_POSTREAD); 4769 ixl_aqb_free(sc, aqb); 4770 } 4771 } 4772 4773 static void 4774 ixl_clear_hw(struct ixl_softc *sc) 4775 { 4776 uint32_t num_queues, base_queue; 4777 uint32_t num_pf_int; 4778 uint32_t num_vf_int; 4779 uint32_t num_vfs; 4780 uint32_t i, j; 4781 uint32_t val; 4782 4783 /* get number of interrupts, queues, and vfs */ 4784 val = ixl_rd(sc, I40E_GLPCI_CNF2); 4785 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 4786 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 4787 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 4788 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 4789 4790 val = ixl_rd(sc, I40E_PFLAN_QALLOC); 4791 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 4792 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 4793 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 4794 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 4795 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 4796 num_queues = (j - base_queue) + 1; 4797 else 4798 num_queues = 0; 4799 4800 val = ixl_rd(sc, I40E_PF_VT_PFALLOC); 4801 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 4802 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 4803 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 4804 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 4805 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 4806 num_vfs = (j - i) + 1; 4807 else 4808 num_vfs = 0; 4809 4810 /* stop all the interrupts */ 4811 ixl_wr(sc, I40E_PFINT_ICR0_ENA, 0); 4812 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 4813 for (i = 0; i < num_pf_int - 2; i++) 4814 ixl_wr(sc, I40E_PFINT_DYN_CTLN(i), val); 4815 4816 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 4817 val = I40E_QUEUE_TYPE_EOL << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4818 ixl_wr(sc, I40E_PFINT_LNKLST0, val); 4819 for (i = 0; i < num_pf_int - 2; i++) 4820 ixl_wr(sc, I40E_PFINT_LNKLSTN(i), val); 4821 val = I40E_QUEUE_TYPE_EOL << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 4822 for (i = 0; i < num_vfs; i++) 4823 ixl_wr(sc, I40E_VPINT_LNKLST0(i), val); 4824 for (i = 0; i < num_vf_int - 2; i++) 4825 ixl_wr(sc, I40E_VPINT_LNKLSTN(i), val); 4826 4827 /* warn the HW of the coming Tx disables */ 4828 for (i = 0; i < num_queues; i++) { 4829 uint32_t abs_queue_idx = base_queue + i; 4830 uint32_t reg_block = 0; 4831 4832 if (abs_queue_idx >= 128) { 4833 reg_block = abs_queue_idx / 128; 4834 abs_queue_idx %= 128; 4835 } 4836 4837 val = ixl_rd(sc, I40E_GLLAN_TXPRE_QDIS(reg_block)); 4838 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 4839 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 4840 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 4841 4842 ixl_wr(sc, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 4843 } 4844 delaymsec(400); 4845 4846 /* stop all the queues */ 4847 for (i = 0; i < num_queues; i++) { 4848 ixl_wr(sc, I40E_QINT_TQCTL(i), 0); 4849 ixl_wr(sc, I40E_QTX_ENA(i), 0); 4850 ixl_wr(sc, I40E_QINT_RQCTL(i), 0); 4851 ixl_wr(sc, I40E_QRX_ENA(i), 0); 4852 } 4853 4854 /* short wait for all queue disables to settle */ 4855 delaymsec(50); 4856 } 4857 4858 static int 4859 ixl_pf_reset(struct ixl_softc *sc) 4860 { 4861 uint32_t cnt = 0; 4862 uint32_t cnt1 = 0; 4863 uint32_t reg = 0; 4864 uint32_t grst_del; 4865 4866 /* 4867 * Poll for Global Reset steady state in case of recent GRST. 4868 * The grst delay value is in 100ms units, and we'll wait a 4869 * couple counts longer to be sure we don't just miss the end. 4870 */ 4871 grst_del = ixl_rd(sc, I40E_GLGEN_RSTCTL); 4872 grst_del &= I40E_GLGEN_RSTCTL_GRSTDEL_MASK; 4873 grst_del >>= I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 4874 grst_del += 10; 4875 4876 for (cnt = 0; cnt < grst_del; cnt++) { 4877 reg = ixl_rd(sc, I40E_GLGEN_RSTAT); 4878 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 4879 break; 4880 delaymsec(100); 4881 } 4882 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 4883 printf(", Global reset polling failed to complete\n"); 4884 return (-1); 4885 } 4886 4887 /* Now Wait for the FW to be ready */ 4888 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 4889 reg = ixl_rd(sc, I40E_GLNVM_ULD); 4890 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4891 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 4892 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4893 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) 4894 break; 4895 4896 delaymsec(10); 4897 } 4898 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 4899 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 4900 printf(", wait for FW Reset complete timed out " 4901 "(I40E_GLNVM_ULD = 0x%x)\n", reg); 4902 return (-1); 4903 } 4904 4905 /* 4906 * If there was a Global Reset in progress when we got here, 4907 * we don't need to do the PF Reset 4908 */ 4909 if (cnt == 0) { 4910 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 4911 ixl_wr(sc, I40E_PFGEN_CTRL, reg | I40E_PFGEN_CTRL_PFSWR_MASK); 4912 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 4913 reg = ixl_rd(sc, I40E_PFGEN_CTRL); 4914 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 4915 break; 4916 delaymsec(1); 4917 } 4918 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 4919 printf(", PF reset polling failed to complete" 4920 "(I40E_PFGEN_CTRL= 0x%x)\n", reg); 4921 return (-1); 4922 } 4923 } 4924 4925 return (0); 4926 } 4927 4928 static uint32_t 4929 ixl_710_rd_ctl(struct ixl_softc *sc, uint32_t r) 4930 { 4931 struct ixl_atq iatq; 4932 struct ixl_aq_desc *iaq; 4933 uint16_t retval; 4934 4935 memset(&iatq, 0, sizeof(iatq)); 4936 iaq = &iatq.iatq_desc; 4937 iaq->iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_READ); 4938 htolem32(&iaq->iaq_param[1], r); 4939 4940 ixl_atq_exec(sc, &iatq, "ixl710rd"); 4941 4942 retval = lemtoh16(&iaq->iaq_retval); 4943 if (retval != IXL_AQ_RC_OK) { 4944 printf("%s: %s failed (%u)\n", DEVNAME(sc), __func__, retval); 4945 return (~0U); 4946 } 4947 4948 return (lemtoh32(&iaq->iaq_param[3])); 4949 } 4950 4951 static void 4952 ixl_710_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 4953 { 4954 struct ixl_atq iatq; 4955 struct ixl_aq_desc *iaq; 4956 uint16_t retval; 4957 4958 memset(&iatq, 0, sizeof(iatq)); 4959 iaq = &iatq.iatq_desc; 4960 iaq->iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_WRITE); 4961 htolem32(&iaq->iaq_param[1], r); 4962 htolem32(&iaq->iaq_param[3], v); 4963 4964 ixl_atq_exec(sc, &iatq, "ixl710wr"); 4965 4966 retval = lemtoh16(&iaq->iaq_retval); 4967 if (retval != IXL_AQ_RC_OK) { 4968 printf("%s: %s %08x=%08x failed (%u)\n", 4969 DEVNAME(sc), __func__, r, v, retval); 4970 } 4971 } 4972 4973 static int 4974 ixl_710_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 4975 { 4976 unsigned int i; 4977 4978 for (i = 0; i < nitems(rsskey->key); i++) 4979 ixl_wr_ctl(sc, I40E_PFQF_HKEY(i), rsskey->key[i]); 4980 4981 return (0); 4982 } 4983 4984 static int 4985 ixl_710_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 4986 { 4987 unsigned int i; 4988 4989 for (i = 0; i < nitems(lut->entries); i++) 4990 ixl_wr(sc, I40E_PFQF_HLUT(i), lut->entries[i]); 4991 4992 return (0); 4993 } 4994 4995 static uint32_t 4996 ixl_722_rd_ctl(struct ixl_softc *sc, uint32_t r) 4997 { 4998 return (ixl_rd(sc, r)); 4999 } 5000 5001 static void 5002 ixl_722_wr_ctl(struct ixl_softc *sc, uint32_t r, uint32_t v) 5003 { 5004 ixl_wr(sc, r, v); 5005 } 5006 5007 static int 5008 ixl_722_set_rss_key(struct ixl_softc *sc, const struct ixl_rss_key *rsskey) 5009 { 5010 /* XXX */ 5011 5012 return (0); 5013 } 5014 5015 static int 5016 ixl_722_set_rss_lut(struct ixl_softc *sc, const struct ixl_rss_lut_128 *lut) 5017 { 5018 /* XXX */ 5019 5020 return (0); 5021 } 5022 5023 static int 5024 ixl_dmamem_alloc(struct ixl_softc *sc, struct ixl_dmamem *ixm, 5025 bus_size_t size, u_int align) 5026 { 5027 ixm->ixm_size = size; 5028 5029 if (bus_dmamap_create(sc->sc_dmat, ixm->ixm_size, 1, 5030 ixm->ixm_size, 0, 5031 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT, 5032 &ixm->ixm_map) != 0) 5033 return (1); 5034 if (bus_dmamem_alloc(sc->sc_dmat, ixm->ixm_size, 5035 align, 0, &ixm->ixm_seg, 1, &ixm->ixm_nsegs, 5036 BUS_DMA_WAITOK | BUS_DMA_ZERO) != 0) 5037 goto destroy; 5038 if (bus_dmamem_map(sc->sc_dmat, &ixm->ixm_seg, ixm->ixm_nsegs, 5039 ixm->ixm_size, &ixm->ixm_kva, BUS_DMA_WAITOK) != 0) 5040 goto free; 5041 if (bus_dmamap_load(sc->sc_dmat, ixm->ixm_map, ixm->ixm_kva, 5042 ixm->ixm_size, NULL, BUS_DMA_WAITOK) != 0) 5043 goto unmap; 5044 5045 return (0); 5046 unmap: 5047 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5048 free: 5049 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5050 destroy: 5051 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5052 return (1); 5053 } 5054 5055 static void 5056 ixl_dmamem_free(struct ixl_softc *sc, struct ixl_dmamem *ixm) 5057 { 5058 bus_dmamap_unload(sc->sc_dmat, ixm->ixm_map); 5059 bus_dmamem_unmap(sc->sc_dmat, ixm->ixm_kva, ixm->ixm_size); 5060 bus_dmamem_free(sc->sc_dmat, &ixm->ixm_seg, 1); 5061 bus_dmamap_destroy(sc->sc_dmat, ixm->ixm_map); 5062 } 5063 5064 #if NKSTAT > 0 5065 5066 CTASSERT(KSTAT_KV_U_NONE <= 0xffU); 5067 CTASSERT(KSTAT_KV_U_PACKETS <= 0xffU); 5068 CTASSERT(KSTAT_KV_U_BYTES <= 0xffU); 5069 5070 struct ixl_counter { 5071 const char *c_name; 5072 uint32_t c_base; 5073 uint8_t c_width; 5074 uint8_t c_type; 5075 }; 5076 5077 const struct ixl_counter ixl_port_counters[] = { 5078 /* GORC */ 5079 { "rx bytes", 0x00300000, 48, KSTAT_KV_U_BYTES }, 5080 /* MLFC */ 5081 { "mac local errs", 0x00300020, 32, KSTAT_KV_U_NONE }, 5082 /* MRFC */ 5083 { "mac remote errs", 0x00300040, 32, KSTAT_KV_U_NONE }, 5084 /* MSPDC */ 5085 { "mac short", 0x00300060, 32, KSTAT_KV_U_PACKETS }, 5086 /* CRCERRS */ 5087 { "crc errs", 0x00300080, 32, KSTAT_KV_U_PACKETS }, 5088 /* RLEC */ 5089 { "rx len errs", 0x003000a0, 32, KSTAT_KV_U_PACKETS }, 5090 /* ERRBC */ 5091 { "byte errs", 0x003000c0, 32, KSTAT_KV_U_PACKETS }, 5092 /* ILLERRC */ 5093 { "illegal byte", 0x003000d0, 32, KSTAT_KV_U_PACKETS }, 5094 /* RUC */ 5095 { "rx undersize", 0x00300100, 32, KSTAT_KV_U_PACKETS }, 5096 /* ROC */ 5097 { "rx oversize", 0x00300120, 32, KSTAT_KV_U_PACKETS }, 5098 /* LXONRXCNT */ 5099 { "rx link xon", 0x00300140, 32, KSTAT_KV_U_PACKETS }, 5100 /* LXOFFRXCNT */ 5101 { "rx link xoff", 0x00300160, 32, KSTAT_KV_U_PACKETS }, 5102 5103 /* Priority XON Received Count */ 5104 /* Priority XOFF Received Count */ 5105 /* Priority XON to XOFF Count */ 5106 5107 /* PRC64 */ 5108 { "rx 64B", 0x00300480, 48, KSTAT_KV_U_PACKETS }, 5109 /* PRC127 */ 5110 { "rx 65-127B", 0x003004A0, 48, KSTAT_KV_U_PACKETS }, 5111 /* PRC255 */ 5112 { "rx 128-255B", 0x003004C0, 48, KSTAT_KV_U_PACKETS }, 5113 /* PRC511 */ 5114 { "rx 256-511B", 0x003004E0, 48, KSTAT_KV_U_PACKETS }, 5115 /* PRC1023 */ 5116 { "rx 512-1023B", 0x00300500, 48, KSTAT_KV_U_PACKETS }, 5117 /* PRC1522 */ 5118 { "rx 1024-1522B", 0x00300520, 48, KSTAT_KV_U_PACKETS }, 5119 /* PRC9522 */ 5120 { "rx 1523-9522B", 0x00300540, 48, KSTAT_KV_U_PACKETS }, 5121 /* ROC */ 5122 { "rx fragment", 0x00300560, 32, KSTAT_KV_U_PACKETS }, 5123 /* RJC */ 5124 { "rx jabber", 0x00300580, 32, KSTAT_KV_U_PACKETS }, 5125 /* UPRC */ 5126 { "rx ucasts", 0x003005a0, 48, KSTAT_KV_U_PACKETS }, 5127 /* MPRC */ 5128 { "rx mcasts", 0x003005c0, 48, KSTAT_KV_U_PACKETS }, 5129 /* BPRC */ 5130 { "rx bcasts", 0x003005e0, 48, KSTAT_KV_U_PACKETS }, 5131 /* RDPC */ 5132 { "rx discards", 0x00300600, 32, KSTAT_KV_U_PACKETS }, 5133 /* LDPC */ 5134 { "rx lo discards", 0x00300620, 32, KSTAT_KV_U_PACKETS }, 5135 /* RUPP */ 5136 { "rx no dest", 0x00300660, 32, KSTAT_KV_U_PACKETS }, 5137 5138 /* GOTC */ 5139 { "tx bytes", 0x00300680, 48, KSTAT_KV_U_BYTES }, 5140 /* PTC64 */ 5141 { "tx 64B", 0x003006A0, 48, KSTAT_KV_U_PACKETS }, 5142 /* PTC127 */ 5143 { "tx 65-127B", 0x003006C0, 48, KSTAT_KV_U_PACKETS }, 5144 /* PTC255 */ 5145 { "tx 128-255B", 0x003006E0, 48, KSTAT_KV_U_PACKETS }, 5146 /* PTC511 */ 5147 { "tx 256-511B", 0x00300700, 48, KSTAT_KV_U_PACKETS }, 5148 /* PTC1023 */ 5149 { "tx 512-1023B", 0x00300720, 48, KSTAT_KV_U_PACKETS }, 5150 /* PTC1522 */ 5151 { "tx 1024-1522B", 0x00300740, 48, KSTAT_KV_U_PACKETS }, 5152 /* PTC9522 */ 5153 { "tx 1523-9522B", 0x00300760, 48, KSTAT_KV_U_PACKETS }, 5154 5155 /* Priority XON Transmitted Count */ 5156 /* Priority XOFF Transmitted Count */ 5157 5158 /* LXONTXC */ 5159 { "tx link xon", 0x00300980, 48, KSTAT_KV_U_PACKETS }, 5160 /* LXOFFTXC */ 5161 { "tx link xoff", 0x003009a0, 48, KSTAT_KV_U_PACKETS }, 5162 /* UPTC */ 5163 { "tx ucasts", 0x003009c0, 48, KSTAT_KV_U_PACKETS }, 5164 /* MPTC */ 5165 { "tx mcasts", 0x003009e0, 48, KSTAT_KV_U_PACKETS }, 5166 /* BPTC */ 5167 { "tx bcasts", 0x00300a00, 48, KSTAT_KV_U_PACKETS }, 5168 /* TDOLD */ 5169 { "tx link down", 0x00300a20, 48, KSTAT_KV_U_PACKETS }, 5170 }; 5171 5172 const struct ixl_counter ixl_vsi_counters[] = { 5173 /* VSI RDPC */ 5174 { "rx discards", 0x00310000, 32, KSTAT_KV_U_PACKETS }, 5175 /* VSI GOTC */ 5176 { "tx bytes", 0x00328000, 48, KSTAT_KV_U_BYTES }, 5177 /* VSI UPTC */ 5178 { "tx ucasts", 0x0033c000, 48, KSTAT_KV_U_PACKETS }, 5179 /* VSI MPTC */ 5180 { "tx mcasts", 0x0033cc00, 48, KSTAT_KV_U_PACKETS }, 5181 /* VSI BPTC */ 5182 { "tx bcasts", 0x0033d800, 48, KSTAT_KV_U_PACKETS }, 5183 /* VSI TEPC */ 5184 { "tx errs", 0x00344000, 48, KSTAT_KV_U_PACKETS }, 5185 /* VSI TDPC */ 5186 { "tx discards", 0x00348000, 48, KSTAT_KV_U_PACKETS }, 5187 /* VSI GORC */ 5188 { "rx bytes", 0x00358000, 48, KSTAT_KV_U_BYTES }, 5189 /* VSI UPRC */ 5190 { "rx ucasts", 0x0036c000, 48, KSTAT_KV_U_PACKETS }, 5191 /* VSI MPRC */ 5192 { "rx mcasts", 0x0036cc00, 48, KSTAT_KV_U_PACKETS }, 5193 /* VSI BPRC */ 5194 { "rx bcasts", 0x0036d800, 48, KSTAT_KV_U_PACKETS }, 5195 /* VSI RUPP */ 5196 { "rx noproto", 0x0036e400, 32, KSTAT_KV_U_PACKETS }, 5197 }; 5198 5199 struct ixl_counter_state { 5200 const struct ixl_counter 5201 *counters; 5202 uint64_t *values; 5203 size_t n; 5204 uint32_t index; 5205 unsigned int gen; 5206 }; 5207 5208 static void 5209 ixl_rd_counters(struct ixl_softc *sc, const struct ixl_counter_state *state, 5210 uint64_t *vs) 5211 { 5212 const struct ixl_counter *c; 5213 bus_addr_t r; 5214 uint64_t v; 5215 size_t i; 5216 5217 for (i = 0; i < state->n; i++) { 5218 c = &state->counters[i]; 5219 5220 r = c->c_base + (state->index * 8); 5221 5222 if (c->c_width == 32) 5223 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, r); 5224 else 5225 v = bus_space_read_8(sc->sc_memt, sc->sc_memh, r); 5226 5227 vs[i] = v; 5228 } 5229 } 5230 5231 static int 5232 ixl_kstat_read(struct kstat *ks) 5233 { 5234 struct ixl_softc *sc = ks->ks_softc; 5235 struct kstat_kv *kvs = ks->ks_data; 5236 struct ixl_counter_state *state = ks->ks_ptr; 5237 unsigned int gen = (state->gen++) & 1; 5238 uint64_t *ovs = state->values + (gen * state->n); 5239 uint64_t *nvs = state->values + (!gen * state->n); 5240 size_t i; 5241 5242 ixl_rd_counters(sc, state, nvs); 5243 getnanouptime(&ks->ks_updated); 5244 5245 for (i = 0; i < state->n; i++) { 5246 const struct ixl_counter *c = &state->counters[i]; 5247 uint64_t n = nvs[i], o = ovs[i]; 5248 5249 if (c->c_width < 64) { 5250 if (n < o) 5251 n += (1ULL << c->c_width); 5252 } 5253 5254 kstat_kv_u64(&kvs[i]) += (n - o); 5255 } 5256 5257 return (0); 5258 } 5259 5260 static void 5261 ixl_kstat_tick(void *arg) 5262 { 5263 struct ixl_softc *sc = arg; 5264 5265 timeout_add_sec(&sc->sc_kstat_tmo, 4); 5266 5267 mtx_enter(&sc->sc_kstat_mtx); 5268 5269 ixl_kstat_read(sc->sc_port_kstat); 5270 ixl_kstat_read(sc->sc_vsi_kstat); 5271 5272 mtx_leave(&sc->sc_kstat_mtx); 5273 } 5274 5275 static struct kstat * 5276 ixl_kstat_create(struct ixl_softc *sc, const char *name, 5277 const struct ixl_counter *counters, size_t n, uint32_t index) 5278 { 5279 struct kstat *ks; 5280 struct kstat_kv *kvs; 5281 struct ixl_counter_state *state; 5282 const struct ixl_counter *c; 5283 unsigned int i; 5284 5285 ks = kstat_create(DEVNAME(sc), 0, name, 0, KSTAT_T_KV, 0); 5286 if (ks == NULL) { 5287 /* unable to create kstats */ 5288 return (NULL); 5289 } 5290 5291 kvs = mallocarray(n, sizeof(*kvs), M_DEVBUF, M_WAITOK|M_ZERO); 5292 for (i = 0; i < n; i++) { 5293 c = &counters[i]; 5294 5295 kstat_kv_unit_init(&kvs[i], c->c_name, 5296 KSTAT_KV_T_COUNTER64, c->c_type); 5297 } 5298 5299 ks->ks_data = kvs; 5300 ks->ks_datalen = n * sizeof(*kvs); 5301 ks->ks_read = ixl_kstat_read; 5302 5303 state = malloc(sizeof(*state), M_DEVBUF, M_WAITOK|M_ZERO); 5304 state->counters = counters; 5305 state->n = n; 5306 state->values = mallocarray(n * 2, sizeof(*state->values), 5307 M_DEVBUF, M_WAITOK|M_ZERO); 5308 state->index = index; 5309 ks->ks_ptr = state; 5310 5311 kstat_set_mutex(ks, &sc->sc_kstat_mtx); 5312 ks->ks_softc = sc; 5313 kstat_install(ks); 5314 5315 /* fetch a baseline */ 5316 ixl_rd_counters(sc, state, state->values); 5317 5318 return (ks); 5319 } 5320 5321 static void 5322 ixl_kstat_attach(struct ixl_softc *sc) 5323 { 5324 mtx_init(&sc->sc_kstat_mtx, IPL_SOFTCLOCK); 5325 timeout_set(&sc->sc_kstat_tmo, ixl_kstat_tick, sc); 5326 5327 sc->sc_port_kstat = ixl_kstat_create(sc, "ixl-port", 5328 ixl_port_counters, nitems(ixl_port_counters), sc->sc_port); 5329 sc->sc_vsi_kstat = ixl_kstat_create(sc, "ixl-vsi", 5330 ixl_vsi_counters, nitems(ixl_vsi_counters), 5331 lemtoh16(&sc->sc_vsi_number)); 5332 5333 /* ixl counters go up even when the interface is down */ 5334 timeout_add_sec(&sc->sc_kstat_tmo, 4); 5335 } 5336 5337 #endif /* NKSTAT > 0 */ 5338