1 /* $OpenBSD: if_lii.c,v 1.29 2010/08/31 17:13:44 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2007 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller 31 */ 32 33 #include "bpfilter.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/sockio.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/malloc.h> 42 #include <sys/device.h> 43 #include <sys/timeout.h> 44 45 #include <machine/bus.h> 46 47 #include <net/if.h> 48 #include <net/if_dl.h> 49 #include <net/if_media.h> 50 #include <net/if_types.h> 51 52 #if NBPFILTER > 0 53 #include <net/bpf.h> 54 #endif 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/if_ether.h> 59 #endif 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/pci/if_liireg.h> 69 70 /*#define LII_DEBUG*/ 71 #ifdef LII_DEBUG 72 #define DPRINTF(x) printf x 73 #else 74 #define DPRINTF(x) 75 #endif 76 77 struct lii_softc { 78 struct device sc_dev; 79 pci_chipset_tag_t sc_pc; 80 pcitag_t sc_tag; 81 82 bus_space_tag_t sc_mmiot; 83 bus_space_handle_t sc_mmioh; 84 bus_size_t sc_mmios; 85 86 /* 87 * We allocate a big chunk of DMA-safe memory for all data exchanges. 88 * It is unfortunate that this chip doesn't seem to do scatter-gather. 89 */ 90 bus_dma_tag_t sc_dmat; 91 bus_dmamap_t sc_ringmap; 92 bus_dma_segment_t sc_ringseg; 93 94 uint8_t *sc_ring; /* the whole area */ 95 size_t sc_ringsize; 96 97 struct rx_pkt *sc_rxp; /* the part used for RX */ 98 struct tx_pkt_status *sc_txs; /* the parts used for TX */ 99 bus_addr_t sc_txsp; 100 char *sc_txdbase; 101 bus_addr_t sc_txdp; 102 103 unsigned int sc_rxcur; 104 /* the active area is [ack; cur[ */ 105 int sc_txs_cur; 106 int sc_txs_ack; 107 int sc_txd_cur; 108 int sc_txd_ack; 109 int sc_free_tx_slots; 110 111 void *sc_ih; 112 113 struct arpcom sc_ac; 114 struct mii_data sc_mii; 115 struct timeout sc_tick; 116 117 int (*sc_memread)(struct lii_softc *, uint32_t, 118 uint32_t *); 119 }; 120 121 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 122 123 int lii_match(struct device *, void *, void *); 124 void lii_attach(struct device *, struct device *, void *); 125 int lii_activate(struct device *, int); 126 127 struct cfdriver lii_cd = { 128 0, 129 "lii", 130 DV_IFNET 131 }; 132 133 struct cfattach lii_ca = { 134 sizeof(struct lii_softc), 135 lii_match, 136 lii_attach, 137 NULL, 138 lii_activate 139 }; 140 141 int lii_reset(struct lii_softc *); 142 int lii_eeprom_present(struct lii_softc *); 143 void lii_read_macaddr(struct lii_softc *, uint8_t *); 144 int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *); 145 void lii_spi_configure(struct lii_softc *); 146 int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *); 147 void lii_iff(struct lii_softc *); 148 void lii_tick(void *); 149 150 int lii_alloc_rings(struct lii_softc *); 151 int lii_free_tx_space(struct lii_softc *); 152 void lii_tx_put(struct lii_softc *, struct mbuf *); 153 154 int lii_mii_readreg(struct device *, int, int); 155 void lii_mii_writereg(struct device *, int, int, int); 156 void lii_mii_statchg(struct device *); 157 158 int lii_media_change(struct ifnet *); 159 void lii_media_status(struct ifnet *, struct ifmediareq *); 160 161 int lii_init(struct ifnet *); 162 void lii_start(struct ifnet *); 163 void lii_stop(struct ifnet *); 164 void lii_watchdog(struct ifnet *); 165 int lii_ioctl(struct ifnet *, u_long, caddr_t); 166 167 int lii_intr(void *); 168 void lii_rxintr(struct lii_softc *); 169 void lii_txintr(struct lii_softc *); 170 171 const struct pci_matchid lii_devices[] = { 172 { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2 } 173 }; 174 175 #define LII_READ_4(sc,reg) \ 176 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 177 #define LII_READ_2(sc,reg) \ 178 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 179 #define LII_READ_1(sc,reg) \ 180 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg)) 181 #define LII_WRITE_4(sc,reg,val) \ 182 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 183 #define LII_WRITE_2(sc,reg,val) \ 184 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 185 #define LII_WRITE_1(sc,reg,val) \ 186 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val)) 187 188 /* 189 * Those are the default Linux parameters. 190 */ 191 192 #define AT_TXD_NUM 64 193 #define AT_TXD_BUFFER_SIZE 8192 194 #define AT_RXD_NUM 64 195 196 /* Pad the RXD buffer so that the packets are on a 128-byte boundary. */ 197 #define AT_RXD_PADDING 120 198 199 int 200 lii_match(struct device *parent, void *match, void *aux) 201 { 202 return (pci_matchbyid((struct pci_attach_args *)aux, lii_devices, 203 nitems(lii_devices))); 204 } 205 206 void 207 lii_attach(struct device *parent, struct device *self, void *aux) 208 { 209 struct lii_softc *sc = (struct lii_softc *)self; 210 struct pci_attach_args *pa = aux; 211 struct ifnet *ifp = &sc->sc_ac.ac_if; 212 pci_intr_handle_t ih; 213 pcireg_t memtype; 214 215 sc->sc_pc = pa->pa_pc; 216 sc->sc_tag = pa->pa_tag; 217 sc->sc_dmat = pa->pa_dmat; 218 219 memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START); 220 if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_mmiot, 221 &sc->sc_mmioh, NULL, &sc->sc_mmios, 0)) { 222 printf(": can't map mem space\n"); 223 return; 224 } 225 226 if (lii_reset(sc)) 227 goto unmap; 228 229 lii_spi_configure(sc); 230 231 if (lii_eeprom_present(sc)) 232 sc->sc_memread = lii_eeprom_read; 233 else 234 sc->sc_memread = lii_spi_read; 235 236 lii_read_macaddr(sc, sc->sc_ac.ac_enaddr); 237 238 if (pci_intr_map(pa, &ih) != 0) { 239 printf(": can't map interrupt\n"); 240 goto unmap; 241 } 242 sc->sc_ih = pci_intr_establish(sc->sc_pc, ih, IPL_NET, 243 lii_intr, sc, DEVNAME(sc)); 244 if (sc->sc_ih == NULL) { 245 printf(": can't establish interrupt\n"); 246 goto unmap; 247 } 248 249 if (lii_alloc_rings(sc)) 250 goto deintr; 251 252 printf(": %s, address %s\n", pci_intr_string(sc->sc_pc, ih), 253 ether_sprintf(sc->sc_ac.ac_enaddr)); 254 255 timeout_set(&sc->sc_tick, lii_tick, sc); 256 257 sc->sc_mii.mii_ifp = ifp; 258 sc->sc_mii.mii_readreg = lii_mii_readreg; 259 sc->sc_mii.mii_writereg = lii_mii_writereg; 260 sc->sc_mii.mii_statchg = lii_mii_statchg; 261 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, lii_media_change, 262 lii_media_status); 263 mii_attach(self, &sc->sc_mii, 0xffffffff, 1, 264 MII_OFFSET_ANY, 0); 265 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 266 267 strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ); 268 ifp->if_softc = sc; 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_capabilities = IFCAP_VLAN_MTU; 271 ifp->if_ioctl = lii_ioctl; 272 ifp->if_start = lii_start; 273 ifp->if_watchdog = lii_watchdog; 274 IFQ_SET_READY(&ifp->if_snd); 275 276 if_attach(ifp); 277 ether_ifattach(ifp); 278 279 return; 280 281 deintr: 282 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 283 unmap: 284 bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, sc->sc_mmios); 285 return; 286 } 287 288 int 289 lii_activate(struct device *self, int act) 290 { 291 struct lii_softc *sc = (struct lii_softc *)self; 292 struct ifnet *ifp = &sc->sc_ac.ac_if; 293 int rv = 0; 294 295 switch (act) { 296 case DVACT_QUIESCE: 297 rv = config_activate_children(self, act); 298 break; 299 case DVACT_SUSPEND: 300 if (ifp->if_flags & IFF_RUNNING) 301 lii_stop(ifp); 302 rv = config_activate_children(self, act); 303 break; 304 case DVACT_RESUME: 305 rv = config_activate_children(self, act); 306 if (ifp->if_flags & IFF_UP) 307 lii_init(ifp); 308 break; 309 } 310 return (rv); 311 } 312 313 int 314 lii_reset(struct lii_softc *sc) 315 { 316 int i; 317 318 DPRINTF(("lii_reset\n")); 319 320 LII_WRITE_4(sc, LII_SMC, SMC_SOFT_RST); 321 DELAY(1000); 322 323 for (i = 0; i < 10; ++i) { 324 if (LII_READ_4(sc, LII_BIS) == 0) 325 break; 326 DELAY(1000); 327 } 328 329 if (i == 10) { 330 printf("%s: reset failed\n", DEVNAME(sc)); 331 return 1; 332 } 333 334 LII_WRITE_4(sc, LII_PHYC, PHYC_ENABLE); 335 DELAY(10); 336 337 /* Init PCI-Express module */ 338 /* Magic Numbers Warning */ 339 LII_WRITE_4(sc, 0x12fc, 0x00006500); 340 LII_WRITE_4(sc, 0x1008, 0x00008000 | 341 LII_READ_4(sc, 0x1008)); 342 343 return 0; 344 } 345 346 int 347 lii_eeprom_present(struct lii_softc *sc) 348 { 349 uint32_t val; 350 351 val = LII_READ_4(sc, LII_SFC); 352 if (val & SFC_EN_VPD) 353 LII_WRITE_4(sc, LII_SFC, val & ~(SFC_EN_VPD)); 354 355 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD, 356 NULL, NULL) == 1; 357 } 358 359 int 360 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 361 { 362 return pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val); 363 } 364 365 void 366 lii_spi_configure(struct lii_softc *sc) 367 { 368 /* 369 * We don't offer a way to configure the SPI Flash vendor parameter, so 370 * the table is given for reference 371 */ 372 static const struct lii_spi_flash_vendor { 373 const char *sfv_name; 374 const uint8_t sfv_opcodes[9]; 375 } lii_sfv[] = { 376 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } }, 377 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } }, 378 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } }, 379 }; 380 #define SF_OPCODE_WRSR 0 381 #define SF_OPCODE_READ 1 382 #define SF_OPCODE_PRGM 2 383 #define SF_OPCODE_WREN 3 384 #define SF_OPCODE_WRDI 4 385 #define SF_OPCODE_RDSR 5 386 #define SF_OPCODE_RDID 6 387 #define SF_OPCODE_SECT_ER 7 388 #define SF_OPCODE_CHIP_ER 8 389 390 #define SF_DEFAULT_VENDOR 0 391 static const uint8_t vendor = SF_DEFAULT_VENDOR; 392 393 /* 394 * Why isn't WRDI used? Heck if I know. 395 */ 396 397 LII_WRITE_1(sc, LII_SFOP_WRSR, 398 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]); 399 LII_WRITE_1(sc, LII_SFOP_READ, 400 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]); 401 LII_WRITE_1(sc, LII_SFOP_PROGRAM, 402 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]); 403 LII_WRITE_1(sc, LII_SFOP_WREN, 404 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]); 405 LII_WRITE_1(sc, LII_SFOP_RDSR, 406 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]); 407 LII_WRITE_1(sc, LII_SFOP_RDID, 408 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]); 409 LII_WRITE_1(sc, LII_SFOP_SC_ERASE, 410 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]); 411 LII_WRITE_1(sc, LII_SFOP_CHIP_ERASE, 412 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]); 413 } 414 415 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \ 416 ( (((cssetup) & SFC_CS_SETUP_MASK) \ 417 << SFC_CS_SETUP_SHIFT) \ 418 | (((clkhi) & SFC_CLK_HI_MASK) \ 419 << SFC_CLK_HI_SHIFT) \ 420 | (((clklo) & SFC_CLK_LO_MASK) \ 421 << SFC_CLK_LO_SHIFT) \ 422 | (((cshold) & SFC_CS_HOLD_MASK) \ 423 << SFC_CS_HOLD_SHIFT) \ 424 | (((cshi) & SFC_CS_HI_MASK) \ 425 << SFC_CS_HI_SHIFT) \ 426 | (((ins) & SFC_INS_MASK) \ 427 << SFC_INS_SHIFT)) 428 429 #define CUSTOM_SPI_CS_SETUP 2 430 #define CUSTOM_SPI_CLK_HI 2 431 #define CUSTOM_SPI_CLK_LO 2 432 #define CUSTOM_SPI_CS_HOLD 2 433 #define CUSTOM_SPI_CS_HI 3 434 435 int 436 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val) 437 { 438 uint32_t v; 439 int i; 440 441 LII_WRITE_4(sc, LII_SF_DATA, 0); 442 LII_WRITE_4(sc, LII_SF_ADDR, reg); 443 444 v = SFC_WAIT_READY | 445 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI, 446 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1); 447 448 LII_WRITE_4(sc, LII_SFC, v); 449 v |= SFC_START; 450 LII_WRITE_4(sc, LII_SFC, v); 451 452 for (i = 0; i < 10; ++i) { 453 DELAY(1000); 454 if (!(LII_READ_4(sc, LII_SFC) & SFC_START)) 455 break; 456 } 457 if (i == 10) 458 return EBUSY; 459 460 *val = LII_READ_4(sc, LII_SF_DATA); 461 return 0; 462 } 463 464 void 465 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea) 466 { 467 uint32_t offset = 0x100; 468 uint32_t val, val1, addr0 = 0, addr1 = 0; 469 uint8_t found = 0; 470 471 while ((*sc->sc_memread)(sc, offset, &val) == 0) { 472 offset += 4; 473 474 /* Each chunk of data starts with a signature */ 475 if ((val & 0xff) != 0x5a) 476 break; 477 if ((*sc->sc_memread)(sc, offset, &val1)) 478 break; 479 480 offset += 4; 481 482 val >>= 16; 483 switch (val) { 484 case LII_MAC_ADDR_0: 485 addr0 = val1; 486 ++found; 487 break; 488 case LII_MAC_ADDR_1: 489 addr1 = val1; 490 ++found; 491 break; 492 default: 493 continue; 494 } 495 } 496 497 #ifdef LII_DEBUG 498 if (found < 2) 499 printf(": error reading MAC address, using registers...\n"); 500 #endif 501 502 addr0 = htole32(addr0); 503 addr1 = htole32(addr1); 504 505 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) || 506 (addr0 == 0 && (addr1 & 0xffff) == 0)) { 507 addr0 = htole32(LII_READ_4(sc, LII_MAC_ADDR_0)); 508 addr1 = htole32(LII_READ_4(sc, LII_MAC_ADDR_1)); 509 } 510 511 ea[0] = (addr1 & 0x0000ff00) >> 8; 512 ea[1] = (addr1 & 0x000000ff); 513 ea[2] = (addr0 & 0xff000000) >> 24; 514 ea[3] = (addr0 & 0x00ff0000) >> 16; 515 ea[4] = (addr0 & 0x0000ff00) >> 8; 516 ea[5] = (addr0 & 0x000000ff); 517 } 518 519 int 520 lii_mii_readreg(struct device *dev, int phy, int reg) 521 { 522 struct lii_softc *sc = (struct lii_softc *)dev; 523 uint32_t val; 524 int i; 525 526 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 527 528 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 529 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 530 531 val |= MDIOC_READ; 532 533 LII_WRITE_4(sc, LII_MDIOC, val); 534 535 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 536 DELAY(2); 537 val = LII_READ_4(sc, LII_MDIOC); 538 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 539 break; 540 } 541 542 if (i == MDIO_WAIT_TIMES) { 543 printf("%s: timeout reading PHY %d reg %d\n", DEVNAME(sc), phy, 544 reg); 545 } 546 547 return (val & 0x0000ffff); 548 } 549 550 void 551 lii_mii_writereg(struct device *dev, int phy, int reg, int data) 552 { 553 struct lii_softc *sc = (struct lii_softc *)dev; 554 uint32_t val; 555 int i; 556 557 val = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT; 558 val |= (data & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT; 559 560 val |= MDIOC_START | MDIOC_SUP_PREAMBLE; 561 val |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT; 562 563 /* val |= MDIOC_WRITE; */ 564 565 LII_WRITE_4(sc, LII_MDIOC, val); 566 567 for (i = 0; i < MDIO_WAIT_TIMES; ++i) { 568 DELAY(2); 569 val = LII_READ_4(sc, LII_MDIOC); 570 if ((val & (MDIOC_START | MDIOC_BUSY)) == 0) 571 break; 572 } 573 574 if (i == MDIO_WAIT_TIMES) { 575 printf("%s: timeout writing PHY %d reg %d\n", DEVNAME(sc), phy, 576 reg); 577 } 578 } 579 580 void 581 lii_mii_statchg(struct device *dev) 582 { 583 struct lii_softc *sc = (struct lii_softc *)dev; 584 uint32_t val; 585 586 DPRINTF(("lii_mii_statchg\n")); 587 588 val = LII_READ_4(sc, LII_MACC); 589 590 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX) 591 val |= MACC_FDX; 592 else 593 val &= ~MACC_FDX; 594 595 LII_WRITE_4(sc, LII_MACC, val); 596 } 597 598 int 599 lii_media_change(struct ifnet *ifp) 600 { 601 struct lii_softc *sc = ifp->if_softc; 602 603 DPRINTF(("lii_media_change\n")); 604 605 if (ifp->if_flags & IFF_UP) 606 mii_mediachg(&sc->sc_mii); 607 return 0; 608 } 609 610 void 611 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr) 612 { 613 struct lii_softc *sc = ifp->if_softc; 614 615 DPRINTF(("lii_media_status\n")); 616 617 mii_pollstat(&sc->sc_mii); 618 imr->ifm_status = sc->sc_mii.mii_media_status; 619 imr->ifm_active = sc->sc_mii.mii_media_active; 620 } 621 622 int 623 lii_init(struct ifnet *ifp) 624 { 625 struct lii_softc *sc = ifp->if_softc; 626 uint32_t val; 627 int error; 628 629 DPRINTF(("lii_init\n")); 630 631 lii_stop(ifp); 632 633 memset(sc->sc_ring, 0, sc->sc_ringsize); 634 635 /* Disable all interrupts */ 636 LII_WRITE_4(sc, LII_ISR, 0xffffffff); 637 638 LII_WRITE_4(sc, LII_DESC_BASE_ADDR_HI, 0); 639 /* XXX 640 sc->sc_ringmap->dm_segs[0].ds_addr >> 32); 641 */ 642 LII_WRITE_4(sc, LII_RXD_BASE_ADDR_LO, 643 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff) 644 + AT_RXD_PADDING); 645 LII_WRITE_4(sc, LII_TXS_BASE_ADDR_LO, 646 sc->sc_txsp & 0xffffffff); 647 LII_WRITE_4(sc, LII_TXD_BASE_ADDR_LO, 648 sc->sc_txdp & 0xffffffff); 649 650 LII_WRITE_2(sc, LII_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4); 651 LII_WRITE_2(sc, LII_TXS_NUM_ENTRIES, AT_TXD_NUM); 652 LII_WRITE_2(sc, LII_RXD_NUM_ENTRIES, AT_RXD_NUM); 653 654 /* 655 * Inter Paket Gap Time = 0x60 (IPGT) 656 * Minimum inter-frame gap for RX = 0x50 (MIFG) 657 * 64-bit Carrier-Sense window = 0x40 (IPGR1) 658 * 96-bit IPG window = 0x60 (IPGR2) 659 */ 660 LII_WRITE_4(sc, LII_MIPFG, 0x60405060); 661 662 /* 663 * Collision window = 0x37 (LCOL) 664 * Maximum # of retrans = 0xf (RETRY) 665 * Maximum binary expansion # = 0xa (ABEBT) 666 * IPG to start jam = 0x7 (JAMIPG) 667 */ 668 LII_WRITE_4(sc, LII_MHDC, 0x07a0f037 | 669 MHDC_EXC_DEF_EN); 670 671 /* 100 means 200us */ 672 LII_WRITE_2(sc, LII_IMTIV, 100); 673 LII_WRITE_2(sc, LII_SMC, SMC_ITIMER_EN); 674 675 /* 500000 means 100ms */ 676 LII_WRITE_2(sc, LII_IALTIV, 50000); 677 678 LII_WRITE_4(sc, LII_MTU, ifp->if_mtu + ETHER_HDR_LEN 679 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 680 681 /* unit unknown for TX cur-through threshold */ 682 LII_WRITE_4(sc, LII_TX_CUT_THRESH, 0x177); 683 684 LII_WRITE_2(sc, LII_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8); 685 LII_WRITE_2(sc, LII_PAUSE_OFF_TH, AT_RXD_NUM / 12); 686 687 sc->sc_rxcur = 0; 688 sc->sc_txs_cur = sc->sc_txs_ack = 0; 689 sc->sc_txd_cur = sc->sc_txd_ack = 0; 690 sc->sc_free_tx_slots = 1; 691 LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur); 692 LII_WRITE_2(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); 693 694 LII_WRITE_1(sc, LII_DMAR, DMAR_EN); 695 LII_WRITE_1(sc, LII_DMAW, DMAW_EN); 696 697 LII_WRITE_4(sc, LII_SMC, LII_READ_4(sc, LII_SMC) | SMC_MANUAL_INT); 698 699 error = ((LII_READ_4(sc, LII_ISR) & ISR_PHY_LINKDOWN) != 0); 700 LII_WRITE_4(sc, LII_ISR, 0x3fffffff); 701 LII_WRITE_4(sc, LII_ISR, 0); 702 if (error) { 703 printf("%s: init failed\n", DEVNAME(sc)); 704 goto out; 705 } 706 707 /* 708 * Initialise MAC. 709 */ 710 val = LII_READ_4(sc, LII_MACC) & MACC_FDX; 711 712 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY | 713 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN | 714 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN; 715 716 val |= 7 << MACC_PREAMBLE_LEN_SHIFT; 717 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT; 718 719 LII_WRITE_4(sc, LII_MACC, val); 720 721 /* Set the hardware MAC address. */ 722 LII_WRITE_4(sc, LII_MAC_ADDR_0, letoh32((sc->sc_ac.ac_enaddr[2] << 24) | 723 (sc->sc_ac.ac_enaddr[3] << 16) | (sc->sc_ac.ac_enaddr[4] << 8) | 724 sc->sc_ac.ac_enaddr[5])); 725 LII_WRITE_4(sc, LII_MAC_ADDR_1, 726 letoh32((sc->sc_ac.ac_enaddr[0] << 8) | sc->sc_ac.ac_enaddr[1])); 727 728 /* Program promiscuous mode and multicast filters. */ 729 lii_iff(sc); 730 731 mii_mediachg(&sc->sc_mii); 732 733 LII_WRITE_4(sc, LII_IMR, IMR_NORMAL_MASK); 734 735 timeout_add_sec(&sc->sc_tick, 1); 736 737 ifp->if_flags |= IFF_RUNNING; 738 ifp->if_flags &= ~IFF_OACTIVE; 739 740 out: 741 return error; 742 } 743 744 void 745 lii_tx_put(struct lii_softc *sc, struct mbuf *m) 746 { 747 int left; 748 struct tx_pkt_header *tph = 749 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur); 750 751 memset(tph, 0, sizeof *tph); 752 tph->txph_size = m->m_pkthdr.len; 753 754 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE; 755 756 /* 757 * We already know we have enough space, so if there is a part of the 758 * space ahead of txd_cur that is active, it doesn't matter because 759 * left will be large enough even without it. 760 */ 761 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur; 762 763 if (left > m->m_pkthdr.len) { 764 m_copydata(m, 0, m->m_pkthdr.len, 765 sc->sc_txdbase + sc->sc_txd_cur); 766 sc->sc_txd_cur += m->m_pkthdr.len; 767 } else { 768 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur); 769 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase); 770 sc->sc_txd_cur = m->m_pkthdr.len - left; 771 } 772 773 /* Round to a 32-bit boundary */ 774 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE; 775 if (sc->sc_txd_cur == sc->sc_txd_ack) 776 sc->sc_free_tx_slots = 0; 777 } 778 779 int 780 lii_free_tx_space(struct lii_softc *sc) 781 { 782 int space; 783 784 if (sc->sc_txd_cur >= sc->sc_txd_ack) 785 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) + 786 sc->sc_txd_ack; 787 else 788 space = sc->sc_txd_ack - sc->sc_txd_cur; 789 790 /* Account for the tx_pkt_header */ 791 return (space - 4); 792 } 793 794 void 795 lii_start(struct ifnet *ifp) 796 { 797 struct lii_softc *sc = ifp->if_softc; 798 struct mbuf *m0; 799 800 DPRINTF(("lii_start\n")); 801 802 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 803 return; 804 805 for (;;) { 806 IFQ_POLL(&ifp->if_snd, m0); 807 if (m0 == NULL) 808 break; 809 810 if (!sc->sc_free_tx_slots || 811 lii_free_tx_space(sc) < m0->m_pkthdr.len) { 812 ifp->if_flags |= IFF_OACTIVE; 813 break; 814 } 815 816 lii_tx_put(sc, m0); 817 818 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur)); 819 820 sc->sc_txs[sc->sc_txs_cur].txps_update = 0; 821 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM; 822 if (sc->sc_txs_cur == sc->sc_txs_ack) 823 sc->sc_free_tx_slots = 0; 824 825 LII_WRITE_2(sc, LII_MB_TXD_WR_IDX, sc->sc_txd_cur/4); 826 827 IFQ_DEQUEUE(&ifp->if_snd, m0); 828 829 #if NBPFILTER > 0 830 if (ifp->if_bpf != NULL) 831 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 832 #endif 833 m_freem(m0); 834 } 835 } 836 837 void 838 lii_stop(struct ifnet *ifp) 839 { 840 struct lii_softc *sc = ifp->if_softc; 841 842 timeout_del(&sc->sc_tick); 843 844 ifp->if_timer = 0; 845 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 846 847 mii_down(&sc->sc_mii); 848 849 lii_reset(sc); 850 851 LII_WRITE_4(sc, LII_IMR, 0); 852 } 853 854 int 855 lii_intr(void *v) 856 { 857 struct lii_softc *sc = v; 858 uint32_t status; 859 860 status = LII_READ_4(sc, LII_ISR); 861 if (status == 0) 862 return 0; 863 864 DPRINTF(("lii_intr (%x)\n", status)); 865 866 /* Clear the interrupt and disable them */ 867 LII_WRITE_4(sc, LII_ISR, status | ISR_DIS_INT); 868 869 if (status & (ISR_PHY | ISR_MANUAL)) { 870 /* Ack PHY interrupt. Magic register */ 871 if (status & ISR_PHY) 872 (void)lii_mii_readreg(&sc->sc_dev, 1, 19); 873 mii_mediachg(&sc->sc_mii); 874 } 875 876 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) { 877 lii_init(&sc->sc_ac.ac_if); 878 return 1; 879 } 880 881 if (status & ISR_RX_EVENT) { 882 #ifdef LII_DEBUG 883 if (!(status & ISR_RS_UPDATE)) 884 printf("rxintr %08x\n", status); 885 #endif 886 lii_rxintr(sc); 887 } 888 889 if (status & ISR_TX_EVENT) 890 lii_txintr(sc); 891 892 /* Re-enable interrupts */ 893 LII_WRITE_4(sc, LII_ISR, 0); 894 895 return 1; 896 } 897 898 void 899 lii_rxintr(struct lii_softc *sc) 900 { 901 struct ifnet *ifp = &sc->sc_ac.ac_if; 902 struct rx_pkt *rxp; 903 struct mbuf *m; 904 uint16_t size; 905 906 DPRINTF(("lii_rxintr\n")); 907 908 for (;;) { 909 rxp = &sc->sc_rxp[sc->sc_rxcur]; 910 if (rxp->rxp_update == 0) 911 break; 912 913 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur, 914 rxp->rxp_size, rxp->rxp_flags)); 915 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM; 916 rxp->rxp_update = 0; 917 if (!(rxp->rxp_flags & LII_RXF_SUCCESS)) { 918 ++ifp->if_ierrors; 919 continue; 920 } 921 922 MGETHDR(m, M_DONTWAIT, MT_DATA); 923 if (m == NULL) { 924 ++ifp->if_ierrors; 925 continue; 926 } 927 size = rxp->rxp_size - ETHER_CRC_LEN; 928 if (size > MHLEN) { 929 MCLGET(m, M_DONTWAIT); 930 if ((m->m_flags & M_EXT) == 0) { 931 m_freem(m); 932 ++ifp->if_ierrors; 933 continue; 934 } 935 } 936 937 m->m_pkthdr.rcvif = ifp; 938 /* Copy the packet withhout the FCS */ 939 m->m_pkthdr.len = m->m_len = size; 940 memcpy(mtod(m, void *), &rxp->rxp_data[0], size); 941 ++ifp->if_ipackets; 942 943 #if NBPFILTER > 0 944 if (ifp->if_bpf) 945 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 946 #endif 947 948 ether_input_mbuf(ifp, m); 949 } 950 951 LII_WRITE_4(sc, LII_MB_RXD_RD_IDX, sc->sc_rxcur); 952 } 953 954 void 955 lii_txintr(struct lii_softc *sc) 956 { 957 struct ifnet *ifp = &sc->sc_ac.ac_if; 958 struct tx_pkt_status *txs; 959 struct tx_pkt_header *txph; 960 961 DPRINTF(("lii_txintr\n")); 962 963 for (;;) { 964 txs = &sc->sc_txs[sc->sc_txs_ack]; 965 if (txs->txps_update == 0) 966 break; 967 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack)); 968 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM; 969 sc->sc_free_tx_slots = 1; 970 971 txs->txps_update = 0; 972 973 txph = (struct tx_pkt_header *) 974 (sc->sc_txdbase + sc->sc_txd_ack); 975 976 if (txph->txph_size != txs->txps_size) { 977 printf("%s: mismatched status and packet\n", 978 DEVNAME(sc)); 979 } 980 981 /* 982 * Move ack by the packet size, taking the packet header in 983 * account and round to the next 32-bit boundary 984 * (7 = sizeof(header) + 3) 985 */ 986 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3; 987 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE; 988 989 if (txs->txps_flags & LII_TXF_SUCCESS) 990 ++ifp->if_opackets; 991 else 992 ++ifp->if_oerrors; 993 ifp->if_flags &= ~IFF_OACTIVE; 994 } 995 996 if (sc->sc_free_tx_slots) 997 lii_start(ifp); 998 } 999 1000 int 1001 lii_alloc_rings(struct lii_softc *sc) 1002 { 1003 int nsegs; 1004 bus_size_t bs; 1005 1006 /* 1007 * We need a big chunk of DMA-friendly memory because descriptors 1008 * are not separate from data on that crappy hardware, which means 1009 * we'll have to copy data from and to that memory zone to and from 1010 * the mbufs. 1011 * 1012 * How lame is that? Using the default values from the Linux driver, 1013 * we allocate space for receiving up to 64 full-size Ethernet frames, 1014 * and only 8kb for transmitting up to 64 Ethernet frames. 1015 */ 1016 1017 sc->sc_ringsize = bs = AT_RXD_PADDING 1018 + AT_RXD_NUM * sizeof(struct rx_pkt) 1019 + AT_TXD_NUM * sizeof(struct tx_pkt_status) 1020 + AT_TXD_BUFFER_SIZE; 1021 1022 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30), 1023 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) { 1024 printf(": failed to create DMA map\n"); 1025 return 1; 1026 } 1027 1028 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30), 1029 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) { 1030 printf(": failed to allocate DMA memory\n"); 1031 goto destroy; 1032 } 1033 1034 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs, 1035 (caddr_t *)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) { 1036 printf(": failed to map DMA memory\n"); 1037 goto free; 1038 } 1039 1040 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring, 1041 bs, NULL, BUS_DMA_NOWAIT) != 0) { 1042 printf(": failed to load DMA memory\n"); 1043 goto unmap; 1044 } 1045 1046 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING); 1047 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING 1048 + AT_RXD_NUM * sizeof(struct rx_pkt)); 1049 sc->sc_txdbase = ((char *)sc->sc_txs) 1050 + AT_TXD_NUM * sizeof(struct tx_pkt_status); 1051 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr 1052 + ((char *)sc->sc_txs - (char *)sc->sc_ring); 1053 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr 1054 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring); 1055 1056 return 0; 1057 1058 unmap: 1059 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs); 1060 free: 1061 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs); 1062 destroy: 1063 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap); 1064 return 1; 1065 } 1066 1067 void 1068 lii_watchdog(struct ifnet *ifp) 1069 { 1070 struct lii_softc *sc = ifp->if_softc; 1071 1072 printf("%s: watchdog timeout\n", DEVNAME(sc)); 1073 ++ifp->if_oerrors; 1074 lii_init(ifp); 1075 } 1076 1077 int 1078 lii_ioctl(struct ifnet *ifp, u_long cmd, caddr_t addr) 1079 { 1080 struct lii_softc *sc = ifp->if_softc; 1081 struct ifaddr *ifa = (struct ifaddr *)addr; 1082 struct ifreq *ifr = (struct ifreq *)addr; 1083 int s, error = 0; 1084 1085 s = splnet(); 1086 1087 switch(cmd) { 1088 case SIOCSIFADDR: 1089 SET(ifp->if_flags, IFF_UP); 1090 #ifdef INET 1091 if (ifa->ifa_addr->sa_family == AF_INET) 1092 arp_ifinit(&sc->sc_ac, ifa); 1093 #endif 1094 /* FALLTHROUGH */ 1095 1096 case SIOCSIFFLAGS: 1097 if (ISSET(ifp->if_flags, IFF_UP)) { 1098 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1099 error = ENETRESET; 1100 else 1101 lii_init(ifp); 1102 } else { 1103 if (ISSET(ifp->if_flags, IFF_RUNNING)) 1104 lii_stop(ifp); 1105 } 1106 break; 1107 1108 case SIOCSIFMEDIA: 1109 case SIOCGIFMEDIA: 1110 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1111 break; 1112 1113 default: 1114 error = ether_ioctl(ifp, &sc->sc_ac, cmd, addr); 1115 } 1116 1117 if (error == ENETRESET) { 1118 if (ifp->if_flags & IFF_RUNNING) 1119 lii_iff(sc); 1120 error = 0; 1121 } 1122 1123 splx(s); 1124 return error; 1125 } 1126 1127 void 1128 lii_iff(struct lii_softc *sc) 1129 { 1130 struct ifnet *ifp = &sc->sc_ac.ac_if; 1131 struct arpcom *ac = &sc->sc_ac; 1132 struct ether_multi *enm; 1133 struct ether_multistep step; 1134 uint32_t hashes[2]; 1135 uint32_t crc, val; 1136 1137 val = LII_READ_4(sc, LII_MACC); 1138 val &= ~(MACC_ALLMULTI_EN | MACC_PROMISC_EN); 1139 ifp->if_flags &= ~IFF_ALLMULTI; 1140 1141 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 1142 ifp->if_flags |= IFF_ALLMULTI; 1143 if (ifp->if_flags & IFF_PROMISC) 1144 val |= MACC_PROMISC_EN; 1145 else 1146 val |= MACC_ALLMULTI_EN; 1147 hashes[0] = hashes[1] = 0xFFFFFFFF; 1148 } else { 1149 /* Program new filter. */ 1150 bzero(hashes, sizeof(hashes)); 1151 1152 ETHER_FIRST_MULTI(step, ac, enm); 1153 while (enm != NULL) { 1154 crc = ether_crc32_be(enm->enm_addrlo, 1155 ETHER_ADDR_LEN); 1156 1157 hashes[((crc >> 31) & 0x1)] |= 1158 (1 << ((crc >> 26) & 0x1f)); 1159 1160 ETHER_NEXT_MULTI(step, enm); 1161 } 1162 } 1163 1164 LII_WRITE_4(sc, LII_MHT, hashes[0]); 1165 LII_WRITE_4(sc, LII_MHT + 4, hashes[1]); 1166 LII_WRITE_4(sc, LII_MACC, val); 1167 } 1168 1169 void 1170 lii_tick(void *v) 1171 { 1172 struct lii_softc *sc = v; 1173 int s; 1174 1175 s = splnet(); 1176 mii_tick(&sc->sc_mii); 1177 splx(s); 1178 1179 timeout_add_sec(&sc->sc_tick, 1); 1180 } 1181